drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44
  45 /**
  46  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  47  *  @hw: pointer to hardware structure
  48  *
  49  *  Initialize the function pointers and assign the MAC type for X550.
  50  *  Does not touch the hardware.
  51  **/
  52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  53 {
  54         struct ixgbe_mac_info *mac = &hw->mac;
  55         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  56         s32 ret_val;
  57
  58         DEBUGFUNC("ixgbe_init_ops_X550");
  59
  60         ret_val = ixgbe_init_ops_X540(hw);
  61         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  62         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  63         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  64         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  65         mac->ops.set_source_address_pruning =
  66                         ixgbe_set_source_address_pruning_X550;
  67         mac->ops.set_ethertype_anti_spoofing =
  68                         ixgbe_set_ethertype_anti_spoofing_X550;
  69
  70         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  71         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  72         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  73         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  74         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  75         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  76         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  77         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  78         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  79
  80         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  81         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  82         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  83         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  84         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  85         switch (hw->device_id) {
  86         case IXGBE_DEV_ID_X550EM_X_10G_T:
  87         case IXGBE_DEV_ID_X550EM_A_10G_T:
  88                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  89                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  90                 break;
  91         default:
  92                 break;
  93         }
  94         return ret_val;
  95 }
  96
  97 /**
  98  * ixgbe_read_cs4227 - Read CS4227 register
  99  * @hw: pointer to hardware structure
 100  * @reg: register number to write
 101  * @value: pointer to receive value read
 102  *
 103  * Returns status code
 104  **/
 105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 106 {
 107         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 108 }
 109
 110 /**
 111  * ixgbe_write_cs4227 - Write CS4227 register
 112  * @hw: pointer to hardware structure
 113  * @reg: register number to write
 114  * @value: value to write to register
 115  *
 116  * Returns status code
 117  **/
 118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 119 {
 120         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 121 }
 122
 123 /**
 124  * ixgbe_read_pe - Read register from port expander
 125  * @hw: pointer to hardware structure
 126  * @reg: register number to read
 127  * @value: pointer to receive read value
 128  *
 129  * Returns status code
 130  **/
 131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 132 {
 133         s32 status;
 134
 135         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 136         if (status != IXGBE_SUCCESS)
 137                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 138                               "port expander access failed with %d\n", status);
 139         return status;
 140 }
 141
 142 /**
 143  * ixgbe_write_pe - Write register to port expander
 144  * @hw: pointer to hardware structure
 145  * @reg: register number to write
 146  * @value: value to write
 147  *
 148  * Returns status code
 149  **/
 150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 151 {
 152         s32 status;
 153
 154         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 155         if (status != IXGBE_SUCCESS)
 156                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 157                               "port expander access failed with %d\n", status);
 158         return status;
 159 }
 160
 161 /**
 162  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 163  * @hw: pointer to hardware structure
 164  *
 165  * This function assumes that the caller has acquired the proper semaphore.
 166  * Returns error code
 167  **/
 168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 169 {
 170         s32 status;
 171         u32 retry;
 172         u16 value;
 173         u8 reg;
 174
 175         /* Trigger hard reset. */
 176         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 177         if (status != IXGBE_SUCCESS)
 178                 return status;
 179         reg |= IXGBE_PE_BIT1;
 180         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 181         if (status != IXGBE_SUCCESS)
 182                 return status;
 183
 184         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 185         if (status != IXGBE_SUCCESS)
 186                 return status;
 187         reg &= ~IXGBE_PE_BIT1;
 188         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 189         if (status != IXGBE_SUCCESS)
 190                 return status;
 191
 192         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 193         if (status != IXGBE_SUCCESS)
 194                 return status;
 195         reg &= ~IXGBE_PE_BIT1;
 196         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199
 200         usec_delay(IXGBE_CS4227_RESET_HOLD);
 201
 202         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 203         if (status != IXGBE_SUCCESS)
 204                 return status;
 205         reg |= IXGBE_PE_BIT1;
 206         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 207         if (status != IXGBE_SUCCESS)
 208                 return status;
 209
 210         /* Wait for the reset to complete. */
 211         msec_delay(IXGBE_CS4227_RESET_DELAY);
 212         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 213                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 214                                            &value);
 215                 if (status == IXGBE_SUCCESS &&
 216                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 217                         break;
 218                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 219         }
 220         if (retry == IXGBE_CS4227_RETRIES) {
 221                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 222                         "CS4227 reset did not complete.");
 223                 return IXGBE_ERR_PHY;
 224         }
 225
 226         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 227         if (status != IXGBE_SUCCESS ||
 228             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 229                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 230                         "CS4227 EEPROM did not load successfully.");
 231                 return IXGBE_ERR_PHY;
 232         }
 233
 234         return IXGBE_SUCCESS;
 235 }
 236
 237 /**
 238  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 239  * @hw: pointer to hardware structure
 240  **/
 241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 242 {
 243         s32 status = IXGBE_SUCCESS;
 244         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 245         u16 value = 0;
 246         u8 retry;
 247
 248         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 249                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 250                 if (status != IXGBE_SUCCESS) {
 251                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 252                                 "semaphore failed with %d", status);
 253                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 254                         continue;
 255                 }
 256
 257                 /* Get status of reset flow. */
 258                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 259
 260                 if (status == IXGBE_SUCCESS &&
 261                     value == IXGBE_CS4227_RESET_COMPLETE)
 262                         goto out;
 263
 264                 if (status != IXGBE_SUCCESS ||
 265                     value != IXGBE_CS4227_RESET_PENDING)
 266                         break;
 267
 268                 /* Reset is pending. Wait and check again. */
 269                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 270                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 271         }
 272
 273         /* If still pending, assume other instance failed. */
 274         if (retry == IXGBE_CS4227_RETRIES) {
 275                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 276                 if (status != IXGBE_SUCCESS) {
 277                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 278                                       "semaphore failed with %d", status);
 279                         return;
 280                 }
 281         }
 282
 283         /* Reset the CS4227. */
 284         status = ixgbe_reset_cs4227(hw);
 285         if (status != IXGBE_SUCCESS) {
 286                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 287                         "CS4227 reset failed: %d", status);
 288                 goto out;
 289         }
 290
 291         /* Reset takes so long, temporarily release semaphore in case the
 292          * other driver instance is waiting for the reset indication.
 293          */
 294         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 295                            IXGBE_CS4227_RESET_PENDING);
 296         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 297         msec_delay(10);
 298         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 299         if (status != IXGBE_SUCCESS) {
 300                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 301                         "semaphore failed with %d", status);
 302                 return;
 303         }
 304
 305         /* Record completion for next time. */
 306         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 307                 IXGBE_CS4227_RESET_COMPLETE);
 308
 309 out:
 310         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 311         msec_delay(hw->eeprom.semaphore_delay);
 312 }
 313
 314 /**
 315  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 316  * @hw: pointer to hardware structure
 317  **/
 318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 319 {
 320         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 321
 322         if (hw->bus.lan_id) {
 323                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 324                 esdp |= IXGBE_ESDP_SDP1_DIR;
 325         }
 326         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 327         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 328         IXGBE_WRITE_FLUSH(hw);
 329 }
 330
 331 /**
 332  * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
 333  * @hw: pointer to hardware structure
 334  * @reg_addr: 32 bit address of PHY register to read
 335  * @dev_type: always unused
 336  * @phy_data: Pointer to read data from PHY register
 337  */
 338 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 339                                      u32 dev_type, u16 *phy_data)
 340 {
 341         u32 i, data, command;
 342         UNREFERENCED_1PARAMETER(dev_type);
 343
 344         /* Setup and write the read command */
 345         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 346                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 347                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
 348                   IXGBE_MSCA_MDI_COMMAND;
 349
 350         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 351
 352         /* Check every 10 usec to see if the access completed.
 353          * The MDI Command bit will clear when the operation is
 354          * complete
 355          */
 356         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 357                 usec_delay(10);
 358
 359                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 360                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 361                         break;
 362         }
 363
 364         if (command & IXGBE_MSCA_MDI_COMMAND) {
 365                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 366                               "PHY read command did not complete.\n");
 367                 return IXGBE_ERR_PHY;
 368         }
 369
 370         /* Read operation is complete.  Get the data from MSRWD */
 371         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 372         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 373         *phy_data = (u16)data;
 374
 375         return IXGBE_SUCCESS;
 376 }
 377
 378 /**
 379  * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
 380  * @hw: pointer to hardware structure
 381  * @reg_addr: 32 bit PHY register to write
 382  * @dev_type: always unused
 383  * @phy_data: Data to write to the PHY register
 384  */
 385 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 386                                       u32 dev_type, u16 phy_data)
 387 {
 388         u32 i, command;
 389         UNREFERENCED_1PARAMETER(dev_type);
 390
 391         /* Put the data in the MDI single read and write data register*/
 392         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 393
 394         /* Setup and write the write command */
 395         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 396                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 397                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
 398                   IXGBE_MSCA_MDI_COMMAND;
 399
 400         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 401
 402         /* Check every 10 usec to see if the access completed.
 403          * The MDI Command bit will clear when the operation is
 404          * complete
 405          */
 406         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 407                 usec_delay(10);
 408
 409                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 410                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 411                         break;
 412         }
 413
 414         if (command & IXGBE_MSCA_MDI_COMMAND) {
 415                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 416                               "PHY write cmd didn't complete\n");
 417                 return IXGBE_ERR_PHY;
 418         }
 419
 420         return IXGBE_SUCCESS;
 421 }
 422
 423 /**
 424  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 425  * @hw: pointer to hardware structure
 426  *
 427  * Returns error code
 428  */
 429 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 430 {
 431         switch (hw->device_id) {
 432         case IXGBE_DEV_ID_X550EM_A_SFP:
 433                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
 434                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
 435                 if (hw->bus.lan_id)
 436                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 437                 else
 438                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 439                 return ixgbe_identify_module_generic(hw);
 440         case IXGBE_DEV_ID_X550EM_X_SFP:
 441                 /* set up for CS4227 usage */
 442                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 443                 ixgbe_setup_mux_ctl(hw);
 444                 ixgbe_check_cs4227(hw);
 445                 /* Fallthrough */
 446
 447         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 448                 return ixgbe_identify_module_generic(hw);
 449                 break;
 450         case IXGBE_DEV_ID_X550EM_X_KX4:
 451                 hw->phy.type = ixgbe_phy_x550em_kx4;
 452                 break;
 453         case IXGBE_DEV_ID_X550EM_X_KR:
 454         case IXGBE_DEV_ID_X550EM_A_KR:
 455         case IXGBE_DEV_ID_X550EM_A_KR_L:
 456                 hw->phy.type = ixgbe_phy_x550em_kr;
 457                 break;
 458         case IXGBE_DEV_ID_X550EM_A_10G_T:
 459                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
 460                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
 461        /* Fallthrough to ixgbe_identify_phy_generic */
 462         case IXGBE_DEV_ID_X550EM_A_1G_T:
 463         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 464         case IXGBE_DEV_ID_X550EM_X_1G_T:
 465         case IXGBE_DEV_ID_X550EM_X_10G_T:
 466                 return ixgbe_identify_phy_generic(hw);
 467         default:
 468                 break;
 469         }
 470         return IXGBE_SUCCESS;
 471 }
 472
 473 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 474                                      u32 device_type, u16 *phy_data)
 475 {
 476         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 477         return IXGBE_NOT_IMPLEMENTED;
 478 }
 479
 480 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 481                                       u32 device_type, u16 phy_data)
 482 {
 483         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 484         return IXGBE_NOT_IMPLEMENTED;
 485 }
 486
 487 /**
 488  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 489  * @hw: pointer to the hardware structure
 490  * @addr: I2C bus address to read from
 491  * @reg: I2C device register to read from
 492  * @val: pointer to location to receive read value
 493  *
 494  * Returns an error code on error.
 495  **/
 496 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 497                                            u16 reg, u16 *val)
 498 {
 499         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 500 }
 501
 502 /**
 503  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 504  * @hw: pointer to the hardware structure
 505  * @addr: I2C bus address to read from
 506  * @reg: I2C device register to read from
 507  * @val: pointer to location to receive read value
 508  *
 509  * Returns an error code on error.
 510  **/
 511 STATIC s32
 512 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 513                                          u16 reg, u16 *val)
 514 {
 515         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 516 }
 517
 518 /**
 519  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 520  * @hw: pointer to the hardware structure
 521  * @addr: I2C bus address to write to
 522  * @reg: I2C device register to write to
 523  * @val: value to write
 524  *
 525  * Returns an error code on error.
 526  **/
 527 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 528                                             u8 addr, u16 reg, u16 val)
 529 {
 530         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 531 }
 532
 533 /**
 534  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 535  * @hw: pointer to the hardware structure
 536  * @addr: I2C bus address to write to
 537  * @reg: I2C device register to write to
 538  * @val: value to write
 539  *
 540  * Returns an error code on error.
 541  **/
 542 STATIC s32
 543 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 544                                           u8 addr, u16 reg, u16 val)
 545 {
 546         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 547 }
 548
 549 /**
 550 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 551 *  @hw: pointer to hardware structure
 552 *
 553 *  Initialize the function pointers and for MAC type X550EM.
 554 *  Does not touch the hardware.
 555 **/
 556 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 557 {
 558         struct ixgbe_mac_info *mac = &hw->mac;
 559         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 560         struct ixgbe_phy_info *phy = &hw->phy;
 561         s32 ret_val;
 562
 563         DEBUGFUNC("ixgbe_init_ops_X550EM");
 564
 565         /* Similar to X550 so start there. */
 566         ret_val = ixgbe_init_ops_X550(hw);
 567
 568         /* Since this function eventually calls
 569          * ixgbe_init_ops_540 by design, we are setting
 570          * the pointers to NULL explicitly here to overwrite
 571          * the values being set in the x540 function.
 572          */
 573         /* Thermal sensor not supported in x550EM */
 574         mac->ops.get_thermal_sensor_data = NULL;
 575         mac->ops.init_thermal_sensor_thresh = NULL;
 576         mac->thermal_sensor_enabled = false;
 577
 578         /* FCOE not supported in x550EM */
 579         mac->ops.get_san_mac_addr = NULL;
 580         mac->ops.set_san_mac_addr = NULL;
 581         mac->ops.get_wwn_prefix = NULL;
 582         mac->ops.get_fcoe_boot_status = NULL;
 583
 584         /* IPsec not supported in x550EM */
 585         mac->ops.disable_sec_rx_path = NULL;
 586         mac->ops.enable_sec_rx_path = NULL;
 587
 588         /* AUTOC register is not present in x550EM. */
 589         mac->ops.prot_autoc_read = NULL;
 590         mac->ops.prot_autoc_write = NULL;
 591
 592         /* X550EM bus type is internal*/
 593         hw->bus.type = ixgbe_bus_type_internal;
 594         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 595
 596
 597         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 598         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 599         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 600         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 601         mac->ops.get_supported_physical_layer =
 602                                     ixgbe_get_supported_physical_layer_X550em;
 603
 604         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 605                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 606         else
 607                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 608
 609         switch (hw->device_id) {
 610         case IXGBE_DEV_ID_X550EM_X_KR:
 611         case IXGBE_DEV_ID_X550EM_A_KR:
 612         case IXGBE_DEV_ID_X550EM_A_KR_L:
 613                 break;
 614         default:
 615                 mac->ops.setup_eee = NULL;
 616         }
 617
 618         /* PHY */
 619         phy->ops.init = ixgbe_init_phy_ops_X550em;
 620         phy->ops.identify = ixgbe_identify_phy_x550em;
 621         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 622                 phy->ops.set_phy_power = NULL;
 623
 624
 625         /* EEPROM */
 626         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 627         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 628         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 629         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 630         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 631         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 632         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 633         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 634
 635         return ret_val;
 636 }
 637
 638 /**
 639 *  ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
 640 *  @hw: pointer to hardware structure
 641 *
 642 *  Initialize the function pointers and for MAC type X550EM_a.
 643 *  Does not touch the hardware.
 644 **/
 645 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
 646 {
 647         struct ixgbe_mac_info *mac = &hw->mac;
 648         s32 ret_val;
 649
 650         DEBUGFUNC("ixgbe_init_ops_X550EM_a");
 651
 652         /* Start with generic X550EM init */
 653         ret_val = ixgbe_init_ops_X550EM(hw);
 654
 655         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
 656             hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
 657                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 658                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 659         } else {
 660                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 661                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 662         }
 663         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 664         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 665
 666         switch (mac->ops.get_media_type(hw)) {
 667         case ixgbe_media_type_fiber:
 668                 mac->ops.setup_fc = ixgbe_setup_fc_fiber_x550em_a;
 669                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
 670                 break;
 671         case ixgbe_media_type_backplane:
 672                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
 673                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
 674                 break;
 675         default:
 676                 break;
 677         }
 678
 679         return ret_val;
 680 }
 681
 682 /**
 683 *  ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
 684 *  @hw: pointer to hardware structure
 685 *
 686 *  Initialize the function pointers and for MAC type X550EM_x.
 687 *  Does not touch the hardware.
 688 **/
 689 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
 690 {
 691         struct ixgbe_mac_info *mac = &hw->mac;
 692         struct ixgbe_link_info *link = &hw->link;
 693         s32 ret_val;
 694
 695         DEBUGFUNC("ixgbe_init_ops_X550EM_x");
 696
 697         /* Start with generic X550EM init */
 698         ret_val = ixgbe_init_ops_X550EM(hw);
 699
 700         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 701         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 702         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 703         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 704         link->ops.read_link = ixgbe_read_i2c_combined_generic;
 705         link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
 706         link->ops.write_link = ixgbe_write_i2c_combined_generic;
 707         link->ops.write_link_unlocked =
 708                                       ixgbe_write_i2c_combined_generic_unlocked;
 709         link->addr = IXGBE_CS4227;
 710
 711         return ret_val;
 712 }
 713
 714 /**
 715  *  ixgbe_dmac_config_X550
 716  *  @hw: pointer to hardware structure
 717  *
 718  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 719  *  When disabling dmac, dmac enable dmac bit is cleared.
 720  **/
 721 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 722 {
 723         u32 reg, high_pri_tc;
 724
 725         DEBUGFUNC("ixgbe_dmac_config_X550");
 726
 727         /* Disable DMA coalescing before configuring */
 728         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 729         reg &= ~IXGBE_DMACR_DMAC_EN;
 730         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 731
 732         /* Disable DMA Coalescing if the watchdog timer is 0 */
 733         if (!hw->mac.dmac_config.watchdog_timer)
 734                 goto out;
 735
 736         ixgbe_dmac_config_tcs_X550(hw);
 737
 738         /* Configure DMA Coalescing Control Register */
 739         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 740
 741         /* Set the watchdog timer in units of 40.96 usec */
 742         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 743         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 744
 745         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 746         /* If fcoe is enabled, set high priority traffic class */
 747         if (hw->mac.dmac_config.fcoe_en) {
 748                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 749                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 750                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 751         }
 752         reg |= IXGBE_DMACR_EN_MNG_IND;
 753
 754         /* Enable DMA coalescing after configuration */
 755         reg |= IXGBE_DMACR_DMAC_EN;
 756         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 757
 758 out:
 759         return IXGBE_SUCCESS;
 760 }
 761
 762 /**
 763  *  ixgbe_dmac_config_tcs_X550
 764  *  @hw: pointer to hardware structure
 765  *
 766  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 767  *  be cleared before configuring.
 768  **/
 769 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 770 {
 771         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 772
 773         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 774
 775         /* Configure DMA coalescing enabled */
 776         switch (hw->mac.dmac_config.link_speed) {
 777         case IXGBE_LINK_SPEED_10_FULL:
 778         case IXGBE_LINK_SPEED_100_FULL:
 779                 pb_headroom = IXGBE_DMACRXT_100M;
 780                 break;
 781         case IXGBE_LINK_SPEED_1GB_FULL:
 782                 pb_headroom = IXGBE_DMACRXT_1G;
 783                 break;
 784         default:
 785                 pb_headroom = IXGBE_DMACRXT_10G;
 786                 break;
 787         }
 788
 789         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 790                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 791
 792         /* Set the per Rx packet buffer receive threshold */
 793         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 794                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 795                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 796
 797                 if (tc < hw->mac.dmac_config.num_tcs) {
 798                         /* Get Rx PB size */
 799                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 800                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 801                                 IXGBE_RXPBSIZE_SHIFT;
 802
 803                         /* Calculate receive buffer threshold in kilobytes */
 804                         if (rx_pb_size > pb_headroom)
 805                                 rx_pb_size = rx_pb_size - pb_headroom;
 806                         else
 807                                 rx_pb_size = 0;
 808
 809                         /* Minimum of MFS shall be set for DMCTH */
 810                         reg |= (rx_pb_size > maxframe_size_kb) ?
 811                                 rx_pb_size : maxframe_size_kb;
 812                 }
 813                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 814         }
 815         return IXGBE_SUCCESS;
 816 }
 817
 818 /**
 819  *  ixgbe_dmac_update_tcs_X550
 820  *  @hw: pointer to hardware structure
 821  *
 822  *  Disables dmac, updates per TC settings, and then enables dmac.
 823  **/
 824 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 825 {
 826         u32 reg;
 827
 828         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 829
 830         /* Disable DMA coalescing before configuring */
 831         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 832         reg &= ~IXGBE_DMACR_DMAC_EN;
 833         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 834
 835         ixgbe_dmac_config_tcs_X550(hw);
 836
 837         /* Enable DMA coalescing after configuration */
 838         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 839         reg |= IXGBE_DMACR_DMAC_EN;
 840         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 841
 842         return IXGBE_SUCCESS;
 843 }
 844
 845 /**
 846  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 847  *  @hw: pointer to hardware structure
 848  *
 849  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 850  *  ixgbe_hw struct in order to set up EEPROM access.
 851  **/
 852 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 853 {
 854         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 855         u32 eec;
 856         u16 eeprom_size;
 857
 858         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 859
 860         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 861                 eeprom->semaphore_delay = 10;
 862                 eeprom->type = ixgbe_flash;
 863
 864                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 865                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 866                                     IXGBE_EEC_SIZE_SHIFT);
 867                 eeprom->word_size = 1 << (eeprom_size +
 868                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 869
 870                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 871                           eeprom->type, eeprom->word_size);
 872         }
 873
 874         return IXGBE_SUCCESS;
 875 }
 876
 877 /**
 878  * ixgbe_enable_eee_x550 - Enable EEE support
 879  * @hw: pointer to hardware structure
 880  */
 881 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
 882 {
 883         u16 autoneg_eee_reg;
 884         u32 link_reg;
 885         s32 status;
 886
 887         if (hw->mac.type == ixgbe_mac_X550) {
 888                 /* Advertise EEE capability */
 889                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 890                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 891                                      &autoneg_eee_reg);
 892
 893                 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 894                                     IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 895                                     IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 896
 897                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 898                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 899                                       autoneg_eee_reg);
 900                 return IXGBE_SUCCESS;
 901         }
 902
 903         switch (hw->device_id) {
 904         case IXGBE_DEV_ID_X550EM_X_KR:
 905         case IXGBE_DEV_ID_X550EM_A_KR:
 906         case IXGBE_DEV_ID_X550EM_A_KR_L:
 907                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 908                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 909                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 910                 if (status != IXGBE_SUCCESS)
 911                         return status;
 912
 913                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 914                         IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 915
 916                 /* Don't advertise FEC capability when EEE enabled. */
 917                 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 918
 919                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 920                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 921                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 922                 if (status != IXGBE_SUCCESS)
 923                         return status;
 924                 break;
 925         default:
 926                 break;
 927         }
 928
 929         return IXGBE_SUCCESS;
 930 }
 931
 932 /**
 933  * ixgbe_disable_eee_x550 - Disable EEE support
 934  * @hw: pointer to hardware structure
 935  */
 936 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
 937 {
 938         u16 autoneg_eee_reg;
 939         u32 link_reg;
 940         s32 status;
 941
 942         if (hw->mac.type == ixgbe_mac_X550) {
 943                 /* Disable advertised EEE capability */
 944                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 945                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 946                                      &autoneg_eee_reg);
 947
 948                 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 949                                      IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 950                                      IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 951
 952                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 953                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 954                                       autoneg_eee_reg);
 955                 return IXGBE_SUCCESS;
 956         }
 957
 958         switch (hw->device_id) {
 959         case IXGBE_DEV_ID_X550EM_X_KR:
 960         case IXGBE_DEV_ID_X550EM_A_KR:
 961         case IXGBE_DEV_ID_X550EM_A_KR_L:
 962                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 963                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 964                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 965                 if (status != IXGBE_SUCCESS)
 966                         return status;
 967
 968                 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 969                               IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 970
 971                 /* Advertise FEC capability when EEE is disabled. */
 972                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 973
 974                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 975                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 976                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 977                 if (status != IXGBE_SUCCESS)
 978                         return status;
 979                 break;
 980         default:
 981                 break;
 982         }
 983
 984         return IXGBE_SUCCESS;
 985 }
 986
 987 /**
 988  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 989  *  @hw: pointer to the HW structure
 990  *  @enable_eee: boolean flag to enable EEE
 991  *
 992  *  Enable/disable EEE based on enable_eee flag.
 993  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 994  *  are modified.
 995  *
 996  **/
 997 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 998 {
 999         s32 status;
1000         u32 eeer;
1001
1002         DEBUGFUNC("ixgbe_setup_eee_X550");
1003
1004         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
1005         /* Enable or disable EEE per flag */
1006         if (enable_eee) {
1007                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1008
1009                 /* Not supported on first revision of X550EM_x. */
1010                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1011                     !(IXGBE_FUSES0_REV_MASK &
1012                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1013                         return IXGBE_SUCCESS;
1014                 status = ixgbe_enable_eee_x550(hw);
1015                 if (status)
1016                         return status;
1017         } else {
1018                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1019
1020                 status = ixgbe_disable_eee_x550(hw);
1021                 if (status)
1022                         return status;
1023         }
1024         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1025
1026         return IXGBE_SUCCESS;
1027 }
1028
1029 /**
1030  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1031  * @hw: pointer to hardware structure
1032  * @enable: enable or disable source address pruning
1033  * @pool: Rx pool to set source address pruning for
1034  **/
1035 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1036                                            unsigned int pool)
1037 {
1038         u64 pfflp;
1039
1040         /* max rx pool is 63 */
1041         if (pool > 63)
1042                 return;
1043
1044         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1045         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1046
1047         if (enable)
1048                 pfflp |= (1ULL << pool);
1049         else
1050                 pfflp &= ~(1ULL << pool);
1051
1052         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1053         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1054 }
1055
1056 /**
1057  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1058  *  @hw: pointer to hardware structure
1059  *  @enable: enable or disable switch for Ethertype anti-spoofing
1060  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1061  *
1062  **/
1063 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1064                 bool enable, int vf)
1065 {
1066         int vf_target_reg = vf >> 3;
1067         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1068         u32 pfvfspoof;
1069
1070         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1071
1072         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1073         if (enable)
1074                 pfvfspoof |= (1 << vf_target_shift);
1075         else
1076                 pfvfspoof &= ~(1 << vf_target_shift);
1077
1078         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1079 }
1080
1081 /**
1082  * ixgbe_iosf_wait - Wait for IOSF command completion
1083  * @hw: pointer to hardware structure
1084  * @ctrl: pointer to location to receive final IOSF control value
1085  *
1086  * Returns failing status on timeout
1087  *
1088  * Note: ctrl can be NULL if the IOSF control register value is not needed
1089  **/
1090 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1091 {
1092         u32 i, command = 0;
1093
1094         /* Check every 10 usec to see if the address cycle completed.
1095          * The SB IOSF BUSY bit will clear when the operation is
1096          * complete
1097          */
1098         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1099                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1100                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1101                         break;
1102                 usec_delay(10);
1103         }
1104         if (ctrl)
1105                 *ctrl = command;
1106         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1107                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1108                 return IXGBE_ERR_PHY;
1109         }
1110
1111         return IXGBE_SUCCESS;
1112 }
1113
1114 /**
1115  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1116  *  of the IOSF device
1117  *  @hw: pointer to hardware structure
1118  *  @reg_addr: 32 bit PHY register to write
1119  *  @device_type: 3 bit device type
1120  *  @data: Data to write to the register
1121  **/
1122 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1123                             u32 device_type, u32 data)
1124 {
1125         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1126         u32 command, error;
1127         s32 ret;
1128
1129         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1130         if (ret != IXGBE_SUCCESS)
1131                 return ret;
1132
1133         ret = ixgbe_iosf_wait(hw, NULL);
1134         if (ret != IXGBE_SUCCESS)
1135                 goto out;
1136
1137         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1138                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1139
1140         /* Write IOSF control register */
1141         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1142
1143         /* Write IOSF data register */
1144         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1145
1146         ret = ixgbe_iosf_wait(hw, &command);
1147
1148         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1149                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1150                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1151                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1152                               "Failed to write, error %x\n", error);
1153                 ret = IXGBE_ERR_PHY;
1154         }
1155
1156 out:
1157         ixgbe_release_swfw_semaphore(hw, gssr);
1158         return ret;
1159 }
1160
1161 /**
1162  *  ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1163  *  @hw: pointer to hardware structure
1164  *  @reg_addr: 32 bit PHY register to write
1165  *  @device_type: 3 bit device type
1166  *  @data: Pointer to read data from the register
1167  **/
1168 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1169                            u32 device_type, u32 *data)
1170 {
1171         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1172         u32 command, error;
1173         s32 ret;
1174
1175         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1176         if (ret != IXGBE_SUCCESS)
1177                 return ret;
1178
1179         ret = ixgbe_iosf_wait(hw, NULL);
1180         if (ret != IXGBE_SUCCESS)
1181                 goto out;
1182
1183         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1184                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1185
1186         /* Write IOSF control register */
1187         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1188
1189         ret = ixgbe_iosf_wait(hw, &command);
1190
1191         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1192                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1193                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1194                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1195                                 "Failed to read, error %x\n", error);
1196                 ret = IXGBE_ERR_PHY;
1197         }
1198
1199         if (ret == IXGBE_SUCCESS)
1200                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1201
1202 out:
1203         ixgbe_release_swfw_semaphore(hw, gssr);
1204         return ret;
1205 }
1206
1207 /**
1208  * ixgbe_get_phy_token - Get the token for shared phy access
1209  * @hw: Pointer to hardware structure
1210  */
1211
1212 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1213 {
1214         struct ixgbe_hic_phy_token_req token_cmd;
1215         s32 status;
1216
1217         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1218         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1219         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1220         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1221         token_cmd.port_number = hw->bus.lan_id;
1222         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1223         token_cmd.pad = 0;
1224         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1225                                               sizeof(token_cmd),
1226                                               IXGBE_HI_COMMAND_TIMEOUT,
1227                                               true);
1228         if (status)
1229                 return status;
1230         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1231                 return IXGBE_SUCCESS;
1232         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1233                 return IXGBE_ERR_FW_RESP_INVALID;
1234
1235         return IXGBE_ERR_TOKEN_RETRY;
1236 }
1237
1238 /**
1239  * ixgbe_put_phy_token - Put the token for shared phy access
1240  * @hw: Pointer to hardware structure
1241  */
1242
1243 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1244 {
1245         struct ixgbe_hic_phy_token_req token_cmd;
1246         s32 status;
1247
1248         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1249         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1250         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1251         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1252         token_cmd.port_number = hw->bus.lan_id;
1253         token_cmd.command_type = FW_PHY_TOKEN_REL;
1254         token_cmd.pad = 0;
1255         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1256                                               sizeof(token_cmd),
1257                                               IXGBE_HI_COMMAND_TIMEOUT,
1258                                               true);
1259         if (status)
1260                 return status;
1261         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1262                 return IXGBE_SUCCESS;
1263
1264         DEBUGOUT("Put PHY Token host interface command failed");
1265         return IXGBE_ERR_FW_RESP_INVALID;
1266 }
1267
1268 /**
1269  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1270  *  of the IOSF device
1271  *  @hw: pointer to hardware structure
1272  *  @reg_addr: 32 bit PHY register to write
1273  *  @device_type: 3 bit device type
1274  *  @data: Data to write to the register
1275  **/
1276 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1277                                   u32 device_type, u32 data)
1278 {
1279         struct ixgbe_hic_internal_phy_req write_cmd;
1280         s32 status;
1281         UNREFERENCED_1PARAMETER(device_type);
1282
1283         memset(&write_cmd, 0, sizeof(write_cmd));
1284         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1285         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1286         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1287         write_cmd.port_number = hw->bus.lan_id;
1288         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1289         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1290         write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1291
1292         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1293                                               sizeof(write_cmd),
1294                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1295
1296         return status;
1297 }
1298
1299 /**
1300  *  ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1301  *  @hw: pointer to hardware structure
1302  *  @reg_addr: 32 bit PHY register to write
1303  *  @device_type: 3 bit device type
1304  *  @data: Pointer to read data from the register
1305  **/
1306 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1307                                  u32 device_type, u32 *data)
1308 {
1309         union {
1310                 struct ixgbe_hic_internal_phy_req cmd;
1311                 struct ixgbe_hic_internal_phy_resp rsp;
1312         } hic;
1313         s32 status;
1314         UNREFERENCED_1PARAMETER(device_type);
1315
1316         memset(&hic, 0, sizeof(hic));
1317         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1318         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1319         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1320         hic.cmd.port_number = hw->bus.lan_id;
1321         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1322         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1323
1324         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1325                                               sizeof(hic.cmd),
1326                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1327
1328         /* Extract the register value from the response. */
1329         *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1330
1331         return status;
1332 }
1333
1334 /**
1335  *  ixgbe_disable_mdd_X550
1336  *  @hw: pointer to hardware structure
1337  *
1338  *  Disable malicious driver detection
1339  **/
1340 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1341 {
1342         u32 reg;
1343
1344         DEBUGFUNC("ixgbe_disable_mdd_X550");
1345
1346         /* Disable MDD for TX DMA and interrupt */
1347         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1348         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1349         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1350
1351         /* Disable MDD for RX and interrupt */
1352         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1353         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1354         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1355 }
1356
1357 /**
1358  *  ixgbe_enable_mdd_X550
1359  *  @hw: pointer to hardware structure
1360  *
1361  *  Enable malicious driver detection
1362  **/
1363 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1364 {
1365         u32 reg;
1366
1367         DEBUGFUNC("ixgbe_enable_mdd_X550");
1368
1369         /* Enable MDD for TX DMA and interrupt */
1370         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1371         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1372         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1373
1374         /* Enable MDD for RX and interrupt */
1375         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1376         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1377         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1378 }
1379
1380 /**
1381  *  ixgbe_restore_mdd_vf_X550
1382  *  @hw: pointer to hardware structure
1383  *  @vf: vf index
1384  *
1385  *  Restore VF that was disabled during malicious driver detection event
1386  **/
1387 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1388 {
1389         u32 idx, reg, num_qs, start_q, bitmask;
1390
1391         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1392
1393         /* Map VF to queues */
1394         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1395         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1396         case IXGBE_MRQC_VMDQRT8TCEN:
1397                 num_qs = 8;  /* 16 VFs / pools */
1398                 bitmask = 0x000000FF;
1399                 break;
1400         case IXGBE_MRQC_VMDQRSS32EN:
1401         case IXGBE_MRQC_VMDQRT4TCEN:
1402                 num_qs = 4;  /* 32 VFs / pools */
1403                 bitmask = 0x0000000F;
1404                 break;
1405         default:            /* 64 VFs / pools */
1406                 num_qs = 2;
1407                 bitmask = 0x00000003;
1408                 break;
1409         }
1410         start_q = vf * num_qs;
1411
1412         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1413         idx = start_q / 32;
1414         reg = 0;
1415         reg |= (bitmask << (start_q % 32));
1416         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1417         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1418 }
1419
1420 /**
1421  *  ixgbe_mdd_event_X550
1422  *  @hw: pointer to hardware structure
1423  *  @vf_bitmap: vf bitmap of malicious vfs
1424  *
1425  *  Handle malicious driver detection event.
1426  **/
1427 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1428 {
1429         u32 wqbr;
1430         u32 i, j, reg, q, shift, vf, idx;
1431
1432         DEBUGFUNC("ixgbe_mdd_event_X550");
1433
1434         /* figure out pool size for mapping to vf's */
1435         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1436         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1437         case IXGBE_MRQC_VMDQRT8TCEN:
1438                 shift = 3;  /* 16 VFs / pools */
1439                 break;
1440         case IXGBE_MRQC_VMDQRSS32EN:
1441         case IXGBE_MRQC_VMDQRT4TCEN:
1442                 shift = 2;  /* 32 VFs / pools */
1443                 break;
1444         default:
1445                 shift = 1;  /* 64 VFs / pools */
1446                 break;
1447         }
1448
1449         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1450         for (i = 0; i < 4; i++) {
1451                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1452                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1453
1454                 if (!wqbr)
1455                         continue;
1456
1457                 /* Get malicious queue */
1458                 for (j = 0; j < 32 && wqbr; j++) {
1459
1460                         if (!(wqbr & (1 << j)))
1461                                 continue;
1462
1463                         /* Get queue from bitmask */
1464                         q = j + (i * 32);
1465
1466                         /* Map queue to vf */
1467                         vf = (q >> shift);
1468
1469                         /* Set vf bit in vf_bitmap */
1470                         idx = vf / 32;
1471                         vf_bitmap[idx] |= (1 << (vf % 32));
1472                         wqbr &= ~(1 << j);
1473                 }
1474         }
1475 }
1476
1477 /**
1478  *  ixgbe_get_media_type_X550em - Get media type
1479  *  @hw: pointer to hardware structure
1480  *
1481  *  Returns the media type (fiber, copper, backplane)
1482  */
1483 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1484 {
1485         enum ixgbe_media_type media_type;
1486
1487         DEBUGFUNC("ixgbe_get_media_type_X550em");
1488
1489         /* Detect if there is a copper PHY attached. */
1490         switch (hw->device_id) {
1491         case IXGBE_DEV_ID_X550EM_X_KR:
1492         case IXGBE_DEV_ID_X550EM_X_KX4:
1493         case IXGBE_DEV_ID_X550EM_A_KR:
1494         case IXGBE_DEV_ID_X550EM_A_KR_L:
1495                 media_type = ixgbe_media_type_backplane;
1496                 break;
1497         case IXGBE_DEV_ID_X550EM_X_SFP:
1498         case IXGBE_DEV_ID_X550EM_A_SFP:
1499         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1500         case IXGBE_DEV_ID_X550EM_A_QSFP:
1501         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1502                 media_type = ixgbe_media_type_fiber;
1503                 break;
1504         case IXGBE_DEV_ID_X550EM_X_1G_T:
1505         case IXGBE_DEV_ID_X550EM_X_10G_T:
1506         case IXGBE_DEV_ID_X550EM_A_10G_T:
1507                 media_type = ixgbe_media_type_copper;
1508                 break;
1509         case IXGBE_DEV_ID_X550EM_A_SGMII:
1510         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1511                 media_type = ixgbe_media_type_backplane;
1512                 hw->phy.type = ixgbe_phy_sgmii;
1513                 break;
1514         case IXGBE_DEV_ID_X550EM_A_1G_T:
1515         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1516                 media_type = ixgbe_media_type_copper;
1517                 break;
1518         default:
1519                 media_type = ixgbe_media_type_unknown;
1520                 break;
1521         }
1522         return media_type;
1523 }
1524
1525 /**
1526  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1527  *  @hw: pointer to hardware structure
1528  *  @linear: true if SFP module is linear
1529  */
1530 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1531 {
1532         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1533
1534         switch (hw->phy.sfp_type) {
1535         case ixgbe_sfp_type_not_present:
1536                 return IXGBE_ERR_SFP_NOT_PRESENT;
1537         case ixgbe_sfp_type_da_cu_core0:
1538         case ixgbe_sfp_type_da_cu_core1:
1539                 *linear = true;
1540                 break;
1541         case ixgbe_sfp_type_srlr_core0:
1542         case ixgbe_sfp_type_srlr_core1:
1543         case ixgbe_sfp_type_da_act_lmt_core0:
1544         case ixgbe_sfp_type_da_act_lmt_core1:
1545         case ixgbe_sfp_type_1g_sx_core0:
1546         case ixgbe_sfp_type_1g_sx_core1:
1547         case ixgbe_sfp_type_1g_lx_core0:
1548         case ixgbe_sfp_type_1g_lx_core1:
1549                 *linear = false;
1550                 break;
1551         case ixgbe_sfp_type_unknown:
1552         case ixgbe_sfp_type_1g_cu_core0:
1553         case ixgbe_sfp_type_1g_cu_core1:
1554         default:
1555                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1556         }
1557
1558         return IXGBE_SUCCESS;
1559 }
1560
1561 /**
1562  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1563  *  @hw: pointer to hardware structure
1564  *
1565  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1566  **/
1567 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1568 {
1569         s32 status;
1570         bool linear;
1571
1572         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1573
1574         status = ixgbe_identify_module_generic(hw);
1575
1576         if (status != IXGBE_SUCCESS)
1577                 return status;
1578
1579         /* Check if SFP module is supported */
1580         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1581
1582         return status;
1583 }
1584
1585 /**
1586  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1587  *  @hw: pointer to hardware structure
1588  */
1589 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1590 {
1591         s32 status;
1592         bool linear;
1593
1594         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1595
1596         /* Check if SFP module is supported */
1597         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1598
1599         if (status != IXGBE_SUCCESS)
1600                 return status;
1601
1602         ixgbe_init_mac_link_ops_X550em(hw);
1603         hw->phy.ops.reset = NULL;
1604
1605         return IXGBE_SUCCESS;
1606 }
1607
1608 /**
1609  * ixgbe_setup_sgmii - Set up link for sgmii
1610  * @hw: pointer to hardware structure
1611  */
1612 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1613                              bool autoneg_wait)
1614 {
1615         struct ixgbe_mac_info *mac = &hw->mac;
1616         u32 lval, sval;
1617         s32 rc;
1618
1619         rc = mac->ops.read_iosf_sb_reg(hw,
1620                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1621                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1622         if (rc)
1623                 return rc;
1624
1625         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1626         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1627         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1628         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1629         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1630         rc = mac->ops.write_iosf_sb_reg(hw,
1631                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1632                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1633         if (rc)
1634                 return rc;
1635
1636         rc = mac->ops.read_iosf_sb_reg(hw,
1637                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1638                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1639         if (rc)
1640                 return rc;
1641
1642         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1643         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1644         rc = mac->ops.write_iosf_sb_reg(hw,
1645                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1646                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1647         if (rc)
1648                 return rc;
1649
1650         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1651         rc = mac->ops.write_iosf_sb_reg(hw,
1652                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1653                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1654         if (rc)
1655                 return rc;
1656
1657         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1658 }
1659
1660  /**
1661  * ixgbe_setup_sgmii_m88 - Set up link for sgmii with Marvell PHYs
1662  * @hw: pointer to hardware structure
1663  */
1664 STATIC s32 ixgbe_setup_sgmii_m88(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1665                                  bool autoneg_wait)
1666 {
1667         struct ixgbe_mac_info *mac = &hw->mac;
1668         u32 lval, sval;
1669         s32 rc;
1670
1671         rc = mac->ops.read_iosf_sb_reg(hw,
1672                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1673                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1674         if (rc)
1675                 return rc;
1676
1677         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1678         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1679         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1680         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1681         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1682         rc = mac->ops.write_iosf_sb_reg(hw,
1683                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1684                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1685         if (rc)
1686                 return rc;
1687
1688         rc = mac->ops.read_iosf_sb_reg(hw,
1689                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1690                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1691         if (rc)
1692                 return rc;
1693
1694         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1695         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1696         rc = mac->ops.write_iosf_sb_reg(hw,
1697                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1698                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1699         if (rc)
1700                 return rc;
1701
1702         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1703         rc = mac->ops.write_iosf_sb_reg(hw,
1704                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1705                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1706         if (rc)
1707                 return rc;
1708
1709         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1710 }
1711
1712 /**
1713  * ixgbe_check_link_m88 - Poll PHY for link
1714  * @hw: pointer to hardware structure
1715  * @speed: pointer to link speed
1716  * @link_up: true when link is up
1717  * @link_up_wait: bool indicating whether to wait for link
1718  *
1719  * Check that both the MAC and PHY have link.
1720  */
1721 static s32
1722 ixgbe_check_link_m88(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1723                      bool *link_up, bool link_up_wait)
1724 {
1725         u16 reg;
1726         s32 rc;
1727         u32 i;
1728
1729         rc = ixgbe_check_mac_link_generic(hw, speed, link_up, link_up_wait);
1730         if (rc || !*link_up)
1731                 return rc;
1732
1733         rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_PHY_SPEC_STATUS, 0, &reg);
1734
1735         /* MAC link is up, so check external PHY link */
1736         *link_up = !!(reg & IXGBE_M88E1500_PHY_SPEC_STATUS_LINK);
1737
1738         if (link_up_wait) {
1739                 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
1740                         if (!rc &&
1741                             (reg & IXGBE_M88E1500_PHY_SPEC_STATUS_LINK)) {
1742                                 *link_up = true;
1743                                 break;
1744                         }
1745                         *link_up = false;
1746                         msec_delay(100);
1747                         rc = hw->phy.ops.read_reg(hw,
1748                                                  IXGBE_M88E1500_PHY_SPEC_STATUS,
1749                                                  0, &reg);
1750                 }
1751         }
1752
1753 #define M88_SPEED(x) (IXGBE_M88E1500_PHY_SPEC_STATUS_RESOLVED  | \
1754                       IXGBE_M88E1500_PHY_SPEC_STATUS_DUPLEX     | \
1755                       ((IXGBE_M88E1500_PHY_SPEC_STATUS_SPEED_##x) <<\
1756                         IXGBE_M88E1500_PHY_SPEC_STATUS_SPEED_SHIFT))
1757
1758         reg &= M88_SPEED(MASK);
1759         switch (reg) {
1760         case M88_SPEED(10):
1761                 *speed = IXGBE_LINK_SPEED_10_FULL;
1762                 break;
1763         case M88_SPEED(100):
1764                 *speed = IXGBE_LINK_SPEED_100_FULL;
1765                 break;
1766         case M88_SPEED(1000):
1767                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1768                 break;
1769         default:
1770                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1771                 break;
1772         }
1773 #undef M88_SPEED
1774
1775         return rc;
1776 }
1777
1778 /**
1779  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1780  *  @hw: pointer to hardware structure
1781  */
1782 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1783 {
1784         struct ixgbe_mac_info *mac = &hw->mac;
1785
1786         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1787
1788         switch (hw->mac.ops.get_media_type(hw)) {
1789         case ixgbe_media_type_fiber:
1790                 /* CS4227 does not support autoneg, so disable the laser control
1791                  * functions for SFP+ fiber
1792                  */
1793                 mac->ops.disable_tx_laser = NULL;
1794                 mac->ops.enable_tx_laser = NULL;
1795                 mac->ops.flap_tx_laser = NULL;
1796                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1797                 mac->ops.set_rate_select_speed =
1798                                         ixgbe_set_soft_rate_select_speed;
1799                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1800                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1801                         mac->ops.setup_mac_link =
1802                                 ixgbe_setup_mac_link_sfp_x550a;
1803                 else
1804                         mac->ops.setup_mac_link =
1805                                 ixgbe_setup_mac_link_sfp_x550em;
1806                 break;
1807         case ixgbe_media_type_copper:
1808                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1809                     hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1810                         mac->ops.setup_link = ixgbe_setup_sgmii_m88;
1811                         mac->ops.check_link = ixgbe_check_link_m88;
1812                 } else {
1813                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1814                         mac->ops.check_link = ixgbe_check_link_t_X550em;
1815                 }
1816                 break;
1817         case ixgbe_media_type_backplane:
1818                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1819                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1820                         mac->ops.setup_link = ixgbe_setup_sgmii;
1821                 break;
1822         default:
1823                 break;
1824         }
1825 }
1826
1827 /**
1828  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1829  *  @hw: pointer to hardware structure
1830  *  @speed: pointer to link speed
1831  *  @autoneg: true when autoneg or autotry is enabled
1832  */
1833 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1834                                        ixgbe_link_speed *speed,
1835                                        bool *autoneg)
1836 {
1837         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1838
1839         /* SFP */
1840         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1841
1842                 /* CS4227 SFP must not enable auto-negotiation */
1843                 *autoneg = false;
1844
1845                 /* Check if 1G SFP module. */
1846                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1847                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1848                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1849                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1850                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1851                         return IXGBE_SUCCESS;
1852                 }
1853
1854                 /* Link capabilities are based on SFP */
1855                 if (hw->phy.multispeed_fiber)
1856                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1857                                  IXGBE_LINK_SPEED_1GB_FULL;
1858                 else
1859                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1860         } else {
1861                 switch (hw->phy.type) {
1862                 case ixgbe_phy_m88:
1863                         *speed = IXGBE_LINK_SPEED_1GB_FULL |
1864                                  IXGBE_LINK_SPEED_100_FULL |
1865                                  IXGBE_LINK_SPEED_10_FULL;
1866                         break;
1867                 case ixgbe_phy_sgmii:
1868                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1869                         break;
1870                 default:
1871                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1872                                  IXGBE_LINK_SPEED_1GB_FULL;
1873                         break;
1874                 }
1875                 *autoneg = true;
1876         }
1877
1878         return IXGBE_SUCCESS;
1879 }
1880
1881 /**
1882  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1883  * @hw: pointer to hardware structure
1884  * @lsc: pointer to boolean flag which indicates whether external Base T
1885  *       PHY interrupt is lsc
1886  *
1887  * Determime if external Base T PHY interrupt cause is high temperature
1888  * failure alarm or link status change.
1889  *
1890  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1891  * failure alarm, else return PHY access status.
1892  */
1893 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1894 {
1895         u32 status;
1896         u16 reg;
1897
1898         *lsc = false;
1899
1900         /* Vendor alarm triggered */
1901         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1902                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1903                                       &reg);
1904
1905         if (status != IXGBE_SUCCESS ||
1906             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1907                 return status;
1908
1909         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1910         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1911                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1912                                       &reg);
1913
1914         if (status != IXGBE_SUCCESS ||
1915             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1916             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1917                 return status;
1918
1919         /* Global alarm triggered */
1920         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1921                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1922                                       &reg);
1923
1924         if (status != IXGBE_SUCCESS)
1925                 return status;
1926
1927         /* If high temperature failure, then return over temp error and exit */
1928         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1929                 /* power down the PHY in case the PHY FW didn't already */
1930                 ixgbe_set_copper_phy_power(hw, false);
1931                 return IXGBE_ERR_OVERTEMP;
1932         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1933                 /*  device fault alarm triggered */
1934                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1935                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1936                                           &reg);
1937
1938                 if (status != IXGBE_SUCCESS)
1939                         return status;
1940
1941                 /* if device fault was due to high temp alarm handle and exit */
1942                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1943                         /* power down the PHY in case the PHY FW didn't */
1944                         ixgbe_set_copper_phy_power(hw, false);
1945                         return IXGBE_ERR_OVERTEMP;
1946                 }
1947         }
1948
1949         /* Vendor alarm 2 triggered */
1950         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1951                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1952
1953         if (status != IXGBE_SUCCESS ||
1954             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1955                 return status;
1956
1957         /* link connect/disconnect event occurred */
1958         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1959                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1960
1961         if (status != IXGBE_SUCCESS)
1962                 return status;
1963
1964         /* Indicate LSC */
1965         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1966                 *lsc = true;
1967
1968         return IXGBE_SUCCESS;
1969 }
1970
1971 /**
1972  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1973  * @hw: pointer to hardware structure
1974  *
1975  * Enable link status change and temperature failure alarm for the external
1976  * Base T PHY
1977  *
1978  * Returns PHY access status
1979  */
1980 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1981 {
1982         u32 status;
1983         u16 reg;
1984         bool lsc;
1985
1986         /* Clear interrupt flags */
1987         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1988
1989         /* Enable link status change alarm */
1990         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1991                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1992
1993         if (status != IXGBE_SUCCESS)
1994                 return status;
1995
1996         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1997
1998         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1999                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2000
2001         if (status != IXGBE_SUCCESS)
2002                 return status;
2003
2004         /* Enable high temperature failure and global fault alarms */
2005         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2006                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2007                                       &reg);
2008
2009         if (status != IXGBE_SUCCESS)
2010                 return status;
2011
2012         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2013                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2014
2015         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2016                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2017                                        reg);
2018
2019         if (status != IXGBE_SUCCESS)
2020                 return status;
2021
2022         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2023         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2024                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2025                                       &reg);
2026
2027         if (status != IXGBE_SUCCESS)
2028                 return status;
2029
2030         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2031                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2032
2033         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2034                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2035                                        reg);
2036
2037         if (status != IXGBE_SUCCESS)
2038                 return status;
2039
2040         /* Enable chip-wide vendor alarm */
2041         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2042                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2043                                       &reg);
2044
2045         if (status != IXGBE_SUCCESS)
2046                 return status;
2047
2048         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2049
2050         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2051                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2052                                        reg);
2053
2054         return status;
2055 }
2056
2057 /**
2058  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2059  *  @hw: pointer to hardware structure
2060  *  @speed: link speed
2061  *
2062  *  Configures the integrated KR PHY.
2063  **/
2064 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2065                                        ixgbe_link_speed speed)
2066 {
2067         s32 status;
2068         u32 reg_val;
2069
2070         status = hw->mac.ops.read_iosf_sb_reg(hw,
2071                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2072                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2073         if (status)
2074                 return status;
2075
2076         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2077         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2078                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2079
2080         /* Advertise 10G support. */
2081         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2082                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2083
2084         /* Advertise 1G support. */
2085         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2086                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2087
2088         /* Restart auto-negotiation. */
2089         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2090         status = hw->mac.ops.write_iosf_sb_reg(hw,
2091                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2092                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2093
2094         return status;
2095 }
2096
2097 /**
2098  * ixgbe_setup_m88 - setup m88 PHY
2099  * @hw: pointer to hardware structure
2100  */
2101 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2102 {
2103         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2104         u16 reg;
2105         s32 rc;
2106
2107         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2108                 return IXGBE_SUCCESS;
2109
2110         rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2111         if (rc)
2112                 return rc;
2113
2114         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2115         if (rc)
2116                 goto out;
2117         if (reg & IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN) {
2118                 reg &= ~IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN;
2119                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2120                                           reg);
2121         }
2122
2123         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, &reg);
2124         if (rc)
2125                 goto out;
2126         if (reg & IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN) {
2127                 reg &= ~IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN;
2128                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0,
2129                                           reg);
2130         }
2131
2132         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 2);
2133         if (rc)
2134                 goto out;
2135
2136         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2137                                       &reg);
2138         if (rc)
2139                 goto out;
2140         if (reg & IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN) {
2141                 reg &= ~IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN;
2142                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2143                                           reg);
2144                 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2145                                                0);
2146                 if (rc)
2147                         goto out;
2148                 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2149                                               &reg);
2150                 if (rc)
2151                         goto out;
2152                 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2153                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2154                                           reg);
2155                 usec_delay(50);
2156         } else {
2157                 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2158                                                0);
2159                 if (rc)
2160                         goto out;
2161         }
2162
2163         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2164         if (rc)
2165                 goto out;
2166
2167         if (!(reg & IXGBE_M88E1500_COPPER_CTRL_AN_EN)) {
2168                 reg |= IXGBE_M88E1500_COPPER_CTRL_AN_EN;
2169                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2170                                           reg);
2171         }
2172
2173         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, &reg);
2174         if (rc)
2175                 goto out;
2176         reg &= ~IXGBE_M88E1500_1000T_CTRL_HALF_DUPLEX;
2177         reg &= ~IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2178         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
2179                 reg |= IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2180         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, reg);
2181
2182         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, &reg);
2183         if (rc)
2184                 goto out;
2185         reg &= ~IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
2186         reg &= ~IXGBE_M88E1500_COPPER_AN_PAUSE;
2187         reg &= ~IXGBE_M88E1500_COPPER_AN_T4;
2188         reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_FD;
2189         reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_HD;
2190         reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_FD;
2191         reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_HD;
2192         switch (hw->fc.current_mode) {
2193         case ixgbe_fc_full:
2194                 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
2195                 break;
2196         case ixgbe_fc_rx_pause:
2197                 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
2198                 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
2199                 break;
2200         case ixgbe_fc_tx_pause:
2201                 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
2202                 break;
2203         default:
2204                 break;
2205         }
2206
2207         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
2208                 reg |= IXGBE_M88E1500_COPPER_AN_100TX_FD;
2209         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
2210                 reg |= IXGBE_M88E1500_COPPER_AN_10TX_FD;
2211         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, reg);
2212
2213         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2214         if (rc)
2215                 goto out;
2216         reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
2217         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2218
2219
2220         hw->mac.ops.release_swfw_sync(hw, mask);
2221         return rc;
2222
2223 out:
2224         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2225         hw->mac.ops.release_swfw_sync(hw, mask);
2226         return rc;
2227 }
2228
2229 /**
2230  * ixgbe_reset_phy_m88e1500 - Reset m88e1500 PHY
2231  * @hw: pointer to hardware structure
2232  *
2233  * The PHY token must be held when calling this function.
2234  */
2235 static s32 ixgbe_reset_phy_m88e1500(struct ixgbe_hw *hw)
2236 {
2237         u16 reg;
2238         s32 rc;
2239
2240         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2241         if (rc)
2242                 return rc;
2243
2244         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2245         if (rc)
2246                 return rc;
2247
2248         reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2249         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2250
2251         usec_delay(10);
2252
2253         return rc;
2254 }
2255
2256 /**
2257  * ixgbe_reset_phy_m88e1543 - Reset m88e1543 PHY
2258  * @hw: pointer to hardware structure
2259  *
2260  * The PHY token must be held when calling this function.
2261  */
2262 static s32 ixgbe_reset_phy_m88e1543(struct ixgbe_hw *hw)
2263 {
2264         return hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2265 }
2266
2267 /**
2268  * ixgbe_reset_phy_m88 - Reset m88 PHY
2269  * @hw: pointer to hardware structure
2270  */
2271 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2272 {
2273         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2274         u16 reg;
2275         s32 rc;
2276
2277         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2278                 return IXGBE_SUCCESS;
2279
2280         rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2281         if (rc)
2282                 return rc;
2283
2284         switch (hw->phy.id) {
2285         case IXGBE_M88E1500_E_PHY_ID:
2286                 rc = ixgbe_reset_phy_m88e1500(hw);
2287                 break;
2288         case IXGBE_M88E1543_E_PHY_ID:
2289                 rc = ixgbe_reset_phy_m88e1543(hw);
2290                 break;
2291         default:
2292                 rc = IXGBE_ERR_PHY;
2293                 break;
2294         }
2295
2296         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2297         if (rc)
2298                 goto out;
2299
2300         reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2301               IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2302               IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2303         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2304         if (rc)
2305                 goto out;
2306
2307         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2308         if (rc)
2309                 goto out;
2310
2311         reg = IXGBE_M88E1500_GEN_CTRL_RESET |
2312               IXGBE_M88E1500_GEN_CTRL_MODE_SGMII_COPPER;
2313         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_GEN_CTRL, 0, reg);
2314         if (rc)
2315                 goto out;
2316
2317         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2318         if (rc)
2319                 goto out;
2320
2321         reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2322               IXGBE_M88E1500_FIBER_CTRL_AN_EN |
2323               IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2324               IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2325         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2326         if (rc)
2327                 goto out;
2328
2329         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2330         if (rc)
2331                 goto out;
2332
2333         reg = (IXGBE_M88E1500_MAC_CTRL_1_DWN_4X <<
2334                IXGBE_M88E1500_MAC_CTRL_1_DWN_SHIFT) |
2335               (IXGBE_M88E1500_MAC_CTRL_1_ED_TM <<
2336                IXGBE_M88E1500_MAC_CTRL_1_ED_SHIFT) |
2337               (IXGBE_M88E1500_MAC_CTRL_1_MDIX_AUTO <<
2338                IXGBE_M88E1500_MAC_CTRL_1_MDIX_SHIFT);
2339         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, reg);
2340         if (rc)
2341                 goto out;
2342
2343         reg = IXGBE_M88E1500_COPPER_CTRL_RESET |
2344               IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2345               IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2346               IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2347               IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB;
2348         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2349         if (rc)
2350                 goto out;
2351
2352         hw->mac.ops.release_swfw_sync(hw, mask);
2353
2354         return ixgbe_setup_m88(hw);
2355
2356 out:
2357         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2358         hw->mac.ops.release_swfw_sync(hw, mask);
2359         return rc;
2360 }
2361
2362 /**
2363  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2364  *  @hw: pointer to hardware structure
2365  *
2366  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2367  *  values.
2368  **/
2369 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2370 {
2371         /* Save NW management interface connected on board. This is used
2372          * to determine internal PHY mode.
2373          */
2374         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2375
2376         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2377          * PHY address. This register field was has only been used for X552.
2378          */
2379         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2380             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2381                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2382                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2383                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2384         }
2385
2386         return IXGBE_SUCCESS;
2387 }
2388
2389 /**
2390  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2391  *  @hw: pointer to hardware structure
2392  *
2393  *  Initialize any function pointers that were not able to be
2394  *  set during init_shared_code because the PHY/SFP type was
2395  *  not known.  Perform the SFP init if necessary.
2396  */
2397 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2398 {
2399         struct ixgbe_phy_info *phy = &hw->phy;
2400         s32 ret_val;
2401
2402         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2403
2404         hw->mac.ops.set_lan_id(hw);
2405
2406         ixgbe_read_mng_if_sel_x550em(hw);
2407
2408         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2409                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2410                 ixgbe_setup_mux_ctl(hw);
2411                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2412         }
2413
2414         switch (hw->device_id) {
2415         case IXGBE_DEV_ID_X550EM_A_1G_T:
2416         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2417                 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2418                 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2419                 break;
2420         default:
2421                 break;
2422         }
2423
2424         /* Identify the PHY or SFP module */
2425         ret_val = phy->ops.identify(hw);
2426         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2427                 return ret_val;
2428
2429         /* Setup function pointers based on detected hardware */
2430         ixgbe_init_mac_link_ops_X550em(hw);
2431         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2432                 phy->ops.reset = NULL;
2433
2434         /* Set functions pointers based on phy type */
2435         switch (hw->phy.type) {
2436         case ixgbe_phy_x550em_kx4:
2437                 phy->ops.setup_link = NULL;
2438                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2439                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2440                 break;
2441         case ixgbe_phy_x550em_kr:
2442                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2443                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2444                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2445                 break;
2446         case ixgbe_phy_x550em_ext_t:
2447                 /* If internal link mode is XFI, then setup iXFI internal link,
2448                  * else setup KR now.
2449                  */
2450                 phy->ops.setup_internal_link =
2451                                               ixgbe_setup_internal_phy_t_x550em;
2452
2453                 /* setup SW LPLU only for first revision of X550EM_x */
2454                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2455                     !(IXGBE_FUSES0_REV_MASK &
2456                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2457                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2458
2459                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2460                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2461                 break;
2462         case ixgbe_phy_sgmii:
2463                 phy->ops.setup_link = NULL;
2464                 break;
2465         case ixgbe_phy_m88:
2466                 phy->ops.setup_link = ixgbe_setup_m88;
2467                 phy->ops.reset = ixgbe_reset_phy_m88;
2468                 break;
2469         default:
2470                 break;
2471         }
2472         return ret_val;
2473 }
2474
2475 /**
2476  * ixgbe_set_mdio_speed - Set MDIO clock speed
2477  *  @hw: pointer to hardware structure
2478  */
2479 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2480 {
2481         u32 hlreg0;
2482
2483         switch (hw->device_id) {
2484         case IXGBE_DEV_ID_X550EM_X_10G_T:
2485         case IXGBE_DEV_ID_X550EM_A_SGMII:
2486         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2487         case IXGBE_DEV_ID_X550EM_A_1G_T:
2488         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2489         case IXGBE_DEV_ID_X550EM_A_10G_T:
2490         case IXGBE_DEV_ID_X550EM_A_SFP:
2491         case IXGBE_DEV_ID_X550EM_A_QSFP:
2492                 /* Config MDIO clock speed before the first MDIO PHY access */
2493                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2494                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2495                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2496                 break;
2497         default:
2498                 break;
2499         }
2500 }
2501
2502 /**
2503  *  ixgbe_reset_hw_X550em - Perform hardware reset
2504  *  @hw: pointer to hardware structure
2505  *
2506  *  Resets the hardware by resetting the transmit and receive units, masks
2507  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2508  *  reset.
2509  */
2510 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2511 {
2512         ixgbe_link_speed link_speed;
2513         s32 status;
2514         u32 ctrl = 0;
2515         u32 i;
2516         bool link_up = false;
2517
2518         DEBUGFUNC("ixgbe_reset_hw_X550em");
2519
2520         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2521         status = hw->mac.ops.stop_adapter(hw);
2522         if (status != IXGBE_SUCCESS)
2523                 return status;
2524
2525         /* flush pending Tx transactions */
2526         ixgbe_clear_tx_pending(hw);
2527
2528         ixgbe_set_mdio_speed(hw);
2529
2530         /* PHY ops must be identified and initialized prior to reset */
2531         status = hw->phy.ops.init(hw);
2532
2533         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2534                 return status;
2535
2536         /* start the external PHY */
2537         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2538                 status = ixgbe_init_ext_t_x550em(hw);
2539                 if (status)
2540                         return status;
2541         }
2542
2543         /* Setup SFP module if there is one present. */
2544         if (hw->phy.sfp_setup_needed) {
2545                 status = hw->mac.ops.setup_sfp(hw);
2546                 hw->phy.sfp_setup_needed = false;
2547         }
2548
2549         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2550                 return status;
2551
2552         /* Reset PHY */
2553         if (!hw->phy.reset_disable && hw->phy.ops.reset)
2554                 hw->phy.ops.reset(hw);
2555
2556 mac_reset_top:
2557         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2558          * If link reset is used when link is up, it might reset the PHY when
2559          * mng is using it.  If link is down or the flag to force full link
2560          * reset is set, then perform link reset.
2561          */
2562         ctrl = IXGBE_CTRL_LNK_RST;
2563         if (!hw->force_full_reset) {
2564                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2565                 if (link_up)
2566                         ctrl = IXGBE_CTRL_RST;
2567         }
2568
2569         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2570         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2571         IXGBE_WRITE_FLUSH(hw);
2572
2573         /* Poll for reset bit to self-clear meaning reset is complete */
2574         for (i = 0; i < 10; i++) {
2575                 usec_delay(1);
2576                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2577                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2578                         break;
2579         }
2580
2581         if (ctrl & IXGBE_CTRL_RST_MASK) {
2582                 status = IXGBE_ERR_RESET_FAILED;
2583                 DEBUGOUT("Reset polling failed to complete.\n");
2584         }
2585
2586         msec_delay(50);
2587
2588         /* Double resets are required for recovery from certain error
2589          * conditions.  Between resets, it is necessary to stall to
2590          * allow time for any pending HW events to complete.
2591          */
2592         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2593                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2594                 goto mac_reset_top;
2595         }
2596
2597         /* Store the permanent mac address */
2598         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2599
2600         /* Store MAC address from RAR0, clear receive address registers, and
2601          * clear the multicast table.  Also reset num_rar_entries to 128,
2602          * since we modify this value when programming the SAN MAC address.
2603          */
2604         hw->mac.num_rar_entries = 128;
2605         hw->mac.ops.init_rx_addrs(hw);
2606
2607         ixgbe_set_mdio_speed(hw);
2608
2609         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2610                 ixgbe_setup_mux_ctl(hw);
2611
2612         return status;
2613 }
2614
2615 /**
2616  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2617  * @hw: pointer to hardware structure
2618  */
2619 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2620 {
2621         u32 status;
2622         u16 reg;
2623
2624         status = hw->phy.ops.read_reg(hw,
2625                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2626                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2627                                       &reg);
2628
2629         if (status != IXGBE_SUCCESS)
2630                 return status;
2631
2632         /* If PHY FW reset completed bit is set then this is the first
2633          * SW instance after a power on so the PHY FW must be un-stalled.
2634          */
2635         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2636                 status = hw->phy.ops.read_reg(hw,
2637                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2638                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2639                                         &reg);
2640
2641                 if (status != IXGBE_SUCCESS)
2642                         return status;
2643
2644                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2645
2646                 status = hw->phy.ops.write_reg(hw,
2647                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2648                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2649                                         reg);
2650
2651                 if (status != IXGBE_SUCCESS)
2652                         return status;
2653         }
2654
2655         return status;
2656 }
2657
2658 /**
2659  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2660  *  @hw: pointer to hardware structure
2661  *
2662  *  Configures the integrated KR PHY for X550EM_x.
2663  **/
2664 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2665 {
2666         if (hw->mac.type != ixgbe_mac_X550EM_x)
2667                 return IXGBE_SUCCESS;
2668
2669         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2670 }
2671
2672 /**
2673  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2674  *  @hw: pointer to hardware structure
2675  *
2676  *  Configure the external PHY and the integrated KR PHY for SFP support.
2677  **/
2678 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2679                                     ixgbe_link_speed speed,
2680                                     bool autoneg_wait_to_complete)
2681 {
2682         s32 ret_val;
2683         u16 reg_slice, reg_val;
2684         bool setup_linear = false;
2685         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2686
2687         /* Check if SFP module is supported and linear */
2688         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2689
2690         /* If no SFP module present, then return success. Return success since
2691          * there is no reason to configure CS4227 and SFP not present error is
2692          * not excepted in the setup MAC link flow.
2693          */
2694         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2695                 return IXGBE_SUCCESS;
2696
2697         if (ret_val != IXGBE_SUCCESS)
2698                 return ret_val;
2699
2700         /* Configure internal PHY for KR/KX. */
2701         ixgbe_setup_kr_speed_x550em(hw, speed);
2702
2703         /* Configure CS4227 LINE side to proper mode. */
2704         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2705                     (hw->bus.lan_id << 12);
2706         if (setup_linear)
2707                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2708         else
2709                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2710         ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2711                                           reg_val);
2712         return ret_val;
2713 }
2714
2715 /**
2716  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2717  *  @hw: pointer to hardware structure
2718  *
2719  *  Configure the the integrated PHY for SFP support.
2720  **/
2721 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2722                                    ixgbe_link_speed speed,
2723                                    bool autoneg_wait_to_complete)
2724 {
2725         s32 ret_val;
2726         u16 reg_phy_ext;
2727         bool setup_linear = false;
2728         u32 reg_slice, reg_phy_int, slice_offset;
2729
2730         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2731
2732         /* Check if SFP module is supported and linear */
2733         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2734
2735         /* If no SFP module present, then return success. Return success since
2736          * SFP not present error is not excepted in the setup MAC link flow.
2737          */
2738         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2739                 return IXGBE_SUCCESS;
2740
2741         if (ret_val != IXGBE_SUCCESS)
2742                 return ret_val;
2743
2744         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2745                 /* Configure internal PHY for native SFI */
2746                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2747                                IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2748                                IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2749
2750                 if (ret_val != IXGBE_SUCCESS)
2751                         return ret_val;
2752
2753                 if (setup_linear) {
2754                         reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2755                         reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2756                 } else {
2757                         reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2758                         reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2759                 }
2760
2761                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2762                                 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2763                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2764
2765                 if (ret_val != IXGBE_SUCCESS)
2766                         return ret_val;
2767
2768                 /* Setup XFI/SFI internal link. */
2769                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2770         } else {
2771                 /* Configure internal PHY for KR/KX. */
2772                 ixgbe_setup_kr_speed_x550em(hw, speed);
2773
2774                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2775                         /* Find Address */
2776                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2777                         return IXGBE_ERR_PHY_ADDR_INVALID;
2778                 }
2779
2780                 /* Get external PHY device id */
2781                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2782                                        IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2783
2784                 if (ret_val != IXGBE_SUCCESS)
2785                         return ret_val;
2786
2787                 /* When configuring quad port CS4223, the MAC instance is part
2788                  * of the slice offset.
2789                  */
2790                 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2791                         slice_offset = (hw->bus.lan_id +
2792                                         (hw->bus.instance_id << 1)) << 12;
2793                 else
2794                         slice_offset = hw->bus.lan_id << 12;
2795
2796                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2797                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2798                 if (setup_linear)
2799                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2800                 else
2801                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2802                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2803                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2804         }
2805         return ret_val;
2806 }
2807
2808 /**
2809  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2810  *  @hw: pointer to hardware structure
2811  *
2812  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2813  **/
2814 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2815 {
2816         struct ixgbe_mac_info *mac = &hw->mac;
2817         s32 status;
2818         u32 reg_val;
2819
2820         /* Disable training protocol FSM. */
2821         status = mac->ops.read_iosf_sb_reg(hw,
2822                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2823                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2824         if (status != IXGBE_SUCCESS)
2825                 return status;
2826         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2827         status = mac->ops.write_iosf_sb_reg(hw,
2828                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2829                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2830         if (status != IXGBE_SUCCESS)
2831                 return status;
2832
2833         /* Disable Flex from training TXFFE. */
2834         status = mac->ops.read_iosf_sb_reg(hw,
2835                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2836                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2837         if (status != IXGBE_SUCCESS)
2838                 return status;
2839         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2840         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2841         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2842         status = mac->ops.write_iosf_sb_reg(hw,
2843                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2844                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2845         if (status != IXGBE_SUCCESS)
2846                 return status;
2847         status = mac->ops.read_iosf_sb_reg(hw,
2848                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2849                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2850         if (status != IXGBE_SUCCESS)
2851                 return status;
2852         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2853         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2854         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2855         status = mac->ops.write_iosf_sb_reg(hw,
2856                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2857                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2858         if (status != IXGBE_SUCCESS)
2859                 return status;
2860
2861         /* Enable override for coefficients. */
2862         status = mac->ops.read_iosf_sb_reg(hw,
2863                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2864                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2865         if (status != IXGBE_SUCCESS)
2866                 return status;
2867         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2868         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2869         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2870         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2871         status = mac->ops.write_iosf_sb_reg(hw,
2872                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2873                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2874         return status;
2875 }
2876
2877 /**
2878  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2879  *  @hw: pointer to hardware structure
2880  *  @speed: the link speed to force
2881  *
2882  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2883  *  internal and external PHY at a specific speed, without autonegotiation.
2884  **/
2885 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2886 {
2887         struct ixgbe_mac_info *mac = &hw->mac;
2888         s32 status;
2889         u32 reg_val;
2890
2891         /* Disable AN and force speed to 10G Serial. */
2892         status = mac->ops.read_iosf_sb_reg(hw,
2893                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2894                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2895         if (status != IXGBE_SUCCESS)
2896                 return status;
2897
2898         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2899         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2900
2901         /* Select forced link speed for internal PHY. */
2902         switch (*speed) {
2903         case IXGBE_LINK_SPEED_10GB_FULL:
2904                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2905                 break;
2906         case IXGBE_LINK_SPEED_1GB_FULL:
2907                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2908                 break;
2909         default:
2910                 /* Other link speeds are not supported by internal KR PHY. */
2911                 return IXGBE_ERR_LINK_SETUP;
2912         }
2913
2914         status = mac->ops.write_iosf_sb_reg(hw,
2915                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2916                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2917         if (status != IXGBE_SUCCESS)
2918                 return status;
2919
2920         /* Additional configuration needed for x550em_x */
2921         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2922                 status = ixgbe_setup_ixfi_x550em_x(hw);
2923                 if (status != IXGBE_SUCCESS)
2924                         return status;
2925         }
2926
2927         /* Toggle port SW reset by AN reset. */
2928         status = mac->ops.read_iosf_sb_reg(hw,
2929                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2930                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2931         if (status != IXGBE_SUCCESS)
2932                 return status;
2933         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2934         status = mac->ops.write_iosf_sb_reg(hw,
2935                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2936                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2937
2938         return status;
2939 }
2940
2941 /**
2942  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2943  * @hw: address of hardware structure
2944  * @link_up: address of boolean to indicate link status
2945  *
2946  * Returns error code if unable to get link status.
2947  */
2948 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2949 {
2950         u32 ret;
2951         u16 autoneg_status;
2952
2953         *link_up = false;
2954
2955         /* read this twice back to back to indicate current status */
2956         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2957                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2958                                    &autoneg_status);
2959         if (ret != IXGBE_SUCCESS)
2960                 return ret;
2961
2962         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2963                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2964                                    &autoneg_status);
2965         if (ret != IXGBE_SUCCESS)
2966                 return ret;
2967
2968         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2969
2970         return IXGBE_SUCCESS;
2971 }
2972
2973 /**
2974  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2975  * @hw: point to hardware structure
2976  *
2977  * Configures the link between the integrated KR PHY and the external X557 PHY
2978  * The driver will call this function when it gets a link status change
2979  * interrupt from the X557 PHY. This function configures the link speed
2980  * between the PHYs to match the link speed of the BASE-T link.
2981  *
2982  * A return of a non-zero value indicates an error, and the base driver should
2983  * not report link up.
2984  */
2985 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2986 {
2987         ixgbe_link_speed force_speed;
2988         bool link_up;
2989         u32 status;
2990         u16 speed;
2991
2992         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2993                 return IXGBE_ERR_CONFIG;
2994
2995         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2996                 /* If link is down, there is no setup necessary so return  */
2997                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2998                 if (status != IXGBE_SUCCESS)
2999                         return status;
3000
3001                 if (!link_up)
3002                         return IXGBE_SUCCESS;
3003
3004                 status = hw->phy.ops.read_reg(hw,
3005                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3006                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3007                                               &speed);
3008                 if (status != IXGBE_SUCCESS)
3009                         return status;
3010
3011                 /* If link is still down - no setup is required so return */
3012                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3013                 if (status != IXGBE_SUCCESS)
3014                         return status;
3015                 if (!link_up)
3016                         return IXGBE_SUCCESS;
3017
3018                 /* clear everything but the speed and duplex bits */
3019                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3020
3021                 switch (speed) {
3022                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3023                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3024                         break;
3025                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3026                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3027                         break;
3028                 default:
3029                         /* Internal PHY does not support anything else */
3030                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
3031                 }
3032
3033                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3034         } else {
3035                 speed = IXGBE_LINK_SPEED_10GB_FULL |
3036                         IXGBE_LINK_SPEED_1GB_FULL;
3037                 return ixgbe_setup_kr_speed_x550em(hw, speed);
3038         }
3039 }
3040
3041 /**
3042  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3043  *  @hw: pointer to hardware structure
3044  *
3045  *  Configures the integrated KR PHY to use internal loopback mode.
3046  **/
3047 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3048 {
3049         s32 status;
3050         u32 reg_val;
3051
3052         /* Disable AN and force speed to 10G Serial. */
3053         status = hw->mac.ops.read_iosf_sb_reg(hw,
3054                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3055                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3056         if (status != IXGBE_SUCCESS)
3057                 return status;
3058         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3059         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3060         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3061         status = hw->mac.ops.write_iosf_sb_reg(hw,
3062                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3063                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3064         if (status != IXGBE_SUCCESS)
3065                 return status;
3066
3067         /* Set near-end loopback clocks. */
3068         status = hw->mac.ops.read_iosf_sb_reg(hw,
3069                       IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3070                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3071         if (status != IXGBE_SUCCESS)
3072                 return status;
3073         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3074         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3075         status = hw->mac.ops.write_iosf_sb_reg(hw,
3076                        IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3077                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3078         if (status != IXGBE_SUCCESS)
3079                 return status;
3080
3081         /* Set loopback enable. */
3082         status = hw->mac.ops.read_iosf_sb_reg(hw,
3083                       IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3084                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3085         if (status != IXGBE_SUCCESS)
3086                 return status;
3087         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3088         status = hw->mac.ops.write_iosf_sb_reg(hw,
3089                        IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3090                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3091         if (status != IXGBE_SUCCESS)
3092                 return status;
3093
3094         /* Training bypass. */
3095         status = hw->mac.ops.read_iosf_sb_reg(hw,
3096                       IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3097                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3098         if (status != IXGBE_SUCCESS)
3099                 return status;
3100         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3101         status = hw->mac.ops.write_iosf_sb_reg(hw,
3102                        IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3103                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3104
3105         return status;
3106 }
3107
3108 /**
3109  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3110  *  assuming that the semaphore is already obtained.
3111  *  @hw: pointer to hardware structure
3112  *  @offset: offset of  word in the EEPROM to read
3113  *  @data: word read from the EEPROM
3114  *
3115  *  Reads a 16 bit word from the EEPROM using the hostif.
3116  **/
3117 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3118                                    u16 *data)
3119 {
3120         s32 status;
3121         struct ixgbe_hic_read_shadow_ram buffer;
3122
3123         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
3124         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3125         buffer.hdr.req.buf_lenh = 0;
3126         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3127         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3128
3129         /* convert offset from words to bytes */
3130         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3131         /* one word */
3132         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3133
3134         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3135                                               sizeof(buffer),
3136                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3137
3138         if (status)
3139                 return status;
3140
3141         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3142                                           FW_NVM_DATA_OFFSET);
3143
3144         return 0;
3145 }
3146
3147 /**
3148  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3149  *  @hw: pointer to hardware structure
3150  *  @offset: offset of  word in the EEPROM to read
3151  *  @data: word read from the EEPROM
3152  *
3153  *  Reads a 16 bit word from the EEPROM using the hostif.
3154  **/
3155 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3156                               u16 *data)
3157 {
3158         s32 status = IXGBE_SUCCESS;
3159
3160         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3161
3162         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3163             IXGBE_SUCCESS) {
3164                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
3165                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3166         } else {
3167                 status = IXGBE_ERR_SWFW_SYNC;
3168         }
3169
3170         return status;
3171 }
3172
3173 /**
3174  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3175  *  @hw: pointer to hardware structure
3176  *  @offset: offset of  word in the EEPROM to read
3177  *  @words: number of words
3178  *  @data: word(s) read from the EEPROM
3179  *
3180  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
3181  **/
3182 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3183                                      u16 offset, u16 words, u16 *data)
3184 {
3185         struct ixgbe_hic_read_shadow_ram buffer;
3186         u32 current_word = 0;
3187         u16 words_to_read;
3188         s32 status;
3189         u32 i;
3190
3191         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3192
3193         /* Take semaphore for the entire operation. */
3194         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3195         if (status) {
3196                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3197                 return status;
3198         }
3199         while (words) {
3200                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3201                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3202                 else
3203                         words_to_read = words;
3204
3205                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3206                 buffer.hdr.req.buf_lenh = 0;
3207                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3208                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3209
3210                 /* convert offset from words to bytes */
3211                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3212                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3213
3214                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3215                                                       sizeof(buffer),
3216                                                       IXGBE_HI_COMMAND_TIMEOUT,
3217                                                       false);
3218
3219                 if (status) {
3220                         DEBUGOUT("Host interface command failed\n");
3221                         goto out;
3222                 }
3223
3224                 for (i = 0; i < words_to_read; i++) {
3225                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3226                                   2 * i;
3227                         u32 value = IXGBE_READ_REG(hw, reg);
3228
3229                         data[current_word] = (u16)(value & 0xffff);
3230                         current_word++;
3231                         i++;
3232                         if (i < words_to_read) {
3233                                 value >>= 16;
3234                                 data[current_word] = (u16)(value & 0xffff);
3235                                 current_word++;
3236                         }
3237                 }
3238                 words -= words_to_read;
3239         }
3240
3241 out:
3242         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3243         return status;
3244 }
3245
3246 /**
3247  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3248  *  @hw: pointer to hardware structure
3249  *  @offset: offset of  word in the EEPROM to write
3250  *  @data: word write to the EEPROM
3251  *
3252  *  Write a 16 bit word to the EEPROM using the hostif.
3253  **/
3254 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3255                                     u16 data)
3256 {
3257         s32 status;
3258         struct ixgbe_hic_write_shadow_ram buffer;
3259
3260         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3261
3262         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3263         buffer.hdr.req.buf_lenh = 0;
3264         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3265         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3266
3267          /* one word */
3268         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3269         buffer.data = data;
3270         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3271
3272         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3273                                               sizeof(buffer),
3274                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3275
3276         return status;
3277 }
3278
3279 /**
3280  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3281  *  @hw: pointer to hardware structure
3282  *  @offset: offset of  word in the EEPROM to write
3283  *  @data: word write to the EEPROM
3284  *
3285  *  Write a 16 bit word to the EEPROM using the hostif.
3286  **/
3287 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3288                                u16 data)
3289 {
3290         s32 status = IXGBE_SUCCESS;
3291
3292         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3293
3294         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3295             IXGBE_SUCCESS) {
3296                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3297                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3298         } else {
3299                 DEBUGOUT("write ee hostif failed to get semaphore");
3300                 status = IXGBE_ERR_SWFW_SYNC;
3301         }
3302
3303         return status;
3304 }
3305
3306 /**
3307  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3308  *  @hw: pointer to hardware structure
3309  *  @offset: offset of  word in the EEPROM to write
3310  *  @words: number of words
3311  *  @data: word(s) write to the EEPROM
3312  *
3313  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3314  **/
3315 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3316                                       u16 offset, u16 words, u16 *data)
3317 {
3318         s32 status = IXGBE_SUCCESS;
3319         u32 i = 0;
3320
3321         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3322
3323         /* Take semaphore for the entire operation. */
3324         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3325         if (status != IXGBE_SUCCESS) {
3326                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3327                 goto out;
3328         }
3329
3330         for (i = 0; i < words; i++) {
3331                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3332                                                          data[i]);
3333
3334                 if (status != IXGBE_SUCCESS) {
3335                         DEBUGOUT("Eeprom buffered write failed\n");
3336                         break;
3337                 }
3338         }
3339
3340         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3341 out:
3342
3343         return status;
3344 }
3345
3346 /**
3347  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3348  * @hw: pointer to hardware structure
3349  * @ptr: pointer offset in eeprom
3350  * @size: size of section pointed by ptr, if 0 first word will be used as size
3351  * @csum: address of checksum to update
3352  *
3353  * Returns error status for any failure
3354  */
3355 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3356                                    u16 size, u16 *csum, u16 *buffer,
3357                                    u32 buffer_size)
3358 {
3359         u16 buf[256];
3360         s32 status;
3361         u16 length, bufsz, i, start;
3362         u16 *local_buffer;
3363
3364         bufsz = sizeof(buf) / sizeof(buf[0]);
3365
3366         /* Read a chunk at the pointer location */
3367         if (!buffer) {
3368                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3369                 if (status) {
3370                         DEBUGOUT("Failed to read EEPROM image\n");
3371                         return status;
3372                 }
3373                 local_buffer = buf;
3374         } else {
3375                 if (buffer_size < ptr)
3376                         return  IXGBE_ERR_PARAM;
3377                 local_buffer = &buffer[ptr];
3378         }
3379
3380         if (size) {
3381                 start = 0;
3382                 length = size;
3383         } else {
3384                 start = 1;
3385                 length = local_buffer[0];
3386
3387                 /* Skip pointer section if length is invalid. */
3388                 if (length == 0xFFFF || length == 0 ||
3389                     (ptr + length) >= hw->eeprom.word_size)
3390                         return IXGBE_SUCCESS;
3391         }
3392
3393         if (buffer && ((u32)start + (u32)length > buffer_size))
3394                 return IXGBE_ERR_PARAM;
3395
3396         for (i = start; length; i++, length--) {
3397                 if (i == bufsz && !buffer) {
3398                         ptr += bufsz;
3399                         i = 0;
3400                         if (length < bufsz)
3401                                 bufsz = length;
3402
3403                         /* Read a chunk at the pointer location */
3404                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3405                                                                   bufsz, buf);
3406                         if (status) {
3407                                 DEBUGOUT("Failed to read EEPROM image\n");
3408                                 return status;
3409                         }
3410                 }
3411                 *csum += local_buffer[i];
3412         }
3413         return IXGBE_SUCCESS;
3414 }
3415
3416 /**
3417  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3418  *  @hw: pointer to hardware structure
3419  *  @buffer: pointer to buffer containing calculated checksum
3420  *  @buffer_size: size of buffer
3421  *
3422  *  Returns a negative error code on error, or the 16-bit checksum
3423  **/
3424 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3425 {
3426         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3427         u16 *local_buffer;
3428         s32 status;
3429         u16 checksum = 0;
3430         u16 pointer, i, size;
3431
3432         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3433
3434         hw->eeprom.ops.init_params(hw);
3435
3436         if (!buffer) {
3437                 /* Read pointer area */
3438                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3439                                                      IXGBE_EEPROM_LAST_WORD + 1,
3440                                                      eeprom_ptrs);
3441                 if (status) {
3442                         DEBUGOUT("Failed to read EEPROM image\n");
3443                         return status;
3444                 }
3445                 local_buffer = eeprom_ptrs;
3446         } else {
3447                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3448                         return IXGBE_ERR_PARAM;
3449                 local_buffer = buffer;
3450         }
3451
3452         /*
3453          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3454          * checksum word itself
3455          */
3456         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3457                 if (i != IXGBE_EEPROM_CHECKSUM)
3458                         checksum += local_buffer[i];
3459
3460         /*
3461          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3462          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3463          */
3464         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3465                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3466                         continue;
3467
3468                 pointer = local_buffer[i];
3469
3470                 /* Skip pointer section if the pointer is invalid. */
3471                 if (pointer == 0xFFFF || pointer == 0 ||
3472                     pointer >= hw->eeprom.word_size)
3473                         continue;
3474
3475                 switch (i) {
3476                 case IXGBE_PCIE_GENERAL_PTR:
3477                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3478                         break;
3479                 case IXGBE_PCIE_CONFIG0_PTR:
3480                 case IXGBE_PCIE_CONFIG1_PTR:
3481                         size = IXGBE_PCIE_CONFIG_SIZE;
3482                         break;
3483                 default:
3484                         size = 0;
3485                         break;
3486                 }
3487
3488                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3489                                                 buffer, buffer_size);
3490                 if (status)
3491                         return status;
3492         }
3493
3494         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3495
3496         return (s32)checksum;
3497 }
3498
3499 /**
3500  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3501  *  @hw: pointer to hardware structure
3502  *
3503  *  Returns a negative error code on error, or the 16-bit checksum
3504  **/
3505 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3506 {
3507         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3508 }
3509
3510 /**
3511  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3512  *  @hw: pointer to hardware structure
3513  *  @checksum_val: calculated checksum
3514  *
3515  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3516  *  caller does not need checksum_val, the value can be NULL.
3517  **/
3518 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3519 {
3520         s32 status;
3521         u16 checksum;
3522         u16 read_checksum = 0;
3523
3524         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3525
3526         /* Read the first word from the EEPROM. If this times out or fails, do
3527          * not continue or we could be in for a very long wait while every
3528          * EEPROM read fails
3529          */
3530         status = hw->eeprom.ops.read(hw, 0, &checksum);
3531         if (status) {
3532                 DEBUGOUT("EEPROM read failed\n");
3533                 return status;
3534         }
3535
3536         status = hw->eeprom.ops.calc_checksum(hw);
3537         if (status < 0)
3538                 return status;
3539
3540         checksum = (u16)(status & 0xffff);
3541
3542         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3543                                            &read_checksum);
3544         if (status)
3545                 return status;
3546
3547         /* Verify read checksum from EEPROM is the same as
3548          * calculated checksum
3549          */
3550         if (read_checksum != checksum) {
3551                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3552                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3553                              "Invalid EEPROM checksum");
3554         }
3555
3556         /* If the user cares, return the calculated checksum */
3557         if (checksum_val)
3558                 *checksum_val = checksum;
3559
3560         return status;
3561 }
3562
3563 /**
3564  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3565  * @hw: pointer to hardware structure
3566  *
3567  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3568  * checksum and updates the EEPROM and instructs the hardware to update
3569  * the flash.
3570  **/
3571 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3572 {
3573         s32 status;
3574         u16 checksum = 0;
3575
3576         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3577
3578         /* Read the first word from the EEPROM. If this times out or fails, do
3579          * not continue or we could be in for a very long wait while every
3580          * EEPROM read fails
3581          */
3582         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3583         if (status) {
3584                 DEBUGOUT("EEPROM read failed\n");
3585                 return status;
3586         }
3587
3588         status = ixgbe_calc_eeprom_checksum_X550(hw);
3589         if (status < 0)
3590                 return status;
3591
3592         checksum = (u16)(status & 0xffff);
3593
3594         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3595                                             checksum);
3596         if (status)
3597                 return status;
3598
3599         status = ixgbe_update_flash_X550(hw);
3600
3601         return status;
3602 }
3603
3604 /**
3605  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3606  *  @hw: pointer to hardware structure
3607  *
3608  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3609  **/
3610 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3611 {
3612         s32 status = IXGBE_SUCCESS;
3613         union ixgbe_hic_hdr2 buffer;
3614
3615         DEBUGFUNC("ixgbe_update_flash_X550");
3616
3617         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3618         buffer.req.buf_lenh = 0;
3619         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3620         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3621
3622         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3623                                               sizeof(buffer),
3624                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3625
3626         return status;
3627 }
3628
3629 /**
3630  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3631  *  @hw: pointer to hardware structure
3632  *
3633  *  Determines physical layer capabilities of the current configuration.
3634  **/
3635 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3636 {
3637         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3638         u16 ext_ability = 0;
3639
3640         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3641
3642         hw->phy.ops.identify(hw);
3643
3644         switch (hw->phy.type) {
3645         case ixgbe_phy_x550em_kr:
3646                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3647                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3648                 break;
3649         case ixgbe_phy_x550em_kx4:
3650                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3651                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3652                 break;
3653         case ixgbe_phy_x550em_ext_t:
3654                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3655                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3656                                      &ext_ability);
3657                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3658                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3659                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3660                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3661                 break;
3662         default:
3663                 break;
3664         }
3665
3666         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3667                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3668
3669         return physical_layer;
3670 }
3671
3672 /**
3673  * ixgbe_get_bus_info_x550em - Set PCI bus info
3674  * @hw: pointer to hardware structure
3675  *
3676  * Sets bus link width and speed to unknown because X550em is
3677  * not a PCI device.
3678  **/
3679 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3680 {
3681
3682         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3683
3684         hw->bus.width = ixgbe_bus_width_unknown;
3685         hw->bus.speed = ixgbe_bus_speed_unknown;
3686
3687         hw->mac.ops.set_lan_id(hw);
3688
3689         return IXGBE_SUCCESS;
3690 }
3691
3692 /**
3693  * ixgbe_disable_rx_x550 - Disable RX unit
3694  *
3695  * Enables the Rx DMA unit for x550
3696  **/
3697 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3698 {
3699         u32 rxctrl, pfdtxgswc;
3700         s32 status;
3701         struct ixgbe_hic_disable_rxen fw_cmd;
3702
3703         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3704
3705         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3706         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3707                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3708                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3709                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3710                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3711                         hw->mac.set_lben = true;
3712                 } else {
3713                         hw->mac.set_lben = false;
3714                 }
3715
3716                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3717                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3718                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3719                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3720
3721                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3722                                         sizeof(struct ixgbe_hic_disable_rxen),
3723                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3724
3725                 /* If we fail - disable RX using register write */
3726                 if (status) {
3727                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3728                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3729                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3730                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3731                         }
3732                 }
3733         }
3734 }
3735
3736 /**
3737  * ixgbe_enter_lplu_x550em - Transition to low power states
3738  *  @hw: pointer to hardware structure
3739  *
3740  * Configures Low Power Link Up on transition to low power states
3741  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3742  * X557 PHY immediately prior to entering LPLU.
3743  **/
3744 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3745 {
3746         u16 an_10g_cntl_reg, autoneg_reg, speed;
3747         s32 status;
3748         ixgbe_link_speed lcd_speed;
3749         u32 save_autoneg;
3750         bool link_up;
3751
3752         /* SW LPLU not required on later HW revisions. */
3753         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3754             (IXGBE_FUSES0_REV_MASK &
3755              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3756                 return IXGBE_SUCCESS;
3757
3758         /* If blocked by MNG FW, then don't restart AN */
3759         if (ixgbe_check_reset_blocked(hw))
3760                 return IXGBE_SUCCESS;
3761
3762         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3763         if (status != IXGBE_SUCCESS)
3764                 return status;
3765
3766         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3767
3768         if (status != IXGBE_SUCCESS)
3769                 return status;
3770
3771         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3772          * disabled, then force link down by entering low power mode.
3773          */
3774         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3775             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3776                 return ixgbe_set_copper_phy_power(hw, FALSE);
3777
3778         /* Determine LCD */
3779         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3780
3781         if (status != IXGBE_SUCCESS)
3782                 return status;
3783
3784         /* If no valid LCD link speed, then force link down and exit. */
3785         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3786                 return ixgbe_set_copper_phy_power(hw, FALSE);
3787
3788         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3789                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3790                                       &speed);
3791
3792         if (status != IXGBE_SUCCESS)
3793                 return status;
3794
3795         /* If no link now, speed is invalid so take link down */
3796         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3797         if (status != IXGBE_SUCCESS)
3798                 return ixgbe_set_copper_phy_power(hw, false);
3799
3800         /* clear everything but the speed bits */
3801         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3802
3803         /* If current speed is already LCD, then exit. */
3804         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3805              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3806             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3807              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3808                 return status;
3809
3810         /* Clear AN completed indication */
3811         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3812                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3813                                       &autoneg_reg);
3814
3815         if (status != IXGBE_SUCCESS)
3816                 return status;
3817
3818         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3819                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3820                              &an_10g_cntl_reg);
3821
3822         if (status != IXGBE_SUCCESS)
3823                 return status;
3824
3825         status = hw->phy.ops.read_reg(hw,
3826                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3827                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3828                              &autoneg_reg);
3829
3830         if (status != IXGBE_SUCCESS)
3831                 return status;
3832
3833         save_autoneg = hw->phy.autoneg_advertised;
3834
3835         /* Setup link at least common link speed */
3836         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3837
3838         /* restore autoneg from before setting lplu speed */
3839         hw->phy.autoneg_advertised = save_autoneg;
3840
3841         return status;
3842 }
3843
3844 /**
3845  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3846  *  @hw: pointer to hardware structure
3847  *  @lcd_speed: pointer to lowest common link speed
3848  *
3849  * Determine lowest common link speed with link partner.
3850  **/
3851 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3852 {
3853         u16 an_lp_status;
3854         s32 status;
3855         u16 word = hw->eeprom.ctrl_word_3;
3856
3857         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3858
3859         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3860                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3861                                       &an_lp_status);
3862
3863         if (status != IXGBE_SUCCESS)
3864                 return status;
3865
3866         /* If link partner advertised 1G, return 1G */
3867         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3868                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3869                 return status;
3870         }
3871
3872         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3873         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3874             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3875                 return status;
3876
3877         /* Link partner not capable of lower speeds, return 10G */
3878         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3879         return status;
3880 }
3881
3882 /**
3883  *  ixgbe_setup_fc_X550em - Set up flow control
3884  *  @hw: pointer to hardware structure
3885  *
3886  *  Called at init time to set up flow control.
3887  **/
3888 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3889 {
3890         s32 ret_val = IXGBE_SUCCESS;
3891         u32 pause, asm_dir, reg_val;
3892
3893         DEBUGFUNC("ixgbe_setup_fc_X550em");
3894
3895         /* Validate the requested mode */
3896         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3897                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3898                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3899                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3900                 goto out;
3901         }
3902
3903         /* 10gig parts do not have a word in the EEPROM to determine the
3904          * default flow control setting, so we explicitly set it to full.
3905          */
3906         if (hw->fc.requested_mode == ixgbe_fc_default)
3907                 hw->fc.requested_mode = ixgbe_fc_full;
3908
3909         /* Determine PAUSE and ASM_DIR bits. */
3910         switch (hw->fc.requested_mode) {
3911         case ixgbe_fc_none:
3912                 pause = 0;
3913                 asm_dir = 0;
3914                 break;
3915         case ixgbe_fc_tx_pause:
3916                 pause = 0;
3917                 asm_dir = 1;
3918                 break;
3919         case ixgbe_fc_rx_pause:
3920                 /* Rx Flow control is enabled and Tx Flow control is
3921                  * disabled by software override. Since there really
3922                  * isn't a way to advertise that we are capable of RX
3923                  * Pause ONLY, we will advertise that we support both
3924                  * symmetric and asymmetric Rx PAUSE, as such we fall
3925                  * through to the fc_full statement.  Later, we will
3926                  * disable the adapter's ability to send PAUSE frames.
3927                  */
3928         case ixgbe_fc_full:
3929                 pause = 1;
3930                 asm_dir = 1;
3931                 break;
3932         default:
3933                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3934                         "Flow control param set incorrectly\n");
3935                 ret_val = IXGBE_ERR_CONFIG;
3936                 goto out;
3937         }
3938
3939         switch (hw->device_id) {
3940         case IXGBE_DEV_ID_X550EM_X_KR:
3941         case IXGBE_DEV_ID_X550EM_A_KR:
3942         case IXGBE_DEV_ID_X550EM_A_KR_L:
3943                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3944                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3945                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3946                 if (ret_val != IXGBE_SUCCESS)
3947                         goto out;
3948                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3949                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3950                 if (pause)
3951                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3952                 if (asm_dir)
3953                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3954                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3955                                        IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3956                                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3957
3958                 /* This device does not fully support AN. */
3959                 hw->fc.disable_fc_autoneg = true;
3960                 break;
3961         default:
3962                 break;
3963         }
3964
3965 out:
3966         return ret_val;
3967 }
3968
3969 /**
3970  *  ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
3971  *  @hw: pointer to hardware structure
3972  *
3973  *  Enable flow control according to IEEE clause 37.
3974  **/
3975 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
3976 {
3977         u32 link_s1, lp_an_page_low, an_cntl_1;
3978         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3979         ixgbe_link_speed speed;
3980         bool link_up;
3981
3982         /* AN should have completed when the cable was plugged in.
3983          * Look for reasons to bail out.  Bail out if:
3984          * - FC autoneg is disabled, or if
3985          * - link is not up.
3986          */
3987         if (hw->fc.disable_fc_autoneg) {
3988                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3989                               "Flow control autoneg is disabled");
3990                 goto out;
3991         }
3992
3993         hw->mac.ops.check_link(hw, &speed, &link_up, false);
3994         if (!link_up) {
3995                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3996                 goto out;
3997         }
3998
3999         /* Check at auto-negotiation has completed */
4000         status = hw->mac.ops.read_iosf_sb_reg(hw,
4001                                       IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4002                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4003
4004         if (status != IXGBE_SUCCESS ||
4005             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4006                 DEBUGOUT("Auto-Negotiation did not complete\n");
4007                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4008                 goto out;
4009         }
4010
4011         /* Read the 10g AN autoc and LP ability registers and resolve
4012          * local flow control settings accordingly
4013          */
4014         status = hw->mac.ops.read_iosf_sb_reg(hw,
4015                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4016                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4017
4018         if (status != IXGBE_SUCCESS) {
4019                 DEBUGOUT("Auto-Negotiation did not complete\n");
4020                 goto out;
4021         }
4022
4023         status = hw->mac.ops.read_iosf_sb_reg(hw,
4024                               IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4025                               IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4026
4027         if (status != IXGBE_SUCCESS) {
4028                 DEBUGOUT("Auto-Negotiation did not complete\n");
4029                 goto out;
4030         }
4031
4032         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4033                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4034                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4035                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4036                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4037
4038 out:
4039         if (status == IXGBE_SUCCESS) {
4040                 hw->fc.fc_was_autonegged = true;
4041         } else {
4042                 hw->fc.fc_was_autonegged = false;
4043                 hw->fc.current_mode = hw->fc.requested_mode;
4044         }
4045 }
4046
4047 /**
4048  *  ixgbe_fc_autoneg_fiber_x550em_a - Enable flow control IEEE clause 37
4049  *  @hw: pointer to hardware structure
4050  *
4051  *  Enable flow control according to IEEE clause 37.
4052  **/
4053 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4054 {
4055         u32 link_s1, pcs_an_lp, pcs_an;
4056         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4057         ixgbe_link_speed speed;
4058         bool link_up;
4059
4060         /* AN should have completed when the cable was plugged in.
4061          * Look for reasons to bail out.  Bail out if:
4062          * - FC autoneg is disabled, or if
4063          * - link is not up.
4064          */
4065         if (hw->fc.disable_fc_autoneg) {
4066                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4067                              "Flow control autoneg is disabled");
4068                 goto out;
4069         }
4070
4071         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4072         if (!link_up) {
4073                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4074                 goto out;
4075         }
4076
4077         /* Check if auto-negotiation has completed */
4078         status = hw->mac.ops.read_iosf_sb_reg(hw,
4079                                          IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4080                                          IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4081
4082         if (status != IXGBE_SUCCESS ||
4083             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4084                 DEBUGOUT("Auto-Negotiation did not complete\n");
4085                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4086                 goto out;
4087         }
4088
4089         /* Determine advertised flow control */
4090         status = hw->mac.ops.read_iosf_sb_reg(hw,
4091                                           IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4092                                           IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an);
4093
4094         if (status != IXGBE_SUCCESS) {
4095                 DEBUGOUT("Auto-Negotiation did not complete\n");
4096                 goto out;
4097         }
4098
4099         /* Determine link parter flow control */
4100         status = hw->mac.ops.read_iosf_sb_reg(hw,
4101                                   IXGBE_KRM_PCS_KX_AN_LP(hw->bus.lan_id),
4102                                   IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an_lp);
4103
4104         if (status != IXGBE_SUCCESS) {
4105                 DEBUGOUT("Auto-Negotiation did not complete\n");
4106                 goto out;
4107         }
4108
4109         status = ixgbe_negotiate_fc(hw, pcs_an, pcs_an_lp,
4110                                     IXGBE_KRM_PCS_KX_AN_SYM_PAUSE,
4111                                     IXGBE_KRM_PCS_KX_AN_ASM_PAUSE,
4112                                     IXGBE_KRM_PCS_KX_AN_LP_SYM_PAUSE,
4113                                     IXGBE_KRM_PCS_KX_AN_LP_ASM_PAUSE);
4114
4115 out:
4116         if (status == IXGBE_SUCCESS) {
4117                 hw->fc.fc_was_autonegged = true;
4118         } else {
4119                 hw->fc.fc_was_autonegged = false;
4120                 hw->fc.current_mode = hw->fc.requested_mode;
4121         }
4122 }
4123
4124 /**
4125  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4126  *  @hw: pointer to hardware structure
4127  *
4128  *  Called at init time to set up flow control.
4129  **/
4130 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4131 {
4132         s32 status = IXGBE_SUCCESS;
4133         u32 an_cntl, link_ctrl = 0;
4134
4135         DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4136
4137         /* Validate the requested mode */
4138         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4139                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4140                       "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4141                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4142         }
4143
4144         if (hw->fc.requested_mode == ixgbe_fc_default)
4145                 hw->fc.requested_mode = ixgbe_fc_full;
4146
4147         /* Set up the 1G and 10G flow control advertisement registers so the
4148          * HW will be able to do FC autoneg once the cable is plugged in.  If
4149          * we link at 10G, the 1G advertisement is harmless and vice versa.
4150          */
4151         status = hw->mac.ops.read_iosf_sb_reg(hw,
4152                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4153                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4154
4155         if (status != IXGBE_SUCCESS) {
4156                 DEBUGOUT("Auto-Negotiation did not complete\n");
4157                 return status;
4158         }
4159
4160         /* The possible values of fc.requested_mode are:
4161          * 0: Flow control is completely disabled
4162          * 1: Rx flow control is enabled (we can receive pause frames,
4163          *    but not send pause frames).
4164          * 2: Tx flow control is enabled (we can send pause frames but
4165          *    we do not support receiving pause frames).
4166          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4167          * other: Invalid.
4168          */
4169         switch (hw->fc.requested_mode) {
4170         case ixgbe_fc_none:
4171                 /* Flow control completely disabled by software override. */
4172                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4173                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4174                 break;
4175         case ixgbe_fc_tx_pause:
4176                 /* Tx Flow control is enabled, and Rx Flow control is
4177                  * disabled by software override.
4178                  */
4179                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4180                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4181                 break;
4182         case ixgbe_fc_rx_pause:
4183                 /* Rx Flow control is enabled and Tx Flow control is
4184                  * disabled by software override. Since there really
4185                  * isn't a way to advertise that we are capable of RX
4186                  * Pause ONLY, we will advertise that we support both
4187                  * symmetric and asymmetric Rx PAUSE, as such we fall
4188                  * through to the fc_full statement.  Later, we will
4189                  * disable the adapter's ability to send PAUSE frames.
4190                  */
4191         case ixgbe_fc_full:
4192                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4193                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4194                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4195                 break;
4196         default:
4197                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4198                               "Flow control param set incorrectly\n");
4199                 return IXGBE_ERR_CONFIG;
4200         }
4201
4202         status = hw->mac.ops.write_iosf_sb_reg(hw,
4203                                        IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4204                                        IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4205
4206         /* Restart auto-negotiation. */
4207         status = hw->mac.ops.read_iosf_sb_reg(hw,
4208                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4209                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
4210
4211         if (status != IXGBE_SUCCESS) {
4212                 DEBUGOUT("Auto-Negotiation did not complete\n");
4213                 return status;
4214         }
4215
4216         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
4217         status = hw->mac.ops.write_iosf_sb_reg(hw,
4218                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4219                                        IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
4220
4221         return status;
4222 }
4223
4224 /**
4225  *  ixgbe_setup_fc_fiber_x550em_a - Set up flow control
4226  *  @hw: pointer to hardware structure
4227  *
4228  *  Called at init time to set up flow control.
4229  **/
4230 s32 ixgbe_setup_fc_fiber_x550em_a(struct ixgbe_hw *hw)
4231 {
4232         struct ixgbe_mac_info *mac = &hw->mac;
4233         s32 rc = IXGBE_SUCCESS;
4234         u32 an_cntl4, lctrl, pcs_an;
4235
4236         DEBUGFUNC("ixgbe_setup_fc_fiber_x550em_a");
4237
4238         /* Validate the requested mode */
4239         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4240                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4241                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4242                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4243         }
4244
4245         /* Enable clause 37 auto-negotiation in KRM_LINK_CTRL_1 */
4246         if (hw->fc.requested_mode == ixgbe_fc_default)
4247                 hw->fc.requested_mode = ixgbe_fc_full;
4248
4249         rc = mac->ops.read_iosf_sb_reg(hw,
4250                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4251                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lctrl);
4252         if (rc)
4253                 return rc;
4254
4255         lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
4256         lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
4257
4258         rc = mac->ops.write_iosf_sb_reg(hw,
4259                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4260                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lctrl);
4261         if (rc)
4262                 return rc;
4263
4264         /* Enable clause 37 over 73 in KRM_AN_CNTL_4 */
4265         rc = mac->ops.read_iosf_sb_reg(hw,
4266                                        IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
4267                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl4);
4268         if (rc)
4269                 return rc;
4270
4271         an_cntl4 |= IXGBE_KRM_AN_CNTL_4_ECSR_AN37_OVER_73;
4272
4273         rc = mac->ops.write_iosf_sb_reg(hw,
4274                                         IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
4275                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl4);
4276         if (rc)
4277                 return rc;
4278
4279         rc = hw->mac.ops.read_iosf_sb_reg(hw,
4280                                           IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4281                                           IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an);
4282
4283         if (rc)
4284                 return rc;
4285
4286         /* The possible values of fc.requested_mode are:
4287          * 0: Flow control is completely disabled
4288          * 1: Rx flow control is enabled (we can receive pause frames,
4289          *    but not send pause frames).
4290          * 2: Tx flow control is enabled (we can send pause frames but
4291          *    we do not support receiving pause frames).
4292          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4293          * other: Invalid.
4294          */
4295         switch (hw->fc.requested_mode) {
4296         case ixgbe_fc_none:
4297                 /* Flow control completely disabled by software override. */
4298                 pcs_an &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4299                             IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4300                 break;
4301         case ixgbe_fc_tx_pause:
4302                 /* Tx Flow control is enabled, and Rx Flow control is
4303                  * disabled by software override.
4304                  */
4305                 pcs_an |= IXGBE_KRM_PCS_KX_AN_ASM_PAUSE;
4306                 pcs_an &= ~IXGBE_KRM_PCS_KX_AN_SYM_PAUSE;
4307                 break;
4308         case ixgbe_fc_rx_pause:
4309                 /* Rx Flow control is enabled and Tx Flow control is
4310                  * disabled by software override. Since there really
4311                  * isn't a way to advertise that we are capable of RX
4312                  * Pause ONLY, we will advertise that we support both
4313                  * symmetric and asymmetric Rx PAUSE, as such we fall
4314                  * through to the fc_full statement.  Later, we will
4315                  * disable the adapter's ability to send PAUSE frames.
4316                  */
4317         case ixgbe_fc_full:
4318                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4319                 pcs_an |= IXGBE_KRM_PCS_KX_AN_SYM_PAUSE |
4320                            IXGBE_KRM_PCS_KX_AN_ASM_PAUSE;
4321                 break;
4322         default:
4323                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4324                               "Flow control param set incorrectly\n");
4325                 return IXGBE_ERR_CONFIG;
4326         }
4327
4328         rc = hw->mac.ops.write_iosf_sb_reg(hw,
4329                                            IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4330                                            IXGBE_SB_IOSF_TARGET_KR_PHY, pcs_an);
4331
4332         /* Restart auto-negotiation. */
4333         rc = hw->mac.ops.read_iosf_sb_reg(hw,
4334                                           IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4335                                           IXGBE_SB_IOSF_TARGET_KR_PHY, &lctrl);
4336
4337         if (rc) {
4338                 DEBUGOUT("Auto-Negotiation did not complete\n");
4339                 return rc;
4340         }
4341
4342         lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
4343         rc = hw->mac.ops.write_iosf_sb_reg(hw,
4344                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4345                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lctrl);
4346
4347         return rc;
4348 }
4349
4350 /**
4351  * ixgbe_set_mux - Set mux for port 1 access with CS4227
4352  * @hw: pointer to hardware structure
4353  * @state: set mux if 1, clear if 0
4354  */
4355 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4356 {
4357         u32 esdp;
4358
4359         if (!hw->bus.lan_id)
4360                 return;
4361         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4362         if (state)
4363                 esdp |= IXGBE_ESDP_SDP1;
4364         else
4365                 esdp &= ~IXGBE_ESDP_SDP1;
4366         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4367         IXGBE_WRITE_FLUSH(hw);
4368 }
4369
4370 /**
4371  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4372  *  @hw: pointer to hardware structure
4373  *  @mask: Mask to specify which semaphore to acquire
4374  *
4375  *  Acquires the SWFW semaphore and sets the I2C MUX
4376  **/
4377 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4378 {
4379         s32 status;
4380
4381         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4382
4383         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4384         if (status)
4385                 return status;
4386
4387         if (mask & IXGBE_GSSR_I2C_MASK)
4388                 ixgbe_set_mux(hw, 1);
4389
4390         return IXGBE_SUCCESS;
4391 }
4392
4393 /**
4394  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4395  *  @hw: pointer to hardware structure
4396  *  @mask: Mask to specify which semaphore to release
4397  *
4398  *  Releases the SWFW semaphore and sets the I2C MUX
4399  **/
4400 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4401 {
4402         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4403
4404         if (mask & IXGBE_GSSR_I2C_MASK)
4405                 ixgbe_set_mux(hw, 0);
4406
4407         ixgbe_release_swfw_sync_X540(hw, mask);
4408 }
4409
4410 /**
4411  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4412  *  @hw: pointer to hardware structure
4413  *  @mask: Mask to specify which semaphore to acquire
4414  *
4415  *  Acquires the SWFW semaphore and get the shared phy token as needed
4416  */
4417 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4418 {
4419         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4420         int retries = FW_PHY_TOKEN_RETRIES;
4421         s32 status = IXGBE_SUCCESS;
4422
4423         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4424
4425         while (--retries) {
4426                 status = IXGBE_SUCCESS;
4427                 if (hmask)
4428                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4429                 if (status)
4430                         return status;
4431                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4432                         return IXGBE_SUCCESS;
4433
4434                 status = ixgbe_get_phy_token(hw);
4435                 if (status == IXGBE_SUCCESS)
4436                         return IXGBE_SUCCESS;
4437
4438                 if (hmask)
4439                         ixgbe_release_swfw_sync_X540(hw, hmask);
4440                 if (status != IXGBE_ERR_TOKEN_RETRY)
4441                         return status;
4442                 msec_delay(FW_PHY_TOKEN_DELAY);
4443         }
4444
4445         return status;
4446 }
4447
4448 /**
4449  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4450  *  @hw: pointer to hardware structure
4451  *  @mask: Mask to specify which semaphore to release
4452  *
4453  *  Releases the SWFW semaphore and puts the shared phy token as needed
4454  */
4455 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4456 {
4457         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4458
4459         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4460
4461         if (mask & IXGBE_GSSR_TOKEN_SM)
4462                 ixgbe_put_phy_token(hw);
4463
4464         if (hmask)
4465                 ixgbe_release_swfw_sync_X540(hw, hmask);
4466 }
4467
4468 /**
4469  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4470  *  @hw: pointer to hardware structure
4471  *  @reg_addr: 32 bit address of PHY register to read
4472  *  @phy_data: Pointer to read data from PHY register
4473  *
4474  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4475  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4476  *  instances.
4477  **/
4478 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4479                              u32 device_type, u16 *phy_data)
4480 {
4481         s32 status;
4482         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4483
4484         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4485
4486         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4487                 return IXGBE_ERR_SWFW_SYNC;
4488
4489         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4490
4491         hw->mac.ops.release_swfw_sync(hw, mask);
4492
4493         return status;
4494 }
4495
4496 /**
4497  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4498  *  @hw: pointer to hardware structure
4499  *  @reg_addr: 32 bit PHY register to write
4500  *  @device_type: 5 bit device type
4501  *  @phy_data: Data to write to the PHY register
4502  *
4503  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4504  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4505  **/
4506 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4507                               u32 device_type, u16 phy_data)
4508 {
4509         s32 status;
4510         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4511
4512         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4513
4514         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4515                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4516                                                  phy_data);
4517                 hw->mac.ops.release_swfw_sync(hw, mask);
4518         } else {
4519                 status = IXGBE_ERR_SWFW_SYNC;
4520         }
4521
4522         return status;
4523 }
4524
4525 /**
4526  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4527  * @hw: pointer to hardware structure
4528  *
4529  * Handle external Base T PHY interrupt. If high temperature
4530  * failure alarm then return error, else if link status change
4531  * then setup internal/external PHY link
4532  *
4533  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4534  * failure alarm, else return PHY access status.
4535  */
4536 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4537 {
4538         bool lsc;
4539         u32 status;
4540
4541         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4542
4543         if (status != IXGBE_SUCCESS)
4544                 return status;
4545
4546         if (lsc)
4547                 return ixgbe_setup_internal_phy(hw);
4548
4549         return IXGBE_SUCCESS;
4550 }
4551
4552 /**
4553  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4554  * @hw: pointer to hardware structure
4555  * @speed: new link speed
4556  * @autoneg_wait_to_complete: true when waiting for completion is needed
4557  *
4558  * Setup internal/external PHY link speed based on link speed, then set
4559  * external PHY auto advertised link speed.
4560  *
4561  * Returns error status for any failure
4562  **/
4563 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4564                                   ixgbe_link_speed speed,
4565                                   bool autoneg_wait_to_complete)
4566 {
4567         s32 status;
4568         ixgbe_link_speed force_speed;
4569
4570         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4571
4572         /* Setup internal/external PHY link speed to iXFI (10G), unless
4573          * only 1G is auto advertised then setup KX link.
4574          */
4575         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4576                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4577         else
4578                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4579
4580         /* If internal link mode is XFI, then setup XFI internal link. */
4581         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4582                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4583
4584                 if (status != IXGBE_SUCCESS)
4585                         return status;
4586         }
4587
4588         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4589 }
4590
4591 /**
4592  * ixgbe_check_link_t_X550em - Determine link and speed status
4593  * @hw: pointer to hardware structure
4594  * @speed: pointer to link speed
4595  * @link_up: true when link is up
4596  * @link_up_wait_to_complete: bool used to wait for link up or not
4597  *
4598  * Check that both the MAC and X557 external PHY have link.
4599  **/
4600 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4601                               bool *link_up, bool link_up_wait_to_complete)
4602 {
4603         u32 status;
4604         u16 autoneg_status;
4605
4606         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4607                 return IXGBE_ERR_CONFIG;
4608
4609         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4610                                               link_up_wait_to_complete);
4611
4612         /* If check link fails or MAC link is not up, then return */
4613         if (status != IXGBE_SUCCESS || !(*link_up))
4614                 return status;
4615
4616         /* MAC link is up, so check external PHY link.
4617          * Read this twice back to back to indicate current status.
4618          */
4619         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4620                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4621                                       &autoneg_status);
4622
4623         if (status != IXGBE_SUCCESS)
4624                 return status;
4625
4626         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4627                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4628                                       &autoneg_status);
4629
4630         if (status != IXGBE_SUCCESS)
4631                 return status;
4632
4633         /* If external PHY link is not up, then indicate link not up */
4634         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4635                 *link_up = false;
4636
4637         return IXGBE_SUCCESS;
4638 }
4639
4640 /**
4641  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4642  *  @hw: pointer to hardware structure
4643  **/
4644 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4645 {
4646         s32 status;
4647
4648         status = ixgbe_reset_phy_generic(hw);
4649
4650         if (status != IXGBE_SUCCESS)
4651                 return status;
4652
4653         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4654         return ixgbe_enable_lasi_ext_t_x550em(hw);
4655 }
4656
4657 /**
4658  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4659  *  @hw: pointer to hardware structure
4660  *  @led_idx: led number to turn on
4661  **/
4662 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4663 {
4664         u16 phy_data;
4665
4666         DEBUGFUNC("ixgbe_led_on_t_X550em");
4667
4668         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4669                 return IXGBE_ERR_PARAM;
4670
4671         /* To turn on the LED, set mode to ON. */
4672         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4673                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4674         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4675         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4676                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4677
4678         return IXGBE_SUCCESS;
4679 }
4680
4681 /**
4682  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4683  *  @hw: pointer to hardware structure
4684  *  @led_idx: led number to turn off
4685  **/
4686 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4687 {
4688         u16 phy_data;
4689
4690         DEBUGFUNC("ixgbe_led_off_t_X550em");
4691
4692         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4693                 return IXGBE_ERR_PARAM;
4694
4695         /* To turn on the LED, set mode to ON. */
4696         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4697                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4698         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4699         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4700                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4701
4702         return IXGBE_SUCCESS;
4703 }
4704