drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41
  42 /**
  43  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  44  *  @hw: pointer to hardware structure
  45  *
  46  *  Initialize the function pointers and assign the MAC type for X550.
  47  *  Does not touch the hardware.
  48  **/
  49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  50 {
  51         struct ixgbe_mac_info *mac = &hw->mac;
  52         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  53         s32 ret_val;
  54
  55         DEBUGFUNC("ixgbe_init_ops_X550");
  56
  57         ret_val = ixgbe_init_ops_X540(hw);
  58         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  59         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  60         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  61         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  62         mac->ops.set_source_address_pruning =
  63                         ixgbe_set_source_address_pruning_X550;
  64         mac->ops.set_ethertype_anti_spoofing =
  65                         ixgbe_set_ethertype_anti_spoofing_X550;
  66
  67         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  68         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  69         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  70         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  71         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  72         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  73         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  74         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  75         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  76
  77         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  78         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  79         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  80         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  81         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  82         return ret_val;
  83 }
  84
  85 /**
  86  * ixgbe_read_cs4227 - Read CS4227 register
  87  * @hw: pointer to hardware structure
  88  * @reg: register number to write
  89  * @value: pointer to receive value read
  90  *
  91  * Returns status code
  92  **/
  93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  94 {
  95         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
  96 }
  97
  98 /**
  99  * ixgbe_write_cs4227 - Write CS4227 register
 100  * @hw: pointer to hardware structure
 101  * @reg: register number to write
 102  * @value: value to write to register
 103  *
 104  * Returns status code
 105  **/
 106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 107 {
 108         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 109 }
 110
 111 /**
 112  * ixgbe_get_cs4227_status - Return CS4227 status
 113  * @hw: pointer to hardware structure
 114  *
 115  * Returns error if CS4227 not successfully initialized
 116  **/
 117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
 118 {
 119         s32 status;
 120         u16 value = 0;
 121         u8 retry;
 122
 123         for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
 124                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
 125                                            &value);
 126                 if (status != IXGBE_SUCCESS)
 127                         return status;
 128                 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
 129                         break;
 130                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 131         }
 132         if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
 133                 return IXGBE_ERR_PHY;
 134
 135         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 136                                     IXGBE_CS4227_SCRATCH_VALUE);
 137         if (status != IXGBE_SUCCESS)
 138                 return status;
 139         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 140         if (status != IXGBE_SUCCESS)
 141                 return status;
 142         if (value != IXGBE_CS4227_SCRATCH_VALUE)
 143                 return IXGBE_ERR_PHY;
 144         return IXGBE_SUCCESS;
 145 }
 146
 147 /**
 148  * ixgbe_read_pe - Read register from port expander
 149  * @hw: pointer to hardware structure
 150  * @reg: register number to read
 151  * @value: pointer to receive read value
 152  *
 153  * Returns status code
 154  **/
 155 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 156 {
 157         s32 status;
 158
 159         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 160         if (status != IXGBE_SUCCESS)
 161                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 162                               "port expander access failed with %d\n", status);
 163         return status;
 164 }
 165
 166 /**
 167  * ixgbe_write_pe - Write register to port expander
 168  * @hw: pointer to hardware structure
 169  * @reg: register number to write
 170  * @value: value to write
 171  *
 172  * Returns status code
 173  **/
 174 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 175 {
 176         s32 status;
 177
 178         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 179         if (status != IXGBE_SUCCESS)
 180                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 181                               "port expander access failed with %d\n", status);
 182         return status;
 183 }
 184
 185 /**
 186  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 187  * @hw: pointer to hardware structure
 188  *
 189  * Returns error code
 190  **/
 191 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 192 {
 193         s32 status;
 194         u8 reg;
 195
 196         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199         reg |= IXGBE_PE_BIT1;
 200         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 201         if (status != IXGBE_SUCCESS)
 202                 return status;
 203
 204         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 205         if (status != IXGBE_SUCCESS)
 206                 return status;
 207         reg &= ~IXGBE_PE_BIT1;
 208         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 209         if (status != IXGBE_SUCCESS)
 210                 return status;
 211
 212         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 213         if (status != IXGBE_SUCCESS)
 214                 return status;
 215         reg &= ~IXGBE_PE_BIT1;
 216         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 217         if (status != IXGBE_SUCCESS)
 218                 return status;
 219
 220         usec_delay(IXGBE_CS4227_RESET_HOLD);
 221
 222         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 223         if (status != IXGBE_SUCCESS)
 224                 return status;
 225         reg |= IXGBE_PE_BIT1;
 226         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 227         if (status != IXGBE_SUCCESS)
 228                 return status;
 229
 230         msec_delay(IXGBE_CS4227_RESET_DELAY);
 231
 232         return IXGBE_SUCCESS;
 233 }
 234
 235 /**
 236  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 237  * @hw: pointer to hardware structure
 238  **/
 239 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 240 {
 241         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 242         s32 status;
 243         u8 retry;
 244
 245         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 246                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 247                 if (status != IXGBE_SUCCESS) {
 248                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 249                                       "semaphore failed with %d\n", status);
 250                         return;
 251                 }
 252                 status = ixgbe_get_cs4227_status(hw);
 253                 if (status == IXGBE_SUCCESS) {
 254                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 255                         msec_delay(hw->eeprom.semaphore_delay);
 256                         return;
 257                 }
 258                 ixgbe_reset_cs4227(hw);
 259                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 260                 msec_delay(hw->eeprom.semaphore_delay);
 261         }
 262         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 263                       "Unable to initialize CS4227, err=%d\n", status);
 264 }
 265
 266 /**
 267  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 268  * @hw: pointer to hardware structure
 269  **/
 270 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 271 {
 272         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 273
 274         if (hw->bus.lan_id) {
 275                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 276                 esdp |= IXGBE_ESDP_SDP1_DIR;
 277         }
 278         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 279         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 280         IXGBE_WRITE_FLUSH(hw);
 281 }
 282
 283 /**
 284  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 285  * @hw: pointer to hardware structure
 286  *
 287  * Returns error code
 288  */
 289 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 290 {
 291         switch (hw->device_id) {
 292         case IXGBE_DEV_ID_X550EM_X_SFP:
 293                 /* set up for CS4227 usage */
 294                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 295                 ixgbe_setup_mux_ctl(hw);
 296                 ixgbe_check_cs4227(hw);
 297
 298                 return ixgbe_identify_module_generic(hw);
 299                 break;
 300         case IXGBE_DEV_ID_X550EM_X_KX4:
 301                 hw->phy.type = ixgbe_phy_x550em_kx4;
 302                 break;
 303         case IXGBE_DEV_ID_X550EM_X_KR:
 304                 hw->phy.type = ixgbe_phy_x550em_kr;
 305                 break;
 306         case IXGBE_DEV_ID_X550EM_X_1G_T:
 307         case IXGBE_DEV_ID_X550EM_X_10G_T:
 308                 return ixgbe_identify_phy_generic(hw);
 309         default:
 310                 break;
 311         }
 312         return IXGBE_SUCCESS;
 313 }
 314
 315 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 316                                      u32 device_type, u16 *phy_data)
 317 {
 318         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 319         return IXGBE_NOT_IMPLEMENTED;
 320 }
 321
 322 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 323                                       u32 device_type, u16 phy_data)
 324 {
 325         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 326         return IXGBE_NOT_IMPLEMENTED;
 327 }
 328
 329 /**
 330 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 331 *  @hw: pointer to hardware structure
 332 *
 333 *  Initialize the function pointers and for MAC type X550EM.
 334 *  Does not touch the hardware.
 335 **/
 336 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 337 {
 338         struct ixgbe_mac_info *mac = &hw->mac;
 339         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 340         struct ixgbe_phy_info *phy = &hw->phy;
 341         s32 ret_val;
 342
 343         DEBUGFUNC("ixgbe_init_ops_X550EM");
 344
 345         /* Similar to X550 so start there. */
 346         ret_val = ixgbe_init_ops_X550(hw);
 347
 348         /* Since this function eventually calls
 349          * ixgbe_init_ops_540 by design, we are setting
 350          * the pointers to NULL explicitly here to overwrite
 351          * the values being set in the x540 function.
 352          */
 353         /* Thermal sensor not supported in x550EM */
 354         mac->ops.get_thermal_sensor_data = NULL;
 355         mac->ops.init_thermal_sensor_thresh = NULL;
 356         mac->thermal_sensor_enabled = false;
 357
 358         /* FCOE not supported in x550EM */
 359         mac->ops.get_san_mac_addr = NULL;
 360         mac->ops.set_san_mac_addr = NULL;
 361         mac->ops.get_wwn_prefix = NULL;
 362         mac->ops.get_fcoe_boot_status = NULL;
 363
 364         /* IPsec not supported in x550EM */
 365         mac->ops.disable_sec_rx_path = NULL;
 366         mac->ops.enable_sec_rx_path = NULL;
 367
 368         /* AUTOC register is not present in x550EM. */
 369         mac->ops.prot_autoc_read = NULL;
 370         mac->ops.prot_autoc_write = NULL;
 371
 372         /* X550EM bus type is internal*/
 373         hw->bus.type = ixgbe_bus_type_internal;
 374         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 375
 376         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 377         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 378         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 379         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 380         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 381         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 382         mac->ops.get_supported_physical_layer =
 383                                     ixgbe_get_supported_physical_layer_X550em;
 384
 385                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 386         /* PHY */
 387         phy->ops.init = ixgbe_init_phy_ops_X550em;
 388         phy->ops.identify = ixgbe_identify_phy_x550em;
 389         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 390                 phy->ops.set_phy_power = NULL;
 391
 392
 393         /* EEPROM */
 394         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 395         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 396         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 397         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 398         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 399         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 400         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 401         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 402
 403         return ret_val;
 404 }
 405
 406 /**
 407  *  ixgbe_dmac_config_X550
 408  *  @hw: pointer to hardware structure
 409  *
 410  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 411  *  When disabling dmac, dmac enable dmac bit is cleared.
 412  **/
 413 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 414 {
 415         u32 reg, high_pri_tc;
 416
 417         DEBUGFUNC("ixgbe_dmac_config_X550");
 418
 419         /* Disable DMA coalescing before configuring */
 420         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 421         reg &= ~IXGBE_DMACR_DMAC_EN;
 422         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 423
 424         /* Disable DMA Coalescing if the watchdog timer is 0 */
 425         if (!hw->mac.dmac_config.watchdog_timer)
 426                 goto out;
 427
 428         ixgbe_dmac_config_tcs_X550(hw);
 429
 430         /* Configure DMA Coalescing Control Register */
 431         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 432
 433         /* Set the watchdog timer in units of 40.96 usec */
 434         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 435         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 436
 437         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 438         /* If fcoe is enabled, set high priority traffic class */
 439         if (hw->mac.dmac_config.fcoe_en) {
 440                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 441                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 442                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 443         }
 444         reg |= IXGBE_DMACR_EN_MNG_IND;
 445
 446         /* Enable DMA coalescing after configuration */
 447         reg |= IXGBE_DMACR_DMAC_EN;
 448         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 449
 450 out:
 451         return IXGBE_SUCCESS;
 452 }
 453
 454 /**
 455  *  ixgbe_dmac_config_tcs_X550
 456  *  @hw: pointer to hardware structure
 457  *
 458  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 459  *  be cleared before configuring.
 460  **/
 461 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 462 {
 463         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 464
 465         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 466
 467         /* Configure DMA coalescing enabled */
 468         switch (hw->mac.dmac_config.link_speed) {
 469         case IXGBE_LINK_SPEED_100_FULL:
 470                 pb_headroom = IXGBE_DMACRXT_100M;
 471                 break;
 472         case IXGBE_LINK_SPEED_1GB_FULL:
 473                 pb_headroom = IXGBE_DMACRXT_1G;
 474                 break;
 475         default:
 476                 pb_headroom = IXGBE_DMACRXT_10G;
 477                 break;
 478         }
 479
 480         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 481                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 482
 483         /* Set the per Rx packet buffer receive threshold */
 484         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 485                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 486                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 487
 488                 if (tc < hw->mac.dmac_config.num_tcs) {
 489                         /* Get Rx PB size */
 490                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 491                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 492                                 IXGBE_RXPBSIZE_SHIFT;
 493
 494                         /* Calculate receive buffer threshold in kilobytes */
 495                         if (rx_pb_size > pb_headroom)
 496                                 rx_pb_size = rx_pb_size - pb_headroom;
 497                         else
 498                                 rx_pb_size = 0;
 499
 500                         /* Minimum of MFS shall be set for DMCTH */
 501                         reg |= (rx_pb_size > maxframe_size_kb) ?
 502                                 rx_pb_size : maxframe_size_kb;
 503                 }
 504                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 505         }
 506         return IXGBE_SUCCESS;
 507 }
 508
 509 /**
 510  *  ixgbe_dmac_update_tcs_X550
 511  *  @hw: pointer to hardware structure
 512  *
 513  *  Disables dmac, updates per TC settings, and then enables dmac.
 514  **/
 515 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 516 {
 517         u32 reg;
 518
 519         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 520
 521         /* Disable DMA coalescing before configuring */
 522         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 523         reg &= ~IXGBE_DMACR_DMAC_EN;
 524         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 525
 526         ixgbe_dmac_config_tcs_X550(hw);
 527
 528         /* Enable DMA coalescing after configuration */
 529         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 530         reg |= IXGBE_DMACR_DMAC_EN;
 531         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 532
 533         return IXGBE_SUCCESS;
 534 }
 535
 536 /**
 537  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 538  *  @hw: pointer to hardware structure
 539  *
 540  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 541  *  ixgbe_hw struct in order to set up EEPROM access.
 542  **/
 543 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 544 {
 545         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 546         u32 eec;
 547         u16 eeprom_size;
 548
 549         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 550
 551         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 552                 eeprom->semaphore_delay = 10;
 553                 eeprom->type = ixgbe_flash;
 554
 555                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 556                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 557                                     IXGBE_EEC_SIZE_SHIFT);
 558                 eeprom->word_size = 1 << (eeprom_size +
 559                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 560
 561                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 562                           eeprom->type, eeprom->word_size);
 563         }
 564
 565         return IXGBE_SUCCESS;
 566 }
 567
 568 /**
 569  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 570  *  @hw: pointer to the HW structure
 571  *  @enable_eee: boolean flag to enable EEE
 572  *
 573  *  Enable/disable EEE based on enable_eee flag.
 574  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 575  *  are modified.
 576  *
 577  **/
 578 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 579 {
 580         u32 eeer;
 581         u16 autoneg_eee_reg;
 582         u32 link_reg;
 583         s32 status;
 584
 585         DEBUGFUNC("ixgbe_setup_eee_X550");
 586
 587         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 588         /* Enable or disable EEE per flag */
 589         if (enable_eee) {
 590                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 591
 592                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 593                         /* Advertise EEE capability */
 594                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 595                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 596
 597                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 598                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 599                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 600
 601                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 602                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 603                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 604                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 605                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 606                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 607                         if (status != IXGBE_SUCCESS)
 608                                 return status;
 609
 610                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 611                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 612
 613                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 614                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 615                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 616                         if (status != IXGBE_SUCCESS)
 617                                 return status;
 618                 }
 619         } else {
 620                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 621
 622                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 623                         /* Disable advertised EEE capability */
 624                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 625                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 626
 627                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 628                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 629                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 630
 631                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 632                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 633                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 634                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 635                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 636                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 637                         if (status != IXGBE_SUCCESS)
 638                                 return status;
 639
 640                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 641                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 642
 643                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 644                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 645                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 646                         if (status != IXGBE_SUCCESS)
 647                                 return status;
 648                 }
 649         }
 650         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 651
 652         return IXGBE_SUCCESS;
 653 }
 654
 655 /**
 656  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 657  * @hw: pointer to hardware structure
 658  * @enable: enable or disable source address pruning
 659  * @pool: Rx pool to set source address pruning for
 660  **/
 661 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 662                                            unsigned int pool)
 663 {
 664         u64 pfflp;
 665
 666         /* max rx pool is 63 */
 667         if (pool > 63)
 668                 return;
 669
 670         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 671         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 672
 673         if (enable)
 674                 pfflp |= (1ULL << pool);
 675         else
 676                 pfflp &= ~(1ULL << pool);
 677
 678         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 679         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 680 }
 681
 682 /**
 683  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 684  *  @hw: pointer to hardware structure
 685  *  @enable: enable or disable switch for Ethertype anti-spoofing
 686  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 687  *
 688  **/
 689 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 690                 bool enable, int vf)
 691 {
 692         int vf_target_reg = vf >> 3;
 693         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 694         u32 pfvfspoof;
 695
 696         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 697
 698         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 699         if (enable)
 700                 pfvfspoof |= (1 << vf_target_shift);
 701         else
 702                 pfvfspoof &= ~(1 << vf_target_shift);
 703
 704         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 705 }
 706
 707 /**
 708  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 709  *  device
 710  *  @hw: pointer to hardware structure
 711  *  @reg_addr: 32 bit PHY register to write
 712  *  @device_type: 3 bit device type
 713  *  @data: Data to write to the register
 714  **/
 715 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 716                             u32 device_type, u32 data)
 717 {
 718         u32 i, command, error;
 719
 720         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 721                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 722
 723         /* Write IOSF control register */
 724         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 725
 726         /* Write IOSF data register */
 727         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 728         /*
 729          * Check every 10 usec to see if the address cycle completed.
 730          * The SB IOSF BUSY bit will clear when the operation is
 731          * complete
 732          */
 733         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 734                 usec_delay(10);
 735
 736                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 737                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 738                         break;
 739         }
 740
 741         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 742                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 743                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 744                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 745                               "Failed to write, error %x\n", error);
 746                 return IXGBE_ERR_PHY;
 747         }
 748
 749         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 750                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
 751                 return IXGBE_ERR_PHY;
 752         }
 753
 754         return IXGBE_SUCCESS;
 755 }
 756
 757 /**
 758  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 759  *  device
 760  *  @hw: pointer to hardware structure
 761  *  @reg_addr: 32 bit PHY register to write
 762  *  @device_type: 3 bit device type
 763  *  @phy_data: Pointer to read data from the register
 764  **/
 765 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 766                            u32 device_type, u32 *data)
 767 {
 768         u32 i, command, error;
 769
 770         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 771                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 772
 773         /* Write IOSF control register */
 774         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 775
 776         /*
 777          * Check every 10 usec to see if the address cycle completed.
 778          * The SB IOSF BUSY bit will clear when the operation is
 779          * complete
 780          */
 781         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 782                 usec_delay(10);
 783
 784                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 785                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 786                         break;
 787         }
 788
 789         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 790                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 791                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 792                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 793                                 "Failed to read, error %x\n", error);
 794                 return IXGBE_ERR_PHY;
 795         }
 796
 797         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 798                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
 799                 return IXGBE_ERR_PHY;
 800         }
 801
 802         *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 803
 804         return IXGBE_SUCCESS;
 805 }
 806
 807 /**
 808  *  ixgbe_disable_mdd_X550
 809  *  @hw: pointer to hardware structure
 810  *
 811  *  Disable malicious driver detection
 812  **/
 813 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 814 {
 815         u32 reg;
 816
 817         DEBUGFUNC("ixgbe_disable_mdd_X550");
 818
 819         /* Disable MDD for TX DMA and interrupt */
 820         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 821         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 822         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 823
 824         /* Disable MDD for RX and interrupt */
 825         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 826         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 827         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 828 }
 829
 830 /**
 831  *  ixgbe_enable_mdd_X550
 832  *  @hw: pointer to hardware structure
 833  *
 834  *  Enable malicious driver detection
 835  **/
 836 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 837 {
 838         u32 reg;
 839
 840         DEBUGFUNC("ixgbe_enable_mdd_X550");
 841
 842         /* Enable MDD for TX DMA and interrupt */
 843         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 844         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 845         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 846
 847         /* Enable MDD for RX and interrupt */
 848         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 849         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 850         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 851 }
 852
 853 /**
 854  *  ixgbe_restore_mdd_vf_X550
 855  *  @hw: pointer to hardware structure
 856  *  @vf: vf index
 857  *
 858  *  Restore VF that was disabled during malicious driver detection event
 859  **/
 860 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 861 {
 862         u32 idx, reg, num_qs, start_q, bitmask;
 863
 864         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 865
 866         /* Map VF to queues */
 867         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 868         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 869         case IXGBE_MRQC_VMDQRT8TCEN:
 870                 num_qs = 8;  /* 16 VFs / pools */
 871                 bitmask = 0x000000FF;
 872                 break;
 873         case IXGBE_MRQC_VMDQRSS32EN:
 874         case IXGBE_MRQC_VMDQRT4TCEN:
 875                 num_qs = 4;  /* 32 VFs / pools */
 876                 bitmask = 0x0000000F;
 877                 break;
 878         default:            /* 64 VFs / pools */
 879                 num_qs = 2;
 880                 bitmask = 0x00000003;
 881                 break;
 882         }
 883         start_q = vf * num_qs;
 884
 885         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 886         idx = start_q / 32;
 887         reg = 0;
 888         reg |= (bitmask << (start_q % 32));
 889         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 890         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 891 }
 892
 893 /**
 894  *  ixgbe_mdd_event_X550
 895  *  @hw: pointer to hardware structure
 896  *  @vf_bitmap: vf bitmap of malicious vfs
 897  *
 898  *  Handle malicious driver detection event.
 899  **/
 900 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 901 {
 902         u32 wqbr;
 903         u32 i, j, reg, q, shift, vf, idx;
 904
 905         DEBUGFUNC("ixgbe_mdd_event_X550");
 906
 907         /* figure out pool size for mapping to vf's */
 908         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 909         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 910         case IXGBE_MRQC_VMDQRT8TCEN:
 911                 shift = 3;  /* 16 VFs / pools */
 912                 break;
 913         case IXGBE_MRQC_VMDQRSS32EN:
 914         case IXGBE_MRQC_VMDQRT4TCEN:
 915                 shift = 2;  /* 32 VFs / pools */
 916                 break;
 917         default:
 918                 shift = 1;  /* 64 VFs / pools */
 919                 break;
 920         }
 921
 922         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
 923         for (i = 0; i < 4; i++) {
 924                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
 925                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
 926
 927                 if (!wqbr)
 928                         continue;
 929
 930                 /* Get malicious queue */
 931                 for (j = 0; j < 32 && wqbr; j++) {
 932
 933                         if (!(wqbr & (1 << j)))
 934                                 continue;
 935
 936                         /* Get queue from bitmask */
 937                         q = j + (i * 32);
 938
 939                         /* Map queue to vf */
 940                         vf = (q >> shift);
 941
 942                         /* Set vf bit in vf_bitmap */
 943                         idx = vf / 32;
 944                         vf_bitmap[idx] |= (1 << (vf % 32));
 945                         wqbr &= ~(1 << j);
 946                 }
 947         }
 948 }
 949
 950 /**
 951  *  ixgbe_get_media_type_X550em - Get media type
 952  *  @hw: pointer to hardware structure
 953  *
 954  *  Returns the media type (fiber, copper, backplane)
 955  */
 956 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
 957 {
 958         enum ixgbe_media_type media_type;
 959
 960         DEBUGFUNC("ixgbe_get_media_type_X550em");
 961
 962         /* Detect if there is a copper PHY attached. */
 963         switch (hw->device_id) {
 964         case IXGBE_DEV_ID_X550EM_X_KR:
 965         case IXGBE_DEV_ID_X550EM_X_KX4:
 966                 media_type = ixgbe_media_type_backplane;
 967                 break;
 968         case IXGBE_DEV_ID_X550EM_X_SFP:
 969                 media_type = ixgbe_media_type_fiber;
 970                 break;
 971         case IXGBE_DEV_ID_X550EM_X_1G_T:
 972         case IXGBE_DEV_ID_X550EM_X_10G_T:
 973                 media_type = ixgbe_media_type_copper;
 974                 break;
 975         default:
 976                 media_type = ixgbe_media_type_unknown;
 977                 break;
 978         }
 979         return media_type;
 980 }
 981
 982 /**
 983  *  ixgbe_setup_sfp_modules_X550em - Setup SFP module
 984  *  @hw: pointer to hardware structure
 985  */
 986 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
 987 {
 988         bool setup_linear;
 989         u16 reg_slice, edc_mode;
 990         s32 ret_val;
 991
 992         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
 993
 994         switch (hw->phy.sfp_type) {
 995         case ixgbe_sfp_type_unknown:
 996                 return IXGBE_SUCCESS;
 997         case ixgbe_sfp_type_not_present:
 998                 return IXGBE_ERR_SFP_NOT_PRESENT;
 999         case ixgbe_sfp_type_da_cu_core0:
1000         case ixgbe_sfp_type_da_cu_core1:
1001                 setup_linear = true;
1002                 break;
1003         case ixgbe_sfp_type_srlr_core0:
1004         case ixgbe_sfp_type_srlr_core1:
1005         case ixgbe_sfp_type_da_act_lmt_core0:
1006         case ixgbe_sfp_type_da_act_lmt_core1:
1007         case ixgbe_sfp_type_1g_sx_core0:
1008         case ixgbe_sfp_type_1g_sx_core1:
1009         case ixgbe_sfp_type_1g_lx_core0:
1010         case ixgbe_sfp_type_1g_lx_core1:
1011                 setup_linear = false;
1012                 break;
1013         default:
1014                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1015         }
1016
1017         ixgbe_init_mac_link_ops_X550em(hw);
1018         hw->phy.ops.reset = NULL;
1019
1020         /* The CS4227 slice address is the base address + the port-pair reg
1021          * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
1022          */
1023         reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12);
1024
1025         if (setup_linear)
1026                 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1027         else
1028                 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1029
1030         /* Configure CS4227 for connection type. */
1031         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1032                                            edc_mode);
1033
1034         if (ret_val != IXGBE_SUCCESS)
1035                 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
1036                                                    edc_mode);
1037
1038         return ret_val;
1039 }
1040
1041 /**
1042  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1043  *  @hw: pointer to hardware structure
1044  */
1045 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1046 {
1047         struct ixgbe_mac_info *mac = &hw->mac;
1048
1049         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1050
1051         /* CS4227 does not support autoneg, so disable the laser control
1052          * functions for SFP+ fiber
1053          */
1054          if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1055                 mac->ops.disable_tx_laser = NULL;
1056                 mac->ops.enable_tx_laser = NULL;
1057                 mac->ops.flap_tx_laser = NULL;
1058                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1059                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1060                 mac->ops.set_rate_select_speed =
1061                                         ixgbe_set_soft_rate_select_speed;
1062          }
1063 }
1064
1065 /**
1066  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1067  *  @hw: pointer to hardware structure
1068  *  @speed: pointer to link speed
1069  *  @autoneg: true when autoneg or autotry is enabled
1070  */
1071 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1072                                        ixgbe_link_speed *speed,
1073                                        bool *autoneg)
1074 {
1075         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1076
1077         /* SFP */
1078         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1079
1080                 /* CS4227 SFP must not enable auto-negotiation */
1081                 *autoneg = false;
1082
1083                 /* Check if 1G SFP module. */
1084                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1085                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1086                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1087                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1088                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1089                         return IXGBE_SUCCESS;
1090                 }
1091
1092                 /* Link capabilities are based on SFP */
1093                 if (hw->phy.multispeed_fiber)
1094                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1095                                  IXGBE_LINK_SPEED_1GB_FULL;
1096                 else
1097                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1098         } else {
1099                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1100                          IXGBE_LINK_SPEED_1GB_FULL;
1101                 *autoneg = true;
1102         }
1103
1104         return IXGBE_SUCCESS;
1105 }
1106
1107 /**
1108  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1109  *  @hw: pointer to hardware structure
1110  *
1111  *  Initialize any function pointers that were not able to be
1112  *  set during init_shared_code because the PHY/SFP type was
1113  *  not known.  Perform the SFP init if necessary.
1114  */
1115 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1116 {
1117         struct ixgbe_phy_info *phy = &hw->phy;
1118         s32 ret_val;
1119
1120         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1121
1122         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1123                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1124                 ixgbe_setup_mux_ctl(hw);
1125         }
1126
1127         /* Identify the PHY or SFP module */
1128         ret_val = phy->ops.identify(hw);
1129         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1130                 return ret_val;
1131
1132         /* Setup function pointers based on detected SFP module and speeds */
1133         ixgbe_init_mac_link_ops_X550em(hw);
1134         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1135                 phy->ops.reset = NULL;
1136
1137         /* Set functions pointers based on phy type */
1138         switch (hw->phy.type) {
1139         case ixgbe_phy_x550em_kx4:
1140                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1141                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1142                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1143                 break;
1144         case ixgbe_phy_x550em_kr:
1145                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1146                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1147                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1148                 break;
1149         case ixgbe_phy_x550em_ext_t:
1150                 phy->ops.setup_internal_link = ixgbe_setup_internal_phy_x550em;
1151                 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1152                 break;
1153         default:
1154                 break;
1155         }
1156         return ret_val;
1157 }
1158
1159 /**
1160  *  ixgbe_reset_hw_X550em - Perform hardware reset
1161  *  @hw: pointer to hardware structure
1162  *
1163  *  Resets the hardware by resetting the transmit and receive units, masks
1164  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1165  *  reset.
1166  */
1167 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1168 {
1169         struct ixgbe_hic_hdr fw_cmd;
1170         ixgbe_link_speed link_speed;
1171         s32 status;
1172         u32 ctrl = 0;
1173         u32 i;
1174         bool link_up = false;
1175
1176         DEBUGFUNC("ixgbe_reset_hw_X550em");
1177
1178         fw_cmd.cmd = FW_PHY_MGMT_REQ_CMD;
1179         fw_cmd.buf_len = 0;
1180         fw_cmd.cmd_or_resp.cmd_resv = 0;
1181         fw_cmd.checksum = FW_DEFAULT_CHECKSUM;
1182         status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
1183                                               sizeof(fw_cmd),
1184                                               IXGBE_HI_PHY_MGMT_REQ_TIMEOUT,
1185                                               true);
1186         if (status)
1187                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1188                               "PHY mgmt command failed with %d\n", status);
1189         else if (fw_cmd.cmd_or_resp.ret_status != FW_CEM_RESP_STATUS_SUCCESS)
1190                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1191                               "PHY mgmt command returned %d\n",
1192                               fw_cmd.cmd_or_resp.ret_status);
1193
1194         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1195         status = hw->mac.ops.stop_adapter(hw);
1196         if (status != IXGBE_SUCCESS)
1197                 return status;
1198
1199         /* flush pending Tx transactions */
1200         ixgbe_clear_tx_pending(hw);
1201
1202         /* PHY ops must be identified and initialized prior to reset */
1203
1204         /* Identify PHY and related function pointers */
1205         status = hw->phy.ops.init(hw);
1206
1207         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1208                 return status;
1209
1210         /* start the external PHY */
1211         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1212                 status = ixgbe_init_ext_t_x550em(hw);
1213                 if (status)
1214                         return status;
1215         }
1216
1217         /* Setup SFP module if there is one present. */
1218         if (hw->phy.sfp_setup_needed) {
1219                 status = hw->mac.ops.setup_sfp(hw);
1220                 hw->phy.sfp_setup_needed = false;
1221         }
1222
1223         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1224                 return status;
1225
1226         /* Reset PHY */
1227         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1228                 hw->phy.ops.reset(hw);
1229
1230 mac_reset_top:
1231         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1232          * If link reset is used when link is up, it might reset the PHY when
1233          * mng is using it.  If link is down or the flag to force full link
1234          * reset is set, then perform link reset.
1235          */
1236         ctrl = IXGBE_CTRL_LNK_RST;
1237         if (!hw->force_full_reset) {
1238                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1239                 if (link_up)
1240                         ctrl = IXGBE_CTRL_RST;
1241         }
1242
1243         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1244         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1245         IXGBE_WRITE_FLUSH(hw);
1246
1247         /* Poll for reset bit to self-clear meaning reset is complete */
1248         for (i = 0; i < 10; i++) {
1249                 usec_delay(1);
1250                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1251                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1252                         break;
1253         }
1254
1255         if (ctrl & IXGBE_CTRL_RST_MASK) {
1256                 status = IXGBE_ERR_RESET_FAILED;
1257                 DEBUGOUT("Reset polling failed to complete.\n");
1258         }
1259
1260         msec_delay(50);
1261
1262         /* Double resets are required for recovery from certain error
1263          * conditions.  Between resets, it is necessary to stall to
1264          * allow time for any pending HW events to complete.
1265          */
1266         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1267                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1268                 goto mac_reset_top;
1269         }
1270
1271         /* Store the permanent mac address */
1272         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1273
1274         /* Store MAC address from RAR0, clear receive address registers, and
1275          * clear the multicast table.  Also reset num_rar_entries to 128,
1276          * since we modify this value when programming the SAN MAC address.
1277          */
1278         hw->mac.num_rar_entries = 128;
1279         hw->mac.ops.init_rx_addrs(hw);
1280
1281
1282         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1283                 ixgbe_setup_mux_ctl(hw);
1284
1285         return status;
1286 }
1287
1288 /**
1289  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1290  * @hw: pointer to hardware structure
1291  */
1292 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1293 {
1294         u32 status;
1295         u16 reg;
1296         u32 retries = 1;
1297
1298         /* TODO: The number of attempts and delay between attempts is undefined */
1299         do {
1300                 /* decrement retries counter and exit if we hit 0 */
1301                 if (retries < 1) {
1302                         ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
1303                                       "External PHY not yet finished resetting.");
1304                         return IXGBE_ERR_PHY;
1305                 }
1306                 retries--;
1307
1308                 usec_delay(0);
1309
1310                 status = hw->phy.ops.read_reg(hw,
1311                                               IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1312                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1313                                               &reg);
1314
1315                 if (status != IXGBE_SUCCESS)
1316                         return status;
1317
1318                 /* Verify PHY FW reset has completed */
1319         } while ((reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) != 1);
1320
1321         /* Set port to low power mode */
1322         status = hw->phy.ops.read_reg(hw,
1323                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
1324                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1325                                       &reg);
1326
1327         if (status != IXGBE_SUCCESS)
1328                 return status;
1329
1330         reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
1331
1332         status = hw->phy.ops.write_reg(hw,
1333                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
1334                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1335                                        reg);
1336
1337         if (status != IXGBE_SUCCESS)
1338                 return status;
1339
1340         /* Enable the transmitter */
1341         status = hw->phy.ops.read_reg(hw,
1342                                       IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
1343                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1344                                       &reg);
1345
1346         if (status != IXGBE_SUCCESS)
1347                 return status;
1348
1349         reg &= ~IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE;
1350
1351         status = hw->phy.ops.write_reg(hw,
1352                                        IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
1353                                        IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1354                                        reg);
1355
1356         if (status != IXGBE_SUCCESS)
1357                 return status;
1358
1359         /* Un-stall the PHY FW */
1360         status = hw->phy.ops.read_reg(hw,
1361                                       IXGBE_MDIO_GLOBAL_RES_PR_10,
1362                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1363                                       &reg);
1364
1365         if (status != IXGBE_SUCCESS)
1366                 return status;
1367
1368         reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1369
1370         status = hw->phy.ops.write_reg(hw,
1371                                        IXGBE_MDIO_GLOBAL_RES_PR_10,
1372                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1373                                        reg);
1374
1375         return status;
1376 }
1377
1378 /**
1379  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1380  *  @hw: pointer to hardware structure
1381  *
1382  *  Configures the integrated KR PHY.
1383  **/
1384 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1385 {
1386         s32 status;
1387         u32 reg_val;
1388
1389         status = ixgbe_read_iosf_sb_reg_x550(hw,
1390                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1391                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1392         if (status)
1393                 return status;
1394
1395         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1396         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1397                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1398         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1399                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1400
1401         /* Advertise 10G support. */
1402         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1403                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1404
1405         /* Advertise 1G support. */
1406         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1407                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1408
1409         /* Restart auto-negotiation. */
1410         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1411         status = ixgbe_write_iosf_sb_reg_x550(hw,
1412                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1413                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1414
1415         return status;
1416 }
1417
1418 /**
1419  *  ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1420  *  @hw: pointer to hardware structure
1421  *
1422  *  Configures the integrated KX4 PHY.
1423  **/
1424 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1425 {
1426         s32 status;
1427         u32 reg_val;
1428
1429         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1430                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, &reg_val);
1431         if (status)
1432                 return status;
1433
1434         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1435                         IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1436
1437         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1438
1439         /* Advertise 10G support. */
1440         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1441                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1442
1443         /* Advertise 1G support. */
1444         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1445                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1446
1447         /* Restart auto-negotiation. */
1448         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1449         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1450                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, reg_val);
1451
1452         return status;
1453 }
1454
1455 /**
1456  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1457  *  @hw: pointer to hardware structure
1458  *  @speed: the link speed to force
1459  *
1460  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1461  *  internal and external PHY at a specific speed, without autonegotiation.
1462  **/
1463 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1464 {
1465         s32 status;
1466         u32 reg_val;
1467
1468         /* Disable AN and force speed to 10G Serial. */
1469         status = ixgbe_read_iosf_sb_reg_x550(hw,
1470                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1471                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1472         if (status != IXGBE_SUCCESS)
1473                 return status;
1474
1475         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1476         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1477
1478         /* Select forced link speed for internal PHY. */
1479         switch (*speed) {
1480         case IXGBE_LINK_SPEED_10GB_FULL:
1481                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1482                 break;
1483         case IXGBE_LINK_SPEED_1GB_FULL:
1484                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1485                 break;
1486         default:
1487                 /* Other link speeds are not supported by internal KR PHY. */
1488                 return IXGBE_ERR_LINK_SETUP;
1489         }
1490
1491         status = ixgbe_write_iosf_sb_reg_x550(hw,
1492                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1493                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1494         if (status != IXGBE_SUCCESS)
1495                 return status;
1496
1497         /* Disable training protocol FSM. */
1498         status = ixgbe_read_iosf_sb_reg_x550(hw,
1499                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1500                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1501         if (status != IXGBE_SUCCESS)
1502                 return status;
1503         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1504         status = ixgbe_write_iosf_sb_reg_x550(hw,
1505                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1506                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1507         if (status != IXGBE_SUCCESS)
1508                 return status;
1509
1510         /* Disable Flex from training TXFFE. */
1511         status = ixgbe_read_iosf_sb_reg_x550(hw,
1512                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1513                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1514         if (status != IXGBE_SUCCESS)
1515                 return status;
1516         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1517         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1518         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1519         status = ixgbe_write_iosf_sb_reg_x550(hw,
1520                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1521                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1522         if (status != IXGBE_SUCCESS)
1523                 return status;
1524         status = ixgbe_read_iosf_sb_reg_x550(hw,
1525                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1526                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1527         if (status != IXGBE_SUCCESS)
1528                 return status;
1529         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1530         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1531         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1532         status = ixgbe_write_iosf_sb_reg_x550(hw,
1533                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1534                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1535         if (status != IXGBE_SUCCESS)
1536                 return status;
1537
1538         /* Enable override for coefficients. */
1539         status = ixgbe_read_iosf_sb_reg_x550(hw,
1540                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1541                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1542         if (status != IXGBE_SUCCESS)
1543                 return status;
1544         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1545         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1546         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1547         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1548         status = ixgbe_write_iosf_sb_reg_x550(hw,
1549                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1550                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1551         if (status != IXGBE_SUCCESS)
1552                 return status;
1553
1554         /* Toggle port SW reset by AN reset. */
1555         status = ixgbe_read_iosf_sb_reg_x550(hw,
1556                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1557                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1558         if (status != IXGBE_SUCCESS)
1559                 return status;
1560         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1561         status = ixgbe_write_iosf_sb_reg_x550(hw,
1562                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1563                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1564
1565         return status;
1566 }
1567
1568 /**
1569  *  ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1570  *  @hw: pointer to hardware structure
1571  *
1572  *  Configures the integrated KR PHY for SFP support.
1573  **/
1574 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1575                                     ixgbe_link_speed speed,
1576                                     bool autoneg_wait_to_complete)
1577 {
1578         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1579
1580         return ixgbe_setup_ixfi_x550em(hw, &speed);
1581 }
1582
1583 /**
1584  * ixgbe_setup_internal_phy_x550em - Configure integrated KR PHY
1585  * @hw: point to hardware structure
1586  *
1587  * Configures the integrated KR PHY to talk to the external PHY. The base
1588  * driver will call this function when it gets notification via interrupt from
1589  * the external PHY. This function forces the internal PHY into iXFI mode at
1590  * the correct speed.
1591  *
1592  * A return of a non-zero value indicates an error, and the base driver should
1593  * not report link up.
1594  */
1595 s32 ixgbe_setup_internal_phy_x550em(struct ixgbe_hw *hw)
1596 {
1597         u32 status;
1598         u16 lasi, autoneg_status, speed;
1599         ixgbe_link_speed force_speed;
1600
1601         /* Verify that the external link status has changed */
1602         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_XENPAK_LASI_STATUS,
1603                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1604                                       &lasi);
1605         if (status != IXGBE_SUCCESS)
1606                 return status;
1607
1608         /* If there was no change in link status, we can just exit */
1609         if (!(lasi & IXGBE_XENPAK_LASI_LINK_STATUS_ALARM))
1610                 return IXGBE_SUCCESS;
1611
1612         /* we read this twice back to back to indicate current status */
1613         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1614                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1615                                       &autoneg_status);
1616         if (status != IXGBE_SUCCESS)
1617                 return status;
1618
1619         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1620                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1621                                       &autoneg_status);
1622         if (status != IXGBE_SUCCESS)
1623                 return status;
1624
1625         /* If link is not up return an error indicating treat link as down */
1626         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1627                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1628
1629         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1630                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1631                                       &speed);
1632
1633         /* clear everything but the speed and duplex bits */
1634         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1635
1636         switch (speed) {
1637         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1638                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1639                 break;
1640         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1641                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1642                 break;
1643         default:
1644                 /* Internal PHY does not support anything else */
1645                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1646         }
1647
1648         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1649 }
1650
1651 /**
1652  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1653  *  @hw: pointer to hardware structure
1654  *
1655  *  Configures the integrated KR PHY to use internal loopback mode.
1656  **/
1657 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1658 {
1659         s32 status;
1660         u32 reg_val;
1661
1662         /* Disable AN and force speed to 10G Serial. */
1663         status = ixgbe_read_iosf_sb_reg_x550(hw,
1664                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1665                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1666         if (status != IXGBE_SUCCESS)
1667                 return status;
1668         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1669         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1670         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1671         status = ixgbe_write_iosf_sb_reg_x550(hw,
1672                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1673                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1674         if (status != IXGBE_SUCCESS)
1675                 return status;
1676
1677         /* Set near-end loopback clocks. */
1678         status = ixgbe_read_iosf_sb_reg_x550(hw,
1679                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1680                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1681         if (status != IXGBE_SUCCESS)
1682                 return status;
1683         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1684         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1685         status = ixgbe_write_iosf_sb_reg_x550(hw,
1686                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1687                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1688         if (status != IXGBE_SUCCESS)
1689                 return status;
1690
1691         /* Set loopback enable. */
1692         status = ixgbe_read_iosf_sb_reg_x550(hw,
1693                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1694                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1695         if (status != IXGBE_SUCCESS)
1696                 return status;
1697         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1698         status = ixgbe_write_iosf_sb_reg_x550(hw,
1699                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1700                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1701         if (status != IXGBE_SUCCESS)
1702                 return status;
1703
1704         /* Training bypass. */
1705         status = ixgbe_read_iosf_sb_reg_x550(hw,
1706                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1707                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1708         if (status != IXGBE_SUCCESS)
1709                 return status;
1710         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1711         status = ixgbe_write_iosf_sb_reg_x550(hw,
1712                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1713                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1714
1715         return status;
1716 }
1717
1718 /**
1719  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1720  *  assuming that the semaphore is already obtained.
1721  *  @hw: pointer to hardware structure
1722  *  @offset: offset of  word in the EEPROM to read
1723  *  @data: word read from the EEPROM
1724  *
1725  *  Reads a 16 bit word from the EEPROM using the hostif.
1726  **/
1727 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1728                                    u16 *data)
1729 {
1730         s32 status;
1731         struct ixgbe_hic_read_shadow_ram buffer;
1732
1733         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1734         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1735         buffer.hdr.req.buf_lenh = 0;
1736         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1737         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1738
1739         /* convert offset from words to bytes */
1740         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1741         /* one word */
1742         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1743
1744         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1745                                               sizeof(buffer),
1746                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1747
1748         if (status)
1749                 return status;
1750
1751         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1752                                           FW_NVM_DATA_OFFSET);
1753
1754         return 0;
1755 }
1756
1757 /**
1758  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1759  *  @hw: pointer to hardware structure
1760  *  @offset: offset of  word in the EEPROM to read
1761  *  @data: word read from the EEPROM
1762  *
1763  *  Reads a 16 bit word from the EEPROM using the hostif.
1764  **/
1765 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1766                               u16 *data)
1767 {
1768         s32 status = IXGBE_SUCCESS;
1769
1770         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1771
1772         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1773             IXGBE_SUCCESS) {
1774                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1775                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1776         } else {
1777                 status = IXGBE_ERR_SWFW_SYNC;
1778         }
1779
1780         return status;
1781 }
1782
1783 /**
1784  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1785  *  @hw: pointer to hardware structure
1786  *  @offset: offset of  word in the EEPROM to read
1787  *  @words: number of words
1788  *  @data: word(s) read from the EEPROM
1789  *
1790  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
1791  **/
1792 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1793                                      u16 offset, u16 words, u16 *data)
1794 {
1795         struct ixgbe_hic_read_shadow_ram buffer;
1796         u32 current_word = 0;
1797         u16 words_to_read;
1798         s32 status;
1799         u32 i;
1800
1801         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1802
1803         /* Take semaphore for the entire operation. */
1804         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1805         if (status) {
1806                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1807                 return status;
1808         }
1809         while (words) {
1810                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1811                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1812                 else
1813                         words_to_read = words;
1814
1815                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1816                 buffer.hdr.req.buf_lenh = 0;
1817                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1818                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1819
1820                 /* convert offset from words to bytes */
1821                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1822                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1823
1824                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1825                                                       sizeof(buffer),
1826                                                       IXGBE_HI_COMMAND_TIMEOUT,
1827                                                       false);
1828
1829                 if (status) {
1830                         DEBUGOUT("Host interface command failed\n");
1831                         goto out;
1832                 }
1833
1834                 for (i = 0; i < words_to_read; i++) {
1835                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1836                                   2 * i;
1837                         u32 value = IXGBE_READ_REG(hw, reg);
1838
1839                         data[current_word] = (u16)(value & 0xffff);
1840                         current_word++;
1841                         i++;
1842                         if (i < words_to_read) {
1843                                 value >>= 16;
1844                                 data[current_word] = (u16)(value & 0xffff);
1845                                 current_word++;
1846                         }
1847                 }
1848                 words -= words_to_read;
1849         }
1850
1851 out:
1852         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1853         return status;
1854 }
1855
1856 /**
1857  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1858  *  @hw: pointer to hardware structure
1859  *  @offset: offset of  word in the EEPROM to write
1860  *  @data: word write to the EEPROM
1861  *
1862  *  Write a 16 bit word to the EEPROM using the hostif.
1863  **/
1864 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1865                                     u16 data)
1866 {
1867         s32 status;
1868         struct ixgbe_hic_write_shadow_ram buffer;
1869
1870         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1871
1872         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1873         buffer.hdr.req.buf_lenh = 0;
1874         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1875         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1876
1877          /* one word */
1878         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1879         buffer.data = data;
1880         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1881
1882         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1883                                               sizeof(buffer),
1884                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1885
1886         return status;
1887 }
1888
1889 /**
1890  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1891  *  @hw: pointer to hardware structure
1892  *  @offset: offset of  word in the EEPROM to write
1893  *  @data: word write to the EEPROM
1894  *
1895  *  Write a 16 bit word to the EEPROM using the hostif.
1896  **/
1897 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1898                                u16 data)
1899 {
1900         s32 status = IXGBE_SUCCESS;
1901
1902         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
1903
1904         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1905             IXGBE_SUCCESS) {
1906                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1907                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1908         } else {
1909                 DEBUGOUT("write ee hostif failed to get semaphore");
1910                 status = IXGBE_ERR_SWFW_SYNC;
1911         }
1912
1913         return status;
1914 }
1915
1916 /**
1917  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1918  *  @hw: pointer to hardware structure
1919  *  @offset: offset of  word in the EEPROM to write
1920  *  @words: number of words
1921  *  @data: word(s) write to the EEPROM
1922  *
1923  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1924  **/
1925 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1926                                       u16 offset, u16 words, u16 *data)
1927 {
1928         s32 status = IXGBE_SUCCESS;
1929         u32 i = 0;
1930
1931         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
1932
1933         /* Take semaphore for the entire operation. */
1934         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1935         if (status != IXGBE_SUCCESS) {
1936                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
1937                 goto out;
1938         }
1939
1940         for (i = 0; i < words; i++) {
1941                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1942                                                          data[i]);
1943
1944                 if (status != IXGBE_SUCCESS) {
1945                         DEBUGOUT("Eeprom buffered write failed\n");
1946                         break;
1947                 }
1948         }
1949
1950         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1951 out:
1952
1953         return status;
1954 }
1955
1956 /**
1957  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
1958  * @hw: pointer to hardware structure
1959  * @ptr: pointer offset in eeprom
1960  * @size: size of section pointed by ptr, if 0 first word will be used as size
1961  * @csum: address of checksum to update
1962  *
1963  * Returns error status for any failure
1964  */
1965 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
1966                                    u16 size, u16 *csum, u16 *buffer,
1967                                    u32 buffer_size)
1968 {
1969         u16 buf[256];
1970         s32 status;
1971         u16 length, bufsz, i, start;
1972         u16 *local_buffer;
1973
1974         bufsz = sizeof(buf) / sizeof(buf[0]);
1975
1976         /* Read a chunk at the pointer location */
1977         if (!buffer) {
1978                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
1979                 if (status) {
1980                         DEBUGOUT("Failed to read EEPROM image\n");
1981                         return status;
1982                 }
1983                 local_buffer = buf;
1984         } else {
1985                 if (buffer_size < ptr)
1986                         return  IXGBE_ERR_PARAM;
1987                 local_buffer = &buffer[ptr];
1988         }
1989
1990         if (size) {
1991                 start = 0;
1992                 length = size;
1993         } else {
1994                 start = 1;
1995                 length = local_buffer[0];
1996
1997                 /* Skip pointer section if length is invalid. */
1998                 if (length == 0xFFFF || length == 0 ||
1999                     (ptr + length) >= hw->eeprom.word_size)
2000                         return IXGBE_SUCCESS;
2001         }
2002
2003         if (buffer && ((u32)start + (u32)length > buffer_size))
2004                 return IXGBE_ERR_PARAM;
2005
2006         for (i = start; length; i++, length--) {
2007                 if (i == bufsz && !buffer) {
2008                         ptr += bufsz;
2009                         i = 0;
2010                         if (length < bufsz)
2011                                 bufsz = length;
2012
2013                         /* Read a chunk at the pointer location */
2014                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2015                                                                   bufsz, buf);
2016                         if (status) {
2017                                 DEBUGOUT("Failed to read EEPROM image\n");
2018                                 return status;
2019                         }
2020                 }
2021                 *csum += local_buffer[i];
2022         }
2023         return IXGBE_SUCCESS;
2024 }
2025
2026 /**
2027  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2028  *  @hw: pointer to hardware structure
2029  *  @buffer: pointer to buffer containing calculated checksum
2030  *  @buffer_size: size of buffer
2031  *
2032  *  Returns a negative error code on error, or the 16-bit checksum
2033  **/
2034 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2035 {
2036         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2037         u16 *local_buffer;
2038         s32 status;
2039         u16 checksum = 0;
2040         u16 pointer, i, size;
2041
2042         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2043
2044         hw->eeprom.ops.init_params(hw);
2045
2046         if (!buffer) {
2047                 /* Read pointer area */
2048                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2049                                                      IXGBE_EEPROM_LAST_WORD + 1,
2050                                                      eeprom_ptrs);
2051                 if (status) {
2052                         DEBUGOUT("Failed to read EEPROM image\n");
2053                         return status;
2054                 }
2055                 local_buffer = eeprom_ptrs;
2056         } else {
2057                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2058                         return IXGBE_ERR_PARAM;
2059                 local_buffer = buffer;
2060         }
2061
2062         /*
2063          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2064          * checksum word itself
2065          */
2066         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2067                 if (i != IXGBE_EEPROM_CHECKSUM)
2068                         checksum += local_buffer[i];
2069
2070         /*
2071          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2072          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2073          */
2074         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2075                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2076                         continue;
2077
2078                 pointer = local_buffer[i];
2079
2080                 /* Skip pointer section if the pointer is invalid. */
2081                 if (pointer == 0xFFFF || pointer == 0 ||
2082                     pointer >= hw->eeprom.word_size)
2083                         continue;
2084
2085                 switch (i) {
2086                 case IXGBE_PCIE_GENERAL_PTR:
2087                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2088                         break;
2089                 case IXGBE_PCIE_CONFIG0_PTR:
2090                 case IXGBE_PCIE_CONFIG1_PTR:
2091                         size = IXGBE_PCIE_CONFIG_SIZE;
2092                         break;
2093                 default:
2094                         size = 0;
2095                         break;
2096                 }
2097
2098                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2099                                                 buffer, buffer_size);
2100                 if (status)
2101                         return status;
2102         }
2103
2104         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2105
2106         return (s32)checksum;
2107 }
2108
2109 /**
2110  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2111  *  @hw: pointer to hardware structure
2112  *
2113  *  Returns a negative error code on error, or the 16-bit checksum
2114  **/
2115 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2116 {
2117         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2118 }
2119
2120 /**
2121  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2122  *  @hw: pointer to hardware structure
2123  *  @checksum_val: calculated checksum
2124  *
2125  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2126  *  caller does not need checksum_val, the value can be NULL.
2127  **/
2128 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2129 {
2130         s32 status;
2131         u16 checksum;
2132         u16 read_checksum = 0;
2133
2134         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2135
2136         /* Read the first word from the EEPROM. If this times out or fails, do
2137          * not continue or we could be in for a very long wait while every
2138          * EEPROM read fails
2139          */
2140         status = hw->eeprom.ops.read(hw, 0, &checksum);
2141         if (status) {
2142                 DEBUGOUT("EEPROM read failed\n");
2143                 return status;
2144         }
2145
2146         status = hw->eeprom.ops.calc_checksum(hw);
2147         if (status < 0)
2148                 return status;
2149
2150         checksum = (u16)(status & 0xffff);
2151
2152         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2153                                            &read_checksum);
2154         if (status)
2155                 return status;
2156
2157         /* Verify read checksum from EEPROM is the same as
2158          * calculated checksum
2159          */
2160         if (read_checksum != checksum) {
2161                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2162                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2163                              "Invalid EEPROM checksum");
2164         }
2165
2166         /* If the user cares, return the calculated checksum */
2167         if (checksum_val)
2168                 *checksum_val = checksum;
2169
2170         return status;
2171 }
2172
2173 /**
2174  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2175  * @hw: pointer to hardware structure
2176  *
2177  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2178  * checksum and updates the EEPROM and instructs the hardware to update
2179  * the flash.
2180  **/
2181 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2182 {
2183         s32 status;
2184         u16 checksum = 0;
2185
2186         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2187
2188         /* Read the first word from the EEPROM. If this times out or fails, do
2189          * not continue or we could be in for a very long wait while every
2190          * EEPROM read fails
2191          */
2192         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2193         if (status) {
2194                 DEBUGOUT("EEPROM read failed\n");
2195                 return status;
2196         }
2197
2198         status = ixgbe_calc_eeprom_checksum_X550(hw);
2199         if (status < 0)
2200                 return status;
2201
2202         checksum = (u16)(status & 0xffff);
2203
2204         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2205                                             checksum);
2206         if (status)
2207                 return status;
2208
2209         status = ixgbe_update_flash_X550(hw);
2210
2211         return status;
2212 }
2213
2214 /**
2215  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2216  *  @hw: pointer to hardware structure
2217  *
2218  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2219  **/
2220 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2221 {
2222         s32 status = IXGBE_SUCCESS;
2223         union ixgbe_hic_hdr2 buffer;
2224
2225         DEBUGFUNC("ixgbe_update_flash_X550");
2226
2227         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2228         buffer.req.buf_lenh = 0;
2229         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2230         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2231
2232         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2233                                               sizeof(buffer),
2234                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2235
2236         return status;
2237 }
2238
2239 /**
2240  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2241  *  @hw: pointer to hardware structure
2242  *
2243  *  Determines physical layer capabilities of the current configuration.
2244  **/
2245 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2246 {
2247         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2248         u16 ext_ability = 0;
2249
2250         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2251
2252         hw->phy.ops.identify(hw);
2253
2254         switch (hw->phy.type) {
2255         case ixgbe_phy_x550em_kr:
2256                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2257                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2258                 break;
2259         case ixgbe_phy_x550em_kx4:
2260                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2261                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2262                 break;
2263         case ixgbe_phy_x550em_ext_t:
2264                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2265                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2266                                      &ext_ability);
2267                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2268                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2269                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2270                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2271                 break;
2272         default:
2273                 break;
2274         }
2275
2276         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2277                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2278
2279         return physical_layer;
2280 }
2281
2282 /**
2283  * ixgbe_get_bus_info_x550em - Set PCI bus info
2284  * @hw: pointer to hardware structure
2285  *
2286  * Sets bus link width and speed to unknown because X550em is
2287  * not a PCI device.
2288  **/
2289 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2290 {
2291
2292         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2293
2294         hw->bus.width = ixgbe_bus_width_unknown;
2295         hw->bus.speed = ixgbe_bus_speed_unknown;
2296
2297         return IXGBE_SUCCESS;
2298 }
2299
2300 /**
2301  * ixgbe_disable_rx_x550 - Disable RX unit
2302  *
2303  * Enables the Rx DMA unit for x550
2304  **/
2305 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2306 {
2307         u32 rxctrl, pfdtxgswc;
2308         s32 status;
2309         struct ixgbe_hic_disable_rxen fw_cmd;
2310
2311         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2312
2313         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2314         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2315                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2316                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2317                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2318                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2319                         hw->mac.set_lben = true;
2320                 } else {
2321                         hw->mac.set_lben = false;
2322                 }
2323
2324                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2325                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2326                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2327                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2328
2329                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2330                                         sizeof(struct ixgbe_hic_disable_rxen),
2331                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2332
2333                 /* If we fail - disable RX using register write */
2334                 if (status) {
2335                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2336                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2337                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2338                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2339                         }
2340                 }
2341         }
2342 }
2343
2344 /**
2345  * ixgbe_enter_lplu_x550em - Transition to low power states
2346  *  @hw: pointer to hardware structure
2347  *
2348  * Configures Low Power Link Up on transition to low power states
2349  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2350  * X557 PHY immediately prior to entering LPLU.
2351  **/
2352 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2353 {
2354         u16 autoneg_status, an_10g_cntl_reg, autoneg_reg, speed;
2355         s32 status;
2356         ixgbe_link_speed lcd_speed;
2357
2358         /* If blocked by MNG FW, then don't restart AN */
2359         if (ixgbe_check_reset_blocked(hw))
2360                 return IXGBE_SUCCESS;
2361
2362         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2363                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2364                                       &autoneg_status);
2365
2366         if (status != IXGBE_SUCCESS)
2367                 return status;
2368
2369         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2370
2371         if (status != IXGBE_SUCCESS)
2372                 return status;
2373
2374         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2375          * disabled, then force link down by entering low power mode.
2376          */
2377         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS) ||
2378             !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2379             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2380                 return ixgbe_set_copper_phy_power(hw, FALSE);
2381
2382         /* Determine LCD */
2383         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2384
2385         if (status != IXGBE_SUCCESS)
2386                 return status;
2387
2388         /* If no valid LCD link speed, then force link down and exit. */
2389         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2390                 return ixgbe_set_copper_phy_power(hw, FALSE);
2391
2392         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2393                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2394                                       &speed);
2395
2396         if (status != IXGBE_SUCCESS)
2397                 return status;
2398
2399         /* clear everything but the speed bits */
2400         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2401
2402         /* If current speed is already LCD, then exit. */
2403         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2404              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2405             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2406              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2407                 return status;
2408
2409         /* Clear AN completed indication */
2410         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2411                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2412                                       &autoneg_status);
2413
2414         if (status != IXGBE_SUCCESS)
2415                 return status;
2416
2417         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2418                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2419                              &an_10g_cntl_reg);
2420
2421         if (status != IXGBE_SUCCESS)
2422                 return status;
2423
2424         status = hw->phy.ops.read_reg(hw,
2425                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2426                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2427                              &autoneg_reg);
2428
2429         if (status != IXGBE_SUCCESS)
2430                 return status;
2431
2432         /* Set AN advertizement to only include LCD  */
2433         if (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL) {
2434                 an_10g_cntl_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
2435                 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
2436         }
2437
2438         if (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL) {
2439                 an_10g_cntl_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
2440                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
2441         }
2442
2443         status = hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2444                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2445                               an_10g_cntl_reg);
2446
2447         if (status != IXGBE_SUCCESS)
2448                 return status;
2449
2450         status = hw->phy.ops.write_reg(hw,
2451                               IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2452                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2453                               autoneg_reg);
2454
2455         if (status != IXGBE_SUCCESS)
2456                 return status;
2457
2458         /* Restart PHY auto-negotiation. */
2459         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
2460                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
2461
2462         if (status != IXGBE_SUCCESS)
2463                 return status;
2464
2465         autoneg_reg |= IXGBE_MII_RESTART;
2466
2467         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
2468                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
2469
2470         if (status != IXGBE_SUCCESS)
2471                 return status;
2472
2473         status = ixgbe_setup_ixfi_x550em(hw, &lcd_speed);
2474
2475         return status;
2476 }
2477
2478 /**
2479  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2480  *  @hw: pointer to hardware structure
2481  *  @lcd_speed: pointer to lowest common link speed
2482  *
2483  * Determine lowest common link speed with link partner.
2484  **/
2485 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2486 {
2487         u16 an_lp_status;
2488         s32 status;
2489         u16 word = hw->eeprom.ctrl_word_3;
2490
2491         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2492
2493         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2494                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2495                                       &an_lp_status);
2496
2497         if (status != IXGBE_SUCCESS)
2498                 return status;
2499
2500         /* If link partner advertised 1G, return 1G */
2501         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2502                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2503                 return status;
2504         }
2505
2506         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2507         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2508             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2509                 return status;
2510
2511         /* Link partner not capable of lower speeds, return 10G */
2512         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2513         return status;
2514 }
2515
2516 /**
2517  *  ixgbe_setup_fc_X550em - Set up flow control
2518  *  @hw: pointer to hardware structure
2519  *
2520  *  Called at init time to set up flow control.
2521  **/
2522 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2523 {
2524         s32 ret_val = IXGBE_SUCCESS;
2525         u32 pause, asm_dir, reg_val;
2526
2527         DEBUGFUNC("ixgbe_setup_fc_X550em");
2528
2529         /* Validate the requested mode */
2530         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2531                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2532                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2533                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2534                 goto out;
2535         }
2536
2537         /* 10gig parts do not have a word in the EEPROM to determine the
2538          * default flow control setting, so we explicitly set it to full.
2539          */
2540         if (hw->fc.requested_mode == ixgbe_fc_default)
2541                 hw->fc.requested_mode = ixgbe_fc_full;
2542
2543         /* Determine PAUSE and ASM_DIR bits. */
2544         switch (hw->fc.requested_mode) {
2545         case ixgbe_fc_none:
2546                 pause = 0;
2547                 asm_dir = 0;
2548                 break;
2549         case ixgbe_fc_tx_pause:
2550                 pause = 0;
2551                 asm_dir = 1;
2552                 break;
2553         case ixgbe_fc_rx_pause:
2554                 /* Rx Flow control is enabled and Tx Flow control is
2555                  * disabled by software override. Since there really
2556                  * isn't a way to advertise that we are capable of RX
2557                  * Pause ONLY, we will advertise that we support both
2558                  * symmetric and asymmetric Rx PAUSE, as such we fall
2559                  * through to the fc_full statement.  Later, we will
2560                  * disable the adapter's ability to send PAUSE frames.
2561                  */
2562         case ixgbe_fc_full:
2563                 pause = 1;
2564                 asm_dir = 1;
2565                 break;
2566         default:
2567                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2568                         "Flow control param set incorrectly\n");
2569                 ret_val = IXGBE_ERR_CONFIG;
2570                 goto out;
2571         }
2572
2573         if (hw->phy.media_type == ixgbe_media_type_backplane) {
2574                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2575                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2576                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2577                 if (ret_val != IXGBE_SUCCESS)
2578                         goto out;
2579                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2580                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2581                 if (pause)
2582                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2583                 if (asm_dir)
2584                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2585                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2586                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2587                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2588
2589                 /* Not all devices fully support AN. */
2590                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR)
2591                         hw->fc.disable_fc_autoneg = true;
2592         }
2593
2594 out:
2595         return ret_val;
2596 }