drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44
  45 /**
  46  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  47  *  @hw: pointer to hardware structure
  48  *
  49  *  Initialize the function pointers and assign the MAC type for X550.
  50  *  Does not touch the hardware.
  51  **/
  52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  53 {
  54         struct ixgbe_mac_info *mac = &hw->mac;
  55         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  56         s32 ret_val;
  57
  58         DEBUGFUNC("ixgbe_init_ops_X550");
  59
  60         ret_val = ixgbe_init_ops_X540(hw);
  61         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  62         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  63         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  64         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  65         mac->ops.set_source_address_pruning =
  66                         ixgbe_set_source_address_pruning_X550;
  67         mac->ops.set_ethertype_anti_spoofing =
  68                         ixgbe_set_ethertype_anti_spoofing_X550;
  69
  70         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  71         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  72         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  73         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  74         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  75         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  76         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  77         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  78         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  79
  80         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  81         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  82         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  83         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  84         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  85         switch (hw->device_id) {
  86         case IXGBE_DEV_ID_X550EM_X_10G_T:
  87         case IXGBE_DEV_ID_X550EM_A_10G_T:
  88                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  89                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  90                 break;
  91         default:
  92                 break;
  93         }
  94         return ret_val;
  95 }
  96
  97 /**
  98  * ixgbe_read_cs4227 - Read CS4227 register
  99  * @hw: pointer to hardware structure
 100  * @reg: register number to write
 101  * @value: pointer to receive value read
 102  *
 103  * Returns status code
 104  **/
 105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 106 {
 107         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 108 }
 109
 110 /**
 111  * ixgbe_write_cs4227 - Write CS4227 register
 112  * @hw: pointer to hardware structure
 113  * @reg: register number to write
 114  * @value: value to write to register
 115  *
 116  * Returns status code
 117  **/
 118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 119 {
 120         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 121 }
 122
 123 /**
 124  * ixgbe_read_pe - Read register from port expander
 125  * @hw: pointer to hardware structure
 126  * @reg: register number to read
 127  * @value: pointer to receive read value
 128  *
 129  * Returns status code
 130  **/
 131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 132 {
 133         s32 status;
 134
 135         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 136         if (status != IXGBE_SUCCESS)
 137                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 138                               "port expander access failed with %d\n", status);
 139         return status;
 140 }
 141
 142 /**
 143  * ixgbe_write_pe - Write register to port expander
 144  * @hw: pointer to hardware structure
 145  * @reg: register number to write
 146  * @value: value to write
 147  *
 148  * Returns status code
 149  **/
 150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 151 {
 152         s32 status;
 153
 154         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 155         if (status != IXGBE_SUCCESS)
 156                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 157                               "port expander access failed with %d\n", status);
 158         return status;
 159 }
 160
 161 /**
 162  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 163  * @hw: pointer to hardware structure
 164  *
 165  * This function assumes that the caller has acquired the proper semaphore.
 166  * Returns error code
 167  **/
 168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 169 {
 170         s32 status;
 171         u32 retry;
 172         u16 value;
 173         u8 reg;
 174
 175         /* Trigger hard reset. */
 176         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 177         if (status != IXGBE_SUCCESS)
 178                 return status;
 179         reg |= IXGBE_PE_BIT1;
 180         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 181         if (status != IXGBE_SUCCESS)
 182                 return status;
 183
 184         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 185         if (status != IXGBE_SUCCESS)
 186                 return status;
 187         reg &= ~IXGBE_PE_BIT1;
 188         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 189         if (status != IXGBE_SUCCESS)
 190                 return status;
 191
 192         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 193         if (status != IXGBE_SUCCESS)
 194                 return status;
 195         reg &= ~IXGBE_PE_BIT1;
 196         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199
 200         usec_delay(IXGBE_CS4227_RESET_HOLD);
 201
 202         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 203         if (status != IXGBE_SUCCESS)
 204                 return status;
 205         reg |= IXGBE_PE_BIT1;
 206         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 207         if (status != IXGBE_SUCCESS)
 208                 return status;
 209
 210         /* Wait for the reset to complete. */
 211         msec_delay(IXGBE_CS4227_RESET_DELAY);
 212         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 213                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 214                                            &value);
 215                 if (status == IXGBE_SUCCESS &&
 216                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 217                         break;
 218                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 219         }
 220         if (retry == IXGBE_CS4227_RETRIES) {
 221                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 222                         "CS4227 reset did not complete.");
 223                 return IXGBE_ERR_PHY;
 224         }
 225
 226         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 227         if (status != IXGBE_SUCCESS ||
 228             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 229                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 230                         "CS4227 EEPROM did not load successfully.");
 231                 return IXGBE_ERR_PHY;
 232         }
 233
 234         return IXGBE_SUCCESS;
 235 }
 236
 237 /**
 238  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 239  * @hw: pointer to hardware structure
 240  **/
 241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 242 {
 243         s32 status = IXGBE_SUCCESS;
 244         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 245         u16 value = 0;
 246         u8 retry;
 247
 248         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 249                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 250                 if (status != IXGBE_SUCCESS) {
 251                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 252                                 "semaphore failed with %d", status);
 253                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 254                         continue;
 255                 }
 256
 257                 /* Get status of reset flow. */
 258                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 259
 260                 if (status == IXGBE_SUCCESS &&
 261                     value == IXGBE_CS4227_RESET_COMPLETE)
 262                         goto out;
 263
 264                 if (status != IXGBE_SUCCESS ||
 265                     value != IXGBE_CS4227_RESET_PENDING)
 266                         break;
 267
 268                 /* Reset is pending. Wait and check again. */
 269                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 270                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 271         }
 272
 273         /* If still pending, assume other instance failed. */
 274         if (retry == IXGBE_CS4227_RETRIES) {
 275                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 276                 if (status != IXGBE_SUCCESS) {
 277                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 278                                       "semaphore failed with %d", status);
 279                         return;
 280                 }
 281         }
 282
 283         /* Reset the CS4227. */
 284         status = ixgbe_reset_cs4227(hw);
 285         if (status != IXGBE_SUCCESS) {
 286                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 287                         "CS4227 reset failed: %d", status);
 288                 goto out;
 289         }
 290
 291         /* Reset takes so long, temporarily release semaphore in case the
 292          * other driver instance is waiting for the reset indication.
 293          */
 294         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 295                            IXGBE_CS4227_RESET_PENDING);
 296         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 297         msec_delay(10);
 298         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 299         if (status != IXGBE_SUCCESS) {
 300                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 301                         "semaphore failed with %d", status);
 302                 return;
 303         }
 304
 305         /* Record completion for next time. */
 306         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 307                 IXGBE_CS4227_RESET_COMPLETE);
 308
 309 out:
 310         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 311         msec_delay(hw->eeprom.semaphore_delay);
 312 }
 313
 314 /**
 315  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 316  * @hw: pointer to hardware structure
 317  **/
 318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 319 {
 320         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 321
 322         if (hw->bus.lan_id) {
 323                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 324                 esdp |= IXGBE_ESDP_SDP1_DIR;
 325         }
 326         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 327         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 328         IXGBE_WRITE_FLUSH(hw);
 329 }
 330
 331 /**
 332  * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
 333  * @hw: pointer to hardware structure
 334  * @reg_addr: 32 bit address of PHY register to read
 335  * @dev_type: always unused
 336  * @phy_data: Pointer to read data from PHY register
 337  */
 338 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 339                                      u32 dev_type, u16 *phy_data)
 340 {
 341         u32 i, data, command;
 342         UNREFERENCED_1PARAMETER(dev_type);
 343
 344         /* Setup and write the read command */
 345         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 346                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 347                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
 348                   IXGBE_MSCA_MDI_COMMAND;
 349
 350         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 351
 352         /* Check every 10 usec to see if the access completed.
 353          * The MDI Command bit will clear when the operation is
 354          * complete
 355          */
 356         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 357                 usec_delay(10);
 358
 359                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 360                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 361                         break;
 362         }
 363
 364         if (command & IXGBE_MSCA_MDI_COMMAND) {
 365                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 366                               "PHY read command did not complete.\n");
 367                 return IXGBE_ERR_PHY;
 368         }
 369
 370         /* Read operation is complete.  Get the data from MSRWD */
 371         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 372         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 373         *phy_data = (u16)data;
 374
 375         return IXGBE_SUCCESS;
 376 }
 377
 378 /**
 379  * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
 380  * @hw: pointer to hardware structure
 381  * @reg_addr: 32 bit PHY register to write
 382  * @dev_type: always unused
 383  * @phy_data: Data to write to the PHY register
 384  */
 385 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 386                                       u32 dev_type, u16 phy_data)
 387 {
 388         u32 i, command;
 389         UNREFERENCED_1PARAMETER(dev_type);
 390
 391         /* Put the data in the MDI single read and write data register*/
 392         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 393
 394         /* Setup and write the write command */
 395         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 396                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 397                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
 398                   IXGBE_MSCA_MDI_COMMAND;
 399
 400         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 401
 402         /* Check every 10 usec to see if the access completed.
 403          * The MDI Command bit will clear when the operation is
 404          * complete
 405          */
 406         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 407                 usec_delay(10);
 408
 409                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 410                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 411                         break;
 412         }
 413
 414         if (command & IXGBE_MSCA_MDI_COMMAND) {
 415                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 416                               "PHY write cmd didn't complete\n");
 417                 return IXGBE_ERR_PHY;
 418         }
 419
 420         return IXGBE_SUCCESS;
 421 }
 422
 423 /**
 424  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 425  * @hw: pointer to hardware structure
 426  *
 427  * Returns error code
 428  */
 429 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 430 {
 431         switch (hw->device_id) {
 432         case IXGBE_DEV_ID_X550EM_A_SFP:
 433                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
 434                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
 435                 if (hw->bus.lan_id)
 436                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 437                 else
 438                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 439                 return ixgbe_identify_module_generic(hw);
 440         case IXGBE_DEV_ID_X550EM_X_SFP:
 441                 /* set up for CS4227 usage */
 442                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 443                 ixgbe_setup_mux_ctl(hw);
 444                 ixgbe_check_cs4227(hw);
 445                 /* Fallthrough */
 446
 447         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 448                 return ixgbe_identify_module_generic(hw);
 449                 break;
 450         case IXGBE_DEV_ID_X550EM_X_KX4:
 451                 hw->phy.type = ixgbe_phy_x550em_kx4;
 452                 break;
 453         case IXGBE_DEV_ID_X550EM_X_KR:
 454         case IXGBE_DEV_ID_X550EM_A_KR:
 455         case IXGBE_DEV_ID_X550EM_A_KR_L:
 456                 hw->phy.type = ixgbe_phy_x550em_kr;
 457                 break;
 458         case IXGBE_DEV_ID_X550EM_A_10G_T:
 459                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
 460                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
 461        /* Fallthrough to ixgbe_identify_phy_generic */
 462         case IXGBE_DEV_ID_X550EM_A_1G_T:
 463         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 464         case IXGBE_DEV_ID_X550EM_X_1G_T:
 465         case IXGBE_DEV_ID_X550EM_X_10G_T:
 466                 return ixgbe_identify_phy_generic(hw);
 467         default:
 468                 break;
 469         }
 470         return IXGBE_SUCCESS;
 471 }
 472
 473 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 474                                      u32 device_type, u16 *phy_data)
 475 {
 476         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 477         return IXGBE_NOT_IMPLEMENTED;
 478 }
 479
 480 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 481                                       u32 device_type, u16 phy_data)
 482 {
 483         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 484         return IXGBE_NOT_IMPLEMENTED;
 485 }
 486
 487 /**
 488  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 489  * @hw: pointer to the hardware structure
 490  * @addr: I2C bus address to read from
 491  * @reg: I2C device register to read from
 492  * @val: pointer to location to receive read value
 493  *
 494  * Returns an error code on error.
 495  **/
 496 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 497                                            u16 reg, u16 *val)
 498 {
 499         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 500 }
 501
 502 /**
 503  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 504  * @hw: pointer to the hardware structure
 505  * @addr: I2C bus address to read from
 506  * @reg: I2C device register to read from
 507  * @val: pointer to location to receive read value
 508  *
 509  * Returns an error code on error.
 510  **/
 511 STATIC s32
 512 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 513                                          u16 reg, u16 *val)
 514 {
 515         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 516 }
 517
 518 /**
 519  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 520  * @hw: pointer to the hardware structure
 521  * @addr: I2C bus address to write to
 522  * @reg: I2C device register to write to
 523  * @val: value to write
 524  *
 525  * Returns an error code on error.
 526  **/
 527 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 528                                             u8 addr, u16 reg, u16 val)
 529 {
 530         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 531 }
 532
 533 /**
 534  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 535  * @hw: pointer to the hardware structure
 536  * @addr: I2C bus address to write to
 537  * @reg: I2C device register to write to
 538  * @val: value to write
 539  *
 540  * Returns an error code on error.
 541  **/
 542 STATIC s32
 543 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 544                                           u8 addr, u16 reg, u16 val)
 545 {
 546         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 547 }
 548
 549 /**
 550 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 551 *  @hw: pointer to hardware structure
 552 *
 553 *  Initialize the function pointers and for MAC type X550EM.
 554 *  Does not touch the hardware.
 555 **/
 556 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 557 {
 558         struct ixgbe_mac_info *mac = &hw->mac;
 559         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 560         struct ixgbe_phy_info *phy = &hw->phy;
 561         s32 ret_val;
 562
 563         DEBUGFUNC("ixgbe_init_ops_X550EM");
 564
 565         /* Similar to X550 so start there. */
 566         ret_val = ixgbe_init_ops_X550(hw);
 567
 568         /* Since this function eventually calls
 569          * ixgbe_init_ops_540 by design, we are setting
 570          * the pointers to NULL explicitly here to overwrite
 571          * the values being set in the x540 function.
 572          */
 573         /* Thermal sensor not supported in x550EM */
 574         mac->ops.get_thermal_sensor_data = NULL;
 575         mac->ops.init_thermal_sensor_thresh = NULL;
 576         mac->thermal_sensor_enabled = false;
 577
 578         /* FCOE not supported in x550EM */
 579         mac->ops.get_san_mac_addr = NULL;
 580         mac->ops.set_san_mac_addr = NULL;
 581         mac->ops.get_wwn_prefix = NULL;
 582         mac->ops.get_fcoe_boot_status = NULL;
 583
 584         /* IPsec not supported in x550EM */
 585         mac->ops.disable_sec_rx_path = NULL;
 586         mac->ops.enable_sec_rx_path = NULL;
 587
 588         /* AUTOC register is not present in x550EM. */
 589         mac->ops.prot_autoc_read = NULL;
 590         mac->ops.prot_autoc_write = NULL;
 591
 592         /* X550EM bus type is internal*/
 593         hw->bus.type = ixgbe_bus_type_internal;
 594         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 595
 596
 597         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 598         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 599         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 600         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 601         mac->ops.get_supported_physical_layer =
 602                                     ixgbe_get_supported_physical_layer_X550em;
 603
 604         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 605                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 606         else
 607                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 608
 609         switch (hw->device_id) {
 610         case IXGBE_DEV_ID_X550EM_X_KR:
 611         case IXGBE_DEV_ID_X550EM_A_KR:
 612         case IXGBE_DEV_ID_X550EM_A_KR_L:
 613                 break;
 614         default:
 615                 mac->ops.setup_eee = NULL;
 616         }
 617
 618         /* PHY */
 619         phy->ops.init = ixgbe_init_phy_ops_X550em;
 620         phy->ops.identify = ixgbe_identify_phy_x550em;
 621         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 622                 phy->ops.set_phy_power = NULL;
 623
 624
 625         /* EEPROM */
 626         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 627         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 628         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 629         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 630         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 631         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 632         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 633         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 634
 635         return ret_val;
 636 }
 637
 638 /**
 639 *  ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
 640 *  @hw: pointer to hardware structure
 641 *
 642 *  Initialize the function pointers and for MAC type X550EM_a.
 643 *  Does not touch the hardware.
 644 **/
 645 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
 646 {
 647         struct ixgbe_mac_info *mac = &hw->mac;
 648         s32 ret_val;
 649
 650         DEBUGFUNC("ixgbe_init_ops_X550EM_a");
 651
 652         /* Start with generic X550EM init */
 653         ret_val = ixgbe_init_ops_X550EM(hw);
 654
 655         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 656         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 657         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 658         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 659         mac->ops.setup_fc = ixgbe_setup_fc_x550a;
 660         mac->ops.fc_autoneg = ixgbe_fc_autoneg_x550a;
 661
 662         return ret_val;
 663 }
 664
 665 /**
 666 *  ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
 667 *  @hw: pointer to hardware structure
 668 *
 669 *  Initialize the function pointers and for MAC type X550EM_x.
 670 *  Does not touch the hardware.
 671 **/
 672 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
 673 {
 674         struct ixgbe_mac_info *mac = &hw->mac;
 675         struct ixgbe_link_info *link = &hw->link;
 676         s32 ret_val;
 677
 678         DEBUGFUNC("ixgbe_init_ops_X550EM_x");
 679
 680         /* Start with generic X550EM init */
 681         ret_val = ixgbe_init_ops_X550EM(hw);
 682
 683         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 684         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 685         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 686         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 687         link->ops.read_link = ixgbe_read_i2c_combined_generic;
 688         link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
 689         link->ops.write_link = ixgbe_write_i2c_combined_generic;
 690         link->ops.write_link_unlocked =
 691                                       ixgbe_write_i2c_combined_generic_unlocked;
 692         link->addr = IXGBE_CS4227;
 693
 694         return ret_val;
 695 }
 696
 697 /**
 698  *  ixgbe_dmac_config_X550
 699  *  @hw: pointer to hardware structure
 700  *
 701  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 702  *  When disabling dmac, dmac enable dmac bit is cleared.
 703  **/
 704 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 705 {
 706         u32 reg, high_pri_tc;
 707
 708         DEBUGFUNC("ixgbe_dmac_config_X550");
 709
 710         /* Disable DMA coalescing before configuring */
 711         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 712         reg &= ~IXGBE_DMACR_DMAC_EN;
 713         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 714
 715         /* Disable DMA Coalescing if the watchdog timer is 0 */
 716         if (!hw->mac.dmac_config.watchdog_timer)
 717                 goto out;
 718
 719         ixgbe_dmac_config_tcs_X550(hw);
 720
 721         /* Configure DMA Coalescing Control Register */
 722         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 723
 724         /* Set the watchdog timer in units of 40.96 usec */
 725         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 726         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 727
 728         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 729         /* If fcoe is enabled, set high priority traffic class */
 730         if (hw->mac.dmac_config.fcoe_en) {
 731                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 732                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 733                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 734         }
 735         reg |= IXGBE_DMACR_EN_MNG_IND;
 736
 737         /* Enable DMA coalescing after configuration */
 738         reg |= IXGBE_DMACR_DMAC_EN;
 739         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 740
 741 out:
 742         return IXGBE_SUCCESS;
 743 }
 744
 745 /**
 746  *  ixgbe_dmac_config_tcs_X550
 747  *  @hw: pointer to hardware structure
 748  *
 749  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 750  *  be cleared before configuring.
 751  **/
 752 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 753 {
 754         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 755
 756         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 757
 758         /* Configure DMA coalescing enabled */
 759         switch (hw->mac.dmac_config.link_speed) {
 760         case IXGBE_LINK_SPEED_100_FULL:
 761                 pb_headroom = IXGBE_DMACRXT_100M;
 762                 break;
 763         case IXGBE_LINK_SPEED_1GB_FULL:
 764                 pb_headroom = IXGBE_DMACRXT_1G;
 765                 break;
 766         default:
 767                 pb_headroom = IXGBE_DMACRXT_10G;
 768                 break;
 769         }
 770
 771         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 772                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 773
 774         /* Set the per Rx packet buffer receive threshold */
 775         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 776                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 777                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 778
 779                 if (tc < hw->mac.dmac_config.num_tcs) {
 780                         /* Get Rx PB size */
 781                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 782                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 783                                 IXGBE_RXPBSIZE_SHIFT;
 784
 785                         /* Calculate receive buffer threshold in kilobytes */
 786                         if (rx_pb_size > pb_headroom)
 787                                 rx_pb_size = rx_pb_size - pb_headroom;
 788                         else
 789                                 rx_pb_size = 0;
 790
 791                         /* Minimum of MFS shall be set for DMCTH */
 792                         reg |= (rx_pb_size > maxframe_size_kb) ?
 793                                 rx_pb_size : maxframe_size_kb;
 794                 }
 795                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 796         }
 797         return IXGBE_SUCCESS;
 798 }
 799
 800 /**
 801  *  ixgbe_dmac_update_tcs_X550
 802  *  @hw: pointer to hardware structure
 803  *
 804  *  Disables dmac, updates per TC settings, and then enables dmac.
 805  **/
 806 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 807 {
 808         u32 reg;
 809
 810         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 811
 812         /* Disable DMA coalescing before configuring */
 813         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 814         reg &= ~IXGBE_DMACR_DMAC_EN;
 815         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 816
 817         ixgbe_dmac_config_tcs_X550(hw);
 818
 819         /* Enable DMA coalescing after configuration */
 820         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 821         reg |= IXGBE_DMACR_DMAC_EN;
 822         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 823
 824         return IXGBE_SUCCESS;
 825 }
 826
 827 /**
 828  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 829  *  @hw: pointer to hardware structure
 830  *
 831  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 832  *  ixgbe_hw struct in order to set up EEPROM access.
 833  **/
 834 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 835 {
 836         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 837         u32 eec;
 838         u16 eeprom_size;
 839
 840         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 841
 842         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 843                 eeprom->semaphore_delay = 10;
 844                 eeprom->type = ixgbe_flash;
 845
 846                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 847                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 848                                     IXGBE_EEC_SIZE_SHIFT);
 849                 eeprom->word_size = 1 << (eeprom_size +
 850                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 851
 852                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 853                           eeprom->type, eeprom->word_size);
 854         }
 855
 856         return IXGBE_SUCCESS;
 857 }
 858
 859 /**
 860  * ixgbe_enable_eee_x550 - Enable EEE support
 861  * @hw: pointer to hardware structure
 862  */
 863 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
 864 {
 865         u16 autoneg_eee_reg;
 866         u32 link_reg;
 867         s32 status;
 868
 869         if (hw->mac.type == ixgbe_mac_X550) {
 870                 /* Advertise EEE capability */
 871                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 872                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 873                                      &autoneg_eee_reg);
 874
 875                 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 876                                     IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 877                                     IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 878
 879                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 880                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 881                                       autoneg_eee_reg);
 882                 return IXGBE_SUCCESS;
 883         }
 884
 885         switch (hw->device_id) {
 886         case IXGBE_DEV_ID_X550EM_X_KR:
 887         case IXGBE_DEV_ID_X550EM_A_KR:
 888         case IXGBE_DEV_ID_X550EM_A_KR_L:
 889                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 890                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 891                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 892                 if (status != IXGBE_SUCCESS)
 893                         return status;
 894
 895                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 896                         IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 897
 898                 /* Don't advertise FEC capability when EEE enabled. */
 899                 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 900
 901                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 902                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 903                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 904                 if (status != IXGBE_SUCCESS)
 905                         return status;
 906                 break;
 907         default:
 908                 break;
 909         }
 910
 911         return IXGBE_SUCCESS;
 912 }
 913
 914 /**
 915  * ixgbe_disable_eee_x550 - Disable EEE support
 916  * @hw: pointer to hardware structure
 917  */
 918 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
 919 {
 920         u16 autoneg_eee_reg;
 921         u32 link_reg;
 922         s32 status;
 923
 924         if (hw->mac.type == ixgbe_mac_X550) {
 925                 /* Disable advertised EEE capability */
 926                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 927                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 928                                      &autoneg_eee_reg);
 929
 930                 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 931                                      IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 932                                      IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 933
 934                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 935                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 936                                       autoneg_eee_reg);
 937                 return IXGBE_SUCCESS;
 938         }
 939
 940         switch (hw->device_id) {
 941         case IXGBE_DEV_ID_X550EM_X_KR:
 942         case IXGBE_DEV_ID_X550EM_A_KR:
 943         case IXGBE_DEV_ID_X550EM_A_KR_L:
 944                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 945                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 946                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 947                 if (status != IXGBE_SUCCESS)
 948                         return status;
 949
 950                 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 951                               IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 952
 953                 /* Advertise FEC capability when EEE is disabled. */
 954                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 955
 956                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 957                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 958                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 959                 if (status != IXGBE_SUCCESS)
 960                         return status;
 961                 break;
 962         default:
 963                 break;
 964         }
 965
 966         return IXGBE_SUCCESS;
 967 }
 968
 969 /**
 970  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 971  *  @hw: pointer to the HW structure
 972  *  @enable_eee: boolean flag to enable EEE
 973  *
 974  *  Enable/disable EEE based on enable_eee flag.
 975  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 976  *  are modified.
 977  *
 978  **/
 979 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 980 {
 981         s32 status;
 982         u32 eeer;
 983
 984         DEBUGFUNC("ixgbe_setup_eee_X550");
 985
 986         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 987         /* Enable or disable EEE per flag */
 988         if (enable_eee) {
 989                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 990
 991                 /* Not supported on first revision of X550EM_x. */
 992                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
 993                     !(IXGBE_FUSES0_REV_MASK &
 994                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
 995                         return IXGBE_SUCCESS;
 996                 status = ixgbe_enable_eee_x550(hw);
 997                 if (status)
 998                         return status;
 999         } else {
1000                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1001
1002                 status = ixgbe_disable_eee_x550(hw);
1003                 if (status)
1004                         return status;
1005         }
1006         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1007
1008         return IXGBE_SUCCESS;
1009 }
1010
1011 /**
1012  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1013  * @hw: pointer to hardware structure
1014  * @enable: enable or disable source address pruning
1015  * @pool: Rx pool to set source address pruning for
1016  **/
1017 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1018                                            unsigned int pool)
1019 {
1020         u64 pfflp;
1021
1022         /* max rx pool is 63 */
1023         if (pool > 63)
1024                 return;
1025
1026         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1027         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1028
1029         if (enable)
1030                 pfflp |= (1ULL << pool);
1031         else
1032                 pfflp &= ~(1ULL << pool);
1033
1034         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1035         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1036 }
1037
1038 /**
1039  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1040  *  @hw: pointer to hardware structure
1041  *  @enable: enable or disable switch for Ethertype anti-spoofing
1042  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1043  *
1044  **/
1045 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1046                 bool enable, int vf)
1047 {
1048         int vf_target_reg = vf >> 3;
1049         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1050         u32 pfvfspoof;
1051
1052         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1053
1054         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1055         if (enable)
1056                 pfvfspoof |= (1 << vf_target_shift);
1057         else
1058                 pfvfspoof &= ~(1 << vf_target_shift);
1059
1060         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1061 }
1062
1063 /**
1064  * ixgbe_iosf_wait - Wait for IOSF command completion
1065  * @hw: pointer to hardware structure
1066  * @ctrl: pointer to location to receive final IOSF control value
1067  *
1068  * Returns failing status on timeout
1069  *
1070  * Note: ctrl can be NULL if the IOSF control register value is not needed
1071  **/
1072 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1073 {
1074         u32 i, command = 0;
1075
1076         /* Check every 10 usec to see if the address cycle completed.
1077          * The SB IOSF BUSY bit will clear when the operation is
1078          * complete
1079          */
1080         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1081                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1082                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1083                         break;
1084                 usec_delay(10);
1085         }
1086         if (ctrl)
1087                 *ctrl = command;
1088         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1089                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1090                 return IXGBE_ERR_PHY;
1091         }
1092
1093         return IXGBE_SUCCESS;
1094 }
1095
1096 /**
1097  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1098  *  device
1099  *  @hw: pointer to hardware structure
1100  *  @reg_addr: 32 bit PHY register to write
1101  *  @device_type: 3 bit device type
1102  *  @data: Data to write to the register
1103  **/
1104 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1105                             u32 device_type, u32 data)
1106 {
1107         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1108         u32 command, error;
1109         s32 ret;
1110
1111         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1112         if (ret != IXGBE_SUCCESS)
1113                 return ret;
1114
1115         ret = ixgbe_iosf_wait(hw, NULL);
1116         if (ret != IXGBE_SUCCESS)
1117                 goto out;
1118
1119         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1120                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1121
1122         /* Write IOSF control register */
1123         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1124
1125         /* Write IOSF data register */
1126         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1127
1128         ret = ixgbe_iosf_wait(hw, &command);
1129
1130         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1131                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1132                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1133                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1134                               "Failed to write, error %x\n", error);
1135                 ret = IXGBE_ERR_PHY;
1136         }
1137
1138 out:
1139         ixgbe_release_swfw_semaphore(hw, gssr);
1140         return ret;
1141 }
1142
1143 /**
1144  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1145  *  device
1146  *  @hw: pointer to hardware structure
1147  *  @reg_addr: 32 bit PHY register to write
1148  *  @device_type: 3 bit device type
1149  *  @phy_data: Pointer to read data from the register
1150  **/
1151 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1152                            u32 device_type, u32 *data)
1153 {
1154         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1155         u32 command, error;
1156         s32 ret;
1157
1158         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1159         if (ret != IXGBE_SUCCESS)
1160                 return ret;
1161
1162         ret = ixgbe_iosf_wait(hw, NULL);
1163         if (ret != IXGBE_SUCCESS)
1164                 goto out;
1165
1166         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1167                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1168
1169         /* Write IOSF control register */
1170         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1171
1172         ret = ixgbe_iosf_wait(hw, &command);
1173
1174         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1175                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1176                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1177                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1178                                 "Failed to read, error %x\n", error);
1179                 ret = IXGBE_ERR_PHY;
1180         }
1181
1182         if (ret == IXGBE_SUCCESS)
1183                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1184
1185 out:
1186         ixgbe_release_swfw_semaphore(hw, gssr);
1187         return ret;
1188 }
1189
1190 /**
1191  * ixgbe_get_phy_token - Get the token for shared phy access
1192  * @hw: Pointer to hardware structure
1193  */
1194
1195 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1196 {
1197         struct ixgbe_hic_phy_token_req token_cmd;
1198         s32 status;
1199
1200         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1201         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1202         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1203         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1204         token_cmd.port_number = hw->bus.lan_id;
1205         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1206         token_cmd.pad = 0;
1207         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1208                                               sizeof(token_cmd),
1209                                               IXGBE_HI_COMMAND_TIMEOUT,
1210                                               true);
1211         if (status)
1212                 return status;
1213         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1214                 return IXGBE_SUCCESS;
1215         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1216                 return IXGBE_ERR_FW_RESP_INVALID;
1217
1218         return IXGBE_ERR_TOKEN_RETRY;
1219 }
1220
1221 /**
1222  * ixgbe_put_phy_token - Put the token for shared phy access
1223  * @hw: Pointer to hardware structure
1224  */
1225
1226 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1227 {
1228         struct ixgbe_hic_phy_token_req token_cmd;
1229         s32 status;
1230
1231         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1232         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1233         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1234         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1235         token_cmd.port_number = hw->bus.lan_id;
1236         token_cmd.command_type = FW_PHY_TOKEN_REL;
1237         token_cmd.pad = 0;
1238         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1239                                               sizeof(token_cmd),
1240                                               IXGBE_HI_COMMAND_TIMEOUT,
1241                                               true);
1242         if (status)
1243                 return status;
1244         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1245                 return IXGBE_SUCCESS;
1246
1247         DEBUGOUT("Put PHY Token host interface command failed");
1248         return IXGBE_ERR_FW_RESP_INVALID;
1249 }
1250
1251 /**
1252  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1253  *  of the IOSF device
1254  *  @hw: pointer to hardware structure
1255  *  @reg_addr: 32 bit PHY register to write
1256  *  @device_type: 3 bit device type
1257  *  @data: Data to write to the register
1258  **/
1259 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1260                                   u32 device_type, u32 data)
1261 {
1262         struct ixgbe_hic_internal_phy_req write_cmd;
1263         s32 status;
1264         UNREFERENCED_1PARAMETER(device_type);
1265
1266         memset(&write_cmd, 0, sizeof(write_cmd));
1267         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1268         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1269         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1270         write_cmd.port_number = hw->bus.lan_id;
1271         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1272         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1273         write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1274
1275         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1276                                               sizeof(write_cmd),
1277                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1278
1279         return status;
1280 }
1281
1282 /**
1283  *  ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
1284  *  of the IOSF device.
1285  *  @hw: pointer to hardware structure
1286  *  @reg_addr: 32 bit PHY register to write
1287  *  @device_type: 3 bit device type
1288  *  @data: Pointer to read data from the register
1289  **/
1290 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1291                                  u32 device_type, u32 *data)
1292 {
1293         union {
1294                 struct ixgbe_hic_internal_phy_req cmd;
1295                 struct ixgbe_hic_internal_phy_resp rsp;
1296         } hic;
1297         s32 status;
1298         UNREFERENCED_1PARAMETER(device_type);
1299
1300         memset(&hic, 0, sizeof(hic));
1301         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1302         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1303         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1304         hic.cmd.port_number = hw->bus.lan_id;
1305         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1306         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1307
1308         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1309                                               sizeof(hic.cmd),
1310                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1311
1312         /* Extract the register value from the response. */
1313         *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1314
1315         return status;
1316 }
1317
1318 /**
1319  *  ixgbe_disable_mdd_X550
1320  *  @hw: pointer to hardware structure
1321  *
1322  *  Disable malicious driver detection
1323  **/
1324 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1325 {
1326         u32 reg;
1327
1328         DEBUGFUNC("ixgbe_disable_mdd_X550");
1329
1330         /* Disable MDD for TX DMA and interrupt */
1331         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1332         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1333         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1334
1335         /* Disable MDD for RX and interrupt */
1336         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1337         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1338         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1339 }
1340
1341 /**
1342  *  ixgbe_enable_mdd_X550
1343  *  @hw: pointer to hardware structure
1344  *
1345  *  Enable malicious driver detection
1346  **/
1347 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1348 {
1349         u32 reg;
1350
1351         DEBUGFUNC("ixgbe_enable_mdd_X550");
1352
1353         /* Enable MDD for TX DMA and interrupt */
1354         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1355         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1356         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1357
1358         /* Enable MDD for RX and interrupt */
1359         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1360         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1361         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1362 }
1363
1364 /**
1365  *  ixgbe_restore_mdd_vf_X550
1366  *  @hw: pointer to hardware structure
1367  *  @vf: vf index
1368  *
1369  *  Restore VF that was disabled during malicious driver detection event
1370  **/
1371 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1372 {
1373         u32 idx, reg, num_qs, start_q, bitmask;
1374
1375         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1376
1377         /* Map VF to queues */
1378         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1379         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1380         case IXGBE_MRQC_VMDQRT8TCEN:
1381                 num_qs = 8;  /* 16 VFs / pools */
1382                 bitmask = 0x000000FF;
1383                 break;
1384         case IXGBE_MRQC_VMDQRSS32EN:
1385         case IXGBE_MRQC_VMDQRT4TCEN:
1386                 num_qs = 4;  /* 32 VFs / pools */
1387                 bitmask = 0x0000000F;
1388                 break;
1389         default:            /* 64 VFs / pools */
1390                 num_qs = 2;
1391                 bitmask = 0x00000003;
1392                 break;
1393         }
1394         start_q = vf * num_qs;
1395
1396         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1397         idx = start_q / 32;
1398         reg = 0;
1399         reg |= (bitmask << (start_q % 32));
1400         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1401         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1402 }
1403
1404 /**
1405  *  ixgbe_mdd_event_X550
1406  *  @hw: pointer to hardware structure
1407  *  @vf_bitmap: vf bitmap of malicious vfs
1408  *
1409  *  Handle malicious driver detection event.
1410  **/
1411 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1412 {
1413         u32 wqbr;
1414         u32 i, j, reg, q, shift, vf, idx;
1415
1416         DEBUGFUNC("ixgbe_mdd_event_X550");
1417
1418         /* figure out pool size for mapping to vf's */
1419         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1420         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1421         case IXGBE_MRQC_VMDQRT8TCEN:
1422                 shift = 3;  /* 16 VFs / pools */
1423                 break;
1424         case IXGBE_MRQC_VMDQRSS32EN:
1425         case IXGBE_MRQC_VMDQRT4TCEN:
1426                 shift = 2;  /* 32 VFs / pools */
1427                 break;
1428         default:
1429                 shift = 1;  /* 64 VFs / pools */
1430                 break;
1431         }
1432
1433         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1434         for (i = 0; i < 4; i++) {
1435                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1436                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1437
1438                 if (!wqbr)
1439                         continue;
1440
1441                 /* Get malicious queue */
1442                 for (j = 0; j < 32 && wqbr; j++) {
1443
1444                         if (!(wqbr & (1 << j)))
1445                                 continue;
1446
1447                         /* Get queue from bitmask */
1448                         q = j + (i * 32);
1449
1450                         /* Map queue to vf */
1451                         vf = (q >> shift);
1452
1453                         /* Set vf bit in vf_bitmap */
1454                         idx = vf / 32;
1455                         vf_bitmap[idx] |= (1 << (vf % 32));
1456                         wqbr &= ~(1 << j);
1457                 }
1458         }
1459 }
1460
1461 /**
1462  *  ixgbe_get_media_type_X550em - Get media type
1463  *  @hw: pointer to hardware structure
1464  *
1465  *  Returns the media type (fiber, copper, backplane)
1466  */
1467 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1468 {
1469         enum ixgbe_media_type media_type;
1470
1471         DEBUGFUNC("ixgbe_get_media_type_X550em");
1472
1473         /* Detect if there is a copper PHY attached. */
1474         switch (hw->device_id) {
1475         case IXGBE_DEV_ID_X550EM_X_KR:
1476         case IXGBE_DEV_ID_X550EM_X_KX4:
1477         case IXGBE_DEV_ID_X550EM_A_KR:
1478         case IXGBE_DEV_ID_X550EM_A_KR_L:
1479                 media_type = ixgbe_media_type_backplane;
1480                 break;
1481         case IXGBE_DEV_ID_X550EM_X_SFP:
1482         case IXGBE_DEV_ID_X550EM_A_SFP:
1483         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1484         case IXGBE_DEV_ID_X550EM_A_QSFP:
1485         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1486                 media_type = ixgbe_media_type_fiber;
1487                 break;
1488         case IXGBE_DEV_ID_X550EM_X_1G_T:
1489         case IXGBE_DEV_ID_X550EM_X_10G_T:
1490         case IXGBE_DEV_ID_X550EM_A_10G_T:
1491                 media_type = ixgbe_media_type_copper;
1492                 break;
1493         case IXGBE_DEV_ID_X550EM_A_SGMII:
1494         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1495                 media_type = ixgbe_media_type_backplane;
1496                 hw->phy.type = ixgbe_phy_sgmii;
1497                 break;
1498         case IXGBE_DEV_ID_X550EM_A_1G_T:
1499         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1500                 media_type = ixgbe_media_type_copper;
1501                 break;
1502         default:
1503                 media_type = ixgbe_media_type_unknown;
1504                 break;
1505         }
1506         return media_type;
1507 }
1508
1509 /**
1510  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1511  *  @hw: pointer to hardware structure
1512  *  @linear: true if SFP module is linear
1513  */
1514 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1515 {
1516         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1517
1518         switch (hw->phy.sfp_type) {
1519         case ixgbe_sfp_type_not_present:
1520                 return IXGBE_ERR_SFP_NOT_PRESENT;
1521         case ixgbe_sfp_type_da_cu_core0:
1522         case ixgbe_sfp_type_da_cu_core1:
1523                 *linear = true;
1524                 break;
1525         case ixgbe_sfp_type_srlr_core0:
1526         case ixgbe_sfp_type_srlr_core1:
1527         case ixgbe_sfp_type_da_act_lmt_core0:
1528         case ixgbe_sfp_type_da_act_lmt_core1:
1529         case ixgbe_sfp_type_1g_sx_core0:
1530         case ixgbe_sfp_type_1g_sx_core1:
1531         case ixgbe_sfp_type_1g_lx_core0:
1532         case ixgbe_sfp_type_1g_lx_core1:
1533                 *linear = false;
1534                 break;
1535         case ixgbe_sfp_type_unknown:
1536         case ixgbe_sfp_type_1g_cu_core0:
1537         case ixgbe_sfp_type_1g_cu_core1:
1538         default:
1539                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1540         }
1541
1542         return IXGBE_SUCCESS;
1543 }
1544
1545 /**
1546  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1547  *  @hw: pointer to hardware structure
1548  *
1549  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1550  **/
1551 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1552 {
1553         s32 status;
1554         bool linear;
1555
1556         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1557
1558         status = ixgbe_identify_module_generic(hw);
1559
1560         if (status != IXGBE_SUCCESS)
1561                 return status;
1562
1563         /* Check if SFP module is supported */
1564         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1565
1566         return status;
1567 }
1568
1569 /**
1570  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1571  *  @hw: pointer to hardware structure
1572  */
1573 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1574 {
1575         s32 status;
1576         bool linear;
1577
1578         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1579
1580         /* Check if SFP module is supported */
1581         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1582
1583         if (status != IXGBE_SUCCESS)
1584                 return status;
1585
1586         ixgbe_init_mac_link_ops_X550em(hw);
1587         hw->phy.ops.reset = NULL;
1588
1589         return IXGBE_SUCCESS;
1590 }
1591
1592 /**
1593  * ixgbe_setup_sgmii - Set up link for sgmii
1594  * @hw: pointer to hardware structure
1595  */
1596 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1597                              bool autoneg_wait)
1598 {
1599         struct ixgbe_mac_info *mac = &hw->mac;
1600         u32 lval, sval;
1601         s32 rc;
1602
1603         rc = mac->ops.read_iosf_sb_reg(hw,
1604                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1605                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1606         if (rc)
1607                 return rc;
1608
1609         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1610         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1611         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1612         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1613         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1614         rc = mac->ops.write_iosf_sb_reg(hw,
1615                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1616                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1617         if (rc)
1618                 return rc;
1619
1620         rc = mac->ops.read_iosf_sb_reg(hw,
1621                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1622                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1623         if (rc)
1624                 return rc;
1625
1626         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1627         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1628         rc = mac->ops.write_iosf_sb_reg(hw,
1629                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1630                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1631         if (rc)
1632                 return rc;
1633
1634         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1635         rc = mac->ops.write_iosf_sb_reg(hw,
1636                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1637                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1638         if (rc)
1639                 return rc;
1640
1641         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1642 }
1643
1644  /**
1645  * ixgbe_setup_sgmii_m88 - Set up link for sgmii with Marvell PHYs
1646  * @hw: pointer to hardware structure
1647  */
1648 STATIC s32 ixgbe_setup_sgmii_m88(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1649                                  bool autoneg_wait)
1650 {
1651         struct ixgbe_mac_info *mac = &hw->mac;
1652         u32 lval, sval;
1653         s32 rc;
1654
1655         rc = mac->ops.read_iosf_sb_reg(hw,
1656                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1657                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1658         if (rc)
1659                 return rc;
1660
1661         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1662         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1663         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1664         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1665         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1666         rc = mac->ops.write_iosf_sb_reg(hw,
1667                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1668                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1669         if (rc)
1670                 return rc;
1671
1672         rc = mac->ops.read_iosf_sb_reg(hw,
1673                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1674                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1675         if (rc)
1676                 return rc;
1677
1678         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1679         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1680         rc = mac->ops.write_iosf_sb_reg(hw,
1681                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1682                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1683         if (rc)
1684                 return rc;
1685
1686         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1687         rc = mac->ops.write_iosf_sb_reg(hw,
1688                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1689                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1690         if (rc)
1691                 return rc;
1692
1693         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1694 }
1695
1696 /**
1697  * ixgbe_check_link_m88 - Poll PHY for link
1698  * @hw: pointer to hardware structure
1699  * @speed: pointer to link speed
1700  * @link_up: true when link is up
1701  * @link_up_wait: bool indicating whether to wait for link
1702  *
1703  * Check that both the MAC and PHY have link.
1704  */
1705 static s32
1706 ixgbe_check_link_m88(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1707                      bool *link_up, bool link_up_wait)
1708 {
1709         u16 reg;
1710         s32 rc;
1711         u32 i;
1712
1713         rc = ixgbe_check_mac_link_generic(hw, speed, link_up, link_up_wait);
1714         if (rc || !*link_up)
1715                 return rc;
1716
1717         rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_PHY_SPEC_STATUS, 0, &reg);
1718
1719         /* MAC link is up, so check external PHY link */
1720         *link_up = !!(reg & IXGBE_M88E1500_PHY_SPEC_STATUS_LINK);
1721
1722         if (link_up_wait) {
1723                 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
1724                         if (!rc &&
1725                             (reg & IXGBE_M88E1500_PHY_SPEC_STATUS_LINK)) {
1726                                 *link_up = true;
1727                                 break;
1728                         }
1729                         *link_up = false;
1730                         msec_delay(100);
1731                         rc = hw->phy.ops.read_reg(hw,
1732                                                  IXGBE_M88E1500_PHY_SPEC_STATUS,
1733                                                  0, &reg);
1734                 }
1735         }
1736
1737 #define M88_SPEED(x) (IXGBE_M88E1500_PHY_SPEC_STATUS_RESOLVED  | \
1738                       IXGBE_M88E1500_PHY_SPEC_STATUS_DUPLEX     | \
1739                       ((IXGBE_M88E1500_PHY_SPEC_STATUS_SPEED_##x) <<\
1740                         IXGBE_M88E1500_PHY_SPEC_STATUS_SPEED_SHIFT))
1741
1742         reg &= M88_SPEED(MASK);
1743         switch (reg) {
1744         case M88_SPEED(10):
1745                 *speed = IXGBE_LINK_SPEED_10_FULL;
1746                 break;
1747         case M88_SPEED(100):
1748                 *speed = IXGBE_LINK_SPEED_100_FULL;
1749                 break;
1750         case M88_SPEED(1000):
1751                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1752                 break;
1753         default:
1754                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1755                 break;
1756         }
1757 #undef M88_SPEED
1758
1759         return rc;
1760 }
1761
1762 /**
1763  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1764  *  @hw: pointer to hardware structure
1765  */
1766 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1767 {
1768         struct ixgbe_mac_info *mac = &hw->mac;
1769
1770         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1771
1772         switch (hw->mac.ops.get_media_type(hw)) {
1773         case ixgbe_media_type_fiber:
1774                 /* CS4227 does not support autoneg, so disable the laser control
1775                  * functions for SFP+ fiber
1776                  */
1777                 mac->ops.disable_tx_laser = NULL;
1778                 mac->ops.enable_tx_laser = NULL;
1779                 mac->ops.flap_tx_laser = NULL;
1780                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1781                 mac->ops.set_rate_select_speed =
1782                                         ixgbe_set_soft_rate_select_speed;
1783                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1784                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1785                         mac->ops.setup_mac_link =
1786                                 ixgbe_setup_mac_link_sfp_x550a;
1787                 else
1788                         mac->ops.setup_mac_link =
1789                                 ixgbe_setup_mac_link_sfp_x550em;
1790                 break;
1791         case ixgbe_media_type_copper:
1792                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1793                     hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1794                         mac->ops.setup_link = ixgbe_setup_sgmii_m88;
1795                         mac->ops.check_link = ixgbe_check_link_m88;
1796                 } else {
1797                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1798                         mac->ops.check_link = ixgbe_check_link_t_X550em;
1799                 }
1800                 break;
1801         case ixgbe_media_type_backplane:
1802                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1803                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1804                         mac->ops.setup_link = ixgbe_setup_sgmii;
1805                 break;
1806         default:
1807                 break;
1808         }
1809 }
1810
1811 /**
1812  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1813  *  @hw: pointer to hardware structure
1814  *  @speed: pointer to link speed
1815  *  @autoneg: true when autoneg or autotry is enabled
1816  */
1817 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1818                                        ixgbe_link_speed *speed,
1819                                        bool *autoneg)
1820 {
1821         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1822
1823         /* SFP */
1824         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1825
1826                 /* CS4227 SFP must not enable auto-negotiation */
1827                 *autoneg = false;
1828
1829                 /* Check if 1G SFP module. */
1830                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1831                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1832                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1833                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1834                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1835                         return IXGBE_SUCCESS;
1836                 }
1837
1838                 /* Link capabilities are based on SFP */
1839                 if (hw->phy.multispeed_fiber)
1840                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1841                                  IXGBE_LINK_SPEED_1GB_FULL;
1842                 else
1843                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1844         } else {
1845                 switch (hw->phy.type) {
1846                 case ixgbe_phy_m88:
1847                         *speed = IXGBE_LINK_SPEED_1GB_FULL |
1848                                  IXGBE_LINK_SPEED_100_FULL |
1849                                  IXGBE_LINK_SPEED_10_FULL;
1850                         break;
1851                 case ixgbe_phy_sgmii:
1852                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1853                         break;
1854                 default:
1855                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1856                                  IXGBE_LINK_SPEED_1GB_FULL;
1857                         break;
1858                 }
1859                 *autoneg = true;
1860         }
1861
1862         return IXGBE_SUCCESS;
1863 }
1864
1865 /**
1866  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1867  * @hw: pointer to hardware structure
1868  * @lsc: pointer to boolean flag which indicates whether external Base T
1869  *       PHY interrupt is lsc
1870  *
1871  * Determime if external Base T PHY interrupt cause is high temperature
1872  * failure alarm or link status change.
1873  *
1874  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1875  * failure alarm, else return PHY access status.
1876  */
1877 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1878 {
1879         u32 status;
1880         u16 reg;
1881
1882         *lsc = false;
1883
1884         /* Vendor alarm triggered */
1885         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1886                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1887                                       &reg);
1888
1889         if (status != IXGBE_SUCCESS ||
1890             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1891                 return status;
1892
1893         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1894         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1895                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1896                                       &reg);
1897
1898         if (status != IXGBE_SUCCESS ||
1899             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1900             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1901                 return status;
1902
1903         /* Global alarm triggered */
1904         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1905                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1906                                       &reg);
1907
1908         if (status != IXGBE_SUCCESS)
1909                 return status;
1910
1911         /* If high temperature failure, then return over temp error and exit */
1912         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1913                 /* power down the PHY in case the PHY FW didn't already */
1914                 ixgbe_set_copper_phy_power(hw, false);
1915                 return IXGBE_ERR_OVERTEMP;
1916         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1917                 /*  device fault alarm triggered */
1918                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1919                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1920                                           &reg);
1921
1922                 if (status != IXGBE_SUCCESS)
1923                         return status;
1924
1925                 /* if device fault was due to high temp alarm handle and exit */
1926                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1927                         /* power down the PHY in case the PHY FW didn't */
1928                         ixgbe_set_copper_phy_power(hw, false);
1929                         return IXGBE_ERR_OVERTEMP;
1930                 }
1931         }
1932
1933         /* Vendor alarm 2 triggered */
1934         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1935                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1936
1937         if (status != IXGBE_SUCCESS ||
1938             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1939                 return status;
1940
1941         /* link connect/disconnect event occurred */
1942         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1943                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1944
1945         if (status != IXGBE_SUCCESS)
1946                 return status;
1947
1948         /* Indicate LSC */
1949         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1950                 *lsc = true;
1951
1952         return IXGBE_SUCCESS;
1953 }
1954
1955 /**
1956  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1957  * @hw: pointer to hardware structure
1958  *
1959  * Enable link status change and temperature failure alarm for the external
1960  * Base T PHY
1961  *
1962  * Returns PHY access status
1963  */
1964 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1965 {
1966         u32 status;
1967         u16 reg;
1968         bool lsc;
1969
1970         /* Clear interrupt flags */
1971         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1972
1973         /* Enable link status change alarm */
1974         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1975                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1976
1977         if (status != IXGBE_SUCCESS)
1978                 return status;
1979
1980         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1981
1982         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1983                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1984
1985         if (status != IXGBE_SUCCESS)
1986                 return status;
1987
1988         /* Enable high temperature failure and global fault alarms */
1989         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1990                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1991                                       &reg);
1992
1993         if (status != IXGBE_SUCCESS)
1994                 return status;
1995
1996         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1997                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1998
1999         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2000                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2001                                        reg);
2002
2003         if (status != IXGBE_SUCCESS)
2004                 return status;
2005
2006         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2007         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2008                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2009                                       &reg);
2010
2011         if (status != IXGBE_SUCCESS)
2012                 return status;
2013
2014         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2015                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2016
2017         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2018                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2019                                        reg);
2020
2021         if (status != IXGBE_SUCCESS)
2022                 return status;
2023
2024         /* Enable chip-wide vendor alarm */
2025         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2026                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2027                                       &reg);
2028
2029         if (status != IXGBE_SUCCESS)
2030                 return status;
2031
2032         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2033
2034         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2035                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2036                                        reg);
2037
2038         return status;
2039 }
2040
2041 /**
2042  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2043  *  @hw: pointer to hardware structure
2044  *  @speed: link speed
2045  *
2046  *  Configures the integrated KR PHY.
2047  **/
2048 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2049                                        ixgbe_link_speed speed)
2050 {
2051         s32 status;
2052         u32 reg_val;
2053
2054         status = hw->mac.ops.read_iosf_sb_reg(hw,
2055                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2056                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2057         if (status)
2058                 return status;
2059
2060         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2061         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2062                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2063
2064         /* Advertise 10G support. */
2065         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2066                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2067
2068         /* Advertise 1G support. */
2069         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2070                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2071
2072         /* Restart auto-negotiation. */
2073         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2074         status = hw->mac.ops.write_iosf_sb_reg(hw,
2075                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2076                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2077
2078         return status;
2079 }
2080
2081 /**
2082  * ixgbe_setup_m88 - setup m88 PHY
2083  * @hw: pointer to hardware structure
2084  */
2085 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2086 {
2087         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2088         u16 reg;
2089         s32 rc;
2090
2091         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2092                 return IXGBE_SUCCESS;
2093
2094         rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2095         if (rc)
2096                 return rc;
2097
2098         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2099         if (rc)
2100                 goto out;
2101         if (reg & IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN) {
2102                 reg &= ~IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN;
2103                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2104                                           reg);
2105         }
2106
2107         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, &reg);
2108         if (rc)
2109                 goto out;
2110         if (reg & IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN) {
2111                 reg &= ~IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN;
2112                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0,
2113                                           reg);
2114         }
2115
2116         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 2);
2117         if (rc)
2118                 goto out;
2119
2120         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2121                                       &reg);
2122         if (rc)
2123                 goto out;
2124         if (reg & IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN) {
2125                 reg &= ~IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN;
2126                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2127                                           reg);
2128                 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2129                                                0);
2130                 if (rc)
2131                         goto out;
2132                 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2133                                               &reg);
2134                 if (rc)
2135                         goto out;
2136                 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2137                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2138                                           reg);
2139                 usec_delay(50);
2140         } else {
2141                 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2142                                                0);
2143                 if (rc)
2144                         goto out;
2145         }
2146
2147         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2148         if (rc)
2149                 goto out;
2150
2151         if (!(reg & IXGBE_M88E1500_COPPER_CTRL_AN_EN)) {
2152                 reg |= IXGBE_M88E1500_COPPER_CTRL_AN_EN;
2153                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2154                                           reg);
2155         }
2156
2157         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, &reg);
2158         if (rc)
2159                 goto out;
2160         reg &= ~IXGBE_M88E1500_1000T_CTRL_HALF_DUPLEX;
2161         reg &= ~IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2162         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
2163                 reg |= IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2164         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, reg);
2165
2166         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, &reg);
2167         if (rc)
2168                 goto out;
2169         reg &= ~IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
2170         reg &= ~IXGBE_M88E1500_COPPER_AN_PAUSE;
2171         reg &= ~IXGBE_M88E1500_COPPER_AN_T4;
2172         reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_FD;
2173         reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_HD;
2174         reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_FD;
2175         reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_HD;
2176         switch (hw->fc.current_mode) {
2177         case ixgbe_fc_full:
2178                 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
2179                 break;
2180         case ixgbe_fc_rx_pause:
2181                 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
2182                 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
2183                 break;
2184         case ixgbe_fc_tx_pause:
2185                 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
2186                 break;
2187         default:
2188                 break;
2189         }
2190
2191         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
2192                 reg |= IXGBE_M88E1500_COPPER_AN_100TX_FD;
2193         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
2194                 reg |= IXGBE_M88E1500_COPPER_AN_10TX_FD;
2195         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, reg);
2196
2197         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2198         if (rc)
2199                 goto out;
2200         reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
2201         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2202
2203
2204         hw->mac.ops.release_swfw_sync(hw, mask);
2205         return rc;
2206
2207 out:
2208         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2209         hw->mac.ops.release_swfw_sync(hw, mask);
2210         return rc;
2211 }
2212
2213 /**
2214  * ixgbe_reset_phy_m88e1500 - Reset m88e1500 PHY
2215  * @hw: pointer to hardware structure
2216  *
2217  * The PHY token must be held when calling this function.
2218  */
2219 static s32 ixgbe_reset_phy_m88e1500(struct ixgbe_hw *hw)
2220 {
2221         u16 reg;
2222         s32 rc;
2223
2224         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2225         if (rc)
2226                 return rc;
2227
2228         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2229         if (rc)
2230                 return rc;
2231
2232         reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2233         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2234
2235         usec_delay(10);
2236
2237         return rc;
2238 }
2239
2240 /**
2241  * ixgbe_reset_phy_m88e1543 - Reset m88e1543 PHY
2242  * @hw: pointer to hardware structure
2243  *
2244  * The PHY token must be held when calling this function.
2245  */
2246 static s32 ixgbe_reset_phy_m88e1543(struct ixgbe_hw *hw)
2247 {
2248         return hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2249 }
2250
2251 /**
2252  * ixgbe_reset_phy_m88 - Reset m88 PHY
2253  * @hw: pointer to hardware structure
2254  */
2255 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2256 {
2257         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2258         u16 reg;
2259         s32 rc;
2260
2261         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2262                 return IXGBE_SUCCESS;
2263
2264         rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2265         if (rc)
2266                 return rc;
2267
2268         switch (hw->phy.id) {
2269         case IXGBE_M88E1500_E_PHY_ID:
2270                 rc = ixgbe_reset_phy_m88e1500(hw);
2271                 break;
2272         case IXGBE_M88E1543_E_PHY_ID:
2273                 rc = ixgbe_reset_phy_m88e1543(hw);
2274                 break;
2275         default:
2276                 rc = IXGBE_ERR_PHY;
2277                 break;
2278         }
2279
2280         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2281         if (rc)
2282                 goto out;
2283
2284         reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2285               IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2286               IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2287         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2288         if (rc)
2289                 goto out;
2290
2291         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2292         if (rc)
2293                 goto out;
2294
2295         reg = IXGBE_M88E1500_GEN_CTRL_RESET |
2296               IXGBE_M88E1500_GEN_CTRL_MODE_SGMII_COPPER;
2297         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_GEN_CTRL, 0, reg);
2298         if (rc)
2299                 goto out;
2300
2301         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2302         if (rc)
2303                 goto out;
2304
2305         reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2306               IXGBE_M88E1500_FIBER_CTRL_AN_EN |
2307               IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2308               IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2309         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2310         if (rc)
2311                 goto out;
2312
2313         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2314         if (rc)
2315                 goto out;
2316
2317         reg = (IXGBE_M88E1500_MAC_CTRL_1_DWN_4X <<
2318                IXGBE_M88E1500_MAC_CTRL_1_DWN_SHIFT) |
2319               (IXGBE_M88E1500_MAC_CTRL_1_ED_TM <<
2320                IXGBE_M88E1500_MAC_CTRL_1_ED_SHIFT) |
2321               (IXGBE_M88E1500_MAC_CTRL_1_MDIX_AUTO <<
2322                IXGBE_M88E1500_MAC_CTRL_1_MDIX_SHIFT);
2323         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, reg);
2324         if (rc)
2325                 goto out;
2326
2327         reg = IXGBE_M88E1500_COPPER_CTRL_RESET |
2328               IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2329               IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2330               IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2331               IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB;
2332         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2333         if (rc)
2334                 goto out;
2335
2336         hw->mac.ops.release_swfw_sync(hw, mask);
2337
2338         return ixgbe_setup_m88(hw);
2339
2340 out:
2341         hw->mac.ops.release_swfw_sync(hw, mask);
2342         return rc;
2343 }
2344
2345 /**
2346  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2347  *  @hw: pointer to hardware structure
2348  *
2349  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2350  *  values.
2351  **/
2352 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2353 {
2354         /* Save NW management interface connected on board. This is used
2355          * to determine internal PHY mode.
2356          */
2357         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2358
2359         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2360          * PHY address. This register field was has only been used for X552.
2361          */
2362         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2363             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2364                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2365                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2366                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2367         }
2368
2369         return IXGBE_SUCCESS;
2370 }
2371
2372 /**
2373  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2374  *  @hw: pointer to hardware structure
2375  *
2376  *  Initialize any function pointers that were not able to be
2377  *  set during init_shared_code because the PHY/SFP type was
2378  *  not known.  Perform the SFP init if necessary.
2379  */
2380 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2381 {
2382         struct ixgbe_phy_info *phy = &hw->phy;
2383         s32 ret_val;
2384
2385         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2386
2387         hw->mac.ops.set_lan_id(hw);
2388
2389         ixgbe_read_mng_if_sel_x550em(hw);
2390
2391         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2392                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2393                 ixgbe_setup_mux_ctl(hw);
2394                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2395         }
2396
2397         switch (hw->device_id) {
2398         case IXGBE_DEV_ID_X550EM_A_1G_T:
2399         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2400                 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2401                 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2402                 break;
2403         default:
2404                 break;
2405         }
2406
2407         /* Identify the PHY or SFP module */
2408         ret_val = phy->ops.identify(hw);
2409         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2410                 return ret_val;
2411
2412         /* Setup function pointers based on detected hardware */
2413         ixgbe_init_mac_link_ops_X550em(hw);
2414         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2415                 phy->ops.reset = NULL;
2416
2417         /* Set functions pointers based on phy type */
2418         switch (hw->phy.type) {
2419         case ixgbe_phy_x550em_kx4:
2420                 phy->ops.setup_link = NULL;
2421                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2422                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2423                 break;
2424         case ixgbe_phy_x550em_kr:
2425                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2426                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2427                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2428                 break;
2429         case ixgbe_phy_x550em_ext_t:
2430                 /* If internal link mode is XFI, then setup iXFI internal link,
2431                  * else setup KR now.
2432                  */
2433                 phy->ops.setup_internal_link =
2434                                               ixgbe_setup_internal_phy_t_x550em;
2435
2436                 /* setup SW LPLU only for first revision of X550EM_x */
2437                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2438                     !(IXGBE_FUSES0_REV_MASK &
2439                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2440                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2441
2442                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2443                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2444                 break;
2445         case ixgbe_phy_sgmii:
2446                 phy->ops.setup_link = NULL;
2447                 break;
2448         case ixgbe_phy_m88:
2449                 phy->ops.setup_link = ixgbe_setup_m88;
2450                 phy->ops.reset = ixgbe_reset_phy_m88;
2451                 break;
2452         default:
2453                 break;
2454         }
2455         return ret_val;
2456 }
2457
2458 /**
2459  * ixgbe_set_mdio_speed - Set MDIO clock speed
2460  *  @hw: pointer to hardware structure
2461  */
2462 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2463 {
2464         u32 hlreg0;
2465
2466         switch (hw->device_id) {
2467         case IXGBE_DEV_ID_X550EM_X_10G_T:
2468         case IXGBE_DEV_ID_X550EM_A_SGMII:
2469         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2470         case IXGBE_DEV_ID_X550EM_A_1G_T:
2471         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2472         case IXGBE_DEV_ID_X550EM_A_10G_T:
2473         case IXGBE_DEV_ID_X550EM_A_SFP:
2474         case IXGBE_DEV_ID_X550EM_A_QSFP:
2475                 /* Config MDIO clock speed before the first MDIO PHY access */
2476                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2477                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2478                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2479                 break;
2480         default:
2481                 break;
2482         }
2483 }
2484
2485 /**
2486  *  ixgbe_reset_hw_X550em - Perform hardware reset
2487  *  @hw: pointer to hardware structure
2488  *
2489  *  Resets the hardware by resetting the transmit and receive units, masks
2490  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2491  *  reset.
2492  */
2493 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2494 {
2495         ixgbe_link_speed link_speed;
2496         s32 status;
2497         u32 ctrl = 0;
2498         u32 i;
2499         bool link_up = false;
2500
2501         DEBUGFUNC("ixgbe_reset_hw_X550em");
2502
2503         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2504         status = hw->mac.ops.stop_adapter(hw);
2505         if (status != IXGBE_SUCCESS)
2506                 return status;
2507
2508         /* flush pending Tx transactions */
2509         ixgbe_clear_tx_pending(hw);
2510
2511         ixgbe_set_mdio_speed(hw);
2512
2513         /* PHY ops must be identified and initialized prior to reset */
2514         status = hw->phy.ops.init(hw);
2515
2516         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2517                 return status;
2518
2519         /* start the external PHY */
2520         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2521                 status = ixgbe_init_ext_t_x550em(hw);
2522                 if (status)
2523                         return status;
2524         }
2525
2526         /* Setup SFP module if there is one present. */
2527         if (hw->phy.sfp_setup_needed) {
2528                 status = hw->mac.ops.setup_sfp(hw);
2529                 hw->phy.sfp_setup_needed = false;
2530         }
2531
2532         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2533                 return status;
2534
2535         /* Reset PHY */
2536         if (!hw->phy.reset_disable && hw->phy.ops.reset)
2537                 hw->phy.ops.reset(hw);
2538
2539 mac_reset_top:
2540         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2541          * If link reset is used when link is up, it might reset the PHY when
2542          * mng is using it.  If link is down or the flag to force full link
2543          * reset is set, then perform link reset.
2544          */
2545         ctrl = IXGBE_CTRL_LNK_RST;
2546         if (!hw->force_full_reset) {
2547                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2548                 if (link_up)
2549                         ctrl = IXGBE_CTRL_RST;
2550         }
2551
2552         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2553         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2554         IXGBE_WRITE_FLUSH(hw);
2555
2556         /* Poll for reset bit to self-clear meaning reset is complete */
2557         for (i = 0; i < 10; i++) {
2558                 usec_delay(1);
2559                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2560                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2561                         break;
2562         }
2563
2564         if (ctrl & IXGBE_CTRL_RST_MASK) {
2565                 status = IXGBE_ERR_RESET_FAILED;
2566                 DEBUGOUT("Reset polling failed to complete.\n");
2567         }
2568
2569         msec_delay(50);
2570
2571         /* Double resets are required for recovery from certain error
2572          * conditions.  Between resets, it is necessary to stall to
2573          * allow time for any pending HW events to complete.
2574          */
2575         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2576                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2577                 goto mac_reset_top;
2578         }
2579
2580         /* Store the permanent mac address */
2581         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2582
2583         /* Store MAC address from RAR0, clear receive address registers, and
2584          * clear the multicast table.  Also reset num_rar_entries to 128,
2585          * since we modify this value when programming the SAN MAC address.
2586          */
2587         hw->mac.num_rar_entries = 128;
2588         hw->mac.ops.init_rx_addrs(hw);
2589
2590         ixgbe_set_mdio_speed(hw);
2591
2592         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2593                 ixgbe_setup_mux_ctl(hw);
2594
2595         return status;
2596 }
2597
2598 /**
2599  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2600  * @hw: pointer to hardware structure
2601  */
2602 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2603 {
2604         u32 status;
2605         u16 reg;
2606
2607         status = hw->phy.ops.read_reg(hw,
2608                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2609                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2610                                       &reg);
2611
2612         if (status != IXGBE_SUCCESS)
2613                 return status;
2614
2615         /* If PHY FW reset completed bit is set then this is the first
2616          * SW instance after a power on so the PHY FW must be un-stalled.
2617          */
2618         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2619                 status = hw->phy.ops.read_reg(hw,
2620                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2621                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2622                                         &reg);
2623
2624                 if (status != IXGBE_SUCCESS)
2625                         return status;
2626
2627                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2628
2629                 status = hw->phy.ops.write_reg(hw,
2630                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2631                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2632                                         reg);
2633
2634                 if (status != IXGBE_SUCCESS)
2635                         return status;
2636         }
2637
2638         return status;
2639 }
2640
2641 /**
2642  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2643  *  @hw: pointer to hardware structure
2644  *
2645  *  Configures the integrated KR PHY for X550EM_x.
2646  **/
2647 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2648 {
2649         if (hw->mac.type != ixgbe_mac_X550EM_x)
2650                 return IXGBE_SUCCESS;
2651
2652         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2653 }
2654
2655 /**
2656  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2657  *  @hw: pointer to hardware structure
2658  *
2659  *  Configure the external PHY and the integrated KR PHY for SFP support.
2660  **/
2661 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2662                                     ixgbe_link_speed speed,
2663                                     bool autoneg_wait_to_complete)
2664 {
2665         s32 ret_val;
2666         u16 reg_slice, reg_val;
2667         bool setup_linear = false;
2668         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2669
2670         /* Check if SFP module is supported and linear */
2671         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2672
2673         /* If no SFP module present, then return success. Return success since
2674          * there is no reason to configure CS4227 and SFP not present error is
2675          * not excepted in the setup MAC link flow.
2676          */
2677         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2678                 return IXGBE_SUCCESS;
2679
2680         if (ret_val != IXGBE_SUCCESS)
2681                 return ret_val;
2682
2683         /* Configure internal PHY for KR/KX. */
2684         ixgbe_setup_kr_speed_x550em(hw, speed);
2685
2686         /* Configure CS4227 LINE side to proper mode. */
2687         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2688                     (hw->bus.lan_id << 12);
2689         if (setup_linear)
2690                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2691         else
2692                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2693         ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2694                                           reg_val);
2695         return ret_val;
2696 }
2697
2698 /**
2699  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2700  *  @hw: pointer to hardware structure
2701  *
2702  *  Configure the the integrated PHY for SFP support.
2703  **/
2704 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2705                                    ixgbe_link_speed speed,
2706                                    bool autoneg_wait_to_complete)
2707 {
2708         s32 ret_val;
2709         u16 reg_phy_ext;
2710         bool setup_linear = false;
2711         u32 reg_slice, reg_phy_int, slice_offset;
2712
2713         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2714
2715         /* Check if SFP module is supported and linear */
2716         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2717
2718         /* If no SFP module present, then return success. Return success since
2719          * SFP not present error is not excepted in the setup MAC link flow.
2720          */
2721         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2722                 return IXGBE_SUCCESS;
2723
2724         if (ret_val != IXGBE_SUCCESS)
2725                 return ret_val;
2726
2727         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2728                 /* Configure internal PHY for native SFI */
2729                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2730                                IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2731                                IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2732
2733                 if (ret_val != IXGBE_SUCCESS)
2734                         return ret_val;
2735
2736                 if (setup_linear) {
2737                         reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2738                         reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2739                 } else {
2740                         reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2741                         reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2742                 }
2743
2744                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2745                                 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2746                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2747
2748                 if (ret_val != IXGBE_SUCCESS)
2749                         return ret_val;
2750
2751                 /* Setup XFI/SFI internal link. */
2752                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2753         } else {
2754                 /* Configure internal PHY for KR/KX. */
2755                 ixgbe_setup_kr_speed_x550em(hw, speed);
2756
2757                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2758                         /* Find Address */
2759                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2760                         return IXGBE_ERR_PHY_ADDR_INVALID;
2761                 }
2762
2763                 /* Get external PHY device id */
2764                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2765                                        IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2766
2767                 if (ret_val != IXGBE_SUCCESS)
2768                         return ret_val;
2769
2770                 /* When configuring quad port CS4223, the MAC instance is part
2771                  * of the slice offset.
2772                  */
2773                 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2774                         slice_offset = (hw->bus.lan_id +
2775                                         (hw->bus.instance_id << 1)) << 12;
2776                 else
2777                         slice_offset = hw->bus.lan_id << 12;
2778
2779                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2780                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2781                 if (setup_linear)
2782                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2783                 else
2784                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2785                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2786                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2787         }
2788         return ret_val;
2789 }
2790
2791 /**
2792  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2793  *  @hw: pointer to hardware structure
2794  *
2795  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2796  **/
2797 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2798 {
2799         s32 status;
2800         u32 reg_val;
2801
2802         /* Disable training protocol FSM. */
2803         status = ixgbe_read_iosf_sb_reg_x550(hw,
2804                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2805                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2806         if (status != IXGBE_SUCCESS)
2807                 return status;
2808         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2809         status = ixgbe_write_iosf_sb_reg_x550(hw,
2810                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2811                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2812         if (status != IXGBE_SUCCESS)
2813                 return status;
2814
2815         /* Disable Flex from training TXFFE. */
2816         status = ixgbe_read_iosf_sb_reg_x550(hw,
2817                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2818                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2819         if (status != IXGBE_SUCCESS)
2820                 return status;
2821         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2822         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2823         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2824         status = ixgbe_write_iosf_sb_reg_x550(hw,
2825                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2826                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2827         if (status != IXGBE_SUCCESS)
2828                 return status;
2829         status = ixgbe_read_iosf_sb_reg_x550(hw,
2830                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2831                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2832         if (status != IXGBE_SUCCESS)
2833                 return status;
2834         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2835         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2836         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2837         status = ixgbe_write_iosf_sb_reg_x550(hw,
2838                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2839                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2840         if (status != IXGBE_SUCCESS)
2841                 return status;
2842
2843         /* Enable override for coefficients. */
2844         status = ixgbe_read_iosf_sb_reg_x550(hw,
2845                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2846                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2847         if (status != IXGBE_SUCCESS)
2848                 return status;
2849         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2850         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2851         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2852         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2853         status = ixgbe_write_iosf_sb_reg_x550(hw,
2854                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2855                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2856         return status;
2857 }
2858
2859 /**
2860  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2861  *  @hw: pointer to hardware structure
2862  *  @speed: the link speed to force
2863  *
2864  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2865  *  internal and external PHY at a specific speed, without autonegotiation.
2866  **/
2867 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2868 {
2869         s32 status;
2870         u32 reg_val;
2871
2872         /* Disable AN and force speed to 10G Serial. */
2873         status = ixgbe_read_iosf_sb_reg_x550(hw,
2874                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2875                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2876         if (status != IXGBE_SUCCESS)
2877                 return status;
2878
2879         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2880         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2881
2882         /* Select forced link speed for internal PHY. */
2883         switch (*speed) {
2884         case IXGBE_LINK_SPEED_10GB_FULL:
2885                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2886                 break;
2887         case IXGBE_LINK_SPEED_1GB_FULL:
2888                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2889                 break;
2890         default:
2891                 /* Other link speeds are not supported by internal KR PHY. */
2892                 return IXGBE_ERR_LINK_SETUP;
2893         }
2894
2895         status = ixgbe_write_iosf_sb_reg_x550(hw,
2896                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2897                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2898         if (status != IXGBE_SUCCESS)
2899                 return status;
2900
2901         /* Additional configuration needed for x550em_x */
2902         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2903                 status = ixgbe_setup_ixfi_x550em_x(hw);
2904                 if (status != IXGBE_SUCCESS)
2905                         return status;
2906         }
2907
2908         /* Toggle port SW reset by AN reset. */
2909         status = ixgbe_read_iosf_sb_reg_x550(hw,
2910                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2911                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2912         if (status != IXGBE_SUCCESS)
2913                 return status;
2914         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2915         status = ixgbe_write_iosf_sb_reg_x550(hw,
2916                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2917                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2918
2919         return status;
2920 }
2921
2922 /**
2923  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2924  * @hw: address of hardware structure
2925  * @link_up: address of boolean to indicate link status
2926  *
2927  * Returns error code if unable to get link status.
2928  */
2929 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2930 {
2931         u32 ret;
2932         u16 autoneg_status;
2933
2934         *link_up = false;
2935
2936         /* read this twice back to back to indicate current status */
2937         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2938                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2939                                    &autoneg_status);
2940         if (ret != IXGBE_SUCCESS)
2941                 return ret;
2942
2943         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2944                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2945                                    &autoneg_status);
2946         if (ret != IXGBE_SUCCESS)
2947                 return ret;
2948
2949         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2950
2951         return IXGBE_SUCCESS;
2952 }
2953
2954 /**
2955  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2956  * @hw: point to hardware structure
2957  *
2958  * Configures the link between the integrated KR PHY and the external X557 PHY
2959  * The driver will call this function when it gets a link status change
2960  * interrupt from the X557 PHY. This function configures the link speed
2961  * between the PHYs to match the link speed of the BASE-T link.
2962  *
2963  * A return of a non-zero value indicates an error, and the base driver should
2964  * not report link up.
2965  */
2966 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2967 {
2968         ixgbe_link_speed force_speed;
2969         bool link_up;
2970         u32 status;
2971         u16 speed;
2972
2973         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2974                 return IXGBE_ERR_CONFIG;
2975
2976         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2977                 /* If link is down, there is no setup necessary so return  */
2978                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2979                 if (status != IXGBE_SUCCESS)
2980                         return status;
2981
2982                 if (!link_up)
2983                         return IXGBE_SUCCESS;
2984
2985                 status = hw->phy.ops.read_reg(hw,
2986                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2987                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2988                                               &speed);
2989                 if (status != IXGBE_SUCCESS)
2990                         return status;
2991
2992                 /* If link is still down - no setup is required so return */
2993                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2994                 if (status != IXGBE_SUCCESS)
2995                         return status;
2996                 if (!link_up)
2997                         return IXGBE_SUCCESS;
2998
2999                 /* clear everything but the speed and duplex bits */
3000                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3001
3002                 switch (speed) {
3003                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3004                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3005                         break;
3006                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3007                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3008                         break;
3009                 default:
3010                         /* Internal PHY does not support anything else */
3011                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
3012                 }
3013
3014                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3015         } else {
3016                 speed = IXGBE_LINK_SPEED_10GB_FULL |
3017                         IXGBE_LINK_SPEED_1GB_FULL;
3018                 return ixgbe_setup_kr_speed_x550em(hw, speed);
3019         }
3020 }
3021
3022 /**
3023  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3024  *  @hw: pointer to hardware structure
3025  *
3026  *  Configures the integrated KR PHY to use internal loopback mode.
3027  **/
3028 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3029 {
3030         s32 status;
3031         u32 reg_val;
3032
3033         /* Disable AN and force speed to 10G Serial. */
3034         status = hw->mac.ops.read_iosf_sb_reg(hw,
3035                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3036                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3037         if (status != IXGBE_SUCCESS)
3038                 return status;
3039         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3040         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3041         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3042         status = hw->mac.ops.write_iosf_sb_reg(hw,
3043                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3044                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3045         if (status != IXGBE_SUCCESS)
3046                 return status;
3047
3048         /* Set near-end loopback clocks. */
3049         status = hw->mac.ops.read_iosf_sb_reg(hw,
3050                       IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3051                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3052         if (status != IXGBE_SUCCESS)
3053                 return status;
3054         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3055         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3056         status = hw->mac.ops.write_iosf_sb_reg(hw,
3057                        IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3058                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3059         if (status != IXGBE_SUCCESS)
3060                 return status;
3061
3062         /* Set loopback enable. */
3063         status = hw->mac.ops.read_iosf_sb_reg(hw,
3064                       IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3065                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3066         if (status != IXGBE_SUCCESS)
3067                 return status;
3068         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3069         status = hw->mac.ops.write_iosf_sb_reg(hw,
3070                        IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3071                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3072         if (status != IXGBE_SUCCESS)
3073                 return status;
3074
3075         /* Training bypass. */
3076         status = hw->mac.ops.read_iosf_sb_reg(hw,
3077                       IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3078                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3079         if (status != IXGBE_SUCCESS)
3080                 return status;
3081         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3082         status = hw->mac.ops.write_iosf_sb_reg(hw,
3083                        IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3084                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3085
3086         return status;
3087 }
3088
3089 /**
3090  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3091  *  assuming that the semaphore is already obtained.
3092  *  @hw: pointer to hardware structure
3093  *  @offset: offset of  word in the EEPROM to read
3094  *  @data: word read from the EEPROM
3095  *
3096  *  Reads a 16 bit word from the EEPROM using the hostif.
3097  **/
3098 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3099                                    u16 *data)
3100 {
3101         s32 status;
3102         struct ixgbe_hic_read_shadow_ram buffer;
3103
3104         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
3105         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3106         buffer.hdr.req.buf_lenh = 0;
3107         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3108         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3109
3110         /* convert offset from words to bytes */
3111         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3112         /* one word */
3113         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3114
3115         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3116                                               sizeof(buffer),
3117                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3118
3119         if (status)
3120                 return status;
3121
3122         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3123                                           FW_NVM_DATA_OFFSET);
3124
3125         return 0;
3126 }
3127
3128 /**
3129  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3130  *  @hw: pointer to hardware structure
3131  *  @offset: offset of  word in the EEPROM to read
3132  *  @data: word read from the EEPROM
3133  *
3134  *  Reads a 16 bit word from the EEPROM using the hostif.
3135  **/
3136 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3137                               u16 *data)
3138 {
3139         s32 status = IXGBE_SUCCESS;
3140
3141         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3142
3143         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3144             IXGBE_SUCCESS) {
3145                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
3146                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3147         } else {
3148                 status = IXGBE_ERR_SWFW_SYNC;
3149         }
3150
3151         return status;
3152 }
3153
3154 /**
3155  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3156  *  @hw: pointer to hardware structure
3157  *  @offset: offset of  word in the EEPROM to read
3158  *  @words: number of words
3159  *  @data: word(s) read from the EEPROM
3160  *
3161  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
3162  **/
3163 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3164                                      u16 offset, u16 words, u16 *data)
3165 {
3166         struct ixgbe_hic_read_shadow_ram buffer;
3167         u32 current_word = 0;
3168         u16 words_to_read;
3169         s32 status;
3170         u32 i;
3171
3172         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3173
3174         /* Take semaphore for the entire operation. */
3175         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3176         if (status) {
3177                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3178                 return status;
3179         }
3180         while (words) {
3181                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3182                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3183                 else
3184                         words_to_read = words;
3185
3186                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3187                 buffer.hdr.req.buf_lenh = 0;
3188                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3189                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3190
3191                 /* convert offset from words to bytes */
3192                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3193                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3194
3195                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3196                                                       sizeof(buffer),
3197                                                       IXGBE_HI_COMMAND_TIMEOUT,
3198                                                       false);
3199
3200                 if (status) {
3201                         DEBUGOUT("Host interface command failed\n");
3202                         goto out;
3203                 }
3204
3205                 for (i = 0; i < words_to_read; i++) {
3206                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3207                                   2 * i;
3208                         u32 value = IXGBE_READ_REG(hw, reg);
3209
3210                         data[current_word] = (u16)(value & 0xffff);
3211                         current_word++;
3212                         i++;
3213                         if (i < words_to_read) {
3214                                 value >>= 16;
3215                                 data[current_word] = (u16)(value & 0xffff);
3216                                 current_word++;
3217                         }
3218                 }
3219                 words -= words_to_read;
3220         }
3221
3222 out:
3223         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3224         return status;
3225 }
3226
3227 /**
3228  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3229  *  @hw: pointer to hardware structure
3230  *  @offset: offset of  word in the EEPROM to write
3231  *  @data: word write to the EEPROM
3232  *
3233  *  Write a 16 bit word to the EEPROM using the hostif.
3234  **/
3235 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3236                                     u16 data)
3237 {
3238         s32 status;
3239         struct ixgbe_hic_write_shadow_ram buffer;
3240
3241         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3242
3243         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3244         buffer.hdr.req.buf_lenh = 0;
3245         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3246         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3247
3248          /* one word */
3249         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3250         buffer.data = data;
3251         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3252
3253         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3254                                               sizeof(buffer),
3255                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3256
3257         return status;
3258 }
3259
3260 /**
3261  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3262  *  @hw: pointer to hardware structure
3263  *  @offset: offset of  word in the EEPROM to write
3264  *  @data: word write to the EEPROM
3265  *
3266  *  Write a 16 bit word to the EEPROM using the hostif.
3267  **/
3268 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3269                                u16 data)
3270 {
3271         s32 status = IXGBE_SUCCESS;
3272
3273         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3274
3275         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3276             IXGBE_SUCCESS) {
3277                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3278                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3279         } else {
3280                 DEBUGOUT("write ee hostif failed to get semaphore");
3281                 status = IXGBE_ERR_SWFW_SYNC;
3282         }
3283
3284         return status;
3285 }
3286
3287 /**
3288  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3289  *  @hw: pointer to hardware structure
3290  *  @offset: offset of  word in the EEPROM to write
3291  *  @words: number of words
3292  *  @data: word(s) write to the EEPROM
3293  *
3294  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3295  **/
3296 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3297                                       u16 offset, u16 words, u16 *data)
3298 {
3299         s32 status = IXGBE_SUCCESS;
3300         u32 i = 0;
3301
3302         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3303
3304         /* Take semaphore for the entire operation. */
3305         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3306         if (status != IXGBE_SUCCESS) {
3307                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3308                 goto out;
3309         }
3310
3311         for (i = 0; i < words; i++) {
3312                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3313                                                          data[i]);
3314
3315                 if (status != IXGBE_SUCCESS) {
3316                         DEBUGOUT("Eeprom buffered write failed\n");
3317                         break;
3318                 }
3319         }
3320
3321         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3322 out:
3323
3324         return status;
3325 }
3326
3327 /**
3328  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3329  * @hw: pointer to hardware structure
3330  * @ptr: pointer offset in eeprom
3331  * @size: size of section pointed by ptr, if 0 first word will be used as size
3332  * @csum: address of checksum to update
3333  *
3334  * Returns error status for any failure
3335  */
3336 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3337                                    u16 size, u16 *csum, u16 *buffer,
3338                                    u32 buffer_size)
3339 {
3340         u16 buf[256];
3341         s32 status;
3342         u16 length, bufsz, i, start;
3343         u16 *local_buffer;
3344
3345         bufsz = sizeof(buf) / sizeof(buf[0]);
3346
3347         /* Read a chunk at the pointer location */
3348         if (!buffer) {
3349                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3350                 if (status) {
3351                         DEBUGOUT("Failed to read EEPROM image\n");
3352                         return status;
3353                 }
3354                 local_buffer = buf;
3355         } else {
3356                 if (buffer_size < ptr)
3357                         return  IXGBE_ERR_PARAM;
3358                 local_buffer = &buffer[ptr];
3359         }
3360
3361         if (size) {
3362                 start = 0;
3363                 length = size;
3364         } else {
3365                 start = 1;
3366                 length = local_buffer[0];
3367
3368                 /* Skip pointer section if length is invalid. */
3369                 if (length == 0xFFFF || length == 0 ||
3370                     (ptr + length) >= hw->eeprom.word_size)
3371                         return IXGBE_SUCCESS;
3372         }
3373
3374         if (buffer && ((u32)start + (u32)length > buffer_size))
3375                 return IXGBE_ERR_PARAM;
3376
3377         for (i = start; length; i++, length--) {
3378                 if (i == bufsz && !buffer) {
3379                         ptr += bufsz;
3380                         i = 0;
3381                         if (length < bufsz)
3382                                 bufsz = length;
3383
3384                         /* Read a chunk at the pointer location */
3385                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3386                                                                   bufsz, buf);
3387                         if (status) {
3388                                 DEBUGOUT("Failed to read EEPROM image\n");
3389                                 return status;
3390                         }
3391                 }
3392                 *csum += local_buffer[i];
3393         }
3394         return IXGBE_SUCCESS;
3395 }
3396
3397 /**
3398  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3399  *  @hw: pointer to hardware structure
3400  *  @buffer: pointer to buffer containing calculated checksum
3401  *  @buffer_size: size of buffer
3402  *
3403  *  Returns a negative error code on error, or the 16-bit checksum
3404  **/
3405 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3406 {
3407         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3408         u16 *local_buffer;
3409         s32 status;
3410         u16 checksum = 0;
3411         u16 pointer, i, size;
3412
3413         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3414
3415         hw->eeprom.ops.init_params(hw);
3416
3417         if (!buffer) {
3418                 /* Read pointer area */
3419                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3420                                                      IXGBE_EEPROM_LAST_WORD + 1,
3421                                                      eeprom_ptrs);
3422                 if (status) {
3423                         DEBUGOUT("Failed to read EEPROM image\n");
3424                         return status;
3425                 }
3426                 local_buffer = eeprom_ptrs;
3427         } else {
3428                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3429                         return IXGBE_ERR_PARAM;
3430                 local_buffer = buffer;
3431         }
3432
3433         /*
3434          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3435          * checksum word itself
3436          */
3437         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3438                 if (i != IXGBE_EEPROM_CHECKSUM)
3439                         checksum += local_buffer[i];
3440
3441         /*
3442          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3443          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3444          */
3445         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3446                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3447                         continue;
3448
3449                 pointer = local_buffer[i];
3450
3451                 /* Skip pointer section if the pointer is invalid. */
3452                 if (pointer == 0xFFFF || pointer == 0 ||
3453                     pointer >= hw->eeprom.word_size)
3454                         continue;
3455
3456                 switch (i) {
3457                 case IXGBE_PCIE_GENERAL_PTR:
3458                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3459                         break;
3460                 case IXGBE_PCIE_CONFIG0_PTR:
3461                 case IXGBE_PCIE_CONFIG1_PTR:
3462                         size = IXGBE_PCIE_CONFIG_SIZE;
3463                         break;
3464                 default:
3465                         size = 0;
3466                         break;
3467                 }
3468
3469                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3470                                                 buffer, buffer_size);
3471                 if (status)
3472                         return status;
3473         }
3474
3475         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3476
3477         return (s32)checksum;
3478 }
3479
3480 /**
3481  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3482  *  @hw: pointer to hardware structure
3483  *
3484  *  Returns a negative error code on error, or the 16-bit checksum
3485  **/
3486 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3487 {
3488         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3489 }
3490
3491 /**
3492  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3493  *  @hw: pointer to hardware structure
3494  *  @checksum_val: calculated checksum
3495  *
3496  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3497  *  caller does not need checksum_val, the value can be NULL.
3498  **/
3499 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3500 {
3501         s32 status;
3502         u16 checksum;
3503         u16 read_checksum = 0;
3504
3505         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3506
3507         /* Read the first word from the EEPROM. If this times out or fails, do
3508          * not continue or we could be in for a very long wait while every
3509          * EEPROM read fails
3510          */
3511         status = hw->eeprom.ops.read(hw, 0, &checksum);
3512         if (status) {
3513                 DEBUGOUT("EEPROM read failed\n");
3514                 return status;
3515         }
3516
3517         status = hw->eeprom.ops.calc_checksum(hw);
3518         if (status < 0)
3519                 return status;
3520
3521         checksum = (u16)(status & 0xffff);
3522
3523         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3524                                            &read_checksum);
3525         if (status)
3526                 return status;
3527
3528         /* Verify read checksum from EEPROM is the same as
3529          * calculated checksum
3530          */
3531         if (read_checksum != checksum) {
3532                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3533                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3534                              "Invalid EEPROM checksum");
3535         }
3536
3537         /* If the user cares, return the calculated checksum */
3538         if (checksum_val)
3539                 *checksum_val = checksum;
3540
3541         return status;
3542 }
3543
3544 /**
3545  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3546  * @hw: pointer to hardware structure
3547  *
3548  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3549  * checksum and updates the EEPROM and instructs the hardware to update
3550  * the flash.
3551  **/
3552 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3553 {
3554         s32 status;
3555         u16 checksum = 0;
3556
3557         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3558
3559         /* Read the first word from the EEPROM. If this times out or fails, do
3560          * not continue or we could be in for a very long wait while every
3561          * EEPROM read fails
3562          */
3563         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3564         if (status) {
3565                 DEBUGOUT("EEPROM read failed\n");
3566                 return status;
3567         }
3568
3569         status = ixgbe_calc_eeprom_checksum_X550(hw);
3570         if (status < 0)
3571                 return status;
3572
3573         checksum = (u16)(status & 0xffff);
3574
3575         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3576                                             checksum);
3577         if (status)
3578                 return status;
3579
3580         status = ixgbe_update_flash_X550(hw);
3581
3582         return status;
3583 }
3584
3585 /**
3586  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3587  *  @hw: pointer to hardware structure
3588  *
3589  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3590  **/
3591 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3592 {
3593         s32 status = IXGBE_SUCCESS;
3594         union ixgbe_hic_hdr2 buffer;
3595
3596         DEBUGFUNC("ixgbe_update_flash_X550");
3597
3598         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3599         buffer.req.buf_lenh = 0;
3600         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3601         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3602
3603         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3604                                               sizeof(buffer),
3605                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3606
3607         return status;
3608 }
3609
3610 /**
3611  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3612  *  @hw: pointer to hardware structure
3613  *
3614  *  Determines physical layer capabilities of the current configuration.
3615  **/
3616 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3617 {
3618         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3619         u16 ext_ability = 0;
3620
3621         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3622
3623         hw->phy.ops.identify(hw);
3624
3625         switch (hw->phy.type) {
3626         case ixgbe_phy_x550em_kr:
3627                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3628                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3629                 break;
3630         case ixgbe_phy_x550em_kx4:
3631                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3632                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3633                 break;
3634         case ixgbe_phy_x550em_ext_t:
3635                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3636                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3637                                      &ext_ability);
3638                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3639                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3640                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3641                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3642                 break;
3643         default:
3644                 break;
3645         }
3646
3647         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3648                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3649
3650         return physical_layer;
3651 }
3652
3653 /**
3654  * ixgbe_get_bus_info_x550em - Set PCI bus info
3655  * @hw: pointer to hardware structure
3656  *
3657  * Sets bus link width and speed to unknown because X550em is
3658  * not a PCI device.
3659  **/
3660 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3661 {
3662
3663         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3664
3665         hw->bus.width = ixgbe_bus_width_unknown;
3666         hw->bus.speed = ixgbe_bus_speed_unknown;
3667
3668         hw->mac.ops.set_lan_id(hw);
3669
3670         return IXGBE_SUCCESS;
3671 }
3672
3673 /**
3674  * ixgbe_disable_rx_x550 - Disable RX unit
3675  *
3676  * Enables the Rx DMA unit for x550
3677  **/
3678 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3679 {
3680         u32 rxctrl, pfdtxgswc;
3681         s32 status;
3682         struct ixgbe_hic_disable_rxen fw_cmd;
3683
3684         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3685
3686         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3687         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3688                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3689                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3690                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3691                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3692                         hw->mac.set_lben = true;
3693                 } else {
3694                         hw->mac.set_lben = false;
3695                 }
3696
3697                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3698                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3699                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3700                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3701
3702                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3703                                         sizeof(struct ixgbe_hic_disable_rxen),
3704                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3705
3706                 /* If we fail - disable RX using register write */
3707                 if (status) {
3708                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3709                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3710                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3711                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3712                         }
3713                 }
3714         }
3715 }
3716
3717 /**
3718  * ixgbe_enter_lplu_x550em - Transition to low power states
3719  *  @hw: pointer to hardware structure
3720  *
3721  * Configures Low Power Link Up on transition to low power states
3722  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3723  * X557 PHY immediately prior to entering LPLU.
3724  **/
3725 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3726 {
3727         u16 an_10g_cntl_reg, autoneg_reg, speed;
3728         s32 status;
3729         ixgbe_link_speed lcd_speed;
3730         u32 save_autoneg;
3731         bool link_up;
3732
3733         /* SW LPLU not required on later HW revisions. */
3734         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3735             (IXGBE_FUSES0_REV_MASK &
3736              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3737                 return IXGBE_SUCCESS;
3738
3739         /* If blocked by MNG FW, then don't restart AN */
3740         if (ixgbe_check_reset_blocked(hw))
3741                 return IXGBE_SUCCESS;
3742
3743         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3744         if (status != IXGBE_SUCCESS)
3745                 return status;
3746
3747         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3748
3749         if (status != IXGBE_SUCCESS)
3750                 return status;
3751
3752         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3753          * disabled, then force link down by entering low power mode.
3754          */
3755         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3756             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3757                 return ixgbe_set_copper_phy_power(hw, FALSE);
3758
3759         /* Determine LCD */
3760         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3761
3762         if (status != IXGBE_SUCCESS)
3763                 return status;
3764
3765         /* If no valid LCD link speed, then force link down and exit. */
3766         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3767                 return ixgbe_set_copper_phy_power(hw, FALSE);
3768
3769         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3770                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3771                                       &speed);
3772
3773         if (status != IXGBE_SUCCESS)
3774                 return status;
3775
3776         /* If no link now, speed is invalid so take link down */
3777         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3778         if (status != IXGBE_SUCCESS)
3779                 return ixgbe_set_copper_phy_power(hw, false);
3780
3781         /* clear everything but the speed bits */
3782         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3783
3784         /* If current speed is already LCD, then exit. */
3785         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3786              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3787             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3788              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3789                 return status;
3790
3791         /* Clear AN completed indication */
3792         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3793                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3794                                       &autoneg_reg);
3795
3796         if (status != IXGBE_SUCCESS)
3797                 return status;
3798
3799         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3800                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3801                              &an_10g_cntl_reg);
3802
3803         if (status != IXGBE_SUCCESS)
3804                 return status;
3805
3806         status = hw->phy.ops.read_reg(hw,
3807                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3808                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3809                              &autoneg_reg);
3810
3811         if (status != IXGBE_SUCCESS)
3812                 return status;
3813
3814         save_autoneg = hw->phy.autoneg_advertised;
3815
3816         /* Setup link at least common link speed */
3817         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3818
3819         /* restore autoneg from before setting lplu speed */
3820         hw->phy.autoneg_advertised = save_autoneg;
3821
3822         return status;
3823 }
3824
3825 /**
3826  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3827  *  @hw: pointer to hardware structure
3828  *  @lcd_speed: pointer to lowest common link speed
3829  *
3830  * Determine lowest common link speed with link partner.
3831  **/
3832 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3833 {
3834         u16 an_lp_status;
3835         s32 status;
3836         u16 word = hw->eeprom.ctrl_word_3;
3837
3838         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3839
3840         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3841                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3842                                       &an_lp_status);
3843
3844         if (status != IXGBE_SUCCESS)
3845                 return status;
3846
3847         /* If link partner advertised 1G, return 1G */
3848         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3849                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3850                 return status;
3851         }
3852
3853         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3854         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3855             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3856                 return status;
3857
3858         /* Link partner not capable of lower speeds, return 10G */
3859         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3860         return status;
3861 }
3862
3863 /**
3864  *  ixgbe_setup_fc_X550em - Set up flow control
3865  *  @hw: pointer to hardware structure
3866  *
3867  *  Called at init time to set up flow control.
3868  **/
3869 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3870 {
3871         s32 ret_val = IXGBE_SUCCESS;
3872         u32 pause, asm_dir, reg_val;
3873
3874         DEBUGFUNC("ixgbe_setup_fc_X550em");
3875
3876         /* Validate the requested mode */
3877         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3878                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3879                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3880                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3881                 goto out;
3882         }
3883
3884         /* 10gig parts do not have a word in the EEPROM to determine the
3885          * default flow control setting, so we explicitly set it to full.
3886          */
3887         if (hw->fc.requested_mode == ixgbe_fc_default)
3888                 hw->fc.requested_mode = ixgbe_fc_full;
3889
3890         /* Determine PAUSE and ASM_DIR bits. */
3891         switch (hw->fc.requested_mode) {
3892         case ixgbe_fc_none:
3893                 pause = 0;
3894                 asm_dir = 0;
3895                 break;
3896         case ixgbe_fc_tx_pause:
3897                 pause = 0;
3898                 asm_dir = 1;
3899                 break;
3900         case ixgbe_fc_rx_pause:
3901                 /* Rx Flow control is enabled and Tx Flow control is
3902                  * disabled by software override. Since there really
3903                  * isn't a way to advertise that we are capable of RX
3904                  * Pause ONLY, we will advertise that we support both
3905                  * symmetric and asymmetric Rx PAUSE, as such we fall
3906                  * through to the fc_full statement.  Later, we will
3907                  * disable the adapter's ability to send PAUSE frames.
3908                  */
3909         case ixgbe_fc_full:
3910                 pause = 1;
3911                 asm_dir = 1;
3912                 break;
3913         default:
3914                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3915                         "Flow control param set incorrectly\n");
3916                 ret_val = IXGBE_ERR_CONFIG;
3917                 goto out;
3918         }
3919
3920         switch (hw->device_id) {
3921         case IXGBE_DEV_ID_X550EM_X_KR:
3922         case IXGBE_DEV_ID_X550EM_A_KR:
3923         case IXGBE_DEV_ID_X550EM_A_KR_L:
3924                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3925                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3926                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3927                 if (ret_val != IXGBE_SUCCESS)
3928                         goto out;
3929                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3930                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3931                 if (pause)
3932                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3933                 if (asm_dir)
3934                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3935                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3936                                        IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3937                                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3938
3939                 /* This device does not fully support AN. */
3940                 hw->fc.disable_fc_autoneg = true;
3941                 break;
3942         default:
3943                 break;
3944         }
3945
3946 out:
3947         return ret_val;
3948 }
3949
3950 /**
3951  *  ixgbe_fc_autoneg_x550a - Enable flow control IEEE clause 37
3952  *  @hw: pointer to hardware structure
3953  *
3954  *  Enable flow control according to IEEE clause 37.
3955  **/
3956 void ixgbe_fc_autoneg_x550a(struct ixgbe_hw *hw)
3957 {
3958         u32 link_s1, lp_an_page_low, an_cntl_1;
3959         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3960         ixgbe_link_speed speed;
3961         bool link_up;
3962
3963         /* AN should have completed when the cable was plugged in.
3964          * Look for reasons to bail out.  Bail out if:
3965          * - FC autoneg is disabled, or if
3966          * - link is not up.
3967          */
3968         if (hw->fc.disable_fc_autoneg) {
3969                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3970                               "Flow control autoneg is disabled");
3971                 goto out;
3972         }
3973
3974         hw->mac.ops.check_link(hw, &speed, &link_up, false);
3975         if (!link_up) {
3976                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3977                 goto out;
3978         }
3979
3980         /* Check at auto-negotiation has completed */
3981         status = hw->mac.ops.read_iosf_sb_reg(hw,
3982                                       IXGBE_KRM_LINK_S1(hw->bus.lan_id),
3983                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
3984
3985         if (status != IXGBE_SUCCESS ||
3986             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
3987                 DEBUGOUT("Auto-Negotiation did not complete\n");
3988                 goto out;
3989         }
3990
3991         /* Read the 10g AN autoc and LP ability registers and resolve
3992          * local flow control settings accordingly
3993          */
3994         status = hw->mac.ops.read_iosf_sb_reg(hw,
3995                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3996                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
3997
3998         if (status != IXGBE_SUCCESS) {
3999                 DEBUGOUT("Auto-Negotiation did not complete\n");
4000                 goto out;
4001         }
4002
4003         status = hw->mac.ops.read_iosf_sb_reg(hw,
4004                               IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4005                               IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4006
4007         if (status != IXGBE_SUCCESS) {
4008                 DEBUGOUT("Auto-Negotiation did not complete\n");
4009                 goto out;
4010         }
4011
4012         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4013                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4014                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4015                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4016                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4017
4018 out:
4019         if (status == IXGBE_SUCCESS) {
4020                 hw->fc.fc_was_autonegged = true;
4021         } else {
4022                 hw->fc.fc_was_autonegged = false;
4023                 hw->fc.current_mode = hw->fc.requested_mode;
4024         }
4025 }
4026
4027 /**
4028  *  ixgbe_setup_fc_x550em - Set up flow control
4029  *  @hw: pointer to hardware structure
4030  *
4031  *  Called at init time to set up flow control.
4032  **/
4033 s32 ixgbe_setup_fc_x550a(struct ixgbe_hw *hw)
4034 {
4035         s32 status = IXGBE_SUCCESS;
4036         u32 an_cntl, link_ctrl = 0;
4037
4038         DEBUGFUNC("ixgbe_setup_fc_x550em");
4039
4040         /* Validate the requested mode */
4041         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4042                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4043                       "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4044                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4045         }
4046
4047         if (hw->fc.requested_mode == ixgbe_fc_default)
4048                 hw->fc.requested_mode = ixgbe_fc_full;
4049
4050         /* Set up the 1G and 10G flow control advertisement registers so the
4051          * HW will be able to do FC autoneg once the cable is plugged in.  If
4052          * we link at 10G, the 1G advertisement is harmless and vice versa.
4053          */
4054         status = hw->mac.ops.read_iosf_sb_reg(hw,
4055                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4056                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4057
4058         if (status != IXGBE_SUCCESS) {
4059                 DEBUGOUT("Auto-Negotiation did not complete\n");
4060                 return status;
4061         }
4062
4063         /* The possible values of fc.requested_mode are:
4064          * 0: Flow control is completely disabled
4065          * 1: Rx flow control is enabled (we can receive pause frames,
4066          *    but not send pause frames).
4067          * 2: Tx flow control is enabled (we can send pause frames but
4068          *    we do not support receiving pause frames).
4069          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4070          * other: Invalid.
4071          */
4072         switch (hw->fc.requested_mode) {
4073         case ixgbe_fc_none:
4074                 /* Flow control completely disabled by software override. */
4075                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4076                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4077                 break;
4078         case ixgbe_fc_tx_pause:
4079                 /* Tx Flow control is enabled, and Rx Flow control is
4080                  * disabled by software override.
4081                  */
4082                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4083                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4084                 break;
4085         case ixgbe_fc_rx_pause:
4086                 /* Rx Flow control is enabled and Tx Flow control is
4087                  * disabled by software override. Since there really
4088                  * isn't a way to advertise that we are capable of RX
4089                  * Pause ONLY, we will advertise that we support both
4090                  * symmetric and asymmetric Rx PAUSE, as such we fall
4091                  * through to the fc_full statement.  Later, we will
4092                  * disable the adapter's ability to send PAUSE frames.
4093                  */
4094         case ixgbe_fc_full:
4095                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4096                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4097                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4098                 break;
4099         default:
4100                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4101                               "Flow control param set incorrectly\n");
4102                 return IXGBE_ERR_CONFIG;
4103         }
4104
4105         status = hw->mac.ops.write_iosf_sb_reg(hw,
4106                                        IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4107                                        IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4108
4109         /* Restart auto-negotiation. */
4110         status = hw->mac.ops.read_iosf_sb_reg(hw,
4111                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4112                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
4113
4114         if (status != IXGBE_SUCCESS) {
4115                 DEBUGOUT("Auto-Negotiation did not complete\n");
4116                 return status;
4117         }
4118
4119         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
4120         status = hw->mac.ops.write_iosf_sb_reg(hw,
4121                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4122                                        IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
4123
4124         return status;
4125 }
4126
4127 /**
4128  * ixgbe_set_mux - Set mux for port 1 access with CS4227
4129  * @hw: pointer to hardware structure
4130  * @state: set mux if 1, clear if 0
4131  */
4132 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4133 {
4134         u32 esdp;
4135
4136         if (!hw->bus.lan_id)
4137                 return;
4138         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4139         if (state)
4140                 esdp |= IXGBE_ESDP_SDP1;
4141         else
4142                 esdp &= ~IXGBE_ESDP_SDP1;
4143         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4144         IXGBE_WRITE_FLUSH(hw);
4145 }
4146
4147 /**
4148  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4149  *  @hw: pointer to hardware structure
4150  *  @mask: Mask to specify which semaphore to acquire
4151  *
4152  *  Acquires the SWFW semaphore and sets the I2C MUX
4153  **/
4154 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4155 {
4156         s32 status;
4157
4158         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4159
4160         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4161         if (status)
4162                 return status;
4163
4164         if (mask & IXGBE_GSSR_I2C_MASK)
4165                 ixgbe_set_mux(hw, 1);
4166
4167         return IXGBE_SUCCESS;
4168 }
4169
4170 /**
4171  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4172  *  @hw: pointer to hardware structure
4173  *  @mask: Mask to specify which semaphore to release
4174  *
4175  *  Releases the SWFW semaphore and sets the I2C MUX
4176  **/
4177 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4178 {
4179         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4180
4181         if (mask & IXGBE_GSSR_I2C_MASK)
4182                 ixgbe_set_mux(hw, 0);
4183
4184         ixgbe_release_swfw_sync_X540(hw, mask);
4185 }
4186
4187 /**
4188  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4189  *  @hw: pointer to hardware structure
4190  *  @mask: Mask to specify which semaphore to acquire
4191  *
4192  *  Acquires the SWFW semaphore and get the shared phy token as needed
4193  */
4194 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4195 {
4196         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4197         int retries = FW_PHY_TOKEN_RETRIES;
4198         s32 status = IXGBE_SUCCESS;
4199
4200         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4201
4202         while (--retries) {
4203                 status = IXGBE_SUCCESS;
4204                 if (hmask)
4205                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4206                 if (status)
4207                         return status;
4208                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4209                         return IXGBE_SUCCESS;
4210
4211                 status = ixgbe_get_phy_token(hw);
4212                 if (status == IXGBE_SUCCESS)
4213                         return IXGBE_SUCCESS;
4214
4215                 if (hmask)
4216                         ixgbe_release_swfw_sync_X540(hw, hmask);
4217                 if (status != IXGBE_ERR_TOKEN_RETRY)
4218                         return status;
4219                 msec_delay(FW_PHY_TOKEN_DELAY);
4220         }
4221
4222         return status;
4223 }
4224
4225 /**
4226  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4227  *  @hw: pointer to hardware structure
4228  *  @mask: Mask to specify which semaphore to release
4229  *
4230  *  Releases the SWFW semaphore and puts the shared phy token as needed
4231  */
4232 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4233 {
4234         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4235
4236         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4237
4238         if (mask & IXGBE_GSSR_TOKEN_SM)
4239                 ixgbe_put_phy_token(hw);
4240
4241         if (hmask)
4242                 ixgbe_release_swfw_sync_X540(hw, hmask);
4243 }
4244
4245 /**
4246  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4247  *  @hw: pointer to hardware structure
4248  *  @reg_addr: 32 bit address of PHY register to read
4249  *  @phy_data: Pointer to read data from PHY register
4250  *
4251  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4252  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4253  *  instances.
4254  **/
4255 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4256                              u32 device_type, u16 *phy_data)
4257 {
4258         s32 status;
4259         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4260
4261         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4262
4263         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4264                 return IXGBE_ERR_SWFW_SYNC;
4265
4266         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4267
4268         hw->mac.ops.release_swfw_sync(hw, mask);
4269
4270         return status;
4271 }
4272
4273 /**
4274  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4275  *  @hw: pointer to hardware structure
4276  *  @reg_addr: 32 bit PHY register to write
4277  *  @device_type: 5 bit device type
4278  *  @phy_data: Data to write to the PHY register
4279  *
4280  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4281  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4282  **/
4283 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4284                               u32 device_type, u16 phy_data)
4285 {
4286         s32 status;
4287         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4288
4289         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4290
4291         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4292                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
4293                                                  phy_data);
4294                 hw->mac.ops.release_swfw_sync(hw, mask);
4295         } else {
4296                 status = IXGBE_ERR_SWFW_SYNC;
4297         }
4298
4299         return status;
4300 }
4301
4302 /**
4303  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4304  * @hw: pointer to hardware structure
4305  *
4306  * Handle external Base T PHY interrupt. If high temperature
4307  * failure alarm then return error, else if link status change
4308  * then setup internal/external PHY link
4309  *
4310  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4311  * failure alarm, else return PHY access status.
4312  */
4313 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4314 {
4315         bool lsc;
4316         u32 status;
4317
4318         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4319
4320         if (status != IXGBE_SUCCESS)
4321                 return status;
4322
4323         if (lsc)
4324                 return ixgbe_setup_internal_phy(hw);
4325
4326         return IXGBE_SUCCESS;
4327 }
4328
4329 /**
4330  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4331  * @hw: pointer to hardware structure
4332  * @speed: new link speed
4333  * @autoneg_wait_to_complete: true when waiting for completion is needed
4334  *
4335  * Setup internal/external PHY link speed based on link speed, then set
4336  * external PHY auto advertised link speed.
4337  *
4338  * Returns error status for any failure
4339  **/
4340 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4341                                   ixgbe_link_speed speed,
4342                                   bool autoneg_wait_to_complete)
4343 {
4344         s32 status;
4345         ixgbe_link_speed force_speed;
4346
4347         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4348
4349         /* Setup internal/external PHY link speed to iXFI (10G), unless
4350          * only 1G is auto advertised then setup KX link.
4351          */
4352         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4353                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4354         else
4355                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4356
4357         /* If internal link mode is XFI, then setup XFI internal link. */
4358         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4359                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4360
4361                 if (status != IXGBE_SUCCESS)
4362                         return status;
4363         }
4364
4365         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4366 }
4367
4368 /**
4369  * ixgbe_check_link_t_X550em - Determine link and speed status
4370  * @hw: pointer to hardware structure
4371  * @speed: pointer to link speed
4372  * @link_up: true when link is up
4373  * @link_up_wait_to_complete: bool used to wait for link up or not
4374  *
4375  * Check that both the MAC and X557 external PHY have link.
4376  **/
4377 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4378                               bool *link_up, bool link_up_wait_to_complete)
4379 {
4380         u32 status;
4381         u16 autoneg_status;
4382
4383         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4384                 return IXGBE_ERR_CONFIG;
4385
4386         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4387                                               link_up_wait_to_complete);
4388
4389         /* If check link fails or MAC link is not up, then return */
4390         if (status != IXGBE_SUCCESS || !(*link_up))
4391                 return status;
4392
4393         /* MAC link is up, so check external PHY link.
4394          * Read this twice back to back to indicate current status.
4395          */
4396         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4397                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4398                                       &autoneg_status);
4399
4400         if (status != IXGBE_SUCCESS)
4401                 return status;
4402
4403         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4404                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4405                                       &autoneg_status);
4406
4407         if (status != IXGBE_SUCCESS)
4408                 return status;
4409
4410         /* If external PHY link is not up, then indicate link not up */
4411         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4412                 *link_up = false;
4413
4414         return IXGBE_SUCCESS;
4415 }
4416
4417 /**
4418  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4419  *  @hw: pointer to hardware structure
4420  **/
4421 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4422 {
4423         s32 status;
4424
4425         status = ixgbe_reset_phy_generic(hw);
4426
4427         if (status != IXGBE_SUCCESS)
4428                 return status;
4429
4430         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4431         return ixgbe_enable_lasi_ext_t_x550em(hw);
4432 }
4433
4434 /**
4435  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4436  *  @hw: pointer to hardware structure
4437  *  @led_idx: led number to turn on
4438  **/
4439 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4440 {
4441         u16 phy_data;
4442
4443         DEBUGFUNC("ixgbe_led_on_t_X550em");
4444
4445         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4446                 return IXGBE_ERR_PARAM;
4447
4448         /* To turn on the LED, set mode to ON. */
4449         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4450                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4451         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4452         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4453                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4454
4455         return IXGBE_SUCCESS;
4456 }
4457
4458 /**
4459  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4460  *  @hw: pointer to hardware structure
4461  *  @led_idx: led number to turn off
4462  **/
4463 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4464 {
4465         u16 phy_data;
4466
4467         DEBUGFUNC("ixgbe_led_off_t_X550em");
4468
4469         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4470                 return IXGBE_ERR_PARAM;
4471
4472         /* To turn on the LED, set mode to ON. */
4473         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4474                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4475         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4476         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4477                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4478
4479         return IXGBE_SUCCESS;
4480 }
4481