drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41
  42 /**
  43  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  44  *  @hw: pointer to hardware structure
  45  *
  46  *  Initialize the function pointers and assign the MAC type for X550.
  47  *  Does not touch the hardware.
  48  **/
  49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  50 {
  51         struct ixgbe_mac_info *mac = &hw->mac;
  52         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  53         s32 ret_val;
  54
  55         DEBUGFUNC("ixgbe_init_ops_X550");
  56
  57         ret_val = ixgbe_init_ops_X540(hw);
  58         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  59         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  60         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  61         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  62         mac->ops.set_source_address_pruning =
  63                         ixgbe_set_source_address_pruning_X550;
  64         mac->ops.set_ethertype_anti_spoofing =
  65                         ixgbe_set_ethertype_anti_spoofing_X550;
  66
  67         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  68         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  69         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  70         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  71         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  72         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  73         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  74         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  75         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  76
  77         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  78         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  79         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  80         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  81         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  82         return ret_val;
  83 }
  84
  85 /**
  86  * ixgbe_read_cs4227 - Read CS4227 register
  87  * @hw: pointer to hardware structure
  88  * @reg: register number to write
  89  * @value: pointer to receive value read
  90  *
  91  * Returns status code
  92  **/
  93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  94 {
  95         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
  96 }
  97
  98 /**
  99  * ixgbe_write_cs4227 - Write CS4227 register
 100  * @hw: pointer to hardware structure
 101  * @reg: register number to write
 102  * @value: value to write to register
 103  *
 104  * Returns status code
 105  **/
 106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 107 {
 108         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 109 }
 110
 111 /**
 112  * ixgbe_get_cs4227_status - Return CS4227 status
 113  * @hw: pointer to hardware structure
 114  *
 115  * Returns error if CS4227 not successfully initialized
 116  **/
 117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
 118 {
 119         s32 status;
 120         u16 value = 0;
 121         u8 retry;
 122
 123         for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
 124                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
 125                                            &value);
 126                 if (status != IXGBE_SUCCESS)
 127                         return status;
 128                 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
 129                         break;
 130                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 131         }
 132         if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
 133                 return IXGBE_ERR_PHY;
 134
 135         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 136                                     IXGBE_CS4227_SCRATCH_VALUE);
 137         if (status != IXGBE_SUCCESS)
 138                 return status;
 139         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 140         if (status != IXGBE_SUCCESS)
 141                 return status;
 142         if (value != IXGBE_CS4227_SCRATCH_VALUE)
 143                 return IXGBE_ERR_PHY;
 144         return IXGBE_SUCCESS;
 145 }
 146
 147 /**
 148  * ixgbe_read_pe - Read register from port expander
 149  * @hw: pointer to hardware structure
 150  * @reg: register number to read
 151  * @value: pointer to receive read value
 152  *
 153  * Returns status code
 154  **/
 155 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 156 {
 157         s32 status;
 158
 159         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 160         if (status != IXGBE_SUCCESS)
 161                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 162                               "port expander access failed with %d\n", status);
 163         return status;
 164 }
 165
 166 /**
 167  * ixgbe_write_pe - Write register to port expander
 168  * @hw: pointer to hardware structure
 169  * @reg: register number to write
 170  * @value: value to write
 171  *
 172  * Returns status code
 173  **/
 174 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 175 {
 176         s32 status;
 177
 178         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 179         if (status != IXGBE_SUCCESS)
 180                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 181                               "port expander access failed with %d\n", status);
 182         return status;
 183 }
 184
 185 /**
 186  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 187  * @hw: pointer to hardware structure
 188  *
 189  * Returns error code
 190  **/
 191 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 192 {
 193         s32 status;
 194         u8 reg;
 195
 196         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199         reg |= IXGBE_PE_BIT1;
 200         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 201         if (status != IXGBE_SUCCESS)
 202                 return status;
 203
 204         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 205         if (status != IXGBE_SUCCESS)
 206                 return status;
 207         reg &= ~IXGBE_PE_BIT1;
 208         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 209         if (status != IXGBE_SUCCESS)
 210                 return status;
 211
 212         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 213         if (status != IXGBE_SUCCESS)
 214                 return status;
 215         reg &= ~IXGBE_PE_BIT1;
 216         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 217         if (status != IXGBE_SUCCESS)
 218                 return status;
 219
 220         usec_delay(IXGBE_CS4227_RESET_HOLD);
 221
 222         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 223         if (status != IXGBE_SUCCESS)
 224                 return status;
 225         reg |= IXGBE_PE_BIT1;
 226         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 227         if (status != IXGBE_SUCCESS)
 228                 return status;
 229
 230         msec_delay(IXGBE_CS4227_RESET_DELAY);
 231
 232         return IXGBE_SUCCESS;
 233 }
 234
 235 /**
 236  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 237  * @hw: pointer to hardware structure
 238  **/
 239 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 240 {
 241         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 242         s32 status;
 243         u8 retry;
 244
 245         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 246                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 247                 if (status != IXGBE_SUCCESS) {
 248                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 249                                       "semaphore failed with %d\n", status);
 250                         return;
 251                 }
 252                 status = ixgbe_get_cs4227_status(hw);
 253                 if (status == IXGBE_SUCCESS) {
 254                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 255                         msec_delay(hw->eeprom.semaphore_delay);
 256                         return;
 257                 }
 258                 ixgbe_reset_cs4227(hw);
 259                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 260                 msec_delay(hw->eeprom.semaphore_delay);
 261         }
 262         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 263                       "Unable to initialize CS4227, err=%d\n", status);
 264 }
 265
 266 /**
 267  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 268  * @hw: pointer to hardware structure
 269  **/
 270 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 271 {
 272         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 273
 274         if (hw->bus.lan_id) {
 275                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 276                 esdp |= IXGBE_ESDP_SDP1_DIR;
 277         }
 278         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 279         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 280         IXGBE_WRITE_FLUSH(hw);
 281 }
 282
 283 /**
 284  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 285  * @hw: pointer to hardware structure
 286  *
 287  * Returns error code
 288  */
 289 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 290 {
 291         switch (hw->device_id) {
 292         case IXGBE_DEV_ID_X550EM_X_SFP:
 293                 /* set up for CS4227 usage */
 294                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 295                 ixgbe_setup_mux_ctl(hw);
 296                 ixgbe_check_cs4227(hw);
 297
 298                 return ixgbe_identify_module_generic(hw);
 299                 break;
 300         case IXGBE_DEV_ID_X550EM_X_KX4:
 301                 hw->phy.type = ixgbe_phy_x550em_kx4;
 302                 break;
 303         case IXGBE_DEV_ID_X550EM_X_KR:
 304                 hw->phy.type = ixgbe_phy_x550em_kr;
 305                 break;
 306         case IXGBE_DEV_ID_X550EM_X_1G_T:
 307         case IXGBE_DEV_ID_X550EM_X_10G_T:
 308                 return ixgbe_identify_phy_generic(hw);
 309         default:
 310                 break;
 311         }
 312         return IXGBE_SUCCESS;
 313 }
 314
 315 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 316                                      u32 device_type, u16 *phy_data)
 317 {
 318         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 319         return IXGBE_NOT_IMPLEMENTED;
 320 }
 321
 322 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 323                                       u32 device_type, u16 phy_data)
 324 {
 325         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 326         return IXGBE_NOT_IMPLEMENTED;
 327 }
 328
 329 /**
 330 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 331 *  @hw: pointer to hardware structure
 332 *
 333 *  Initialize the function pointers and for MAC type X550EM.
 334 *  Does not touch the hardware.
 335 **/
 336 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 337 {
 338         struct ixgbe_mac_info *mac = &hw->mac;
 339         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 340         struct ixgbe_phy_info *phy = &hw->phy;
 341         s32 ret_val;
 342
 343         DEBUGFUNC("ixgbe_init_ops_X550EM");
 344
 345         /* Similar to X550 so start there. */
 346         ret_val = ixgbe_init_ops_X550(hw);
 347
 348         /* Since this function eventually calls
 349          * ixgbe_init_ops_540 by design, we are setting
 350          * the pointers to NULL explicitly here to overwrite
 351          * the values being set in the x540 function.
 352          */
 353         /* Thermal sensor not supported in x550EM */
 354         mac->ops.get_thermal_sensor_data = NULL;
 355         mac->ops.init_thermal_sensor_thresh = NULL;
 356         mac->thermal_sensor_enabled = false;
 357
 358         /* FCOE not supported in x550EM */
 359         mac->ops.get_san_mac_addr = NULL;
 360         mac->ops.set_san_mac_addr = NULL;
 361         mac->ops.get_wwn_prefix = NULL;
 362         mac->ops.get_fcoe_boot_status = NULL;
 363
 364         /* IPsec not supported in x550EM */
 365         mac->ops.disable_sec_rx_path = NULL;
 366         mac->ops.enable_sec_rx_path = NULL;
 367
 368         /* AUTOC register is not present in x550EM. */
 369         mac->ops.prot_autoc_read = NULL;
 370         mac->ops.prot_autoc_write = NULL;
 371
 372         /* X550EM bus type is internal*/
 373         hw->bus.type = ixgbe_bus_type_internal;
 374         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 375
 376         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 377         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 378         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 379         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 380         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 381         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 382         mac->ops.get_supported_physical_layer =
 383                                     ixgbe_get_supported_physical_layer_X550em;
 384
 385                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 386         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 387         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 388
 389         /* PHY */
 390         phy->ops.init = ixgbe_init_phy_ops_X550em;
 391         phy->ops.identify = ixgbe_identify_phy_x550em;
 392         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 393                 phy->ops.set_phy_power = NULL;
 394
 395
 396         /* EEPROM */
 397         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 398         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 399         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 400         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 401         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 402         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 403         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 404         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 405
 406         return ret_val;
 407 }
 408
 409 /**
 410  *  ixgbe_dmac_config_X550
 411  *  @hw: pointer to hardware structure
 412  *
 413  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 414  *  When disabling dmac, dmac enable dmac bit is cleared.
 415  **/
 416 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 417 {
 418         u32 reg, high_pri_tc;
 419
 420         DEBUGFUNC("ixgbe_dmac_config_X550");
 421
 422         /* Disable DMA coalescing before configuring */
 423         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 424         reg &= ~IXGBE_DMACR_DMAC_EN;
 425         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 426
 427         /* Disable DMA Coalescing if the watchdog timer is 0 */
 428         if (!hw->mac.dmac_config.watchdog_timer)
 429                 goto out;
 430
 431         ixgbe_dmac_config_tcs_X550(hw);
 432
 433         /* Configure DMA Coalescing Control Register */
 434         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 435
 436         /* Set the watchdog timer in units of 40.96 usec */
 437         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 438         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 439
 440         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 441         /* If fcoe is enabled, set high priority traffic class */
 442         if (hw->mac.dmac_config.fcoe_en) {
 443                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 444                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 445                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 446         }
 447         reg |= IXGBE_DMACR_EN_MNG_IND;
 448
 449         /* Enable DMA coalescing after configuration */
 450         reg |= IXGBE_DMACR_DMAC_EN;
 451         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 452
 453 out:
 454         return IXGBE_SUCCESS;
 455 }
 456
 457 /**
 458  *  ixgbe_dmac_config_tcs_X550
 459  *  @hw: pointer to hardware structure
 460  *
 461  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 462  *  be cleared before configuring.
 463  **/
 464 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 465 {
 466         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 467
 468         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 469
 470         /* Configure DMA coalescing enabled */
 471         switch (hw->mac.dmac_config.link_speed) {
 472         case IXGBE_LINK_SPEED_100_FULL:
 473                 pb_headroom = IXGBE_DMACRXT_100M;
 474                 break;
 475         case IXGBE_LINK_SPEED_1GB_FULL:
 476                 pb_headroom = IXGBE_DMACRXT_1G;
 477                 break;
 478         default:
 479                 pb_headroom = IXGBE_DMACRXT_10G;
 480                 break;
 481         }
 482
 483         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 484                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 485
 486         /* Set the per Rx packet buffer receive threshold */
 487         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 488                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 489                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 490
 491                 if (tc < hw->mac.dmac_config.num_tcs) {
 492                         /* Get Rx PB size */
 493                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 494                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 495                                 IXGBE_RXPBSIZE_SHIFT;
 496
 497                         /* Calculate receive buffer threshold in kilobytes */
 498                         if (rx_pb_size > pb_headroom)
 499                                 rx_pb_size = rx_pb_size - pb_headroom;
 500                         else
 501                                 rx_pb_size = 0;
 502
 503                         /* Minimum of MFS shall be set for DMCTH */
 504                         reg |= (rx_pb_size > maxframe_size_kb) ?
 505                                 rx_pb_size : maxframe_size_kb;
 506                 }
 507                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 508         }
 509         return IXGBE_SUCCESS;
 510 }
 511
 512 /**
 513  *  ixgbe_dmac_update_tcs_X550
 514  *  @hw: pointer to hardware structure
 515  *
 516  *  Disables dmac, updates per TC settings, and then enables dmac.
 517  **/
 518 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 519 {
 520         u32 reg;
 521
 522         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 523
 524         /* Disable DMA coalescing before configuring */
 525         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 526         reg &= ~IXGBE_DMACR_DMAC_EN;
 527         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 528
 529         ixgbe_dmac_config_tcs_X550(hw);
 530
 531         /* Enable DMA coalescing after configuration */
 532         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 533         reg |= IXGBE_DMACR_DMAC_EN;
 534         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 535
 536         return IXGBE_SUCCESS;
 537 }
 538
 539 /**
 540  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 541  *  @hw: pointer to hardware structure
 542  *
 543  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 544  *  ixgbe_hw struct in order to set up EEPROM access.
 545  **/
 546 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 547 {
 548         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 549         u32 eec;
 550         u16 eeprom_size;
 551
 552         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 553
 554         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 555                 eeprom->semaphore_delay = 10;
 556                 eeprom->type = ixgbe_flash;
 557
 558                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 559                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 560                                     IXGBE_EEC_SIZE_SHIFT);
 561                 eeprom->word_size = 1 << (eeprom_size +
 562                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 563
 564                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 565                           eeprom->type, eeprom->word_size);
 566         }
 567
 568         return IXGBE_SUCCESS;
 569 }
 570
 571 /**
 572  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 573  *  @hw: pointer to the HW structure
 574  *  @enable_eee: boolean flag to enable EEE
 575  *
 576  *  Enable/disable EEE based on enable_eee flag.
 577  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 578  *  are modified.
 579  *
 580  **/
 581 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 582 {
 583         u32 eeer;
 584         u16 autoneg_eee_reg;
 585         u32 link_reg;
 586         s32 status;
 587
 588         DEBUGFUNC("ixgbe_setup_eee_X550");
 589
 590         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 591         /* Enable or disable EEE per flag */
 592         if (enable_eee) {
 593                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 594
 595                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 596                         /* Advertise EEE capability */
 597                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 598                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 599
 600                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 601                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 602                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 603
 604                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 605                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 606                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 607                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 608                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 609                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 610                         if (status != IXGBE_SUCCESS)
 611                                 return status;
 612
 613                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 614                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 615
 616                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 617                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 618                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 619                         if (status != IXGBE_SUCCESS)
 620                                 return status;
 621                 }
 622         } else {
 623                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 624
 625                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 626                         /* Disable advertised EEE capability */
 627                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 628                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 629
 630                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 631                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 632                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 633
 634                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 635                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 636                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 637                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 638                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 639                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 640                         if (status != IXGBE_SUCCESS)
 641                                 return status;
 642
 643                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 644                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 645
 646                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 647                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 648                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 649                         if (status != IXGBE_SUCCESS)
 650                                 return status;
 651                 }
 652         }
 653         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 654
 655         return IXGBE_SUCCESS;
 656 }
 657
 658 /**
 659  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 660  * @hw: pointer to hardware structure
 661  * @enable: enable or disable source address pruning
 662  * @pool: Rx pool to set source address pruning for
 663  **/
 664 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 665                                            unsigned int pool)
 666 {
 667         u64 pfflp;
 668
 669         /* max rx pool is 63 */
 670         if (pool > 63)
 671                 return;
 672
 673         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 674         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 675
 676         if (enable)
 677                 pfflp |= (1ULL << pool);
 678         else
 679                 pfflp &= ~(1ULL << pool);
 680
 681         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 682         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 683 }
 684
 685 /**
 686  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 687  *  @hw: pointer to hardware structure
 688  *  @enable: enable or disable switch for Ethertype anti-spoofing
 689  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 690  *
 691  **/
 692 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 693                 bool enable, int vf)
 694 {
 695         int vf_target_reg = vf >> 3;
 696         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 697         u32 pfvfspoof;
 698
 699         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 700
 701         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 702         if (enable)
 703                 pfvfspoof |= (1 << vf_target_shift);
 704         else
 705                 pfvfspoof &= ~(1 << vf_target_shift);
 706
 707         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 708 }
 709
 710 /**
 711  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 712  *  device
 713  *  @hw: pointer to hardware structure
 714  *  @reg_addr: 32 bit PHY register to write
 715  *  @device_type: 3 bit device type
 716  *  @data: Data to write to the register
 717  **/
 718 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 719                             u32 device_type, u32 data)
 720 {
 721         u32 i, command, error;
 722
 723         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 724                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 725
 726         /* Write IOSF control register */
 727         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 728
 729         /* Write IOSF data register */
 730         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 731         /*
 732          * Check every 10 usec to see if the address cycle completed.
 733          * The SB IOSF BUSY bit will clear when the operation is
 734          * complete
 735          */
 736         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 737                 usec_delay(10);
 738
 739                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 740                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 741                         break;
 742         }
 743
 744         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 745                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 746                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 747                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 748                               "Failed to write, error %x\n", error);
 749                 return IXGBE_ERR_PHY;
 750         }
 751
 752         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 753                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
 754                 return IXGBE_ERR_PHY;
 755         }
 756
 757         return IXGBE_SUCCESS;
 758 }
 759
 760 /**
 761  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 762  *  device
 763  *  @hw: pointer to hardware structure
 764  *  @reg_addr: 32 bit PHY register to write
 765  *  @device_type: 3 bit device type
 766  *  @phy_data: Pointer to read data from the register
 767  **/
 768 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 769                            u32 device_type, u32 *data)
 770 {
 771         u32 i, command, error;
 772
 773         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 774                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 775
 776         /* Write IOSF control register */
 777         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 778
 779         /*
 780          * Check every 10 usec to see if the address cycle completed.
 781          * The SB IOSF BUSY bit will clear when the operation is
 782          * complete
 783          */
 784         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 785                 usec_delay(10);
 786
 787                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 788                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 789                         break;
 790         }
 791
 792         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 793                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 794                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 795                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 796                                 "Failed to read, error %x\n", error);
 797                 return IXGBE_ERR_PHY;
 798         }
 799
 800         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 801                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
 802                 return IXGBE_ERR_PHY;
 803         }
 804
 805         *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 806
 807         return IXGBE_SUCCESS;
 808 }
 809
 810 /**
 811  *  ixgbe_disable_mdd_X550
 812  *  @hw: pointer to hardware structure
 813  *
 814  *  Disable malicious driver detection
 815  **/
 816 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 817 {
 818         u32 reg;
 819
 820         DEBUGFUNC("ixgbe_disable_mdd_X550");
 821
 822         /* Disable MDD for TX DMA and interrupt */
 823         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 824         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 825         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 826
 827         /* Disable MDD for RX and interrupt */
 828         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 829         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 830         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 831 }
 832
 833 /**
 834  *  ixgbe_enable_mdd_X550
 835  *  @hw: pointer to hardware structure
 836  *
 837  *  Enable malicious driver detection
 838  **/
 839 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 840 {
 841         u32 reg;
 842
 843         DEBUGFUNC("ixgbe_enable_mdd_X550");
 844
 845         /* Enable MDD for TX DMA and interrupt */
 846         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 847         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 848         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 849
 850         /* Enable MDD for RX and interrupt */
 851         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 852         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 853         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 854 }
 855
 856 /**
 857  *  ixgbe_restore_mdd_vf_X550
 858  *  @hw: pointer to hardware structure
 859  *  @vf: vf index
 860  *
 861  *  Restore VF that was disabled during malicious driver detection event
 862  **/
 863 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 864 {
 865         u32 idx, reg, num_qs, start_q, bitmask;
 866
 867         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 868
 869         /* Map VF to queues */
 870         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 871         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 872         case IXGBE_MRQC_VMDQRT8TCEN:
 873                 num_qs = 8;  /* 16 VFs / pools */
 874                 bitmask = 0x000000FF;
 875                 break;
 876         case IXGBE_MRQC_VMDQRSS32EN:
 877         case IXGBE_MRQC_VMDQRT4TCEN:
 878                 num_qs = 4;  /* 32 VFs / pools */
 879                 bitmask = 0x0000000F;
 880                 break;
 881         default:            /* 64 VFs / pools */
 882                 num_qs = 2;
 883                 bitmask = 0x00000003;
 884                 break;
 885         }
 886         start_q = vf * num_qs;
 887
 888         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 889         idx = start_q / 32;
 890         reg = 0;
 891         reg |= (bitmask << (start_q % 32));
 892         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 893         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 894 }
 895
 896 /**
 897  *  ixgbe_mdd_event_X550
 898  *  @hw: pointer to hardware structure
 899  *  @vf_bitmap: vf bitmap of malicious vfs
 900  *
 901  *  Handle malicious driver detection event.
 902  **/
 903 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 904 {
 905         u32 wqbr;
 906         u32 i, j, reg, q, shift, vf, idx;
 907
 908         DEBUGFUNC("ixgbe_mdd_event_X550");
 909
 910         /* figure out pool size for mapping to vf's */
 911         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 912         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 913         case IXGBE_MRQC_VMDQRT8TCEN:
 914                 shift = 3;  /* 16 VFs / pools */
 915                 break;
 916         case IXGBE_MRQC_VMDQRSS32EN:
 917         case IXGBE_MRQC_VMDQRT4TCEN:
 918                 shift = 2;  /* 32 VFs / pools */
 919                 break;
 920         default:
 921                 shift = 1;  /* 64 VFs / pools */
 922                 break;
 923         }
 924
 925         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
 926         for (i = 0; i < 4; i++) {
 927                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
 928                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
 929
 930                 if (!wqbr)
 931                         continue;
 932
 933                 /* Get malicious queue */
 934                 for (j = 0; j < 32 && wqbr; j++) {
 935
 936                         if (!(wqbr & (1 << j)))
 937                                 continue;
 938
 939                         /* Get queue from bitmask */
 940                         q = j + (i * 32);
 941
 942                         /* Map queue to vf */
 943                         vf = (q >> shift);
 944
 945                         /* Set vf bit in vf_bitmap */
 946                         idx = vf / 32;
 947                         vf_bitmap[idx] |= (1 << (vf % 32));
 948                         wqbr &= ~(1 << j);
 949                 }
 950         }
 951 }
 952
 953 /**
 954  *  ixgbe_get_media_type_X550em - Get media type
 955  *  @hw: pointer to hardware structure
 956  *
 957  *  Returns the media type (fiber, copper, backplane)
 958  */
 959 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
 960 {
 961         enum ixgbe_media_type media_type;
 962
 963         DEBUGFUNC("ixgbe_get_media_type_X550em");
 964
 965         /* Detect if there is a copper PHY attached. */
 966         switch (hw->device_id) {
 967         case IXGBE_DEV_ID_X550EM_X_KR:
 968         case IXGBE_DEV_ID_X550EM_X_KX4:
 969                 media_type = ixgbe_media_type_backplane;
 970                 break;
 971         case IXGBE_DEV_ID_X550EM_X_SFP:
 972                 media_type = ixgbe_media_type_fiber;
 973                 break;
 974         case IXGBE_DEV_ID_X550EM_X_1G_T:
 975         case IXGBE_DEV_ID_X550EM_X_10G_T:
 976                 media_type = ixgbe_media_type_copper;
 977                 break;
 978         default:
 979                 media_type = ixgbe_media_type_unknown;
 980                 break;
 981         }
 982         return media_type;
 983 }
 984
 985 /**
 986  *  ixgbe_setup_sfp_modules_X550em - Setup SFP module
 987  *  @hw: pointer to hardware structure
 988  */
 989 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
 990 {
 991         bool setup_linear;
 992         u16 reg_slice, edc_mode;
 993         s32 ret_val;
 994
 995         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
 996
 997         switch (hw->phy.sfp_type) {
 998         case ixgbe_sfp_type_unknown:
 999                 return IXGBE_SUCCESS;
1000         case ixgbe_sfp_type_not_present:
1001                 return IXGBE_ERR_SFP_NOT_PRESENT;
1002         case ixgbe_sfp_type_da_cu_core0:
1003         case ixgbe_sfp_type_da_cu_core1:
1004                 setup_linear = true;
1005                 break;
1006         case ixgbe_sfp_type_srlr_core0:
1007         case ixgbe_sfp_type_srlr_core1:
1008         case ixgbe_sfp_type_da_act_lmt_core0:
1009         case ixgbe_sfp_type_da_act_lmt_core1:
1010         case ixgbe_sfp_type_1g_sx_core0:
1011         case ixgbe_sfp_type_1g_sx_core1:
1012         case ixgbe_sfp_type_1g_lx_core0:
1013         case ixgbe_sfp_type_1g_lx_core1:
1014                 setup_linear = false;
1015                 break;
1016         default:
1017                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1018         }
1019
1020         ixgbe_init_mac_link_ops_X550em(hw);
1021         hw->phy.ops.reset = NULL;
1022
1023         /* The CS4227 slice address is the base address + the port-pair reg
1024          * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
1025          */
1026         reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12);
1027
1028         if (setup_linear)
1029                 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1030         else
1031                 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1032
1033         /* Configure CS4227 for connection type. */
1034         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1035                                            edc_mode);
1036
1037         if (ret_val != IXGBE_SUCCESS)
1038                 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
1039                                                    edc_mode);
1040
1041         return ret_val;
1042 }
1043
1044 /**
1045  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1046  *  @hw: pointer to hardware structure
1047  */
1048 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1049 {
1050         struct ixgbe_mac_info *mac = &hw->mac;
1051
1052         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1053
1054         /* CS4227 does not support autoneg, so disable the laser control
1055          * functions for SFP+ fiber
1056          */
1057          if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1058                 mac->ops.disable_tx_laser = NULL;
1059                 mac->ops.enable_tx_laser = NULL;
1060                 mac->ops.flap_tx_laser = NULL;
1061                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1062                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1063                 mac->ops.set_rate_select_speed =
1064                                         ixgbe_set_soft_rate_select_speed;
1065          }
1066 }
1067
1068 /**
1069  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1070  *  @hw: pointer to hardware structure
1071  *  @speed: pointer to link speed
1072  *  @autoneg: true when autoneg or autotry is enabled
1073  */
1074 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1075                                        ixgbe_link_speed *speed,
1076                                        bool *autoneg)
1077 {
1078         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1079
1080         /* SFP */
1081         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1082
1083                 /* CS4227 SFP must not enable auto-negotiation */
1084                 *autoneg = false;
1085
1086                 /* Check if 1G SFP module. */
1087                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1088                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1089                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1090                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1091                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1092                         return IXGBE_SUCCESS;
1093                 }
1094
1095                 /* Link capabilities are based on SFP */
1096                 if (hw->phy.multispeed_fiber)
1097                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1098                                  IXGBE_LINK_SPEED_1GB_FULL;
1099                 else
1100                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1101         } else {
1102                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1103                          IXGBE_LINK_SPEED_1GB_FULL;
1104                 *autoneg = true;
1105         }
1106
1107         return IXGBE_SUCCESS;
1108 }
1109
1110 /**
1111  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1112  *  @hw: pointer to hardware structure
1113  *
1114  *  Initialize any function pointers that were not able to be
1115  *  set during init_shared_code because the PHY/SFP type was
1116  *  not known.  Perform the SFP init if necessary.
1117  */
1118 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1119 {
1120         struct ixgbe_phy_info *phy = &hw->phy;
1121         s32 ret_val;
1122
1123         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1124
1125         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1126                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1127                 ixgbe_setup_mux_ctl(hw);
1128         }
1129
1130         /* Identify the PHY or SFP module */
1131         ret_val = phy->ops.identify(hw);
1132         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1133                 return ret_val;
1134
1135         /* Setup function pointers based on detected SFP module and speeds */
1136         ixgbe_init_mac_link_ops_X550em(hw);
1137         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1138                 phy->ops.reset = NULL;
1139
1140         /* Set functions pointers based on phy type */
1141         switch (hw->phy.type) {
1142         case ixgbe_phy_x550em_kx4:
1143                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1144                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1145                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1146                 break;
1147         case ixgbe_phy_x550em_kr:
1148                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1149                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1150                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1151                 break;
1152         case ixgbe_phy_x550em_ext_t:
1153                 phy->ops.setup_internal_link =
1154                                          ixgbe_setup_internal_phy_t_x550em;
1155                 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1156                 break;
1157         default:
1158                 break;
1159         }
1160         return ret_val;
1161 }
1162
1163 /**
1164  *  ixgbe_reset_hw_X550em - Perform hardware reset
1165  *  @hw: pointer to hardware structure
1166  *
1167  *  Resets the hardware by resetting the transmit and receive units, masks
1168  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1169  *  reset.
1170  */
1171 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1172 {
1173         struct ixgbe_hic_hdr fw_cmd;
1174         ixgbe_link_speed link_speed;
1175         s32 status;
1176         u32 ctrl = 0;
1177         u32 i;
1178         bool link_up = false;
1179
1180         DEBUGFUNC("ixgbe_reset_hw_X550em");
1181
1182         fw_cmd.cmd = FW_PHY_MGMT_REQ_CMD;
1183         fw_cmd.buf_len = 0;
1184         fw_cmd.cmd_or_resp.cmd_resv = 0;
1185         fw_cmd.checksum = FW_DEFAULT_CHECKSUM;
1186         status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
1187                                               sizeof(fw_cmd),
1188                                               IXGBE_HI_PHY_MGMT_REQ_TIMEOUT,
1189                                               true);
1190         if (status)
1191                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1192                               "PHY mgmt command failed with %d\n", status);
1193         else if (fw_cmd.cmd_or_resp.ret_status != FW_CEM_RESP_STATUS_SUCCESS)
1194                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1195                               "PHY mgmt command returned %d\n",
1196                               fw_cmd.cmd_or_resp.ret_status);
1197
1198         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1199         status = hw->mac.ops.stop_adapter(hw);
1200         if (status != IXGBE_SUCCESS)
1201                 return status;
1202
1203         /* flush pending Tx transactions */
1204         ixgbe_clear_tx_pending(hw);
1205
1206         /* PHY ops must be identified and initialized prior to reset */
1207
1208         /* Identify PHY and related function pointers */
1209         status = hw->phy.ops.init(hw);
1210
1211         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1212                 return status;
1213
1214         /* start the external PHY */
1215         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1216                 status = ixgbe_init_ext_t_x550em(hw);
1217                 if (status)
1218                         return status;
1219         }
1220
1221         /* Setup SFP module if there is one present. */
1222         if (hw->phy.sfp_setup_needed) {
1223                 status = hw->mac.ops.setup_sfp(hw);
1224                 hw->phy.sfp_setup_needed = false;
1225         }
1226
1227         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1228                 return status;
1229
1230         /* Reset PHY */
1231         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1232                 hw->phy.ops.reset(hw);
1233
1234 mac_reset_top:
1235         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1236          * If link reset is used when link is up, it might reset the PHY when
1237          * mng is using it.  If link is down or the flag to force full link
1238          * reset is set, then perform link reset.
1239          */
1240         ctrl = IXGBE_CTRL_LNK_RST;
1241         if (!hw->force_full_reset) {
1242                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1243                 if (link_up)
1244                         ctrl = IXGBE_CTRL_RST;
1245         }
1246
1247         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1248         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1249         IXGBE_WRITE_FLUSH(hw);
1250
1251         /* Poll for reset bit to self-clear meaning reset is complete */
1252         for (i = 0; i < 10; i++) {
1253                 usec_delay(1);
1254                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1255                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1256                         break;
1257         }
1258
1259         if (ctrl & IXGBE_CTRL_RST_MASK) {
1260                 status = IXGBE_ERR_RESET_FAILED;
1261                 DEBUGOUT("Reset polling failed to complete.\n");
1262         }
1263
1264         msec_delay(50);
1265
1266         /* Double resets are required for recovery from certain error
1267          * conditions.  Between resets, it is necessary to stall to
1268          * allow time for any pending HW events to complete.
1269          */
1270         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1271                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1272                 goto mac_reset_top;
1273         }
1274
1275         /* Store the permanent mac address */
1276         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1277
1278         /* Store MAC address from RAR0, clear receive address registers, and
1279          * clear the multicast table.  Also reset num_rar_entries to 128,
1280          * since we modify this value when programming the SAN MAC address.
1281          */
1282         hw->mac.num_rar_entries = 128;
1283         hw->mac.ops.init_rx_addrs(hw);
1284
1285
1286         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1287                 ixgbe_setup_mux_ctl(hw);
1288
1289         return status;
1290 }
1291
1292 /**
1293  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1294  * @hw: pointer to hardware structure
1295  */
1296 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1297 {
1298         u32 status;
1299         u16 reg;
1300
1301         status = hw->phy.ops.read_reg(hw,
1302                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1303                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1304                                       &reg);
1305
1306         if (status != IXGBE_SUCCESS)
1307                 return status;
1308
1309         /* If PHY FW reset completed bit is set then this is the first
1310          * SW instance after a power on so the PHY FW must be un-stalled.
1311          */
1312         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1313                 status = hw->phy.ops.read_reg(hw,
1314                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1315                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1316                                         &reg);
1317
1318                 if (status != IXGBE_SUCCESS)
1319                         return status;
1320
1321                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1322
1323                 status = hw->phy.ops.write_reg(hw,
1324                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1325                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1326                                         reg);
1327
1328                 if (status != IXGBE_SUCCESS)
1329                         return status;
1330         }
1331
1332         return status;
1333 }
1334
1335 /**
1336  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1337  *  @hw: pointer to hardware structure
1338  *
1339  *  Configures the integrated KR PHY.
1340  **/
1341 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1342 {
1343         s32 status;
1344         u32 reg_val;
1345
1346         status = ixgbe_read_iosf_sb_reg_x550(hw,
1347                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1348                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1349         if (status)
1350                 return status;
1351
1352         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1353         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1354                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1355         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1356                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1357
1358         /* Advertise 10G support. */
1359         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1360                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1361
1362         /* Advertise 1G support. */
1363         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1364                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1365
1366         /* Restart auto-negotiation. */
1367         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1368         status = ixgbe_write_iosf_sb_reg_x550(hw,
1369                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1370                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1371
1372         return status;
1373 }
1374
1375 /**
1376  *  ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1377  *  @hw: pointer to hardware structure
1378  *
1379  *  Configures the integrated KX4 PHY.
1380  **/
1381 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1382 {
1383         s32 status;
1384         u32 reg_val;
1385
1386         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1387                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, &reg_val);
1388         if (status)
1389                 return status;
1390
1391         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1392                         IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1393
1394         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1395
1396         /* Advertise 10G support. */
1397         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1398                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1399
1400         /* Advertise 1G support. */
1401         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1402                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1403
1404         /* Restart auto-negotiation. */
1405         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1406         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1407                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, reg_val);
1408
1409         return status;
1410 }
1411
1412 /**
1413  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1414  *  @hw: pointer to hardware structure
1415  *  @speed: the link speed to force
1416  *
1417  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1418  *  internal and external PHY at a specific speed, without autonegotiation.
1419  **/
1420 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1421 {
1422         s32 status;
1423         u32 reg_val;
1424
1425         /* Disable AN and force speed to 10G Serial. */
1426         status = ixgbe_read_iosf_sb_reg_x550(hw,
1427                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1428                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1429         if (status != IXGBE_SUCCESS)
1430                 return status;
1431
1432         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1433         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1434
1435         /* Select forced link speed for internal PHY. */
1436         switch (*speed) {
1437         case IXGBE_LINK_SPEED_10GB_FULL:
1438                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1439                 break;
1440         case IXGBE_LINK_SPEED_1GB_FULL:
1441                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1442                 break;
1443         default:
1444                 /* Other link speeds are not supported by internal KR PHY. */
1445                 return IXGBE_ERR_LINK_SETUP;
1446         }
1447
1448         status = ixgbe_write_iosf_sb_reg_x550(hw,
1449                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1450                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1451         if (status != IXGBE_SUCCESS)
1452                 return status;
1453
1454         /* Disable training protocol FSM. */
1455         status = ixgbe_read_iosf_sb_reg_x550(hw,
1456                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1457                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1458         if (status != IXGBE_SUCCESS)
1459                 return status;
1460         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1461         status = ixgbe_write_iosf_sb_reg_x550(hw,
1462                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1463                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1464         if (status != IXGBE_SUCCESS)
1465                 return status;
1466
1467         /* Disable Flex from training TXFFE. */
1468         status = ixgbe_read_iosf_sb_reg_x550(hw,
1469                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1470                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1471         if (status != IXGBE_SUCCESS)
1472                 return status;
1473         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1474         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1475         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1476         status = ixgbe_write_iosf_sb_reg_x550(hw,
1477                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1478                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1479         if (status != IXGBE_SUCCESS)
1480                 return status;
1481         status = ixgbe_read_iosf_sb_reg_x550(hw,
1482                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1483                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1484         if (status != IXGBE_SUCCESS)
1485                 return status;
1486         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1487         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1488         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1489         status = ixgbe_write_iosf_sb_reg_x550(hw,
1490                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1491                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1492         if (status != IXGBE_SUCCESS)
1493                 return status;
1494
1495         /* Enable override for coefficients. */
1496         status = ixgbe_read_iosf_sb_reg_x550(hw,
1497                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1498                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1499         if (status != IXGBE_SUCCESS)
1500                 return status;
1501         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1502         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1503         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1504         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1505         status = ixgbe_write_iosf_sb_reg_x550(hw,
1506                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1507                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1508         if (status != IXGBE_SUCCESS)
1509                 return status;
1510
1511         /* Toggle port SW reset by AN reset. */
1512         status = ixgbe_read_iosf_sb_reg_x550(hw,
1513                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1514                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1515         if (status != IXGBE_SUCCESS)
1516                 return status;
1517         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1518         status = ixgbe_write_iosf_sb_reg_x550(hw,
1519                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1520                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1521
1522         return status;
1523 }
1524
1525 /**
1526  *  ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1527  *  @hw: pointer to hardware structure
1528  *
1529  *  Configures the integrated KR PHY for SFP support.
1530  **/
1531 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1532                                     ixgbe_link_speed speed,
1533                                     bool autoneg_wait_to_complete)
1534 {
1535         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1536
1537         return ixgbe_setup_ixfi_x550em(hw, &speed);
1538 }
1539
1540 /**
1541  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1542  * @hw: point to hardware structure
1543  *
1544  * Configures the link between the integrated KR PHY and the external X557 PHY
1545  * The driver will call this function when it gets a link status change
1546  * interrupt from the X557 PHY. This function configures the link speed
1547  * between the PHYs to match the link speed of the BASE-T link.
1548  *
1549  * A return of a non-zero value indicates an error, and the base driver should
1550  * not report link up.
1551  */
1552 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1553 {
1554         u32 status;
1555         u16 autoneg_status, speed;
1556         ixgbe_link_speed force_speed;
1557
1558         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1559                 return IXGBE_ERR_CONFIG;
1560
1561         /* read this twice back to back to indicate current status */
1562         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1563                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1564                                       &autoneg_status);
1565         if (status != IXGBE_SUCCESS)
1566                 return status;
1567
1568         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1569                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1570                                       &autoneg_status);
1571         if (status != IXGBE_SUCCESS)
1572                 return status;
1573
1574         /* If link is not up, then there is no setup necessary so return  */
1575         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1576                 return IXGBE_SUCCESS;
1577
1578         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1579                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1580                                       &speed);
1581
1582         /* clear everything but the speed and duplex bits */
1583         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1584
1585         switch (speed) {
1586         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1587                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1588                 break;
1589         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1590                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1591                 break;
1592         default:
1593                 /* Internal PHY does not support anything else */
1594                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1595         }
1596
1597         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1598 }
1599
1600 /**
1601  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1602  *  @hw: pointer to hardware structure
1603  *
1604  *  Configures the integrated KR PHY to use internal loopback mode.
1605  **/
1606 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1607 {
1608         s32 status;
1609         u32 reg_val;
1610
1611         /* Disable AN and force speed to 10G Serial. */
1612         status = ixgbe_read_iosf_sb_reg_x550(hw,
1613                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1614                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1615         if (status != IXGBE_SUCCESS)
1616                 return status;
1617         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1618         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1619         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1620         status = ixgbe_write_iosf_sb_reg_x550(hw,
1621                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1622                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1623         if (status != IXGBE_SUCCESS)
1624                 return status;
1625
1626         /* Set near-end loopback clocks. */
1627         status = ixgbe_read_iosf_sb_reg_x550(hw,
1628                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1629                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1630         if (status != IXGBE_SUCCESS)
1631                 return status;
1632         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1633         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1634         status = ixgbe_write_iosf_sb_reg_x550(hw,
1635                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1636                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1637         if (status != IXGBE_SUCCESS)
1638                 return status;
1639
1640         /* Set loopback enable. */
1641         status = ixgbe_read_iosf_sb_reg_x550(hw,
1642                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1643                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1644         if (status != IXGBE_SUCCESS)
1645                 return status;
1646         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1647         status = ixgbe_write_iosf_sb_reg_x550(hw,
1648                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1649                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1650         if (status != IXGBE_SUCCESS)
1651                 return status;
1652
1653         /* Training bypass. */
1654         status = ixgbe_read_iosf_sb_reg_x550(hw,
1655                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1656                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1657         if (status != IXGBE_SUCCESS)
1658                 return status;
1659         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1660         status = ixgbe_write_iosf_sb_reg_x550(hw,
1661                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1662                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1663
1664         return status;
1665 }
1666
1667 /**
1668  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1669  *  assuming that the semaphore is already obtained.
1670  *  @hw: pointer to hardware structure
1671  *  @offset: offset of  word in the EEPROM to read
1672  *  @data: word read from the EEPROM
1673  *
1674  *  Reads a 16 bit word from the EEPROM using the hostif.
1675  **/
1676 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1677                                    u16 *data)
1678 {
1679         s32 status;
1680         struct ixgbe_hic_read_shadow_ram buffer;
1681
1682         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1683         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1684         buffer.hdr.req.buf_lenh = 0;
1685         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1686         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1687
1688         /* convert offset from words to bytes */
1689         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1690         /* one word */
1691         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1692
1693         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1694                                               sizeof(buffer),
1695                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1696
1697         if (status)
1698                 return status;
1699
1700         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1701                                           FW_NVM_DATA_OFFSET);
1702
1703         return 0;
1704 }
1705
1706 /**
1707  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1708  *  @hw: pointer to hardware structure
1709  *  @offset: offset of  word in the EEPROM to read
1710  *  @data: word read from the EEPROM
1711  *
1712  *  Reads a 16 bit word from the EEPROM using the hostif.
1713  **/
1714 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1715                               u16 *data)
1716 {
1717         s32 status = IXGBE_SUCCESS;
1718
1719         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1720
1721         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1722             IXGBE_SUCCESS) {
1723                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1724                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1725         } else {
1726                 status = IXGBE_ERR_SWFW_SYNC;
1727         }
1728
1729         return status;
1730 }
1731
1732 /**
1733  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1734  *  @hw: pointer to hardware structure
1735  *  @offset: offset of  word in the EEPROM to read
1736  *  @words: number of words
1737  *  @data: word(s) read from the EEPROM
1738  *
1739  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
1740  **/
1741 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1742                                      u16 offset, u16 words, u16 *data)
1743 {
1744         struct ixgbe_hic_read_shadow_ram buffer;
1745         u32 current_word = 0;
1746         u16 words_to_read;
1747         s32 status;
1748         u32 i;
1749
1750         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1751
1752         /* Take semaphore for the entire operation. */
1753         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1754         if (status) {
1755                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1756                 return status;
1757         }
1758         while (words) {
1759                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1760                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1761                 else
1762                         words_to_read = words;
1763
1764                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1765                 buffer.hdr.req.buf_lenh = 0;
1766                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1767                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1768
1769                 /* convert offset from words to bytes */
1770                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1771                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1772
1773                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1774                                                       sizeof(buffer),
1775                                                       IXGBE_HI_COMMAND_TIMEOUT,
1776                                                       false);
1777
1778                 if (status) {
1779                         DEBUGOUT("Host interface command failed\n");
1780                         goto out;
1781                 }
1782
1783                 for (i = 0; i < words_to_read; i++) {
1784                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1785                                   2 * i;
1786                         u32 value = IXGBE_READ_REG(hw, reg);
1787
1788                         data[current_word] = (u16)(value & 0xffff);
1789                         current_word++;
1790                         i++;
1791                         if (i < words_to_read) {
1792                                 value >>= 16;
1793                                 data[current_word] = (u16)(value & 0xffff);
1794                                 current_word++;
1795                         }
1796                 }
1797                 words -= words_to_read;
1798         }
1799
1800 out:
1801         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1802         return status;
1803 }
1804
1805 /**
1806  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1807  *  @hw: pointer to hardware structure
1808  *  @offset: offset of  word in the EEPROM to write
1809  *  @data: word write to the EEPROM
1810  *
1811  *  Write a 16 bit word to the EEPROM using the hostif.
1812  **/
1813 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1814                                     u16 data)
1815 {
1816         s32 status;
1817         struct ixgbe_hic_write_shadow_ram buffer;
1818
1819         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1820
1821         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1822         buffer.hdr.req.buf_lenh = 0;
1823         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1824         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1825
1826          /* one word */
1827         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1828         buffer.data = data;
1829         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1830
1831         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1832                                               sizeof(buffer),
1833                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1834
1835         return status;
1836 }
1837
1838 /**
1839  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1840  *  @hw: pointer to hardware structure
1841  *  @offset: offset of  word in the EEPROM to write
1842  *  @data: word write to the EEPROM
1843  *
1844  *  Write a 16 bit word to the EEPROM using the hostif.
1845  **/
1846 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1847                                u16 data)
1848 {
1849         s32 status = IXGBE_SUCCESS;
1850
1851         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
1852
1853         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1854             IXGBE_SUCCESS) {
1855                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1856                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1857         } else {
1858                 DEBUGOUT("write ee hostif failed to get semaphore");
1859                 status = IXGBE_ERR_SWFW_SYNC;
1860         }
1861
1862         return status;
1863 }
1864
1865 /**
1866  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1867  *  @hw: pointer to hardware structure
1868  *  @offset: offset of  word in the EEPROM to write
1869  *  @words: number of words
1870  *  @data: word(s) write to the EEPROM
1871  *
1872  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1873  **/
1874 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1875                                       u16 offset, u16 words, u16 *data)
1876 {
1877         s32 status = IXGBE_SUCCESS;
1878         u32 i = 0;
1879
1880         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
1881
1882         /* Take semaphore for the entire operation. */
1883         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1884         if (status != IXGBE_SUCCESS) {
1885                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
1886                 goto out;
1887         }
1888
1889         for (i = 0; i < words; i++) {
1890                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1891                                                          data[i]);
1892
1893                 if (status != IXGBE_SUCCESS) {
1894                         DEBUGOUT("Eeprom buffered write failed\n");
1895                         break;
1896                 }
1897         }
1898
1899         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1900 out:
1901
1902         return status;
1903 }
1904
1905 /**
1906  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
1907  * @hw: pointer to hardware structure
1908  * @ptr: pointer offset in eeprom
1909  * @size: size of section pointed by ptr, if 0 first word will be used as size
1910  * @csum: address of checksum to update
1911  *
1912  * Returns error status for any failure
1913  */
1914 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
1915                                    u16 size, u16 *csum, u16 *buffer,
1916                                    u32 buffer_size)
1917 {
1918         u16 buf[256];
1919         s32 status;
1920         u16 length, bufsz, i, start;
1921         u16 *local_buffer;
1922
1923         bufsz = sizeof(buf) / sizeof(buf[0]);
1924
1925         /* Read a chunk at the pointer location */
1926         if (!buffer) {
1927                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
1928                 if (status) {
1929                         DEBUGOUT("Failed to read EEPROM image\n");
1930                         return status;
1931                 }
1932                 local_buffer = buf;
1933         } else {
1934                 if (buffer_size < ptr)
1935                         return  IXGBE_ERR_PARAM;
1936                 local_buffer = &buffer[ptr];
1937         }
1938
1939         if (size) {
1940                 start = 0;
1941                 length = size;
1942         } else {
1943                 start = 1;
1944                 length = local_buffer[0];
1945
1946                 /* Skip pointer section if length is invalid. */
1947                 if (length == 0xFFFF || length == 0 ||
1948                     (ptr + length) >= hw->eeprom.word_size)
1949                         return IXGBE_SUCCESS;
1950         }
1951
1952         if (buffer && ((u32)start + (u32)length > buffer_size))
1953                 return IXGBE_ERR_PARAM;
1954
1955         for (i = start; length; i++, length--) {
1956                 if (i == bufsz && !buffer) {
1957                         ptr += bufsz;
1958                         i = 0;
1959                         if (length < bufsz)
1960                                 bufsz = length;
1961
1962                         /* Read a chunk at the pointer location */
1963                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
1964                                                                   bufsz, buf);
1965                         if (status) {
1966                                 DEBUGOUT("Failed to read EEPROM image\n");
1967                                 return status;
1968                         }
1969                 }
1970                 *csum += local_buffer[i];
1971         }
1972         return IXGBE_SUCCESS;
1973 }
1974
1975 /**
1976  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
1977  *  @hw: pointer to hardware structure
1978  *  @buffer: pointer to buffer containing calculated checksum
1979  *  @buffer_size: size of buffer
1980  *
1981  *  Returns a negative error code on error, or the 16-bit checksum
1982  **/
1983 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
1984 {
1985         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
1986         u16 *local_buffer;
1987         s32 status;
1988         u16 checksum = 0;
1989         u16 pointer, i, size;
1990
1991         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
1992
1993         hw->eeprom.ops.init_params(hw);
1994
1995         if (!buffer) {
1996                 /* Read pointer area */
1997                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1998                                                      IXGBE_EEPROM_LAST_WORD + 1,
1999                                                      eeprom_ptrs);
2000                 if (status) {
2001                         DEBUGOUT("Failed to read EEPROM image\n");
2002                         return status;
2003                 }
2004                 local_buffer = eeprom_ptrs;
2005         } else {
2006                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2007                         return IXGBE_ERR_PARAM;
2008                 local_buffer = buffer;
2009         }
2010
2011         /*
2012          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2013          * checksum word itself
2014          */
2015         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2016                 if (i != IXGBE_EEPROM_CHECKSUM)
2017                         checksum += local_buffer[i];
2018
2019         /*
2020          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2021          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2022          */
2023         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2024                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2025                         continue;
2026
2027                 pointer = local_buffer[i];
2028
2029                 /* Skip pointer section if the pointer is invalid. */
2030                 if (pointer == 0xFFFF || pointer == 0 ||
2031                     pointer >= hw->eeprom.word_size)
2032                         continue;
2033
2034                 switch (i) {
2035                 case IXGBE_PCIE_GENERAL_PTR:
2036                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2037                         break;
2038                 case IXGBE_PCIE_CONFIG0_PTR:
2039                 case IXGBE_PCIE_CONFIG1_PTR:
2040                         size = IXGBE_PCIE_CONFIG_SIZE;
2041                         break;
2042                 default:
2043                         size = 0;
2044                         break;
2045                 }
2046
2047                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2048                                                 buffer, buffer_size);
2049                 if (status)
2050                         return status;
2051         }
2052
2053         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2054
2055         return (s32)checksum;
2056 }
2057
2058 /**
2059  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2060  *  @hw: pointer to hardware structure
2061  *
2062  *  Returns a negative error code on error, or the 16-bit checksum
2063  **/
2064 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2065 {
2066         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2067 }
2068
2069 /**
2070  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2071  *  @hw: pointer to hardware structure
2072  *  @checksum_val: calculated checksum
2073  *
2074  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2075  *  caller does not need checksum_val, the value can be NULL.
2076  **/
2077 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2078 {
2079         s32 status;
2080         u16 checksum;
2081         u16 read_checksum = 0;
2082
2083         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2084
2085         /* Read the first word from the EEPROM. If this times out or fails, do
2086          * not continue or we could be in for a very long wait while every
2087          * EEPROM read fails
2088          */
2089         status = hw->eeprom.ops.read(hw, 0, &checksum);
2090         if (status) {
2091                 DEBUGOUT("EEPROM read failed\n");
2092                 return status;
2093         }
2094
2095         status = hw->eeprom.ops.calc_checksum(hw);
2096         if (status < 0)
2097                 return status;
2098
2099         checksum = (u16)(status & 0xffff);
2100
2101         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2102                                            &read_checksum);
2103         if (status)
2104                 return status;
2105
2106         /* Verify read checksum from EEPROM is the same as
2107          * calculated checksum
2108          */
2109         if (read_checksum != checksum) {
2110                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2111                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2112                              "Invalid EEPROM checksum");
2113         }
2114
2115         /* If the user cares, return the calculated checksum */
2116         if (checksum_val)
2117                 *checksum_val = checksum;
2118
2119         return status;
2120 }
2121
2122 /**
2123  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2124  * @hw: pointer to hardware structure
2125  *
2126  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2127  * checksum and updates the EEPROM and instructs the hardware to update
2128  * the flash.
2129  **/
2130 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2131 {
2132         s32 status;
2133         u16 checksum = 0;
2134
2135         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2136
2137         /* Read the first word from the EEPROM. If this times out or fails, do
2138          * not continue or we could be in for a very long wait while every
2139          * EEPROM read fails
2140          */
2141         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2142         if (status) {
2143                 DEBUGOUT("EEPROM read failed\n");
2144                 return status;
2145         }
2146
2147         status = ixgbe_calc_eeprom_checksum_X550(hw);
2148         if (status < 0)
2149                 return status;
2150
2151         checksum = (u16)(status & 0xffff);
2152
2153         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2154                                             checksum);
2155         if (status)
2156                 return status;
2157
2158         status = ixgbe_update_flash_X550(hw);
2159
2160         return status;
2161 }
2162
2163 /**
2164  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2165  *  @hw: pointer to hardware structure
2166  *
2167  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2168  **/
2169 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2170 {
2171         s32 status = IXGBE_SUCCESS;
2172         union ixgbe_hic_hdr2 buffer;
2173
2174         DEBUGFUNC("ixgbe_update_flash_X550");
2175
2176         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2177         buffer.req.buf_lenh = 0;
2178         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2179         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2180
2181         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2182                                               sizeof(buffer),
2183                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2184
2185         return status;
2186 }
2187
2188 /**
2189  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2190  *  @hw: pointer to hardware structure
2191  *
2192  *  Determines physical layer capabilities of the current configuration.
2193  **/
2194 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2195 {
2196         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2197         u16 ext_ability = 0;
2198
2199         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2200
2201         hw->phy.ops.identify(hw);
2202
2203         switch (hw->phy.type) {
2204         case ixgbe_phy_x550em_kr:
2205                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2206                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2207                 break;
2208         case ixgbe_phy_x550em_kx4:
2209                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2210                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2211                 break;
2212         case ixgbe_phy_x550em_ext_t:
2213                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2214                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2215                                      &ext_ability);
2216                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2217                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2218                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2219                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2220                 break;
2221         default:
2222                 break;
2223         }
2224
2225         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2226                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2227
2228         return physical_layer;
2229 }
2230
2231 /**
2232  * ixgbe_get_bus_info_x550em - Set PCI bus info
2233  * @hw: pointer to hardware structure
2234  *
2235  * Sets bus link width and speed to unknown because X550em is
2236  * not a PCI device.
2237  **/
2238 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2239 {
2240
2241         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2242
2243         hw->bus.width = ixgbe_bus_width_unknown;
2244         hw->bus.speed = ixgbe_bus_speed_unknown;
2245
2246         return IXGBE_SUCCESS;
2247 }
2248
2249 /**
2250  * ixgbe_disable_rx_x550 - Disable RX unit
2251  *
2252  * Enables the Rx DMA unit for x550
2253  **/
2254 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2255 {
2256         u32 rxctrl, pfdtxgswc;
2257         s32 status;
2258         struct ixgbe_hic_disable_rxen fw_cmd;
2259
2260         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2261
2262         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2263         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2264                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2265                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2266                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2267                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2268                         hw->mac.set_lben = true;
2269                 } else {
2270                         hw->mac.set_lben = false;
2271                 }
2272
2273                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2274                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2275                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2276                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2277
2278                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2279                                         sizeof(struct ixgbe_hic_disable_rxen),
2280                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2281
2282                 /* If we fail - disable RX using register write */
2283                 if (status) {
2284                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2285                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2286                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2287                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2288                         }
2289                 }
2290         }
2291 }
2292
2293 /**
2294  * ixgbe_enter_lplu_x550em - Transition to low power states
2295  *  @hw: pointer to hardware structure
2296  *
2297  * Configures Low Power Link Up on transition to low power states
2298  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2299  * X557 PHY immediately prior to entering LPLU.
2300  **/
2301 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2302 {
2303         u16 autoneg_status, an_10g_cntl_reg, autoneg_reg, speed;
2304         s32 status;
2305         ixgbe_link_speed lcd_speed;
2306
2307         /* If blocked by MNG FW, then don't restart AN */
2308         if (ixgbe_check_reset_blocked(hw))
2309                 return IXGBE_SUCCESS;
2310
2311         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2312                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2313                                       &autoneg_status);
2314
2315         if (status != IXGBE_SUCCESS)
2316                 return status;
2317
2318         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2319
2320         if (status != IXGBE_SUCCESS)
2321                 return status;
2322
2323         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2324          * disabled, then force link down by entering low power mode.
2325          */
2326         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS) ||
2327             !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2328             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2329                 return ixgbe_set_copper_phy_power(hw, FALSE);
2330
2331         /* Determine LCD */
2332         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2333
2334         if (status != IXGBE_SUCCESS)
2335                 return status;
2336
2337         /* If no valid LCD link speed, then force link down and exit. */
2338         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2339                 return ixgbe_set_copper_phy_power(hw, FALSE);
2340
2341         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2342                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2343                                       &speed);
2344
2345         if (status != IXGBE_SUCCESS)
2346                 return status;
2347
2348         /* clear everything but the speed bits */
2349         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2350
2351         /* If current speed is already LCD, then exit. */
2352         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2353              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2354             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2355              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2356                 return status;
2357
2358         /* Clear AN completed indication */
2359         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2360                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2361                                       &autoneg_status);
2362
2363         if (status != IXGBE_SUCCESS)
2364                 return status;
2365
2366         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2367                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2368                              &an_10g_cntl_reg);
2369
2370         if (status != IXGBE_SUCCESS)
2371                 return status;
2372
2373         status = hw->phy.ops.read_reg(hw,
2374                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2375                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2376                              &autoneg_reg);
2377
2378         if (status != IXGBE_SUCCESS)
2379                 return status;
2380
2381         /* Set AN advertizement to only include LCD  */
2382         if (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL) {
2383                 an_10g_cntl_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
2384                 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
2385         }
2386
2387         if (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL) {
2388                 an_10g_cntl_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
2389                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
2390         }
2391
2392         status = hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2393                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2394                               an_10g_cntl_reg);
2395
2396         if (status != IXGBE_SUCCESS)
2397                 return status;
2398
2399         status = hw->phy.ops.write_reg(hw,
2400                               IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2401                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2402                               autoneg_reg);
2403
2404         if (status != IXGBE_SUCCESS)
2405                 return status;
2406
2407         /* Restart PHY auto-negotiation. */
2408         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
2409                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
2410
2411         if (status != IXGBE_SUCCESS)
2412                 return status;
2413
2414         autoneg_reg |= IXGBE_MII_RESTART;
2415
2416         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
2417                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
2418
2419         if (status != IXGBE_SUCCESS)
2420                 return status;
2421
2422         status = ixgbe_setup_ixfi_x550em(hw, &lcd_speed);
2423
2424         return status;
2425 }
2426
2427 /**
2428  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2429  *  @hw: pointer to hardware structure
2430  *  @lcd_speed: pointer to lowest common link speed
2431  *
2432  * Determine lowest common link speed with link partner.
2433  **/
2434 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2435 {
2436         u16 an_lp_status;
2437         s32 status;
2438         u16 word = hw->eeprom.ctrl_word_3;
2439
2440         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2441
2442         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2443                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2444                                       &an_lp_status);
2445
2446         if (status != IXGBE_SUCCESS)
2447                 return status;
2448
2449         /* If link partner advertised 1G, return 1G */
2450         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2451                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2452                 return status;
2453         }
2454
2455         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2456         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2457             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2458                 return status;
2459
2460         /* Link partner not capable of lower speeds, return 10G */
2461         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2462         return status;
2463 }
2464
2465 /**
2466  *  ixgbe_setup_fc_X550em - Set up flow control
2467  *  @hw: pointer to hardware structure
2468  *
2469  *  Called at init time to set up flow control.
2470  **/
2471 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2472 {
2473         s32 ret_val = IXGBE_SUCCESS;
2474         u32 pause, asm_dir, reg_val;
2475
2476         DEBUGFUNC("ixgbe_setup_fc_X550em");
2477
2478         /* Validate the requested mode */
2479         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2480                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2481                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2482                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2483                 goto out;
2484         }
2485
2486         /* 10gig parts do not have a word in the EEPROM to determine the
2487          * default flow control setting, so we explicitly set it to full.
2488          */
2489         if (hw->fc.requested_mode == ixgbe_fc_default)
2490                 hw->fc.requested_mode = ixgbe_fc_full;
2491
2492         /* Determine PAUSE and ASM_DIR bits. */
2493         switch (hw->fc.requested_mode) {
2494         case ixgbe_fc_none:
2495                 pause = 0;
2496                 asm_dir = 0;
2497                 break;
2498         case ixgbe_fc_tx_pause:
2499                 pause = 0;
2500                 asm_dir = 1;
2501                 break;
2502         case ixgbe_fc_rx_pause:
2503                 /* Rx Flow control is enabled and Tx Flow control is
2504                  * disabled by software override. Since there really
2505                  * isn't a way to advertise that we are capable of RX
2506                  * Pause ONLY, we will advertise that we support both
2507                  * symmetric and asymmetric Rx PAUSE, as such we fall
2508                  * through to the fc_full statement.  Later, we will
2509                  * disable the adapter's ability to send PAUSE frames.
2510                  */
2511         case ixgbe_fc_full:
2512                 pause = 1;
2513                 asm_dir = 1;
2514                 break;
2515         default:
2516                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2517                         "Flow control param set incorrectly\n");
2518                 ret_val = IXGBE_ERR_CONFIG;
2519                 goto out;
2520         }
2521
2522         if (hw->phy.media_type == ixgbe_media_type_backplane) {
2523                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2524                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2525                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2526                 if (ret_val != IXGBE_SUCCESS)
2527                         goto out;
2528                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2529                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2530                 if (pause)
2531                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2532                 if (asm_dir)
2533                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2534                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2535                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2536                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2537
2538                 /* Not all devices fully support AN. */
2539                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR)
2540                         hw->fc.disable_fc_autoneg = true;
2541         }
2542
2543 out:
2544         return ret_val;
2545 }
2546
2547 /**
2548  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2549  * @hw: pointer to hardware structure
2550  * @state: set mux if 1, clear if 0
2551  */
2552 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2553 {
2554         u32 esdp;
2555
2556         if (!hw->bus.lan_id)
2557                 return;
2558         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2559         if (state)
2560                 esdp |= IXGBE_ESDP_SDP1;
2561         else
2562                 esdp &= ~IXGBE_ESDP_SDP1;
2563         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2564         IXGBE_WRITE_FLUSH(hw);
2565 }
2566
2567 /**
2568  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2569  *  @hw: pointer to hardware structure
2570  *  @mask: Mask to specify which semaphore to acquire
2571  *
2572  *  Acquires the SWFW semaphore and sets the I2C MUX
2573  **/
2574 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2575 {
2576         s32 status;
2577
2578         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2579
2580         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2581         if (status)
2582                 return status;
2583
2584         if (mask & IXGBE_GSSR_I2C_MASK)
2585                 ixgbe_set_mux(hw, 1);
2586
2587         return IXGBE_SUCCESS;
2588 }
2589
2590 /**
2591  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2592  *  @hw: pointer to hardware structure
2593  *  @mask: Mask to specify which semaphore to release
2594  *
2595  *  Releases the SWFW semaphore and sets the I2C MUX
2596  **/
2597 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2598 {
2599         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2600
2601         if (mask & IXGBE_GSSR_I2C_MASK)
2602                 ixgbe_set_mux(hw, 0);
2603
2604         ixgbe_release_swfw_sync_X540(hw, mask);
2605 }