1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
43 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
44 * @hw: pointer to hardware structure
46 * Initialize the function pointers and assign the MAC type for X550.
47 * Does not touch the hardware.
49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
51 struct ixgbe_mac_info *mac = &hw->mac;
52 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
55 DEBUGFUNC("ixgbe_init_ops_X550");
57 ret_val = ixgbe_init_ops_X540(hw);
58 mac->ops.dmac_config = ixgbe_dmac_config_X550;
59 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
60 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
61 mac->ops.setup_eee = ixgbe_setup_eee_X550;
62 mac->ops.set_source_address_pruning =
63 ixgbe_set_source_address_pruning_X550;
64 mac->ops.set_ethertype_anti_spoofing =
65 ixgbe_set_ethertype_anti_spoofing_X550;
67 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
68 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
69 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
70 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
71 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
72 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
73 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
74 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
75 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
77 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
78 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
79 mac->ops.mdd_event = ixgbe_mdd_event_X550;
80 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
81 mac->ops.disable_rx = ixgbe_disable_rx_x550;
86 * ixgbe_read_cs4227 - Read CS4227 register
87 * @hw: pointer to hardware structure
88 * @reg: register number to write
89 * @value: pointer to receive value read
93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
95 return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
99 * ixgbe_write_cs4227 - Write CS4227 register
100 * @hw: pointer to hardware structure
101 * @reg: register number to write
102 * @value: value to write to register
104 * Returns status code
106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
108 return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
112 * ixgbe_get_cs4227_status - Return CS4227 status
113 * @hw: pointer to hardware structure
115 * Returns error if CS4227 not successfully initialized
117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
123 for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
124 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
126 if (status != IXGBE_SUCCESS)
128 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
130 msec_delay(IXGBE_CS4227_CHECK_DELAY);
132 if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
133 return IXGBE_ERR_PHY;
135 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
136 IXGBE_CS4227_SCRATCH_VALUE);
137 if (status != IXGBE_SUCCESS)
139 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
140 if (status != IXGBE_SUCCESS)
142 if (value != IXGBE_CS4227_SCRATCH_VALUE)
143 return IXGBE_ERR_PHY;
144 return IXGBE_SUCCESS;
148 * ixgbe_read_pe - Read register from port expander
149 * @hw: pointer to hardware structure
150 * @reg: register number to read
151 * @value: pointer to receive read value
153 * Returns status code
155 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
159 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
160 if (status != IXGBE_SUCCESS)
161 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
162 "port expander access failed with %d\n", status);
167 * ixgbe_write_pe - Write register to port expander
168 * @hw: pointer to hardware structure
169 * @reg: register number to write
170 * @value: value to write
172 * Returns status code
174 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
178 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
179 if (status != IXGBE_SUCCESS)
180 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
181 "port expander access failed with %d\n", status);
186 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
187 * @hw: pointer to hardware structure
191 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
196 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
197 if (status != IXGBE_SUCCESS)
199 reg |= IXGBE_PE_BIT1;
200 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
201 if (status != IXGBE_SUCCESS)
204 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
205 if (status != IXGBE_SUCCESS)
207 reg &= ~IXGBE_PE_BIT1;
208 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
209 if (status != IXGBE_SUCCESS)
212 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
213 if (status != IXGBE_SUCCESS)
215 reg &= ~IXGBE_PE_BIT1;
216 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
217 if (status != IXGBE_SUCCESS)
220 usec_delay(IXGBE_CS4227_RESET_HOLD);
222 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
223 if (status != IXGBE_SUCCESS)
225 reg |= IXGBE_PE_BIT1;
226 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
227 if (status != IXGBE_SUCCESS)
230 msec_delay(IXGBE_CS4227_RESET_DELAY);
232 return IXGBE_SUCCESS;
236 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
237 * @hw: pointer to hardware structure
239 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
241 u32 swfw_mask = hw->phy.phy_semaphore_mask;
245 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
246 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
247 if (status != IXGBE_SUCCESS) {
248 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
249 "semaphore failed with %d\n", status);
252 status = ixgbe_get_cs4227_status(hw);
253 if (status == IXGBE_SUCCESS) {
254 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
255 msec_delay(hw->eeprom.semaphore_delay);
258 ixgbe_reset_cs4227(hw);
259 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
260 msec_delay(hw->eeprom.semaphore_delay);
262 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
263 "Unable to initialize CS4227, err=%d\n", status);
267 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
268 * @hw: pointer to hardware structure
270 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
272 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
274 if (hw->bus.lan_id) {
275 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
276 esdp |= IXGBE_ESDP_SDP1_DIR;
278 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
279 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
280 IXGBE_WRITE_FLUSH(hw);
284 * ixgbe_identify_phy_x550em - Get PHY type based on device id
285 * @hw: pointer to hardware structure
289 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
291 switch (hw->device_id) {
292 case IXGBE_DEV_ID_X550EM_X_SFP:
293 /* set up for CS4227 usage */
294 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
295 ixgbe_setup_mux_ctl(hw);
296 ixgbe_check_cs4227(hw);
298 return ixgbe_identify_module_generic(hw);
300 case IXGBE_DEV_ID_X550EM_X_KX4:
301 hw->phy.type = ixgbe_phy_x550em_kx4;
303 case IXGBE_DEV_ID_X550EM_X_KR:
304 hw->phy.type = ixgbe_phy_x550em_kr;
306 case IXGBE_DEV_ID_X550EM_X_1G_T:
307 case IXGBE_DEV_ID_X550EM_X_10G_T:
308 return ixgbe_identify_phy_generic(hw);
312 return IXGBE_SUCCESS;
315 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
316 u32 device_type, u16 *phy_data)
318 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
319 return IXGBE_NOT_IMPLEMENTED;
322 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
323 u32 device_type, u16 phy_data)
325 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
326 return IXGBE_NOT_IMPLEMENTED;
330 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
331 * @hw: pointer to hardware structure
333 * Initialize the function pointers and for MAC type X550EM.
334 * Does not touch the hardware.
336 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
338 struct ixgbe_mac_info *mac = &hw->mac;
339 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
340 struct ixgbe_phy_info *phy = &hw->phy;
343 DEBUGFUNC("ixgbe_init_ops_X550EM");
345 /* Similar to X550 so start there. */
346 ret_val = ixgbe_init_ops_X550(hw);
348 /* Since this function eventually calls
349 * ixgbe_init_ops_540 by design, we are setting
350 * the pointers to NULL explicitly here to overwrite
351 * the values being set in the x540 function.
353 /* Thermal sensor not supported in x550EM */
354 mac->ops.get_thermal_sensor_data = NULL;
355 mac->ops.init_thermal_sensor_thresh = NULL;
356 mac->thermal_sensor_enabled = false;
358 /* FCOE not supported in x550EM */
359 mac->ops.get_san_mac_addr = NULL;
360 mac->ops.set_san_mac_addr = NULL;
361 mac->ops.get_wwn_prefix = NULL;
362 mac->ops.get_fcoe_boot_status = NULL;
364 /* IPsec not supported in x550EM */
365 mac->ops.disable_sec_rx_path = NULL;
366 mac->ops.enable_sec_rx_path = NULL;
368 /* AUTOC register is not present in x550EM. */
369 mac->ops.prot_autoc_read = NULL;
370 mac->ops.prot_autoc_write = NULL;
372 /* X550EM bus type is internal*/
373 hw->bus.type = ixgbe_bus_type_internal;
374 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
376 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
377 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
378 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
379 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
380 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
381 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
382 mac->ops.get_supported_physical_layer =
383 ixgbe_get_supported_physical_layer_X550em;
385 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
386 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
387 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
390 phy->ops.init = ixgbe_init_phy_ops_X550em;
391 phy->ops.identify = ixgbe_identify_phy_x550em;
392 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
393 phy->ops.set_phy_power = NULL;
397 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
398 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
399 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
400 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
401 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
402 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
403 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
404 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
410 * ixgbe_dmac_config_X550
411 * @hw: pointer to hardware structure
413 * Configure DMA coalescing. If enabling dmac, dmac is activated.
414 * When disabling dmac, dmac enable dmac bit is cleared.
416 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
418 u32 reg, high_pri_tc;
420 DEBUGFUNC("ixgbe_dmac_config_X550");
422 /* Disable DMA coalescing before configuring */
423 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
424 reg &= ~IXGBE_DMACR_DMAC_EN;
425 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
427 /* Disable DMA Coalescing if the watchdog timer is 0 */
428 if (!hw->mac.dmac_config.watchdog_timer)
431 ixgbe_dmac_config_tcs_X550(hw);
433 /* Configure DMA Coalescing Control Register */
434 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
436 /* Set the watchdog timer in units of 40.96 usec */
437 reg &= ~IXGBE_DMACR_DMACWT_MASK;
438 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
440 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
441 /* If fcoe is enabled, set high priority traffic class */
442 if (hw->mac.dmac_config.fcoe_en) {
443 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
444 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
445 IXGBE_DMACR_HIGH_PRI_TC_MASK);
447 reg |= IXGBE_DMACR_EN_MNG_IND;
449 /* Enable DMA coalescing after configuration */
450 reg |= IXGBE_DMACR_DMAC_EN;
451 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
454 return IXGBE_SUCCESS;
458 * ixgbe_dmac_config_tcs_X550
459 * @hw: pointer to hardware structure
461 * Configure DMA coalescing threshold per TC. The dmac enable bit must
462 * be cleared before configuring.
464 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
466 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
468 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
470 /* Configure DMA coalescing enabled */
471 switch (hw->mac.dmac_config.link_speed) {
472 case IXGBE_LINK_SPEED_100_FULL:
473 pb_headroom = IXGBE_DMACRXT_100M;
475 case IXGBE_LINK_SPEED_1GB_FULL:
476 pb_headroom = IXGBE_DMACRXT_1G;
479 pb_headroom = IXGBE_DMACRXT_10G;
483 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
484 IXGBE_MHADD_MFS_SHIFT) / 1024);
486 /* Set the per Rx packet buffer receive threshold */
487 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
488 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
489 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
491 if (tc < hw->mac.dmac_config.num_tcs) {
493 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
494 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
495 IXGBE_RXPBSIZE_SHIFT;
497 /* Calculate receive buffer threshold in kilobytes */
498 if (rx_pb_size > pb_headroom)
499 rx_pb_size = rx_pb_size - pb_headroom;
503 /* Minimum of MFS shall be set for DMCTH */
504 reg |= (rx_pb_size > maxframe_size_kb) ?
505 rx_pb_size : maxframe_size_kb;
507 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
509 return IXGBE_SUCCESS;
513 * ixgbe_dmac_update_tcs_X550
514 * @hw: pointer to hardware structure
516 * Disables dmac, updates per TC settings, and then enables dmac.
518 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
522 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
524 /* Disable DMA coalescing before configuring */
525 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
526 reg &= ~IXGBE_DMACR_DMAC_EN;
527 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
529 ixgbe_dmac_config_tcs_X550(hw);
531 /* Enable DMA coalescing after configuration */
532 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
533 reg |= IXGBE_DMACR_DMAC_EN;
534 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
536 return IXGBE_SUCCESS;
540 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
541 * @hw: pointer to hardware structure
543 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
544 * ixgbe_hw struct in order to set up EEPROM access.
546 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
548 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
552 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
554 if (eeprom->type == ixgbe_eeprom_uninitialized) {
555 eeprom->semaphore_delay = 10;
556 eeprom->type = ixgbe_flash;
558 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
559 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
560 IXGBE_EEC_SIZE_SHIFT);
561 eeprom->word_size = 1 << (eeprom_size +
562 IXGBE_EEPROM_WORD_SIZE_SHIFT);
564 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
565 eeprom->type, eeprom->word_size);
568 return IXGBE_SUCCESS;
572 * ixgbe_setup_eee_X550 - Enable/disable EEE support
573 * @hw: pointer to the HW structure
574 * @enable_eee: boolean flag to enable EEE
576 * Enable/disable EEE based on enable_eee flag.
577 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
581 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
588 DEBUGFUNC("ixgbe_setup_eee_X550");
590 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
591 /* Enable or disable EEE per flag */
593 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
595 if (hw->device_id == IXGBE_DEV_ID_X550T) {
596 /* Advertise EEE capability */
597 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
598 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
600 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
601 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
602 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
604 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
605 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
606 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
607 status = ixgbe_read_iosf_sb_reg_x550(hw,
608 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
609 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
610 if (status != IXGBE_SUCCESS)
613 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
614 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
616 status = ixgbe_write_iosf_sb_reg_x550(hw,
617 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
618 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
619 if (status != IXGBE_SUCCESS)
623 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
625 if (hw->device_id == IXGBE_DEV_ID_X550T) {
626 /* Disable advertised EEE capability */
627 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
628 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
630 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
631 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
632 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
634 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
635 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
636 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
637 status = ixgbe_read_iosf_sb_reg_x550(hw,
638 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
639 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
640 if (status != IXGBE_SUCCESS)
643 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
644 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
646 status = ixgbe_write_iosf_sb_reg_x550(hw,
647 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
648 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
649 if (status != IXGBE_SUCCESS)
653 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
655 return IXGBE_SUCCESS;
659 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
660 * @hw: pointer to hardware structure
661 * @enable: enable or disable source address pruning
662 * @pool: Rx pool to set source address pruning for
664 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
669 /* max rx pool is 63 */
673 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
674 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
677 pfflp |= (1ULL << pool);
679 pfflp &= ~(1ULL << pool);
681 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
682 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
686 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
687 * @hw: pointer to hardware structure
688 * @enable: enable or disable switch for Ethertype anti-spoofing
689 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
692 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
695 int vf_target_reg = vf >> 3;
696 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
699 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
701 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
703 pfvfspoof |= (1 << vf_target_shift);
705 pfvfspoof &= ~(1 << vf_target_shift);
707 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
711 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
713 * @hw: pointer to hardware structure
714 * @reg_addr: 32 bit PHY register to write
715 * @device_type: 3 bit device type
716 * @data: Data to write to the register
718 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
719 u32 device_type, u32 data)
721 u32 i, command, error;
723 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
724 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
726 /* Write IOSF control register */
727 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
729 /* Write IOSF data register */
730 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
732 * Check every 10 usec to see if the address cycle completed.
733 * The SB IOSF BUSY bit will clear when the operation is
736 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
739 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
740 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
744 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
745 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
746 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
747 ERROR_REPORT2(IXGBE_ERROR_POLLING,
748 "Failed to write, error %x\n", error);
749 return IXGBE_ERR_PHY;
752 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
753 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
754 return IXGBE_ERR_PHY;
757 return IXGBE_SUCCESS;
761 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
763 * @hw: pointer to hardware structure
764 * @reg_addr: 32 bit PHY register to write
765 * @device_type: 3 bit device type
766 * @phy_data: Pointer to read data from the register
768 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
769 u32 device_type, u32 *data)
771 u32 i, command, error;
773 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
774 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
776 /* Write IOSF control register */
777 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
780 * Check every 10 usec to see if the address cycle completed.
781 * The SB IOSF BUSY bit will clear when the operation is
784 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
787 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
788 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
792 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
793 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
794 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
795 ERROR_REPORT2(IXGBE_ERROR_POLLING,
796 "Failed to read, error %x\n", error);
797 return IXGBE_ERR_PHY;
800 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
801 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
802 return IXGBE_ERR_PHY;
805 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
807 return IXGBE_SUCCESS;
811 * ixgbe_disable_mdd_X550
812 * @hw: pointer to hardware structure
814 * Disable malicious driver detection
816 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
820 DEBUGFUNC("ixgbe_disable_mdd_X550");
822 /* Disable MDD for TX DMA and interrupt */
823 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
824 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
825 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
827 /* Disable MDD for RX and interrupt */
828 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
829 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
830 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
834 * ixgbe_enable_mdd_X550
835 * @hw: pointer to hardware structure
837 * Enable malicious driver detection
839 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
843 DEBUGFUNC("ixgbe_enable_mdd_X550");
845 /* Enable MDD for TX DMA and interrupt */
846 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
847 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
848 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
850 /* Enable MDD for RX and interrupt */
851 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
852 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
853 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
857 * ixgbe_restore_mdd_vf_X550
858 * @hw: pointer to hardware structure
861 * Restore VF that was disabled during malicious driver detection event
863 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
865 u32 idx, reg, num_qs, start_q, bitmask;
867 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
869 /* Map VF to queues */
870 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
871 switch (reg & IXGBE_MRQC_MRQE_MASK) {
872 case IXGBE_MRQC_VMDQRT8TCEN:
873 num_qs = 8; /* 16 VFs / pools */
874 bitmask = 0x000000FF;
876 case IXGBE_MRQC_VMDQRSS32EN:
877 case IXGBE_MRQC_VMDQRT4TCEN:
878 num_qs = 4; /* 32 VFs / pools */
879 bitmask = 0x0000000F;
881 default: /* 64 VFs / pools */
883 bitmask = 0x00000003;
886 start_q = vf * num_qs;
888 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
891 reg |= (bitmask << (start_q % 32));
892 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
893 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
897 * ixgbe_mdd_event_X550
898 * @hw: pointer to hardware structure
899 * @vf_bitmap: vf bitmap of malicious vfs
901 * Handle malicious driver detection event.
903 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
906 u32 i, j, reg, q, shift, vf, idx;
908 DEBUGFUNC("ixgbe_mdd_event_X550");
910 /* figure out pool size for mapping to vf's */
911 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
912 switch (reg & IXGBE_MRQC_MRQE_MASK) {
913 case IXGBE_MRQC_VMDQRT8TCEN:
914 shift = 3; /* 16 VFs / pools */
916 case IXGBE_MRQC_VMDQRSS32EN:
917 case IXGBE_MRQC_VMDQRT4TCEN:
918 shift = 2; /* 32 VFs / pools */
921 shift = 1; /* 64 VFs / pools */
925 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
926 for (i = 0; i < 4; i++) {
927 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
928 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
933 /* Get malicious queue */
934 for (j = 0; j < 32 && wqbr; j++) {
936 if (!(wqbr & (1 << j)))
939 /* Get queue from bitmask */
942 /* Map queue to vf */
945 /* Set vf bit in vf_bitmap */
947 vf_bitmap[idx] |= (1 << (vf % 32));
954 * ixgbe_get_media_type_X550em - Get media type
955 * @hw: pointer to hardware structure
957 * Returns the media type (fiber, copper, backplane)
959 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
961 enum ixgbe_media_type media_type;
963 DEBUGFUNC("ixgbe_get_media_type_X550em");
965 /* Detect if there is a copper PHY attached. */
966 switch (hw->device_id) {
967 case IXGBE_DEV_ID_X550EM_X_KR:
968 case IXGBE_DEV_ID_X550EM_X_KX4:
969 media_type = ixgbe_media_type_backplane;
971 case IXGBE_DEV_ID_X550EM_X_SFP:
972 media_type = ixgbe_media_type_fiber;
974 case IXGBE_DEV_ID_X550EM_X_1G_T:
975 case IXGBE_DEV_ID_X550EM_X_10G_T:
976 media_type = ixgbe_media_type_copper;
979 media_type = ixgbe_media_type_unknown;
986 * ixgbe_setup_sfp_modules_X550em - Setup SFP module
987 * @hw: pointer to hardware structure
989 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
992 u16 reg_slice, edc_mode;
995 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
997 switch (hw->phy.sfp_type) {
998 case ixgbe_sfp_type_unknown:
999 return IXGBE_SUCCESS;
1000 case ixgbe_sfp_type_not_present:
1001 return IXGBE_ERR_SFP_NOT_PRESENT;
1002 case ixgbe_sfp_type_da_cu_core0:
1003 case ixgbe_sfp_type_da_cu_core1:
1004 setup_linear = true;
1006 case ixgbe_sfp_type_srlr_core0:
1007 case ixgbe_sfp_type_srlr_core1:
1008 case ixgbe_sfp_type_da_act_lmt_core0:
1009 case ixgbe_sfp_type_da_act_lmt_core1:
1010 case ixgbe_sfp_type_1g_sx_core0:
1011 case ixgbe_sfp_type_1g_sx_core1:
1012 case ixgbe_sfp_type_1g_lx_core0:
1013 case ixgbe_sfp_type_1g_lx_core1:
1014 setup_linear = false;
1017 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1020 ixgbe_init_mac_link_ops_X550em(hw);
1021 hw->phy.ops.reset = NULL;
1023 /* The CS4227 slice address is the base address + the port-pair reg
1024 * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
1026 reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12);
1029 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1031 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1033 /* Configure CS4227 for connection type. */
1034 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1037 if (ret_val != IXGBE_SUCCESS)
1038 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
1045 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1046 * @hw: pointer to hardware structure
1048 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1050 struct ixgbe_mac_info *mac = &hw->mac;
1052 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1054 /* CS4227 does not support autoneg, so disable the laser control
1055 * functions for SFP+ fiber
1057 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1058 mac->ops.disable_tx_laser = NULL;
1059 mac->ops.enable_tx_laser = NULL;
1060 mac->ops.flap_tx_laser = NULL;
1061 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1062 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1063 mac->ops.set_rate_select_speed =
1064 ixgbe_set_soft_rate_select_speed;
1069 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1070 * @hw: pointer to hardware structure
1071 * @speed: pointer to link speed
1072 * @autoneg: true when autoneg or autotry is enabled
1074 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1075 ixgbe_link_speed *speed,
1078 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1081 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1083 /* CS4227 SFP must not enable auto-negotiation */
1086 /* Check if 1G SFP module. */
1087 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1088 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1089 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1090 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1091 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1092 return IXGBE_SUCCESS;
1095 /* Link capabilities are based on SFP */
1096 if (hw->phy.multispeed_fiber)
1097 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1098 IXGBE_LINK_SPEED_1GB_FULL;
1100 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1102 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1103 IXGBE_LINK_SPEED_1GB_FULL;
1107 return IXGBE_SUCCESS;
1111 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1112 * @hw: pointer to hardware structure
1114 * Initialize any function pointers that were not able to be
1115 * set during init_shared_code because the PHY/SFP type was
1116 * not known. Perform the SFP init if necessary.
1118 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1120 struct ixgbe_phy_info *phy = &hw->phy;
1123 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1125 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1126 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1127 ixgbe_setup_mux_ctl(hw);
1130 /* Identify the PHY or SFP module */
1131 ret_val = phy->ops.identify(hw);
1132 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1135 /* Setup function pointers based on detected SFP module and speeds */
1136 ixgbe_init_mac_link_ops_X550em(hw);
1137 if (phy->sfp_type != ixgbe_sfp_type_unknown)
1138 phy->ops.reset = NULL;
1140 /* Set functions pointers based on phy type */
1141 switch (hw->phy.type) {
1142 case ixgbe_phy_x550em_kx4:
1143 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1144 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1145 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1147 case ixgbe_phy_x550em_kr:
1148 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1149 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1150 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1152 case ixgbe_phy_x550em_ext_t:
1153 phy->ops.setup_internal_link =
1154 ixgbe_setup_internal_phy_t_x550em;
1155 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1164 * ixgbe_reset_hw_X550em - Perform hardware reset
1165 * @hw: pointer to hardware structure
1167 * Resets the hardware by resetting the transmit and receive units, masks
1168 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1171 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1173 struct ixgbe_hic_hdr fw_cmd;
1174 ixgbe_link_speed link_speed;
1178 bool link_up = false;
1180 DEBUGFUNC("ixgbe_reset_hw_X550em");
1182 fw_cmd.cmd = FW_PHY_MGMT_REQ_CMD;
1184 fw_cmd.cmd_or_resp.cmd_resv = 0;
1185 fw_cmd.checksum = FW_DEFAULT_CHECKSUM;
1186 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
1188 IXGBE_HI_PHY_MGMT_REQ_TIMEOUT,
1191 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1192 "PHY mgmt command failed with %d\n", status);
1193 else if (fw_cmd.cmd_or_resp.ret_status != FW_CEM_RESP_STATUS_SUCCESS)
1194 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1195 "PHY mgmt command returned %d\n",
1196 fw_cmd.cmd_or_resp.ret_status);
1198 /* Call adapter stop to disable Tx/Rx and clear interrupts */
1199 status = hw->mac.ops.stop_adapter(hw);
1200 if (status != IXGBE_SUCCESS)
1203 /* flush pending Tx transactions */
1204 ixgbe_clear_tx_pending(hw);
1206 /* PHY ops must be identified and initialized prior to reset */
1208 /* Identify PHY and related function pointers */
1209 status = hw->phy.ops.init(hw);
1211 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1214 /* start the external PHY */
1215 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1216 status = ixgbe_init_ext_t_x550em(hw);
1221 /* Setup SFP module if there is one present. */
1222 if (hw->phy.sfp_setup_needed) {
1223 status = hw->mac.ops.setup_sfp(hw);
1224 hw->phy.sfp_setup_needed = false;
1227 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1231 if (!hw->phy.reset_disable && hw->phy.ops.reset)
1232 hw->phy.ops.reset(hw);
1235 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
1236 * If link reset is used when link is up, it might reset the PHY when
1237 * mng is using it. If link is down or the flag to force full link
1238 * reset is set, then perform link reset.
1240 ctrl = IXGBE_CTRL_LNK_RST;
1241 if (!hw->force_full_reset) {
1242 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1244 ctrl = IXGBE_CTRL_RST;
1247 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1248 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1249 IXGBE_WRITE_FLUSH(hw);
1251 /* Poll for reset bit to self-clear meaning reset is complete */
1252 for (i = 0; i < 10; i++) {
1254 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1255 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1259 if (ctrl & IXGBE_CTRL_RST_MASK) {
1260 status = IXGBE_ERR_RESET_FAILED;
1261 DEBUGOUT("Reset polling failed to complete.\n");
1266 /* Double resets are required for recovery from certain error
1267 * conditions. Between resets, it is necessary to stall to
1268 * allow time for any pending HW events to complete.
1270 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1271 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1275 /* Store the permanent mac address */
1276 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1278 /* Store MAC address from RAR0, clear receive address registers, and
1279 * clear the multicast table. Also reset num_rar_entries to 128,
1280 * since we modify this value when programming the SAN MAC address.
1282 hw->mac.num_rar_entries = 128;
1283 hw->mac.ops.init_rx_addrs(hw);
1286 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1287 ixgbe_setup_mux_ctl(hw);
1293 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1294 * @hw: pointer to hardware structure
1296 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1301 status = hw->phy.ops.read_reg(hw,
1302 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1303 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1306 if (status != IXGBE_SUCCESS)
1309 /* If PHY FW reset completed bit is set then this is the first
1310 * SW instance after a power on so the PHY FW must be un-stalled.
1312 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1313 status = hw->phy.ops.read_reg(hw,
1314 IXGBE_MDIO_GLOBAL_RES_PR_10,
1315 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1318 if (status != IXGBE_SUCCESS)
1321 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1323 status = hw->phy.ops.write_reg(hw,
1324 IXGBE_MDIO_GLOBAL_RES_PR_10,
1325 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1328 if (status != IXGBE_SUCCESS)
1336 * ixgbe_setup_kr_x550em - Configure the KR PHY.
1337 * @hw: pointer to hardware structure
1339 * Configures the integrated KR PHY.
1341 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1346 status = ixgbe_read_iosf_sb_reg_x550(hw,
1347 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1348 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1352 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1353 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1354 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1355 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1356 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1358 /* Advertise 10G support. */
1359 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1360 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1362 /* Advertise 1G support. */
1363 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1364 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1366 /* Restart auto-negotiation. */
1367 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1368 status = ixgbe_write_iosf_sb_reg_x550(hw,
1369 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1370 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1376 * ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1377 * @hw: pointer to hardware structure
1379 * Configures the integrated KX4 PHY.
1381 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1386 status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1387 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, ®_val);
1391 reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1392 IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1394 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1396 /* Advertise 10G support. */
1397 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1398 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1400 /* Advertise 1G support. */
1401 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1402 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1404 /* Restart auto-negotiation. */
1405 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1406 status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1407 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, reg_val);
1413 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1414 * @hw: pointer to hardware structure
1415 * @speed: the link speed to force
1417 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1418 * internal and external PHY at a specific speed, without autonegotiation.
1420 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1425 /* Disable AN and force speed to 10G Serial. */
1426 status = ixgbe_read_iosf_sb_reg_x550(hw,
1427 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1428 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1429 if (status != IXGBE_SUCCESS)
1432 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1433 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1435 /* Select forced link speed for internal PHY. */
1437 case IXGBE_LINK_SPEED_10GB_FULL:
1438 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1440 case IXGBE_LINK_SPEED_1GB_FULL:
1441 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1444 /* Other link speeds are not supported by internal KR PHY. */
1445 return IXGBE_ERR_LINK_SETUP;
1448 status = ixgbe_write_iosf_sb_reg_x550(hw,
1449 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1450 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1451 if (status != IXGBE_SUCCESS)
1454 /* Disable training protocol FSM. */
1455 status = ixgbe_read_iosf_sb_reg_x550(hw,
1456 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1457 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1458 if (status != IXGBE_SUCCESS)
1460 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1461 status = ixgbe_write_iosf_sb_reg_x550(hw,
1462 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1463 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1464 if (status != IXGBE_SUCCESS)
1467 /* Disable Flex from training TXFFE. */
1468 status = ixgbe_read_iosf_sb_reg_x550(hw,
1469 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1470 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1471 if (status != IXGBE_SUCCESS)
1473 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1474 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1475 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1476 status = ixgbe_write_iosf_sb_reg_x550(hw,
1477 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1478 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1479 if (status != IXGBE_SUCCESS)
1481 status = ixgbe_read_iosf_sb_reg_x550(hw,
1482 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1483 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1484 if (status != IXGBE_SUCCESS)
1486 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1487 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1488 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1489 status = ixgbe_write_iosf_sb_reg_x550(hw,
1490 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1491 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1492 if (status != IXGBE_SUCCESS)
1495 /* Enable override for coefficients. */
1496 status = ixgbe_read_iosf_sb_reg_x550(hw,
1497 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1498 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1499 if (status != IXGBE_SUCCESS)
1501 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1502 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1503 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1504 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1505 status = ixgbe_write_iosf_sb_reg_x550(hw,
1506 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1507 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1508 if (status != IXGBE_SUCCESS)
1511 /* Toggle port SW reset by AN reset. */
1512 status = ixgbe_read_iosf_sb_reg_x550(hw,
1513 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1514 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1515 if (status != IXGBE_SUCCESS)
1517 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1518 status = ixgbe_write_iosf_sb_reg_x550(hw,
1519 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1520 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1526 * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1527 * @hw: pointer to hardware structure
1529 * Configures the integrated KR PHY for SFP support.
1531 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1532 ixgbe_link_speed speed,
1533 bool autoneg_wait_to_complete)
1535 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1537 return ixgbe_setup_ixfi_x550em(hw, &speed);
1541 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1542 * @hw: point to hardware structure
1544 * Configures the link between the integrated KR PHY and the external X557 PHY
1545 * The driver will call this function when it gets a link status change
1546 * interrupt from the X557 PHY. This function configures the link speed
1547 * between the PHYs to match the link speed of the BASE-T link.
1549 * A return of a non-zero value indicates an error, and the base driver should
1550 * not report link up.
1552 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1555 u16 autoneg_status, speed;
1556 ixgbe_link_speed force_speed;
1558 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1559 return IXGBE_ERR_CONFIG;
1561 /* read this twice back to back to indicate current status */
1562 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1563 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1565 if (status != IXGBE_SUCCESS)
1568 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1569 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1571 if (status != IXGBE_SUCCESS)
1574 /* If link is not up, then there is no setup necessary so return */
1575 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1576 return IXGBE_SUCCESS;
1578 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1579 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1582 /* clear everything but the speed and duplex bits */
1583 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1586 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1587 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1589 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1590 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1593 /* Internal PHY does not support anything else */
1594 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1597 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1601 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1602 * @hw: pointer to hardware structure
1604 * Configures the integrated KR PHY to use internal loopback mode.
1606 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1611 /* Disable AN and force speed to 10G Serial. */
1612 status = ixgbe_read_iosf_sb_reg_x550(hw,
1613 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1614 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1615 if (status != IXGBE_SUCCESS)
1617 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1618 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1619 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1620 status = ixgbe_write_iosf_sb_reg_x550(hw,
1621 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1622 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1623 if (status != IXGBE_SUCCESS)
1626 /* Set near-end loopback clocks. */
1627 status = ixgbe_read_iosf_sb_reg_x550(hw,
1628 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1629 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1630 if (status != IXGBE_SUCCESS)
1632 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1633 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1634 status = ixgbe_write_iosf_sb_reg_x550(hw,
1635 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1636 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1637 if (status != IXGBE_SUCCESS)
1640 /* Set loopback enable. */
1641 status = ixgbe_read_iosf_sb_reg_x550(hw,
1642 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1643 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1644 if (status != IXGBE_SUCCESS)
1646 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1647 status = ixgbe_write_iosf_sb_reg_x550(hw,
1648 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1649 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1650 if (status != IXGBE_SUCCESS)
1653 /* Training bypass. */
1654 status = ixgbe_read_iosf_sb_reg_x550(hw,
1655 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1656 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1657 if (status != IXGBE_SUCCESS)
1659 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1660 status = ixgbe_write_iosf_sb_reg_x550(hw,
1661 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1662 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1668 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1669 * assuming that the semaphore is already obtained.
1670 * @hw: pointer to hardware structure
1671 * @offset: offset of word in the EEPROM to read
1672 * @data: word read from the EEPROM
1674 * Reads a 16 bit word from the EEPROM using the hostif.
1676 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1680 struct ixgbe_hic_read_shadow_ram buffer;
1682 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1683 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1684 buffer.hdr.req.buf_lenh = 0;
1685 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1686 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1688 /* convert offset from words to bytes */
1689 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1691 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1693 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1695 IXGBE_HI_COMMAND_TIMEOUT, false);
1700 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1701 FW_NVM_DATA_OFFSET);
1707 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1708 * @hw: pointer to hardware structure
1709 * @offset: offset of word in the EEPROM to read
1710 * @data: word read from the EEPROM
1712 * Reads a 16 bit word from the EEPROM using the hostif.
1714 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1717 s32 status = IXGBE_SUCCESS;
1719 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1721 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1723 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1724 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1726 status = IXGBE_ERR_SWFW_SYNC;
1733 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1734 * @hw: pointer to hardware structure
1735 * @offset: offset of word in the EEPROM to read
1736 * @words: number of words
1737 * @data: word(s) read from the EEPROM
1739 * Reads a 16 bit word(s) from the EEPROM using the hostif.
1741 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1742 u16 offset, u16 words, u16 *data)
1744 struct ixgbe_hic_read_shadow_ram buffer;
1745 u32 current_word = 0;
1750 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1752 /* Take semaphore for the entire operation. */
1753 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1755 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1759 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1760 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1762 words_to_read = words;
1764 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1765 buffer.hdr.req.buf_lenh = 0;
1766 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1767 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1769 /* convert offset from words to bytes */
1770 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1771 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1773 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1775 IXGBE_HI_COMMAND_TIMEOUT,
1779 DEBUGOUT("Host interface command failed\n");
1783 for (i = 0; i < words_to_read; i++) {
1784 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1786 u32 value = IXGBE_READ_REG(hw, reg);
1788 data[current_word] = (u16)(value & 0xffff);
1791 if (i < words_to_read) {
1793 data[current_word] = (u16)(value & 0xffff);
1797 words -= words_to_read;
1801 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1806 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1807 * @hw: pointer to hardware structure
1808 * @offset: offset of word in the EEPROM to write
1809 * @data: word write to the EEPROM
1811 * Write a 16 bit word to the EEPROM using the hostif.
1813 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1817 struct ixgbe_hic_write_shadow_ram buffer;
1819 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1821 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1822 buffer.hdr.req.buf_lenh = 0;
1823 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1824 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1827 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1829 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1831 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1833 IXGBE_HI_COMMAND_TIMEOUT, false);
1839 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1840 * @hw: pointer to hardware structure
1841 * @offset: offset of word in the EEPROM to write
1842 * @data: word write to the EEPROM
1844 * Write a 16 bit word to the EEPROM using the hostif.
1846 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1849 s32 status = IXGBE_SUCCESS;
1851 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
1853 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1855 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1856 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1858 DEBUGOUT("write ee hostif failed to get semaphore");
1859 status = IXGBE_ERR_SWFW_SYNC;
1866 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1867 * @hw: pointer to hardware structure
1868 * @offset: offset of word in the EEPROM to write
1869 * @words: number of words
1870 * @data: word(s) write to the EEPROM
1872 * Write a 16 bit word(s) to the EEPROM using the hostif.
1874 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1875 u16 offset, u16 words, u16 *data)
1877 s32 status = IXGBE_SUCCESS;
1880 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
1882 /* Take semaphore for the entire operation. */
1883 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1884 if (status != IXGBE_SUCCESS) {
1885 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
1889 for (i = 0; i < words; i++) {
1890 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1893 if (status != IXGBE_SUCCESS) {
1894 DEBUGOUT("Eeprom buffered write failed\n");
1899 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1906 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
1907 * @hw: pointer to hardware structure
1908 * @ptr: pointer offset in eeprom
1909 * @size: size of section pointed by ptr, if 0 first word will be used as size
1910 * @csum: address of checksum to update
1912 * Returns error status for any failure
1914 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
1915 u16 size, u16 *csum, u16 *buffer,
1920 u16 length, bufsz, i, start;
1923 bufsz = sizeof(buf) / sizeof(buf[0]);
1925 /* Read a chunk at the pointer location */
1927 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
1929 DEBUGOUT("Failed to read EEPROM image\n");
1934 if (buffer_size < ptr)
1935 return IXGBE_ERR_PARAM;
1936 local_buffer = &buffer[ptr];
1944 length = local_buffer[0];
1946 /* Skip pointer section if length is invalid. */
1947 if (length == 0xFFFF || length == 0 ||
1948 (ptr + length) >= hw->eeprom.word_size)
1949 return IXGBE_SUCCESS;
1952 if (buffer && ((u32)start + (u32)length > buffer_size))
1953 return IXGBE_ERR_PARAM;
1955 for (i = start; length; i++, length--) {
1956 if (i == bufsz && !buffer) {
1962 /* Read a chunk at the pointer location */
1963 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
1966 DEBUGOUT("Failed to read EEPROM image\n");
1970 *csum += local_buffer[i];
1972 return IXGBE_SUCCESS;
1976 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
1977 * @hw: pointer to hardware structure
1978 * @buffer: pointer to buffer containing calculated checksum
1979 * @buffer_size: size of buffer
1981 * Returns a negative error code on error, or the 16-bit checksum
1983 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
1985 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
1989 u16 pointer, i, size;
1991 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
1993 hw->eeprom.ops.init_params(hw);
1996 /* Read pointer area */
1997 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1998 IXGBE_EEPROM_LAST_WORD + 1,
2001 DEBUGOUT("Failed to read EEPROM image\n");
2004 local_buffer = eeprom_ptrs;
2006 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2007 return IXGBE_ERR_PARAM;
2008 local_buffer = buffer;
2012 * For X550 hardware include 0x0-0x41 in the checksum, skip the
2013 * checksum word itself
2015 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2016 if (i != IXGBE_EEPROM_CHECKSUM)
2017 checksum += local_buffer[i];
2020 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
2021 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2023 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2024 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2027 pointer = local_buffer[i];
2029 /* Skip pointer section if the pointer is invalid. */
2030 if (pointer == 0xFFFF || pointer == 0 ||
2031 pointer >= hw->eeprom.word_size)
2035 case IXGBE_PCIE_GENERAL_PTR:
2036 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2038 case IXGBE_PCIE_CONFIG0_PTR:
2039 case IXGBE_PCIE_CONFIG1_PTR:
2040 size = IXGBE_PCIE_CONFIG_SIZE;
2047 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2048 buffer, buffer_size);
2053 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2055 return (s32)checksum;
2059 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2060 * @hw: pointer to hardware structure
2062 * Returns a negative error code on error, or the 16-bit checksum
2064 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2066 return ixgbe_calc_checksum_X550(hw, NULL, 0);
2070 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2071 * @hw: pointer to hardware structure
2072 * @checksum_val: calculated checksum
2074 * Performs checksum calculation and validates the EEPROM checksum. If the
2075 * caller does not need checksum_val, the value can be NULL.
2077 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2081 u16 read_checksum = 0;
2083 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2085 /* Read the first word from the EEPROM. If this times out or fails, do
2086 * not continue or we could be in for a very long wait while every
2089 status = hw->eeprom.ops.read(hw, 0, &checksum);
2091 DEBUGOUT("EEPROM read failed\n");
2095 status = hw->eeprom.ops.calc_checksum(hw);
2099 checksum = (u16)(status & 0xffff);
2101 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2106 /* Verify read checksum from EEPROM is the same as
2107 * calculated checksum
2109 if (read_checksum != checksum) {
2110 status = IXGBE_ERR_EEPROM_CHECKSUM;
2111 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2112 "Invalid EEPROM checksum");
2115 /* If the user cares, return the calculated checksum */
2117 *checksum_val = checksum;
2123 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2124 * @hw: pointer to hardware structure
2126 * After writing EEPROM to shadow RAM using EEWR register, software calculates
2127 * checksum and updates the EEPROM and instructs the hardware to update
2130 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2135 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2137 /* Read the first word from the EEPROM. If this times out or fails, do
2138 * not continue or we could be in for a very long wait while every
2141 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2143 DEBUGOUT("EEPROM read failed\n");
2147 status = ixgbe_calc_eeprom_checksum_X550(hw);
2151 checksum = (u16)(status & 0xffff);
2153 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2158 status = ixgbe_update_flash_X550(hw);
2164 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2165 * @hw: pointer to hardware structure
2167 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2169 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2171 s32 status = IXGBE_SUCCESS;
2172 union ixgbe_hic_hdr2 buffer;
2174 DEBUGFUNC("ixgbe_update_flash_X550");
2176 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2177 buffer.req.buf_lenh = 0;
2178 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2179 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2181 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2183 IXGBE_HI_COMMAND_TIMEOUT, false);
2189 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2190 * @hw: pointer to hardware structure
2192 * Determines physical layer capabilities of the current configuration.
2194 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2196 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2197 u16 ext_ability = 0;
2199 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2201 hw->phy.ops.identify(hw);
2203 switch (hw->phy.type) {
2204 case ixgbe_phy_x550em_kr:
2205 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2206 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2208 case ixgbe_phy_x550em_kx4:
2209 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2210 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2212 case ixgbe_phy_x550em_ext_t:
2213 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2214 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2216 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2217 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2218 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2219 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2225 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2226 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2228 return physical_layer;
2232 * ixgbe_get_bus_info_x550em - Set PCI bus info
2233 * @hw: pointer to hardware structure
2235 * Sets bus link width and speed to unknown because X550em is
2238 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2241 DEBUGFUNC("ixgbe_get_bus_info_x550em");
2243 hw->bus.width = ixgbe_bus_width_unknown;
2244 hw->bus.speed = ixgbe_bus_speed_unknown;
2246 return IXGBE_SUCCESS;
2250 * ixgbe_disable_rx_x550 - Disable RX unit
2252 * Enables the Rx DMA unit for x550
2254 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2256 u32 rxctrl, pfdtxgswc;
2258 struct ixgbe_hic_disable_rxen fw_cmd;
2260 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2262 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2263 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2264 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2265 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2266 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2267 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2268 hw->mac.set_lben = true;
2270 hw->mac.set_lben = false;
2273 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2274 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2275 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2276 fw_cmd.port_number = (u8)hw->bus.lan_id;
2278 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2279 sizeof(struct ixgbe_hic_disable_rxen),
2280 IXGBE_HI_COMMAND_TIMEOUT, true);
2282 /* If we fail - disable RX using register write */
2284 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2285 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2286 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2287 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2294 * ixgbe_enter_lplu_x550em - Transition to low power states
2295 * @hw: pointer to hardware structure
2297 * Configures Low Power Link Up on transition to low power states
2298 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2299 * X557 PHY immediately prior to entering LPLU.
2301 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2303 u16 autoneg_status, an_10g_cntl_reg, autoneg_reg, speed;
2305 ixgbe_link_speed lcd_speed;
2307 /* If blocked by MNG FW, then don't restart AN */
2308 if (ixgbe_check_reset_blocked(hw))
2309 return IXGBE_SUCCESS;
2311 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2312 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2315 if (status != IXGBE_SUCCESS)
2318 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2320 if (status != IXGBE_SUCCESS)
2323 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2324 * disabled, then force link down by entering low power mode.
2326 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS) ||
2327 !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2328 !(hw->wol_enabled || ixgbe_mng_present(hw)))
2329 return ixgbe_set_copper_phy_power(hw, FALSE);
2332 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2334 if (status != IXGBE_SUCCESS)
2337 /* If no valid LCD link speed, then force link down and exit. */
2338 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2339 return ixgbe_set_copper_phy_power(hw, FALSE);
2341 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2342 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2345 if (status != IXGBE_SUCCESS)
2348 /* clear everything but the speed bits */
2349 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2351 /* If current speed is already LCD, then exit. */
2352 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2353 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2354 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2355 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2358 /* Clear AN completed indication */
2359 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2360 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2363 if (status != IXGBE_SUCCESS)
2366 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2367 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2370 if (status != IXGBE_SUCCESS)
2373 status = hw->phy.ops.read_reg(hw,
2374 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2375 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2378 if (status != IXGBE_SUCCESS)
2381 /* Set AN advertizement to only include LCD */
2382 if (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL) {
2383 an_10g_cntl_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
2384 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
2387 if (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL) {
2388 an_10g_cntl_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
2389 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
2392 status = hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2393 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2396 if (status != IXGBE_SUCCESS)
2399 status = hw->phy.ops.write_reg(hw,
2400 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2401 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2404 if (status != IXGBE_SUCCESS)
2407 /* Restart PHY auto-negotiation. */
2408 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
2409 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
2411 if (status != IXGBE_SUCCESS)
2414 autoneg_reg |= IXGBE_MII_RESTART;
2416 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
2417 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
2419 if (status != IXGBE_SUCCESS)
2422 status = ixgbe_setup_ixfi_x550em(hw, &lcd_speed);
2428 * ixgbe_get_lcd_x550em - Determine lowest common denominator
2429 * @hw: pointer to hardware structure
2430 * @lcd_speed: pointer to lowest common link speed
2432 * Determine lowest common link speed with link partner.
2434 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2438 u16 word = hw->eeprom.ctrl_word_3;
2440 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2442 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2443 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2446 if (status != IXGBE_SUCCESS)
2449 /* If link partner advertised 1G, return 1G */
2450 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2451 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2455 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2456 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2457 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2460 /* Link partner not capable of lower speeds, return 10G */
2461 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2466 * ixgbe_setup_fc_X550em - Set up flow control
2467 * @hw: pointer to hardware structure
2469 * Called at init time to set up flow control.
2471 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2473 s32 ret_val = IXGBE_SUCCESS;
2474 u32 pause, asm_dir, reg_val;
2476 DEBUGFUNC("ixgbe_setup_fc_X550em");
2478 /* Validate the requested mode */
2479 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2480 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2481 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2482 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2486 /* 10gig parts do not have a word in the EEPROM to determine the
2487 * default flow control setting, so we explicitly set it to full.
2489 if (hw->fc.requested_mode == ixgbe_fc_default)
2490 hw->fc.requested_mode = ixgbe_fc_full;
2492 /* Determine PAUSE and ASM_DIR bits. */
2493 switch (hw->fc.requested_mode) {
2498 case ixgbe_fc_tx_pause:
2502 case ixgbe_fc_rx_pause:
2503 /* Rx Flow control is enabled and Tx Flow control is
2504 * disabled by software override. Since there really
2505 * isn't a way to advertise that we are capable of RX
2506 * Pause ONLY, we will advertise that we support both
2507 * symmetric and asymmetric Rx PAUSE, as such we fall
2508 * through to the fc_full statement. Later, we will
2509 * disable the adapter's ability to send PAUSE frames.
2516 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2517 "Flow control param set incorrectly\n");
2518 ret_val = IXGBE_ERR_CONFIG;
2522 if (hw->phy.media_type == ixgbe_media_type_backplane) {
2523 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2524 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2525 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2526 if (ret_val != IXGBE_SUCCESS)
2528 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2529 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2531 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2533 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2534 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2535 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2536 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2538 /* Not all devices fully support AN. */
2539 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR)
2540 hw->fc.disable_fc_autoneg = true;
2548 * ixgbe_set_mux - Set mux for port 1 access with CS4227
2549 * @hw: pointer to hardware structure
2550 * @state: set mux if 1, clear if 0
2552 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2556 if (!hw->bus.lan_id)
2558 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2560 esdp |= IXGBE_ESDP_SDP1;
2562 esdp &= ~IXGBE_ESDP_SDP1;
2563 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2564 IXGBE_WRITE_FLUSH(hw);
2568 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2569 * @hw: pointer to hardware structure
2570 * @mask: Mask to specify which semaphore to acquire
2572 * Acquires the SWFW semaphore and sets the I2C MUX
2574 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2578 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2580 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2584 if (mask & IXGBE_GSSR_I2C_MASK)
2585 ixgbe_set_mux(hw, 1);
2587 return IXGBE_SUCCESS;
2591 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2592 * @hw: pointer to hardware structure
2593 * @mask: Mask to specify which semaphore to release
2595 * Releases the SWFW semaphore and sets the I2C MUX
2597 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2599 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2601 if (mask & IXGBE_GSSR_I2C_MASK)
2602 ixgbe_set_mux(hw, 0);
2604 ixgbe_release_swfw_sync_X540(hw, mask);