drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41
  42 /**
  43  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  44  *  @hw: pointer to hardware structure
  45  *
  46  *  Initialize the function pointers and assign the MAC type for X550.
  47  *  Does not touch the hardware.
  48  **/
  49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  50 {
  51         struct ixgbe_mac_info *mac = &hw->mac;
  52         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  53         s32 ret_val;
  54
  55         DEBUGFUNC("ixgbe_init_ops_X550");
  56
  57         ret_val = ixgbe_init_ops_X540(hw);
  58         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  59         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  60         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  61         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  62         mac->ops.set_source_address_pruning =
  63                         ixgbe_set_source_address_pruning_X550;
  64         mac->ops.set_ethertype_anti_spoofing =
  65                         ixgbe_set_ethertype_anti_spoofing_X550;
  66
  67         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  68         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  69         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  70         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  71         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  72         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  73         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  74         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  75         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  76
  77         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  78         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  79         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  80         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  81         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  82         return ret_val;
  83 }
  84
  85 /**
  86  * ixgbe_read_cs4227 - Read CS4227 register
  87  * @hw: pointer to hardware structure
  88  * @reg: register number to write
  89  * @value: pointer to receive value read
  90  *
  91  * Returns status code
  92  **/
  93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  94 {
  95         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
  96 }
  97
  98 /**
  99  * ixgbe_write_cs4227 - Write CS4227 register
 100  * @hw: pointer to hardware structure
 101  * @reg: register number to write
 102  * @value: value to write to register
 103  *
 104  * Returns status code
 105  **/
 106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 107 {
 108         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 109 }
 110
 111 /**
 112  * ixgbe_get_cs4227_status - Return CS4227 status
 113  * @hw: pointer to hardware structure
 114  *
 115  * Returns error if CS4227 not successfully initialized
 116  **/
 117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
 118 {
 119         s32 status;
 120         u16 value = 0;
 121         u16 reg_slice, reg_val;
 122         u8 retry;
 123
 124         for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
 125                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
 126                                            &value);
 127                 if (status != IXGBE_SUCCESS)
 128                         return status;
 129                 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
 130                         break;
 131                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 132         }
 133         if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
 134                 return IXGBE_ERR_PHY;
 135
 136         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 137         if (status != IXGBE_SUCCESS)
 138                 return status;
 139
 140         /* If this is the first time after power-on, check the ucode.
 141          * Otherwise, this will disrupt link on all ports. Because we
 142          * can only do this the first time, we must check all ports,
 143          * not just our own.
 144          */
 145         if (value != IXGBE_CS4227_SCRATCH_VALUE) {
 146                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB;
 147                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
 148                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 149                 if (status != IXGBE_SUCCESS)
 150                         return status;
 151
 152                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB;
 153                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
 154                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 155                 if (status != IXGBE_SUCCESS)
 156                         return status;
 157
 158                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12);
 159                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
 160                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 161                 if (status != IXGBE_SUCCESS)
 162                         return status;
 163
 164                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12);
 165                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
 166                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 167                 if (status != IXGBE_SUCCESS)
 168                         return status;
 169
 170                 msec_delay(10);
 171         }
 172
 173         /* Verify that the ucode is operational on all ports. */
 174         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB;
 175         reg_val = 0xFFFF;
 176         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 177         if (status != IXGBE_SUCCESS)
 178                 return status;
 179         if (reg_val != 0)
 180                 return IXGBE_ERR_PHY;
 181
 182         reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB;
 183         reg_val = 0xFFFF;
 184         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 185         if (status != IXGBE_SUCCESS)
 186                 return status;
 187         if (reg_val != 0)
 188                 return IXGBE_ERR_PHY;
 189
 190         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12);
 191         reg_val = 0xFFFF;
 192         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 193         if (status != IXGBE_SUCCESS)
 194                 return status;
 195         if (reg_val != 0)
 196                 return IXGBE_ERR_PHY;
 197
 198         reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12);
 199         reg_val = 0xFFFF;
 200         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 201         if (status != IXGBE_SUCCESS)
 202                 return status;
 203         if (reg_val != 0)
 204                 return IXGBE_ERR_PHY;
 205
 206         /* Set scratch indicating that the diagnostic was successful. */
 207         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 208                                     IXGBE_CS4227_SCRATCH_VALUE);
 209         if (status != IXGBE_SUCCESS)
 210                 return status;
 211         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 212         if (status != IXGBE_SUCCESS)
 213                 return status;
 214         if (value != IXGBE_CS4227_SCRATCH_VALUE)
 215                 return IXGBE_ERR_PHY;
 216
 217         return IXGBE_SUCCESS;
 218 }
 219
 220 /**
 221  * ixgbe_read_pe - Read register from port expander
 222  * @hw: pointer to hardware structure
 223  * @reg: register number to read
 224  * @value: pointer to receive read value
 225  *
 226  * Returns status code
 227  **/
 228 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 229 {
 230         s32 status;
 231
 232         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 233         if (status != IXGBE_SUCCESS)
 234                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 235                               "port expander access failed with %d\n", status);
 236         return status;
 237 }
 238
 239 /**
 240  * ixgbe_write_pe - Write register to port expander
 241  * @hw: pointer to hardware structure
 242  * @reg: register number to write
 243  * @value: value to write
 244  *
 245  * Returns status code
 246  **/
 247 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 248 {
 249         s32 status;
 250
 251         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 252         if (status != IXGBE_SUCCESS)
 253                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 254                               "port expander access failed with %d\n", status);
 255         return status;
 256 }
 257
 258 /**
 259  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 260  * @hw: pointer to hardware structure
 261  *
 262  * Returns error code
 263  **/
 264 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 265 {
 266         s32 status;
 267         u8 reg;
 268
 269         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 270         if (status != IXGBE_SUCCESS)
 271                 return status;
 272         reg |= IXGBE_PE_BIT1;
 273         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 274         if (status != IXGBE_SUCCESS)
 275                 return status;
 276
 277         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 278         if (status != IXGBE_SUCCESS)
 279                 return status;
 280         reg &= ~IXGBE_PE_BIT1;
 281         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 282         if (status != IXGBE_SUCCESS)
 283                 return status;
 284
 285         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 286         if (status != IXGBE_SUCCESS)
 287                 return status;
 288         reg &= ~IXGBE_PE_BIT1;
 289         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 290         if (status != IXGBE_SUCCESS)
 291                 return status;
 292
 293         usec_delay(IXGBE_CS4227_RESET_HOLD);
 294
 295         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 296         if (status != IXGBE_SUCCESS)
 297                 return status;
 298         reg |= IXGBE_PE_BIT1;
 299         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 300         if (status != IXGBE_SUCCESS)
 301                 return status;
 302
 303         msec_delay(IXGBE_CS4227_RESET_DELAY);
 304
 305         return IXGBE_SUCCESS;
 306 }
 307
 308 /**
 309  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 310  * @hw: pointer to hardware structure
 311  **/
 312 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 313 {
 314         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 315         s32 status;
 316         u8 retry;
 317
 318         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 319                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 320                 if (status != IXGBE_SUCCESS) {
 321                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 322                                       "semaphore failed with %d\n", status);
 323                         return;
 324                 }
 325                 status = ixgbe_get_cs4227_status(hw);
 326                 if (status == IXGBE_SUCCESS) {
 327                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 328                         msec_delay(hw->eeprom.semaphore_delay);
 329                         return;
 330                 }
 331                 ixgbe_reset_cs4227(hw);
 332                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 333                 msec_delay(hw->eeprom.semaphore_delay);
 334         }
 335         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 336                       "Unable to initialize CS4227, err=%d\n", status);
 337 }
 338
 339 /**
 340  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 341  * @hw: pointer to hardware structure
 342  **/
 343 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 344 {
 345         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 346
 347         if (hw->bus.lan_id) {
 348                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 349                 esdp |= IXGBE_ESDP_SDP1_DIR;
 350         }
 351         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 352         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 353         IXGBE_WRITE_FLUSH(hw);
 354 }
 355
 356 /**
 357  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 358  * @hw: pointer to hardware structure
 359  *
 360  * Returns error code
 361  */
 362 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 363 {
 364         switch (hw->device_id) {
 365         case IXGBE_DEV_ID_X550EM_X_SFP:
 366                 /* set up for CS4227 usage */
 367                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 368                 ixgbe_setup_mux_ctl(hw);
 369                 ixgbe_check_cs4227(hw);
 370
 371                 return ixgbe_identify_module_generic(hw);
 372                 break;
 373         case IXGBE_DEV_ID_X550EM_X_KX4:
 374                 hw->phy.type = ixgbe_phy_x550em_kx4;
 375                 break;
 376         case IXGBE_DEV_ID_X550EM_X_KR:
 377                 hw->phy.type = ixgbe_phy_x550em_kr;
 378                 break;
 379         case IXGBE_DEV_ID_X550EM_X_1G_T:
 380         case IXGBE_DEV_ID_X550EM_X_10G_T:
 381                 return ixgbe_identify_phy_generic(hw);
 382         default:
 383                 break;
 384         }
 385         return IXGBE_SUCCESS;
 386 }
 387
 388 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 389                                      u32 device_type, u16 *phy_data)
 390 {
 391         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 392         return IXGBE_NOT_IMPLEMENTED;
 393 }
 394
 395 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 396                                       u32 device_type, u16 phy_data)
 397 {
 398         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 399         return IXGBE_NOT_IMPLEMENTED;
 400 }
 401
 402 /**
 403 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 404 *  @hw: pointer to hardware structure
 405 *
 406 *  Initialize the function pointers and for MAC type X550EM.
 407 *  Does not touch the hardware.
 408 **/
 409 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 410 {
 411         struct ixgbe_mac_info *mac = &hw->mac;
 412         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 413         struct ixgbe_phy_info *phy = &hw->phy;
 414         s32 ret_val;
 415
 416         DEBUGFUNC("ixgbe_init_ops_X550EM");
 417
 418         /* Similar to X550 so start there. */
 419         ret_val = ixgbe_init_ops_X550(hw);
 420
 421         /* Since this function eventually calls
 422          * ixgbe_init_ops_540 by design, we are setting
 423          * the pointers to NULL explicitly here to overwrite
 424          * the values being set in the x540 function.
 425          */
 426         /* Thermal sensor not supported in x550EM */
 427         mac->ops.get_thermal_sensor_data = NULL;
 428         mac->ops.init_thermal_sensor_thresh = NULL;
 429         mac->thermal_sensor_enabled = false;
 430
 431         /* FCOE not supported in x550EM */
 432         mac->ops.get_san_mac_addr = NULL;
 433         mac->ops.set_san_mac_addr = NULL;
 434         mac->ops.get_wwn_prefix = NULL;
 435         mac->ops.get_fcoe_boot_status = NULL;
 436
 437         /* IPsec not supported in x550EM */
 438         mac->ops.disable_sec_rx_path = NULL;
 439         mac->ops.enable_sec_rx_path = NULL;
 440
 441         /* AUTOC register is not present in x550EM. */
 442         mac->ops.prot_autoc_read = NULL;
 443         mac->ops.prot_autoc_write = NULL;
 444
 445         /* X550EM bus type is internal*/
 446         hw->bus.type = ixgbe_bus_type_internal;
 447         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 448
 449         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 450         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 451         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 452         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 453         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 454         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 455         mac->ops.get_supported_physical_layer =
 456                                     ixgbe_get_supported_physical_layer_X550em;
 457
 458         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 459                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 460         else
 461                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 462
 463         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 464         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 465
 466         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
 467                 mac->ops.setup_eee = NULL;
 468
 469         /* PHY */
 470         phy->ops.init = ixgbe_init_phy_ops_X550em;
 471         phy->ops.identify = ixgbe_identify_phy_x550em;
 472         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 473                 phy->ops.set_phy_power = NULL;
 474
 475
 476         /* EEPROM */
 477         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 478         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 479         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 480         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 481         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 482         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 483         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 484         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 485
 486         return ret_val;
 487 }
 488
 489 /**
 490  *  ixgbe_dmac_config_X550
 491  *  @hw: pointer to hardware structure
 492  *
 493  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 494  *  When disabling dmac, dmac enable dmac bit is cleared.
 495  **/
 496 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 497 {
 498         u32 reg, high_pri_tc;
 499
 500         DEBUGFUNC("ixgbe_dmac_config_X550");
 501
 502         /* Disable DMA coalescing before configuring */
 503         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 504         reg &= ~IXGBE_DMACR_DMAC_EN;
 505         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 506
 507         /* Disable DMA Coalescing if the watchdog timer is 0 */
 508         if (!hw->mac.dmac_config.watchdog_timer)
 509                 goto out;
 510
 511         ixgbe_dmac_config_tcs_X550(hw);
 512
 513         /* Configure DMA Coalescing Control Register */
 514         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 515
 516         /* Set the watchdog timer in units of 40.96 usec */
 517         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 518         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 519
 520         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 521         /* If fcoe is enabled, set high priority traffic class */
 522         if (hw->mac.dmac_config.fcoe_en) {
 523                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 524                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 525                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 526         }
 527         reg |= IXGBE_DMACR_EN_MNG_IND;
 528
 529         /* Enable DMA coalescing after configuration */
 530         reg |= IXGBE_DMACR_DMAC_EN;
 531         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 532
 533 out:
 534         return IXGBE_SUCCESS;
 535 }
 536
 537 /**
 538  *  ixgbe_dmac_config_tcs_X550
 539  *  @hw: pointer to hardware structure
 540  *
 541  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 542  *  be cleared before configuring.
 543  **/
 544 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 545 {
 546         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 547
 548         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 549
 550         /* Configure DMA coalescing enabled */
 551         switch (hw->mac.dmac_config.link_speed) {
 552         case IXGBE_LINK_SPEED_100_FULL:
 553                 pb_headroom = IXGBE_DMACRXT_100M;
 554                 break;
 555         case IXGBE_LINK_SPEED_1GB_FULL:
 556                 pb_headroom = IXGBE_DMACRXT_1G;
 557                 break;
 558         default:
 559                 pb_headroom = IXGBE_DMACRXT_10G;
 560                 break;
 561         }
 562
 563         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 564                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 565
 566         /* Set the per Rx packet buffer receive threshold */
 567         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 568                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 569                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 570
 571                 if (tc < hw->mac.dmac_config.num_tcs) {
 572                         /* Get Rx PB size */
 573                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 574                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 575                                 IXGBE_RXPBSIZE_SHIFT;
 576
 577                         /* Calculate receive buffer threshold in kilobytes */
 578                         if (rx_pb_size > pb_headroom)
 579                                 rx_pb_size = rx_pb_size - pb_headroom;
 580                         else
 581                                 rx_pb_size = 0;
 582
 583                         /* Minimum of MFS shall be set for DMCTH */
 584                         reg |= (rx_pb_size > maxframe_size_kb) ?
 585                                 rx_pb_size : maxframe_size_kb;
 586                 }
 587                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 588         }
 589         return IXGBE_SUCCESS;
 590 }
 591
 592 /**
 593  *  ixgbe_dmac_update_tcs_X550
 594  *  @hw: pointer to hardware structure
 595  *
 596  *  Disables dmac, updates per TC settings, and then enables dmac.
 597  **/
 598 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 599 {
 600         u32 reg;
 601
 602         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 603
 604         /* Disable DMA coalescing before configuring */
 605         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 606         reg &= ~IXGBE_DMACR_DMAC_EN;
 607         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 608
 609         ixgbe_dmac_config_tcs_X550(hw);
 610
 611         /* Enable DMA coalescing after configuration */
 612         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 613         reg |= IXGBE_DMACR_DMAC_EN;
 614         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 615
 616         return IXGBE_SUCCESS;
 617 }
 618
 619 /**
 620  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 621  *  @hw: pointer to hardware structure
 622  *
 623  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 624  *  ixgbe_hw struct in order to set up EEPROM access.
 625  **/
 626 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 627 {
 628         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 629         u32 eec;
 630         u16 eeprom_size;
 631
 632         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 633
 634         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 635                 eeprom->semaphore_delay = 10;
 636                 eeprom->type = ixgbe_flash;
 637
 638                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 639                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 640                                     IXGBE_EEC_SIZE_SHIFT);
 641                 eeprom->word_size = 1 << (eeprom_size +
 642                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 643
 644                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 645                           eeprom->type, eeprom->word_size);
 646         }
 647
 648         return IXGBE_SUCCESS;
 649 }
 650
 651 /**
 652  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 653  *  @hw: pointer to the HW structure
 654  *  @enable_eee: boolean flag to enable EEE
 655  *
 656  *  Enable/disable EEE based on enable_eee flag.
 657  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 658  *  are modified.
 659  *
 660  **/
 661 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 662 {
 663         u32 eeer;
 664         u16 autoneg_eee_reg;
 665         u32 link_reg;
 666         s32 status;
 667
 668         DEBUGFUNC("ixgbe_setup_eee_X550");
 669
 670         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 671         /* Enable or disable EEE per flag */
 672         if (enable_eee) {
 673                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 674
 675                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 676                         /* Advertise EEE capability */
 677                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 678                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 679
 680                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 681                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 682                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 683
 684                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 685                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 686                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 687                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 688                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 689                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 690                         if (status != IXGBE_SUCCESS)
 691                                 return status;
 692
 693                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 694                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 695
 696                         /* Must disable FEC when EEE is enabled. */
 697                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
 698                                 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
 699
 700                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 701                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 702                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 703                         if (status != IXGBE_SUCCESS)
 704                                 return status;
 705                 }
 706         } else {
 707                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 708
 709                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 710                         /* Disable advertised EEE capability */
 711                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 712                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 713
 714                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 715                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 716                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 717
 718                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 719                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 720                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 721                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 722                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 723                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 724                         if (status != IXGBE_SUCCESS)
 725                                 return status;
 726
 727                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 728                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 729
 730                         /* Enable FEC when EEE is disabled. */
 731                         link_reg |= (IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
 732                                 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
 733
 734                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 735                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 736                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 737                         if (status != IXGBE_SUCCESS)
 738                                 return status;
 739                 }
 740         }
 741         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 742
 743         return IXGBE_SUCCESS;
 744 }
 745
 746 /**
 747  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 748  * @hw: pointer to hardware structure
 749  * @enable: enable or disable source address pruning
 750  * @pool: Rx pool to set source address pruning for
 751  **/
 752 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 753                                            unsigned int pool)
 754 {
 755         u64 pfflp;
 756
 757         /* max rx pool is 63 */
 758         if (pool > 63)
 759                 return;
 760
 761         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 762         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 763
 764         if (enable)
 765                 pfflp |= (1ULL << pool);
 766         else
 767                 pfflp &= ~(1ULL << pool);
 768
 769         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 770         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 771 }
 772
 773 /**
 774  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 775  *  @hw: pointer to hardware structure
 776  *  @enable: enable or disable switch for Ethertype anti-spoofing
 777  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 778  *
 779  **/
 780 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 781                 bool enable, int vf)
 782 {
 783         int vf_target_reg = vf >> 3;
 784         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 785         u32 pfvfspoof;
 786
 787         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 788
 789         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 790         if (enable)
 791                 pfvfspoof |= (1 << vf_target_shift);
 792         else
 793                 pfvfspoof &= ~(1 << vf_target_shift);
 794
 795         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 796 }
 797
 798 /**
 799  * ixgbe_iosf_wait - Wait for IOSF command completion
 800  * @hw: pointer to hardware structure
 801  * @ctrl: pointer to location to receive final IOSF control value
 802  *
 803  * Returns failing status on timeout
 804  *
 805  * Note: ctrl can be NULL if the IOSF control register value is not needed
 806  **/
 807 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 808 {
 809         u32 i, command = 0;
 810
 811         /* Check every 10 usec to see if the address cycle completed.
 812          * The SB IOSF BUSY bit will clear when the operation is
 813          * complete
 814          */
 815         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 816                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 817                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 818                         break;
 819                 usec_delay(10);
 820         }
 821         if (ctrl)
 822                 *ctrl = command;
 823         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 824                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
 825                 return IXGBE_ERR_PHY;
 826         }
 827
 828         return IXGBE_SUCCESS;
 829 }
 830
 831 /**
 832  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 833  *  device
 834  *  @hw: pointer to hardware structure
 835  *  @reg_addr: 32 bit PHY register to write
 836  *  @device_type: 3 bit device type
 837  *  @data: Data to write to the register
 838  **/
 839 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 840                             u32 device_type, u32 data)
 841 {
 842         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 843         u32 command, error;
 844         s32 ret;
 845
 846         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 847         if (ret != IXGBE_SUCCESS)
 848                 return ret;
 849
 850         ret = ixgbe_iosf_wait(hw, NULL);
 851         if (ret != IXGBE_SUCCESS)
 852                 goto out;
 853
 854         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 855                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 856
 857         /* Write IOSF control register */
 858         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 859
 860         /* Write IOSF data register */
 861         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 862
 863         ret = ixgbe_iosf_wait(hw, &command);
 864
 865         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 866                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 867                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 868                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 869                               "Failed to write, error %x\n", error);
 870                 ret = IXGBE_ERR_PHY;
 871         }
 872
 873 out:
 874         ixgbe_release_swfw_semaphore(hw, gssr);
 875         return ret;
 876 }
 877
 878 /**
 879  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 880  *  device
 881  *  @hw: pointer to hardware structure
 882  *  @reg_addr: 32 bit PHY register to write
 883  *  @device_type: 3 bit device type
 884  *  @phy_data: Pointer to read data from the register
 885  **/
 886 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 887                            u32 device_type, u32 *data)
 888 {
 889         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 890         u32 command, error;
 891         s32 ret;
 892
 893         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 894         if (ret != IXGBE_SUCCESS)
 895                 return ret;
 896
 897         ret = ixgbe_iosf_wait(hw, NULL);
 898         if (ret != IXGBE_SUCCESS)
 899                 goto out;
 900
 901         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 902                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 903
 904         /* Write IOSF control register */
 905         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 906
 907         ret = ixgbe_iosf_wait(hw, &command);
 908
 909         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 910                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 911                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 912                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 913                                 "Failed to read, error %x\n", error);
 914                 ret = IXGBE_ERR_PHY;
 915         }
 916
 917         if (ret == IXGBE_SUCCESS)
 918                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 919
 920 out:
 921         ixgbe_release_swfw_semaphore(hw, gssr);
 922         return ret;
 923 }
 924
 925 /**
 926  *  ixgbe_disable_mdd_X550
 927  *  @hw: pointer to hardware structure
 928  *
 929  *  Disable malicious driver detection
 930  **/
 931 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 932 {
 933         u32 reg;
 934
 935         DEBUGFUNC("ixgbe_disable_mdd_X550");
 936
 937         /* Disable MDD for TX DMA and interrupt */
 938         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 939         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 940         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 941
 942         /* Disable MDD for RX and interrupt */
 943         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 944         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 945         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 946 }
 947
 948 /**
 949  *  ixgbe_enable_mdd_X550
 950  *  @hw: pointer to hardware structure
 951  *
 952  *  Enable malicious driver detection
 953  **/
 954 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 955 {
 956         u32 reg;
 957
 958         DEBUGFUNC("ixgbe_enable_mdd_X550");
 959
 960         /* Enable MDD for TX DMA and interrupt */
 961         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 962         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 963         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 964
 965         /* Enable MDD for RX and interrupt */
 966         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 967         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 968         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 969 }
 970
 971 /**
 972  *  ixgbe_restore_mdd_vf_X550
 973  *  @hw: pointer to hardware structure
 974  *  @vf: vf index
 975  *
 976  *  Restore VF that was disabled during malicious driver detection event
 977  **/
 978 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 979 {
 980         u32 idx, reg, num_qs, start_q, bitmask;
 981
 982         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 983
 984         /* Map VF to queues */
 985         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 986         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 987         case IXGBE_MRQC_VMDQRT8TCEN:
 988                 num_qs = 8;  /* 16 VFs / pools */
 989                 bitmask = 0x000000FF;
 990                 break;
 991         case IXGBE_MRQC_VMDQRSS32EN:
 992         case IXGBE_MRQC_VMDQRT4TCEN:
 993                 num_qs = 4;  /* 32 VFs / pools */
 994                 bitmask = 0x0000000F;
 995                 break;
 996         default:            /* 64 VFs / pools */
 997                 num_qs = 2;
 998                 bitmask = 0x00000003;
 999                 break;
1000         }
1001         start_q = vf * num_qs;
1002
1003         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1004         idx = start_q / 32;
1005         reg = 0;
1006         reg |= (bitmask << (start_q % 32));
1007         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1008         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1009 }
1010
1011 /**
1012  *  ixgbe_mdd_event_X550
1013  *  @hw: pointer to hardware structure
1014  *  @vf_bitmap: vf bitmap of malicious vfs
1015  *
1016  *  Handle malicious driver detection event.
1017  **/
1018 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1019 {
1020         u32 wqbr;
1021         u32 i, j, reg, q, shift, vf, idx;
1022
1023         DEBUGFUNC("ixgbe_mdd_event_X550");
1024
1025         /* figure out pool size for mapping to vf's */
1026         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1027         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1028         case IXGBE_MRQC_VMDQRT8TCEN:
1029                 shift = 3;  /* 16 VFs / pools */
1030                 break;
1031         case IXGBE_MRQC_VMDQRSS32EN:
1032         case IXGBE_MRQC_VMDQRT4TCEN:
1033                 shift = 2;  /* 32 VFs / pools */
1034                 break;
1035         default:
1036                 shift = 1;  /* 64 VFs / pools */
1037                 break;
1038         }
1039
1040         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1041         for (i = 0; i < 4; i++) {
1042                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1043                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1044
1045                 if (!wqbr)
1046                         continue;
1047
1048                 /* Get malicious queue */
1049                 for (j = 0; j < 32 && wqbr; j++) {
1050
1051                         if (!(wqbr & (1 << j)))
1052                                 continue;
1053
1054                         /* Get queue from bitmask */
1055                         q = j + (i * 32);
1056
1057                         /* Map queue to vf */
1058                         vf = (q >> shift);
1059
1060                         /* Set vf bit in vf_bitmap */
1061                         idx = vf / 32;
1062                         vf_bitmap[idx] |= (1 << (vf % 32));
1063                         wqbr &= ~(1 << j);
1064                 }
1065         }
1066 }
1067
1068 /**
1069  *  ixgbe_get_media_type_X550em - Get media type
1070  *  @hw: pointer to hardware structure
1071  *
1072  *  Returns the media type (fiber, copper, backplane)
1073  */
1074 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1075 {
1076         enum ixgbe_media_type media_type;
1077
1078         DEBUGFUNC("ixgbe_get_media_type_X550em");
1079
1080         /* Detect if there is a copper PHY attached. */
1081         switch (hw->device_id) {
1082         case IXGBE_DEV_ID_X550EM_X_KR:
1083         case IXGBE_DEV_ID_X550EM_X_KX4:
1084                 media_type = ixgbe_media_type_backplane;
1085                 break;
1086         case IXGBE_DEV_ID_X550EM_X_SFP:
1087                 media_type = ixgbe_media_type_fiber;
1088                 break;
1089         case IXGBE_DEV_ID_X550EM_X_1G_T:
1090         case IXGBE_DEV_ID_X550EM_X_10G_T:
1091                 media_type = ixgbe_media_type_copper;
1092                 break;
1093         default:
1094                 media_type = ixgbe_media_type_unknown;
1095                 break;
1096         }
1097         return media_type;
1098 }
1099
1100 /**
1101  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1102  *  @hw: pointer to hardware structure
1103  *  @linear: true if SFP module is linear
1104  */
1105 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1106 {
1107         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1108
1109         switch (hw->phy.sfp_type) {
1110         case ixgbe_sfp_type_not_present:
1111                 return IXGBE_ERR_SFP_NOT_PRESENT;
1112         case ixgbe_sfp_type_da_cu_core0:
1113         case ixgbe_sfp_type_da_cu_core1:
1114                 *linear = true;
1115                 break;
1116         case ixgbe_sfp_type_srlr_core0:
1117         case ixgbe_sfp_type_srlr_core1:
1118         case ixgbe_sfp_type_da_act_lmt_core0:
1119         case ixgbe_sfp_type_da_act_lmt_core1:
1120         case ixgbe_sfp_type_1g_sx_core0:
1121         case ixgbe_sfp_type_1g_sx_core1:
1122         case ixgbe_sfp_type_1g_lx_core0:
1123         case ixgbe_sfp_type_1g_lx_core1:
1124                 *linear = false;
1125                 break;
1126         case ixgbe_sfp_type_unknown:
1127         case ixgbe_sfp_type_1g_cu_core0:
1128         case ixgbe_sfp_type_1g_cu_core1:
1129         default:
1130                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1131         }
1132
1133         return IXGBE_SUCCESS;
1134 }
1135
1136 /**
1137  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1138  *  @hw: pointer to hardware structure
1139  *
1140  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1141  **/
1142 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1143 {
1144         s32 status;
1145         bool linear;
1146
1147         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1148
1149         status = ixgbe_identify_module_generic(hw);
1150
1151         if (status != IXGBE_SUCCESS)
1152                 return status;
1153
1154         /* Check if SFP module is supported */
1155         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1156
1157         return status;
1158 }
1159
1160 /**
1161  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1162  *  @hw: pointer to hardware structure
1163  */
1164 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1165 {
1166         s32 status;
1167         bool linear;
1168
1169         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1170
1171         /* Check if SFP module is supported */
1172         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1173
1174         if (status != IXGBE_SUCCESS)
1175                 return status;
1176
1177         ixgbe_init_mac_link_ops_X550em(hw);
1178         hw->phy.ops.reset = NULL;
1179
1180         return IXGBE_SUCCESS;
1181 }
1182
1183 /**
1184  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1185  *  @hw: pointer to hardware structure
1186  */
1187 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1188 {
1189         struct ixgbe_mac_info *mac = &hw->mac;
1190
1191         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1192
1193          switch (hw->mac.ops.get_media_type(hw)) {
1194          case ixgbe_media_type_fiber:
1195                 /* CS4227 does not support autoneg, so disable the laser control
1196                  * functions for SFP+ fiber
1197                  */
1198                 mac->ops.disable_tx_laser = NULL;
1199                 mac->ops.enable_tx_laser = NULL;
1200                 mac->ops.flap_tx_laser = NULL;
1201                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1202                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1203                 mac->ops.set_rate_select_speed =
1204                                         ixgbe_set_soft_rate_select_speed;
1205                 break;
1206         case ixgbe_media_type_copper:
1207                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1208                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1209                 break;
1210         default:
1211                 break;
1212          }
1213 }
1214
1215 /**
1216  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1217  *  @hw: pointer to hardware structure
1218  *  @speed: pointer to link speed
1219  *  @autoneg: true when autoneg or autotry is enabled
1220  */
1221 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1222                                        ixgbe_link_speed *speed,
1223                                        bool *autoneg)
1224 {
1225         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1226
1227         /* SFP */
1228         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1229
1230                 /* CS4227 SFP must not enable auto-negotiation */
1231                 *autoneg = false;
1232
1233                 /* Check if 1G SFP module. */
1234                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1235                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1236                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1237                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1238                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1239                         return IXGBE_SUCCESS;
1240                 }
1241
1242                 /* Link capabilities are based on SFP */
1243                 if (hw->phy.multispeed_fiber)
1244                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1245                                  IXGBE_LINK_SPEED_1GB_FULL;
1246                 else
1247                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1248         } else {
1249                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1250                          IXGBE_LINK_SPEED_1GB_FULL;
1251                 *autoneg = true;
1252         }
1253
1254         return IXGBE_SUCCESS;
1255 }
1256
1257 /**
1258  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1259  * @hw: pointer to hardware structure
1260  * @lsc: pointer to boolean flag which indicates whether external Base T
1261  *       PHY interrupt is lsc
1262  *
1263  * Determime if external Base T PHY interrupt cause is high temperature
1264  * failure alarm or link status change.
1265  *
1266  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1267  * failure alarm, else return PHY access status.
1268  */
1269 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1270 {
1271         u32 status;
1272         u16 reg;
1273
1274         *lsc = false;
1275
1276         /* Vendor alarm triggered */
1277         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1278                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1279                                       &reg);
1280
1281         if (status != IXGBE_SUCCESS ||
1282             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1283                 return status;
1284
1285         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1286         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1287                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1288                                       &reg);
1289
1290         if (status != IXGBE_SUCCESS ||
1291             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1292             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1293                 return status;
1294
1295         /* High temperature failure alarm triggered */
1296         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1297                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1298                                       &reg);
1299
1300         if (status != IXGBE_SUCCESS)
1301                 return status;
1302
1303         /* If high temperature failure, then return over temp error and exit */
1304         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1305                 /* power down the PHY in case the PHY FW didn't already */
1306                 ixgbe_set_copper_phy_power(hw, false);
1307                 return IXGBE_ERR_OVERTEMP;
1308         }
1309
1310         /* Vendor alarm 2 triggered */
1311         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1312                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1313
1314         if (status != IXGBE_SUCCESS ||
1315             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1316                 return status;
1317
1318         /* link connect/disconnect event occurred */
1319         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1320                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1321
1322         if (status != IXGBE_SUCCESS)
1323                 return status;
1324
1325         /* Indicate LSC */
1326         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1327                 *lsc = true;
1328
1329         return IXGBE_SUCCESS;
1330 }
1331
1332 /**
1333  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1334  * @hw: pointer to hardware structure
1335  *
1336  * Enable link status change and temperature failure alarm for the external
1337  * Base T PHY
1338  *
1339  * Returns PHY access status
1340  */
1341 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1342 {
1343         u32 status;
1344         u16 reg;
1345         bool lsc;
1346
1347         /* Clear interrupt flags */
1348         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1349
1350         /* Enable link status change alarm */
1351         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1352                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1353
1354         if (status != IXGBE_SUCCESS)
1355                 return status;
1356
1357         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1358
1359         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1360                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1361
1362         if (status != IXGBE_SUCCESS)
1363                 return status;
1364
1365         /* Enables high temperature failure alarm */
1366         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1367                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1368                                       &reg);
1369
1370         if (status != IXGBE_SUCCESS)
1371                 return status;
1372
1373         reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1374
1375         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1376                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1377                                        reg);
1378
1379         if (status != IXGBE_SUCCESS)
1380                 return status;
1381
1382         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1383         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1384                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1385                                       &reg);
1386
1387         if (status != IXGBE_SUCCESS)
1388                 return status;
1389
1390         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1391                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1392
1393         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1394                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1395                                        reg);
1396
1397         if (status != IXGBE_SUCCESS)
1398                 return status;
1399
1400         /* Enable chip-wide vendor alarm */
1401         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1402                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1403                                       &reg);
1404
1405         if (status != IXGBE_SUCCESS)
1406                 return status;
1407
1408         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1409
1410         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1411                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1412                                        reg);
1413
1414         return status;
1415 }
1416
1417 /**
1418  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1419  *  @hw: pointer to hardware structure
1420  *
1421  *  Initialize any function pointers that were not able to be
1422  *  set during init_shared_code because the PHY/SFP type was
1423  *  not known.  Perform the SFP init if necessary.
1424  */
1425 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1426 {
1427         struct ixgbe_phy_info *phy = &hw->phy;
1428         s32 ret_val;
1429
1430         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1431
1432         hw->mac.ops.set_lan_id(hw);
1433
1434         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1435                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1436                 ixgbe_setup_mux_ctl(hw);
1437
1438                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1439         }
1440
1441         /* Identify the PHY or SFP module */
1442         ret_val = phy->ops.identify(hw);
1443         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1444                 return ret_val;
1445
1446         /* Setup function pointers based on detected hardware */
1447         ixgbe_init_mac_link_ops_X550em(hw);
1448         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1449                 phy->ops.reset = NULL;
1450
1451         /* Set functions pointers based on phy type */
1452         switch (hw->phy.type) {
1453         case ixgbe_phy_x550em_kx4:
1454                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1455                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1456                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1457                 break;
1458         case ixgbe_phy_x550em_kr:
1459                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1460                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1461                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1462                 break;
1463         case ixgbe_phy_x550em_ext_t:
1464                 phy->ops.setup_internal_link =
1465                                          ixgbe_setup_internal_phy_t_x550em;
1466                 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1467                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1468                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1469                 break;
1470         default:
1471                 break;
1472         }
1473         return ret_val;
1474 }
1475
1476 /**
1477  *  ixgbe_reset_hw_X550em - Perform hardware reset
1478  *  @hw: pointer to hardware structure
1479  *
1480  *  Resets the hardware by resetting the transmit and receive units, masks
1481  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1482  *  reset.
1483  */
1484 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1485 {
1486         ixgbe_link_speed link_speed;
1487         s32 status;
1488         u32 ctrl = 0;
1489         u32 i;
1490         bool link_up = false;
1491
1492         DEBUGFUNC("ixgbe_reset_hw_X550em");
1493
1494         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1495         status = hw->mac.ops.stop_adapter(hw);
1496         if (status != IXGBE_SUCCESS)
1497                 return status;
1498
1499         /* flush pending Tx transactions */
1500         ixgbe_clear_tx_pending(hw);
1501
1502         /* PHY ops must be identified and initialized prior to reset */
1503
1504         /* Identify PHY and related function pointers */
1505         status = hw->phy.ops.init(hw);
1506
1507         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1508                 return status;
1509
1510         /* start the external PHY */
1511         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1512                 status = ixgbe_init_ext_t_x550em(hw);
1513                 if (status)
1514                         return status;
1515         }
1516
1517         /* Setup SFP module if there is one present. */
1518         if (hw->phy.sfp_setup_needed) {
1519                 status = hw->mac.ops.setup_sfp(hw);
1520                 hw->phy.sfp_setup_needed = false;
1521         }
1522
1523         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1524                 return status;
1525
1526         /* Reset PHY */
1527         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1528                 hw->phy.ops.reset(hw);
1529
1530 mac_reset_top:
1531         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1532          * If link reset is used when link is up, it might reset the PHY when
1533          * mng is using it.  If link is down or the flag to force full link
1534          * reset is set, then perform link reset.
1535          */
1536         ctrl = IXGBE_CTRL_LNK_RST;
1537         if (!hw->force_full_reset) {
1538                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1539                 if (link_up)
1540                         ctrl = IXGBE_CTRL_RST;
1541         }
1542
1543         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1544         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1545         IXGBE_WRITE_FLUSH(hw);
1546
1547         /* Poll for reset bit to self-clear meaning reset is complete */
1548         for (i = 0; i < 10; i++) {
1549                 usec_delay(1);
1550                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1551                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1552                         break;
1553         }
1554
1555         if (ctrl & IXGBE_CTRL_RST_MASK) {
1556                 status = IXGBE_ERR_RESET_FAILED;
1557                 DEBUGOUT("Reset polling failed to complete.\n");
1558         }
1559
1560         msec_delay(50);
1561
1562         /* Double resets are required for recovery from certain error
1563          * conditions.  Between resets, it is necessary to stall to
1564          * allow time for any pending HW events to complete.
1565          */
1566         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1567                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1568                 goto mac_reset_top;
1569         }
1570
1571         /* Store the permanent mac address */
1572         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1573
1574         /* Store MAC address from RAR0, clear receive address registers, and
1575          * clear the multicast table.  Also reset num_rar_entries to 128,
1576          * since we modify this value when programming the SAN MAC address.
1577          */
1578         hw->mac.num_rar_entries = 128;
1579         hw->mac.ops.init_rx_addrs(hw);
1580
1581
1582         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1583                 ixgbe_setup_mux_ctl(hw);
1584
1585         return status;
1586 }
1587
1588 /**
1589  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1590  * @hw: pointer to hardware structure
1591  */
1592 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1593 {
1594         u32 status;
1595         u16 reg;
1596
1597         status = hw->phy.ops.read_reg(hw,
1598                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1599                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1600                                       &reg);
1601
1602         if (status != IXGBE_SUCCESS)
1603                 return status;
1604
1605         /* If PHY FW reset completed bit is set then this is the first
1606          * SW instance after a power on so the PHY FW must be un-stalled.
1607          */
1608         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1609                 status = hw->phy.ops.read_reg(hw,
1610                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1611                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1612                                         &reg);
1613
1614                 if (status != IXGBE_SUCCESS)
1615                         return status;
1616
1617                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1618
1619                 status = hw->phy.ops.write_reg(hw,
1620                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1621                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1622                                         reg);
1623
1624                 if (status != IXGBE_SUCCESS)
1625                         return status;
1626         }
1627
1628         return status;
1629 }
1630
1631 /**
1632  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1633  *  @hw: pointer to hardware structure
1634  *
1635  *  Configures the integrated KR PHY.
1636  **/
1637 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1638 {
1639         s32 status;
1640         u32 reg_val;
1641
1642         status = ixgbe_read_iosf_sb_reg_x550(hw,
1643                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1644                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1645         if (status)
1646                 return status;
1647
1648         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1649         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1650                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1651
1652         /* Advertise 10G support. */
1653         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1654                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1655
1656         /* Advertise 1G support. */
1657         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1658                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1659
1660         /* Restart auto-negotiation. */
1661         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1662         status = ixgbe_write_iosf_sb_reg_x550(hw,
1663                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1664                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1665
1666         return status;
1667 }
1668
1669 /**
1670  *  ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1671  *  @hw: pointer to hardware structure
1672  *
1673  *  Configures the integrated KX4 PHY.
1674  **/
1675 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1676 {
1677         s32 status;
1678         u32 reg_val;
1679
1680         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1681                 IXGBE_SB_IOSF_TARGET_KX4_PCS, &reg_val);
1682         if (status)
1683                 return status;
1684
1685         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1686                         IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1687
1688         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1689
1690         /* Advertise 10G support. */
1691         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1692                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1693
1694         /* Advertise 1G support. */
1695         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1696                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1697
1698         /* Restart auto-negotiation. */
1699         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1700         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1701                 IXGBE_SB_IOSF_TARGET_KX4_PCS, reg_val);
1702
1703         return status;
1704 }
1705
1706 /**
1707  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1708  *  @hw: pointer to hardware structure
1709  *  @speed: the link speed to force
1710  *
1711  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1712  *  internal and external PHY at a specific speed, without autonegotiation.
1713  **/
1714 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1715 {
1716         s32 status;
1717         u32 reg_val;
1718
1719         /* Disable AN and force speed to 10G Serial. */
1720         status = ixgbe_read_iosf_sb_reg_x550(hw,
1721                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1722                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1723         if (status != IXGBE_SUCCESS)
1724                 return status;
1725
1726         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1727         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1728
1729         /* Select forced link speed for internal PHY. */
1730         switch (*speed) {
1731         case IXGBE_LINK_SPEED_10GB_FULL:
1732                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1733                 break;
1734         case IXGBE_LINK_SPEED_1GB_FULL:
1735                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1736                 break;
1737         default:
1738                 /* Other link speeds are not supported by internal KR PHY. */
1739                 return IXGBE_ERR_LINK_SETUP;
1740         }
1741
1742         status = ixgbe_write_iosf_sb_reg_x550(hw,
1743                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1744                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1745         if (status != IXGBE_SUCCESS)
1746                 return status;
1747
1748         /* Disable training protocol FSM. */
1749         status = ixgbe_read_iosf_sb_reg_x550(hw,
1750                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1751                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1752         if (status != IXGBE_SUCCESS)
1753                 return status;
1754         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1755         status = ixgbe_write_iosf_sb_reg_x550(hw,
1756                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1757                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1758         if (status != IXGBE_SUCCESS)
1759                 return status;
1760
1761         /* Disable Flex from training TXFFE. */
1762         status = ixgbe_read_iosf_sb_reg_x550(hw,
1763                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1764                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1765         if (status != IXGBE_SUCCESS)
1766                 return status;
1767         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1768         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1769         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1770         status = ixgbe_write_iosf_sb_reg_x550(hw,
1771                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1772                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1773         if (status != IXGBE_SUCCESS)
1774                 return status;
1775         status = ixgbe_read_iosf_sb_reg_x550(hw,
1776                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1777                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1778         if (status != IXGBE_SUCCESS)
1779                 return status;
1780         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1781         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1782         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1783         status = ixgbe_write_iosf_sb_reg_x550(hw,
1784                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1785                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1786         if (status != IXGBE_SUCCESS)
1787                 return status;
1788
1789         /* Enable override for coefficients. */
1790         status = ixgbe_read_iosf_sb_reg_x550(hw,
1791                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1792                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1793         if (status != IXGBE_SUCCESS)
1794                 return status;
1795         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1796         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1797         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1798         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1799         status = ixgbe_write_iosf_sb_reg_x550(hw,
1800                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1801                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1802         if (status != IXGBE_SUCCESS)
1803                 return status;
1804
1805         /* Toggle port SW reset by AN reset. */
1806         status = ixgbe_read_iosf_sb_reg_x550(hw,
1807                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1808                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1809         if (status != IXGBE_SUCCESS)
1810                 return status;
1811         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1812         status = ixgbe_write_iosf_sb_reg_x550(hw,
1813                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1814                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1815
1816         return status;
1817 }
1818
1819 /**
1820  *  ixgbe_setup_mac_link_sfp_x550em - Configure the CS4227 & KR PHY for SFP
1821  *  @hw: pointer to hardware structure
1822  *
1823  *  Configure the external CS4227 PHY and the integrated KR PHY for SFP support.
1824  **/
1825 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1826                                     ixgbe_link_speed speed,
1827                                     bool autoneg_wait_to_complete)
1828 {
1829         s32 ret_val;
1830         u16 reg_slice, reg_val;
1831         bool setup_linear = false;
1832         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1833
1834         /* Check if SFP module is supported and linear */
1835         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1836
1837         /* If no SFP module present, then return success. Return success since
1838          * there is no reason to configure CS4227 and SFP not present error is
1839          * not excepted in the setup MAC link flow.
1840          */
1841         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1842                 return IXGBE_SUCCESS;
1843
1844         if (ret_val != IXGBE_SUCCESS)
1845                 return ret_val;
1846
1847         /* Configure CS4227 for LINE connection rate then type. */
1848         reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1849         reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1850         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1851                                            reg_val);
1852
1853         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1854         if (setup_linear)
1855                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1856         else
1857                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1858         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1859                                            reg_val);
1860
1861         /* Configure CS4227 for HOST connection rate then type. */
1862         reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1863         reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1864         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1865                                            reg_val);
1866
1867         reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1868         if (setup_linear)
1869                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1870         else
1871                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1872         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1873                                            reg_val);
1874
1875         /* Configure the internal PHY. */
1876         ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1877
1878         return ret_val;
1879 }
1880
1881 /**
1882  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1883  * @hw: point to hardware structure
1884  *
1885  * Configures the link between the integrated KR PHY and the external X557 PHY
1886  * The driver will call this function when it gets a link status change
1887  * interrupt from the X557 PHY. This function configures the link speed
1888  * between the PHYs to match the link speed of the BASE-T link.
1889  *
1890  * A return of a non-zero value indicates an error, and the base driver should
1891  * not report link up.
1892  */
1893 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1894 {
1895         u32 status;
1896         u16 autoneg_status, speed;
1897         ixgbe_link_speed force_speed;
1898
1899         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1900                 return IXGBE_ERR_CONFIG;
1901
1902         /* read this twice back to back to indicate current status */
1903         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1904                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1905                                       &autoneg_status);
1906         if (status != IXGBE_SUCCESS)
1907                 return status;
1908
1909         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1910                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1911                                       &autoneg_status);
1912         if (status != IXGBE_SUCCESS)
1913                 return status;
1914
1915         /* If link is not up, then there is no setup necessary so return  */
1916         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1917                 return IXGBE_SUCCESS;
1918
1919         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1920                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1921                                       &speed);
1922
1923         /* clear everything but the speed and duplex bits */
1924         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1925
1926         switch (speed) {
1927         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1928                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1929                 break;
1930         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1931                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1932                 break;
1933         default:
1934                 /* Internal PHY does not support anything else */
1935                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1936         }
1937
1938         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1939 }
1940
1941 /**
1942  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1943  *  @hw: pointer to hardware structure
1944  *
1945  *  Configures the integrated KR PHY to use internal loopback mode.
1946  **/
1947 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1948 {
1949         s32 status;
1950         u32 reg_val;
1951
1952         /* Disable AN and force speed to 10G Serial. */
1953         status = ixgbe_read_iosf_sb_reg_x550(hw,
1954                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1955                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1956         if (status != IXGBE_SUCCESS)
1957                 return status;
1958         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1959         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1960         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1961         status = ixgbe_write_iosf_sb_reg_x550(hw,
1962                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1963                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1964         if (status != IXGBE_SUCCESS)
1965                 return status;
1966
1967         /* Set near-end loopback clocks. */
1968         status = ixgbe_read_iosf_sb_reg_x550(hw,
1969                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1970                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1971         if (status != IXGBE_SUCCESS)
1972                 return status;
1973         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1974         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1975         status = ixgbe_write_iosf_sb_reg_x550(hw,
1976                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1977                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1978         if (status != IXGBE_SUCCESS)
1979                 return status;
1980
1981         /* Set loopback enable. */
1982         status = ixgbe_read_iosf_sb_reg_x550(hw,
1983                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1984                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1985         if (status != IXGBE_SUCCESS)
1986                 return status;
1987         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1988         status = ixgbe_write_iosf_sb_reg_x550(hw,
1989                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1990                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1991         if (status != IXGBE_SUCCESS)
1992                 return status;
1993
1994         /* Training bypass. */
1995         status = ixgbe_read_iosf_sb_reg_x550(hw,
1996                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1997                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1998         if (status != IXGBE_SUCCESS)
1999                 return status;
2000         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2001         status = ixgbe_write_iosf_sb_reg_x550(hw,
2002                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2003                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2004
2005         return status;
2006 }
2007
2008 /**
2009  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2010  *  assuming that the semaphore is already obtained.
2011  *  @hw: pointer to hardware structure
2012  *  @offset: offset of  word in the EEPROM to read
2013  *  @data: word read from the EEPROM
2014  *
2015  *  Reads a 16 bit word from the EEPROM using the hostif.
2016  **/
2017 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2018                                    u16 *data)
2019 {
2020         s32 status;
2021         struct ixgbe_hic_read_shadow_ram buffer;
2022
2023         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2024         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2025         buffer.hdr.req.buf_lenh = 0;
2026         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2027         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2028
2029         /* convert offset from words to bytes */
2030         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2031         /* one word */
2032         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2033
2034         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2035                                               sizeof(buffer),
2036                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2037
2038         if (status)
2039                 return status;
2040
2041         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2042                                           FW_NVM_DATA_OFFSET);
2043
2044         return 0;
2045 }
2046
2047 /**
2048  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2049  *  @hw: pointer to hardware structure
2050  *  @offset: offset of  word in the EEPROM to read
2051  *  @data: word read from the EEPROM
2052  *
2053  *  Reads a 16 bit word from the EEPROM using the hostif.
2054  **/
2055 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2056                               u16 *data)
2057 {
2058         s32 status = IXGBE_SUCCESS;
2059
2060         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2061
2062         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2063             IXGBE_SUCCESS) {
2064                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2065                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2066         } else {
2067                 status = IXGBE_ERR_SWFW_SYNC;
2068         }
2069
2070         return status;
2071 }
2072
2073 /**
2074  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2075  *  @hw: pointer to hardware structure
2076  *  @offset: offset of  word in the EEPROM to read
2077  *  @words: number of words
2078  *  @data: word(s) read from the EEPROM
2079  *
2080  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
2081  **/
2082 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2083                                      u16 offset, u16 words, u16 *data)
2084 {
2085         struct ixgbe_hic_read_shadow_ram buffer;
2086         u32 current_word = 0;
2087         u16 words_to_read;
2088         s32 status;
2089         u32 i;
2090
2091         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2092
2093         /* Take semaphore for the entire operation. */
2094         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2095         if (status) {
2096                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2097                 return status;
2098         }
2099         while (words) {
2100                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2101                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2102                 else
2103                         words_to_read = words;
2104
2105                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2106                 buffer.hdr.req.buf_lenh = 0;
2107                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2108                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2109
2110                 /* convert offset from words to bytes */
2111                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2112                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2113
2114                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2115                                                       sizeof(buffer),
2116                                                       IXGBE_HI_COMMAND_TIMEOUT,
2117                                                       false);
2118
2119                 if (status) {
2120                         DEBUGOUT("Host interface command failed\n");
2121                         goto out;
2122                 }
2123
2124                 for (i = 0; i < words_to_read; i++) {
2125                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2126                                   2 * i;
2127                         u32 value = IXGBE_READ_REG(hw, reg);
2128
2129                         data[current_word] = (u16)(value & 0xffff);
2130                         current_word++;
2131                         i++;
2132                         if (i < words_to_read) {
2133                                 value >>= 16;
2134                                 data[current_word] = (u16)(value & 0xffff);
2135                                 current_word++;
2136                         }
2137                 }
2138                 words -= words_to_read;
2139         }
2140
2141 out:
2142         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2143         return status;
2144 }
2145
2146 /**
2147  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2148  *  @hw: pointer to hardware structure
2149  *  @offset: offset of  word in the EEPROM to write
2150  *  @data: word write to the EEPROM
2151  *
2152  *  Write a 16 bit word to the EEPROM using the hostif.
2153  **/
2154 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2155                                     u16 data)
2156 {
2157         s32 status;
2158         struct ixgbe_hic_write_shadow_ram buffer;
2159
2160         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2161
2162         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2163         buffer.hdr.req.buf_lenh = 0;
2164         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2165         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2166
2167          /* one word */
2168         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2169         buffer.data = data;
2170         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2171
2172         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2173                                               sizeof(buffer),
2174                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2175
2176         return status;
2177 }
2178
2179 /**
2180  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2181  *  @hw: pointer to hardware structure
2182  *  @offset: offset of  word in the EEPROM to write
2183  *  @data: word write to the EEPROM
2184  *
2185  *  Write a 16 bit word to the EEPROM using the hostif.
2186  **/
2187 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2188                                u16 data)
2189 {
2190         s32 status = IXGBE_SUCCESS;
2191
2192         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2193
2194         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2195             IXGBE_SUCCESS) {
2196                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2197                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2198         } else {
2199                 DEBUGOUT("write ee hostif failed to get semaphore");
2200                 status = IXGBE_ERR_SWFW_SYNC;
2201         }
2202
2203         return status;
2204 }
2205
2206 /**
2207  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2208  *  @hw: pointer to hardware structure
2209  *  @offset: offset of  word in the EEPROM to write
2210  *  @words: number of words
2211  *  @data: word(s) write to the EEPROM
2212  *
2213  *  Write a 16 bit word(s) to the EEPROM using the hostif.
2214  **/
2215 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2216                                       u16 offset, u16 words, u16 *data)
2217 {
2218         s32 status = IXGBE_SUCCESS;
2219         u32 i = 0;
2220
2221         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2222
2223         /* Take semaphore for the entire operation. */
2224         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2225         if (status != IXGBE_SUCCESS) {
2226                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2227                 goto out;
2228         }
2229
2230         for (i = 0; i < words; i++) {
2231                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2232                                                          data[i]);
2233
2234                 if (status != IXGBE_SUCCESS) {
2235                         DEBUGOUT("Eeprom buffered write failed\n");
2236                         break;
2237                 }
2238         }
2239
2240         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2241 out:
2242
2243         return status;
2244 }
2245
2246 /**
2247  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2248  * @hw: pointer to hardware structure
2249  * @ptr: pointer offset in eeprom
2250  * @size: size of section pointed by ptr, if 0 first word will be used as size
2251  * @csum: address of checksum to update
2252  *
2253  * Returns error status for any failure
2254  */
2255 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2256                                    u16 size, u16 *csum, u16 *buffer,
2257                                    u32 buffer_size)
2258 {
2259         u16 buf[256];
2260         s32 status;
2261         u16 length, bufsz, i, start;
2262         u16 *local_buffer;
2263
2264         bufsz = sizeof(buf) / sizeof(buf[0]);
2265
2266         /* Read a chunk at the pointer location */
2267         if (!buffer) {
2268                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2269                 if (status) {
2270                         DEBUGOUT("Failed to read EEPROM image\n");
2271                         return status;
2272                 }
2273                 local_buffer = buf;
2274         } else {
2275                 if (buffer_size < ptr)
2276                         return  IXGBE_ERR_PARAM;
2277                 local_buffer = &buffer[ptr];
2278         }
2279
2280         if (size) {
2281                 start = 0;
2282                 length = size;
2283         } else {
2284                 start = 1;
2285                 length = local_buffer[0];
2286
2287                 /* Skip pointer section if length is invalid. */
2288                 if (length == 0xFFFF || length == 0 ||
2289                     (ptr + length) >= hw->eeprom.word_size)
2290                         return IXGBE_SUCCESS;
2291         }
2292
2293         if (buffer && ((u32)start + (u32)length > buffer_size))
2294                 return IXGBE_ERR_PARAM;
2295
2296         for (i = start; length; i++, length--) {
2297                 if (i == bufsz && !buffer) {
2298                         ptr += bufsz;
2299                         i = 0;
2300                         if (length < bufsz)
2301                                 bufsz = length;
2302
2303                         /* Read a chunk at the pointer location */
2304                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2305                                                                   bufsz, buf);
2306                         if (status) {
2307                                 DEBUGOUT("Failed to read EEPROM image\n");
2308                                 return status;
2309                         }
2310                 }
2311                 *csum += local_buffer[i];
2312         }
2313         return IXGBE_SUCCESS;
2314 }
2315
2316 /**
2317  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2318  *  @hw: pointer to hardware structure
2319  *  @buffer: pointer to buffer containing calculated checksum
2320  *  @buffer_size: size of buffer
2321  *
2322  *  Returns a negative error code on error, or the 16-bit checksum
2323  **/
2324 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2325 {
2326         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2327         u16 *local_buffer;
2328         s32 status;
2329         u16 checksum = 0;
2330         u16 pointer, i, size;
2331
2332         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2333
2334         hw->eeprom.ops.init_params(hw);
2335
2336         if (!buffer) {
2337                 /* Read pointer area */
2338                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2339                                                      IXGBE_EEPROM_LAST_WORD + 1,
2340                                                      eeprom_ptrs);
2341                 if (status) {
2342                         DEBUGOUT("Failed to read EEPROM image\n");
2343                         return status;
2344                 }
2345                 local_buffer = eeprom_ptrs;
2346         } else {
2347                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2348                         return IXGBE_ERR_PARAM;
2349                 local_buffer = buffer;
2350         }
2351
2352         /*
2353          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2354          * checksum word itself
2355          */
2356         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2357                 if (i != IXGBE_EEPROM_CHECKSUM)
2358                         checksum += local_buffer[i];
2359
2360         /*
2361          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2362          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2363          */
2364         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2365                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2366                         continue;
2367
2368                 pointer = local_buffer[i];
2369
2370                 /* Skip pointer section if the pointer is invalid. */
2371                 if (pointer == 0xFFFF || pointer == 0 ||
2372                     pointer >= hw->eeprom.word_size)
2373                         continue;
2374
2375                 switch (i) {
2376                 case IXGBE_PCIE_GENERAL_PTR:
2377                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2378                         break;
2379                 case IXGBE_PCIE_CONFIG0_PTR:
2380                 case IXGBE_PCIE_CONFIG1_PTR:
2381                         size = IXGBE_PCIE_CONFIG_SIZE;
2382                         break;
2383                 default:
2384                         size = 0;
2385                         break;
2386                 }
2387
2388                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2389                                                 buffer, buffer_size);
2390                 if (status)
2391                         return status;
2392         }
2393
2394         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2395
2396         return (s32)checksum;
2397 }
2398
2399 /**
2400  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2401  *  @hw: pointer to hardware structure
2402  *
2403  *  Returns a negative error code on error, or the 16-bit checksum
2404  **/
2405 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2406 {
2407         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2408 }
2409
2410 /**
2411  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2412  *  @hw: pointer to hardware structure
2413  *  @checksum_val: calculated checksum
2414  *
2415  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2416  *  caller does not need checksum_val, the value can be NULL.
2417  **/
2418 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2419 {
2420         s32 status;
2421         u16 checksum;
2422         u16 read_checksum = 0;
2423
2424         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2425
2426         /* Read the first word from the EEPROM. If this times out or fails, do
2427          * not continue or we could be in for a very long wait while every
2428          * EEPROM read fails
2429          */
2430         status = hw->eeprom.ops.read(hw, 0, &checksum);
2431         if (status) {
2432                 DEBUGOUT("EEPROM read failed\n");
2433                 return status;
2434         }
2435
2436         status = hw->eeprom.ops.calc_checksum(hw);
2437         if (status < 0)
2438                 return status;
2439
2440         checksum = (u16)(status & 0xffff);
2441
2442         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2443                                            &read_checksum);
2444         if (status)
2445                 return status;
2446
2447         /* Verify read checksum from EEPROM is the same as
2448          * calculated checksum
2449          */
2450         if (read_checksum != checksum) {
2451                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2452                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2453                              "Invalid EEPROM checksum");
2454         }
2455
2456         /* If the user cares, return the calculated checksum */
2457         if (checksum_val)
2458                 *checksum_val = checksum;
2459
2460         return status;
2461 }
2462
2463 /**
2464  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2465  * @hw: pointer to hardware structure
2466  *
2467  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2468  * checksum and updates the EEPROM and instructs the hardware to update
2469  * the flash.
2470  **/
2471 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2472 {
2473         s32 status;
2474         u16 checksum = 0;
2475
2476         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2477
2478         /* Read the first word from the EEPROM. If this times out or fails, do
2479          * not continue or we could be in for a very long wait while every
2480          * EEPROM read fails
2481          */
2482         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2483         if (status) {
2484                 DEBUGOUT("EEPROM read failed\n");
2485                 return status;
2486         }
2487
2488         status = ixgbe_calc_eeprom_checksum_X550(hw);
2489         if (status < 0)
2490                 return status;
2491
2492         checksum = (u16)(status & 0xffff);
2493
2494         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2495                                             checksum);
2496         if (status)
2497                 return status;
2498
2499         status = ixgbe_update_flash_X550(hw);
2500
2501         return status;
2502 }
2503
2504 /**
2505  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2506  *  @hw: pointer to hardware structure
2507  *
2508  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2509  **/
2510 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2511 {
2512         s32 status = IXGBE_SUCCESS;
2513         union ixgbe_hic_hdr2 buffer;
2514
2515         DEBUGFUNC("ixgbe_update_flash_X550");
2516
2517         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2518         buffer.req.buf_lenh = 0;
2519         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2520         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2521
2522         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2523                                               sizeof(buffer),
2524                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2525
2526         return status;
2527 }
2528
2529 /**
2530  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2531  *  @hw: pointer to hardware structure
2532  *
2533  *  Determines physical layer capabilities of the current configuration.
2534  **/
2535 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2536 {
2537         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2538         u16 ext_ability = 0;
2539
2540         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2541
2542         hw->phy.ops.identify(hw);
2543
2544         switch (hw->phy.type) {
2545         case ixgbe_phy_x550em_kr:
2546                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2547                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2548                 break;
2549         case ixgbe_phy_x550em_kx4:
2550                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2551                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2552                 break;
2553         case ixgbe_phy_x550em_ext_t:
2554                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2555                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2556                                      &ext_ability);
2557                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2558                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2559                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2560                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2561                 break;
2562         default:
2563                 break;
2564         }
2565
2566         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2567                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2568
2569         return physical_layer;
2570 }
2571
2572 /**
2573  * ixgbe_get_bus_info_x550em - Set PCI bus info
2574  * @hw: pointer to hardware structure
2575  *
2576  * Sets bus link width and speed to unknown because X550em is
2577  * not a PCI device.
2578  **/
2579 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2580 {
2581
2582         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2583
2584         hw->bus.width = ixgbe_bus_width_unknown;
2585         hw->bus.speed = ixgbe_bus_speed_unknown;
2586
2587         hw->mac.ops.set_lan_id(hw);
2588
2589         return IXGBE_SUCCESS;
2590 }
2591
2592 /**
2593  * ixgbe_disable_rx_x550 - Disable RX unit
2594  *
2595  * Enables the Rx DMA unit for x550
2596  **/
2597 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2598 {
2599         u32 rxctrl, pfdtxgswc;
2600         s32 status;
2601         struct ixgbe_hic_disable_rxen fw_cmd;
2602
2603         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2604
2605         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2606         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2607                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2608                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2609                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2610                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2611                         hw->mac.set_lben = true;
2612                 } else {
2613                         hw->mac.set_lben = false;
2614                 }
2615
2616                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2617                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2618                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2619                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2620
2621                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2622                                         sizeof(struct ixgbe_hic_disable_rxen),
2623                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2624
2625                 /* If we fail - disable RX using register write */
2626                 if (status) {
2627                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2628                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2629                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2630                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2631                         }
2632                 }
2633         }
2634 }
2635
2636 /**
2637  * ixgbe_enter_lplu_x550em - Transition to low power states
2638  *  @hw: pointer to hardware structure
2639  *
2640  * Configures Low Power Link Up on transition to low power states
2641  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2642  * X557 PHY immediately prior to entering LPLU.
2643  **/
2644 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2645 {
2646         u16 autoneg_status, an_10g_cntl_reg, autoneg_reg, speed;
2647         s32 status;
2648         ixgbe_link_speed lcd_speed;
2649         u32 save_autoneg;
2650
2651         /* If blocked by MNG FW, then don't restart AN */
2652         if (ixgbe_check_reset_blocked(hw))
2653                 return IXGBE_SUCCESS;
2654
2655         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2656                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2657                                       &autoneg_status);
2658
2659         if (status != IXGBE_SUCCESS)
2660                 return status;
2661
2662         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2663
2664         if (status != IXGBE_SUCCESS)
2665                 return status;
2666
2667         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2668          * disabled, then force link down by entering low power mode.
2669          */
2670         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS) ||
2671             !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2672             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2673                 return ixgbe_set_copper_phy_power(hw, FALSE);
2674
2675         /* Determine LCD */
2676         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2677
2678         if (status != IXGBE_SUCCESS)
2679                 return status;
2680
2681         /* If no valid LCD link speed, then force link down and exit. */
2682         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2683                 return ixgbe_set_copper_phy_power(hw, FALSE);
2684
2685         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2686                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2687                                       &speed);
2688
2689         if (status != IXGBE_SUCCESS)
2690                 return status;
2691
2692         /* clear everything but the speed bits */
2693         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2694
2695         /* If current speed is already LCD, then exit. */
2696         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2697              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2698             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2699              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2700                 return status;
2701
2702         /* Clear AN completed indication */
2703         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2704                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2705                                       &autoneg_status);
2706
2707         if (status != IXGBE_SUCCESS)
2708                 return status;
2709
2710         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2711                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2712                              &an_10g_cntl_reg);
2713
2714         if (status != IXGBE_SUCCESS)
2715                 return status;
2716
2717         status = hw->phy.ops.read_reg(hw,
2718                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2719                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2720                              &autoneg_reg);
2721
2722         if (status != IXGBE_SUCCESS)
2723                 return status;
2724
2725         save_autoneg = hw->phy.autoneg_advertised;
2726
2727         /* Setup link at least common link speed */
2728         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2729
2730         /* restore autoneg from before setting lplu speed */
2731         hw->phy.autoneg_advertised = save_autoneg;
2732
2733         return status;
2734 }
2735
2736 /**
2737  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2738  *  @hw: pointer to hardware structure
2739  *  @lcd_speed: pointer to lowest common link speed
2740  *
2741  * Determine lowest common link speed with link partner.
2742  **/
2743 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2744 {
2745         u16 an_lp_status;
2746         s32 status;
2747         u16 word = hw->eeprom.ctrl_word_3;
2748
2749         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2750
2751         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2752                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2753                                       &an_lp_status);
2754
2755         if (status != IXGBE_SUCCESS)
2756                 return status;
2757
2758         /* If link partner advertised 1G, return 1G */
2759         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2760                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2761                 return status;
2762         }
2763
2764         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2765         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2766             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2767                 return status;
2768
2769         /* Link partner not capable of lower speeds, return 10G */
2770         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2771         return status;
2772 }
2773
2774 /**
2775  *  ixgbe_setup_fc_X550em - Set up flow control
2776  *  @hw: pointer to hardware structure
2777  *
2778  *  Called at init time to set up flow control.
2779  **/
2780 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2781 {
2782         s32 ret_val = IXGBE_SUCCESS;
2783         u32 pause, asm_dir, reg_val;
2784
2785         DEBUGFUNC("ixgbe_setup_fc_X550em");
2786
2787         /* Validate the requested mode */
2788         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2789                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2790                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2791                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2792                 goto out;
2793         }
2794
2795         /* 10gig parts do not have a word in the EEPROM to determine the
2796          * default flow control setting, so we explicitly set it to full.
2797          */
2798         if (hw->fc.requested_mode == ixgbe_fc_default)
2799                 hw->fc.requested_mode = ixgbe_fc_full;
2800
2801         /* Determine PAUSE and ASM_DIR bits. */
2802         switch (hw->fc.requested_mode) {
2803         case ixgbe_fc_none:
2804                 pause = 0;
2805                 asm_dir = 0;
2806                 break;
2807         case ixgbe_fc_tx_pause:
2808                 pause = 0;
2809                 asm_dir = 1;
2810                 break;
2811         case ixgbe_fc_rx_pause:
2812                 /* Rx Flow control is enabled and Tx Flow control is
2813                  * disabled by software override. Since there really
2814                  * isn't a way to advertise that we are capable of RX
2815                  * Pause ONLY, we will advertise that we support both
2816                  * symmetric and asymmetric Rx PAUSE, as such we fall
2817                  * through to the fc_full statement.  Later, we will
2818                  * disable the adapter's ability to send PAUSE frames.
2819                  */
2820         case ixgbe_fc_full:
2821                 pause = 1;
2822                 asm_dir = 1;
2823                 break;
2824         default:
2825                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2826                         "Flow control param set incorrectly\n");
2827                 ret_val = IXGBE_ERR_CONFIG;
2828                 goto out;
2829         }
2830
2831         if (hw->phy.media_type == ixgbe_media_type_backplane) {
2832                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2833                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2834                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2835                 if (ret_val != IXGBE_SUCCESS)
2836                         goto out;
2837                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2838                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2839                 if (pause)
2840                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2841                 if (asm_dir)
2842                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2843                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2844                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2845                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2846
2847                 /* Not all devices fully support AN. */
2848                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR)
2849                         hw->fc.disable_fc_autoneg = true;
2850         }
2851
2852 out:
2853         return ret_val;
2854 }
2855
2856 /**
2857  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2858  * @hw: pointer to hardware structure
2859  * @state: set mux if 1, clear if 0
2860  */
2861 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2862 {
2863         u32 esdp;
2864
2865         if (!hw->bus.lan_id)
2866                 return;
2867         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2868         if (state)
2869                 esdp |= IXGBE_ESDP_SDP1;
2870         else
2871                 esdp &= ~IXGBE_ESDP_SDP1;
2872         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2873         IXGBE_WRITE_FLUSH(hw);
2874 }
2875
2876 /**
2877  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2878  *  @hw: pointer to hardware structure
2879  *  @mask: Mask to specify which semaphore to acquire
2880  *
2881  *  Acquires the SWFW semaphore and sets the I2C MUX
2882  **/
2883 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2884 {
2885         s32 status;
2886
2887         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2888
2889         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2890         if (status)
2891                 return status;
2892
2893         if (mask & IXGBE_GSSR_I2C_MASK)
2894                 ixgbe_set_mux(hw, 1);
2895
2896         return IXGBE_SUCCESS;
2897 }
2898
2899 /**
2900  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2901  *  @hw: pointer to hardware structure
2902  *  @mask: Mask to specify which semaphore to release
2903  *
2904  *  Releases the SWFW semaphore and sets the I2C MUX
2905  **/
2906 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2907 {
2908         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2909
2910         if (mask & IXGBE_GSSR_I2C_MASK)
2911                 ixgbe_set_mux(hw, 0);
2912
2913         ixgbe_release_swfw_sync_X540(hw, mask);
2914 }
2915
2916 /**
2917  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2918  * @hw: pointer to hardware structure
2919  *
2920  * Handle external Base T PHY interrupt. If high temperature
2921  * failure alarm then return error, else if link status change
2922  * then setup internal/external PHY link
2923  *
2924  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2925  * failure alarm, else return PHY access status.
2926  */
2927 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2928 {
2929         bool lsc;
2930         u32 status;
2931
2932         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2933
2934         if (status != IXGBE_SUCCESS)
2935                 return status;
2936
2937         if (lsc)
2938                 return ixgbe_setup_internal_phy_t_x550em(hw);
2939
2940         return IXGBE_SUCCESS;
2941 }
2942
2943 /**
2944  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
2945  * @hw: pointer to hardware structure
2946  * @speed: new link speed
2947  * @autoneg_wait_to_complete: true when waiting for completion is needed
2948  *
2949  * Setup internal/external PHY link speed based on link speed, then set
2950  * external PHY auto advertised link speed.
2951  *
2952  * Returns error status for any failure
2953  **/
2954 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
2955                                   ixgbe_link_speed speed,
2956                                   bool autoneg_wait_to_complete)
2957 {
2958         s32 status;
2959         ixgbe_link_speed force_speed;
2960
2961         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
2962
2963         /* Setup internal/external PHY link speed to iXFI (10G), unless
2964          * only 1G is auto advertised then setup KX link.
2965          */
2966         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2967                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2968         else
2969                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2970
2971         status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
2972
2973         if (status != IXGBE_SUCCESS)
2974                 return status;
2975
2976         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
2977 }
2978
2979 /**
2980  * ixgbe_check_link_t_X550em - Determine link and speed status
2981  * @hw: pointer to hardware structure
2982  * @speed: pointer to link speed
2983  * @link_up: true when link is up
2984  * @link_up_wait_to_complete: bool used to wait for link up or not
2985  *
2986  * Check that both the MAC and X557 external PHY have link.
2987  **/
2988 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
2989                               bool *link_up, bool link_up_wait_to_complete)
2990 {
2991         u32 status;
2992         u16 autoneg_status;
2993
2994         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2995                 return IXGBE_ERR_CONFIG;
2996
2997         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
2998                                               link_up_wait_to_complete);
2999
3000         /* If check link fails or MAC link is not up, then return */
3001         if (status != IXGBE_SUCCESS || !(*link_up))
3002                 return status;
3003
3004         /* MAC link is up, so check external PHY link.
3005          * Read this twice back to back to indicate current status.
3006          */
3007         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3008                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3009                                       &autoneg_status);
3010
3011         if (status != IXGBE_SUCCESS)
3012                 return status;
3013
3014         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3015                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3016                                       &autoneg_status);
3017
3018         if (status != IXGBE_SUCCESS)
3019                 return status;
3020
3021         /* If external PHY link is not up, then indicate link not up */
3022         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3023                 *link_up = false;
3024
3025         return IXGBE_SUCCESS;
3026 }
3027
3028 /**
3029  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3030  *  @hw: pointer to hardware structure
3031  **/
3032 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3033 {
3034         s32 status;
3035
3036         status = ixgbe_reset_phy_generic(hw);
3037
3038         if (status != IXGBE_SUCCESS)
3039                 return status;
3040
3041         /* Configure Link Status Alarm and Temperature Threshold interrupts */
3042         return ixgbe_enable_lasi_ext_t_x550em(hw);
3043 }