drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44
  45 /**
  46  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  47  *  @hw: pointer to hardware structure
  48  *
  49  *  Initialize the function pointers and assign the MAC type for X550.
  50  *  Does not touch the hardware.
  51  **/
  52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  53 {
  54         struct ixgbe_mac_info *mac = &hw->mac;
  55         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  56         s32 ret_val;
  57
  58         DEBUGFUNC("ixgbe_init_ops_X550");
  59
  60         ret_val = ixgbe_init_ops_X540(hw);
  61         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  62         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  63         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  64         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  65         mac->ops.set_source_address_pruning =
  66                         ixgbe_set_source_address_pruning_X550;
  67         mac->ops.set_ethertype_anti_spoofing =
  68                         ixgbe_set_ethertype_anti_spoofing_X550;
  69
  70         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  71         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  72         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  73         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  74         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  75         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  76         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  77         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  78         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  79
  80         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  81         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  82         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  83         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  84         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  85         switch (hw->device_id) {
  86         case IXGBE_DEV_ID_X550EM_X_10G_T:
  87         case IXGBE_DEV_ID_X550EM_A_10G_T:
  88                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  89                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  90                 break;
  91         default:
  92                 break;
  93         }
  94         return ret_val;
  95 }
  96
  97 /**
  98  * ixgbe_read_cs4227 - Read CS4227 register
  99  * @hw: pointer to hardware structure
 100  * @reg: register number to write
 101  * @value: pointer to receive value read
 102  *
 103  * Returns status code
 104  **/
 105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 106 {
 107         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 108 }
 109
 110 /**
 111  * ixgbe_write_cs4227 - Write CS4227 register
 112  * @hw: pointer to hardware structure
 113  * @reg: register number to write
 114  * @value: value to write to register
 115  *
 116  * Returns status code
 117  **/
 118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 119 {
 120         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 121 }
 122
 123 /**
 124  * ixgbe_read_pe - Read register from port expander
 125  * @hw: pointer to hardware structure
 126  * @reg: register number to read
 127  * @value: pointer to receive read value
 128  *
 129  * Returns status code
 130  **/
 131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 132 {
 133         s32 status;
 134
 135         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 136         if (status != IXGBE_SUCCESS)
 137                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 138                               "port expander access failed with %d\n", status);
 139         return status;
 140 }
 141
 142 /**
 143  * ixgbe_write_pe - Write register to port expander
 144  * @hw: pointer to hardware structure
 145  * @reg: register number to write
 146  * @value: value to write
 147  *
 148  * Returns status code
 149  **/
 150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 151 {
 152         s32 status;
 153
 154         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 155         if (status != IXGBE_SUCCESS)
 156                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 157                               "port expander access failed with %d\n", status);
 158         return status;
 159 }
 160
 161 /**
 162  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 163  * @hw: pointer to hardware structure
 164  *
 165  * This function assumes that the caller has acquired the proper semaphore.
 166  * Returns error code
 167  **/
 168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 169 {
 170         s32 status;
 171         u32 retry;
 172         u16 value;
 173         u8 reg;
 174
 175         /* Trigger hard reset. */
 176         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 177         if (status != IXGBE_SUCCESS)
 178                 return status;
 179         reg |= IXGBE_PE_BIT1;
 180         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 181         if (status != IXGBE_SUCCESS)
 182                 return status;
 183
 184         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 185         if (status != IXGBE_SUCCESS)
 186                 return status;
 187         reg &= ~IXGBE_PE_BIT1;
 188         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 189         if (status != IXGBE_SUCCESS)
 190                 return status;
 191
 192         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 193         if (status != IXGBE_SUCCESS)
 194                 return status;
 195         reg &= ~IXGBE_PE_BIT1;
 196         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199
 200         usec_delay(IXGBE_CS4227_RESET_HOLD);
 201
 202         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 203         if (status != IXGBE_SUCCESS)
 204                 return status;
 205         reg |= IXGBE_PE_BIT1;
 206         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 207         if (status != IXGBE_SUCCESS)
 208                 return status;
 209
 210         /* Wait for the reset to complete. */
 211         msec_delay(IXGBE_CS4227_RESET_DELAY);
 212         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 213                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 214                                            &value);
 215                 if (status == IXGBE_SUCCESS &&
 216                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 217                         break;
 218                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 219         }
 220         if (retry == IXGBE_CS4227_RETRIES) {
 221                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 222                         "CS4227 reset did not complete.");
 223                 return IXGBE_ERR_PHY;
 224         }
 225
 226         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 227         if (status != IXGBE_SUCCESS ||
 228             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 229                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 230                         "CS4227 EEPROM did not load successfully.");
 231                 return IXGBE_ERR_PHY;
 232         }
 233
 234         return IXGBE_SUCCESS;
 235 }
 236
 237 /**
 238  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 239  * @hw: pointer to hardware structure
 240  **/
 241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 242 {
 243         s32 status = IXGBE_SUCCESS;
 244         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 245         u16 value = 0;
 246         u8 retry;
 247
 248         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 249                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 250                 if (status != IXGBE_SUCCESS) {
 251                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 252                                 "semaphore failed with %d", status);
 253                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 254                         continue;
 255                 }
 256
 257                 /* Get status of reset flow. */
 258                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 259
 260                 if (status == IXGBE_SUCCESS &&
 261                     value == IXGBE_CS4227_RESET_COMPLETE)
 262                         goto out;
 263
 264                 if (status != IXGBE_SUCCESS ||
 265                     value != IXGBE_CS4227_RESET_PENDING)
 266                         break;
 267
 268                 /* Reset is pending. Wait and check again. */
 269                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 270                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 271         }
 272
 273         /* If still pending, assume other instance failed. */
 274         if (retry == IXGBE_CS4227_RETRIES) {
 275                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 276                 if (status != IXGBE_SUCCESS) {
 277                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 278                                       "semaphore failed with %d", status);
 279                         return;
 280                 }
 281         }
 282
 283         /* Reset the CS4227. */
 284         status = ixgbe_reset_cs4227(hw);
 285         if (status != IXGBE_SUCCESS) {
 286                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 287                         "CS4227 reset failed: %d", status);
 288                 goto out;
 289         }
 290
 291         /* Reset takes so long, temporarily release semaphore in case the
 292          * other driver instance is waiting for the reset indication.
 293          */
 294         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 295                            IXGBE_CS4227_RESET_PENDING);
 296         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 297         msec_delay(10);
 298         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 299         if (status != IXGBE_SUCCESS) {
 300                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 301                         "semaphore failed with %d", status);
 302                 return;
 303         }
 304
 305         /* Record completion for next time. */
 306         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 307                 IXGBE_CS4227_RESET_COMPLETE);
 308
 309 out:
 310         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 311         msec_delay(hw->eeprom.semaphore_delay);
 312 }
 313
 314 /**
 315  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 316  * @hw: pointer to hardware structure
 317  **/
 318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 319 {
 320         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 321
 322         if (hw->bus.lan_id) {
 323                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 324                 esdp |= IXGBE_ESDP_SDP1_DIR;
 325         }
 326         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 327         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 328         IXGBE_WRITE_FLUSH(hw);
 329 }
 330
 331 /**
 332  * ixgbe_identify_phy_1g - Get 1g PHY type based on device id
 333  * @hw: pointer to hardware structure
 334  *
 335  * Returns error code
 336  */
 337 static s32 ixgbe_identify_phy_1g(struct ixgbe_hw *hw)
 338 {
 339         u16 phy_id_high;
 340         u16 phy_id_low;
 341         u32 val;
 342
 343         val = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 344                                    hw->phy.addr, &phy_id_high);
 345         if (val || phy_id_high == 0xFFFF) {
 346                 hw->phy.type = ixgbe_phy_sgmii;
 347                 return 0;
 348         }
 349
 350         val = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 351                                    hw->phy.addr, &phy_id_low);
 352         if (val)
 353                 return val;
 354
 355         hw->phy.id = (u32)phy_id_high << 16;
 356         hw->phy.id |= phy_id_low & IXGBE_PHY_REVISION_MASK;
 357         hw->phy.revision = (u32)phy_id_low & ~IXGBE_PHY_REVISION_MASK;
 358         hw->phy.type = ixgbe_phy_m88;
 359
 360         return 0;
 361 }
 362
 363 /**
 364  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 365  * @hw: pointer to hardware structure
 366  *
 367  * Returns error code
 368  */
 369 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 370 {
 371         switch (hw->device_id) {
 372         case IXGBE_DEV_ID_X550EM_A_SFP:
 373                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_TOKEN_SM;
 374                 if (hw->bus.lan_id)
 375                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 376                 else
 377                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 378                 return ixgbe_identify_module_generic(hw);
 379         case IXGBE_DEV_ID_X550EM_X_SFP:
 380                 /* set up for CS4227 usage */
 381                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 382                 ixgbe_setup_mux_ctl(hw);
 383                 ixgbe_check_cs4227(hw);
 384                 /* Fallthrough */
 385
 386         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 387                 return ixgbe_identify_module_generic(hw);
 388                 break;
 389         case IXGBE_DEV_ID_X550EM_X_KX4:
 390                 hw->phy.type = ixgbe_phy_x550em_kx4;
 391                 break;
 392         case IXGBE_DEV_ID_X550EM_X_KR:
 393         case IXGBE_DEV_ID_X550EM_A_KR:
 394         case IXGBE_DEV_ID_X550EM_A_KR_L:
 395                 hw->phy.type = ixgbe_phy_x550em_kr;
 396                 break;
 397         case IXGBE_DEV_ID_X550EM_X_1G_T:
 398         case IXGBE_DEV_ID_X550EM_X_10G_T:
 399         case IXGBE_DEV_ID_X550EM_A_10G_T:
 400                 return ixgbe_identify_phy_generic(hw);
 401         case IXGBE_DEV_ID_X550EM_A_1G_T:
 402         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 403                 return ixgbe_identify_phy_1g(hw);
 404         default:
 405                 break;
 406         }
 407         return IXGBE_SUCCESS;
 408 }
 409
 410 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 411                                      u32 device_type, u16 *phy_data)
 412 {
 413         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 414         return IXGBE_NOT_IMPLEMENTED;
 415 }
 416
 417 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 418                                       u32 device_type, u16 phy_data)
 419 {
 420         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 421         return IXGBE_NOT_IMPLEMENTED;
 422 }
 423
 424 /**
 425  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 426  * @hw: pointer to the hardware structure
 427  * @addr: I2C bus address to read from
 428  * @reg: I2C device register to read from
 429  * @val: pointer to location to receive read value
 430  *
 431  * Returns an error code on error.
 432  **/
 433 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 434                                            u16 reg, u16 *val)
 435 {
 436         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 437 }
 438
 439 /**
 440  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 441  * @hw: pointer to the hardware structure
 442  * @addr: I2C bus address to read from
 443  * @reg: I2C device register to read from
 444  * @val: pointer to location to receive read value
 445  *
 446  * Returns an error code on error.
 447  **/
 448 static s32
 449 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 450                                          u16 reg, u16 *val)
 451 {
 452         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 453 }
 454
 455 /**
 456  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 457  * @hw: pointer to the hardware structure
 458  * @addr: I2C bus address to write to
 459  * @reg: I2C device register to write to
 460  * @val: value to write
 461  *
 462  * Returns an error code on error.
 463  **/
 464 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 465                                             u8 addr, u16 reg, u16 val)
 466 {
 467         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 468 }
 469
 470 /**
 471  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 472  * @hw: pointer to the hardware structure
 473  * @addr: I2C bus address to write to
 474  * @reg: I2C device register to write to
 475  * @val: value to write
 476  *
 477  * Returns an error code on error.
 478  **/
 479 static s32
 480 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 481                                           u8 addr, u16 reg, u16 val)
 482 {
 483         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 484 }
 485
 486 /**
 487 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 488 *  @hw: pointer to hardware structure
 489 *
 490 *  Initialize the function pointers and for MAC type X550EM.
 491 *  Does not touch the hardware.
 492 **/
 493 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 494 {
 495         struct ixgbe_mac_info *mac = &hw->mac;
 496         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 497         struct ixgbe_phy_info *phy = &hw->phy;
 498         struct ixgbe_link_info *link = &hw->link;
 499         s32 ret_val;
 500
 501         DEBUGFUNC("ixgbe_init_ops_X550EM");
 502
 503         /* Similar to X550 so start there. */
 504         ret_val = ixgbe_init_ops_X550(hw);
 505
 506         /* Since this function eventually calls
 507          * ixgbe_init_ops_540 by design, we are setting
 508          * the pointers to NULL explicitly here to overwrite
 509          * the values being set in the x540 function.
 510          */
 511         /* Thermal sensor not supported in x550EM */
 512         mac->ops.get_thermal_sensor_data = NULL;
 513         mac->ops.init_thermal_sensor_thresh = NULL;
 514         mac->thermal_sensor_enabled = false;
 515
 516         /* FCOE not supported in x550EM */
 517         mac->ops.get_san_mac_addr = NULL;
 518         mac->ops.set_san_mac_addr = NULL;
 519         mac->ops.get_wwn_prefix = NULL;
 520         mac->ops.get_fcoe_boot_status = NULL;
 521
 522         /* IPsec not supported in x550EM */
 523         mac->ops.disable_sec_rx_path = NULL;
 524         mac->ops.enable_sec_rx_path = NULL;
 525
 526         /* AUTOC register is not present in x550EM. */
 527         mac->ops.prot_autoc_read = NULL;
 528         mac->ops.prot_autoc_write = NULL;
 529
 530         /* X550EM bus type is internal*/
 531         hw->bus.type = ixgbe_bus_type_internal;
 532         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 533
 534         if (hw->mac.type == ixgbe_mac_X550EM_x) {
 535                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 536                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 537                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 538                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 539                 link->ops.read_link = ixgbe_read_i2c_combined_generic;
 540                 link->ops.read_link_unlocked =
 541                                 ixgbe_read_i2c_combined_generic_unlocked;
 542                 link->ops.write_link = ixgbe_write_i2c_combined_generic;
 543                 link->ops.write_link_unlocked =
 544                                 ixgbe_write_i2c_combined_generic_unlocked;
 545                 link->addr = IXGBE_CS4227;
 546         }
 547         if (hw->mac.type == ixgbe_mac_X550EM_a) {
 548                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 549                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 550                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 551                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 552         }
 553
 554         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 555         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 556         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 557         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 558         mac->ops.get_supported_physical_layer =
 559                                     ixgbe_get_supported_physical_layer_X550em;
 560
 561         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 562                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 563         else
 564                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 565
 566         switch (hw->device_id) {
 567         case IXGBE_DEV_ID_X550EM_X_KR:
 568         case IXGBE_DEV_ID_X550EM_A_KR:
 569         case IXGBE_DEV_ID_X550EM_A_KR_L:
 570                 break;
 571         default:
 572                 mac->ops.setup_eee = NULL;
 573         }
 574
 575         /* PHY */
 576         phy->ops.init = ixgbe_init_phy_ops_X550em;
 577         phy->ops.identify = ixgbe_identify_phy_x550em;
 578         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 579                 phy->ops.set_phy_power = NULL;
 580
 581
 582         /* EEPROM */
 583         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 584         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 585         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 586         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 587         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 588         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 589         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 590         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 591
 592         return ret_val;
 593 }
 594
 595 /**
 596  *  ixgbe_dmac_config_X550
 597  *  @hw: pointer to hardware structure
 598  *
 599  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 600  *  When disabling dmac, dmac enable dmac bit is cleared.
 601  **/
 602 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 603 {
 604         u32 reg, high_pri_tc;
 605
 606         DEBUGFUNC("ixgbe_dmac_config_X550");
 607
 608         /* Disable DMA coalescing before configuring */
 609         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 610         reg &= ~IXGBE_DMACR_DMAC_EN;
 611         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 612
 613         /* Disable DMA Coalescing if the watchdog timer is 0 */
 614         if (!hw->mac.dmac_config.watchdog_timer)
 615                 goto out;
 616
 617         ixgbe_dmac_config_tcs_X550(hw);
 618
 619         /* Configure DMA Coalescing Control Register */
 620         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 621
 622         /* Set the watchdog timer in units of 40.96 usec */
 623         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 624         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 625
 626         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 627         /* If fcoe is enabled, set high priority traffic class */
 628         if (hw->mac.dmac_config.fcoe_en) {
 629                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 630                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 631                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 632         }
 633         reg |= IXGBE_DMACR_EN_MNG_IND;
 634
 635         /* Enable DMA coalescing after configuration */
 636         reg |= IXGBE_DMACR_DMAC_EN;
 637         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 638
 639 out:
 640         return IXGBE_SUCCESS;
 641 }
 642
 643 /**
 644  *  ixgbe_dmac_config_tcs_X550
 645  *  @hw: pointer to hardware structure
 646  *
 647  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 648  *  be cleared before configuring.
 649  **/
 650 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 651 {
 652         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 653
 654         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 655
 656         /* Configure DMA coalescing enabled */
 657         switch (hw->mac.dmac_config.link_speed) {
 658         case IXGBE_LINK_SPEED_100_FULL:
 659                 pb_headroom = IXGBE_DMACRXT_100M;
 660                 break;
 661         case IXGBE_LINK_SPEED_1GB_FULL:
 662                 pb_headroom = IXGBE_DMACRXT_1G;
 663                 break;
 664         default:
 665                 pb_headroom = IXGBE_DMACRXT_10G;
 666                 break;
 667         }
 668
 669         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 670                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 671
 672         /* Set the per Rx packet buffer receive threshold */
 673         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 674                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 675                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 676
 677                 if (tc < hw->mac.dmac_config.num_tcs) {
 678                         /* Get Rx PB size */
 679                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 680                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 681                                 IXGBE_RXPBSIZE_SHIFT;
 682
 683                         /* Calculate receive buffer threshold in kilobytes */
 684                         if (rx_pb_size > pb_headroom)
 685                                 rx_pb_size = rx_pb_size - pb_headroom;
 686                         else
 687                                 rx_pb_size = 0;
 688
 689                         /* Minimum of MFS shall be set for DMCTH */
 690                         reg |= (rx_pb_size > maxframe_size_kb) ?
 691                                 rx_pb_size : maxframe_size_kb;
 692                 }
 693                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 694         }
 695         return IXGBE_SUCCESS;
 696 }
 697
 698 /**
 699  *  ixgbe_dmac_update_tcs_X550
 700  *  @hw: pointer to hardware structure
 701  *
 702  *  Disables dmac, updates per TC settings, and then enables dmac.
 703  **/
 704 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 705 {
 706         u32 reg;
 707
 708         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 709
 710         /* Disable DMA coalescing before configuring */
 711         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 712         reg &= ~IXGBE_DMACR_DMAC_EN;
 713         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 714
 715         ixgbe_dmac_config_tcs_X550(hw);
 716
 717         /* Enable DMA coalescing after configuration */
 718         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 719         reg |= IXGBE_DMACR_DMAC_EN;
 720         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 721
 722         return IXGBE_SUCCESS;
 723 }
 724
 725 /**
 726  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 727  *  @hw: pointer to hardware structure
 728  *
 729  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 730  *  ixgbe_hw struct in order to set up EEPROM access.
 731  **/
 732 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 733 {
 734         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 735         u32 eec;
 736         u16 eeprom_size;
 737
 738         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 739
 740         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 741                 eeprom->semaphore_delay = 10;
 742                 eeprom->type = ixgbe_flash;
 743
 744                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 745                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 746                                     IXGBE_EEC_SIZE_SHIFT);
 747                 eeprom->word_size = 1 << (eeprom_size +
 748                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 749
 750                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 751                           eeprom->type, eeprom->word_size);
 752         }
 753
 754         return IXGBE_SUCCESS;
 755 }
 756
 757 /**
 758  * ixgbe_enable_eee_x550 - Enable EEE support
 759  * @hw: pointer to hardware structure
 760  */
 761 static s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
 762 {
 763         u16 autoneg_eee_reg;
 764         u32 link_reg;
 765         s32 status;
 766
 767         if (hw->mac.type == ixgbe_mac_X550) {
 768                 /* Advertise EEE capability */
 769                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 770                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 771                                      &autoneg_eee_reg);
 772
 773                 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 774                                     IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 775                                     IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 776
 777                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 778                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 779                                       autoneg_eee_reg);
 780                 return IXGBE_SUCCESS;
 781         }
 782
 783         switch (hw->device_id) {
 784         case IXGBE_DEV_ID_X550EM_X_KR:
 785         case IXGBE_DEV_ID_X550EM_A_KR:
 786         case IXGBE_DEV_ID_X550EM_A_KR_L:
 787                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 788                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 789                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 790                 if (status != IXGBE_SUCCESS)
 791                         return status;
 792
 793                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 794                         IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 795
 796                 /* Don't advertise FEC capability when EEE enabled. */
 797                 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 798
 799                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 800                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 801                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 802                 if (status != IXGBE_SUCCESS)
 803                         return status;
 804                 break;
 805         default:
 806                 break;
 807         }
 808
 809         return IXGBE_SUCCESS;
 810 }
 811
 812 /**
 813  * ixgbe_disable_eee_x550 - Disable EEE support
 814  * @hw: pointer to hardware structure
 815  */
 816 static s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
 817 {
 818         u16 autoneg_eee_reg;
 819         u32 link_reg;
 820         s32 status;
 821
 822         if (hw->mac.type == ixgbe_mac_X550) {
 823                 /* Disable advertised EEE capability */
 824                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 825                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 826                                      &autoneg_eee_reg);
 827
 828                 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 829                                      IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 830                                      IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 831
 832                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 833                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 834                                       autoneg_eee_reg);
 835                 return IXGBE_SUCCESS;
 836         }
 837
 838         switch (hw->device_id) {
 839         case IXGBE_DEV_ID_X550EM_X_KR:
 840         case IXGBE_DEV_ID_X550EM_A_KR:
 841         case IXGBE_DEV_ID_X550EM_A_KR_L:
 842                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 843                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 844                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 845                 if (status != IXGBE_SUCCESS)
 846                         return status;
 847
 848                 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 849                               IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 850
 851                 /* Advertise FEC capability when EEE is disabled. */
 852                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 853
 854                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 855                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 856                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 857                 if (status != IXGBE_SUCCESS)
 858                         return status;
 859                 break;
 860         default:
 861                 break;
 862         }
 863
 864         return IXGBE_SUCCESS;
 865 }
 866
 867 /**
 868  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 869  *  @hw: pointer to the HW structure
 870  *  @enable_eee: boolean flag to enable EEE
 871  *
 872  *  Enable/disable EEE based on enable_eee flag.
 873  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 874  *  are modified.
 875  *
 876  **/
 877 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 878 {
 879         s32 status;
 880         u32 eeer;
 881
 882         DEBUGFUNC("ixgbe_setup_eee_X550");
 883
 884         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 885         /* Enable or disable EEE per flag */
 886         if (enable_eee) {
 887                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 888
 889                 /* Not supported on first revision of X550EM_x. */
 890                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
 891                     !(IXGBE_FUSES0_REV_MASK &
 892                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
 893                         return IXGBE_SUCCESS;
 894                 status = ixgbe_enable_eee_x550(hw);
 895                 if (status)
 896                         return status;
 897         } else {
 898                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 899
 900                 status = ixgbe_disable_eee_x550(hw);
 901                 if (status)
 902                         return status;
 903         }
 904         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 905
 906         return IXGBE_SUCCESS;
 907 }
 908
 909 /**
 910  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 911  * @hw: pointer to hardware structure
 912  * @enable: enable or disable source address pruning
 913  * @pool: Rx pool to set source address pruning for
 914  **/
 915 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 916                                            unsigned int pool)
 917 {
 918         u64 pfflp;
 919
 920         /* max rx pool is 63 */
 921         if (pool > 63)
 922                 return;
 923
 924         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 925         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 926
 927         if (enable)
 928                 pfflp |= (1ULL << pool);
 929         else
 930                 pfflp &= ~(1ULL << pool);
 931
 932         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 933         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 934 }
 935
 936 /**
 937  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 938  *  @hw: pointer to hardware structure
 939  *  @enable: enable or disable switch for Ethertype anti-spoofing
 940  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 941  *
 942  **/
 943 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 944                 bool enable, int vf)
 945 {
 946         int vf_target_reg = vf >> 3;
 947         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 948         u32 pfvfspoof;
 949
 950         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 951
 952         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 953         if (enable)
 954                 pfvfspoof |= (1 << vf_target_shift);
 955         else
 956                 pfvfspoof &= ~(1 << vf_target_shift);
 957
 958         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 959 }
 960
 961 /**
 962  * ixgbe_iosf_wait - Wait for IOSF command completion
 963  * @hw: pointer to hardware structure
 964  * @ctrl: pointer to location to receive final IOSF control value
 965  *
 966  * Returns failing status on timeout
 967  *
 968  * Note: ctrl can be NULL if the IOSF control register value is not needed
 969  **/
 970 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 971 {
 972         u32 i, command = 0;
 973
 974         /* Check every 10 usec to see if the address cycle completed.
 975          * The SB IOSF BUSY bit will clear when the operation is
 976          * complete
 977          */
 978         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 979                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 980                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 981                         break;
 982                 usec_delay(10);
 983         }
 984         if (ctrl)
 985                 *ctrl = command;
 986         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 987                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
 988                 return IXGBE_ERR_PHY;
 989         }
 990
 991         return IXGBE_SUCCESS;
 992 }
 993
 994 /**
 995  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 996  *  device
 997  *  @hw: pointer to hardware structure
 998  *  @reg_addr: 32 bit PHY register to write
 999  *  @device_type: 3 bit device type
1000  *  @data: Data to write to the register
1001  **/
1002 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1003                             u32 device_type, u32 data)
1004 {
1005         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1006         u32 command, error;
1007         s32 ret;
1008
1009         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1010         if (ret != IXGBE_SUCCESS)
1011                 return ret;
1012
1013         ret = ixgbe_iosf_wait(hw, NULL);
1014         if (ret != IXGBE_SUCCESS)
1015                 goto out;
1016
1017         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1018                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1019
1020         /* Write IOSF control register */
1021         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1022
1023         /* Write IOSF data register */
1024         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1025
1026         ret = ixgbe_iosf_wait(hw, &command);
1027
1028         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1029                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1030                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1031                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1032                               "Failed to write, error %x\n", error);
1033                 ret = IXGBE_ERR_PHY;
1034         }
1035
1036 out:
1037         ixgbe_release_swfw_semaphore(hw, gssr);
1038         return ret;
1039 }
1040
1041 /**
1042  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1043  *  device
1044  *  @hw: pointer to hardware structure
1045  *  @reg_addr: 32 bit PHY register to write
1046  *  @device_type: 3 bit device type
1047  *  @phy_data: Pointer to read data from the register
1048  **/
1049 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1050                            u32 device_type, u32 *data)
1051 {
1052         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1053         u32 command, error;
1054         s32 ret;
1055
1056         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1057         if (ret != IXGBE_SUCCESS)
1058                 return ret;
1059
1060         ret = ixgbe_iosf_wait(hw, NULL);
1061         if (ret != IXGBE_SUCCESS)
1062                 goto out;
1063
1064         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1065                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1066
1067         /* Write IOSF control register */
1068         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1069
1070         ret = ixgbe_iosf_wait(hw, &command);
1071
1072         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1073                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1074                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1075                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1076                                 "Failed to read, error %x\n", error);
1077                 ret = IXGBE_ERR_PHY;
1078         }
1079
1080         if (ret == IXGBE_SUCCESS)
1081                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1082
1083 out:
1084         ixgbe_release_swfw_semaphore(hw, gssr);
1085         return ret;
1086 }
1087
1088 /**
1089  * ixgbe_get_phy_token - Get the token for shared phy access
1090  * @hw: Pointer to hardware structure
1091  */
1092
1093 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1094 {
1095         struct ixgbe_hic_phy_token_req token_cmd;
1096         s32 status;
1097
1098         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1099         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1100         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1101         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1102         token_cmd.port_number = hw->bus.lan_id;
1103         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1104         token_cmd.pad = 0;
1105         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1106                                               sizeof(token_cmd),
1107                                               IXGBE_HI_COMMAND_TIMEOUT,
1108                                               true);
1109         if (status)
1110                 return status;
1111         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1112                 return IXGBE_SUCCESS;
1113         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1114                 return IXGBE_ERR_FW_RESP_INVALID;
1115
1116         return IXGBE_ERR_TOKEN_RETRY;
1117 }
1118
1119 /**
1120  * ixgbe_put_phy_token - Put the token for shared phy access
1121  * @hw: Pointer to hardware structure
1122  */
1123
1124 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1125 {
1126         struct ixgbe_hic_phy_token_req token_cmd;
1127         s32 status;
1128
1129         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1130         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1131         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1132         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1133         token_cmd.port_number = hw->bus.lan_id;
1134         token_cmd.command_type = FW_PHY_TOKEN_REL;
1135         token_cmd.pad = 0;
1136         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1137                                               sizeof(token_cmd),
1138                                               IXGBE_HI_COMMAND_TIMEOUT,
1139                                               true);
1140         if (status)
1141                 return status;
1142         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1143                 return IXGBE_SUCCESS;
1144         return IXGBE_ERR_FW_RESP_INVALID;
1145 }
1146
1147 /**
1148  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1149  *  of the IOSF device
1150  *  @hw: pointer to hardware structure
1151  *  @reg_addr: 32 bit PHY register to write
1152  *  @device_type: 3 bit device type
1153  *  @data: Data to write to the register
1154  **/
1155 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1156                                   u32 device_type, u32 data)
1157 {
1158         struct ixgbe_hic_internal_phy_req write_cmd;
1159         s32 status;
1160         UNREFERENCED_1PARAMETER(device_type);
1161
1162         memset(&write_cmd, 0, sizeof(write_cmd));
1163         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1164         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1165         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1166         write_cmd.port_number = hw->bus.lan_id;
1167         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1168         write_cmd.address = (u16)reg_addr;
1169         write_cmd.write_data = data;
1170
1171         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1172                                               sizeof(write_cmd),
1173                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1174
1175         return status;
1176 }
1177
1178 /**
1179  *  ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
1180  *  of the IOSF device.
1181  *  @hw: pointer to hardware structure
1182  *  @reg_addr: 32 bit PHY register to write
1183  *  @device_type: 3 bit device type
1184  *  @data: Pointer to read data from the register
1185  **/
1186 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1187                                  u32 device_type, u32 *data)
1188 {
1189         struct ixgbe_hic_internal_phy_req read_cmd;
1190         s32 status;
1191         UNREFERENCED_1PARAMETER(device_type);
1192
1193         memset(&read_cmd, 0, sizeof(read_cmd));
1194         read_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1195         read_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1196         read_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1197         read_cmd.port_number = hw->bus.lan_id;
1198         read_cmd.command_type = FW_INT_PHY_REQ_READ;
1199         read_cmd.address = (u16)reg_addr;
1200
1201         status = ixgbe_host_interface_command(hw, (u32 *)&read_cmd,
1202                                               sizeof(read_cmd),
1203                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1204
1205         /* Extract the register value from the response. */
1206         *data = ((struct ixgbe_hic_internal_phy_resp *)&read_cmd)->read_data;
1207
1208         return status;
1209 }
1210
1211 /**
1212  *  ixgbe_disable_mdd_X550
1213  *  @hw: pointer to hardware structure
1214  *
1215  *  Disable malicious driver detection
1216  **/
1217 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1218 {
1219         u32 reg;
1220
1221         DEBUGFUNC("ixgbe_disable_mdd_X550");
1222
1223         /* Disable MDD for TX DMA and interrupt */
1224         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1225         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1226         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1227
1228         /* Disable MDD for RX and interrupt */
1229         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1230         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1231         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1232 }
1233
1234 /**
1235  *  ixgbe_enable_mdd_X550
1236  *  @hw: pointer to hardware structure
1237  *
1238  *  Enable malicious driver detection
1239  **/
1240 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1241 {
1242         u32 reg;
1243
1244         DEBUGFUNC("ixgbe_enable_mdd_X550");
1245
1246         /* Enable MDD for TX DMA and interrupt */
1247         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1248         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1249         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1250
1251         /* Enable MDD for RX and interrupt */
1252         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1253         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1254         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1255 }
1256
1257 /**
1258  *  ixgbe_restore_mdd_vf_X550
1259  *  @hw: pointer to hardware structure
1260  *  @vf: vf index
1261  *
1262  *  Restore VF that was disabled during malicious driver detection event
1263  **/
1264 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1265 {
1266         u32 idx, reg, num_qs, start_q, bitmask;
1267
1268         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1269
1270         /* Map VF to queues */
1271         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1272         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1273         case IXGBE_MRQC_VMDQRT8TCEN:
1274                 num_qs = 8;  /* 16 VFs / pools */
1275                 bitmask = 0x000000FF;
1276                 break;
1277         case IXGBE_MRQC_VMDQRSS32EN:
1278         case IXGBE_MRQC_VMDQRT4TCEN:
1279                 num_qs = 4;  /* 32 VFs / pools */
1280                 bitmask = 0x0000000F;
1281                 break;
1282         default:            /* 64 VFs / pools */
1283                 num_qs = 2;
1284                 bitmask = 0x00000003;
1285                 break;
1286         }
1287         start_q = vf * num_qs;
1288
1289         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1290         idx = start_q / 32;
1291         reg = 0;
1292         reg |= (bitmask << (start_q % 32));
1293         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1294         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1295 }
1296
1297 /**
1298  *  ixgbe_mdd_event_X550
1299  *  @hw: pointer to hardware structure
1300  *  @vf_bitmap: vf bitmap of malicious vfs
1301  *
1302  *  Handle malicious driver detection event.
1303  **/
1304 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1305 {
1306         u32 wqbr;
1307         u32 i, j, reg, q, shift, vf, idx;
1308
1309         DEBUGFUNC("ixgbe_mdd_event_X550");
1310
1311         /* figure out pool size for mapping to vf's */
1312         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1313         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1314         case IXGBE_MRQC_VMDQRT8TCEN:
1315                 shift = 3;  /* 16 VFs / pools */
1316                 break;
1317         case IXGBE_MRQC_VMDQRSS32EN:
1318         case IXGBE_MRQC_VMDQRT4TCEN:
1319                 shift = 2;  /* 32 VFs / pools */
1320                 break;
1321         default:
1322                 shift = 1;  /* 64 VFs / pools */
1323                 break;
1324         }
1325
1326         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1327         for (i = 0; i < 4; i++) {
1328                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1329                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1330
1331                 if (!wqbr)
1332                         continue;
1333
1334                 /* Get malicious queue */
1335                 for (j = 0; j < 32 && wqbr; j++) {
1336
1337                         if (!(wqbr & (1 << j)))
1338                                 continue;
1339
1340                         /* Get queue from bitmask */
1341                         q = j + (i * 32);
1342
1343                         /* Map queue to vf */
1344                         vf = (q >> shift);
1345
1346                         /* Set vf bit in vf_bitmap */
1347                         idx = vf / 32;
1348                         vf_bitmap[idx] |= (1 << (vf % 32));
1349                         wqbr &= ~(1 << j);
1350                 }
1351         }
1352 }
1353
1354 /**
1355  *  ixgbe_get_media_type_X550em - Get media type
1356  *  @hw: pointer to hardware structure
1357  *
1358  *  Returns the media type (fiber, copper, backplane)
1359  */
1360 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1361 {
1362         enum ixgbe_media_type media_type;
1363
1364         DEBUGFUNC("ixgbe_get_media_type_X550em");
1365
1366         /* Detect if there is a copper PHY attached. */
1367         switch (hw->device_id) {
1368         case IXGBE_DEV_ID_X550EM_X_KR:
1369         case IXGBE_DEV_ID_X550EM_X_KX4:
1370         case IXGBE_DEV_ID_X550EM_A_KR:
1371         case IXGBE_DEV_ID_X550EM_A_KR_L:
1372                 media_type = ixgbe_media_type_backplane;
1373                 break;
1374         case IXGBE_DEV_ID_X550EM_X_SFP:
1375         case IXGBE_DEV_ID_X550EM_A_SFP:
1376         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1377         case IXGBE_DEV_ID_X550EM_A_QSFP:
1378         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1379                 media_type = ixgbe_media_type_fiber;
1380                 break;
1381         case IXGBE_DEV_ID_X550EM_X_1G_T:
1382         case IXGBE_DEV_ID_X550EM_X_10G_T:
1383         case IXGBE_DEV_ID_X550EM_A_10G_T:
1384                 media_type = ixgbe_media_type_copper;
1385                 break;
1386         case IXGBE_DEV_ID_X550EM_A_1G_T:
1387         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1388                 media_type = ixgbe_media_type_sgmii;
1389                 hw->phy.type = ixgbe_phy_sgmii;
1390                 break;
1391         default:
1392                 media_type = ixgbe_media_type_unknown;
1393                 break;
1394         }
1395         return media_type;
1396 }
1397
1398 /**
1399  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1400  *  @hw: pointer to hardware structure
1401  *  @linear: true if SFP module is linear
1402  */
1403 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1404 {
1405         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1406
1407         switch (hw->phy.sfp_type) {
1408         case ixgbe_sfp_type_not_present:
1409                 return IXGBE_ERR_SFP_NOT_PRESENT;
1410         case ixgbe_sfp_type_da_cu_core0:
1411         case ixgbe_sfp_type_da_cu_core1:
1412                 *linear = true;
1413                 break;
1414         case ixgbe_sfp_type_srlr_core0:
1415         case ixgbe_sfp_type_srlr_core1:
1416         case ixgbe_sfp_type_da_act_lmt_core0:
1417         case ixgbe_sfp_type_da_act_lmt_core1:
1418         case ixgbe_sfp_type_1g_sx_core0:
1419         case ixgbe_sfp_type_1g_sx_core1:
1420         case ixgbe_sfp_type_1g_lx_core0:
1421         case ixgbe_sfp_type_1g_lx_core1:
1422                 *linear = false;
1423                 break;
1424         case ixgbe_sfp_type_unknown:
1425         case ixgbe_sfp_type_1g_cu_core0:
1426         case ixgbe_sfp_type_1g_cu_core1:
1427         default:
1428                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1429         }
1430
1431         return IXGBE_SUCCESS;
1432 }
1433
1434 /**
1435  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1436  *  @hw: pointer to hardware structure
1437  *
1438  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1439  **/
1440 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1441 {
1442         s32 status;
1443         bool linear;
1444
1445         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1446
1447         status = ixgbe_identify_module_generic(hw);
1448
1449         if (status != IXGBE_SUCCESS)
1450                 return status;
1451
1452         /* Check if SFP module is supported */
1453         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1454
1455         return status;
1456 }
1457
1458 /**
1459  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1460  *  @hw: pointer to hardware structure
1461  */
1462 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1463 {
1464         s32 status;
1465         bool linear;
1466
1467         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1468
1469         /* Check if SFP module is supported */
1470         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1471
1472         if (status != IXGBE_SUCCESS)
1473                 return status;
1474
1475         ixgbe_init_mac_link_ops_X550em(hw);
1476         hw->phy.ops.reset = NULL;
1477
1478         return IXGBE_SUCCESS;
1479 }
1480
1481 /**
1482  * ixgbe_setup_sgmii - Set up link for sgmii
1483  * @hw: pointer to hardware structure
1484  */
1485 static s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1486                              bool autoneg_wait_to_complete)
1487 {
1488         struct ixgbe_mac_info *mac = &hw->mac;
1489         u32 lval, sval;
1490         s32 rc;
1491         UNREFERENCED_2PARAMETER(speed, autoneg_wait_to_complete);
1492
1493         rc = mac->ops.read_iosf_sb_reg(hw,
1494                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1495                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1496         if (rc)
1497                 return rc;
1498
1499         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1500         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1501         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1502         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1503         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1504         rc = mac->ops.write_iosf_sb_reg(hw,
1505                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1506                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1507         if (rc)
1508                 return rc;
1509
1510         rc = mac->ops.read_iosf_sb_reg(hw,
1511                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1512                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1513         if (rc)
1514                 return rc;
1515
1516         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1517         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1518         rc = mac->ops.write_iosf_sb_reg(hw,
1519                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1520                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1521         if (rc)
1522                 return rc;
1523
1524         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1525         rc = mac->ops.write_iosf_sb_reg(hw,
1526                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1527                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1528
1529         return rc;
1530 }
1531
1532 /**
1533  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1534  *  @hw: pointer to hardware structure
1535  */
1536 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1537 {
1538         struct ixgbe_mac_info *mac = &hw->mac;
1539
1540         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1541
1542         switch (hw->mac.ops.get_media_type(hw)) {
1543         case ixgbe_media_type_fiber:
1544                 /* CS4227 does not support autoneg, so disable the laser control
1545                  * functions for SFP+ fiber
1546                  */
1547                 mac->ops.disable_tx_laser = NULL;
1548                 mac->ops.enable_tx_laser = NULL;
1549                 mac->ops.flap_tx_laser = NULL;
1550                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1551                 mac->ops.set_rate_select_speed =
1552                                         ixgbe_set_soft_rate_select_speed;
1553                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1554                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1555                         mac->ops.setup_mac_link =
1556                                 ixgbe_setup_mac_link_sfp_x550a;
1557                 else
1558                         mac->ops.setup_mac_link =
1559                                 ixgbe_setup_mac_link_sfp_x550em;
1560                 break;
1561         case ixgbe_media_type_copper:
1562                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1563                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1564                 break;
1565         case ixgbe_media_type_backplane:
1566                 break;
1567         case ixgbe_media_type_sgmii:
1568                 mac->ops.setup_link = ixgbe_setup_sgmii;
1569                 break;
1570         default:
1571                 break;
1572         }
1573 }
1574
1575 /**
1576  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1577  *  @hw: pointer to hardware structure
1578  *  @speed: pointer to link speed
1579  *  @autoneg: true when autoneg or autotry is enabled
1580  */
1581 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1582                                        ixgbe_link_speed *speed,
1583                                        bool *autoneg)
1584 {
1585         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1586
1587         /* SFP */
1588         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1589
1590                 /* CS4227 SFP must not enable auto-negotiation */
1591                 *autoneg = false;
1592
1593                 /* Check if 1G SFP module. */
1594                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1595                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1596                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1597                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1598                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1599                         return IXGBE_SUCCESS;
1600                 }
1601
1602                 /* Link capabilities are based on SFP */
1603                 if (hw->phy.multispeed_fiber)
1604                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1605                                  IXGBE_LINK_SPEED_1GB_FULL;
1606                 else
1607                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1608         } else {
1609                 switch (hw->phy.type) {
1610                 case ixgbe_phy_m88:
1611                         *speed = IXGBE_LINK_SPEED_100_FULL |
1612                                  IXGBE_LINK_SPEED_1GB_FULL;
1613                         break;
1614                 case ixgbe_phy_sgmii:
1615                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1616                         break;
1617                 default:
1618                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1619                                  IXGBE_LINK_SPEED_1GB_FULL;
1620                         break;
1621                 }
1622                 *autoneg = true;
1623         }
1624
1625         return IXGBE_SUCCESS;
1626 }
1627
1628 /**
1629  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1630  * @hw: pointer to hardware structure
1631  * @lsc: pointer to boolean flag which indicates whether external Base T
1632  *       PHY interrupt is lsc
1633  *
1634  * Determime if external Base T PHY interrupt cause is high temperature
1635  * failure alarm or link status change.
1636  *
1637  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1638  * failure alarm, else return PHY access status.
1639  */
1640 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1641 {
1642         u32 status;
1643         u16 reg;
1644
1645         *lsc = false;
1646
1647         /* Vendor alarm triggered */
1648         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1649                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1650                                       &reg);
1651
1652         if (status != IXGBE_SUCCESS ||
1653             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1654                 return status;
1655
1656         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1657         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1658                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1659                                       &reg);
1660
1661         if (status != IXGBE_SUCCESS ||
1662             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1663             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1664                 return status;
1665
1666         /* Global alarm triggered */
1667         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1668                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1669                                       &reg);
1670
1671         if (status != IXGBE_SUCCESS)
1672                 return status;
1673
1674         /* If high temperature failure, then return over temp error and exit */
1675         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1676                 /* power down the PHY in case the PHY FW didn't already */
1677                 ixgbe_set_copper_phy_power(hw, false);
1678                 return IXGBE_ERR_OVERTEMP;
1679         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1680                 /*  device fault alarm triggered */
1681                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1682                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1683                                           &reg);
1684
1685                 if (status != IXGBE_SUCCESS)
1686                         return status;
1687
1688                 /* if device fault was due to high temp alarm handle and exit */
1689                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1690                         /* power down the PHY in case the PHY FW didn't */
1691                         ixgbe_set_copper_phy_power(hw, false);
1692                         return IXGBE_ERR_OVERTEMP;
1693                 }
1694         }
1695
1696         /* Vendor alarm 2 triggered */
1697         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1698                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1699
1700         if (status != IXGBE_SUCCESS ||
1701             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1702                 return status;
1703
1704         /* link connect/disconnect event occurred */
1705         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1706                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1707
1708         if (status != IXGBE_SUCCESS)
1709                 return status;
1710
1711         /* Indicate LSC */
1712         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1713                 *lsc = true;
1714
1715         return IXGBE_SUCCESS;
1716 }
1717
1718 /**
1719  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1720  * @hw: pointer to hardware structure
1721  *
1722  * Enable link status change and temperature failure alarm for the external
1723  * Base T PHY
1724  *
1725  * Returns PHY access status
1726  */
1727 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1728 {
1729         u32 status;
1730         u16 reg;
1731         bool lsc;
1732
1733         /* Clear interrupt flags */
1734         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1735
1736         /* Enable link status change alarm */
1737         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1738                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1739
1740         if (status != IXGBE_SUCCESS)
1741                 return status;
1742
1743         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1744
1745         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1746                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1747
1748         if (status != IXGBE_SUCCESS)
1749                 return status;
1750
1751         /* Enable high temperature failure and global fault alarms */
1752         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1753                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1754                                       &reg);
1755
1756         if (status != IXGBE_SUCCESS)
1757                 return status;
1758
1759         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1760                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1761
1762         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1763                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1764                                        reg);
1765
1766         if (status != IXGBE_SUCCESS)
1767                 return status;
1768
1769         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1770         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1771                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1772                                       &reg);
1773
1774         if (status != IXGBE_SUCCESS)
1775                 return status;
1776
1777         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1778                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1779
1780         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1781                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1782                                        reg);
1783
1784         if (status != IXGBE_SUCCESS)
1785                 return status;
1786
1787         /* Enable chip-wide vendor alarm */
1788         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1789                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1790                                       &reg);
1791
1792         if (status != IXGBE_SUCCESS)
1793                 return status;
1794
1795         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1796
1797         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1798                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1799                                        reg);
1800
1801         return status;
1802 }
1803
1804 /**
1805  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1806  *  @hw: pointer to hardware structure
1807  *  @speed: link speed
1808  *
1809  *  Configures the integrated KR PHY.
1810  **/
1811 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1812                                        ixgbe_link_speed speed)
1813 {
1814         s32 status;
1815         u32 reg_val;
1816
1817         status = hw->mac.ops.read_iosf_sb_reg(hw,
1818                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1819                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1820         if (status)
1821                 return status;
1822
1823         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1824         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1825                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1826
1827         /* Advertise 10G support. */
1828         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1829                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1830
1831         /* Advertise 1G support. */
1832         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1833                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1834
1835         /* Restart auto-negotiation. */
1836         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1837         status = hw->mac.ops.write_iosf_sb_reg(hw,
1838                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1839                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1840
1841         return status;
1842 }
1843
1844 /**
1845  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
1846  *  @hw: pointer to hardware structure
1847  *
1848  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
1849  *  values.
1850  **/
1851 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
1852 {
1853         /* Save NW management interface connected on board. This is used
1854          * to determine internal PHY mode.
1855          */
1856         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1857
1858         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
1859          * PHY address. This register field was has only been used for X552.
1860          */
1861         if (hw->mac.type == ixgbe_mac_X550EM_a &&
1862             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
1863                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
1864                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
1865                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
1866         }
1867
1868         return IXGBE_SUCCESS;
1869 }
1870
1871 /**
1872  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1873  *  @hw: pointer to hardware structure
1874  *
1875  *  Initialize any function pointers that were not able to be
1876  *  set during init_shared_code because the PHY/SFP type was
1877  *  not known.  Perform the SFP init if necessary.
1878  */
1879 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1880 {
1881         struct ixgbe_phy_info *phy = &hw->phy;
1882         s32 ret_val;
1883
1884         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1885
1886         hw->mac.ops.set_lan_id(hw);
1887
1888         ixgbe_read_mng_if_sel_x550em(hw);
1889
1890         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1891                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1892                 ixgbe_setup_mux_ctl(hw);
1893                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1894         }
1895
1896         /* Identify the PHY or SFP module */
1897         ret_val = phy->ops.identify(hw);
1898         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1899                 return ret_val;
1900
1901         /* Setup function pointers based on detected hardware */
1902         ixgbe_init_mac_link_ops_X550em(hw);
1903         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1904                 phy->ops.reset = NULL;
1905
1906         /* Set functions pointers based on phy type */
1907         switch (hw->phy.type) {
1908         case ixgbe_phy_x550em_kx4:
1909                 phy->ops.setup_link = NULL;
1910                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1911                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1912                 break;
1913         case ixgbe_phy_x550em_kr:
1914                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1915                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1916                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1917                 break;
1918         case ixgbe_phy_x550em_ext_t:
1919                 /* If internal link mode is XFI, then setup iXFI internal link,
1920                  * else setup KR now.
1921                  */
1922                 phy->ops.setup_internal_link =
1923                                               ixgbe_setup_internal_phy_t_x550em;
1924
1925                 /* setup SW LPLU only for first revision of X550EM_x */
1926                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1927                     !(IXGBE_FUSES0_REV_MASK &
1928                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1929                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1930
1931                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1932                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1933                 break;
1934         case ixgbe_phy_sgmii:
1935                 phy->ops.setup_link = NULL;
1936                 break;
1937         case ixgbe_phy_m88:
1938                 break;
1939         default:
1940                 break;
1941         }
1942         return ret_val;
1943 }
1944
1945 /**
1946  * ixgbe_set_mdio_speed - Set MDIO clock speed
1947  *  @hw: pointer to hardware structure
1948  */
1949 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
1950 {
1951         u32 hlreg0;
1952
1953         switch (hw->device_id) {
1954         case IXGBE_DEV_ID_X550EM_X_10G_T:
1955         case IXGBE_DEV_ID_X550EM_A_1G_T:
1956         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1957         case IXGBE_DEV_ID_X550EM_A_10G_T:
1958         case IXGBE_DEV_ID_X550EM_A_SFP:
1959         case IXGBE_DEV_ID_X550EM_A_QSFP:
1960                 /* Config MDIO clock speed before the first MDIO PHY access */
1961                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1962                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1963                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1964                 break;
1965         default:
1966                 break;
1967         }
1968 }
1969
1970 /**
1971  *  ixgbe_reset_hw_X550em - Perform hardware reset
1972  *  @hw: pointer to hardware structure
1973  *
1974  *  Resets the hardware by resetting the transmit and receive units, masks
1975  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1976  *  reset.
1977  */
1978 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1979 {
1980         ixgbe_link_speed link_speed;
1981         s32 status;
1982         u32 ctrl = 0;
1983         u32 i;
1984         bool link_up = false;
1985
1986         DEBUGFUNC("ixgbe_reset_hw_X550em");
1987
1988         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1989         status = hw->mac.ops.stop_adapter(hw);
1990         if (status != IXGBE_SUCCESS)
1991                 return status;
1992
1993         /* flush pending Tx transactions */
1994         ixgbe_clear_tx_pending(hw);
1995
1996         ixgbe_set_mdio_speed(hw);
1997
1998         /* PHY ops must be identified and initialized prior to reset */
1999         status = hw->phy.ops.init(hw);
2000
2001         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2002                 return status;
2003
2004         /* start the external PHY */
2005         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2006                 status = ixgbe_init_ext_t_x550em(hw);
2007                 if (status)
2008                         return status;
2009         }
2010
2011         /* Setup SFP module if there is one present. */
2012         if (hw->phy.sfp_setup_needed) {
2013                 status = hw->mac.ops.setup_sfp(hw);
2014                 hw->phy.sfp_setup_needed = false;
2015         }
2016
2017         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2018                 return status;
2019
2020         /* Reset PHY */
2021         if (!hw->phy.reset_disable && hw->phy.ops.reset)
2022                 hw->phy.ops.reset(hw);
2023
2024 mac_reset_top:
2025         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2026          * If link reset is used when link is up, it might reset the PHY when
2027          * mng is using it.  If link is down or the flag to force full link
2028          * reset is set, then perform link reset.
2029          */
2030         ctrl = IXGBE_CTRL_LNK_RST;
2031         if (!hw->force_full_reset) {
2032                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2033                 if (link_up)
2034                         ctrl = IXGBE_CTRL_RST;
2035         }
2036
2037         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2038         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2039         IXGBE_WRITE_FLUSH(hw);
2040
2041         /* Poll for reset bit to self-clear meaning reset is complete */
2042         for (i = 0; i < 10; i++) {
2043                 usec_delay(1);
2044                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2045                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2046                         break;
2047         }
2048
2049         if (ctrl & IXGBE_CTRL_RST_MASK) {
2050                 status = IXGBE_ERR_RESET_FAILED;
2051                 DEBUGOUT("Reset polling failed to complete.\n");
2052         }
2053
2054         msec_delay(50);
2055
2056         /* Double resets are required for recovery from certain error
2057          * conditions.  Between resets, it is necessary to stall to
2058          * allow time for any pending HW events to complete.
2059          */
2060         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2061                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2062                 goto mac_reset_top;
2063         }
2064
2065         /* Store the permanent mac address */
2066         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2067
2068         /* Store MAC address from RAR0, clear receive address registers, and
2069          * clear the multicast table.  Also reset num_rar_entries to 128,
2070          * since we modify this value when programming the SAN MAC address.
2071          */
2072         hw->mac.num_rar_entries = 128;
2073         hw->mac.ops.init_rx_addrs(hw);
2074
2075         ixgbe_set_mdio_speed(hw);
2076
2077         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2078                 ixgbe_setup_mux_ctl(hw);
2079
2080         return status;
2081 }
2082
2083 /**
2084  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2085  * @hw: pointer to hardware structure
2086  */
2087 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2088 {
2089         u32 status;
2090         u16 reg;
2091
2092         status = hw->phy.ops.read_reg(hw,
2093                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2094                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2095                                       &reg);
2096
2097         if (status != IXGBE_SUCCESS)
2098                 return status;
2099
2100         /* If PHY FW reset completed bit is set then this is the first
2101          * SW instance after a power on so the PHY FW must be un-stalled.
2102          */
2103         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2104                 status = hw->phy.ops.read_reg(hw,
2105                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2106                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2107                                         &reg);
2108
2109                 if (status != IXGBE_SUCCESS)
2110                         return status;
2111
2112                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2113
2114                 status = hw->phy.ops.write_reg(hw,
2115                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2116                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2117                                         reg);
2118
2119                 if (status != IXGBE_SUCCESS)
2120                         return status;
2121         }
2122
2123         return status;
2124 }
2125
2126 /**
2127  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2128  *  @hw: pointer to hardware structure
2129  *
2130  *  Configures the integrated KR PHY for X550EM_x.
2131  **/
2132 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2133 {
2134         if (hw->mac.type != ixgbe_mac_X550EM_x)
2135                 return IXGBE_SUCCESS;
2136
2137         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2138 }
2139
2140 /**
2141  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2142  *  @hw: pointer to hardware structure
2143  *
2144  *  Configure the external PHY and the integrated KR PHY for SFP support.
2145  **/
2146 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2147                                     ixgbe_link_speed speed,
2148                                     bool autoneg_wait_to_complete)
2149 {
2150         s32 ret_val;
2151         u16 reg_slice, reg_val;
2152         bool setup_linear = false;
2153         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2154
2155         /* Check if SFP module is supported and linear */
2156         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2157
2158         /* If no SFP module present, then return success. Return success since
2159          * there is no reason to configure CS4227 and SFP not present error is
2160          * not excepted in the setup MAC link flow.
2161          */
2162         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2163                 return IXGBE_SUCCESS;
2164
2165         if (ret_val != IXGBE_SUCCESS)
2166                 return ret_val;
2167
2168         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2169                 /* Configure CS4227 LINE side to 10G SR. */
2170                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2171                             (hw->bus.lan_id << 12);
2172                 reg_val = IXGBE_CS4227_SPEED_10G;
2173                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2174                                                   reg_val);
2175
2176                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2177                             (hw->bus.lan_id << 12);
2178                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2179                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2180                                                   reg_val);
2181
2182                 /* Configure CS4227 for HOST connection rate then type. */
2183                 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2184                             (hw->bus.lan_id << 12);
2185                 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2186                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2187                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2188                                                   reg_val);
2189
2190                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2191                             (hw->bus.lan_id << 12);
2192                 if (setup_linear)
2193                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2194                 else
2195                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2196                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2197                                                   reg_val);
2198
2199                 /* Setup XFI internal link. */
2200                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2201         } else {
2202                 /* Configure internal PHY for KR/KX. */
2203                 ixgbe_setup_kr_speed_x550em(hw, speed);
2204
2205                 /* Configure CS4227 LINE side to proper mode. */
2206                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2207                             (hw->bus.lan_id << 12);
2208                 if (setup_linear)
2209                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2210                 else
2211                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2212                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2213                                                   reg_val);
2214         }
2215         return ret_val;
2216 }
2217
2218 /**
2219  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2220  *  @hw: pointer to hardware structure
2221  *
2222  *  Configure the the integrated PHY for SFP support.
2223  **/
2224 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2225                                    ixgbe_link_speed speed,
2226                                    bool autoneg_wait_to_complete)
2227 {
2228         s32 ret_val;
2229         u16 reg_phy_ext;
2230         bool setup_linear = false;
2231         u32 reg_slice, reg_phy_int, slice_offset;
2232
2233         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2234
2235         /* Check if SFP module is supported and linear */
2236         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2237
2238         /* If no SFP module present, then return success. Return success since
2239          * SFP not present error is not excepted in the setup MAC link flow.
2240          */
2241         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2242                 return IXGBE_SUCCESS;
2243
2244         if (ret_val != IXGBE_SUCCESS)
2245                 return ret_val;
2246
2247         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2248                 /* Configure internal PHY for native SFI */
2249                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2250                                IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2251                                IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2252
2253                 if (ret_val != IXGBE_SUCCESS)
2254                         return ret_val;
2255
2256                 if (setup_linear) {
2257                         reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2258                         reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2259                 } else {
2260                         reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2261                         reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2262                 }
2263
2264                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2265                                 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2266                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2267
2268                 if (ret_val != IXGBE_SUCCESS)
2269                         return ret_val;
2270
2271                 /* Setup XFI/SFI internal link. */
2272                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2273         } else {
2274                 /* Configure internal PHY for KR/KX. */
2275                 ixgbe_setup_kr_speed_x550em(hw, speed);
2276
2277                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2278                         /* Find Address */
2279                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2280                         return IXGBE_ERR_PHY_ADDR_INVALID;
2281                 }
2282
2283                 /* Get external PHY device id */
2284                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2285                                        IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2286
2287                 if (ret_val != IXGBE_SUCCESS)
2288                         return ret_val;
2289
2290                 /* When configuring quad port CS4223, the MAC instance is part
2291                  * of the slice offset.
2292                  */
2293                 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2294                         slice_offset = (hw->bus.lan_id +
2295                                         (hw->bus.instance_id << 1)) << 12;
2296                 else
2297                         slice_offset = hw->bus.lan_id << 12;
2298
2299                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2300                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2301                 if (setup_linear)
2302                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2303                 else
2304                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2305                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2306                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2307         }
2308         return ret_val;
2309 }
2310
2311 /**
2312  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2313  *  @hw: pointer to hardware structure
2314  *
2315  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2316  **/
2317 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2318 {
2319         s32 status;
2320         u32 reg_val;
2321
2322         /* Disable training protocol FSM. */
2323         status = ixgbe_read_iosf_sb_reg_x550(hw,
2324                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2325                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2326         if (status != IXGBE_SUCCESS)
2327                 return status;
2328         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2329         status = ixgbe_write_iosf_sb_reg_x550(hw,
2330                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2331                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2332         if (status != IXGBE_SUCCESS)
2333                 return status;
2334
2335         /* Disable Flex from training TXFFE. */
2336         status = ixgbe_read_iosf_sb_reg_x550(hw,
2337                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2338                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2339         if (status != IXGBE_SUCCESS)
2340                 return status;
2341         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2342         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2343         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2344         status = ixgbe_write_iosf_sb_reg_x550(hw,
2345                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2346                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2347         if (status != IXGBE_SUCCESS)
2348                 return status;
2349         status = ixgbe_read_iosf_sb_reg_x550(hw,
2350                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2351                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2352         if (status != IXGBE_SUCCESS)
2353                 return status;
2354         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2355         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2356         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2357         status = ixgbe_write_iosf_sb_reg_x550(hw,
2358                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2359                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2360         if (status != IXGBE_SUCCESS)
2361                 return status;
2362
2363         /* Enable override for coefficients. */
2364         status = ixgbe_read_iosf_sb_reg_x550(hw,
2365                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2366                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2367         if (status != IXGBE_SUCCESS)
2368                 return status;
2369         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2370         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2371         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2372         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2373         status = ixgbe_write_iosf_sb_reg_x550(hw,
2374                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2375                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2376         return status;
2377 }
2378
2379 /**
2380  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2381  *  @hw: pointer to hardware structure
2382  *  @speed: the link speed to force
2383  *
2384  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2385  *  internal and external PHY at a specific speed, without autonegotiation.
2386  **/
2387 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2388 {
2389         s32 status;
2390         u32 reg_val;
2391
2392         /* Disable AN and force speed to 10G Serial. */
2393         status = ixgbe_read_iosf_sb_reg_x550(hw,
2394                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2395                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2396         if (status != IXGBE_SUCCESS)
2397                 return status;
2398
2399         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2400         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2401
2402         /* Select forced link speed for internal PHY. */
2403         switch (*speed) {
2404         case IXGBE_LINK_SPEED_10GB_FULL:
2405                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2406                 break;
2407         case IXGBE_LINK_SPEED_1GB_FULL:
2408                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2409                 break;
2410         default:
2411                 /* Other link speeds are not supported by internal KR PHY. */
2412                 return IXGBE_ERR_LINK_SETUP;
2413         }
2414
2415         status = ixgbe_write_iosf_sb_reg_x550(hw,
2416                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2417                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2418         if (status != IXGBE_SUCCESS)
2419                 return status;
2420
2421         /* Additional configuration needed for x550em_x */
2422         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2423                 status = ixgbe_setup_ixfi_x550em_x(hw);
2424                 if (status != IXGBE_SUCCESS)
2425                         return status;
2426         }
2427
2428         /* Toggle port SW reset by AN reset. */
2429         status = ixgbe_read_iosf_sb_reg_x550(hw,
2430                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2431                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2432         if (status != IXGBE_SUCCESS)
2433                 return status;
2434         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2435         status = ixgbe_write_iosf_sb_reg_x550(hw,
2436                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2437                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2438
2439         return status;
2440 }
2441
2442 /**
2443  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2444  * @hw: address of hardware structure
2445  * @link_up: address of boolean to indicate link status
2446  *
2447  * Returns error code if unable to get link status.
2448  */
2449 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2450 {
2451         u32 ret;
2452         u16 autoneg_status;
2453
2454         *link_up = false;
2455
2456         /* read this twice back to back to indicate current status */
2457         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2458                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2459                                    &autoneg_status);
2460         if (ret != IXGBE_SUCCESS)
2461                 return ret;
2462
2463         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2464                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2465                                    &autoneg_status);
2466         if (ret != IXGBE_SUCCESS)
2467                 return ret;
2468
2469         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2470
2471         return IXGBE_SUCCESS;
2472 }
2473
2474 /**
2475  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2476  * @hw: point to hardware structure
2477  *
2478  * Configures the link between the integrated KR PHY and the external X557 PHY
2479  * The driver will call this function when it gets a link status change
2480  * interrupt from the X557 PHY. This function configures the link speed
2481  * between the PHYs to match the link speed of the BASE-T link.
2482  *
2483  * A return of a non-zero value indicates an error, and the base driver should
2484  * not report link up.
2485  */
2486 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2487 {
2488         ixgbe_link_speed force_speed;
2489         bool link_up;
2490         u32 status;
2491         u16 speed;
2492
2493         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2494                 return IXGBE_ERR_CONFIG;
2495
2496         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2497                 /* If link is down, there is no setup necessary so return  */
2498                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2499                 if (status != IXGBE_SUCCESS)
2500                         return status;
2501
2502                 if (!link_up)
2503                         return IXGBE_SUCCESS;
2504
2505                 status = hw->phy.ops.read_reg(hw,
2506                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2507                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2508                                               &speed);
2509                 if (status != IXGBE_SUCCESS)
2510                         return status;
2511
2512                 /* If link is still down - no setup is required so return */
2513                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2514                 if (status != IXGBE_SUCCESS)
2515                         return status;
2516                 if (!link_up)
2517                         return IXGBE_SUCCESS;
2518
2519                 /* clear everything but the speed and duplex bits */
2520                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2521
2522                 switch (speed) {
2523                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2524                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2525                         break;
2526                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2527                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2528                         break;
2529                 default:
2530                         /* Internal PHY does not support anything else */
2531                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
2532                 }
2533
2534                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2535         } else {
2536                 speed = IXGBE_LINK_SPEED_10GB_FULL |
2537                         IXGBE_LINK_SPEED_1GB_FULL;
2538                 return ixgbe_setup_kr_speed_x550em(hw, speed);
2539         }
2540 }
2541
2542 /**
2543  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2544  *  @hw: pointer to hardware structure
2545  *
2546  *  Configures the integrated KR PHY to use internal loopback mode.
2547  **/
2548 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2549 {
2550         s32 status;
2551         u32 reg_val;
2552
2553         /* Disable AN and force speed to 10G Serial. */
2554         status = hw->mac.ops.read_iosf_sb_reg(hw,
2555                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2556                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2557         if (status != IXGBE_SUCCESS)
2558                 return status;
2559         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2560         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2561         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2562         status = hw->mac.ops.write_iosf_sb_reg(hw,
2563                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2564                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2565         if (status != IXGBE_SUCCESS)
2566                 return status;
2567
2568         /* Set near-end loopback clocks. */
2569         status = hw->mac.ops.read_iosf_sb_reg(hw,
2570                       IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2571                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2572         if (status != IXGBE_SUCCESS)
2573                 return status;
2574         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2575         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2576         status = hw->mac.ops.write_iosf_sb_reg(hw,
2577                        IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2578                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2579         if (status != IXGBE_SUCCESS)
2580                 return status;
2581
2582         /* Set loopback enable. */
2583         status = hw->mac.ops.read_iosf_sb_reg(hw,
2584                       IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2585                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2586         if (status != IXGBE_SUCCESS)
2587                 return status;
2588         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2589         status = hw->mac.ops.write_iosf_sb_reg(hw,
2590                        IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2591                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2592         if (status != IXGBE_SUCCESS)
2593                 return status;
2594
2595         /* Training bypass. */
2596         status = hw->mac.ops.read_iosf_sb_reg(hw,
2597                       IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2598                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2599         if (status != IXGBE_SUCCESS)
2600                 return status;
2601         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2602         status = hw->mac.ops.write_iosf_sb_reg(hw,
2603                        IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2604                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2605
2606         return status;
2607 }
2608
2609 /**
2610  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2611  *  assuming that the semaphore is already obtained.
2612  *  @hw: pointer to hardware structure
2613  *  @offset: offset of  word in the EEPROM to read
2614  *  @data: word read from the EEPROM
2615  *
2616  *  Reads a 16 bit word from the EEPROM using the hostif.
2617  **/
2618 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2619                                    u16 *data)
2620 {
2621         s32 status;
2622         struct ixgbe_hic_read_shadow_ram buffer;
2623
2624         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2625         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2626         buffer.hdr.req.buf_lenh = 0;
2627         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2628         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2629
2630         /* convert offset from words to bytes */
2631         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2632         /* one word */
2633         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2634
2635         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2636                                               sizeof(buffer),
2637                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2638
2639         if (status)
2640                 return status;
2641
2642         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2643                                           FW_NVM_DATA_OFFSET);
2644
2645         return 0;
2646 }
2647
2648 /**
2649  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2650  *  @hw: pointer to hardware structure
2651  *  @offset: offset of  word in the EEPROM to read
2652  *  @data: word read from the EEPROM
2653  *
2654  *  Reads a 16 bit word from the EEPROM using the hostif.
2655  **/
2656 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2657                               u16 *data)
2658 {
2659         s32 status = IXGBE_SUCCESS;
2660
2661         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2662
2663         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2664             IXGBE_SUCCESS) {
2665                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2666                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2667         } else {
2668                 status = IXGBE_ERR_SWFW_SYNC;
2669         }
2670
2671         return status;
2672 }
2673
2674 /**
2675  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2676  *  @hw: pointer to hardware structure
2677  *  @offset: offset of  word in the EEPROM to read
2678  *  @words: number of words
2679  *  @data: word(s) read from the EEPROM
2680  *
2681  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
2682  **/
2683 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2684                                      u16 offset, u16 words, u16 *data)
2685 {
2686         struct ixgbe_hic_read_shadow_ram buffer;
2687         u32 current_word = 0;
2688         u16 words_to_read;
2689         s32 status;
2690         u32 i;
2691
2692         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2693
2694         /* Take semaphore for the entire operation. */
2695         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2696         if (status) {
2697                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2698                 return status;
2699         }
2700         while (words) {
2701                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2702                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2703                 else
2704                         words_to_read = words;
2705
2706                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2707                 buffer.hdr.req.buf_lenh = 0;
2708                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2709                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2710
2711                 /* convert offset from words to bytes */
2712                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2713                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2714
2715                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2716                                                       sizeof(buffer),
2717                                                       IXGBE_HI_COMMAND_TIMEOUT,
2718                                                       false);
2719
2720                 if (status) {
2721                         DEBUGOUT("Host interface command failed\n");
2722                         goto out;
2723                 }
2724
2725                 for (i = 0; i < words_to_read; i++) {
2726                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2727                                   2 * i;
2728                         u32 value = IXGBE_READ_REG(hw, reg);
2729
2730                         data[current_word] = (u16)(value & 0xffff);
2731                         current_word++;
2732                         i++;
2733                         if (i < words_to_read) {
2734                                 value >>= 16;
2735                                 data[current_word] = (u16)(value & 0xffff);
2736                                 current_word++;
2737                         }
2738                 }
2739                 words -= words_to_read;
2740         }
2741
2742 out:
2743         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2744         return status;
2745 }
2746
2747 /**
2748  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2749  *  @hw: pointer to hardware structure
2750  *  @offset: offset of  word in the EEPROM to write
2751  *  @data: word write to the EEPROM
2752  *
2753  *  Write a 16 bit word to the EEPROM using the hostif.
2754  **/
2755 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2756                                     u16 data)
2757 {
2758         s32 status;
2759         struct ixgbe_hic_write_shadow_ram buffer;
2760
2761         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2762
2763         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2764         buffer.hdr.req.buf_lenh = 0;
2765         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2766         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2767
2768          /* one word */
2769         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2770         buffer.data = data;
2771         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2772
2773         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2774                                               sizeof(buffer),
2775                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2776
2777         return status;
2778 }
2779
2780 /**
2781  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2782  *  @hw: pointer to hardware structure
2783  *  @offset: offset of  word in the EEPROM to write
2784  *  @data: word write to the EEPROM
2785  *
2786  *  Write a 16 bit word to the EEPROM using the hostif.
2787  **/
2788 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2789                                u16 data)
2790 {
2791         s32 status = IXGBE_SUCCESS;
2792
2793         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2794
2795         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2796             IXGBE_SUCCESS) {
2797                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2798                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2799         } else {
2800                 DEBUGOUT("write ee hostif failed to get semaphore");
2801                 status = IXGBE_ERR_SWFW_SYNC;
2802         }
2803
2804         return status;
2805 }
2806
2807 /**
2808  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2809  *  @hw: pointer to hardware structure
2810  *  @offset: offset of  word in the EEPROM to write
2811  *  @words: number of words
2812  *  @data: word(s) write to the EEPROM
2813  *
2814  *  Write a 16 bit word(s) to the EEPROM using the hostif.
2815  **/
2816 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2817                                       u16 offset, u16 words, u16 *data)
2818 {
2819         s32 status = IXGBE_SUCCESS;
2820         u32 i = 0;
2821
2822         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2823
2824         /* Take semaphore for the entire operation. */
2825         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2826         if (status != IXGBE_SUCCESS) {
2827                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2828                 goto out;
2829         }
2830
2831         for (i = 0; i < words; i++) {
2832                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2833                                                          data[i]);
2834
2835                 if (status != IXGBE_SUCCESS) {
2836                         DEBUGOUT("Eeprom buffered write failed\n");
2837                         break;
2838                 }
2839         }
2840
2841         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2842 out:
2843
2844         return status;
2845 }
2846
2847 /**
2848  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2849  * @hw: pointer to hardware structure
2850  * @ptr: pointer offset in eeprom
2851  * @size: size of section pointed by ptr, if 0 first word will be used as size
2852  * @csum: address of checksum to update
2853  *
2854  * Returns error status for any failure
2855  */
2856 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2857                                    u16 size, u16 *csum, u16 *buffer,
2858                                    u32 buffer_size)
2859 {
2860         u16 buf[256];
2861         s32 status;
2862         u16 length, bufsz, i, start;
2863         u16 *local_buffer;
2864
2865         bufsz = sizeof(buf) / sizeof(buf[0]);
2866
2867         /* Read a chunk at the pointer location */
2868         if (!buffer) {
2869                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2870                 if (status) {
2871                         DEBUGOUT("Failed to read EEPROM image\n");
2872                         return status;
2873                 }
2874                 local_buffer = buf;
2875         } else {
2876                 if (buffer_size < ptr)
2877                         return  IXGBE_ERR_PARAM;
2878                 local_buffer = &buffer[ptr];
2879         }
2880
2881         if (size) {
2882                 start = 0;
2883                 length = size;
2884         } else {
2885                 start = 1;
2886                 length = local_buffer[0];
2887
2888                 /* Skip pointer section if length is invalid. */
2889                 if (length == 0xFFFF || length == 0 ||
2890                     (ptr + length) >= hw->eeprom.word_size)
2891                         return IXGBE_SUCCESS;
2892         }
2893
2894         if (buffer && ((u32)start + (u32)length > buffer_size))
2895                 return IXGBE_ERR_PARAM;
2896
2897         for (i = start; length; i++, length--) {
2898                 if (i == bufsz && !buffer) {
2899                         ptr += bufsz;
2900                         i = 0;
2901                         if (length < bufsz)
2902                                 bufsz = length;
2903
2904                         /* Read a chunk at the pointer location */
2905                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2906                                                                   bufsz, buf);
2907                         if (status) {
2908                                 DEBUGOUT("Failed to read EEPROM image\n");
2909                                 return status;
2910                         }
2911                 }
2912                 *csum += local_buffer[i];
2913         }
2914         return IXGBE_SUCCESS;
2915 }
2916
2917 /**
2918  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2919  *  @hw: pointer to hardware structure
2920  *  @buffer: pointer to buffer containing calculated checksum
2921  *  @buffer_size: size of buffer
2922  *
2923  *  Returns a negative error code on error, or the 16-bit checksum
2924  **/
2925 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2926 {
2927         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2928         u16 *local_buffer;
2929         s32 status;
2930         u16 checksum = 0;
2931         u16 pointer, i, size;
2932
2933         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2934
2935         hw->eeprom.ops.init_params(hw);
2936
2937         if (!buffer) {
2938                 /* Read pointer area */
2939                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2940                                                      IXGBE_EEPROM_LAST_WORD + 1,
2941                                                      eeprom_ptrs);
2942                 if (status) {
2943                         DEBUGOUT("Failed to read EEPROM image\n");
2944                         return status;
2945                 }
2946                 local_buffer = eeprom_ptrs;
2947         } else {
2948                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2949                         return IXGBE_ERR_PARAM;
2950                 local_buffer = buffer;
2951         }
2952
2953         /*
2954          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2955          * checksum word itself
2956          */
2957         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2958                 if (i != IXGBE_EEPROM_CHECKSUM)
2959                         checksum += local_buffer[i];
2960
2961         /*
2962          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2963          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2964          */
2965         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2966                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2967                         continue;
2968
2969                 pointer = local_buffer[i];
2970
2971                 /* Skip pointer section if the pointer is invalid. */
2972                 if (pointer == 0xFFFF || pointer == 0 ||
2973                     pointer >= hw->eeprom.word_size)
2974                         continue;
2975
2976                 switch (i) {
2977                 case IXGBE_PCIE_GENERAL_PTR:
2978                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2979                         break;
2980                 case IXGBE_PCIE_CONFIG0_PTR:
2981                 case IXGBE_PCIE_CONFIG1_PTR:
2982                         size = IXGBE_PCIE_CONFIG_SIZE;
2983                         break;
2984                 default:
2985                         size = 0;
2986                         break;
2987                 }
2988
2989                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2990                                                 buffer, buffer_size);
2991                 if (status)
2992                         return status;
2993         }
2994
2995         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2996
2997         return (s32)checksum;
2998 }
2999
3000 /**
3001  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3002  *  @hw: pointer to hardware structure
3003  *
3004  *  Returns a negative error code on error, or the 16-bit checksum
3005  **/
3006 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3007 {
3008         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3009 }
3010
3011 /**
3012  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3013  *  @hw: pointer to hardware structure
3014  *  @checksum_val: calculated checksum
3015  *
3016  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3017  *  caller does not need checksum_val, the value can be NULL.
3018  **/
3019 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3020 {
3021         s32 status;
3022         u16 checksum;
3023         u16 read_checksum = 0;
3024
3025         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3026
3027         /* Read the first word from the EEPROM. If this times out or fails, do
3028          * not continue or we could be in for a very long wait while every
3029          * EEPROM read fails
3030          */
3031         status = hw->eeprom.ops.read(hw, 0, &checksum);
3032         if (status) {
3033                 DEBUGOUT("EEPROM read failed\n");
3034                 return status;
3035         }
3036
3037         status = hw->eeprom.ops.calc_checksum(hw);
3038         if (status < 0)
3039                 return status;
3040
3041         checksum = (u16)(status & 0xffff);
3042
3043         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3044                                            &read_checksum);
3045         if (status)
3046                 return status;
3047
3048         /* Verify read checksum from EEPROM is the same as
3049          * calculated checksum
3050          */
3051         if (read_checksum != checksum) {
3052                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3053                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3054                              "Invalid EEPROM checksum");
3055         }
3056
3057         /* If the user cares, return the calculated checksum */
3058         if (checksum_val)
3059                 *checksum_val = checksum;
3060
3061         return status;
3062 }
3063
3064 /**
3065  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3066  * @hw: pointer to hardware structure
3067  *
3068  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3069  * checksum and updates the EEPROM and instructs the hardware to update
3070  * the flash.
3071  **/
3072 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3073 {
3074         s32 status;
3075         u16 checksum = 0;
3076
3077         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3078
3079         /* Read the first word from the EEPROM. If this times out or fails, do
3080          * not continue or we could be in for a very long wait while every
3081          * EEPROM read fails
3082          */
3083         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3084         if (status) {
3085                 DEBUGOUT("EEPROM read failed\n");
3086                 return status;
3087         }
3088
3089         status = ixgbe_calc_eeprom_checksum_X550(hw);
3090         if (status < 0)
3091                 return status;
3092
3093         checksum = (u16)(status & 0xffff);
3094
3095         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3096                                             checksum);
3097         if (status)
3098                 return status;
3099
3100         status = ixgbe_update_flash_X550(hw);
3101
3102         return status;
3103 }
3104
3105 /**
3106  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3107  *  @hw: pointer to hardware structure
3108  *
3109  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3110  **/
3111 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3112 {
3113         s32 status = IXGBE_SUCCESS;
3114         union ixgbe_hic_hdr2 buffer;
3115
3116         DEBUGFUNC("ixgbe_update_flash_X550");
3117
3118         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3119         buffer.req.buf_lenh = 0;
3120         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3121         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3122
3123         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3124                                               sizeof(buffer),
3125                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3126
3127         return status;
3128 }
3129
3130 /**
3131  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3132  *  @hw: pointer to hardware structure
3133  *
3134  *  Determines physical layer capabilities of the current configuration.
3135  **/
3136 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3137 {
3138         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3139         u16 ext_ability = 0;
3140
3141         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3142
3143         hw->phy.ops.identify(hw);
3144
3145         switch (hw->phy.type) {
3146         case ixgbe_phy_x550em_kr:
3147                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3148                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3149                 break;
3150         case ixgbe_phy_x550em_kx4:
3151                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3152                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3153                 break;
3154         case ixgbe_phy_x550em_ext_t:
3155                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3156                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3157                                      &ext_ability);
3158                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3159                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3160                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3161                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3162                 break;
3163         default:
3164                 break;
3165         }
3166
3167         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3168                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3169
3170         return physical_layer;
3171 }
3172
3173 /**
3174  * ixgbe_get_bus_info_x550em - Set PCI bus info
3175  * @hw: pointer to hardware structure
3176  *
3177  * Sets bus link width and speed to unknown because X550em is
3178  * not a PCI device.
3179  **/
3180 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3181 {
3182
3183         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3184
3185         hw->bus.width = ixgbe_bus_width_unknown;
3186         hw->bus.speed = ixgbe_bus_speed_unknown;
3187
3188         hw->mac.ops.set_lan_id(hw);
3189
3190         return IXGBE_SUCCESS;
3191 }
3192
3193 /**
3194  * ixgbe_disable_rx_x550 - Disable RX unit
3195  *
3196  * Enables the Rx DMA unit for x550
3197  **/
3198 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3199 {
3200         u32 rxctrl, pfdtxgswc;
3201         s32 status;
3202         struct ixgbe_hic_disable_rxen fw_cmd;
3203
3204         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3205
3206         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3207         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3208                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3209                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3210                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3211                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3212                         hw->mac.set_lben = true;
3213                 } else {
3214                         hw->mac.set_lben = false;
3215                 }
3216
3217                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3218                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3219                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3220                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3221
3222                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3223                                         sizeof(struct ixgbe_hic_disable_rxen),
3224                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3225
3226                 /* If we fail - disable RX using register write */
3227                 if (status) {
3228                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3229                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3230                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3231                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3232                         }
3233                 }
3234         }
3235 }
3236
3237 /**
3238  * ixgbe_enter_lplu_x550em - Transition to low power states
3239  *  @hw: pointer to hardware structure
3240  *
3241  * Configures Low Power Link Up on transition to low power states
3242  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3243  * X557 PHY immediately prior to entering LPLU.
3244  **/
3245 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3246 {
3247         u16 an_10g_cntl_reg, autoneg_reg, speed;
3248         s32 status;
3249         ixgbe_link_speed lcd_speed;
3250         u32 save_autoneg;
3251         bool link_up;
3252
3253         /* SW LPLU not required on later HW revisions. */
3254         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3255             (IXGBE_FUSES0_REV_MASK &
3256              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3257                 return IXGBE_SUCCESS;
3258
3259         /* If blocked by MNG FW, then don't restart AN */
3260         if (ixgbe_check_reset_blocked(hw))
3261                 return IXGBE_SUCCESS;
3262
3263         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3264         if (status != IXGBE_SUCCESS)
3265                 return status;
3266
3267         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3268
3269         if (status != IXGBE_SUCCESS)
3270                 return status;
3271
3272         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3273          * disabled, then force link down by entering low power mode.
3274          */
3275         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3276             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3277                 return ixgbe_set_copper_phy_power(hw, FALSE);
3278
3279         /* Determine LCD */
3280         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3281
3282         if (status != IXGBE_SUCCESS)
3283                 return status;
3284
3285         /* If no valid LCD link speed, then force link down and exit. */
3286         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3287                 return ixgbe_set_copper_phy_power(hw, FALSE);
3288
3289         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3290                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3291                                       &speed);
3292
3293         if (status != IXGBE_SUCCESS)
3294                 return status;
3295
3296         /* If no link now, speed is invalid so take link down */
3297         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3298         if (status != IXGBE_SUCCESS)
3299                 return ixgbe_set_copper_phy_power(hw, false);
3300
3301         /* clear everything but the speed bits */
3302         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3303
3304         /* If current speed is already LCD, then exit. */
3305         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3306              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3307             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3308              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3309                 return status;
3310
3311         /* Clear AN completed indication */
3312         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3313                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3314                                       &autoneg_reg);
3315
3316         if (status != IXGBE_SUCCESS)
3317                 return status;
3318
3319         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3320                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3321                              &an_10g_cntl_reg);
3322
3323         if (status != IXGBE_SUCCESS)
3324                 return status;
3325
3326         status = hw->phy.ops.read_reg(hw,
3327                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3328                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3329                              &autoneg_reg);
3330
3331         if (status != IXGBE_SUCCESS)
3332                 return status;
3333
3334         save_autoneg = hw->phy.autoneg_advertised;
3335
3336         /* Setup link at least common link speed */
3337         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3338
3339         /* restore autoneg from before setting lplu speed */
3340         hw->phy.autoneg_advertised = save_autoneg;
3341
3342         return status;
3343 }
3344
3345 /**
3346  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3347  *  @hw: pointer to hardware structure
3348  *  @lcd_speed: pointer to lowest common link speed
3349  *
3350  * Determine lowest common link speed with link partner.
3351  **/
3352 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3353 {
3354         u16 an_lp_status;
3355         s32 status;
3356         u16 word = hw->eeprom.ctrl_word_3;
3357
3358         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3359
3360         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3361                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3362                                       &an_lp_status);
3363
3364         if (status != IXGBE_SUCCESS)
3365                 return status;
3366
3367         /* If link partner advertised 1G, return 1G */
3368         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3369                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3370                 return status;
3371         }
3372
3373         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3374         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3375             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3376                 return status;
3377
3378         /* Link partner not capable of lower speeds, return 10G */
3379         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3380         return status;
3381 }
3382
3383 /**
3384  *  ixgbe_setup_fc_X550em - Set up flow control
3385  *  @hw: pointer to hardware structure
3386  *
3387  *  Called at init time to set up flow control.
3388  **/
3389 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3390 {
3391         s32 ret_val = IXGBE_SUCCESS;
3392         u32 pause, asm_dir, reg_val;
3393
3394         DEBUGFUNC("ixgbe_setup_fc_X550em");
3395
3396         /* Validate the requested mode */
3397         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3398                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3399                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3400                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3401                 goto out;
3402         }
3403
3404         /* 10gig parts do not have a word in the EEPROM to determine the
3405          * default flow control setting, so we explicitly set it to full.
3406          */
3407         if (hw->fc.requested_mode == ixgbe_fc_default)
3408                 hw->fc.requested_mode = ixgbe_fc_full;
3409
3410         /* Determine PAUSE and ASM_DIR bits. */
3411         switch (hw->fc.requested_mode) {
3412         case ixgbe_fc_none:
3413                 pause = 0;
3414                 asm_dir = 0;
3415                 break;
3416         case ixgbe_fc_tx_pause:
3417                 pause = 0;
3418                 asm_dir = 1;
3419                 break;
3420         case ixgbe_fc_rx_pause:
3421                 /* Rx Flow control is enabled and Tx Flow control is
3422                  * disabled by software override. Since there really
3423                  * isn't a way to advertise that we are capable of RX
3424                  * Pause ONLY, we will advertise that we support both
3425                  * symmetric and asymmetric Rx PAUSE, as such we fall
3426                  * through to the fc_full statement.  Later, we will
3427                  * disable the adapter's ability to send PAUSE frames.
3428                  */
3429         case ixgbe_fc_full:
3430                 pause = 1;
3431                 asm_dir = 1;
3432                 break;
3433         default:
3434                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3435                         "Flow control param set incorrectly\n");
3436                 ret_val = IXGBE_ERR_CONFIG;
3437                 goto out;
3438         }
3439
3440         switch (hw->device_id) {
3441         case IXGBE_DEV_ID_X550EM_X_KR:
3442         case IXGBE_DEV_ID_X550EM_A_KR:
3443         case IXGBE_DEV_ID_X550EM_A_KR_L:
3444                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3445                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3446                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3447                 if (ret_val != IXGBE_SUCCESS)
3448                         goto out;
3449                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3450                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3451                 if (pause)
3452                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3453                 if (asm_dir)
3454                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3455                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3456                                        IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3457                                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3458
3459                 /* This device does not fully support AN. */
3460                 hw->fc.disable_fc_autoneg = true;
3461                 break;
3462         default:
3463                 break;
3464         }
3465
3466 out:
3467         return ret_val;
3468 }
3469
3470 /**
3471  * ixgbe_set_mux - Set mux for port 1 access with CS4227
3472  * @hw: pointer to hardware structure
3473  * @state: set mux if 1, clear if 0
3474  */
3475 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3476 {
3477         u32 esdp;
3478
3479         if (!hw->bus.lan_id)
3480                 return;
3481         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3482         if (state)
3483                 esdp |= IXGBE_ESDP_SDP1;
3484         else
3485                 esdp &= ~IXGBE_ESDP_SDP1;
3486         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3487         IXGBE_WRITE_FLUSH(hw);
3488 }
3489
3490 /**
3491  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3492  *  @hw: pointer to hardware structure
3493  *  @mask: Mask to specify which semaphore to acquire
3494  *
3495  *  Acquires the SWFW semaphore and sets the I2C MUX
3496  **/
3497 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3498 {
3499         s32 status;
3500
3501         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
3502
3503         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3504         if (status)
3505                 return status;
3506
3507         if (mask & IXGBE_GSSR_I2C_MASK)
3508                 ixgbe_set_mux(hw, 1);
3509
3510         return IXGBE_SUCCESS;
3511 }
3512
3513 /**
3514  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3515  *  @hw: pointer to hardware structure
3516  *  @mask: Mask to specify which semaphore to release
3517  *
3518  *  Releases the SWFW semaphore and sets the I2C MUX
3519  **/
3520 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3521 {
3522         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3523
3524         if (mask & IXGBE_GSSR_I2C_MASK)
3525                 ixgbe_set_mux(hw, 0);
3526
3527         ixgbe_release_swfw_sync_X540(hw, mask);
3528 }
3529
3530 /**
3531  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
3532  *  @hw: pointer to hardware structure
3533  *  @mask: Mask to specify which semaphore to acquire
3534  *
3535  *  Acquires the SWFW semaphore and get the shared phy token as needed
3536  */
3537 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3538 {
3539         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3540         int retries = FW_PHY_TOKEN_RETRIES;
3541         s32 status = IXGBE_SUCCESS;
3542
3543         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
3544
3545         while (--retries) {
3546                 status = IXGBE_SUCCESS;
3547                 if (hmask)
3548                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3549                 if (status)
3550                         return status;
3551                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3552                         return IXGBE_SUCCESS;
3553
3554                 status = ixgbe_get_phy_token(hw);
3555                 if (status == IXGBE_SUCCESS)
3556                         return IXGBE_SUCCESS;
3557
3558                 if (hmask)
3559                         ixgbe_release_swfw_sync_X540(hw, hmask);
3560                 if (status != IXGBE_ERR_TOKEN_RETRY)
3561                         return status;
3562                 msec_delay(FW_PHY_TOKEN_DELAY);
3563         }
3564
3565         return status;
3566 }
3567
3568 /**
3569  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
3570  *  @hw: pointer to hardware structure
3571  *  @mask: Mask to specify which semaphore to release
3572  *
3573  *  Releases the SWFW semaphore and puts the shared phy token as needed
3574  */
3575 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3576 {
3577         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3578
3579         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
3580
3581         if (mask & IXGBE_GSSR_TOKEN_SM)
3582                 ixgbe_put_phy_token(hw);
3583
3584         if (hmask)
3585                 ixgbe_release_swfw_sync_X540(hw, hmask);
3586 }
3587
3588 /**
3589  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
3590  * @hw: pointer to hardware structure
3591  *
3592  * Handle external Base T PHY interrupt. If high temperature
3593  * failure alarm then return error, else if link status change
3594  * then setup internal/external PHY link
3595  *
3596  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
3597  * failure alarm, else return PHY access status.
3598  */
3599 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
3600 {
3601         bool lsc;
3602         u32 status;
3603
3604         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
3605
3606         if (status != IXGBE_SUCCESS)
3607                 return status;
3608
3609         if (lsc)
3610                 return ixgbe_setup_internal_phy(hw);
3611
3612         return IXGBE_SUCCESS;
3613 }
3614
3615 /**
3616  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
3617  * @hw: pointer to hardware structure
3618  * @speed: new link speed
3619  * @autoneg_wait_to_complete: true when waiting for completion is needed
3620  *
3621  * Setup internal/external PHY link speed based on link speed, then set
3622  * external PHY auto advertised link speed.
3623  *
3624  * Returns error status for any failure
3625  **/
3626 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3627                                   ixgbe_link_speed speed,
3628                                   bool autoneg_wait_to_complete)
3629 {
3630         s32 status;
3631         ixgbe_link_speed force_speed;
3632
3633         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3634
3635         /* Setup internal/external PHY link speed to iXFI (10G), unless
3636          * only 1G is auto advertised then setup KX link.
3637          */
3638         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3639                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3640         else
3641                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3642
3643         /* If internal link mode is XFI, then setup XFI internal link. */
3644         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3645                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3646
3647                 if (status != IXGBE_SUCCESS)
3648                         return status;
3649         }
3650
3651         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3652 }
3653
3654 /**
3655  * ixgbe_check_link_t_X550em - Determine link and speed status
3656  * @hw: pointer to hardware structure
3657  * @speed: pointer to link speed
3658  * @link_up: true when link is up
3659  * @link_up_wait_to_complete: bool used to wait for link up or not
3660  *
3661  * Check that both the MAC and X557 external PHY have link.
3662  **/
3663 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3664                               bool *link_up, bool link_up_wait_to_complete)
3665 {
3666         u32 status;
3667         u16 autoneg_status;
3668
3669         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3670                 return IXGBE_ERR_CONFIG;
3671
3672         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3673                                               link_up_wait_to_complete);
3674
3675         /* If check link fails or MAC link is not up, then return */
3676         if (status != IXGBE_SUCCESS || !(*link_up))
3677                 return status;
3678
3679         /* MAC link is up, so check external PHY link.
3680          * Read this twice back to back to indicate current status.
3681          */
3682         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3683                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3684                                       &autoneg_status);
3685
3686         if (status != IXGBE_SUCCESS)
3687                 return status;
3688
3689         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3690                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3691                                       &autoneg_status);
3692
3693         if (status != IXGBE_SUCCESS)
3694                 return status;
3695
3696         /* If external PHY link is not up, then indicate link not up */
3697         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3698                 *link_up = false;
3699
3700         return IXGBE_SUCCESS;
3701 }
3702
3703 /**
3704  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3705  *  @hw: pointer to hardware structure
3706  **/
3707 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3708 {
3709         s32 status;
3710
3711         status = ixgbe_reset_phy_generic(hw);
3712
3713         if (status != IXGBE_SUCCESS)
3714                 return status;
3715
3716         /* Configure Link Status Alarm and Temperature Threshold interrupts */
3717         return ixgbe_enable_lasi_ext_t_x550em(hw);
3718 }
3719
3720 /**
3721  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
3722  *  @hw: pointer to hardware structure
3723  *  @led_idx: led number to turn on
3724  **/
3725 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3726 {
3727         u16 phy_data;
3728
3729         DEBUGFUNC("ixgbe_led_on_t_X550em");
3730
3731         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3732                 return IXGBE_ERR_PARAM;
3733
3734         /* To turn on the LED, set mode to ON. */
3735         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3736                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3737         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3738         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3739                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3740
3741         return IXGBE_SUCCESS;
3742 }
3743
3744 /**
3745  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3746  *  @hw: pointer to hardware structure
3747  *  @led_idx: led number to turn off
3748  **/
3749 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3750 {
3751         u16 phy_data;
3752
3753         DEBUGFUNC("ixgbe_led_off_t_X550em");
3754
3755         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3756                 return IXGBE_ERR_PARAM;
3757
3758         /* To turn on the LED, set mode to ON. */
3759         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3760                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3761         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3762         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3763                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3764
3765         return IXGBE_SUCCESS;
3766 }
3767