drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41
  42 /**
  43  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  44  *  @hw: pointer to hardware structure
  45  *
  46  *  Initialize the function pointers and assign the MAC type for X550.
  47  *  Does not touch the hardware.
  48  **/
  49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  50 {
  51         struct ixgbe_mac_info *mac = &hw->mac;
  52         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  53         s32 ret_val;
  54
  55         DEBUGFUNC("ixgbe_init_ops_X550");
  56
  57         ret_val = ixgbe_init_ops_X540(hw);
  58         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  59         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  60         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  61         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  62         mac->ops.set_source_address_pruning =
  63                         ixgbe_set_source_address_pruning_X550;
  64         mac->ops.set_ethertype_anti_spoofing =
  65                         ixgbe_set_ethertype_anti_spoofing_X550;
  66
  67         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  68         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  69         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  70         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  71         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  72         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  73         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  74         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  75         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  76
  77         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  78         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  79         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  80         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  81         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  82         return ret_val;
  83 }
  84
  85 /**
  86  * ixgbe_read_cs4227 - Read CS4227 register
  87  * @hw: pointer to hardware structure
  88  * @reg: register number to write
  89  * @value: pointer to receive value read
  90  *
  91  * Returns status code
  92  **/
  93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  94 {
  95         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
  96 }
  97
  98 /**
  99  * ixgbe_write_cs4227 - Write CS4227 register
 100  * @hw: pointer to hardware structure
 101  * @reg: register number to write
 102  * @value: value to write to register
 103  *
 104  * Returns status code
 105  **/
 106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 107 {
 108         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 109 }
 110
 111 /**
 112  * ixgbe_get_cs4227_status - Return CS4227 status
 113  * @hw: pointer to hardware structure
 114  *
 115  * Returns error if CS4227 not successfully initialized
 116  **/
 117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
 118 {
 119         s32 status;
 120         u16 value = 0;
 121         u8 retry;
 122
 123         for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
 124                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
 125                                            &value);
 126                 if (status != IXGBE_SUCCESS)
 127                         return status;
 128                 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
 129                         break;
 130                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 131         }
 132         if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
 133                 return IXGBE_ERR_PHY;
 134
 135         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 136                                     IXGBE_CS4227_SCRATCH_VALUE);
 137         if (status != IXGBE_SUCCESS)
 138                 return status;
 139         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 140         if (status != IXGBE_SUCCESS)
 141                 return status;
 142         if (value != IXGBE_CS4227_SCRATCH_VALUE)
 143                 return IXGBE_ERR_PHY;
 144         return IXGBE_SUCCESS;
 145 }
 146
 147 /**
 148  * ixgbe_read_pe - Read register from port expander
 149  * @hw: pointer to hardware structure
 150  * @reg: register number to read
 151  * @value: pointer to receive read value
 152  *
 153  * Returns status code
 154  **/
 155 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 156 {
 157         s32 status;
 158
 159         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 160         if (status != IXGBE_SUCCESS)
 161                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 162                               "port expander access failed with %d\n", status);
 163         return status;
 164 }
 165
 166 /**
 167  * ixgbe_write_pe - Write register to port expander
 168  * @hw: pointer to hardware structure
 169  * @reg: register number to write
 170  * @value: value to write
 171  *
 172  * Returns status code
 173  **/
 174 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 175 {
 176         s32 status;
 177
 178         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 179         if (status != IXGBE_SUCCESS)
 180                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 181                               "port expander access failed with %d\n", status);
 182         return status;
 183 }
 184
 185 /**
 186  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 187  * @hw: pointer to hardware structure
 188  *
 189  * Returns error code
 190  **/
 191 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 192 {
 193         s32 status;
 194         u8 reg;
 195
 196         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199         reg |= IXGBE_PE_BIT1;
 200         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 201         if (status != IXGBE_SUCCESS)
 202                 return status;
 203
 204         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 205         if (status != IXGBE_SUCCESS)
 206                 return status;
 207         reg &= ~IXGBE_PE_BIT1;
 208         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 209         if (status != IXGBE_SUCCESS)
 210                 return status;
 211
 212         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 213         if (status != IXGBE_SUCCESS)
 214                 return status;
 215         reg &= ~IXGBE_PE_BIT1;
 216         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 217         if (status != IXGBE_SUCCESS)
 218                 return status;
 219
 220         usec_delay(IXGBE_CS4227_RESET_HOLD);
 221
 222         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 223         if (status != IXGBE_SUCCESS)
 224                 return status;
 225         reg |= IXGBE_PE_BIT1;
 226         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 227         if (status != IXGBE_SUCCESS)
 228                 return status;
 229
 230         msec_delay(IXGBE_CS4227_RESET_DELAY);
 231
 232         return IXGBE_SUCCESS;
 233 }
 234
 235 /**
 236  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 237  * @hw: pointer to hardware structure
 238  **/
 239 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 240 {
 241         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 242         s32 status;
 243         u8 retry;
 244
 245         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 246                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 247                 if (status != IXGBE_SUCCESS) {
 248                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 249                                       "semaphore failed with %d\n", status);
 250                         return;
 251                 }
 252                 status = ixgbe_get_cs4227_status(hw);
 253                 if (status == IXGBE_SUCCESS) {
 254                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 255                         msec_delay(hw->eeprom.semaphore_delay);
 256                         return;
 257                 }
 258                 ixgbe_reset_cs4227(hw);
 259                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 260                 msec_delay(hw->eeprom.semaphore_delay);
 261         }
 262         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 263                       "Unable to initialize CS4227, err=%d\n", status);
 264 }
 265
 266 /**
 267  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 268  * @hw: pointer to hardware structure
 269  **/
 270 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 271 {
 272         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 273
 274         if (hw->bus.lan_id) {
 275                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 276                 esdp |= IXGBE_ESDP_SDP1_DIR;
 277         }
 278         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 279         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 280         IXGBE_WRITE_FLUSH(hw);
 281 }
 282
 283 /**
 284  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 285  * @hw: pointer to hardware structure
 286  *
 287  * Returns error code
 288  */
 289 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 290 {
 291         switch (hw->device_id) {
 292         case IXGBE_DEV_ID_X550EM_X_SFP:
 293                 /* set up for CS4227 usage */
 294                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 295                 ixgbe_setup_mux_ctl(hw);
 296                 ixgbe_check_cs4227(hw);
 297
 298                 return ixgbe_identify_module_generic(hw);
 299                 break;
 300         case IXGBE_DEV_ID_X550EM_X_KX4:
 301                 hw->phy.type = ixgbe_phy_x550em_kx4;
 302                 break;
 303         case IXGBE_DEV_ID_X550EM_X_KR:
 304                 hw->phy.type = ixgbe_phy_x550em_kr;
 305                 break;
 306         case IXGBE_DEV_ID_X550EM_X_1G_T:
 307         case IXGBE_DEV_ID_X550EM_X_10G_T:
 308                 return ixgbe_identify_phy_generic(hw);
 309         default:
 310                 break;
 311         }
 312         return IXGBE_SUCCESS;
 313 }
 314
 315 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 316                                      u32 device_type, u16 *phy_data)
 317 {
 318         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 319         return IXGBE_NOT_IMPLEMENTED;
 320 }
 321
 322 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 323                                       u32 device_type, u16 phy_data)
 324 {
 325         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 326         return IXGBE_NOT_IMPLEMENTED;
 327 }
 328
 329 /**
 330 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 331 *  @hw: pointer to hardware structure
 332 *
 333 *  Initialize the function pointers and for MAC type X550EM.
 334 *  Does not touch the hardware.
 335 **/
 336 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 337 {
 338         struct ixgbe_mac_info *mac = &hw->mac;
 339         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 340         struct ixgbe_phy_info *phy = &hw->phy;
 341         s32 ret_val;
 342
 343         DEBUGFUNC("ixgbe_init_ops_X550EM");
 344
 345         /* Similar to X550 so start there. */
 346         ret_val = ixgbe_init_ops_X550(hw);
 347
 348         /* Since this function eventually calls
 349          * ixgbe_init_ops_540 by design, we are setting
 350          * the pointers to NULL explicitly here to overwrite
 351          * the values being set in the x540 function.
 352          */
 353         /* Thermal sensor not supported in x550EM */
 354         mac->ops.get_thermal_sensor_data = NULL;
 355         mac->ops.init_thermal_sensor_thresh = NULL;
 356         mac->thermal_sensor_enabled = false;
 357
 358         /* FCOE not supported in x550EM */
 359         mac->ops.get_san_mac_addr = NULL;
 360         mac->ops.set_san_mac_addr = NULL;
 361         mac->ops.get_wwn_prefix = NULL;
 362         mac->ops.get_fcoe_boot_status = NULL;
 363
 364         /* IPsec not supported in x550EM */
 365         mac->ops.disable_sec_rx_path = NULL;
 366         mac->ops.enable_sec_rx_path = NULL;
 367
 368         /* X550EM bus type is internal*/
 369         hw->bus.type = ixgbe_bus_type_internal;
 370         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 371
 372         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 373         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 374         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 375         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 376         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 377         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 378         mac->ops.get_supported_physical_layer =
 379                                     ixgbe_get_supported_physical_layer_X550em;
 380
 381         /* PHY */
 382         phy->ops.init = ixgbe_init_phy_ops_X550em;
 383         phy->ops.identify = ixgbe_identify_phy_x550em;
 384         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 385                 phy->ops.set_phy_power = NULL;
 386
 387
 388         /* EEPROM */
 389         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 390         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 391         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 392         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 393         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 394         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 395         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 396         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 397
 398         return ret_val;
 399 }
 400
 401 /**
 402  *  ixgbe_dmac_config_X550
 403  *  @hw: pointer to hardware structure
 404  *
 405  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 406  *  When disabling dmac, dmac enable dmac bit is cleared.
 407  **/
 408 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 409 {
 410         u32 reg, high_pri_tc;
 411
 412         DEBUGFUNC("ixgbe_dmac_config_X550");
 413
 414         /* Disable DMA coalescing before configuring */
 415         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 416         reg &= ~IXGBE_DMACR_DMAC_EN;
 417         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 418
 419         /* Disable DMA Coalescing if the watchdog timer is 0 */
 420         if (!hw->mac.dmac_config.watchdog_timer)
 421                 goto out;
 422
 423         ixgbe_dmac_config_tcs_X550(hw);
 424
 425         /* Configure DMA Coalescing Control Register */
 426         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 427
 428         /* Set the watchdog timer in units of 40.96 usec */
 429         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 430         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 431
 432         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 433         /* If fcoe is enabled, set high priority traffic class */
 434         if (hw->mac.dmac_config.fcoe_en) {
 435                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 436                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 437                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 438         }
 439         reg |= IXGBE_DMACR_EN_MNG_IND;
 440
 441         /* Enable DMA coalescing after configuration */
 442         reg |= IXGBE_DMACR_DMAC_EN;
 443         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 444
 445 out:
 446         return IXGBE_SUCCESS;
 447 }
 448
 449 /**
 450  *  ixgbe_dmac_config_tcs_X550
 451  *  @hw: pointer to hardware structure
 452  *
 453  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 454  *  be cleared before configuring.
 455  **/
 456 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 457 {
 458         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 459
 460         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 461
 462         /* Configure DMA coalescing enabled */
 463         switch (hw->mac.dmac_config.link_speed) {
 464         case IXGBE_LINK_SPEED_100_FULL:
 465                 pb_headroom = IXGBE_DMACRXT_100M;
 466                 break;
 467         case IXGBE_LINK_SPEED_1GB_FULL:
 468                 pb_headroom = IXGBE_DMACRXT_1G;
 469                 break;
 470         default:
 471                 pb_headroom = IXGBE_DMACRXT_10G;
 472                 break;
 473         }
 474
 475         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 476                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 477
 478         /* Set the per Rx packet buffer receive threshold */
 479         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 480                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 481                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 482
 483                 if (tc < hw->mac.dmac_config.num_tcs) {
 484                         /* Get Rx PB size */
 485                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 486                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 487                                 IXGBE_RXPBSIZE_SHIFT;
 488
 489                         /* Calculate receive buffer threshold in kilobytes */
 490                         if (rx_pb_size > pb_headroom)
 491                                 rx_pb_size = rx_pb_size - pb_headroom;
 492                         else
 493                                 rx_pb_size = 0;
 494
 495                         /* Minimum of MFS shall be set for DMCTH */
 496                         reg |= (rx_pb_size > maxframe_size_kb) ?
 497                                 rx_pb_size : maxframe_size_kb;
 498                 }
 499                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 500         }
 501         return IXGBE_SUCCESS;
 502 }
 503
 504 /**
 505  *  ixgbe_dmac_update_tcs_X550
 506  *  @hw: pointer to hardware structure
 507  *
 508  *  Disables dmac, updates per TC settings, and then enables dmac.
 509  **/
 510 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 511 {
 512         u32 reg;
 513
 514         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 515
 516         /* Disable DMA coalescing before configuring */
 517         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 518         reg &= ~IXGBE_DMACR_DMAC_EN;
 519         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 520
 521         ixgbe_dmac_config_tcs_X550(hw);
 522
 523         /* Enable DMA coalescing after configuration */
 524         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 525         reg |= IXGBE_DMACR_DMAC_EN;
 526         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 527
 528         return IXGBE_SUCCESS;
 529 }
 530
 531 /**
 532  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 533  *  @hw: pointer to hardware structure
 534  *
 535  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 536  *  ixgbe_hw struct in order to set up EEPROM access.
 537  **/
 538 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 539 {
 540         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 541         u32 eec;
 542         u16 eeprom_size;
 543
 544         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 545
 546         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 547                 eeprom->semaphore_delay = 10;
 548                 eeprom->type = ixgbe_flash;
 549
 550                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 551                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 552                                     IXGBE_EEC_SIZE_SHIFT);
 553                 eeprom->word_size = 1 << (eeprom_size +
 554                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 555
 556                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 557                           eeprom->type, eeprom->word_size);
 558         }
 559
 560         return IXGBE_SUCCESS;
 561 }
 562
 563 /**
 564  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 565  *  @hw: pointer to the HW structure
 566  *  @enable_eee: boolean flag to enable EEE
 567  *
 568  *  Enable/disable EEE based on enable_eee flag.
 569  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 570  *  are modified.
 571  *
 572  **/
 573 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 574 {
 575         u32 eeer;
 576         u16 autoneg_eee_reg;
 577         u32 link_reg;
 578         s32 status;
 579
 580         DEBUGFUNC("ixgbe_setup_eee_X550");
 581
 582         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 583         /* Enable or disable EEE per flag */
 584         if (enable_eee) {
 585                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 586
 587                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 588                         /* Advertise EEE capability */
 589                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 590                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 591
 592                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 593                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 594                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 595
 596                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 597                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 598                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 599                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 600                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 601                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 602                         if (status != IXGBE_SUCCESS)
 603                                 return status;
 604
 605                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 606                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 607
 608                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 609                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 610                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 611                         if (status != IXGBE_SUCCESS)
 612                                 return status;
 613                 }
 614         } else {
 615                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 616
 617                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 618                         /* Disable advertised EEE capability */
 619                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 620                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 621
 622                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 623                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 624                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 625
 626                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 627                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 628                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 629                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 630                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 631                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 632                         if (status != IXGBE_SUCCESS)
 633                                 return status;
 634
 635                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 636                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 637
 638                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 639                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 640                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 641                         if (status != IXGBE_SUCCESS)
 642                                 return status;
 643                 }
 644         }
 645         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 646
 647         return IXGBE_SUCCESS;
 648 }
 649
 650 /**
 651  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 652  * @hw: pointer to hardware structure
 653  * @enable: enable or disable source address pruning
 654  * @pool: Rx pool to set source address pruning for
 655  **/
 656 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 657                                            unsigned int pool)
 658 {
 659         u64 pfflp;
 660
 661         /* max rx pool is 63 */
 662         if (pool > 63)
 663                 return;
 664
 665         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 666         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 667
 668         if (enable)
 669                 pfflp |= (1ULL << pool);
 670         else
 671                 pfflp &= ~(1ULL << pool);
 672
 673         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 674         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 675 }
 676
 677 /**
 678  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 679  *  @hw: pointer to hardware structure
 680  *  @enable: enable or disable switch for Ethertype anti-spoofing
 681  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 682  *
 683  **/
 684 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 685                 bool enable, int vf)
 686 {
 687         int vf_target_reg = vf >> 3;
 688         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 689         u32 pfvfspoof;
 690
 691         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 692
 693         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 694         if (enable)
 695                 pfvfspoof |= (1 << vf_target_shift);
 696         else
 697                 pfvfspoof &= ~(1 << vf_target_shift);
 698
 699         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 700 }
 701
 702 /**
 703  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 704  *  device
 705  *  @hw: pointer to hardware structure
 706  *  @reg_addr: 32 bit PHY register to write
 707  *  @device_type: 3 bit device type
 708  *  @data: Data to write to the register
 709  **/
 710 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 711                             u32 device_type, u32 data)
 712 {
 713         u32 i, command, error;
 714
 715         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 716                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 717
 718         /* Write IOSF control register */
 719         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 720
 721         /* Write IOSF data register */
 722         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 723         /*
 724          * Check every 10 usec to see if the address cycle completed.
 725          * The SB IOSF BUSY bit will clear when the operation is
 726          * complete
 727          */
 728         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 729                 usec_delay(10);
 730
 731                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 732                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 733                         break;
 734         }
 735
 736         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 737                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 738                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 739                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 740                               "Failed to write, error %x\n", error);
 741                 return IXGBE_ERR_PHY;
 742         }
 743
 744         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 745                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
 746                 return IXGBE_ERR_PHY;
 747         }
 748
 749         return IXGBE_SUCCESS;
 750 }
 751
 752 /**
 753  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 754  *  device
 755  *  @hw: pointer to hardware structure
 756  *  @reg_addr: 32 bit PHY register to write
 757  *  @device_type: 3 bit device type
 758  *  @phy_data: Pointer to read data from the register
 759  **/
 760 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 761                            u32 device_type, u32 *data)
 762 {
 763         u32 i, command, error;
 764
 765         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 766                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 767
 768         /* Write IOSF control register */
 769         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 770
 771         /*
 772          * Check every 10 usec to see if the address cycle completed.
 773          * The SB IOSF BUSY bit will clear when the operation is
 774          * complete
 775          */
 776         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 777                 usec_delay(10);
 778
 779                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 780                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 781                         break;
 782         }
 783
 784         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 785                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 786                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 787                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 788                                 "Failed to read, error %x\n", error);
 789                 return IXGBE_ERR_PHY;
 790         }
 791
 792         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 793                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
 794                 return IXGBE_ERR_PHY;
 795         }
 796
 797         *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 798
 799         return IXGBE_SUCCESS;
 800 }
 801
 802 /**
 803  *  ixgbe_disable_mdd_X550
 804  *  @hw: pointer to hardware structure
 805  *
 806  *  Disable malicious driver detection
 807  **/
 808 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 809 {
 810         u32 reg;
 811
 812         DEBUGFUNC("ixgbe_disable_mdd_X550");
 813
 814         /* Disable MDD for TX DMA and interrupt */
 815         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 816         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 817         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 818
 819         /* Disable MDD for RX and interrupt */
 820         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 821         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 822         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 823 }
 824
 825 /**
 826  *  ixgbe_enable_mdd_X550
 827  *  @hw: pointer to hardware structure
 828  *
 829  *  Enable malicious driver detection
 830  **/
 831 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 832 {
 833         u32 reg;
 834
 835         DEBUGFUNC("ixgbe_enable_mdd_X550");
 836
 837         /* Enable MDD for TX DMA and interrupt */
 838         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 839         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 840         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 841
 842         /* Enable MDD for RX and interrupt */
 843         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 844         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 845         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 846 }
 847
 848 /**
 849  *  ixgbe_restore_mdd_vf_X550
 850  *  @hw: pointer to hardware structure
 851  *  @vf: vf index
 852  *
 853  *  Restore VF that was disabled during malicious driver detection event
 854  **/
 855 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 856 {
 857         u32 idx, reg, num_qs, start_q, bitmask;
 858
 859         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 860
 861         /* Map VF to queues */
 862         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 863         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 864         case IXGBE_MRQC_VMDQRT8TCEN:
 865                 num_qs = 8;  /* 16 VFs / pools */
 866                 bitmask = 0x000000FF;
 867                 break;
 868         case IXGBE_MRQC_VMDQRSS32EN:
 869         case IXGBE_MRQC_VMDQRT4TCEN:
 870                 num_qs = 4;  /* 32 VFs / pools */
 871                 bitmask = 0x0000000F;
 872                 break;
 873         default:            /* 64 VFs / pools */
 874                 num_qs = 2;
 875                 bitmask = 0x00000003;
 876                 break;
 877         }
 878         start_q = vf * num_qs;
 879
 880         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 881         idx = start_q / 32;
 882         reg = 0;
 883         reg |= (bitmask << (start_q % 32));
 884         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 885         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 886 }
 887
 888 /**
 889  *  ixgbe_mdd_event_X550
 890  *  @hw: pointer to hardware structure
 891  *  @vf_bitmap: vf bitmap of malicious vfs
 892  *
 893  *  Handle malicious driver detection event.
 894  **/
 895 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 896 {
 897         u32 wqbr;
 898         u32 i, j, reg, q, shift, vf, idx;
 899
 900         DEBUGFUNC("ixgbe_mdd_event_X550");
 901
 902         /* figure out pool size for mapping to vf's */
 903         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 904         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 905         case IXGBE_MRQC_VMDQRT8TCEN:
 906                 shift = 3;  /* 16 VFs / pools */
 907                 break;
 908         case IXGBE_MRQC_VMDQRSS32EN:
 909         case IXGBE_MRQC_VMDQRT4TCEN:
 910                 shift = 2;  /* 32 VFs / pools */
 911                 break;
 912         default:
 913                 shift = 1;  /* 64 VFs / pools */
 914                 break;
 915         }
 916
 917         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
 918         for (i = 0; i < 4; i++) {
 919                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
 920                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
 921
 922                 if (!wqbr)
 923                         continue;
 924
 925                 /* Get malicious queue */
 926                 for (j = 0; j < 32 && wqbr; j++) {
 927
 928                         if (!(wqbr & (1 << j)))
 929                                 continue;
 930
 931                         /* Get queue from bitmask */
 932                         q = j + (i * 32);
 933
 934                         /* Map queue to vf */
 935                         vf = (q >> shift);
 936
 937                         /* Set vf bit in vf_bitmap */
 938                         idx = vf / 32;
 939                         vf_bitmap[idx] |= (1 << (vf % 32));
 940                         wqbr &= ~(1 << j);
 941                 }
 942         }
 943 }
 944
 945 /**
 946  *  ixgbe_get_media_type_X550em - Get media type
 947  *  @hw: pointer to hardware structure
 948  *
 949  *  Returns the media type (fiber, copper, backplane)
 950  */
 951 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
 952 {
 953         enum ixgbe_media_type media_type;
 954
 955         DEBUGFUNC("ixgbe_get_media_type_X550em");
 956
 957         /* Detect if there is a copper PHY attached. */
 958         switch (hw->device_id) {
 959         case IXGBE_DEV_ID_X550EM_X_KR:
 960         case IXGBE_DEV_ID_X550EM_X_KX4:
 961                 media_type = ixgbe_media_type_backplane;
 962                 break;
 963         case IXGBE_DEV_ID_X550EM_X_SFP:
 964                 media_type = ixgbe_media_type_fiber;
 965                 break;
 966         case IXGBE_DEV_ID_X550EM_X_1G_T:
 967         case IXGBE_DEV_ID_X550EM_X_10G_T:
 968                 media_type = ixgbe_media_type_copper;
 969                 break;
 970         default:
 971                 media_type = ixgbe_media_type_unknown;
 972                 break;
 973         }
 974         return media_type;
 975 }
 976
 977 /**
 978  *  ixgbe_setup_sfp_modules_X550em - Setup SFP module
 979  *  @hw: pointer to hardware structure
 980  */
 981 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
 982 {
 983         bool setup_linear;
 984         u16 reg_slice, edc_mode;
 985         s32 ret_val;
 986
 987         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
 988
 989         switch (hw->phy.sfp_type) {
 990         case ixgbe_sfp_type_unknown:
 991                 return IXGBE_SUCCESS;
 992         case ixgbe_sfp_type_not_present:
 993                 return IXGBE_ERR_SFP_NOT_PRESENT;
 994         case ixgbe_sfp_type_da_cu_core0:
 995         case ixgbe_sfp_type_da_cu_core1:
 996                 setup_linear = true;
 997                 break;
 998         case ixgbe_sfp_type_srlr_core0:
 999         case ixgbe_sfp_type_srlr_core1:
1000         case ixgbe_sfp_type_da_act_lmt_core0:
1001         case ixgbe_sfp_type_da_act_lmt_core1:
1002         case ixgbe_sfp_type_1g_sx_core0:
1003         case ixgbe_sfp_type_1g_sx_core1:
1004         case ixgbe_sfp_type_1g_lx_core0:
1005         case ixgbe_sfp_type_1g_lx_core1:
1006                 setup_linear = false;
1007                 break;
1008         default:
1009                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1010         }
1011
1012         ixgbe_init_mac_link_ops_X550em(hw);
1013         hw->phy.ops.reset = NULL;
1014
1015         /* The CS4227 slice address is the base address + the port-pair reg
1016          * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
1017          */
1018         reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12);
1019
1020         if (setup_linear)
1021                 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1022         else
1023                 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1024
1025         /* Configure CS4227 for connection type. */
1026         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1027                                            edc_mode);
1028
1029         if (ret_val != IXGBE_SUCCESS)
1030                 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
1031                                                    edc_mode);
1032
1033         return ret_val;
1034 }
1035
1036 /**
1037  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1038  *  @hw: pointer to hardware structure
1039  */
1040 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1041 {
1042         struct ixgbe_mac_info *mac = &hw->mac;
1043
1044         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1045
1046         /* CS4227 does not support autoneg, so disable the laser control
1047          * functions for SFP+ fiber
1048          */
1049          if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1050                 mac->ops.disable_tx_laser = NULL;
1051                 mac->ops.enable_tx_laser = NULL;
1052                 mac->ops.flap_tx_laser = NULL;
1053                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1054                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1055                 mac->ops.set_rate_select_speed =
1056                                         ixgbe_set_soft_rate_select_speed;
1057          }
1058 }
1059
1060 /**
1061  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1062  *  @hw: pointer to hardware structure
1063  *  @speed: pointer to link speed
1064  *  @autoneg: true when autoneg or autotry is enabled
1065  */
1066 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1067                                        ixgbe_link_speed *speed,
1068                                        bool *autoneg)
1069 {
1070         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1071
1072         /* SFP */
1073         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1074
1075                 /* CS4227 SFP must not enable auto-negotiation */
1076                 *autoneg = false;
1077
1078                 /* Check if 1G SFP module. */
1079                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1080                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1081                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1082                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1083                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1084                         return IXGBE_SUCCESS;
1085                 }
1086
1087                 /* Link capabilities are based on SFP */
1088                 if (hw->phy.multispeed_fiber)
1089                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1090                                  IXGBE_LINK_SPEED_1GB_FULL;
1091                 else
1092                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1093         } else {
1094                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1095                          IXGBE_LINK_SPEED_1GB_FULL;
1096                 *autoneg = true;
1097         }
1098
1099         return IXGBE_SUCCESS;
1100 }
1101
1102 /**
1103  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1104  *  @hw: pointer to hardware structure
1105  *
1106  *  Initialize any function pointers that were not able to be
1107  *  set during init_shared_code because the PHY/SFP type was
1108  *  not known.  Perform the SFP init if necessary.
1109  */
1110 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1111 {
1112         struct ixgbe_phy_info *phy = &hw->phy;
1113         s32 ret_val;
1114
1115         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1116
1117         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1118                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1119                 ixgbe_setup_mux_ctl(hw);
1120         }
1121
1122         /* Identify the PHY or SFP module */
1123         ret_val = phy->ops.identify(hw);
1124         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1125                 return ret_val;
1126
1127         /* Setup function pointers based on detected SFP module and speeds */
1128         ixgbe_init_mac_link_ops_X550em(hw);
1129         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1130                 phy->ops.reset = NULL;
1131
1132         /* Set functions pointers based on phy type */
1133         switch (hw->phy.type) {
1134         case ixgbe_phy_x550em_kx4:
1135                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1136                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1137                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1138                 break;
1139         case ixgbe_phy_x550em_kr:
1140                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1141                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1142                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1143                 break;
1144         case ixgbe_phy_x550em_ext_t:
1145                 phy->ops.setup_internal_link = ixgbe_setup_internal_phy_x550em;
1146                 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1147                 break;
1148         default:
1149                 break;
1150         }
1151         return ret_val;
1152 }
1153
1154 /**
1155  *  ixgbe_reset_hw_X550em - Perform hardware reset
1156  *  @hw: pointer to hardware structure
1157  *
1158  *  Resets the hardware by resetting the transmit and receive units, masks
1159  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1160  *  reset.
1161  */
1162 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1163 {
1164         struct ixgbe_hic_hdr fw_cmd;
1165         ixgbe_link_speed link_speed;
1166         s32 status;
1167         u32 ctrl = 0;
1168         u32 i;
1169         bool link_up = false;
1170
1171         DEBUGFUNC("ixgbe_reset_hw_X550em");
1172
1173         fw_cmd.cmd = FW_PHY_MGMT_REQ_CMD;
1174         fw_cmd.buf_len = 0;
1175         fw_cmd.cmd_or_resp.cmd_resv = 0;
1176         fw_cmd.checksum = FW_DEFAULT_CHECKSUM;
1177         status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
1178                                               sizeof(fw_cmd),
1179                                               IXGBE_HI_PHY_MGMT_REQ_TIMEOUT,
1180                                               true);
1181         if (status)
1182                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1183                               "PHY mgmt command failed with %d\n", status);
1184         else if (fw_cmd.cmd_or_resp.ret_status != FW_CEM_RESP_STATUS_SUCCESS)
1185                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1186                               "PHY mgmt command returned %d\n",
1187                               fw_cmd.cmd_or_resp.ret_status);
1188
1189         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1190         status = hw->mac.ops.stop_adapter(hw);
1191         if (status != IXGBE_SUCCESS)
1192                 return status;
1193
1194         /* flush pending Tx transactions */
1195         ixgbe_clear_tx_pending(hw);
1196
1197         /* PHY ops must be identified and initialized prior to reset */
1198
1199         /* Identify PHY and related function pointers */
1200         status = hw->phy.ops.init(hw);
1201
1202         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1203                 return status;
1204
1205         /* start the external PHY */
1206         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1207                 status = ixgbe_init_ext_t_x550em(hw);
1208                 if (status)
1209                         return status;
1210         }
1211
1212         /* Setup SFP module if there is one present. */
1213         if (hw->phy.sfp_setup_needed) {
1214                 status = hw->mac.ops.setup_sfp(hw);
1215                 hw->phy.sfp_setup_needed = false;
1216         }
1217
1218         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1219                 return status;
1220
1221         /* Reset PHY */
1222         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1223                 hw->phy.ops.reset(hw);
1224
1225 mac_reset_top:
1226         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1227          * If link reset is used when link is up, it might reset the PHY when
1228          * mng is using it.  If link is down or the flag to force full link
1229          * reset is set, then perform link reset.
1230          */
1231         ctrl = IXGBE_CTRL_LNK_RST;
1232         if (!hw->force_full_reset) {
1233                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1234                 if (link_up)
1235                         ctrl = IXGBE_CTRL_RST;
1236         }
1237
1238         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1239         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1240         IXGBE_WRITE_FLUSH(hw);
1241
1242         /* Poll for reset bit to self-clear meaning reset is complete */
1243         for (i = 0; i < 10; i++) {
1244                 usec_delay(1);
1245                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1246                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1247                         break;
1248         }
1249
1250         if (ctrl & IXGBE_CTRL_RST_MASK) {
1251                 status = IXGBE_ERR_RESET_FAILED;
1252                 DEBUGOUT("Reset polling failed to complete.\n");
1253         }
1254
1255         msec_delay(50);
1256
1257         /* Double resets are required for recovery from certain error
1258          * conditions.  Between resets, it is necessary to stall to
1259          * allow time for any pending HW events to complete.
1260          */
1261         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1262                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1263                 goto mac_reset_top;
1264         }
1265
1266         /* Store the permanent mac address */
1267         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1268
1269         /* Store MAC address from RAR0, clear receive address registers, and
1270          * clear the multicast table.  Also reset num_rar_entries to 128,
1271          * since we modify this value when programming the SAN MAC address.
1272          */
1273         hw->mac.num_rar_entries = 128;
1274         hw->mac.ops.init_rx_addrs(hw);
1275
1276
1277         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1278                 ixgbe_setup_mux_ctl(hw);
1279
1280         return status;
1281 }
1282
1283 /**
1284  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1285  * @hw: pointer to hardware structure
1286  */
1287 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1288 {
1289         u32 status;
1290         u16 reg;
1291         u32 retries = 1;
1292
1293         /* TODO: The number of attempts and delay between attempts is undefined */
1294         do {
1295                 /* decrement retries counter and exit if we hit 0 */
1296                 if (retries < 1) {
1297                         ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
1298                                       "External PHY not yet finished resetting.");
1299                         return IXGBE_ERR_PHY;
1300                 }
1301                 retries--;
1302
1303                 usec_delay(0);
1304
1305                 status = hw->phy.ops.read_reg(hw,
1306                                               IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1307                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1308                                               &reg);
1309
1310                 if (status != IXGBE_SUCCESS)
1311                         return status;
1312
1313                 /* Verify PHY FW reset has completed */
1314         } while ((reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) != 1);
1315
1316         /* Set port to low power mode */
1317         status = hw->phy.ops.read_reg(hw,
1318                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
1319                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1320                                       &reg);
1321
1322         if (status != IXGBE_SUCCESS)
1323                 return status;
1324
1325         reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
1326
1327         status = hw->phy.ops.write_reg(hw,
1328                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
1329                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1330                                        reg);
1331
1332         if (status != IXGBE_SUCCESS)
1333                 return status;
1334
1335         /* Enable the transmitter */
1336         status = hw->phy.ops.read_reg(hw,
1337                                       IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
1338                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1339                                       &reg);
1340
1341         if (status != IXGBE_SUCCESS)
1342                 return status;
1343
1344         reg &= ~IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE;
1345
1346         status = hw->phy.ops.write_reg(hw,
1347                                        IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
1348                                        IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1349                                        reg);
1350
1351         if (status != IXGBE_SUCCESS)
1352                 return status;
1353
1354         /* Un-stall the PHY FW */
1355         status = hw->phy.ops.read_reg(hw,
1356                                       IXGBE_MDIO_GLOBAL_RES_PR_10,
1357                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1358                                       &reg);
1359
1360         if (status != IXGBE_SUCCESS)
1361                 return status;
1362
1363         reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1364
1365         status = hw->phy.ops.write_reg(hw,
1366                                        IXGBE_MDIO_GLOBAL_RES_PR_10,
1367                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1368                                        reg);
1369
1370         return status;
1371 }
1372
1373 /**
1374  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1375  *  @hw: pointer to hardware structure
1376  *
1377  *  Configures the integrated KR PHY.
1378  **/
1379 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1380 {
1381         s32 status;
1382         u32 reg_val;
1383
1384         status = ixgbe_read_iosf_sb_reg_x550(hw,
1385                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1386                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1387         if (status)
1388                 return status;
1389
1390         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1391         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1392                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1393         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1394                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1395
1396         /* Advertise 10G support. */
1397         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1398                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1399
1400         /* Advertise 1G support. */
1401         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1402                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1403
1404         /* Restart auto-negotiation. */
1405         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1406         status = ixgbe_write_iosf_sb_reg_x550(hw,
1407                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1408                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1409
1410         return status;
1411 }
1412
1413 /**
1414  *  ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1415  *  @hw: pointer to hardware structure
1416  *
1417  *  Configures the integrated KX4 PHY.
1418  **/
1419 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1420 {
1421         s32 status;
1422         u32 reg_val;
1423
1424         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1425                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, &reg_val);
1426         if (status)
1427                 return status;
1428
1429         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1430                         IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1431
1432         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1433
1434         /* Advertise 10G support. */
1435         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1436                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1437
1438         /* Advertise 1G support. */
1439         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1440                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1441
1442         /* Restart auto-negotiation. */
1443         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1444         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1445                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, reg_val);
1446
1447         return status;
1448 }
1449
1450 /**
1451  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1452  *  @hw: pointer to hardware structure
1453  *  @speed: the link speed to force
1454  *
1455  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1456  *  internal and external PHY at a specific speed, without autonegotiation.
1457  **/
1458 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1459 {
1460         s32 status;
1461         u32 reg_val;
1462
1463         /* Disable AN and force speed to 10G Serial. */
1464         status = ixgbe_read_iosf_sb_reg_x550(hw,
1465                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1466                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1467         if (status != IXGBE_SUCCESS)
1468                 return status;
1469
1470         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1471         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1472
1473         /* Select forced link speed for internal PHY. */
1474         switch (*speed) {
1475         case IXGBE_LINK_SPEED_10GB_FULL:
1476                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1477                 break;
1478         case IXGBE_LINK_SPEED_1GB_FULL:
1479                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1480                 break;
1481         default:
1482                 /* Other link speeds are not supported by internal KR PHY. */
1483                 return IXGBE_ERR_LINK_SETUP;
1484         }
1485
1486         status = ixgbe_write_iosf_sb_reg_x550(hw,
1487                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1488                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1489         if (status != IXGBE_SUCCESS)
1490                 return status;
1491
1492         /* Disable training protocol FSM. */
1493         status = ixgbe_read_iosf_sb_reg_x550(hw,
1494                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1495                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1496         if (status != IXGBE_SUCCESS)
1497                 return status;
1498         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1499         status = ixgbe_write_iosf_sb_reg_x550(hw,
1500                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1501                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1502         if (status != IXGBE_SUCCESS)
1503                 return status;
1504
1505         /* Disable Flex from training TXFFE. */
1506         status = ixgbe_read_iosf_sb_reg_x550(hw,
1507                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1508                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1509         if (status != IXGBE_SUCCESS)
1510                 return status;
1511         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1512         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1513         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1514         status = ixgbe_write_iosf_sb_reg_x550(hw,
1515                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1516                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1517         if (status != IXGBE_SUCCESS)
1518                 return status;
1519         status = ixgbe_read_iosf_sb_reg_x550(hw,
1520                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1521                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1522         if (status != IXGBE_SUCCESS)
1523                 return status;
1524         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1525         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1526         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1527         status = ixgbe_write_iosf_sb_reg_x550(hw,
1528                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1529                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1530         if (status != IXGBE_SUCCESS)
1531                 return status;
1532
1533         /* Enable override for coefficients. */
1534         status = ixgbe_read_iosf_sb_reg_x550(hw,
1535                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1536                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1537         if (status != IXGBE_SUCCESS)
1538                 return status;
1539         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1540         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1541         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1542         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1543         status = ixgbe_write_iosf_sb_reg_x550(hw,
1544                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1545                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1546         if (status != IXGBE_SUCCESS)
1547                 return status;
1548
1549         /* Toggle port SW reset by AN reset. */
1550         status = ixgbe_read_iosf_sb_reg_x550(hw,
1551                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1552                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1553         if (status != IXGBE_SUCCESS)
1554                 return status;
1555         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1556         status = ixgbe_write_iosf_sb_reg_x550(hw,
1557                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1558                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1559
1560         return status;
1561 }
1562
1563 /**
1564  *  ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1565  *  @hw: pointer to hardware structure
1566  *
1567  *  Configures the integrated KR PHY for SFP support.
1568  **/
1569 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1570                                     ixgbe_link_speed speed,
1571                                     bool autoneg_wait_to_complete)
1572 {
1573         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1574
1575         return ixgbe_setup_ixfi_x550em(hw, &speed);
1576 }
1577
1578 /**
1579  * ixgbe_setup_internal_phy_x550em - Configure integrated KR PHY
1580  * @hw: point to hardware structure
1581  *
1582  * Configures the integrated KR PHY to talk to the external PHY. The base
1583  * driver will call this function when it gets notification via interrupt from
1584  * the external PHY. This function forces the internal PHY into iXFI mode at
1585  * the correct speed.
1586  *
1587  * A return of a non-zero value indicates an error, and the base driver should
1588  * not report link up.
1589  */
1590 s32 ixgbe_setup_internal_phy_x550em(struct ixgbe_hw *hw)
1591 {
1592         u32 status;
1593         u16 lasi, autoneg_status, speed;
1594         ixgbe_link_speed force_speed;
1595
1596         /* Verify that the external link status has changed */
1597         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_XENPAK_LASI_STATUS,
1598                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1599                                       &lasi);
1600         if (status != IXGBE_SUCCESS)
1601                 return status;
1602
1603         /* If there was no change in link status, we can just exit */
1604         if (!(lasi & IXGBE_XENPAK_LASI_LINK_STATUS_ALARM))
1605                 return IXGBE_SUCCESS;
1606
1607         /* we read this twice back to back to indicate current status */
1608         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1609                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1610                                       &autoneg_status);
1611         if (status != IXGBE_SUCCESS)
1612                 return status;
1613
1614         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1615                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1616                                       &autoneg_status);
1617         if (status != IXGBE_SUCCESS)
1618                 return status;
1619
1620         /* If link is not up return an error indicating treat link as down */
1621         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1622                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1623
1624         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1625                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1626                                       &speed);
1627
1628         /* clear everything but the speed and duplex bits */
1629         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1630
1631         switch (speed) {
1632         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1633                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1634                 break;
1635         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1636                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1637                 break;
1638         default:
1639                 /* Internal PHY does not support anything else */
1640                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1641         }
1642
1643         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1644 }
1645
1646 /**
1647  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1648  *  @hw: pointer to hardware structure
1649  *
1650  *  Configures the integrated KR PHY to use internal loopback mode.
1651  **/
1652 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1653 {
1654         s32 status;
1655         u32 reg_val;
1656
1657         /* Disable AN and force speed to 10G Serial. */
1658         status = ixgbe_read_iosf_sb_reg_x550(hw,
1659                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1660                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1661         if (status != IXGBE_SUCCESS)
1662                 return status;
1663         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1664         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1665         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1666         status = ixgbe_write_iosf_sb_reg_x550(hw,
1667                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1668                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1669         if (status != IXGBE_SUCCESS)
1670                 return status;
1671
1672         /* Set near-end loopback clocks. */
1673         status = ixgbe_read_iosf_sb_reg_x550(hw,
1674                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1675                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1676         if (status != IXGBE_SUCCESS)
1677                 return status;
1678         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1679         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1680         status = ixgbe_write_iosf_sb_reg_x550(hw,
1681                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1682                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1683         if (status != IXGBE_SUCCESS)
1684                 return status;
1685
1686         /* Set loopback enable. */
1687         status = ixgbe_read_iosf_sb_reg_x550(hw,
1688                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1689                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1690         if (status != IXGBE_SUCCESS)
1691                 return status;
1692         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1693         status = ixgbe_write_iosf_sb_reg_x550(hw,
1694                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1695                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1696         if (status != IXGBE_SUCCESS)
1697                 return status;
1698
1699         /* Training bypass. */
1700         status = ixgbe_read_iosf_sb_reg_x550(hw,
1701                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1702                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1703         if (status != IXGBE_SUCCESS)
1704                 return status;
1705         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1706         status = ixgbe_write_iosf_sb_reg_x550(hw,
1707                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1708                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1709
1710         return status;
1711 }
1712
1713 /**
1714  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1715  *  assuming that the semaphore is already obtained.
1716  *  @hw: pointer to hardware structure
1717  *  @offset: offset of  word in the EEPROM to read
1718  *  @data: word read from the EEPROM
1719  *
1720  *  Reads a 16 bit word from the EEPROM using the hostif.
1721  **/
1722 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1723                                    u16 *data)
1724 {
1725         s32 status;
1726         struct ixgbe_hic_read_shadow_ram buffer;
1727
1728         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1729         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1730         buffer.hdr.req.buf_lenh = 0;
1731         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1732         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1733
1734         /* convert offset from words to bytes */
1735         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1736         /* one word */
1737         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1738
1739         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1740                                               sizeof(buffer),
1741                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1742
1743         if (status)
1744                 return status;
1745
1746         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1747                                           FW_NVM_DATA_OFFSET);
1748
1749         return 0;
1750 }
1751
1752 /**
1753  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1754  *  @hw: pointer to hardware structure
1755  *  @offset: offset of  word in the EEPROM to read
1756  *  @data: word read from the EEPROM
1757  *
1758  *  Reads a 16 bit word from the EEPROM using the hostif.
1759  **/
1760 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1761                               u16 *data)
1762 {
1763         s32 status = IXGBE_SUCCESS;
1764
1765         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1766
1767         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1768             IXGBE_SUCCESS) {
1769                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1770                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1771         } else {
1772                 status = IXGBE_ERR_SWFW_SYNC;
1773         }
1774
1775         return status;
1776 }
1777
1778 /**
1779  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1780  *  @hw: pointer to hardware structure
1781  *  @offset: offset of  word in the EEPROM to read
1782  *  @words: number of words
1783  *  @data: word(s) read from the EEPROM
1784  *
1785  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
1786  **/
1787 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1788                                      u16 offset, u16 words, u16 *data)
1789 {
1790         struct ixgbe_hic_read_shadow_ram buffer;
1791         u32 current_word = 0;
1792         u16 words_to_read;
1793         s32 status;
1794         u32 i;
1795
1796         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1797
1798         /* Take semaphore for the entire operation. */
1799         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1800         if (status) {
1801                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1802                 return status;
1803         }
1804         while (words) {
1805                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1806                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1807                 else
1808                         words_to_read = words;
1809
1810                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1811                 buffer.hdr.req.buf_lenh = 0;
1812                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1813                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1814
1815                 /* convert offset from words to bytes */
1816                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1817                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1818
1819                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1820                                                       sizeof(buffer),
1821                                                       IXGBE_HI_COMMAND_TIMEOUT,
1822                                                       false);
1823
1824                 if (status) {
1825                         DEBUGOUT("Host interface command failed\n");
1826                         goto out;
1827                 }
1828
1829                 for (i = 0; i < words_to_read; i++) {
1830                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1831                                   2 * i;
1832                         u32 value = IXGBE_READ_REG(hw, reg);
1833
1834                         data[current_word] = (u16)(value & 0xffff);
1835                         current_word++;
1836                         i++;
1837                         if (i < words_to_read) {
1838                                 value >>= 16;
1839                                 data[current_word] = (u16)(value & 0xffff);
1840                                 current_word++;
1841                         }
1842                 }
1843                 words -= words_to_read;
1844         }
1845
1846 out:
1847         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1848         return status;
1849 }
1850
1851 /**
1852  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1853  *  @hw: pointer to hardware structure
1854  *  @offset: offset of  word in the EEPROM to write
1855  *  @data: word write to the EEPROM
1856  *
1857  *  Write a 16 bit word to the EEPROM using the hostif.
1858  **/
1859 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1860                                     u16 data)
1861 {
1862         s32 status;
1863         struct ixgbe_hic_write_shadow_ram buffer;
1864
1865         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1866
1867         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1868         buffer.hdr.req.buf_lenh = 0;
1869         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1870         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1871
1872          /* one word */
1873         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1874         buffer.data = data;
1875         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1876
1877         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1878                                               sizeof(buffer),
1879                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1880
1881         return status;
1882 }
1883
1884 /**
1885  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1886  *  @hw: pointer to hardware structure
1887  *  @offset: offset of  word in the EEPROM to write
1888  *  @data: word write to the EEPROM
1889  *
1890  *  Write a 16 bit word to the EEPROM using the hostif.
1891  **/
1892 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1893                                u16 data)
1894 {
1895         s32 status = IXGBE_SUCCESS;
1896
1897         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
1898
1899         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1900             IXGBE_SUCCESS) {
1901                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1902                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1903         } else {
1904                 DEBUGOUT("write ee hostif failed to get semaphore");
1905                 status = IXGBE_ERR_SWFW_SYNC;
1906         }
1907
1908         return status;
1909 }
1910
1911 /**
1912  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1913  *  @hw: pointer to hardware structure
1914  *  @offset: offset of  word in the EEPROM to write
1915  *  @words: number of words
1916  *  @data: word(s) write to the EEPROM
1917  *
1918  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1919  **/
1920 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1921                                       u16 offset, u16 words, u16 *data)
1922 {
1923         s32 status = IXGBE_SUCCESS;
1924         u32 i = 0;
1925
1926         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
1927
1928         /* Take semaphore for the entire operation. */
1929         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1930         if (status != IXGBE_SUCCESS) {
1931                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
1932                 goto out;
1933         }
1934
1935         for (i = 0; i < words; i++) {
1936                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1937                                                          data[i]);
1938
1939                 if (status != IXGBE_SUCCESS) {
1940                         DEBUGOUT("Eeprom buffered write failed\n");
1941                         break;
1942                 }
1943         }
1944
1945         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1946 out:
1947
1948         return status;
1949 }
1950
1951 /**
1952  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
1953  * @hw: pointer to hardware structure
1954  * @ptr: pointer offset in eeprom
1955  * @size: size of section pointed by ptr, if 0 first word will be used as size
1956  * @csum: address of checksum to update
1957  *
1958  * Returns error status for any failure
1959  */
1960 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
1961                                    u16 size, u16 *csum, u16 *buffer,
1962                                    u32 buffer_size)
1963 {
1964         u16 buf[256];
1965         s32 status;
1966         u16 length, bufsz, i, start;
1967         u16 *local_buffer;
1968
1969         bufsz = sizeof(buf) / sizeof(buf[0]);
1970
1971         /* Read a chunk at the pointer location */
1972         if (!buffer) {
1973                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
1974                 if (status) {
1975                         DEBUGOUT("Failed to read EEPROM image\n");
1976                         return status;
1977                 }
1978                 local_buffer = buf;
1979         } else {
1980                 if (buffer_size < ptr)
1981                         return  IXGBE_ERR_PARAM;
1982                 local_buffer = &buffer[ptr];
1983         }
1984
1985         if (size) {
1986                 start = 0;
1987                 length = size;
1988         } else {
1989                 start = 1;
1990                 length = local_buffer[0];
1991
1992                 /* Skip pointer section if length is invalid. */
1993                 if (length == 0xFFFF || length == 0 ||
1994                     (ptr + length) >= hw->eeprom.word_size)
1995                         return IXGBE_SUCCESS;
1996         }
1997
1998         if (buffer && ((u32)start + (u32)length > buffer_size))
1999                 return IXGBE_ERR_PARAM;
2000
2001         for (i = start; length; i++, length--) {
2002                 if (i == bufsz && !buffer) {
2003                         ptr += bufsz;
2004                         i = 0;
2005                         if (length < bufsz)
2006                                 bufsz = length;
2007
2008                         /* Read a chunk at the pointer location */
2009                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2010                                                                   bufsz, buf);
2011                         if (status) {
2012                                 DEBUGOUT("Failed to read EEPROM image\n");
2013                                 return status;
2014                         }
2015                 }
2016                 *csum += local_buffer[i];
2017         }
2018         return IXGBE_SUCCESS;
2019 }
2020
2021 /**
2022  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2023  *  @hw: pointer to hardware structure
2024  *  @buffer: pointer to buffer containing calculated checksum
2025  *  @buffer_size: size of buffer
2026  *
2027  *  Returns a negative error code on error, or the 16-bit checksum
2028  **/
2029 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2030 {
2031         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2032         u16 *local_buffer;
2033         s32 status;
2034         u16 checksum = 0;
2035         u16 pointer, i, size;
2036
2037         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2038
2039         hw->eeprom.ops.init_params(hw);
2040
2041         if (!buffer) {
2042                 /* Read pointer area */
2043                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2044                                                      IXGBE_EEPROM_LAST_WORD + 1,
2045                                                      eeprom_ptrs);
2046                 if (status) {
2047                         DEBUGOUT("Failed to read EEPROM image\n");
2048                         return status;
2049                 }
2050                 local_buffer = eeprom_ptrs;
2051         } else {
2052                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2053                         return IXGBE_ERR_PARAM;
2054                 local_buffer = buffer;
2055         }
2056
2057         /*
2058          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2059          * checksum word itself
2060          */
2061         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2062                 if (i != IXGBE_EEPROM_CHECKSUM)
2063                         checksum += local_buffer[i];
2064
2065         /*
2066          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2067          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2068          */
2069         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2070                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2071                         continue;
2072
2073                 pointer = local_buffer[i];
2074
2075                 /* Skip pointer section if the pointer is invalid. */
2076                 if (pointer == 0xFFFF || pointer == 0 ||
2077                     pointer >= hw->eeprom.word_size)
2078                         continue;
2079
2080                 switch (i) {
2081                 case IXGBE_PCIE_GENERAL_PTR:
2082                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2083                         break;
2084                 case IXGBE_PCIE_CONFIG0_PTR:
2085                 case IXGBE_PCIE_CONFIG1_PTR:
2086                         size = IXGBE_PCIE_CONFIG_SIZE;
2087                         break;
2088                 default:
2089                         size = 0;
2090                         break;
2091                 }
2092
2093                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2094                                                 buffer, buffer_size);
2095                 if (status)
2096                         return status;
2097         }
2098
2099         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2100
2101         return (s32)checksum;
2102 }
2103
2104 /**
2105  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2106  *  @hw: pointer to hardware structure
2107  *
2108  *  Returns a negative error code on error, or the 16-bit checksum
2109  **/
2110 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2111 {
2112         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2113 }
2114
2115 /**
2116  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2117  *  @hw: pointer to hardware structure
2118  *  @checksum_val: calculated checksum
2119  *
2120  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2121  *  caller does not need checksum_val, the value can be NULL.
2122  **/
2123 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2124 {
2125         s32 status;
2126         u16 checksum;
2127         u16 read_checksum = 0;
2128
2129         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2130
2131         /* Read the first word from the EEPROM. If this times out or fails, do
2132          * not continue or we could be in for a very long wait while every
2133          * EEPROM read fails
2134          */
2135         status = hw->eeprom.ops.read(hw, 0, &checksum);
2136         if (status) {
2137                 DEBUGOUT("EEPROM read failed\n");
2138                 return status;
2139         }
2140
2141         status = hw->eeprom.ops.calc_checksum(hw);
2142         if (status < 0)
2143                 return status;
2144
2145         checksum = (u16)(status & 0xffff);
2146
2147         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2148                                            &read_checksum);
2149         if (status)
2150                 return status;
2151
2152         /* Verify read checksum from EEPROM is the same as
2153          * calculated checksum
2154          */
2155         if (read_checksum != checksum) {
2156                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2157                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2158                              "Invalid EEPROM checksum");
2159         }
2160
2161         /* If the user cares, return the calculated checksum */
2162         if (checksum_val)
2163                 *checksum_val = checksum;
2164
2165         return status;
2166 }
2167
2168 /**
2169  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2170  * @hw: pointer to hardware structure
2171  *
2172  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2173  * checksum and updates the EEPROM and instructs the hardware to update
2174  * the flash.
2175  **/
2176 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2177 {
2178         s32 status;
2179         u16 checksum = 0;
2180
2181         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2182
2183         /* Read the first word from the EEPROM. If this times out or fails, do
2184          * not continue or we could be in for a very long wait while every
2185          * EEPROM read fails
2186          */
2187         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2188         if (status) {
2189                 DEBUGOUT("EEPROM read failed\n");
2190                 return status;
2191         }
2192
2193         status = ixgbe_calc_eeprom_checksum_X550(hw);
2194         if (status < 0)
2195                 return status;
2196
2197         checksum = (u16)(status & 0xffff);
2198
2199         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2200                                             checksum);
2201         if (status)
2202                 return status;
2203
2204         status = ixgbe_update_flash_X550(hw);
2205
2206         return status;
2207 }
2208
2209 /**
2210  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2211  *  @hw: pointer to hardware structure
2212  *
2213  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2214  **/
2215 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2216 {
2217         s32 status = IXGBE_SUCCESS;
2218         union ixgbe_hic_hdr2 buffer;
2219
2220         DEBUGFUNC("ixgbe_update_flash_X550");
2221
2222         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2223         buffer.req.buf_lenh = 0;
2224         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2225         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2226
2227         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2228                                               sizeof(buffer),
2229                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2230
2231         return status;
2232 }
2233
2234 /**
2235  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2236  *  @hw: pointer to hardware structure
2237  *
2238  *  Determines physical layer capabilities of the current configuration.
2239  **/
2240 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2241 {
2242         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2243         u16 ext_ability = 0;
2244
2245         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2246
2247         hw->phy.ops.identify(hw);
2248
2249         switch (hw->phy.type) {
2250         case ixgbe_phy_x550em_kr:
2251                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2252                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2253                 break;
2254         case ixgbe_phy_x550em_kx4:
2255                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2256                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2257                 break;
2258         case ixgbe_phy_x550em_ext_t:
2259                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2260                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2261                                      &ext_ability);
2262                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2263                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2264                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2265                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2266                 break;
2267         default:
2268                 break;
2269         }
2270
2271         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2272                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2273
2274         return physical_layer;
2275 }
2276
2277 /**
2278  * ixgbe_get_bus_info_x550em - Set PCI bus info
2279  * @hw: pointer to hardware structure
2280  *
2281  * Sets bus link width and speed to unknown because X550em is
2282  * not a PCI device.
2283  **/
2284 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2285 {
2286
2287         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2288
2289         hw->bus.width = ixgbe_bus_width_unknown;
2290         hw->bus.speed = ixgbe_bus_speed_unknown;
2291
2292         return IXGBE_SUCCESS;
2293 }
2294
2295 /**
2296  * ixgbe_disable_rx_x550 - Disable RX unit
2297  *
2298  * Enables the Rx DMA unit for x550
2299  **/
2300 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2301 {
2302         u32 rxctrl, pfdtxgswc;
2303         s32 status;
2304         struct ixgbe_hic_disable_rxen fw_cmd;
2305
2306         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2307
2308         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2309         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2310                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2311                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2312                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2313                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2314                         hw->mac.set_lben = true;
2315                 } else {
2316                         hw->mac.set_lben = false;
2317                 }
2318
2319                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2320                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2321                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2322                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2323
2324                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2325                                         sizeof(struct ixgbe_hic_disable_rxen),
2326                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2327
2328                 /* If we fail - disable RX using register write */
2329                 if (status) {
2330                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2331                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2332                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2333                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2334                         }
2335                 }
2336         }
2337 }
2338
2339 /**
2340  * ixgbe_enter_lplu_x550em - Transition to low power states
2341  *  @hw: pointer to hardware structure
2342  *
2343  * Configures Low Power Link Up on transition to low power states
2344  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2345  * X557 PHY immediately prior to entering LPLU.
2346  **/
2347 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2348 {
2349         u16 autoneg_status, an_10g_cntl_reg, autoneg_reg, speed;
2350         s32 status;
2351         ixgbe_link_speed lcd_speed;
2352
2353         /* If blocked by MNG FW, then don't restart AN */
2354         if (ixgbe_check_reset_blocked(hw))
2355                 return IXGBE_SUCCESS;
2356
2357         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2358                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2359                                       &autoneg_status);
2360
2361         if (status != IXGBE_SUCCESS)
2362                 return status;
2363
2364         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2365
2366         if (status != IXGBE_SUCCESS)
2367                 return status;
2368
2369         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2370          * disabled, then force link down by entering low power mode.
2371          */
2372         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS) ||
2373             !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2374             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2375                 return ixgbe_set_copper_phy_power(hw, FALSE);
2376
2377         /* Determine LCD */
2378         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2379
2380         if (status != IXGBE_SUCCESS)
2381                 return status;
2382
2383         /* If no valid LCD link speed, then force link down and exit. */
2384         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2385                 return ixgbe_set_copper_phy_power(hw, FALSE);
2386
2387         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2388                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2389                                       &speed);
2390
2391         if (status != IXGBE_SUCCESS)
2392                 return status;
2393
2394         /* clear everything but the speed bits */
2395         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2396
2397         /* If current speed is already LCD, then exit. */
2398         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2399              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2400             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2401              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2402                 return status;
2403
2404         /* Clear AN completed indication */
2405         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2406                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2407                                       &autoneg_status);
2408
2409         if (status != IXGBE_SUCCESS)
2410                 return status;
2411
2412         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2413                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2414                              &an_10g_cntl_reg);
2415
2416         if (status != IXGBE_SUCCESS)
2417                 return status;
2418
2419         status = hw->phy.ops.read_reg(hw,
2420                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2421                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2422                              &autoneg_reg);
2423
2424         if (status != IXGBE_SUCCESS)
2425                 return status;
2426
2427         /* Set AN advertizement to only include LCD  */
2428         if (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL) {
2429                 an_10g_cntl_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
2430                 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
2431         }
2432
2433         if (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL) {
2434                 an_10g_cntl_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
2435                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
2436         }
2437
2438         status = hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2439                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2440                               an_10g_cntl_reg);
2441
2442         if (status != IXGBE_SUCCESS)
2443                 return status;
2444
2445         status = hw->phy.ops.write_reg(hw,
2446                               IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2447                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2448                               autoneg_reg);
2449
2450         if (status != IXGBE_SUCCESS)
2451                 return status;
2452
2453         /* Restart PHY auto-negotiation. */
2454         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
2455                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
2456
2457         if (status != IXGBE_SUCCESS)
2458                 return status;
2459
2460         autoneg_reg |= IXGBE_MII_RESTART;
2461
2462         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
2463                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
2464
2465         if (status != IXGBE_SUCCESS)
2466                 return status;
2467
2468         status = ixgbe_setup_ixfi_x550em(hw, &lcd_speed);
2469
2470         return status;
2471 }
2472
2473 /**
2474  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2475  *  @hw: pointer to hardware structure
2476  *  @lcd_speed: pointer to lowest common link speed
2477  *
2478  * Determine lowest common link speed with link partner.
2479  **/
2480 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2481 {
2482         u16 an_lp_status;
2483         s32 status;
2484         u16 word = hw->eeprom.ctrl_word_3;
2485
2486         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2487
2488         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2489                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2490                                       &an_lp_status);
2491
2492         if (status != IXGBE_SUCCESS)
2493                 return status;
2494
2495         /* If link partner advertised 1G, return 1G */
2496         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2497                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2498                 return status;
2499         }
2500
2501         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2502         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2503             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2504                 return status;
2505
2506         /* Link partner not capable of lower speeds, return 10G */
2507         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2508         return status;
2509 }