drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44
  45 /**
  46  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  47  *  @hw: pointer to hardware structure
  48  *
  49  *  Initialize the function pointers and assign the MAC type for X550.
  50  *  Does not touch the hardware.
  51  **/
  52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  53 {
  54         struct ixgbe_mac_info *mac = &hw->mac;
  55         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  56         s32 ret_val;
  57
  58         DEBUGFUNC("ixgbe_init_ops_X550");
  59
  60         ret_val = ixgbe_init_ops_X540(hw);
  61         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  62         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  63         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  64         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  65         mac->ops.set_source_address_pruning =
  66                         ixgbe_set_source_address_pruning_X550;
  67         mac->ops.set_ethertype_anti_spoofing =
  68                         ixgbe_set_ethertype_anti_spoofing_X550;
  69
  70         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  71         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  72         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  73         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  74         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  75         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  76         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  77         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  78         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  79
  80         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  81         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  82         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  83         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  84         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  85         switch (hw->device_id) {
  86         case IXGBE_DEV_ID_X550EM_X_10G_T:
  87         case IXGBE_DEV_ID_X550EM_A_10G_T:
  88                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  89                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  90                 break;
  91         default:
  92                 break;
  93         }
  94         return ret_val;
  95 }
  96
  97 /**
  98  * ixgbe_read_cs4227 - Read CS4227 register
  99  * @hw: pointer to hardware structure
 100  * @reg: register number to write
 101  * @value: pointer to receive value read
 102  *
 103  * Returns status code
 104  **/
 105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 106 {
 107         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 108 }
 109
 110 /**
 111  * ixgbe_write_cs4227 - Write CS4227 register
 112  * @hw: pointer to hardware structure
 113  * @reg: register number to write
 114  * @value: value to write to register
 115  *
 116  * Returns status code
 117  **/
 118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 119 {
 120         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 121 }
 122
 123 /**
 124  * ixgbe_read_pe - Read register from port expander
 125  * @hw: pointer to hardware structure
 126  * @reg: register number to read
 127  * @value: pointer to receive read value
 128  *
 129  * Returns status code
 130  **/
 131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 132 {
 133         s32 status;
 134
 135         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 136         if (status != IXGBE_SUCCESS)
 137                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 138                               "port expander access failed with %d\n", status);
 139         return status;
 140 }
 141
 142 /**
 143  * ixgbe_write_pe - Write register to port expander
 144  * @hw: pointer to hardware structure
 145  * @reg: register number to write
 146  * @value: value to write
 147  *
 148  * Returns status code
 149  **/
 150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 151 {
 152         s32 status;
 153
 154         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 155         if (status != IXGBE_SUCCESS)
 156                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 157                               "port expander access failed with %d\n", status);
 158         return status;
 159 }
 160
 161 /**
 162  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 163  * @hw: pointer to hardware structure
 164  *
 165  * This function assumes that the caller has acquired the proper semaphore.
 166  * Returns error code
 167  **/
 168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 169 {
 170         s32 status;
 171         u32 retry;
 172         u16 value;
 173         u8 reg;
 174
 175         /* Trigger hard reset. */
 176         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 177         if (status != IXGBE_SUCCESS)
 178                 return status;
 179         reg |= IXGBE_PE_BIT1;
 180         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 181         if (status != IXGBE_SUCCESS)
 182                 return status;
 183
 184         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 185         if (status != IXGBE_SUCCESS)
 186                 return status;
 187         reg &= ~IXGBE_PE_BIT1;
 188         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 189         if (status != IXGBE_SUCCESS)
 190                 return status;
 191
 192         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 193         if (status != IXGBE_SUCCESS)
 194                 return status;
 195         reg &= ~IXGBE_PE_BIT1;
 196         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199
 200         usec_delay(IXGBE_CS4227_RESET_HOLD);
 201
 202         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 203         if (status != IXGBE_SUCCESS)
 204                 return status;
 205         reg |= IXGBE_PE_BIT1;
 206         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 207         if (status != IXGBE_SUCCESS)
 208                 return status;
 209
 210         /* Wait for the reset to complete. */
 211         msec_delay(IXGBE_CS4227_RESET_DELAY);
 212         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 213                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 214                                            &value);
 215                 if (status == IXGBE_SUCCESS &&
 216                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 217                         break;
 218                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 219         }
 220         if (retry == IXGBE_CS4227_RETRIES) {
 221                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 222                         "CS4227 reset did not complete.");
 223                 return IXGBE_ERR_PHY;
 224         }
 225
 226         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 227         if (status != IXGBE_SUCCESS ||
 228             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 229                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 230                         "CS4227 EEPROM did not load successfully.");
 231                 return IXGBE_ERR_PHY;
 232         }
 233
 234         return IXGBE_SUCCESS;
 235 }
 236
 237 /**
 238  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 239  * @hw: pointer to hardware structure
 240  **/
 241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 242 {
 243         s32 status = IXGBE_SUCCESS;
 244         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 245         u16 value = 0;
 246         u8 retry;
 247
 248         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 249                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 250                 if (status != IXGBE_SUCCESS) {
 251                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 252                                 "semaphore failed with %d", status);
 253                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 254                         continue;
 255                 }
 256
 257                 /* Get status of reset flow. */
 258                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 259
 260                 if (status == IXGBE_SUCCESS &&
 261                     value == IXGBE_CS4227_RESET_COMPLETE)
 262                         goto out;
 263
 264                 if (status != IXGBE_SUCCESS ||
 265                     value != IXGBE_CS4227_RESET_PENDING)
 266                         break;
 267
 268                 /* Reset is pending. Wait and check again. */
 269                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 270                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 271         }
 272
 273         /* If still pending, assume other instance failed. */
 274         if (retry == IXGBE_CS4227_RETRIES) {
 275                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 276                 if (status != IXGBE_SUCCESS) {
 277                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 278                                       "semaphore failed with %d", status);
 279                         return;
 280                 }
 281         }
 282
 283         /* Reset the CS4227. */
 284         status = ixgbe_reset_cs4227(hw);
 285         if (status != IXGBE_SUCCESS) {
 286                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 287                         "CS4227 reset failed: %d", status);
 288                 goto out;
 289         }
 290
 291         /* Reset takes so long, temporarily release semaphore in case the
 292          * other driver instance is waiting for the reset indication.
 293          */
 294         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 295                            IXGBE_CS4227_RESET_PENDING);
 296         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 297         msec_delay(10);
 298         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 299         if (status != IXGBE_SUCCESS) {
 300                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 301                         "semaphore failed with %d", status);
 302                 return;
 303         }
 304
 305         /* Record completion for next time. */
 306         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 307                 IXGBE_CS4227_RESET_COMPLETE);
 308
 309 out:
 310         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 311         msec_delay(hw->eeprom.semaphore_delay);
 312 }
 313
 314 /**
 315  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 316  * @hw: pointer to hardware structure
 317  **/
 318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 319 {
 320         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 321
 322         if (hw->bus.lan_id) {
 323                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 324                 esdp |= IXGBE_ESDP_SDP1_DIR;
 325         }
 326         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 327         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 328         IXGBE_WRITE_FLUSH(hw);
 329 }
 330
 331 /**
 332  * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
 333  * @hw: pointer to hardware structure
 334  * @reg_addr: 32 bit address of PHY register to read
 335  * @dev_type: always unused
 336  * @phy_data: Pointer to read data from PHY register
 337  */
 338 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 339                                      u32 dev_type, u16 *phy_data)
 340 {
 341         u32 i, data, command;
 342         UNREFERENCED_1PARAMETER(dev_type);
 343
 344         /* Setup and write the read command */
 345         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 346                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 347                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
 348                   IXGBE_MSCA_MDI_COMMAND;
 349
 350         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 351
 352         /* Check every 10 usec to see if the access completed.
 353          * The MDI Command bit will clear when the operation is
 354          * complete
 355          */
 356         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 357                 usec_delay(10);
 358
 359                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 360                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 361                         break;
 362         }
 363
 364         if (command & IXGBE_MSCA_MDI_COMMAND) {
 365                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 366                               "PHY read command did not complete.\n");
 367                 return IXGBE_ERR_PHY;
 368         }
 369
 370         /* Read operation is complete.  Get the data from MSRWD */
 371         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 372         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 373         *phy_data = (u16)data;
 374
 375         return IXGBE_SUCCESS;
 376 }
 377
 378 /**
 379  * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
 380  * @hw: pointer to hardware structure
 381  * @reg_addr: 32 bit PHY register to write
 382  * @dev_type: always unused
 383  * @phy_data: Data to write to the PHY register
 384  */
 385 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 386                                       u32 dev_type, u16 phy_data)
 387 {
 388         u32 i, command;
 389         UNREFERENCED_1PARAMETER(dev_type);
 390
 391         /* Put the data in the MDI single read and write data register*/
 392         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 393
 394         /* Setup and write the write command */
 395         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 396                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 397                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
 398                   IXGBE_MSCA_MDI_COMMAND;
 399
 400         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 401
 402         /* Check every 10 usec to see if the access completed.
 403          * The MDI Command bit will clear when the operation is
 404          * complete
 405          */
 406         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 407                 usec_delay(10);
 408
 409                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 410                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 411                         break;
 412         }
 413
 414         if (command & IXGBE_MSCA_MDI_COMMAND) {
 415                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 416                               "PHY write cmd didn't complete\n");
 417                 return IXGBE_ERR_PHY;
 418         }
 419
 420         return IXGBE_SUCCESS;
 421 }
 422
 423 /**
 424  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 425  * @hw: pointer to hardware structure
 426  *
 427  * Returns error code
 428  */
 429 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 430 {
 431         switch (hw->device_id) {
 432         case IXGBE_DEV_ID_X550EM_A_SFP:
 433                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
 434                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
 435                 if (hw->bus.lan_id)
 436                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 437                 else
 438                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 439                 return ixgbe_identify_module_generic(hw);
 440         case IXGBE_DEV_ID_X550EM_X_SFP:
 441                 /* set up for CS4227 usage */
 442                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 443                 ixgbe_setup_mux_ctl(hw);
 444                 ixgbe_check_cs4227(hw);
 445                 /* Fallthrough */
 446
 447         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 448                 return ixgbe_identify_module_generic(hw);
 449                 break;
 450         case IXGBE_DEV_ID_X550EM_X_KX4:
 451                 hw->phy.type = ixgbe_phy_x550em_kx4;
 452                 break;
 453         case IXGBE_DEV_ID_X550EM_X_KR:
 454         case IXGBE_DEV_ID_X550EM_A_KR:
 455         case IXGBE_DEV_ID_X550EM_A_KR_L:
 456                 hw->phy.type = ixgbe_phy_x550em_kr;
 457                 break;
 458         case IXGBE_DEV_ID_X550EM_A_10G_T:
 459                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
 460                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
 461        /* Fallthrough to ixgbe_identify_phy_generic */
 462         case IXGBE_DEV_ID_X550EM_A_1G_T:
 463         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 464         case IXGBE_DEV_ID_X550EM_X_1G_T:
 465         case IXGBE_DEV_ID_X550EM_X_10G_T:
 466                 return ixgbe_identify_phy_generic(hw);
 467         default:
 468                 break;
 469         }
 470         return IXGBE_SUCCESS;
 471 }
 472
 473 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 474                                      u32 device_type, u16 *phy_data)
 475 {
 476         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 477         return IXGBE_NOT_IMPLEMENTED;
 478 }
 479
 480 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 481                                       u32 device_type, u16 phy_data)
 482 {
 483         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 484         return IXGBE_NOT_IMPLEMENTED;
 485 }
 486
 487 /**
 488  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 489  * @hw: pointer to the hardware structure
 490  * @addr: I2C bus address to read from
 491  * @reg: I2C device register to read from
 492  * @val: pointer to location to receive read value
 493  *
 494  * Returns an error code on error.
 495  **/
 496 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 497                                            u16 reg, u16 *val)
 498 {
 499         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 500 }
 501
 502 /**
 503  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 504  * @hw: pointer to the hardware structure
 505  * @addr: I2C bus address to read from
 506  * @reg: I2C device register to read from
 507  * @val: pointer to location to receive read value
 508  *
 509  * Returns an error code on error.
 510  **/
 511 STATIC s32
 512 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 513                                          u16 reg, u16 *val)
 514 {
 515         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 516 }
 517
 518 /**
 519  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 520  * @hw: pointer to the hardware structure
 521  * @addr: I2C bus address to write to
 522  * @reg: I2C device register to write to
 523  * @val: value to write
 524  *
 525  * Returns an error code on error.
 526  **/
 527 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 528                                             u8 addr, u16 reg, u16 val)
 529 {
 530         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 531 }
 532
 533 /**
 534  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 535  * @hw: pointer to the hardware structure
 536  * @addr: I2C bus address to write to
 537  * @reg: I2C device register to write to
 538  * @val: value to write
 539  *
 540  * Returns an error code on error.
 541  **/
 542 STATIC s32
 543 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 544                                           u8 addr, u16 reg, u16 val)
 545 {
 546         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 547 }
 548
 549 /**
 550 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 551 *  @hw: pointer to hardware structure
 552 *
 553 *  Initialize the function pointers and for MAC type X550EM.
 554 *  Does not touch the hardware.
 555 **/
 556 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 557 {
 558         struct ixgbe_mac_info *mac = &hw->mac;
 559         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 560         struct ixgbe_phy_info *phy = &hw->phy;
 561         s32 ret_val;
 562
 563         DEBUGFUNC("ixgbe_init_ops_X550EM");
 564
 565         /* Similar to X550 so start there. */
 566         ret_val = ixgbe_init_ops_X550(hw);
 567
 568         /* Since this function eventually calls
 569          * ixgbe_init_ops_540 by design, we are setting
 570          * the pointers to NULL explicitly here to overwrite
 571          * the values being set in the x540 function.
 572          */
 573         /* Thermal sensor not supported in x550EM */
 574         mac->ops.get_thermal_sensor_data = NULL;
 575         mac->ops.init_thermal_sensor_thresh = NULL;
 576         mac->thermal_sensor_enabled = false;
 577
 578         /* FCOE not supported in x550EM */
 579         mac->ops.get_san_mac_addr = NULL;
 580         mac->ops.set_san_mac_addr = NULL;
 581         mac->ops.get_wwn_prefix = NULL;
 582         mac->ops.get_fcoe_boot_status = NULL;
 583
 584         /* IPsec not supported in x550EM */
 585         mac->ops.disable_sec_rx_path = NULL;
 586         mac->ops.enable_sec_rx_path = NULL;
 587
 588         /* AUTOC register is not present in x550EM. */
 589         mac->ops.prot_autoc_read = NULL;
 590         mac->ops.prot_autoc_write = NULL;
 591
 592         /* X550EM bus type is internal*/
 593         hw->bus.type = ixgbe_bus_type_internal;
 594         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 595
 596
 597         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 598         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 599         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 600         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 601         mac->ops.get_supported_physical_layer =
 602                                     ixgbe_get_supported_physical_layer_X550em;
 603
 604         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 605                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 606         else
 607                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 608
 609         switch (hw->device_id) {
 610         case IXGBE_DEV_ID_X550EM_X_KR:
 611         case IXGBE_DEV_ID_X550EM_A_KR:
 612         case IXGBE_DEV_ID_X550EM_A_KR_L:
 613                 break;
 614         default:
 615                 mac->ops.setup_eee = NULL;
 616         }
 617
 618         /* PHY */
 619         phy->ops.init = ixgbe_init_phy_ops_X550em;
 620         phy->ops.identify = ixgbe_identify_phy_x550em;
 621         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 622                 phy->ops.set_phy_power = NULL;
 623
 624
 625         /* EEPROM */
 626         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 627         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 628         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 629         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 630         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 631         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 632         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 633         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 634
 635         return ret_val;
 636 }
 637
 638 /**
 639 *  ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
 640 *  @hw: pointer to hardware structure
 641 *
 642 *  Initialize the function pointers and for MAC type X550EM_a.
 643 *  Does not touch the hardware.
 644 **/
 645 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
 646 {
 647         struct ixgbe_mac_info *mac = &hw->mac;
 648         s32 ret_val;
 649
 650         DEBUGFUNC("ixgbe_init_ops_X550EM_a");
 651
 652         /* Start with generic X550EM init */
 653         ret_val = ixgbe_init_ops_X550EM(hw);
 654
 655         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 656         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 657         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 658         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 659         mac->ops.fc_autoneg = ixgbe_fc_autoneg_x550a;
 660
 661         switch (mac->ops.get_media_type(hw)) {
 662         case ixgbe_media_type_fiber:
 663                 mac->ops.setup_fc = ixgbe_setup_fc_fiber_x550em_a;
 664                 break;
 665         case ixgbe_media_type_backplane:
 666                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
 667                 break;
 668         default:
 669                 break;
 670         }
 671
 672         return ret_val;
 673 }
 674
 675 /**
 676 *  ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
 677 *  @hw: pointer to hardware structure
 678 *
 679 *  Initialize the function pointers and for MAC type X550EM_x.
 680 *  Does not touch the hardware.
 681 **/
 682 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
 683 {
 684         struct ixgbe_mac_info *mac = &hw->mac;
 685         struct ixgbe_link_info *link = &hw->link;
 686         s32 ret_val;
 687
 688         DEBUGFUNC("ixgbe_init_ops_X550EM_x");
 689
 690         /* Start with generic X550EM init */
 691         ret_val = ixgbe_init_ops_X550EM(hw);
 692
 693         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 694         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 695         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 696         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 697         link->ops.read_link = ixgbe_read_i2c_combined_generic;
 698         link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
 699         link->ops.write_link = ixgbe_write_i2c_combined_generic;
 700         link->ops.write_link_unlocked =
 701                                       ixgbe_write_i2c_combined_generic_unlocked;
 702         link->addr = IXGBE_CS4227;
 703
 704         return ret_val;
 705 }
 706
 707 /**
 708  *  ixgbe_dmac_config_X550
 709  *  @hw: pointer to hardware structure
 710  *
 711  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 712  *  When disabling dmac, dmac enable dmac bit is cleared.
 713  **/
 714 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 715 {
 716         u32 reg, high_pri_tc;
 717
 718         DEBUGFUNC("ixgbe_dmac_config_X550");
 719
 720         /* Disable DMA coalescing before configuring */
 721         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 722         reg &= ~IXGBE_DMACR_DMAC_EN;
 723         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 724
 725         /* Disable DMA Coalescing if the watchdog timer is 0 */
 726         if (!hw->mac.dmac_config.watchdog_timer)
 727                 goto out;
 728
 729         ixgbe_dmac_config_tcs_X550(hw);
 730
 731         /* Configure DMA Coalescing Control Register */
 732         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 733
 734         /* Set the watchdog timer in units of 40.96 usec */
 735         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 736         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 737
 738         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 739         /* If fcoe is enabled, set high priority traffic class */
 740         if (hw->mac.dmac_config.fcoe_en) {
 741                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 742                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 743                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 744         }
 745         reg |= IXGBE_DMACR_EN_MNG_IND;
 746
 747         /* Enable DMA coalescing after configuration */
 748         reg |= IXGBE_DMACR_DMAC_EN;
 749         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 750
 751 out:
 752         return IXGBE_SUCCESS;
 753 }
 754
 755 /**
 756  *  ixgbe_dmac_config_tcs_X550
 757  *  @hw: pointer to hardware structure
 758  *
 759  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 760  *  be cleared before configuring.
 761  **/
 762 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 763 {
 764         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 765
 766         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 767
 768         /* Configure DMA coalescing enabled */
 769         switch (hw->mac.dmac_config.link_speed) {
 770         case IXGBE_LINK_SPEED_100_FULL:
 771                 pb_headroom = IXGBE_DMACRXT_100M;
 772                 break;
 773         case IXGBE_LINK_SPEED_1GB_FULL:
 774                 pb_headroom = IXGBE_DMACRXT_1G;
 775                 break;
 776         default:
 777                 pb_headroom = IXGBE_DMACRXT_10G;
 778                 break;
 779         }
 780
 781         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 782                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 783
 784         /* Set the per Rx packet buffer receive threshold */
 785         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 786                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 787                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 788
 789                 if (tc < hw->mac.dmac_config.num_tcs) {
 790                         /* Get Rx PB size */
 791                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 792                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 793                                 IXGBE_RXPBSIZE_SHIFT;
 794
 795                         /* Calculate receive buffer threshold in kilobytes */
 796                         if (rx_pb_size > pb_headroom)
 797                                 rx_pb_size = rx_pb_size - pb_headroom;
 798                         else
 799                                 rx_pb_size = 0;
 800
 801                         /* Minimum of MFS shall be set for DMCTH */
 802                         reg |= (rx_pb_size > maxframe_size_kb) ?
 803                                 rx_pb_size : maxframe_size_kb;
 804                 }
 805                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 806         }
 807         return IXGBE_SUCCESS;
 808 }
 809
 810 /**
 811  *  ixgbe_dmac_update_tcs_X550
 812  *  @hw: pointer to hardware structure
 813  *
 814  *  Disables dmac, updates per TC settings, and then enables dmac.
 815  **/
 816 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 817 {
 818         u32 reg;
 819
 820         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 821
 822         /* Disable DMA coalescing before configuring */
 823         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 824         reg &= ~IXGBE_DMACR_DMAC_EN;
 825         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 826
 827         ixgbe_dmac_config_tcs_X550(hw);
 828
 829         /* Enable DMA coalescing after configuration */
 830         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 831         reg |= IXGBE_DMACR_DMAC_EN;
 832         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 833
 834         return IXGBE_SUCCESS;
 835 }
 836
 837 /**
 838  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 839  *  @hw: pointer to hardware structure
 840  *
 841  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 842  *  ixgbe_hw struct in order to set up EEPROM access.
 843  **/
 844 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 845 {
 846         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 847         u32 eec;
 848         u16 eeprom_size;
 849
 850         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 851
 852         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 853                 eeprom->semaphore_delay = 10;
 854                 eeprom->type = ixgbe_flash;
 855
 856                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 857                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 858                                     IXGBE_EEC_SIZE_SHIFT);
 859                 eeprom->word_size = 1 << (eeprom_size +
 860                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 861
 862                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 863                           eeprom->type, eeprom->word_size);
 864         }
 865
 866         return IXGBE_SUCCESS;
 867 }
 868
 869 /**
 870  * ixgbe_enable_eee_x550 - Enable EEE support
 871  * @hw: pointer to hardware structure
 872  */
 873 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
 874 {
 875         u16 autoneg_eee_reg;
 876         u32 link_reg;
 877         s32 status;
 878
 879         if (hw->mac.type == ixgbe_mac_X550) {
 880                 /* Advertise EEE capability */
 881                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 882                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 883                                      &autoneg_eee_reg);
 884
 885                 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 886                                     IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 887                                     IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 888
 889                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 890                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 891                                       autoneg_eee_reg);
 892                 return IXGBE_SUCCESS;
 893         }
 894
 895         switch (hw->device_id) {
 896         case IXGBE_DEV_ID_X550EM_X_KR:
 897         case IXGBE_DEV_ID_X550EM_A_KR:
 898         case IXGBE_DEV_ID_X550EM_A_KR_L:
 899                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 900                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 901                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 902                 if (status != IXGBE_SUCCESS)
 903                         return status;
 904
 905                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 906                         IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 907
 908                 /* Don't advertise FEC capability when EEE enabled. */
 909                 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 910
 911                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 912                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 913                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 914                 if (status != IXGBE_SUCCESS)
 915                         return status;
 916                 break;
 917         default:
 918                 break;
 919         }
 920
 921         return IXGBE_SUCCESS;
 922 }
 923
 924 /**
 925  * ixgbe_disable_eee_x550 - Disable EEE support
 926  * @hw: pointer to hardware structure
 927  */
 928 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
 929 {
 930         u16 autoneg_eee_reg;
 931         u32 link_reg;
 932         s32 status;
 933
 934         if (hw->mac.type == ixgbe_mac_X550) {
 935                 /* Disable advertised EEE capability */
 936                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 937                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 938                                      &autoneg_eee_reg);
 939
 940                 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 941                                      IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 942                                      IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 943
 944                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 945                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 946                                       autoneg_eee_reg);
 947                 return IXGBE_SUCCESS;
 948         }
 949
 950         switch (hw->device_id) {
 951         case IXGBE_DEV_ID_X550EM_X_KR:
 952         case IXGBE_DEV_ID_X550EM_A_KR:
 953         case IXGBE_DEV_ID_X550EM_A_KR_L:
 954                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 955                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 956                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 957                 if (status != IXGBE_SUCCESS)
 958                         return status;
 959
 960                 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 961                               IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 962
 963                 /* Advertise FEC capability when EEE is disabled. */
 964                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 965
 966                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 967                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 968                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 969                 if (status != IXGBE_SUCCESS)
 970                         return status;
 971                 break;
 972         default:
 973                 break;
 974         }
 975
 976         return IXGBE_SUCCESS;
 977 }
 978
 979 /**
 980  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 981  *  @hw: pointer to the HW structure
 982  *  @enable_eee: boolean flag to enable EEE
 983  *
 984  *  Enable/disable EEE based on enable_eee flag.
 985  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 986  *  are modified.
 987  *
 988  **/
 989 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 990 {
 991         s32 status;
 992         u32 eeer;
 993
 994         DEBUGFUNC("ixgbe_setup_eee_X550");
 995
 996         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 997         /* Enable or disable EEE per flag */
 998         if (enable_eee) {
 999                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1000
1001                 /* Not supported on first revision of X550EM_x. */
1002                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1003                     !(IXGBE_FUSES0_REV_MASK &
1004                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1005                         return IXGBE_SUCCESS;
1006                 status = ixgbe_enable_eee_x550(hw);
1007                 if (status)
1008                         return status;
1009         } else {
1010                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1011
1012                 status = ixgbe_disable_eee_x550(hw);
1013                 if (status)
1014                         return status;
1015         }
1016         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1017
1018         return IXGBE_SUCCESS;
1019 }
1020
1021 /**
1022  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1023  * @hw: pointer to hardware structure
1024  * @enable: enable or disable source address pruning
1025  * @pool: Rx pool to set source address pruning for
1026  **/
1027 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1028                                            unsigned int pool)
1029 {
1030         u64 pfflp;
1031
1032         /* max rx pool is 63 */
1033         if (pool > 63)
1034                 return;
1035
1036         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1037         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1038
1039         if (enable)
1040                 pfflp |= (1ULL << pool);
1041         else
1042                 pfflp &= ~(1ULL << pool);
1043
1044         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1045         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1046 }
1047
1048 /**
1049  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1050  *  @hw: pointer to hardware structure
1051  *  @enable: enable or disable switch for Ethertype anti-spoofing
1052  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1053  *
1054  **/
1055 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1056                 bool enable, int vf)
1057 {
1058         int vf_target_reg = vf >> 3;
1059         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1060         u32 pfvfspoof;
1061
1062         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1063
1064         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1065         if (enable)
1066                 pfvfspoof |= (1 << vf_target_shift);
1067         else
1068                 pfvfspoof &= ~(1 << vf_target_shift);
1069
1070         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1071 }
1072
1073 /**
1074  * ixgbe_iosf_wait - Wait for IOSF command completion
1075  * @hw: pointer to hardware structure
1076  * @ctrl: pointer to location to receive final IOSF control value
1077  *
1078  * Returns failing status on timeout
1079  *
1080  * Note: ctrl can be NULL if the IOSF control register value is not needed
1081  **/
1082 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1083 {
1084         u32 i, command = 0;
1085
1086         /* Check every 10 usec to see if the address cycle completed.
1087          * The SB IOSF BUSY bit will clear when the operation is
1088          * complete
1089          */
1090         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1091                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1092                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1093                         break;
1094                 usec_delay(10);
1095         }
1096         if (ctrl)
1097                 *ctrl = command;
1098         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1099                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1100                 return IXGBE_ERR_PHY;
1101         }
1102
1103         return IXGBE_SUCCESS;
1104 }
1105
1106 /**
1107  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1108  *  device
1109  *  @hw: pointer to hardware structure
1110  *  @reg_addr: 32 bit PHY register to write
1111  *  @device_type: 3 bit device type
1112  *  @data: Data to write to the register
1113  **/
1114 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1115                             u32 device_type, u32 data)
1116 {
1117         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1118         u32 command, error;
1119         s32 ret;
1120
1121         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1122         if (ret != IXGBE_SUCCESS)
1123                 return ret;
1124
1125         ret = ixgbe_iosf_wait(hw, NULL);
1126         if (ret != IXGBE_SUCCESS)
1127                 goto out;
1128
1129         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1130                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1131
1132         /* Write IOSF control register */
1133         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1134
1135         /* Write IOSF data register */
1136         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1137
1138         ret = ixgbe_iosf_wait(hw, &command);
1139
1140         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1141                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1142                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1143                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1144                               "Failed to write, error %x\n", error);
1145                 ret = IXGBE_ERR_PHY;
1146         }
1147
1148 out:
1149         ixgbe_release_swfw_semaphore(hw, gssr);
1150         return ret;
1151 }
1152
1153 /**
1154  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1155  *  device
1156  *  @hw: pointer to hardware structure
1157  *  @reg_addr: 32 bit PHY register to write
1158  *  @device_type: 3 bit device type
1159  *  @phy_data: Pointer to read data from the register
1160  **/
1161 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1162                            u32 device_type, u32 *data)
1163 {
1164         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1165         u32 command, error;
1166         s32 ret;
1167
1168         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1169         if (ret != IXGBE_SUCCESS)
1170                 return ret;
1171
1172         ret = ixgbe_iosf_wait(hw, NULL);
1173         if (ret != IXGBE_SUCCESS)
1174                 goto out;
1175
1176         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1177                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1178
1179         /* Write IOSF control register */
1180         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1181
1182         ret = ixgbe_iosf_wait(hw, &command);
1183
1184         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1185                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1186                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1187                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1188                                 "Failed to read, error %x\n", error);
1189                 ret = IXGBE_ERR_PHY;
1190         }
1191
1192         if (ret == IXGBE_SUCCESS)
1193                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1194
1195 out:
1196         ixgbe_release_swfw_semaphore(hw, gssr);
1197         return ret;
1198 }
1199
1200 /**
1201  * ixgbe_get_phy_token - Get the token for shared phy access
1202  * @hw: Pointer to hardware structure
1203  */
1204
1205 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1206 {
1207         struct ixgbe_hic_phy_token_req token_cmd;
1208         s32 status;
1209
1210         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1211         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1212         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1213         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1214         token_cmd.port_number = hw->bus.lan_id;
1215         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1216         token_cmd.pad = 0;
1217         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1218                                               sizeof(token_cmd),
1219                                               IXGBE_HI_COMMAND_TIMEOUT,
1220                                               true);
1221         if (status)
1222                 return status;
1223         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1224                 return IXGBE_SUCCESS;
1225         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1226                 return IXGBE_ERR_FW_RESP_INVALID;
1227
1228         return IXGBE_ERR_TOKEN_RETRY;
1229 }
1230
1231 /**
1232  * ixgbe_put_phy_token - Put the token for shared phy access
1233  * @hw: Pointer to hardware structure
1234  */
1235
1236 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1237 {
1238         struct ixgbe_hic_phy_token_req token_cmd;
1239         s32 status;
1240
1241         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1242         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1243         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1244         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1245         token_cmd.port_number = hw->bus.lan_id;
1246         token_cmd.command_type = FW_PHY_TOKEN_REL;
1247         token_cmd.pad = 0;
1248         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1249                                               sizeof(token_cmd),
1250                                               IXGBE_HI_COMMAND_TIMEOUT,
1251                                               true);
1252         if (status)
1253                 return status;
1254         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1255                 return IXGBE_SUCCESS;
1256
1257         DEBUGOUT("Put PHY Token host interface command failed");
1258         return IXGBE_ERR_FW_RESP_INVALID;
1259 }
1260
1261 /**
1262  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1263  *  of the IOSF device
1264  *  @hw: pointer to hardware structure
1265  *  @reg_addr: 32 bit PHY register to write
1266  *  @device_type: 3 bit device type
1267  *  @data: Data to write to the register
1268  **/
1269 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1270                                   u32 device_type, u32 data)
1271 {
1272         struct ixgbe_hic_internal_phy_req write_cmd;
1273         s32 status;
1274         UNREFERENCED_1PARAMETER(device_type);
1275
1276         memset(&write_cmd, 0, sizeof(write_cmd));
1277         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1278         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1279         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1280         write_cmd.port_number = hw->bus.lan_id;
1281         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1282         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1283         write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1284
1285         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1286                                               sizeof(write_cmd),
1287                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1288
1289         return status;
1290 }
1291
1292 /**
1293  *  ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
1294  *  of the IOSF device.
1295  *  @hw: pointer to hardware structure
1296  *  @reg_addr: 32 bit PHY register to write
1297  *  @device_type: 3 bit device type
1298  *  @data: Pointer to read data from the register
1299  **/
1300 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1301                                  u32 device_type, u32 *data)
1302 {
1303         union {
1304                 struct ixgbe_hic_internal_phy_req cmd;
1305                 struct ixgbe_hic_internal_phy_resp rsp;
1306         } hic;
1307         s32 status;
1308         UNREFERENCED_1PARAMETER(device_type);
1309
1310         memset(&hic, 0, sizeof(hic));
1311         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1312         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1313         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1314         hic.cmd.port_number = hw->bus.lan_id;
1315         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1316         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1317
1318         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1319                                               sizeof(hic.cmd),
1320                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1321
1322         /* Extract the register value from the response. */
1323         *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1324
1325         return status;
1326 }
1327
1328 /**
1329  *  ixgbe_disable_mdd_X550
1330  *  @hw: pointer to hardware structure
1331  *
1332  *  Disable malicious driver detection
1333  **/
1334 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1335 {
1336         u32 reg;
1337
1338         DEBUGFUNC("ixgbe_disable_mdd_X550");
1339
1340         /* Disable MDD for TX DMA and interrupt */
1341         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1342         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1343         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1344
1345         /* Disable MDD for RX and interrupt */
1346         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1347         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1348         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1349 }
1350
1351 /**
1352  *  ixgbe_enable_mdd_X550
1353  *  @hw: pointer to hardware structure
1354  *
1355  *  Enable malicious driver detection
1356  **/
1357 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1358 {
1359         u32 reg;
1360
1361         DEBUGFUNC("ixgbe_enable_mdd_X550");
1362
1363         /* Enable MDD for TX DMA and interrupt */
1364         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1365         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1366         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1367
1368         /* Enable MDD for RX and interrupt */
1369         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1370         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1371         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1372 }
1373
1374 /**
1375  *  ixgbe_restore_mdd_vf_X550
1376  *  @hw: pointer to hardware structure
1377  *  @vf: vf index
1378  *
1379  *  Restore VF that was disabled during malicious driver detection event
1380  **/
1381 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1382 {
1383         u32 idx, reg, num_qs, start_q, bitmask;
1384
1385         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1386
1387         /* Map VF to queues */
1388         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1389         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1390         case IXGBE_MRQC_VMDQRT8TCEN:
1391                 num_qs = 8;  /* 16 VFs / pools */
1392                 bitmask = 0x000000FF;
1393                 break;
1394         case IXGBE_MRQC_VMDQRSS32EN:
1395         case IXGBE_MRQC_VMDQRT4TCEN:
1396                 num_qs = 4;  /* 32 VFs / pools */
1397                 bitmask = 0x0000000F;
1398                 break;
1399         default:            /* 64 VFs / pools */
1400                 num_qs = 2;
1401                 bitmask = 0x00000003;
1402                 break;
1403         }
1404         start_q = vf * num_qs;
1405
1406         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1407         idx = start_q / 32;
1408         reg = 0;
1409         reg |= (bitmask << (start_q % 32));
1410         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1411         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1412 }
1413
1414 /**
1415  *  ixgbe_mdd_event_X550
1416  *  @hw: pointer to hardware structure
1417  *  @vf_bitmap: vf bitmap of malicious vfs
1418  *
1419  *  Handle malicious driver detection event.
1420  **/
1421 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1422 {
1423         u32 wqbr;
1424         u32 i, j, reg, q, shift, vf, idx;
1425
1426         DEBUGFUNC("ixgbe_mdd_event_X550");
1427
1428         /* figure out pool size for mapping to vf's */
1429         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1430         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1431         case IXGBE_MRQC_VMDQRT8TCEN:
1432                 shift = 3;  /* 16 VFs / pools */
1433                 break;
1434         case IXGBE_MRQC_VMDQRSS32EN:
1435         case IXGBE_MRQC_VMDQRT4TCEN:
1436                 shift = 2;  /* 32 VFs / pools */
1437                 break;
1438         default:
1439                 shift = 1;  /* 64 VFs / pools */
1440                 break;
1441         }
1442
1443         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1444         for (i = 0; i < 4; i++) {
1445                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1446                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1447
1448                 if (!wqbr)
1449                         continue;
1450
1451                 /* Get malicious queue */
1452                 for (j = 0; j < 32 && wqbr; j++) {
1453
1454                         if (!(wqbr & (1 << j)))
1455                                 continue;
1456
1457                         /* Get queue from bitmask */
1458                         q = j + (i * 32);
1459
1460                         /* Map queue to vf */
1461                         vf = (q >> shift);
1462
1463                         /* Set vf bit in vf_bitmap */
1464                         idx = vf / 32;
1465                         vf_bitmap[idx] |= (1 << (vf % 32));
1466                         wqbr &= ~(1 << j);
1467                 }
1468         }
1469 }
1470
1471 /**
1472  *  ixgbe_get_media_type_X550em - Get media type
1473  *  @hw: pointer to hardware structure
1474  *
1475  *  Returns the media type (fiber, copper, backplane)
1476  */
1477 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1478 {
1479         enum ixgbe_media_type media_type;
1480
1481         DEBUGFUNC("ixgbe_get_media_type_X550em");
1482
1483         /* Detect if there is a copper PHY attached. */
1484         switch (hw->device_id) {
1485         case IXGBE_DEV_ID_X550EM_X_KR:
1486         case IXGBE_DEV_ID_X550EM_X_KX4:
1487         case IXGBE_DEV_ID_X550EM_A_KR:
1488         case IXGBE_DEV_ID_X550EM_A_KR_L:
1489                 media_type = ixgbe_media_type_backplane;
1490                 break;
1491         case IXGBE_DEV_ID_X550EM_X_SFP:
1492         case IXGBE_DEV_ID_X550EM_A_SFP:
1493         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1494         case IXGBE_DEV_ID_X550EM_A_QSFP:
1495         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1496                 media_type = ixgbe_media_type_fiber;
1497                 break;
1498         case IXGBE_DEV_ID_X550EM_X_1G_T:
1499         case IXGBE_DEV_ID_X550EM_X_10G_T:
1500         case IXGBE_DEV_ID_X550EM_A_10G_T:
1501                 media_type = ixgbe_media_type_copper;
1502                 break;
1503         case IXGBE_DEV_ID_X550EM_A_SGMII:
1504         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1505                 media_type = ixgbe_media_type_backplane;
1506                 hw->phy.type = ixgbe_phy_sgmii;
1507                 break;
1508         case IXGBE_DEV_ID_X550EM_A_1G_T:
1509         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1510                 media_type = ixgbe_media_type_copper;
1511                 break;
1512         default:
1513                 media_type = ixgbe_media_type_unknown;
1514                 break;
1515         }
1516         return media_type;
1517 }
1518
1519 /**
1520  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1521  *  @hw: pointer to hardware structure
1522  *  @linear: true if SFP module is linear
1523  */
1524 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1525 {
1526         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1527
1528         switch (hw->phy.sfp_type) {
1529         case ixgbe_sfp_type_not_present:
1530                 return IXGBE_ERR_SFP_NOT_PRESENT;
1531         case ixgbe_sfp_type_da_cu_core0:
1532         case ixgbe_sfp_type_da_cu_core1:
1533                 *linear = true;
1534                 break;
1535         case ixgbe_sfp_type_srlr_core0:
1536         case ixgbe_sfp_type_srlr_core1:
1537         case ixgbe_sfp_type_da_act_lmt_core0:
1538         case ixgbe_sfp_type_da_act_lmt_core1:
1539         case ixgbe_sfp_type_1g_sx_core0:
1540         case ixgbe_sfp_type_1g_sx_core1:
1541         case ixgbe_sfp_type_1g_lx_core0:
1542         case ixgbe_sfp_type_1g_lx_core1:
1543                 *linear = false;
1544                 break;
1545         case ixgbe_sfp_type_unknown:
1546         case ixgbe_sfp_type_1g_cu_core0:
1547         case ixgbe_sfp_type_1g_cu_core1:
1548         default:
1549                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1550         }
1551
1552         return IXGBE_SUCCESS;
1553 }
1554
1555 /**
1556  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1557  *  @hw: pointer to hardware structure
1558  *
1559  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1560  **/
1561 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1562 {
1563         s32 status;
1564         bool linear;
1565
1566         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1567
1568         status = ixgbe_identify_module_generic(hw);
1569
1570         if (status != IXGBE_SUCCESS)
1571                 return status;
1572
1573         /* Check if SFP module is supported */
1574         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1575
1576         return status;
1577 }
1578
1579 /**
1580  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1581  *  @hw: pointer to hardware structure
1582  */
1583 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1584 {
1585         s32 status;
1586         bool linear;
1587
1588         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1589
1590         /* Check if SFP module is supported */
1591         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1592
1593         if (status != IXGBE_SUCCESS)
1594                 return status;
1595
1596         ixgbe_init_mac_link_ops_X550em(hw);
1597         hw->phy.ops.reset = NULL;
1598
1599         return IXGBE_SUCCESS;
1600 }
1601
1602 /**
1603  * ixgbe_setup_sgmii - Set up link for sgmii
1604  * @hw: pointer to hardware structure
1605  */
1606 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1607                              bool autoneg_wait)
1608 {
1609         struct ixgbe_mac_info *mac = &hw->mac;
1610         u32 lval, sval;
1611         s32 rc;
1612
1613         rc = mac->ops.read_iosf_sb_reg(hw,
1614                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1615                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1616         if (rc)
1617                 return rc;
1618
1619         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1620         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1621         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1622         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1623         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1624         rc = mac->ops.write_iosf_sb_reg(hw,
1625                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1626                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1627         if (rc)
1628                 return rc;
1629
1630         rc = mac->ops.read_iosf_sb_reg(hw,
1631                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1632                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1633         if (rc)
1634                 return rc;
1635
1636         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1637         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1638         rc = mac->ops.write_iosf_sb_reg(hw,
1639                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1640                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1641         if (rc)
1642                 return rc;
1643
1644         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1645         rc = mac->ops.write_iosf_sb_reg(hw,
1646                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1647                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1648         if (rc)
1649                 return rc;
1650
1651         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1652 }
1653
1654  /**
1655  * ixgbe_setup_sgmii_m88 - Set up link for sgmii with Marvell PHYs
1656  * @hw: pointer to hardware structure
1657  */
1658 STATIC s32 ixgbe_setup_sgmii_m88(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1659                                  bool autoneg_wait)
1660 {
1661         struct ixgbe_mac_info *mac = &hw->mac;
1662         u32 lval, sval;
1663         s32 rc;
1664
1665         rc = mac->ops.read_iosf_sb_reg(hw,
1666                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1667                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1668         if (rc)
1669                 return rc;
1670
1671         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1672         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1673         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1674         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1675         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1676         rc = mac->ops.write_iosf_sb_reg(hw,
1677                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1678                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1679         if (rc)
1680                 return rc;
1681
1682         rc = mac->ops.read_iosf_sb_reg(hw,
1683                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1684                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1685         if (rc)
1686                 return rc;
1687
1688         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1689         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1690         rc = mac->ops.write_iosf_sb_reg(hw,
1691                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1692                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1693         if (rc)
1694                 return rc;
1695
1696         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1697         rc = mac->ops.write_iosf_sb_reg(hw,
1698                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1699                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1700         if (rc)
1701                 return rc;
1702
1703         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1704 }
1705
1706 /**
1707  * ixgbe_check_link_m88 - Poll PHY for link
1708  * @hw: pointer to hardware structure
1709  * @speed: pointer to link speed
1710  * @link_up: true when link is up
1711  * @link_up_wait: bool indicating whether to wait for link
1712  *
1713  * Check that both the MAC and PHY have link.
1714  */
1715 static s32
1716 ixgbe_check_link_m88(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1717                      bool *link_up, bool link_up_wait)
1718 {
1719         u16 reg;
1720         s32 rc;
1721         u32 i;
1722
1723         rc = ixgbe_check_mac_link_generic(hw, speed, link_up, link_up_wait);
1724         if (rc || !*link_up)
1725                 return rc;
1726
1727         rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_PHY_SPEC_STATUS, 0, &reg);
1728
1729         /* MAC link is up, so check external PHY link */
1730         *link_up = !!(reg & IXGBE_M88E1500_PHY_SPEC_STATUS_LINK);
1731
1732         if (link_up_wait) {
1733                 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
1734                         if (!rc &&
1735                             (reg & IXGBE_M88E1500_PHY_SPEC_STATUS_LINK)) {
1736                                 *link_up = true;
1737                                 break;
1738                         }
1739                         *link_up = false;
1740                         msec_delay(100);
1741                         rc = hw->phy.ops.read_reg(hw,
1742                                                  IXGBE_M88E1500_PHY_SPEC_STATUS,
1743                                                  0, &reg);
1744                 }
1745         }
1746
1747 #define M88_SPEED(x) (IXGBE_M88E1500_PHY_SPEC_STATUS_RESOLVED  | \
1748                       IXGBE_M88E1500_PHY_SPEC_STATUS_DUPLEX     | \
1749                       ((IXGBE_M88E1500_PHY_SPEC_STATUS_SPEED_##x) <<\
1750                         IXGBE_M88E1500_PHY_SPEC_STATUS_SPEED_SHIFT))
1751
1752         reg &= M88_SPEED(MASK);
1753         switch (reg) {
1754         case M88_SPEED(10):
1755                 *speed = IXGBE_LINK_SPEED_10_FULL;
1756                 break;
1757         case M88_SPEED(100):
1758                 *speed = IXGBE_LINK_SPEED_100_FULL;
1759                 break;
1760         case M88_SPEED(1000):
1761                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1762                 break;
1763         default:
1764                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1765                 break;
1766         }
1767 #undef M88_SPEED
1768
1769         return rc;
1770 }
1771
1772 /**
1773  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1774  *  @hw: pointer to hardware structure
1775  */
1776 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1777 {
1778         struct ixgbe_mac_info *mac = &hw->mac;
1779
1780         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1781
1782         switch (hw->mac.ops.get_media_type(hw)) {
1783         case ixgbe_media_type_fiber:
1784                 /* CS4227 does not support autoneg, so disable the laser control
1785                  * functions for SFP+ fiber
1786                  */
1787                 mac->ops.disable_tx_laser = NULL;
1788                 mac->ops.enable_tx_laser = NULL;
1789                 mac->ops.flap_tx_laser = NULL;
1790                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1791                 mac->ops.set_rate_select_speed =
1792                                         ixgbe_set_soft_rate_select_speed;
1793                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1794                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1795                         mac->ops.setup_mac_link =
1796                                 ixgbe_setup_mac_link_sfp_x550a;
1797                 else
1798                         mac->ops.setup_mac_link =
1799                                 ixgbe_setup_mac_link_sfp_x550em;
1800                 break;
1801         case ixgbe_media_type_copper:
1802                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1803                     hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1804                         mac->ops.setup_link = ixgbe_setup_sgmii_m88;
1805                         mac->ops.check_link = ixgbe_check_link_m88;
1806                 } else {
1807                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1808                         mac->ops.check_link = ixgbe_check_link_t_X550em;
1809                 }
1810                 break;
1811         case ixgbe_media_type_backplane:
1812                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1813                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1814                         mac->ops.setup_link = ixgbe_setup_sgmii;
1815                 break;
1816         default:
1817                 break;
1818         }
1819 }
1820
1821 /**
1822  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1823  *  @hw: pointer to hardware structure
1824  *  @speed: pointer to link speed
1825  *  @autoneg: true when autoneg or autotry is enabled
1826  */
1827 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1828                                        ixgbe_link_speed *speed,
1829                                        bool *autoneg)
1830 {
1831         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1832
1833         /* SFP */
1834         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1835
1836                 /* CS4227 SFP must not enable auto-negotiation */
1837                 *autoneg = false;
1838
1839                 /* Check if 1G SFP module. */
1840                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1841                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1842                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1843                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1844                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1845                         return IXGBE_SUCCESS;
1846                 }
1847
1848                 /* Link capabilities are based on SFP */
1849                 if (hw->phy.multispeed_fiber)
1850                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1851                                  IXGBE_LINK_SPEED_1GB_FULL;
1852                 else
1853                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1854         } else {
1855                 switch (hw->phy.type) {
1856                 case ixgbe_phy_m88:
1857                         *speed = IXGBE_LINK_SPEED_1GB_FULL |
1858                                  IXGBE_LINK_SPEED_100_FULL |
1859                                  IXGBE_LINK_SPEED_10_FULL;
1860                         break;
1861                 case ixgbe_phy_sgmii:
1862                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1863                         break;
1864                 default:
1865                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1866                                  IXGBE_LINK_SPEED_1GB_FULL;
1867                         break;
1868                 }
1869                 *autoneg = true;
1870         }
1871
1872         return IXGBE_SUCCESS;
1873 }
1874
1875 /**
1876  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1877  * @hw: pointer to hardware structure
1878  * @lsc: pointer to boolean flag which indicates whether external Base T
1879  *       PHY interrupt is lsc
1880  *
1881  * Determime if external Base T PHY interrupt cause is high temperature
1882  * failure alarm or link status change.
1883  *
1884  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1885  * failure alarm, else return PHY access status.
1886  */
1887 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1888 {
1889         u32 status;
1890         u16 reg;
1891
1892         *lsc = false;
1893
1894         /* Vendor alarm triggered */
1895         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1896                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1897                                       &reg);
1898
1899         if (status != IXGBE_SUCCESS ||
1900             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1901                 return status;
1902
1903         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1904         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1905                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1906                                       &reg);
1907
1908         if (status != IXGBE_SUCCESS ||
1909             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1910             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1911                 return status;
1912
1913         /* Global alarm triggered */
1914         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1915                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1916                                       &reg);
1917
1918         if (status != IXGBE_SUCCESS)
1919                 return status;
1920
1921         /* If high temperature failure, then return over temp error and exit */
1922         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1923                 /* power down the PHY in case the PHY FW didn't already */
1924                 ixgbe_set_copper_phy_power(hw, false);
1925                 return IXGBE_ERR_OVERTEMP;
1926         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1927                 /*  device fault alarm triggered */
1928                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1929                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1930                                           &reg);
1931
1932                 if (status != IXGBE_SUCCESS)
1933                         return status;
1934
1935                 /* if device fault was due to high temp alarm handle and exit */
1936                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1937                         /* power down the PHY in case the PHY FW didn't */
1938                         ixgbe_set_copper_phy_power(hw, false);
1939                         return IXGBE_ERR_OVERTEMP;
1940                 }
1941         }
1942
1943         /* Vendor alarm 2 triggered */
1944         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1945                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1946
1947         if (status != IXGBE_SUCCESS ||
1948             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1949                 return status;
1950
1951         /* link connect/disconnect event occurred */
1952         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1953                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1954
1955         if (status != IXGBE_SUCCESS)
1956                 return status;
1957
1958         /* Indicate LSC */
1959         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1960                 *lsc = true;
1961
1962         return IXGBE_SUCCESS;
1963 }
1964
1965 /**
1966  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1967  * @hw: pointer to hardware structure
1968  *
1969  * Enable link status change and temperature failure alarm for the external
1970  * Base T PHY
1971  *
1972  * Returns PHY access status
1973  */
1974 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1975 {
1976         u32 status;
1977         u16 reg;
1978         bool lsc;
1979
1980         /* Clear interrupt flags */
1981         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1982
1983         /* Enable link status change alarm */
1984         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1985                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1986
1987         if (status != IXGBE_SUCCESS)
1988                 return status;
1989
1990         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1991
1992         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1993                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1994
1995         if (status != IXGBE_SUCCESS)
1996                 return status;
1997
1998         /* Enable high temperature failure and global fault alarms */
1999         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2000                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2001                                       &reg);
2002
2003         if (status != IXGBE_SUCCESS)
2004                 return status;
2005
2006         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2007                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2008
2009         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2010                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2011                                        reg);
2012
2013         if (status != IXGBE_SUCCESS)
2014                 return status;
2015
2016         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2017         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2018                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2019                                       &reg);
2020
2021         if (status != IXGBE_SUCCESS)
2022                 return status;
2023
2024         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2025                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2026
2027         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2028                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2029                                        reg);
2030
2031         if (status != IXGBE_SUCCESS)
2032                 return status;
2033
2034         /* Enable chip-wide vendor alarm */
2035         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2036                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2037                                       &reg);
2038
2039         if (status != IXGBE_SUCCESS)
2040                 return status;
2041
2042         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2043
2044         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2045                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2046                                        reg);
2047
2048         return status;
2049 }
2050
2051 /**
2052  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2053  *  @hw: pointer to hardware structure
2054  *  @speed: link speed
2055  *
2056  *  Configures the integrated KR PHY.
2057  **/
2058 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2059                                        ixgbe_link_speed speed)
2060 {
2061         s32 status;
2062         u32 reg_val;
2063
2064         status = hw->mac.ops.read_iosf_sb_reg(hw,
2065                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2066                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2067         if (status)
2068                 return status;
2069
2070         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2071         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2072                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2073
2074         /* Advertise 10G support. */
2075         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2076                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2077
2078         /* Advertise 1G support. */
2079         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2080                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2081
2082         /* Restart auto-negotiation. */
2083         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2084         status = hw->mac.ops.write_iosf_sb_reg(hw,
2085                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2086                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2087
2088         return status;
2089 }
2090
2091 /**
2092  * ixgbe_setup_m88 - setup m88 PHY
2093  * @hw: pointer to hardware structure
2094  */
2095 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2096 {
2097         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2098         u16 reg;
2099         s32 rc;
2100
2101         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2102                 return IXGBE_SUCCESS;
2103
2104         rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2105         if (rc)
2106                 return rc;
2107
2108         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2109         if (rc)
2110                 goto out;
2111         if (reg & IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN) {
2112                 reg &= ~IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN;
2113                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2114                                           reg);
2115         }
2116
2117         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, &reg);
2118         if (rc)
2119                 goto out;
2120         if (reg & IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN) {
2121                 reg &= ~IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN;
2122                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0,
2123                                           reg);
2124         }
2125
2126         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 2);
2127         if (rc)
2128                 goto out;
2129
2130         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2131                                       &reg);
2132         if (rc)
2133                 goto out;
2134         if (reg & IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN) {
2135                 reg &= ~IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN;
2136                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2137                                           reg);
2138                 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2139                                                0);
2140                 if (rc)
2141                         goto out;
2142                 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2143                                               &reg);
2144                 if (rc)
2145                         goto out;
2146                 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2147                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2148                                           reg);
2149                 usec_delay(50);
2150         } else {
2151                 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2152                                                0);
2153                 if (rc)
2154                         goto out;
2155         }
2156
2157         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2158         if (rc)
2159                 goto out;
2160
2161         if (!(reg & IXGBE_M88E1500_COPPER_CTRL_AN_EN)) {
2162                 reg |= IXGBE_M88E1500_COPPER_CTRL_AN_EN;
2163                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2164                                           reg);
2165         }
2166
2167         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, &reg);
2168         if (rc)
2169                 goto out;
2170         reg &= ~IXGBE_M88E1500_1000T_CTRL_HALF_DUPLEX;
2171         reg &= ~IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2172         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
2173                 reg |= IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2174         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, reg);
2175
2176         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, &reg);
2177         if (rc)
2178                 goto out;
2179         reg &= ~IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
2180         reg &= ~IXGBE_M88E1500_COPPER_AN_PAUSE;
2181         reg &= ~IXGBE_M88E1500_COPPER_AN_T4;
2182         reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_FD;
2183         reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_HD;
2184         reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_FD;
2185         reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_HD;
2186         switch (hw->fc.current_mode) {
2187         case ixgbe_fc_full:
2188                 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
2189                 break;
2190         case ixgbe_fc_rx_pause:
2191                 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
2192                 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
2193                 break;
2194         case ixgbe_fc_tx_pause:
2195                 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
2196                 break;
2197         default:
2198                 break;
2199         }
2200
2201         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
2202                 reg |= IXGBE_M88E1500_COPPER_AN_100TX_FD;
2203         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
2204                 reg |= IXGBE_M88E1500_COPPER_AN_10TX_FD;
2205         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, reg);
2206
2207         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2208         if (rc)
2209                 goto out;
2210         reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
2211         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2212
2213
2214         hw->mac.ops.release_swfw_sync(hw, mask);
2215         return rc;
2216
2217 out:
2218         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2219         hw->mac.ops.release_swfw_sync(hw, mask);
2220         return rc;
2221 }
2222
2223 /**
2224  * ixgbe_reset_phy_m88e1500 - Reset m88e1500 PHY
2225  * @hw: pointer to hardware structure
2226  *
2227  * The PHY token must be held when calling this function.
2228  */
2229 static s32 ixgbe_reset_phy_m88e1500(struct ixgbe_hw *hw)
2230 {
2231         u16 reg;
2232         s32 rc;
2233
2234         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2235         if (rc)
2236                 return rc;
2237
2238         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2239         if (rc)
2240                 return rc;
2241
2242         reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2243         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2244
2245         usec_delay(10);
2246
2247         return rc;
2248 }
2249
2250 /**
2251  * ixgbe_reset_phy_m88e1543 - Reset m88e1543 PHY
2252  * @hw: pointer to hardware structure
2253  *
2254  * The PHY token must be held when calling this function.
2255  */
2256 static s32 ixgbe_reset_phy_m88e1543(struct ixgbe_hw *hw)
2257 {
2258         return hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2259 }
2260
2261 /**
2262  * ixgbe_reset_phy_m88 - Reset m88 PHY
2263  * @hw: pointer to hardware structure
2264  */
2265 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2266 {
2267         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2268         u16 reg;
2269         s32 rc;
2270
2271         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2272                 return IXGBE_SUCCESS;
2273
2274         rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2275         if (rc)
2276                 return rc;
2277
2278         switch (hw->phy.id) {
2279         case IXGBE_M88E1500_E_PHY_ID:
2280                 rc = ixgbe_reset_phy_m88e1500(hw);
2281                 break;
2282         case IXGBE_M88E1543_E_PHY_ID:
2283                 rc = ixgbe_reset_phy_m88e1543(hw);
2284                 break;
2285         default:
2286                 rc = IXGBE_ERR_PHY;
2287                 break;
2288         }
2289
2290         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2291         if (rc)
2292                 goto out;
2293
2294         reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2295               IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2296               IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2297         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2298         if (rc)
2299                 goto out;
2300
2301         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2302         if (rc)
2303                 goto out;
2304
2305         reg = IXGBE_M88E1500_GEN_CTRL_RESET |
2306               IXGBE_M88E1500_GEN_CTRL_MODE_SGMII_COPPER;
2307         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_GEN_CTRL, 0, reg);
2308         if (rc)
2309                 goto out;
2310
2311         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2312         if (rc)
2313                 goto out;
2314
2315         reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2316               IXGBE_M88E1500_FIBER_CTRL_AN_EN |
2317               IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2318               IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2319         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2320         if (rc)
2321                 goto out;
2322
2323         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2324         if (rc)
2325                 goto out;
2326
2327         reg = (IXGBE_M88E1500_MAC_CTRL_1_DWN_4X <<
2328                IXGBE_M88E1500_MAC_CTRL_1_DWN_SHIFT) |
2329               (IXGBE_M88E1500_MAC_CTRL_1_ED_TM <<
2330                IXGBE_M88E1500_MAC_CTRL_1_ED_SHIFT) |
2331               (IXGBE_M88E1500_MAC_CTRL_1_MDIX_AUTO <<
2332                IXGBE_M88E1500_MAC_CTRL_1_MDIX_SHIFT);
2333         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, reg);
2334         if (rc)
2335                 goto out;
2336
2337         reg = IXGBE_M88E1500_COPPER_CTRL_RESET |
2338               IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2339               IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2340               IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2341               IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB;
2342         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2343         if (rc)
2344                 goto out;
2345
2346         hw->mac.ops.release_swfw_sync(hw, mask);
2347
2348         return ixgbe_setup_m88(hw);
2349
2350 out:
2351         hw->mac.ops.release_swfw_sync(hw, mask);
2352         return rc;
2353 }
2354
2355 /**
2356  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2357  *  @hw: pointer to hardware structure
2358  *
2359  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2360  *  values.
2361  **/
2362 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2363 {
2364         /* Save NW management interface connected on board. This is used
2365          * to determine internal PHY mode.
2366          */
2367         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2368
2369         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2370          * PHY address. This register field was has only been used for X552.
2371          */
2372         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2373             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2374                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2375                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2376                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2377         }
2378
2379         return IXGBE_SUCCESS;
2380 }
2381
2382 /**
2383  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2384  *  @hw: pointer to hardware structure
2385  *
2386  *  Initialize any function pointers that were not able to be
2387  *  set during init_shared_code because the PHY/SFP type was
2388  *  not known.  Perform the SFP init if necessary.
2389  */
2390 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2391 {
2392         struct ixgbe_phy_info *phy = &hw->phy;
2393         s32 ret_val;
2394
2395         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2396
2397         hw->mac.ops.set_lan_id(hw);
2398
2399         ixgbe_read_mng_if_sel_x550em(hw);
2400
2401         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2402                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2403                 ixgbe_setup_mux_ctl(hw);
2404                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2405         }
2406
2407         switch (hw->device_id) {
2408         case IXGBE_DEV_ID_X550EM_A_1G_T:
2409         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2410                 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2411                 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2412                 break;
2413         default:
2414                 break;
2415         }
2416
2417         /* Identify the PHY or SFP module */
2418         ret_val = phy->ops.identify(hw);
2419         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2420                 return ret_val;
2421
2422         /* Setup function pointers based on detected hardware */
2423         ixgbe_init_mac_link_ops_X550em(hw);
2424         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2425                 phy->ops.reset = NULL;
2426
2427         /* Set functions pointers based on phy type */
2428         switch (hw->phy.type) {
2429         case ixgbe_phy_x550em_kx4:
2430                 phy->ops.setup_link = NULL;
2431                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2432                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2433                 break;
2434         case ixgbe_phy_x550em_kr:
2435                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2436                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2437                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2438                 break;
2439         case ixgbe_phy_x550em_ext_t:
2440                 /* If internal link mode is XFI, then setup iXFI internal link,
2441                  * else setup KR now.
2442                  */
2443                 phy->ops.setup_internal_link =
2444                                               ixgbe_setup_internal_phy_t_x550em;
2445
2446                 /* setup SW LPLU only for first revision of X550EM_x */
2447                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2448                     !(IXGBE_FUSES0_REV_MASK &
2449                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2450                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2451
2452                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2453                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2454                 break;
2455         case ixgbe_phy_sgmii:
2456                 phy->ops.setup_link = NULL;
2457                 break;
2458         case ixgbe_phy_m88:
2459                 phy->ops.setup_link = ixgbe_setup_m88;
2460                 phy->ops.reset = ixgbe_reset_phy_m88;
2461                 break;
2462         default:
2463                 break;
2464         }
2465         return ret_val;
2466 }
2467
2468 /**
2469  * ixgbe_set_mdio_speed - Set MDIO clock speed
2470  *  @hw: pointer to hardware structure
2471  */
2472 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2473 {
2474         u32 hlreg0;
2475
2476         switch (hw->device_id) {
2477         case IXGBE_DEV_ID_X550EM_X_10G_T:
2478         case IXGBE_DEV_ID_X550EM_A_SGMII:
2479         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2480         case IXGBE_DEV_ID_X550EM_A_1G_T:
2481         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2482         case IXGBE_DEV_ID_X550EM_A_10G_T:
2483         case IXGBE_DEV_ID_X550EM_A_SFP:
2484         case IXGBE_DEV_ID_X550EM_A_QSFP:
2485                 /* Config MDIO clock speed before the first MDIO PHY access */
2486                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2487                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2488                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2489                 break;
2490         default:
2491                 break;
2492         }
2493 }
2494
2495 /**
2496  *  ixgbe_reset_hw_X550em - Perform hardware reset
2497  *  @hw: pointer to hardware structure
2498  *
2499  *  Resets the hardware by resetting the transmit and receive units, masks
2500  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2501  *  reset.
2502  */
2503 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2504 {
2505         ixgbe_link_speed link_speed;
2506         s32 status;
2507         u32 ctrl = 0;
2508         u32 i;
2509         bool link_up = false;
2510
2511         DEBUGFUNC("ixgbe_reset_hw_X550em");
2512
2513         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2514         status = hw->mac.ops.stop_adapter(hw);
2515         if (status != IXGBE_SUCCESS)
2516                 return status;
2517
2518         /* flush pending Tx transactions */
2519         ixgbe_clear_tx_pending(hw);
2520
2521         ixgbe_set_mdio_speed(hw);
2522
2523         /* PHY ops must be identified and initialized prior to reset */
2524         status = hw->phy.ops.init(hw);
2525
2526         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2527                 return status;
2528
2529         /* start the external PHY */
2530         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2531                 status = ixgbe_init_ext_t_x550em(hw);
2532                 if (status)
2533                         return status;
2534         }
2535
2536         /* Setup SFP module if there is one present. */
2537         if (hw->phy.sfp_setup_needed) {
2538                 status = hw->mac.ops.setup_sfp(hw);
2539                 hw->phy.sfp_setup_needed = false;
2540         }
2541
2542         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2543                 return status;
2544
2545         /* Reset PHY */
2546         if (!hw->phy.reset_disable && hw->phy.ops.reset)
2547                 hw->phy.ops.reset(hw);
2548
2549 mac_reset_top:
2550         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2551          * If link reset is used when link is up, it might reset the PHY when
2552          * mng is using it.  If link is down or the flag to force full link
2553          * reset is set, then perform link reset.
2554          */
2555         ctrl = IXGBE_CTRL_LNK_RST;
2556         if (!hw->force_full_reset) {
2557                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2558                 if (link_up)
2559                         ctrl = IXGBE_CTRL_RST;
2560         }
2561
2562         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2563         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2564         IXGBE_WRITE_FLUSH(hw);
2565
2566         /* Poll for reset bit to self-clear meaning reset is complete */
2567         for (i = 0; i < 10; i++) {
2568                 usec_delay(1);
2569                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2570                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2571                         break;
2572         }
2573
2574         if (ctrl & IXGBE_CTRL_RST_MASK) {
2575                 status = IXGBE_ERR_RESET_FAILED;
2576                 DEBUGOUT("Reset polling failed to complete.\n");
2577         }
2578
2579         msec_delay(50);
2580
2581         /* Double resets are required for recovery from certain error
2582          * conditions.  Between resets, it is necessary to stall to
2583          * allow time for any pending HW events to complete.
2584          */
2585         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2586                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2587                 goto mac_reset_top;
2588         }
2589
2590         /* Store the permanent mac address */
2591         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2592
2593         /* Store MAC address from RAR0, clear receive address registers, and
2594          * clear the multicast table.  Also reset num_rar_entries to 128,
2595          * since we modify this value when programming the SAN MAC address.
2596          */
2597         hw->mac.num_rar_entries = 128;
2598         hw->mac.ops.init_rx_addrs(hw);
2599
2600         ixgbe_set_mdio_speed(hw);
2601
2602         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2603                 ixgbe_setup_mux_ctl(hw);
2604
2605         return status;
2606 }
2607
2608 /**
2609  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2610  * @hw: pointer to hardware structure
2611  */
2612 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2613 {
2614         u32 status;
2615         u16 reg;
2616
2617         status = hw->phy.ops.read_reg(hw,
2618                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2619                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2620                                       &reg);
2621
2622         if (status != IXGBE_SUCCESS)
2623                 return status;
2624
2625         /* If PHY FW reset completed bit is set then this is the first
2626          * SW instance after a power on so the PHY FW must be un-stalled.
2627          */
2628         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2629                 status = hw->phy.ops.read_reg(hw,
2630                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2631                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2632                                         &reg);
2633
2634                 if (status != IXGBE_SUCCESS)
2635                         return status;
2636
2637                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2638
2639                 status = hw->phy.ops.write_reg(hw,
2640                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2641                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2642                                         reg);
2643
2644                 if (status != IXGBE_SUCCESS)
2645                         return status;
2646         }
2647
2648         return status;
2649 }
2650
2651 /**
2652  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2653  *  @hw: pointer to hardware structure
2654  *
2655  *  Configures the integrated KR PHY for X550EM_x.
2656  **/
2657 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2658 {
2659         if (hw->mac.type != ixgbe_mac_X550EM_x)
2660                 return IXGBE_SUCCESS;
2661
2662         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2663 }
2664
2665 /**
2666  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2667  *  @hw: pointer to hardware structure
2668  *
2669  *  Configure the external PHY and the integrated KR PHY for SFP support.
2670  **/
2671 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2672                                     ixgbe_link_speed speed,
2673                                     bool autoneg_wait_to_complete)
2674 {
2675         s32 ret_val;
2676         u16 reg_slice, reg_val;
2677         bool setup_linear = false;
2678         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2679
2680         /* Check if SFP module is supported and linear */
2681         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2682
2683         /* If no SFP module present, then return success. Return success since
2684          * there is no reason to configure CS4227 and SFP not present error is
2685          * not excepted in the setup MAC link flow.
2686          */
2687         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2688                 return IXGBE_SUCCESS;
2689
2690         if (ret_val != IXGBE_SUCCESS)
2691                 return ret_val;
2692
2693         /* Configure internal PHY for KR/KX. */
2694         ixgbe_setup_kr_speed_x550em(hw, speed);
2695
2696         /* Configure CS4227 LINE side to proper mode. */
2697         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2698                     (hw->bus.lan_id << 12);
2699         if (setup_linear)
2700                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2701         else
2702                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2703         ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2704                                           reg_val);
2705         return ret_val;
2706 }
2707
2708 /**
2709  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2710  *  @hw: pointer to hardware structure
2711  *
2712  *  Configure the the integrated PHY for SFP support.
2713  **/
2714 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2715                                    ixgbe_link_speed speed,
2716                                    bool autoneg_wait_to_complete)
2717 {
2718         s32 ret_val;
2719         u16 reg_phy_ext;
2720         bool setup_linear = false;
2721         u32 reg_slice, reg_phy_int, slice_offset;
2722
2723         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2724
2725         /* Check if SFP module is supported and linear */
2726         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2727
2728         /* If no SFP module present, then return success. Return success since
2729          * SFP not present error is not excepted in the setup MAC link flow.
2730          */
2731         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2732                 return IXGBE_SUCCESS;
2733
2734         if (ret_val != IXGBE_SUCCESS)
2735                 return ret_val;
2736
2737         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2738                 /* Configure internal PHY for native SFI */
2739                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2740                                IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2741                                IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2742
2743                 if (ret_val != IXGBE_SUCCESS)
2744                         return ret_val;
2745
2746                 if (setup_linear) {
2747                         reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2748                         reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2749                 } else {
2750                         reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2751                         reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2752                 }
2753
2754                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2755                                 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2756                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2757
2758                 if (ret_val != IXGBE_SUCCESS)
2759                         return ret_val;
2760
2761                 /* Setup XFI/SFI internal link. */
2762                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2763         } else {
2764                 /* Configure internal PHY for KR/KX. */
2765                 ixgbe_setup_kr_speed_x550em(hw, speed);
2766
2767                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2768                         /* Find Address */
2769                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2770                         return IXGBE_ERR_PHY_ADDR_INVALID;
2771                 }
2772
2773                 /* Get external PHY device id */
2774                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2775                                        IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2776
2777                 if (ret_val != IXGBE_SUCCESS)
2778                         return ret_val;
2779
2780                 /* When configuring quad port CS4223, the MAC instance is part
2781                  * of the slice offset.
2782                  */
2783                 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2784                         slice_offset = (hw->bus.lan_id +
2785                                         (hw->bus.instance_id << 1)) << 12;
2786                 else
2787                         slice_offset = hw->bus.lan_id << 12;
2788
2789                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2790                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2791                 if (setup_linear)
2792                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2793                 else
2794                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2795                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2796                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2797         }
2798         return ret_val;
2799 }
2800
2801 /**
2802  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2803  *  @hw: pointer to hardware structure
2804  *
2805  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2806  **/
2807 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2808 {
2809         s32 status;
2810         u32 reg_val;
2811
2812         /* Disable training protocol FSM. */
2813         status = ixgbe_read_iosf_sb_reg_x550(hw,
2814                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2815                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2816         if (status != IXGBE_SUCCESS)
2817                 return status;
2818         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2819         status = ixgbe_write_iosf_sb_reg_x550(hw,
2820                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2821                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2822         if (status != IXGBE_SUCCESS)
2823                 return status;
2824
2825         /* Disable Flex from training TXFFE. */
2826         status = ixgbe_read_iosf_sb_reg_x550(hw,
2827                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2828                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2829         if (status != IXGBE_SUCCESS)
2830                 return status;
2831         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2832         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2833         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2834         status = ixgbe_write_iosf_sb_reg_x550(hw,
2835                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2836                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2837         if (status != IXGBE_SUCCESS)
2838                 return status;
2839         status = ixgbe_read_iosf_sb_reg_x550(hw,
2840                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2841                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2842         if (status != IXGBE_SUCCESS)
2843                 return status;
2844         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2845         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2846         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2847         status = ixgbe_write_iosf_sb_reg_x550(hw,
2848                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2849                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2850         if (status != IXGBE_SUCCESS)
2851                 return status;
2852
2853         /* Enable override for coefficients. */
2854         status = ixgbe_read_iosf_sb_reg_x550(hw,
2855                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2856                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2857         if (status != IXGBE_SUCCESS)
2858                 return status;
2859         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2860         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2861         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2862         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2863         status = ixgbe_write_iosf_sb_reg_x550(hw,
2864                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2865                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2866         return status;
2867 }
2868
2869 /**
2870  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2871  *  @hw: pointer to hardware structure
2872  *  @speed: the link speed to force
2873  *
2874  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2875  *  internal and external PHY at a specific speed, without autonegotiation.
2876  **/
2877 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2878 {
2879         s32 status;
2880         u32 reg_val;
2881
2882         /* Disable AN and force speed to 10G Serial. */
2883         status = ixgbe_read_iosf_sb_reg_x550(hw,
2884                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2885                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2886         if (status != IXGBE_SUCCESS)
2887                 return status;
2888
2889         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2890         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2891
2892         /* Select forced link speed for internal PHY. */
2893         switch (*speed) {
2894         case IXGBE_LINK_SPEED_10GB_FULL:
2895                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2896                 break;
2897         case IXGBE_LINK_SPEED_1GB_FULL:
2898                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2899                 break;
2900         default:
2901                 /* Other link speeds are not supported by internal KR PHY. */
2902                 return IXGBE_ERR_LINK_SETUP;
2903         }
2904
2905         status = ixgbe_write_iosf_sb_reg_x550(hw,
2906                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2907                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2908         if (status != IXGBE_SUCCESS)
2909                 return status;
2910
2911         /* Additional configuration needed for x550em_x */
2912         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2913                 status = ixgbe_setup_ixfi_x550em_x(hw);
2914                 if (status != IXGBE_SUCCESS)
2915                         return status;
2916         }
2917
2918         /* Toggle port SW reset by AN reset. */
2919         status = ixgbe_read_iosf_sb_reg_x550(hw,
2920                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2921                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2922         if (status != IXGBE_SUCCESS)
2923                 return status;
2924         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2925         status = ixgbe_write_iosf_sb_reg_x550(hw,
2926                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2927                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2928
2929         return status;
2930 }
2931
2932 /**
2933  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2934  * @hw: address of hardware structure
2935  * @link_up: address of boolean to indicate link status
2936  *
2937  * Returns error code if unable to get link status.
2938  */
2939 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2940 {
2941         u32 ret;
2942         u16 autoneg_status;
2943
2944         *link_up = false;
2945
2946         /* read this twice back to back to indicate current status */
2947         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2948                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2949                                    &autoneg_status);
2950         if (ret != IXGBE_SUCCESS)
2951                 return ret;
2952
2953         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2954                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2955                                    &autoneg_status);
2956         if (ret != IXGBE_SUCCESS)
2957                 return ret;
2958
2959         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2960
2961         return IXGBE_SUCCESS;
2962 }
2963
2964 /**
2965  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2966  * @hw: point to hardware structure
2967  *
2968  * Configures the link between the integrated KR PHY and the external X557 PHY
2969  * The driver will call this function when it gets a link status change
2970  * interrupt from the X557 PHY. This function configures the link speed
2971  * between the PHYs to match the link speed of the BASE-T link.
2972  *
2973  * A return of a non-zero value indicates an error, and the base driver should
2974  * not report link up.
2975  */
2976 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2977 {
2978         ixgbe_link_speed force_speed;
2979         bool link_up;
2980         u32 status;
2981         u16 speed;
2982
2983         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2984                 return IXGBE_ERR_CONFIG;
2985
2986         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2987                 /* If link is down, there is no setup necessary so return  */
2988                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2989                 if (status != IXGBE_SUCCESS)
2990                         return status;
2991
2992                 if (!link_up)
2993                         return IXGBE_SUCCESS;
2994
2995                 status = hw->phy.ops.read_reg(hw,
2996                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2997                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2998                                               &speed);
2999                 if (status != IXGBE_SUCCESS)
3000                         return status;
3001
3002                 /* If link is still down - no setup is required so return */
3003                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3004                 if (status != IXGBE_SUCCESS)
3005                         return status;
3006                 if (!link_up)
3007                         return IXGBE_SUCCESS;
3008
3009                 /* clear everything but the speed and duplex bits */
3010                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3011
3012                 switch (speed) {
3013                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3014                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3015                         break;
3016                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3017                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3018                         break;
3019                 default:
3020                         /* Internal PHY does not support anything else */
3021                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
3022                 }
3023
3024                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3025         } else {
3026                 speed = IXGBE_LINK_SPEED_10GB_FULL |
3027                         IXGBE_LINK_SPEED_1GB_FULL;
3028                 return ixgbe_setup_kr_speed_x550em(hw, speed);
3029         }
3030 }
3031
3032 /**
3033  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3034  *  @hw: pointer to hardware structure
3035  *
3036  *  Configures the integrated KR PHY to use internal loopback mode.
3037  **/
3038 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3039 {
3040         s32 status;
3041         u32 reg_val;
3042
3043         /* Disable AN and force speed to 10G Serial. */
3044         status = hw->mac.ops.read_iosf_sb_reg(hw,
3045                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3046                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3047         if (status != IXGBE_SUCCESS)
3048                 return status;
3049         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3050         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3051         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3052         status = hw->mac.ops.write_iosf_sb_reg(hw,
3053                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3054                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3055         if (status != IXGBE_SUCCESS)
3056                 return status;
3057
3058         /* Set near-end loopback clocks. */
3059         status = hw->mac.ops.read_iosf_sb_reg(hw,
3060                       IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3061                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3062         if (status != IXGBE_SUCCESS)
3063                 return status;
3064         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3065         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3066         status = hw->mac.ops.write_iosf_sb_reg(hw,
3067                        IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3068                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3069         if (status != IXGBE_SUCCESS)
3070                 return status;
3071
3072         /* Set loopback enable. */
3073         status = hw->mac.ops.read_iosf_sb_reg(hw,
3074                       IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3075                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3076         if (status != IXGBE_SUCCESS)
3077                 return status;
3078         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3079         status = hw->mac.ops.write_iosf_sb_reg(hw,
3080                        IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3081                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3082         if (status != IXGBE_SUCCESS)
3083                 return status;
3084
3085         /* Training bypass. */
3086         status = hw->mac.ops.read_iosf_sb_reg(hw,
3087                       IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3088                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3089         if (status != IXGBE_SUCCESS)
3090                 return status;
3091         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3092         status = hw->mac.ops.write_iosf_sb_reg(hw,
3093                        IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3094                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3095
3096         return status;
3097 }
3098
3099 /**
3100  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3101  *  assuming that the semaphore is already obtained.
3102  *  @hw: pointer to hardware structure
3103  *  @offset: offset of  word in the EEPROM to read
3104  *  @data: word read from the EEPROM
3105  *
3106  *  Reads a 16 bit word from the EEPROM using the hostif.
3107  **/
3108 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3109                                    u16 *data)
3110 {
3111         s32 status;
3112         struct ixgbe_hic_read_shadow_ram buffer;
3113
3114         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
3115         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3116         buffer.hdr.req.buf_lenh = 0;
3117         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3118         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3119
3120         /* convert offset from words to bytes */
3121         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3122         /* one word */
3123         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3124
3125         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3126                                               sizeof(buffer),
3127                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3128
3129         if (status)
3130                 return status;
3131
3132         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3133                                           FW_NVM_DATA_OFFSET);
3134
3135         return 0;
3136 }
3137
3138 /**
3139  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3140  *  @hw: pointer to hardware structure
3141  *  @offset: offset of  word in the EEPROM to read
3142  *  @data: word read from the EEPROM
3143  *
3144  *  Reads a 16 bit word from the EEPROM using the hostif.
3145  **/
3146 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3147                               u16 *data)
3148 {
3149         s32 status = IXGBE_SUCCESS;
3150
3151         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3152
3153         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3154             IXGBE_SUCCESS) {
3155                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
3156                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3157         } else {
3158                 status = IXGBE_ERR_SWFW_SYNC;
3159         }
3160
3161         return status;
3162 }
3163
3164 /**
3165  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3166  *  @hw: pointer to hardware structure
3167  *  @offset: offset of  word in the EEPROM to read
3168  *  @words: number of words
3169  *  @data: word(s) read from the EEPROM
3170  *
3171  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
3172  **/
3173 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3174                                      u16 offset, u16 words, u16 *data)
3175 {
3176         struct ixgbe_hic_read_shadow_ram buffer;
3177         u32 current_word = 0;
3178         u16 words_to_read;
3179         s32 status;
3180         u32 i;
3181
3182         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3183
3184         /* Take semaphore for the entire operation. */
3185         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3186         if (status) {
3187                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3188                 return status;
3189         }
3190         while (words) {
3191                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3192                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3193                 else
3194                         words_to_read = words;
3195
3196                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3197                 buffer.hdr.req.buf_lenh = 0;
3198                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3199                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3200
3201                 /* convert offset from words to bytes */
3202                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3203                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3204
3205                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3206                                                       sizeof(buffer),
3207                                                       IXGBE_HI_COMMAND_TIMEOUT,
3208                                                       false);
3209
3210                 if (status) {
3211                         DEBUGOUT("Host interface command failed\n");
3212                         goto out;
3213                 }
3214
3215                 for (i = 0; i < words_to_read; i++) {
3216                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3217                                   2 * i;
3218                         u32 value = IXGBE_READ_REG(hw, reg);
3219
3220                         data[current_word] = (u16)(value & 0xffff);
3221                         current_word++;
3222                         i++;
3223                         if (i < words_to_read) {
3224                                 value >>= 16;
3225                                 data[current_word] = (u16)(value & 0xffff);
3226                                 current_word++;
3227                         }
3228                 }
3229                 words -= words_to_read;
3230         }
3231
3232 out:
3233         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3234         return status;
3235 }
3236
3237 /**
3238  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3239  *  @hw: pointer to hardware structure
3240  *  @offset: offset of  word in the EEPROM to write
3241  *  @data: word write to the EEPROM
3242  *
3243  *  Write a 16 bit word to the EEPROM using the hostif.
3244  **/
3245 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3246                                     u16 data)
3247 {
3248         s32 status;
3249         struct ixgbe_hic_write_shadow_ram buffer;
3250
3251         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3252
3253         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3254         buffer.hdr.req.buf_lenh = 0;
3255         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3256         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3257
3258          /* one word */
3259         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3260         buffer.data = data;
3261         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3262
3263         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3264                                               sizeof(buffer),
3265                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3266
3267         return status;
3268 }
3269
3270 /**
3271  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3272  *  @hw: pointer to hardware structure
3273  *  @offset: offset of  word in the EEPROM to write
3274  *  @data: word write to the EEPROM
3275  *
3276  *  Write a 16 bit word to the EEPROM using the hostif.
3277  **/
3278 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3279                                u16 data)
3280 {
3281         s32 status = IXGBE_SUCCESS;
3282
3283         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3284
3285         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3286             IXGBE_SUCCESS) {
3287                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3288                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3289         } else {
3290                 DEBUGOUT("write ee hostif failed to get semaphore");
3291                 status = IXGBE_ERR_SWFW_SYNC;
3292         }
3293
3294         return status;
3295 }
3296
3297 /**
3298  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3299  *  @hw: pointer to hardware structure
3300  *  @offset: offset of  word in the EEPROM to write
3301  *  @words: number of words
3302  *  @data: word(s) write to the EEPROM
3303  *
3304  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3305  **/
3306 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3307                                       u16 offset, u16 words, u16 *data)
3308 {
3309         s32 status = IXGBE_SUCCESS;
3310         u32 i = 0;
3311
3312         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3313
3314         /* Take semaphore for the entire operation. */
3315         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3316         if (status != IXGBE_SUCCESS) {
3317                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3318                 goto out;
3319         }
3320
3321         for (i = 0; i < words; i++) {
3322                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3323                                                          data[i]);
3324
3325                 if (status != IXGBE_SUCCESS) {
3326                         DEBUGOUT("Eeprom buffered write failed\n");
3327                         break;
3328                 }
3329         }
3330
3331         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3332 out:
3333
3334         return status;
3335 }
3336
3337 /**
3338  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3339  * @hw: pointer to hardware structure
3340  * @ptr: pointer offset in eeprom
3341  * @size: size of section pointed by ptr, if 0 first word will be used as size
3342  * @csum: address of checksum to update
3343  *
3344  * Returns error status for any failure
3345  */
3346 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3347                                    u16 size, u16 *csum, u16 *buffer,
3348                                    u32 buffer_size)
3349 {
3350         u16 buf[256];
3351         s32 status;
3352         u16 length, bufsz, i, start;
3353         u16 *local_buffer;
3354
3355         bufsz = sizeof(buf) / sizeof(buf[0]);
3356
3357         /* Read a chunk at the pointer location */
3358         if (!buffer) {
3359                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3360                 if (status) {
3361                         DEBUGOUT("Failed to read EEPROM image\n");
3362                         return status;
3363                 }
3364                 local_buffer = buf;
3365         } else {
3366                 if (buffer_size < ptr)
3367                         return  IXGBE_ERR_PARAM;
3368                 local_buffer = &buffer[ptr];
3369         }
3370
3371         if (size) {
3372                 start = 0;
3373                 length = size;
3374         } else {
3375                 start = 1;
3376                 length = local_buffer[0];
3377
3378                 /* Skip pointer section if length is invalid. */
3379                 if (length == 0xFFFF || length == 0 ||
3380                     (ptr + length) >= hw->eeprom.word_size)
3381                         return IXGBE_SUCCESS;
3382         }
3383
3384         if (buffer && ((u32)start + (u32)length > buffer_size))
3385                 return IXGBE_ERR_PARAM;
3386
3387         for (i = start; length; i++, length--) {
3388                 if (i == bufsz && !buffer) {
3389                         ptr += bufsz;
3390                         i = 0;
3391                         if (length < bufsz)
3392                                 bufsz = length;
3393
3394                         /* Read a chunk at the pointer location */
3395                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3396                                                                   bufsz, buf);
3397                         if (status) {
3398                                 DEBUGOUT("Failed to read EEPROM image\n");
3399                                 return status;
3400                         }
3401                 }
3402                 *csum += local_buffer[i];
3403         }
3404         return IXGBE_SUCCESS;
3405 }
3406
3407 /**
3408  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3409  *  @hw: pointer to hardware structure
3410  *  @buffer: pointer to buffer containing calculated checksum
3411  *  @buffer_size: size of buffer
3412  *
3413  *  Returns a negative error code on error, or the 16-bit checksum
3414  **/
3415 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3416 {
3417         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3418         u16 *local_buffer;
3419         s32 status;
3420         u16 checksum = 0;
3421         u16 pointer, i, size;
3422
3423         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3424
3425         hw->eeprom.ops.init_params(hw);
3426
3427         if (!buffer) {
3428                 /* Read pointer area */
3429                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3430                                                      IXGBE_EEPROM_LAST_WORD + 1,
3431                                                      eeprom_ptrs);
3432                 if (status) {
3433                         DEBUGOUT("Failed to read EEPROM image\n");
3434                         return status;
3435                 }
3436                 local_buffer = eeprom_ptrs;
3437         } else {
3438                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3439                         return IXGBE_ERR_PARAM;
3440                 local_buffer = buffer;
3441         }
3442
3443         /*
3444          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3445          * checksum word itself
3446          */
3447         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3448                 if (i != IXGBE_EEPROM_CHECKSUM)
3449                         checksum += local_buffer[i];
3450
3451         /*
3452          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3453          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3454          */
3455         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3456                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3457                         continue;
3458
3459                 pointer = local_buffer[i];
3460
3461                 /* Skip pointer section if the pointer is invalid. */
3462                 if (pointer == 0xFFFF || pointer == 0 ||
3463                     pointer >= hw->eeprom.word_size)
3464                         continue;
3465
3466                 switch (i) {
3467                 case IXGBE_PCIE_GENERAL_PTR:
3468                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3469                         break;
3470                 case IXGBE_PCIE_CONFIG0_PTR:
3471                 case IXGBE_PCIE_CONFIG1_PTR:
3472                         size = IXGBE_PCIE_CONFIG_SIZE;
3473                         break;
3474                 default:
3475                         size = 0;
3476                         break;
3477                 }
3478
3479                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3480                                                 buffer, buffer_size);
3481                 if (status)
3482                         return status;
3483         }
3484
3485         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3486
3487         return (s32)checksum;
3488 }
3489
3490 /**
3491  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3492  *  @hw: pointer to hardware structure
3493  *
3494  *  Returns a negative error code on error, or the 16-bit checksum
3495  **/
3496 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3497 {
3498         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3499 }
3500
3501 /**
3502  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3503  *  @hw: pointer to hardware structure
3504  *  @checksum_val: calculated checksum
3505  *
3506  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3507  *  caller does not need checksum_val, the value can be NULL.
3508  **/
3509 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3510 {
3511         s32 status;
3512         u16 checksum;
3513         u16 read_checksum = 0;
3514
3515         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3516
3517         /* Read the first word from the EEPROM. If this times out or fails, do
3518          * not continue or we could be in for a very long wait while every
3519          * EEPROM read fails
3520          */
3521         status = hw->eeprom.ops.read(hw, 0, &checksum);
3522         if (status) {
3523                 DEBUGOUT("EEPROM read failed\n");
3524                 return status;
3525         }
3526
3527         status = hw->eeprom.ops.calc_checksum(hw);
3528         if (status < 0)
3529                 return status;
3530
3531         checksum = (u16)(status & 0xffff);
3532
3533         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3534                                            &read_checksum);
3535         if (status)
3536                 return status;
3537
3538         /* Verify read checksum from EEPROM is the same as
3539          * calculated checksum
3540          */
3541         if (read_checksum != checksum) {
3542                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3543                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3544                              "Invalid EEPROM checksum");
3545         }
3546
3547         /* If the user cares, return the calculated checksum */
3548         if (checksum_val)
3549                 *checksum_val = checksum;
3550
3551         return status;
3552 }
3553
3554 /**
3555  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3556  * @hw: pointer to hardware structure
3557  *
3558  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3559  * checksum and updates the EEPROM and instructs the hardware to update
3560  * the flash.
3561  **/
3562 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3563 {
3564         s32 status;
3565         u16 checksum = 0;
3566
3567         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3568
3569         /* Read the first word from the EEPROM. If this times out or fails, do
3570          * not continue or we could be in for a very long wait while every
3571          * EEPROM read fails
3572          */
3573         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3574         if (status) {
3575                 DEBUGOUT("EEPROM read failed\n");
3576                 return status;
3577         }
3578
3579         status = ixgbe_calc_eeprom_checksum_X550(hw);
3580         if (status < 0)
3581                 return status;
3582
3583         checksum = (u16)(status & 0xffff);
3584
3585         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3586                                             checksum);
3587         if (status)
3588                 return status;
3589
3590         status = ixgbe_update_flash_X550(hw);
3591
3592         return status;
3593 }
3594
3595 /**
3596  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3597  *  @hw: pointer to hardware structure
3598  *
3599  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3600  **/
3601 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3602 {
3603         s32 status = IXGBE_SUCCESS;
3604         union ixgbe_hic_hdr2 buffer;
3605
3606         DEBUGFUNC("ixgbe_update_flash_X550");
3607
3608         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3609         buffer.req.buf_lenh = 0;
3610         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3611         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3612
3613         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3614                                               sizeof(buffer),
3615                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3616
3617         return status;
3618 }
3619
3620 /**
3621  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3622  *  @hw: pointer to hardware structure
3623  *
3624  *  Determines physical layer capabilities of the current configuration.
3625  **/
3626 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3627 {
3628         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3629         u16 ext_ability = 0;
3630
3631         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3632
3633         hw->phy.ops.identify(hw);
3634
3635         switch (hw->phy.type) {
3636         case ixgbe_phy_x550em_kr:
3637                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3638                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3639                 break;
3640         case ixgbe_phy_x550em_kx4:
3641                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3642                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3643                 break;
3644         case ixgbe_phy_x550em_ext_t:
3645                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3646                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3647                                      &ext_ability);
3648                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3649                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3650                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3651                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3652                 break;
3653         default:
3654                 break;
3655         }
3656
3657         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3658                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3659
3660         return physical_layer;
3661 }
3662
3663 /**
3664  * ixgbe_get_bus_info_x550em - Set PCI bus info
3665  * @hw: pointer to hardware structure
3666  *
3667  * Sets bus link width and speed to unknown because X550em is
3668  * not a PCI device.
3669  **/
3670 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3671 {
3672
3673         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3674
3675         hw->bus.width = ixgbe_bus_width_unknown;
3676         hw->bus.speed = ixgbe_bus_speed_unknown;
3677
3678         hw->mac.ops.set_lan_id(hw);
3679
3680         return IXGBE_SUCCESS;
3681 }
3682
3683 /**
3684  * ixgbe_disable_rx_x550 - Disable RX unit
3685  *
3686  * Enables the Rx DMA unit for x550
3687  **/
3688 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3689 {
3690         u32 rxctrl, pfdtxgswc;
3691         s32 status;
3692         struct ixgbe_hic_disable_rxen fw_cmd;
3693
3694         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3695
3696         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3697         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3698                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3699                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3700                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3701                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3702                         hw->mac.set_lben = true;
3703                 } else {
3704                         hw->mac.set_lben = false;
3705                 }
3706
3707                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3708                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3709                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3710                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3711
3712                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3713                                         sizeof(struct ixgbe_hic_disable_rxen),
3714                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3715
3716                 /* If we fail - disable RX using register write */
3717                 if (status) {
3718                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3719                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3720                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3721                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3722                         }
3723                 }
3724         }
3725 }
3726
3727 /**
3728  * ixgbe_enter_lplu_x550em - Transition to low power states
3729  *  @hw: pointer to hardware structure
3730  *
3731  * Configures Low Power Link Up on transition to low power states
3732  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3733  * X557 PHY immediately prior to entering LPLU.
3734  **/
3735 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3736 {
3737         u16 an_10g_cntl_reg, autoneg_reg, speed;
3738         s32 status;
3739         ixgbe_link_speed lcd_speed;
3740         u32 save_autoneg;
3741         bool link_up;
3742
3743         /* SW LPLU not required on later HW revisions. */
3744         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3745             (IXGBE_FUSES0_REV_MASK &
3746              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3747                 return IXGBE_SUCCESS;
3748
3749         /* If blocked by MNG FW, then don't restart AN */
3750         if (ixgbe_check_reset_blocked(hw))
3751                 return IXGBE_SUCCESS;
3752
3753         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3754         if (status != IXGBE_SUCCESS)
3755                 return status;
3756
3757         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3758
3759         if (status != IXGBE_SUCCESS)
3760                 return status;
3761
3762         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3763          * disabled, then force link down by entering low power mode.
3764          */
3765         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3766             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3767                 return ixgbe_set_copper_phy_power(hw, FALSE);
3768
3769         /* Determine LCD */
3770         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3771
3772         if (status != IXGBE_SUCCESS)
3773                 return status;
3774
3775         /* If no valid LCD link speed, then force link down and exit. */
3776         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3777                 return ixgbe_set_copper_phy_power(hw, FALSE);
3778
3779         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3780                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3781                                       &speed);
3782
3783         if (status != IXGBE_SUCCESS)
3784                 return status;
3785
3786         /* If no link now, speed is invalid so take link down */
3787         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3788         if (status != IXGBE_SUCCESS)
3789                 return ixgbe_set_copper_phy_power(hw, false);
3790
3791         /* clear everything but the speed bits */
3792         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3793
3794         /* If current speed is already LCD, then exit. */
3795         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3796              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3797             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3798              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3799                 return status;
3800
3801         /* Clear AN completed indication */
3802         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3803                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3804                                       &autoneg_reg);
3805
3806         if (status != IXGBE_SUCCESS)
3807                 return status;
3808
3809         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3810                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3811                              &an_10g_cntl_reg);
3812
3813         if (status != IXGBE_SUCCESS)
3814                 return status;
3815
3816         status = hw->phy.ops.read_reg(hw,
3817                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3818                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3819                              &autoneg_reg);
3820
3821         if (status != IXGBE_SUCCESS)
3822                 return status;
3823
3824         save_autoneg = hw->phy.autoneg_advertised;
3825
3826         /* Setup link at least common link speed */
3827         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3828
3829         /* restore autoneg from before setting lplu speed */
3830         hw->phy.autoneg_advertised = save_autoneg;
3831
3832         return status;
3833 }
3834
3835 /**
3836  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3837  *  @hw: pointer to hardware structure
3838  *  @lcd_speed: pointer to lowest common link speed
3839  *
3840  * Determine lowest common link speed with link partner.
3841  **/
3842 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3843 {
3844         u16 an_lp_status;
3845         s32 status;
3846         u16 word = hw->eeprom.ctrl_word_3;
3847
3848         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3849
3850         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3851                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3852                                       &an_lp_status);
3853
3854         if (status != IXGBE_SUCCESS)
3855                 return status;
3856
3857         /* If link partner advertised 1G, return 1G */
3858         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3859                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3860                 return status;
3861         }
3862
3863         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3864         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3865             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3866                 return status;
3867
3868         /* Link partner not capable of lower speeds, return 10G */
3869         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3870         return status;
3871 }
3872
3873 /**
3874  *  ixgbe_setup_fc_X550em - Set up flow control
3875  *  @hw: pointer to hardware structure
3876  *
3877  *  Called at init time to set up flow control.
3878  **/
3879 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3880 {
3881         s32 ret_val = IXGBE_SUCCESS;
3882         u32 pause, asm_dir, reg_val;
3883
3884         DEBUGFUNC("ixgbe_setup_fc_X550em");
3885
3886         /* Validate the requested mode */
3887         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3888                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3889                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3890                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3891                 goto out;
3892         }
3893
3894         /* 10gig parts do not have a word in the EEPROM to determine the
3895          * default flow control setting, so we explicitly set it to full.
3896          */
3897         if (hw->fc.requested_mode == ixgbe_fc_default)
3898                 hw->fc.requested_mode = ixgbe_fc_full;
3899
3900         /* Determine PAUSE and ASM_DIR bits. */
3901         switch (hw->fc.requested_mode) {
3902         case ixgbe_fc_none:
3903                 pause = 0;
3904                 asm_dir = 0;
3905                 break;
3906         case ixgbe_fc_tx_pause:
3907                 pause = 0;
3908                 asm_dir = 1;
3909                 break;
3910         case ixgbe_fc_rx_pause:
3911                 /* Rx Flow control is enabled and Tx Flow control is
3912                  * disabled by software override. Since there really
3913                  * isn't a way to advertise that we are capable of RX
3914                  * Pause ONLY, we will advertise that we support both
3915                  * symmetric and asymmetric Rx PAUSE, as such we fall
3916                  * through to the fc_full statement.  Later, we will
3917                  * disable the adapter's ability to send PAUSE frames.
3918                  */
3919         case ixgbe_fc_full:
3920                 pause = 1;
3921                 asm_dir = 1;
3922                 break;
3923         default:
3924                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3925                         "Flow control param set incorrectly\n");
3926                 ret_val = IXGBE_ERR_CONFIG;
3927                 goto out;
3928         }
3929
3930         switch (hw->device_id) {
3931         case IXGBE_DEV_ID_X550EM_X_KR:
3932         case IXGBE_DEV_ID_X550EM_A_KR:
3933         case IXGBE_DEV_ID_X550EM_A_KR_L:
3934                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3935                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3936                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3937                 if (ret_val != IXGBE_SUCCESS)
3938                         goto out;
3939                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3940                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3941                 if (pause)
3942                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3943                 if (asm_dir)
3944                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3945                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3946                                        IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3947                                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3948
3949                 /* This device does not fully support AN. */
3950                 hw->fc.disable_fc_autoneg = true;
3951                 break;
3952         default:
3953                 break;
3954         }
3955
3956 out:
3957         return ret_val;
3958 }
3959
3960 /**
3961  *  ixgbe_fc_autoneg_x550a - Enable flow control IEEE clause 37
3962  *  @hw: pointer to hardware structure
3963  *
3964  *  Enable flow control according to IEEE clause 37.
3965  **/
3966 void ixgbe_fc_autoneg_x550a(struct ixgbe_hw *hw)
3967 {
3968         u32 link_s1, lp_an_page_low, an_cntl_1;
3969         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3970         ixgbe_link_speed speed;
3971         bool link_up;
3972
3973         /* AN should have completed when the cable was plugged in.
3974          * Look for reasons to bail out.  Bail out if:
3975          * - FC autoneg is disabled, or if
3976          * - link is not up.
3977          */
3978         if (hw->fc.disable_fc_autoneg) {
3979                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3980                               "Flow control autoneg is disabled");
3981                 goto out;
3982         }
3983
3984         hw->mac.ops.check_link(hw, &speed, &link_up, false);
3985         if (!link_up) {
3986                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3987                 goto out;
3988         }
3989
3990         /* Check at auto-negotiation has completed */
3991         status = hw->mac.ops.read_iosf_sb_reg(hw,
3992                                       IXGBE_KRM_LINK_S1(hw->bus.lan_id),
3993                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
3994
3995         if (status != IXGBE_SUCCESS ||
3996             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
3997                 DEBUGOUT("Auto-Negotiation did not complete\n");
3998                 goto out;
3999         }
4000
4001         /* Read the 10g AN autoc and LP ability registers and resolve
4002          * local flow control settings accordingly
4003          */
4004         status = hw->mac.ops.read_iosf_sb_reg(hw,
4005                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4006                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4007
4008         if (status != IXGBE_SUCCESS) {
4009                 DEBUGOUT("Auto-Negotiation did not complete\n");
4010                 goto out;
4011         }
4012
4013         status = hw->mac.ops.read_iosf_sb_reg(hw,
4014                               IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4015                               IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4016
4017         if (status != IXGBE_SUCCESS) {
4018                 DEBUGOUT("Auto-Negotiation did not complete\n");
4019                 goto out;
4020         }
4021
4022         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4023                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4024                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4025                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4026                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4027
4028 out:
4029         if (status == IXGBE_SUCCESS) {
4030                 hw->fc.fc_was_autonegged = true;
4031         } else {
4032                 hw->fc.fc_was_autonegged = false;
4033                 hw->fc.current_mode = hw->fc.requested_mode;
4034         }
4035 }
4036
4037 /**
4038  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4039  *  @hw: pointer to hardware structure
4040  *
4041  *  Called at init time to set up flow control.
4042  **/
4043 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4044 {
4045         s32 status = IXGBE_SUCCESS;
4046         u32 an_cntl, link_ctrl = 0;
4047
4048         DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4049
4050         /* Validate the requested mode */
4051         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4052                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4053                       "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4054                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4055         }
4056
4057         if (hw->fc.requested_mode == ixgbe_fc_default)
4058                 hw->fc.requested_mode = ixgbe_fc_full;
4059
4060         /* Set up the 1G and 10G flow control advertisement registers so the
4061          * HW will be able to do FC autoneg once the cable is plugged in.  If
4062          * we link at 10G, the 1G advertisement is harmless and vice versa.
4063          */
4064         status = hw->mac.ops.read_iosf_sb_reg(hw,
4065                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4066                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4067
4068         if (status != IXGBE_SUCCESS) {
4069                 DEBUGOUT("Auto-Negotiation did not complete\n");
4070                 return status;
4071         }
4072
4073         /* The possible values of fc.requested_mode are:
4074          * 0: Flow control is completely disabled
4075          * 1: Rx flow control is enabled (we can receive pause frames,
4076          *    but not send pause frames).
4077          * 2: Tx flow control is enabled (we can send pause frames but
4078          *    we do not support receiving pause frames).
4079          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4080          * other: Invalid.
4081          */
4082         switch (hw->fc.requested_mode) {
4083         case ixgbe_fc_none:
4084                 /* Flow control completely disabled by software override. */
4085                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4086                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4087                 break;
4088         case ixgbe_fc_tx_pause:
4089                 /* Tx Flow control is enabled, and Rx Flow control is
4090                  * disabled by software override.
4091                  */
4092                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4093                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4094                 break;
4095         case ixgbe_fc_rx_pause:
4096                 /* Rx Flow control is enabled and Tx Flow control is
4097                  * disabled by software override. Since there really
4098                  * isn't a way to advertise that we are capable of RX
4099                  * Pause ONLY, we will advertise that we support both
4100                  * symmetric and asymmetric Rx PAUSE, as such we fall
4101                  * through to the fc_full statement.  Later, we will
4102                  * disable the adapter's ability to send PAUSE frames.
4103                  */
4104         case ixgbe_fc_full:
4105                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4106                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4107                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4108                 break;
4109         default:
4110                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4111                               "Flow control param set incorrectly\n");
4112                 return IXGBE_ERR_CONFIG;
4113         }
4114
4115         status = hw->mac.ops.write_iosf_sb_reg(hw,
4116                                        IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4117                                        IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4118
4119         /* Restart auto-negotiation. */
4120         status = hw->mac.ops.read_iosf_sb_reg(hw,
4121                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4122                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
4123
4124         if (status != IXGBE_SUCCESS) {
4125                 DEBUGOUT("Auto-Negotiation did not complete\n");
4126                 return status;
4127         }
4128
4129         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
4130         status = hw->mac.ops.write_iosf_sb_reg(hw,
4131                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4132                                        IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
4133
4134         return status;
4135 }
4136
4137 /**
4138  *  ixgbe_setup_fc_fiber_x550em_a - Set up flow control
4139  *  @hw: pointer to hardware structure
4140  *
4141  *  Called at init time to set up flow control.
4142  **/
4143 s32 ixgbe_setup_fc_fiber_x550em_a(struct ixgbe_hw *hw)
4144 {
4145         struct ixgbe_mac_info *mac = &hw->mac;
4146         s32 rc = IXGBE_SUCCESS;
4147         u32 an_cntl4, lctrl, pcs_an;
4148
4149         DEBUGFUNC("ixgbe_setup_fc_fiber_x550em_a");
4150
4151         /* Validate the requested mode */
4152         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4153                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4154                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4155                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4156         }
4157
4158         /* Enable clause 37 auto-negotiation in KRM_LINK_CTRL_1 */
4159         if (hw->fc.requested_mode == ixgbe_fc_default)
4160                 hw->fc.requested_mode = ixgbe_fc_full;
4161
4162         rc = mac->ops.read_iosf_sb_reg(hw,
4163                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4164                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lctrl);
4165         if (rc)
4166                 return rc;
4167
4168         lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
4169         lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
4170
4171         rc = mac->ops.write_iosf_sb_reg(hw,
4172                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4173                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lctrl);
4174         if (rc)
4175                 return rc;
4176
4177         /* Enable clause 37 over 73 in KRM_AN_CNTL_4 */
4178         rc = mac->ops.read_iosf_sb_reg(hw,
4179                                        IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
4180                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl4);
4181         if (rc)
4182                 return rc;
4183
4184         an_cntl4 |= IXGBE_KRM_AN_CNTL_4_ECSR_AN37_OVER_73;
4185
4186         rc = mac->ops.write_iosf_sb_reg(hw,
4187                                         IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
4188                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl4);
4189         if (rc)
4190                 return rc;
4191
4192         rc = hw->mac.ops.read_iosf_sb_reg(hw,
4193                                           IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4194                                           IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an);
4195
4196         if (rc)
4197                 return rc;
4198
4199         /* The possible values of fc.requested_mode are:
4200          * 0: Flow control is completely disabled
4201          * 1: Rx flow control is enabled (we can receive pause frames,
4202          *    but not send pause frames).
4203          * 2: Tx flow control is enabled (we can send pause frames but
4204          *    we do not support receiving pause frames).
4205          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4206          * other: Invalid.
4207          */
4208         switch (hw->fc.requested_mode) {
4209         case ixgbe_fc_none:
4210                 /* Flow control completely disabled by software override. */
4211                 pcs_an &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4212                             IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4213                 break;
4214         case ixgbe_fc_tx_pause:
4215                 /* Tx Flow control is enabled, and Rx Flow control is
4216                  * disabled by software override.
4217                  */
4218                 pcs_an |= IXGBE_KRM_PCS_KX_AN_ASM_PAUSE;
4219                 pcs_an &= ~IXGBE_KRM_PCS_KX_AN_SYM_PAUSE;
4220                 break;
4221         case ixgbe_fc_rx_pause:
4222                 /* Rx Flow control is enabled and Tx Flow control is
4223                  * disabled by software override. Since there really
4224                  * isn't a way to advertise that we are capable of RX
4225                  * Pause ONLY, we will advertise that we support both
4226                  * symmetric and asymmetric Rx PAUSE, as such we fall
4227                  * through to the fc_full statement.  Later, we will
4228                  * disable the adapter's ability to send PAUSE frames.
4229                  */
4230         case ixgbe_fc_full:
4231                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4232                 pcs_an |= IXGBE_KRM_PCS_KX_AN_SYM_PAUSE |
4233                            IXGBE_KRM_PCS_KX_AN_ASM_PAUSE;
4234                 break;
4235         default:
4236                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4237                               "Flow control param set incorrectly\n");
4238                 return IXGBE_ERR_CONFIG;
4239         }
4240
4241         rc = hw->mac.ops.write_iosf_sb_reg(hw,
4242                                            IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4243                                            IXGBE_SB_IOSF_TARGET_KR_PHY, pcs_an);
4244
4245         /* Restart auto-negotiation. */
4246         rc = hw->mac.ops.read_iosf_sb_reg(hw,
4247                                           IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4248                                           IXGBE_SB_IOSF_TARGET_KR_PHY, &lctrl);
4249
4250         if (rc) {
4251                 DEBUGOUT("Auto-Negotiation did not complete\n");
4252                 return rc;
4253         }
4254
4255         lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
4256         rc = hw->mac.ops.write_iosf_sb_reg(hw,
4257                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4258                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lctrl);
4259
4260         return rc;
4261 }
4262
4263 /**
4264  * ixgbe_set_mux - Set mux for port 1 access with CS4227
4265  * @hw: pointer to hardware structure
4266  * @state: set mux if 1, clear if 0
4267  */
4268 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4269 {
4270         u32 esdp;
4271
4272         if (!hw->bus.lan_id)
4273                 return;
4274         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4275         if (state)
4276                 esdp |= IXGBE_ESDP_SDP1;
4277         else
4278                 esdp &= ~IXGBE_ESDP_SDP1;
4279         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4280         IXGBE_WRITE_FLUSH(hw);
4281 }
4282
4283 /**
4284  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4285  *  @hw: pointer to hardware structure
4286  *  @mask: Mask to specify which semaphore to acquire
4287  *
4288  *  Acquires the SWFW semaphore and sets the I2C MUX
4289  **/
4290 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4291 {
4292         s32 status;
4293
4294         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4295
4296         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4297         if (status)
4298                 return status;
4299
4300         if (mask & IXGBE_GSSR_I2C_MASK)
4301                 ixgbe_set_mux(hw, 1);
4302
4303         return IXGBE_SUCCESS;
4304 }
4305
4306 /**
4307  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4308  *  @hw: pointer to hardware structure
4309  *  @mask: Mask to specify which semaphore to release
4310  *
4311  *  Releases the SWFW semaphore and sets the I2C MUX
4312  **/
4313 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4314 {
4315         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4316
4317         if (mask & IXGBE_GSSR_I2C_MASK)
4318                 ixgbe_set_mux(hw, 0);
4319
4320         ixgbe_release_swfw_sync_X540(hw, mask);
4321 }
4322
4323 /**
4324  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4325  *  @hw: pointer to hardware structure
4326  *  @mask: Mask to specify which semaphore to acquire
4327  *
4328  *  Acquires the SWFW semaphore and get the shared phy token as needed
4329  */
4330 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4331 {
4332         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4333         int retries = FW_PHY_TOKEN_RETRIES;
4334         s32 status = IXGBE_SUCCESS;
4335
4336         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4337
4338         while (--retries) {
4339                 status = IXGBE_SUCCESS;
4340                 if (hmask)
4341                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4342                 if (status)
4343                         return status;
4344                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4345                         return IXGBE_SUCCESS;
4346
4347                 status = ixgbe_get_phy_token(hw);
4348                 if (status == IXGBE_SUCCESS)
4349                         return IXGBE_SUCCESS;
4350
4351                 if (hmask)
4352                         ixgbe_release_swfw_sync_X540(hw, hmask);
4353                 if (status != IXGBE_ERR_TOKEN_RETRY)
4354                         return status;
4355                 msec_delay(FW_PHY_TOKEN_DELAY);
4356         }
4357
4358         return status;
4359 }
4360
4361 /**
4362  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4363  *  @hw: pointer to hardware structure
4364  *  @mask: Mask to specify which semaphore to release
4365  *
4366  *  Releases the SWFW semaphore and puts the shared phy token as needed
4367  */
4368 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4369 {
4370         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4371
4372         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4373
4374         if (mask & IXGBE_GSSR_TOKEN_SM)
4375                 ixgbe_put_phy_token(hw);
4376
4377         if (hmask)
4378                 ixgbe_release_swfw_sync_X540(hw, hmask);
4379 }
4380
4381 /**
4382  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4383  *  @hw: pointer to hardware structure
4384  *  @reg_addr: 32 bit address of PHY register to read
4385  *  @phy_data: Pointer to read data from PHY register
4386  *
4387  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4388  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4389  *  instances.
4390  **/
4391 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4392                              u32 device_type, u16 *phy_data)
4393 {
4394         s32 status;
4395         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4396
4397         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4398
4399         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4400                 return IXGBE_ERR_SWFW_SYNC;
4401
4402         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4403
4404         hw->mac.ops.release_swfw_sync(hw, mask);
4405
4406         return status;
4407 }
4408
4409 /**
4410  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4411  *  @hw: pointer to hardware structure
4412  *  @reg_addr: 32 bit PHY register to write
4413  *  @device_type: 5 bit device type
4414  *  @phy_data: Data to write to the PHY register
4415  *
4416  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4417  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4418  **/
4419 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4420                               u32 device_type, u16 phy_data)
4421 {
4422         s32 status;
4423         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4424
4425         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4426
4427         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4428                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
4429                                                  phy_data);
4430                 hw->mac.ops.release_swfw_sync(hw, mask);
4431         } else {
4432                 status = IXGBE_ERR_SWFW_SYNC;
4433         }
4434
4435         return status;
4436 }
4437
4438 /**
4439  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4440  * @hw: pointer to hardware structure
4441  *
4442  * Handle external Base T PHY interrupt. If high temperature
4443  * failure alarm then return error, else if link status change
4444  * then setup internal/external PHY link
4445  *
4446  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4447  * failure alarm, else return PHY access status.
4448  */
4449 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4450 {
4451         bool lsc;
4452         u32 status;
4453
4454         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4455
4456         if (status != IXGBE_SUCCESS)
4457                 return status;
4458
4459         if (lsc)
4460                 return ixgbe_setup_internal_phy(hw);
4461
4462         return IXGBE_SUCCESS;
4463 }
4464
4465 /**
4466  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4467  * @hw: pointer to hardware structure
4468  * @speed: new link speed
4469  * @autoneg_wait_to_complete: true when waiting for completion is needed
4470  *
4471  * Setup internal/external PHY link speed based on link speed, then set
4472  * external PHY auto advertised link speed.
4473  *
4474  * Returns error status for any failure
4475  **/
4476 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4477                                   ixgbe_link_speed speed,
4478                                   bool autoneg_wait_to_complete)
4479 {
4480         s32 status;
4481         ixgbe_link_speed force_speed;
4482
4483         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4484
4485         /* Setup internal/external PHY link speed to iXFI (10G), unless
4486          * only 1G is auto advertised then setup KX link.
4487          */
4488         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4489                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4490         else
4491                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4492
4493         /* If internal link mode is XFI, then setup XFI internal link. */
4494         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4495                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4496
4497                 if (status != IXGBE_SUCCESS)
4498                         return status;
4499         }
4500
4501         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4502 }
4503
4504 /**
4505  * ixgbe_check_link_t_X550em - Determine link and speed status
4506  * @hw: pointer to hardware structure
4507  * @speed: pointer to link speed
4508  * @link_up: true when link is up
4509  * @link_up_wait_to_complete: bool used to wait for link up or not
4510  *
4511  * Check that both the MAC and X557 external PHY have link.
4512  **/
4513 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4514                               bool *link_up, bool link_up_wait_to_complete)
4515 {
4516         u32 status;
4517         u16 autoneg_status;
4518
4519         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4520                 return IXGBE_ERR_CONFIG;
4521
4522         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4523                                               link_up_wait_to_complete);
4524
4525         /* If check link fails or MAC link is not up, then return */
4526         if (status != IXGBE_SUCCESS || !(*link_up))
4527                 return status;
4528
4529         /* MAC link is up, so check external PHY link.
4530          * Read this twice back to back to indicate current status.
4531          */
4532         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4533                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4534                                       &autoneg_status);
4535
4536         if (status != IXGBE_SUCCESS)
4537                 return status;
4538
4539         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4540                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4541                                       &autoneg_status);
4542
4543         if (status != IXGBE_SUCCESS)
4544                 return status;
4545
4546         /* If external PHY link is not up, then indicate link not up */
4547         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4548                 *link_up = false;
4549
4550         return IXGBE_SUCCESS;
4551 }
4552
4553 /**
4554  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4555  *  @hw: pointer to hardware structure
4556  **/
4557 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4558 {
4559         s32 status;
4560
4561         status = ixgbe_reset_phy_generic(hw);
4562
4563         if (status != IXGBE_SUCCESS)
4564                 return status;
4565
4566         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4567         return ixgbe_enable_lasi_ext_t_x550em(hw);
4568 }
4569
4570 /**
4571  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4572  *  @hw: pointer to hardware structure
4573  *  @led_idx: led number to turn on
4574  **/
4575 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4576 {
4577         u16 phy_data;
4578
4579         DEBUGFUNC("ixgbe_led_on_t_X550em");
4580
4581         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4582                 return IXGBE_ERR_PARAM;
4583
4584         /* To turn on the LED, set mode to ON. */
4585         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4586                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4587         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4588         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4589                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4590
4591         return IXGBE_SUCCESS;
4592 }
4593
4594 /**
4595  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4596  *  @hw: pointer to hardware structure
4597  *  @led_idx: led number to turn off
4598  **/
4599 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4600 {
4601         u16 phy_data;
4602
4603         DEBUGFUNC("ixgbe_led_off_t_X550em");
4604
4605         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4606                 return IXGBE_ERR_PARAM;
4607
4608         /* To turn on the LED, set mode to ON. */
4609         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4610                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4611         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4612         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4613                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4614
4615         return IXGBE_SUCCESS;
4616 }
4617