drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41
  42 /**
  43  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  44  *  @hw: pointer to hardware structure
  45  *
  46  *  Initialize the function pointers and assign the MAC type for X550.
  47  *  Does not touch the hardware.
  48  **/
  49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  50 {
  51         struct ixgbe_mac_info *mac = &hw->mac;
  52         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  53         s32 ret_val;
  54
  55         DEBUGFUNC("ixgbe_init_ops_X550");
  56
  57         ret_val = ixgbe_init_ops_X540(hw);
  58         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  59         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  60         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  61         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  62         mac->ops.set_source_address_pruning =
  63                         ixgbe_set_source_address_pruning_X550;
  64         mac->ops.set_ethertype_anti_spoofing =
  65                         ixgbe_set_ethertype_anti_spoofing_X550;
  66
  67         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  68         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  69         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  70         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  71         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  72         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  73         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  74         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  75         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  76
  77         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  78         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  79         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  80         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  81         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  82         return ret_val;
  83 }
  84
  85 /**
  86  * ixgbe_read_cs4227 - Read CS4227 register
  87  * @hw: pointer to hardware structure
  88  * @reg: register number to write
  89  * @value: pointer to receive value read
  90  *
  91  * Returns status code
  92  **/
  93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  94 {
  95         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
  96 }
  97
  98 /**
  99  * ixgbe_write_cs4227 - Write CS4227 register
 100  * @hw: pointer to hardware structure
 101  * @reg: register number to write
 102  * @value: value to write to register
 103  *
 104  * Returns status code
 105  **/
 106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 107 {
 108         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 109 }
 110
 111 /**
 112  * ixgbe_get_cs4227_status - Return CS4227 status
 113  * @hw: pointer to hardware structure
 114  *
 115  * Returns error if CS4227 not successfully initialized
 116  **/
 117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
 118 {
 119         s32 status;
 120         u16 value = 0;
 121         u8 retry;
 122
 123         for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
 124                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
 125                                            &value);
 126                 if (status != IXGBE_SUCCESS)
 127                         return status;
 128                 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
 129                         break;
 130                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 131         }
 132         if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
 133                 return IXGBE_ERR_PHY;
 134
 135         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 136                                     IXGBE_CS4227_SCRATCH_VALUE);
 137         if (status != IXGBE_SUCCESS)
 138                 return status;
 139         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 140         if (status != IXGBE_SUCCESS)
 141                 return status;
 142         if (value != IXGBE_CS4227_SCRATCH_VALUE)
 143                 return IXGBE_ERR_PHY;
 144         return IXGBE_SUCCESS;
 145 }
 146
 147 /**
 148  * ixgbe_read_pe - Read register from port expander
 149  * @hw: pointer to hardware structure
 150  * @reg: register number to read
 151  * @value: pointer to receive read value
 152  *
 153  * Returns status code
 154  **/
 155 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 156 {
 157         s32 status;
 158
 159         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 160         if (status != IXGBE_SUCCESS)
 161                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 162                               "port expander access failed with %d\n", status);
 163         return status;
 164 }
 165
 166 /**
 167  * ixgbe_write_pe - Write register to port expander
 168  * @hw: pointer to hardware structure
 169  * @reg: register number to write
 170  * @value: value to write
 171  *
 172  * Returns status code
 173  **/
 174 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 175 {
 176         s32 status;
 177
 178         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 179         if (status != IXGBE_SUCCESS)
 180                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 181                               "port expander access failed with %d\n", status);
 182         return status;
 183 }
 184
 185 /**
 186  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 187  * @hw: pointer to hardware structure
 188  *
 189  * Returns error code
 190  **/
 191 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 192 {
 193         s32 status;
 194         u8 reg;
 195
 196         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199         reg |= IXGBE_PE_BIT1;
 200         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 201         if (status != IXGBE_SUCCESS)
 202                 return status;
 203
 204         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 205         if (status != IXGBE_SUCCESS)
 206                 return status;
 207         reg &= ~IXGBE_PE_BIT1;
 208         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 209         if (status != IXGBE_SUCCESS)
 210                 return status;
 211
 212         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 213         if (status != IXGBE_SUCCESS)
 214                 return status;
 215         reg &= ~IXGBE_PE_BIT1;
 216         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 217         if (status != IXGBE_SUCCESS)
 218                 return status;
 219
 220         usec_delay(IXGBE_CS4227_RESET_HOLD);
 221
 222         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 223         if (status != IXGBE_SUCCESS)
 224                 return status;
 225         reg |= IXGBE_PE_BIT1;
 226         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 227         if (status != IXGBE_SUCCESS)
 228                 return status;
 229
 230         msec_delay(IXGBE_CS4227_RESET_DELAY);
 231
 232         return IXGBE_SUCCESS;
 233 }
 234
 235 /**
 236  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 237  * @hw: pointer to hardware structure
 238  **/
 239 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 240 {
 241         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 242         s32 status;
 243         u8 retry;
 244
 245         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 246                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 247                 if (status != IXGBE_SUCCESS) {
 248                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 249                                       "semaphore failed with %d\n", status);
 250                         return;
 251                 }
 252                 status = ixgbe_get_cs4227_status(hw);
 253                 if (status == IXGBE_SUCCESS) {
 254                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 255                         msec_delay(hw->eeprom.semaphore_delay);
 256                         return;
 257                 }
 258                 ixgbe_reset_cs4227(hw);
 259                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 260                 msec_delay(hw->eeprom.semaphore_delay);
 261         }
 262         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 263                       "Unable to initialize CS4227, err=%d\n", status);
 264 }
 265
 266 /**
 267  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 268  * @hw: pointer to hardware structure
 269  **/
 270 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 271 {
 272         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 273
 274         if (hw->bus.lan_id) {
 275                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 276                 esdp |= IXGBE_ESDP_SDP1_DIR;
 277         }
 278         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 279         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 280         IXGBE_WRITE_FLUSH(hw);
 281 }
 282
 283 /**
 284  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 285  * @hw: pointer to hardware structure
 286  *
 287  * Returns error code
 288  */
 289 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 290 {
 291         switch (hw->device_id) {
 292         case IXGBE_DEV_ID_X550EM_X_SFP:
 293                 /* set up for CS4227 usage */
 294                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 295                 ixgbe_setup_mux_ctl(hw);
 296                 ixgbe_check_cs4227(hw);
 297
 298                 return ixgbe_identify_module_generic(hw);
 299                 break;
 300         case IXGBE_DEV_ID_X550EM_X_KX4:
 301                 hw->phy.type = ixgbe_phy_x550em_kx4;
 302                 break;
 303         case IXGBE_DEV_ID_X550EM_X_KR:
 304                 hw->phy.type = ixgbe_phy_x550em_kr;
 305                 break;
 306         case IXGBE_DEV_ID_X550EM_X_1G_T:
 307         case IXGBE_DEV_ID_X550EM_X_10G_T:
 308                 return ixgbe_identify_phy_generic(hw);
 309         default:
 310                 break;
 311         }
 312         return IXGBE_SUCCESS;
 313 }
 314
 315 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 316                                      u32 device_type, u16 *phy_data)
 317 {
 318         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 319         return IXGBE_NOT_IMPLEMENTED;
 320 }
 321
 322 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 323                                       u32 device_type, u16 phy_data)
 324 {
 325         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 326         return IXGBE_NOT_IMPLEMENTED;
 327 }
 328
 329 /**
 330 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 331 *  @hw: pointer to hardware structure
 332 *
 333 *  Initialize the function pointers and for MAC type X550EM.
 334 *  Does not touch the hardware.
 335 **/
 336 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 337 {
 338         struct ixgbe_mac_info *mac = &hw->mac;
 339         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 340         struct ixgbe_phy_info *phy = &hw->phy;
 341         s32 ret_val;
 342
 343         DEBUGFUNC("ixgbe_init_ops_X550EM");
 344
 345         /* Similar to X550 so start there. */
 346         ret_val = ixgbe_init_ops_X550(hw);
 347
 348         /* Since this function eventually calls
 349          * ixgbe_init_ops_540 by design, we are setting
 350          * the pointers to NULL explicitly here to overwrite
 351          * the values being set in the x540 function.
 352          */
 353         /* Thermal sensor not supported in x550EM */
 354         mac->ops.get_thermal_sensor_data = NULL;
 355         mac->ops.init_thermal_sensor_thresh = NULL;
 356         mac->thermal_sensor_enabled = false;
 357
 358         /* FCOE not supported in x550EM */
 359         mac->ops.get_san_mac_addr = NULL;
 360         mac->ops.set_san_mac_addr = NULL;
 361         mac->ops.get_wwn_prefix = NULL;
 362         mac->ops.get_fcoe_boot_status = NULL;
 363
 364         /* IPsec not supported in x550EM */
 365         mac->ops.disable_sec_rx_path = NULL;
 366         mac->ops.enable_sec_rx_path = NULL;
 367
 368         /* AUTOC register is not present in x550EM. */
 369         mac->ops.prot_autoc_read = NULL;
 370         mac->ops.prot_autoc_write = NULL;
 371
 372         /* X550EM bus type is internal*/
 373         hw->bus.type = ixgbe_bus_type_internal;
 374         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 375
 376         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 377         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 378         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 379         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 380         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 381         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 382         mac->ops.get_supported_physical_layer =
 383                                     ixgbe_get_supported_physical_layer_X550em;
 384
 385         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 386                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 387         else
 388                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 389
 390         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 391         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 392
 393         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
 394                 mac->ops.setup_eee = NULL;
 395
 396         /* PHY */
 397         phy->ops.init = ixgbe_init_phy_ops_X550em;
 398         phy->ops.identify = ixgbe_identify_phy_x550em;
 399         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 400                 phy->ops.set_phy_power = NULL;
 401
 402
 403         /* EEPROM */
 404         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 405         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 406         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 407         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 408         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 409         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 410         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 411         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 412
 413         return ret_val;
 414 }
 415
 416 /**
 417  *  ixgbe_dmac_config_X550
 418  *  @hw: pointer to hardware structure
 419  *
 420  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 421  *  When disabling dmac, dmac enable dmac bit is cleared.
 422  **/
 423 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 424 {
 425         u32 reg, high_pri_tc;
 426
 427         DEBUGFUNC("ixgbe_dmac_config_X550");
 428
 429         /* Disable DMA coalescing before configuring */
 430         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 431         reg &= ~IXGBE_DMACR_DMAC_EN;
 432         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 433
 434         /* Disable DMA Coalescing if the watchdog timer is 0 */
 435         if (!hw->mac.dmac_config.watchdog_timer)
 436                 goto out;
 437
 438         ixgbe_dmac_config_tcs_X550(hw);
 439
 440         /* Configure DMA Coalescing Control Register */
 441         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 442
 443         /* Set the watchdog timer in units of 40.96 usec */
 444         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 445         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 446
 447         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 448         /* If fcoe is enabled, set high priority traffic class */
 449         if (hw->mac.dmac_config.fcoe_en) {
 450                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 451                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 452                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 453         }
 454         reg |= IXGBE_DMACR_EN_MNG_IND;
 455
 456         /* Enable DMA coalescing after configuration */
 457         reg |= IXGBE_DMACR_DMAC_EN;
 458         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 459
 460 out:
 461         return IXGBE_SUCCESS;
 462 }
 463
 464 /**
 465  *  ixgbe_dmac_config_tcs_X550
 466  *  @hw: pointer to hardware structure
 467  *
 468  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 469  *  be cleared before configuring.
 470  **/
 471 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 472 {
 473         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 474
 475         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 476
 477         /* Configure DMA coalescing enabled */
 478         switch (hw->mac.dmac_config.link_speed) {
 479         case IXGBE_LINK_SPEED_100_FULL:
 480                 pb_headroom = IXGBE_DMACRXT_100M;
 481                 break;
 482         case IXGBE_LINK_SPEED_1GB_FULL:
 483                 pb_headroom = IXGBE_DMACRXT_1G;
 484                 break;
 485         default:
 486                 pb_headroom = IXGBE_DMACRXT_10G;
 487                 break;
 488         }
 489
 490         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 491                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 492
 493         /* Set the per Rx packet buffer receive threshold */
 494         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 495                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 496                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 497
 498                 if (tc < hw->mac.dmac_config.num_tcs) {
 499                         /* Get Rx PB size */
 500                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 501                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 502                                 IXGBE_RXPBSIZE_SHIFT;
 503
 504                         /* Calculate receive buffer threshold in kilobytes */
 505                         if (rx_pb_size > pb_headroom)
 506                                 rx_pb_size = rx_pb_size - pb_headroom;
 507                         else
 508                                 rx_pb_size = 0;
 509
 510                         /* Minimum of MFS shall be set for DMCTH */
 511                         reg |= (rx_pb_size > maxframe_size_kb) ?
 512                                 rx_pb_size : maxframe_size_kb;
 513                 }
 514                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 515         }
 516         return IXGBE_SUCCESS;
 517 }
 518
 519 /**
 520  *  ixgbe_dmac_update_tcs_X550
 521  *  @hw: pointer to hardware structure
 522  *
 523  *  Disables dmac, updates per TC settings, and then enables dmac.
 524  **/
 525 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 526 {
 527         u32 reg;
 528
 529         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 530
 531         /* Disable DMA coalescing before configuring */
 532         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 533         reg &= ~IXGBE_DMACR_DMAC_EN;
 534         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 535
 536         ixgbe_dmac_config_tcs_X550(hw);
 537
 538         /* Enable DMA coalescing after configuration */
 539         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 540         reg |= IXGBE_DMACR_DMAC_EN;
 541         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 542
 543         return IXGBE_SUCCESS;
 544 }
 545
 546 /**
 547  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 548  *  @hw: pointer to hardware structure
 549  *
 550  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 551  *  ixgbe_hw struct in order to set up EEPROM access.
 552  **/
 553 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 554 {
 555         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 556         u32 eec;
 557         u16 eeprom_size;
 558
 559         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 560
 561         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 562                 eeprom->semaphore_delay = 10;
 563                 eeprom->type = ixgbe_flash;
 564
 565                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 566                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 567                                     IXGBE_EEC_SIZE_SHIFT);
 568                 eeprom->word_size = 1 << (eeprom_size +
 569                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 570
 571                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 572                           eeprom->type, eeprom->word_size);
 573         }
 574
 575         return IXGBE_SUCCESS;
 576 }
 577
 578 /**
 579  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 580  *  @hw: pointer to the HW structure
 581  *  @enable_eee: boolean flag to enable EEE
 582  *
 583  *  Enable/disable EEE based on enable_eee flag.
 584  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 585  *  are modified.
 586  *
 587  **/
 588 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 589 {
 590         u32 eeer;
 591         u16 autoneg_eee_reg;
 592         u32 link_reg;
 593         s32 status;
 594
 595         DEBUGFUNC("ixgbe_setup_eee_X550");
 596
 597         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 598         /* Enable or disable EEE per flag */
 599         if (enable_eee) {
 600                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 601
 602                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 603                         /* Advertise EEE capability */
 604                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 605                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 606
 607                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 608                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 609                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 610
 611                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 612                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 613                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 614                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 615                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 616                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 617                         if (status != IXGBE_SUCCESS)
 618                                 return status;
 619
 620                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 621                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 622
 623                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 624                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 625                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 626                         if (status != IXGBE_SUCCESS)
 627                                 return status;
 628                 }
 629         } else {
 630                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 631
 632                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 633                         /* Disable advertised EEE capability */
 634                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 635                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 636
 637                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 638                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 639                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 640
 641                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 642                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 643                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 644                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 645                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 646                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 647                         if (status != IXGBE_SUCCESS)
 648                                 return status;
 649
 650                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 651                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 652
 653                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 654                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 655                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 656                         if (status != IXGBE_SUCCESS)
 657                                 return status;
 658                 }
 659         }
 660         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 661
 662         return IXGBE_SUCCESS;
 663 }
 664
 665 /**
 666  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 667  * @hw: pointer to hardware structure
 668  * @enable: enable or disable source address pruning
 669  * @pool: Rx pool to set source address pruning for
 670  **/
 671 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 672                                            unsigned int pool)
 673 {
 674         u64 pfflp;
 675
 676         /* max rx pool is 63 */
 677         if (pool > 63)
 678                 return;
 679
 680         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 681         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 682
 683         if (enable)
 684                 pfflp |= (1ULL << pool);
 685         else
 686                 pfflp &= ~(1ULL << pool);
 687
 688         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 689         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 690 }
 691
 692 /**
 693  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 694  *  @hw: pointer to hardware structure
 695  *  @enable: enable or disable switch for Ethertype anti-spoofing
 696  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 697  *
 698  **/
 699 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 700                 bool enable, int vf)
 701 {
 702         int vf_target_reg = vf >> 3;
 703         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 704         u32 pfvfspoof;
 705
 706         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 707
 708         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 709         if (enable)
 710                 pfvfspoof |= (1 << vf_target_shift);
 711         else
 712                 pfvfspoof &= ~(1 << vf_target_shift);
 713
 714         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 715 }
 716
 717 /**
 718  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 719  *  device
 720  *  @hw: pointer to hardware structure
 721  *  @reg_addr: 32 bit PHY register to write
 722  *  @device_type: 3 bit device type
 723  *  @data: Data to write to the register
 724  **/
 725 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 726                             u32 device_type, u32 data)
 727 {
 728         u32 i, command, error;
 729
 730         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 731                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 732
 733         /* Write IOSF control register */
 734         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 735
 736         /* Write IOSF data register */
 737         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 738         /*
 739          * Check every 10 usec to see if the address cycle completed.
 740          * The SB IOSF BUSY bit will clear when the operation is
 741          * complete
 742          */
 743         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 744                 usec_delay(10);
 745
 746                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 747                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 748                         break;
 749         }
 750
 751         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 752                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 753                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 754                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 755                               "Failed to write, error %x\n", error);
 756                 return IXGBE_ERR_PHY;
 757         }
 758
 759         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 760                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
 761                 return IXGBE_ERR_PHY;
 762         }
 763
 764         return IXGBE_SUCCESS;
 765 }
 766
 767 /**
 768  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 769  *  device
 770  *  @hw: pointer to hardware structure
 771  *  @reg_addr: 32 bit PHY register to write
 772  *  @device_type: 3 bit device type
 773  *  @phy_data: Pointer to read data from the register
 774  **/
 775 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 776                            u32 device_type, u32 *data)
 777 {
 778         u32 i, command, error;
 779
 780         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 781                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 782
 783         /* Write IOSF control register */
 784         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 785
 786         /*
 787          * Check every 10 usec to see if the address cycle completed.
 788          * The SB IOSF BUSY bit will clear when the operation is
 789          * complete
 790          */
 791         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 792                 usec_delay(10);
 793
 794                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 795                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 796                         break;
 797         }
 798
 799         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 800                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 801                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 802                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 803                                 "Failed to read, error %x\n", error);
 804                 return IXGBE_ERR_PHY;
 805         }
 806
 807         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 808                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
 809                 return IXGBE_ERR_PHY;
 810         }
 811
 812         *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 813
 814         return IXGBE_SUCCESS;
 815 }
 816
 817 /**
 818  *  ixgbe_disable_mdd_X550
 819  *  @hw: pointer to hardware structure
 820  *
 821  *  Disable malicious driver detection
 822  **/
 823 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 824 {
 825         u32 reg;
 826
 827         DEBUGFUNC("ixgbe_disable_mdd_X550");
 828
 829         /* Disable MDD for TX DMA and interrupt */
 830         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 831         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 832         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 833
 834         /* Disable MDD for RX and interrupt */
 835         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 836         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 837         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 838 }
 839
 840 /**
 841  *  ixgbe_enable_mdd_X550
 842  *  @hw: pointer to hardware structure
 843  *
 844  *  Enable malicious driver detection
 845  **/
 846 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 847 {
 848         u32 reg;
 849
 850         DEBUGFUNC("ixgbe_enable_mdd_X550");
 851
 852         /* Enable MDD for TX DMA and interrupt */
 853         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 854         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 855         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 856
 857         /* Enable MDD for RX and interrupt */
 858         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 859         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 860         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 861 }
 862
 863 /**
 864  *  ixgbe_restore_mdd_vf_X550
 865  *  @hw: pointer to hardware structure
 866  *  @vf: vf index
 867  *
 868  *  Restore VF that was disabled during malicious driver detection event
 869  **/
 870 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 871 {
 872         u32 idx, reg, num_qs, start_q, bitmask;
 873
 874         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 875
 876         /* Map VF to queues */
 877         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 878         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 879         case IXGBE_MRQC_VMDQRT8TCEN:
 880                 num_qs = 8;  /* 16 VFs / pools */
 881                 bitmask = 0x000000FF;
 882                 break;
 883         case IXGBE_MRQC_VMDQRSS32EN:
 884         case IXGBE_MRQC_VMDQRT4TCEN:
 885                 num_qs = 4;  /* 32 VFs / pools */
 886                 bitmask = 0x0000000F;
 887                 break;
 888         default:            /* 64 VFs / pools */
 889                 num_qs = 2;
 890                 bitmask = 0x00000003;
 891                 break;
 892         }
 893         start_q = vf * num_qs;
 894
 895         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 896         idx = start_q / 32;
 897         reg = 0;
 898         reg |= (bitmask << (start_q % 32));
 899         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 900         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 901 }
 902
 903 /**
 904  *  ixgbe_mdd_event_X550
 905  *  @hw: pointer to hardware structure
 906  *  @vf_bitmap: vf bitmap of malicious vfs
 907  *
 908  *  Handle malicious driver detection event.
 909  **/
 910 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 911 {
 912         u32 wqbr;
 913         u32 i, j, reg, q, shift, vf, idx;
 914
 915         DEBUGFUNC("ixgbe_mdd_event_X550");
 916
 917         /* figure out pool size for mapping to vf's */
 918         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 919         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 920         case IXGBE_MRQC_VMDQRT8TCEN:
 921                 shift = 3;  /* 16 VFs / pools */
 922                 break;
 923         case IXGBE_MRQC_VMDQRSS32EN:
 924         case IXGBE_MRQC_VMDQRT4TCEN:
 925                 shift = 2;  /* 32 VFs / pools */
 926                 break;
 927         default:
 928                 shift = 1;  /* 64 VFs / pools */
 929                 break;
 930         }
 931
 932         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
 933         for (i = 0; i < 4; i++) {
 934                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
 935                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
 936
 937                 if (!wqbr)
 938                         continue;
 939
 940                 /* Get malicious queue */
 941                 for (j = 0; j < 32 && wqbr; j++) {
 942
 943                         if (!(wqbr & (1 << j)))
 944                                 continue;
 945
 946                         /* Get queue from bitmask */
 947                         q = j + (i * 32);
 948
 949                         /* Map queue to vf */
 950                         vf = (q >> shift);
 951
 952                         /* Set vf bit in vf_bitmap */
 953                         idx = vf / 32;
 954                         vf_bitmap[idx] |= (1 << (vf % 32));
 955                         wqbr &= ~(1 << j);
 956                 }
 957         }
 958 }
 959
 960 /**
 961  *  ixgbe_get_media_type_X550em - Get media type
 962  *  @hw: pointer to hardware structure
 963  *
 964  *  Returns the media type (fiber, copper, backplane)
 965  */
 966 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
 967 {
 968         enum ixgbe_media_type media_type;
 969
 970         DEBUGFUNC("ixgbe_get_media_type_X550em");
 971
 972         /* Detect if there is a copper PHY attached. */
 973         switch (hw->device_id) {
 974         case IXGBE_DEV_ID_X550EM_X_KR:
 975         case IXGBE_DEV_ID_X550EM_X_KX4:
 976                 media_type = ixgbe_media_type_backplane;
 977                 break;
 978         case IXGBE_DEV_ID_X550EM_X_SFP:
 979                 media_type = ixgbe_media_type_fiber;
 980                 break;
 981         case IXGBE_DEV_ID_X550EM_X_1G_T:
 982         case IXGBE_DEV_ID_X550EM_X_10G_T:
 983                 media_type = ixgbe_media_type_copper;
 984                 break;
 985         default:
 986                 media_type = ixgbe_media_type_unknown;
 987                 break;
 988         }
 989         return media_type;
 990 }
 991
 992 /**
 993  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
 994  *  @hw: pointer to hardware structure
 995  *  @linear: true if SFP module is linear
 996  */
 997 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
 998 {
 999         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1000
1001         switch (hw->phy.sfp_type) {
1002         case ixgbe_sfp_type_not_present:
1003                 return IXGBE_ERR_SFP_NOT_PRESENT;
1004         case ixgbe_sfp_type_da_cu_core0:
1005         case ixgbe_sfp_type_da_cu_core1:
1006                 *linear = true;
1007                 break;
1008         case ixgbe_sfp_type_srlr_core0:
1009         case ixgbe_sfp_type_srlr_core1:
1010         case ixgbe_sfp_type_da_act_lmt_core0:
1011         case ixgbe_sfp_type_da_act_lmt_core1:
1012         case ixgbe_sfp_type_1g_sx_core0:
1013         case ixgbe_sfp_type_1g_sx_core1:
1014         case ixgbe_sfp_type_1g_lx_core0:
1015         case ixgbe_sfp_type_1g_lx_core1:
1016                 *linear = false;
1017                 break;
1018         case ixgbe_sfp_type_unknown:
1019         case ixgbe_sfp_type_1g_cu_core0:
1020         case ixgbe_sfp_type_1g_cu_core1:
1021         default:
1022                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1023         }
1024
1025         return IXGBE_SUCCESS;
1026 }
1027
1028 /**
1029  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1030  *  @hw: pointer to hardware structure
1031  *
1032  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1033  **/
1034 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1035 {
1036         s32 status;
1037         bool linear;
1038
1039         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1040
1041         status = ixgbe_identify_module_generic(hw);
1042
1043         if (status != IXGBE_SUCCESS)
1044                 return status;
1045
1046         /* Check if SFP module is supported */
1047         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1048
1049         return status;
1050 }
1051
1052 /**
1053  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1054  *  @hw: pointer to hardware structure
1055  */
1056 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1057 {
1058         s32 status;
1059         bool linear;
1060
1061         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1062
1063         /* Check if SFP module is supported */
1064         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1065
1066         if (status != IXGBE_SUCCESS)
1067                 return status;
1068
1069         ixgbe_init_mac_link_ops_X550em(hw);
1070         hw->phy.ops.reset = NULL;
1071
1072         return IXGBE_SUCCESS;
1073 }
1074
1075 /**
1076  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1077  *  @hw: pointer to hardware structure
1078  */
1079 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1080 {
1081         struct ixgbe_mac_info *mac = &hw->mac;
1082
1083         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1084
1085          switch (hw->mac.ops.get_media_type(hw)) {
1086          case ixgbe_media_type_fiber:
1087                 /* CS4227 does not support autoneg, so disable the laser control
1088                  * functions for SFP+ fiber
1089                  */
1090                 mac->ops.disable_tx_laser = NULL;
1091                 mac->ops.enable_tx_laser = NULL;
1092                 mac->ops.flap_tx_laser = NULL;
1093                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1094                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1095                 mac->ops.set_rate_select_speed =
1096                                         ixgbe_set_soft_rate_select_speed;
1097                 break;
1098         case ixgbe_media_type_copper:
1099                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1100                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1101                 break;
1102         default:
1103                 break;
1104          }
1105 }
1106
1107 /**
1108  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1109  *  @hw: pointer to hardware structure
1110  *  @speed: pointer to link speed
1111  *  @autoneg: true when autoneg or autotry is enabled
1112  */
1113 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1114                                        ixgbe_link_speed *speed,
1115                                        bool *autoneg)
1116 {
1117         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1118
1119         /* SFP */
1120         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1121
1122                 /* CS4227 SFP must not enable auto-negotiation */
1123                 *autoneg = false;
1124
1125                 /* Check if 1G SFP module. */
1126                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1127                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1128                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1129                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1130                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1131                         return IXGBE_SUCCESS;
1132                 }
1133
1134                 /* Link capabilities are based on SFP */
1135                 if (hw->phy.multispeed_fiber)
1136                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1137                                  IXGBE_LINK_SPEED_1GB_FULL;
1138                 else
1139                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1140         } else {
1141                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1142                          IXGBE_LINK_SPEED_1GB_FULL;
1143                 *autoneg = true;
1144         }
1145
1146         return IXGBE_SUCCESS;
1147 }
1148
1149 /**
1150  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1151  * @hw: pointer to hardware structure
1152  * @lsc: pointer to boolean flag which indicates whether external Base T
1153  *       PHY interrupt is lsc
1154  *
1155  * Determime if external Base T PHY interrupt cause is high temperature
1156  * failure alarm or link status change.
1157  *
1158  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1159  * failure alarm, else return PHY access status.
1160  */
1161 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1162 {
1163         u32 status;
1164         u16 reg;
1165
1166         *lsc = false;
1167
1168         /* Vendor alarm triggered */
1169         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1170                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1171                                       &reg);
1172
1173         if (status != IXGBE_SUCCESS ||
1174             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1175                 return status;
1176
1177         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1178         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1179                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1180                                       &reg);
1181
1182         if (status != IXGBE_SUCCESS ||
1183             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1184             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1185                 return status;
1186
1187         /* High temperature failure alarm triggered */
1188         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1189                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1190                                       &reg);
1191
1192         if (status != IXGBE_SUCCESS)
1193                 return status;
1194
1195         /* If high temperature failure, then return over temp error and exit */
1196         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL)
1197                 return IXGBE_ERR_OVERTEMP;
1198
1199         /* Vendor alarm 2 triggered */
1200         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1201                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1202
1203         if (status != IXGBE_SUCCESS ||
1204             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1205                 return status;
1206
1207         /* link connect/disconnect event occurred */
1208         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1209                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1210
1211         if (status != IXGBE_SUCCESS)
1212                 return status;
1213
1214         /* Indicate LSC */
1215         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1216                 *lsc = true;
1217
1218         return IXGBE_SUCCESS;
1219 }
1220
1221 /**
1222  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1223  * @hw: pointer to hardware structure
1224  *
1225  * Enable link status change and temperature failure alarm for the external
1226  * Base T PHY
1227  *
1228  * Returns PHY access status
1229  */
1230 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1231 {
1232         u32 status;
1233         u16 reg;
1234         bool lsc;
1235
1236         /* Clear interrupt flags */
1237         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1238
1239         /* Enable link status change alarm */
1240         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1241                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1242
1243         if (status != IXGBE_SUCCESS)
1244                 return status;
1245
1246         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1247
1248         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1249                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1250
1251         if (status != IXGBE_SUCCESS)
1252                 return status;
1253
1254         /* Enables high temperature failure alarm */
1255         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1256                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1257                                       &reg);
1258
1259         if (status != IXGBE_SUCCESS)
1260                 return status;
1261
1262         reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1263
1264         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1265                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1266                                        reg);
1267
1268         if (status != IXGBE_SUCCESS)
1269                 return status;
1270
1271         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1272         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1273                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1274                                       &reg);
1275
1276         if (status != IXGBE_SUCCESS)
1277                 return status;
1278
1279         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1280                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1281
1282         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1283                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1284                                        reg);
1285
1286         if (status != IXGBE_SUCCESS)
1287                 return status;
1288
1289         /* Enable chip-wide vendor alarm */
1290         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1291                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1292                                       &reg);
1293
1294         if (status != IXGBE_SUCCESS)
1295                 return status;
1296
1297         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1298
1299         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1300                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1301                                        reg);
1302
1303         return status;
1304 }
1305
1306 /**
1307  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1308  *  @hw: pointer to hardware structure
1309  *
1310  *  Initialize any function pointers that were not able to be
1311  *  set during init_shared_code because the PHY/SFP type was
1312  *  not known.  Perform the SFP init if necessary.
1313  */
1314 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1315 {
1316         struct ixgbe_phy_info *phy = &hw->phy;
1317         s32 ret_val;
1318
1319         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1320
1321         hw->mac.ops.set_lan_id(hw);
1322
1323         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1324                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1325                 ixgbe_setup_mux_ctl(hw);
1326
1327                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1328         }
1329
1330         /* Identify the PHY or SFP module */
1331         ret_val = phy->ops.identify(hw);
1332         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1333                 return ret_val;
1334
1335         /* Setup function pointers based on detected hardware */
1336         ixgbe_init_mac_link_ops_X550em(hw);
1337         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1338                 phy->ops.reset = NULL;
1339
1340         /* Set functions pointers based on phy type */
1341         switch (hw->phy.type) {
1342         case ixgbe_phy_x550em_kx4:
1343                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1344                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1345                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1346                 break;
1347         case ixgbe_phy_x550em_kr:
1348                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1349                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1350                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1351                 break;
1352         case ixgbe_phy_x550em_ext_t:
1353                 phy->ops.setup_internal_link =
1354                                          ixgbe_setup_internal_phy_t_x550em;
1355                 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1356                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1357                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1358                 break;
1359         default:
1360                 break;
1361         }
1362         return ret_val;
1363 }
1364
1365 /**
1366  *  ixgbe_reset_hw_X550em - Perform hardware reset
1367  *  @hw: pointer to hardware structure
1368  *
1369  *  Resets the hardware by resetting the transmit and receive units, masks
1370  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1371  *  reset.
1372  */
1373 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1374 {
1375         ixgbe_link_speed link_speed;
1376         s32 status;
1377         u32 ctrl = 0;
1378         u32 i;
1379         bool link_up = false;
1380
1381         DEBUGFUNC("ixgbe_reset_hw_X550em");
1382
1383         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1384         status = hw->mac.ops.stop_adapter(hw);
1385         if (status != IXGBE_SUCCESS)
1386                 return status;
1387
1388         /* flush pending Tx transactions */
1389         ixgbe_clear_tx_pending(hw);
1390
1391         /* PHY ops must be identified and initialized prior to reset */
1392
1393         /* Identify PHY and related function pointers */
1394         status = hw->phy.ops.init(hw);
1395
1396         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1397                 return status;
1398
1399         /* start the external PHY */
1400         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1401                 status = ixgbe_init_ext_t_x550em(hw);
1402                 if (status)
1403                         return status;
1404         }
1405
1406         /* Setup SFP module if there is one present. */
1407         if (hw->phy.sfp_setup_needed) {
1408                 status = hw->mac.ops.setup_sfp(hw);
1409                 hw->phy.sfp_setup_needed = false;
1410         }
1411
1412         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1413                 return status;
1414
1415         /* Reset PHY */
1416         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1417                 hw->phy.ops.reset(hw);
1418
1419 mac_reset_top:
1420         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1421          * If link reset is used when link is up, it might reset the PHY when
1422          * mng is using it.  If link is down or the flag to force full link
1423          * reset is set, then perform link reset.
1424          */
1425         ctrl = IXGBE_CTRL_LNK_RST;
1426         if (!hw->force_full_reset) {
1427                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1428                 if (link_up)
1429                         ctrl = IXGBE_CTRL_RST;
1430         }
1431
1432         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1433         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1434         IXGBE_WRITE_FLUSH(hw);
1435
1436         /* Poll for reset bit to self-clear meaning reset is complete */
1437         for (i = 0; i < 10; i++) {
1438                 usec_delay(1);
1439                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1440                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1441                         break;
1442         }
1443
1444         if (ctrl & IXGBE_CTRL_RST_MASK) {
1445                 status = IXGBE_ERR_RESET_FAILED;
1446                 DEBUGOUT("Reset polling failed to complete.\n");
1447         }
1448
1449         msec_delay(50);
1450
1451         /* Double resets are required for recovery from certain error
1452          * conditions.  Between resets, it is necessary to stall to
1453          * allow time for any pending HW events to complete.
1454          */
1455         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1456                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1457                 goto mac_reset_top;
1458         }
1459
1460         /* Store the permanent mac address */
1461         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1462
1463         /* Store MAC address from RAR0, clear receive address registers, and
1464          * clear the multicast table.  Also reset num_rar_entries to 128,
1465          * since we modify this value when programming the SAN MAC address.
1466          */
1467         hw->mac.num_rar_entries = 128;
1468         hw->mac.ops.init_rx_addrs(hw);
1469
1470
1471         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1472                 ixgbe_setup_mux_ctl(hw);
1473
1474         return status;
1475 }
1476
1477 /**
1478  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1479  * @hw: pointer to hardware structure
1480  */
1481 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1482 {
1483         u32 status;
1484         u16 reg;
1485
1486         status = hw->phy.ops.read_reg(hw,
1487                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1488                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1489                                       &reg);
1490
1491         if (status != IXGBE_SUCCESS)
1492                 return status;
1493
1494         /* If PHY FW reset completed bit is set then this is the first
1495          * SW instance after a power on so the PHY FW must be un-stalled.
1496          */
1497         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1498                 status = hw->phy.ops.read_reg(hw,
1499                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1500                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1501                                         &reg);
1502
1503                 if (status != IXGBE_SUCCESS)
1504                         return status;
1505
1506                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1507
1508                 status = hw->phy.ops.write_reg(hw,
1509                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1510                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1511                                         reg);
1512
1513                 if (status != IXGBE_SUCCESS)
1514                         return status;
1515         }
1516
1517         return status;
1518 }
1519
1520 /**
1521  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1522  *  @hw: pointer to hardware structure
1523  *
1524  *  Configures the integrated KR PHY.
1525  **/
1526 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1527 {
1528         s32 status;
1529         u32 reg_val;
1530
1531         status = ixgbe_read_iosf_sb_reg_x550(hw,
1532                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1533                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1534         if (status)
1535                 return status;
1536
1537         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1538         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1539                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1540         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1541                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1542
1543         /* Advertise 10G support. */
1544         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1545                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1546
1547         /* Advertise 1G support. */
1548         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1549                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1550
1551         /* Restart auto-negotiation. */
1552         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1553         status = ixgbe_write_iosf_sb_reg_x550(hw,
1554                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1555                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1556
1557         return status;
1558 }
1559
1560 /**
1561  *  ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1562  *  @hw: pointer to hardware structure
1563  *
1564  *  Configures the integrated KX4 PHY.
1565  **/
1566 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1567 {
1568         s32 status;
1569         u32 reg_val;
1570
1571         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1572                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, &reg_val);
1573         if (status)
1574                 return status;
1575
1576         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1577                         IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1578
1579         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1580
1581         /* Advertise 10G support. */
1582         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1583                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1584
1585         /* Advertise 1G support. */
1586         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1587                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1588
1589         /* Restart auto-negotiation. */
1590         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1591         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1592                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, reg_val);
1593
1594         return status;
1595 }
1596
1597 /**
1598  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1599  *  @hw: pointer to hardware structure
1600  *  @speed: the link speed to force
1601  *
1602  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1603  *  internal and external PHY at a specific speed, without autonegotiation.
1604  **/
1605 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1606 {
1607         s32 status;
1608         u32 reg_val;
1609
1610         /* Disable AN and force speed to 10G Serial. */
1611         status = ixgbe_read_iosf_sb_reg_x550(hw,
1612                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1613                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1614         if (status != IXGBE_SUCCESS)
1615                 return status;
1616
1617         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1618         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1619
1620         /* Select forced link speed for internal PHY. */
1621         switch (*speed) {
1622         case IXGBE_LINK_SPEED_10GB_FULL:
1623                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1624                 break;
1625         case IXGBE_LINK_SPEED_1GB_FULL:
1626                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1627                 break;
1628         default:
1629                 /* Other link speeds are not supported by internal KR PHY. */
1630                 return IXGBE_ERR_LINK_SETUP;
1631         }
1632
1633         status = ixgbe_write_iosf_sb_reg_x550(hw,
1634                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1635                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1636         if (status != IXGBE_SUCCESS)
1637                 return status;
1638
1639         /* Disable training protocol FSM. */
1640         status = ixgbe_read_iosf_sb_reg_x550(hw,
1641                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1642                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1643         if (status != IXGBE_SUCCESS)
1644                 return status;
1645         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1646         status = ixgbe_write_iosf_sb_reg_x550(hw,
1647                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1648                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1649         if (status != IXGBE_SUCCESS)
1650                 return status;
1651
1652         /* Disable Flex from training TXFFE. */
1653         status = ixgbe_read_iosf_sb_reg_x550(hw,
1654                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1655                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1656         if (status != IXGBE_SUCCESS)
1657                 return status;
1658         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1659         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1660         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1661         status = ixgbe_write_iosf_sb_reg_x550(hw,
1662                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1663                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1664         if (status != IXGBE_SUCCESS)
1665                 return status;
1666         status = ixgbe_read_iosf_sb_reg_x550(hw,
1667                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1668                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1669         if (status != IXGBE_SUCCESS)
1670                 return status;
1671         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1672         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1673         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1674         status = ixgbe_write_iosf_sb_reg_x550(hw,
1675                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1676                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1677         if (status != IXGBE_SUCCESS)
1678                 return status;
1679
1680         /* Enable override for coefficients. */
1681         status = ixgbe_read_iosf_sb_reg_x550(hw,
1682                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1683                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1684         if (status != IXGBE_SUCCESS)
1685                 return status;
1686         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1687         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1688         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1689         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1690         status = ixgbe_write_iosf_sb_reg_x550(hw,
1691                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1692                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1693         if (status != IXGBE_SUCCESS)
1694                 return status;
1695
1696         /* Toggle port SW reset by AN reset. */
1697         status = ixgbe_read_iosf_sb_reg_x550(hw,
1698                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1699                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1700         if (status != IXGBE_SUCCESS)
1701                 return status;
1702         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1703         status = ixgbe_write_iosf_sb_reg_x550(hw,
1704                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1705                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1706
1707         return status;
1708 }
1709
1710 /**
1711  *  ixgbe_setup_mac_link_sfp_x550em - Configure the CS4227 & KR PHY for SFP
1712  *  @hw: pointer to hardware structure
1713  *
1714  *  Configure the external CS4227 PHY and the integrated KR PHY for SFP support.
1715  **/
1716 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1717                                     ixgbe_link_speed speed,
1718                                     bool autoneg_wait_to_complete)
1719 {
1720         s32 ret_val;
1721         u16 reg_slice, reg_val;
1722         bool setup_linear = false;
1723         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1724
1725         /* Check if SFP module is supported and linear */
1726         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1727
1728         /* If no SFP module present, then return success. Return success since
1729          * there is no reason to configure CS4227 and SFP not present error is
1730          * not excepted in the setup MAC link flow.
1731          */
1732         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1733                 return IXGBE_SUCCESS;
1734
1735         if (ret_val != IXGBE_SUCCESS)
1736                 return ret_val;
1737
1738         /* Configure CS4227 for connection rate. */
1739         reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1740         reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1741         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1742                                            reg_val);
1743
1744         /* Configure CS4227 for connection type. */
1745         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1746         if (setup_linear)
1747                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1748         else
1749                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1750         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1751                                            reg_val);
1752
1753         reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1754         reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1755         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1756                                            reg_val);
1757
1758         /* Configure CS4227 for connection type. */
1759         reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1760         if (setup_linear)
1761                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1762         else
1763                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1764         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1765                                            reg_val);
1766
1767         /* Configure the internal PHY. */
1768         ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1769
1770         return ret_val;
1771 }
1772
1773 /**
1774  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1775  * @hw: point to hardware structure
1776  *
1777  * Configures the link between the integrated KR PHY and the external X557 PHY
1778  * The driver will call this function when it gets a link status change
1779  * interrupt from the X557 PHY. This function configures the link speed
1780  * between the PHYs to match the link speed of the BASE-T link.
1781  *
1782  * A return of a non-zero value indicates an error, and the base driver should
1783  * not report link up.
1784  */
1785 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1786 {
1787         u32 status;
1788         u16 autoneg_status, speed;
1789         ixgbe_link_speed force_speed;
1790
1791         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1792                 return IXGBE_ERR_CONFIG;
1793
1794         /* read this twice back to back to indicate current status */
1795         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1796                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1797                                       &autoneg_status);
1798         if (status != IXGBE_SUCCESS)
1799                 return status;
1800
1801         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1802                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1803                                       &autoneg_status);
1804         if (status != IXGBE_SUCCESS)
1805                 return status;
1806
1807         /* If link is not up, then there is no setup necessary so return  */
1808         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1809                 return IXGBE_SUCCESS;
1810
1811         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1812                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1813                                       &speed);
1814
1815         /* clear everything but the speed and duplex bits */
1816         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1817
1818         switch (speed) {
1819         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1820                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1821                 break;
1822         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1823                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1824                 break;
1825         default:
1826                 /* Internal PHY does not support anything else */
1827                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1828         }
1829
1830         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1831 }
1832
1833 /**
1834  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1835  *  @hw: pointer to hardware structure
1836  *
1837  *  Configures the integrated KR PHY to use internal loopback mode.
1838  **/
1839 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1840 {
1841         s32 status;
1842         u32 reg_val;
1843
1844         /* Disable AN and force speed to 10G Serial. */
1845         status = ixgbe_read_iosf_sb_reg_x550(hw,
1846                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1847                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1848         if (status != IXGBE_SUCCESS)
1849                 return status;
1850         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1851         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1852         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1853         status = ixgbe_write_iosf_sb_reg_x550(hw,
1854                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1855                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1856         if (status != IXGBE_SUCCESS)
1857                 return status;
1858
1859         /* Set near-end loopback clocks. */
1860         status = ixgbe_read_iosf_sb_reg_x550(hw,
1861                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1862                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1863         if (status != IXGBE_SUCCESS)
1864                 return status;
1865         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1866         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1867         status = ixgbe_write_iosf_sb_reg_x550(hw,
1868                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1869                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1870         if (status != IXGBE_SUCCESS)
1871                 return status;
1872
1873         /* Set loopback enable. */
1874         status = ixgbe_read_iosf_sb_reg_x550(hw,
1875                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1876                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1877         if (status != IXGBE_SUCCESS)
1878                 return status;
1879         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1880         status = ixgbe_write_iosf_sb_reg_x550(hw,
1881                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1882                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1883         if (status != IXGBE_SUCCESS)
1884                 return status;
1885
1886         /* Training bypass. */
1887         status = ixgbe_read_iosf_sb_reg_x550(hw,
1888                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1889                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1890         if (status != IXGBE_SUCCESS)
1891                 return status;
1892         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1893         status = ixgbe_write_iosf_sb_reg_x550(hw,
1894                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1895                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1896
1897         return status;
1898 }
1899
1900 /**
1901  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1902  *  assuming that the semaphore is already obtained.
1903  *  @hw: pointer to hardware structure
1904  *  @offset: offset of  word in the EEPROM to read
1905  *  @data: word read from the EEPROM
1906  *
1907  *  Reads a 16 bit word from the EEPROM using the hostif.
1908  **/
1909 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1910                                    u16 *data)
1911 {
1912         s32 status;
1913         struct ixgbe_hic_read_shadow_ram buffer;
1914
1915         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1916         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1917         buffer.hdr.req.buf_lenh = 0;
1918         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1919         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1920
1921         /* convert offset from words to bytes */
1922         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1923         /* one word */
1924         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1925
1926         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1927                                               sizeof(buffer),
1928                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1929
1930         if (status)
1931                 return status;
1932
1933         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1934                                           FW_NVM_DATA_OFFSET);
1935
1936         return 0;
1937 }
1938
1939 /**
1940  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1941  *  @hw: pointer to hardware structure
1942  *  @offset: offset of  word in the EEPROM to read
1943  *  @data: word read from the EEPROM
1944  *
1945  *  Reads a 16 bit word from the EEPROM using the hostif.
1946  **/
1947 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1948                               u16 *data)
1949 {
1950         s32 status = IXGBE_SUCCESS;
1951
1952         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1953
1954         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1955             IXGBE_SUCCESS) {
1956                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1957                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1958         } else {
1959                 status = IXGBE_ERR_SWFW_SYNC;
1960         }
1961
1962         return status;
1963 }
1964
1965 /**
1966  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1967  *  @hw: pointer to hardware structure
1968  *  @offset: offset of  word in the EEPROM to read
1969  *  @words: number of words
1970  *  @data: word(s) read from the EEPROM
1971  *
1972  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
1973  **/
1974 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1975                                      u16 offset, u16 words, u16 *data)
1976 {
1977         struct ixgbe_hic_read_shadow_ram buffer;
1978         u32 current_word = 0;
1979         u16 words_to_read;
1980         s32 status;
1981         u32 i;
1982
1983         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1984
1985         /* Take semaphore for the entire operation. */
1986         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1987         if (status) {
1988                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1989                 return status;
1990         }
1991         while (words) {
1992                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1993                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1994                 else
1995                         words_to_read = words;
1996
1997                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1998                 buffer.hdr.req.buf_lenh = 0;
1999                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2000                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2001
2002                 /* convert offset from words to bytes */
2003                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2004                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2005
2006                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2007                                                       sizeof(buffer),
2008                                                       IXGBE_HI_COMMAND_TIMEOUT,
2009                                                       false);
2010
2011                 if (status) {
2012                         DEBUGOUT("Host interface command failed\n");
2013                         goto out;
2014                 }
2015
2016                 for (i = 0; i < words_to_read; i++) {
2017                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2018                                   2 * i;
2019                         u32 value = IXGBE_READ_REG(hw, reg);
2020
2021                         data[current_word] = (u16)(value & 0xffff);
2022                         current_word++;
2023                         i++;
2024                         if (i < words_to_read) {
2025                                 value >>= 16;
2026                                 data[current_word] = (u16)(value & 0xffff);
2027                                 current_word++;
2028                         }
2029                 }
2030                 words -= words_to_read;
2031         }
2032
2033 out:
2034         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2035         return status;
2036 }
2037
2038 /**
2039  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2040  *  @hw: pointer to hardware structure
2041  *  @offset: offset of  word in the EEPROM to write
2042  *  @data: word write to the EEPROM
2043  *
2044  *  Write a 16 bit word to the EEPROM using the hostif.
2045  **/
2046 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2047                                     u16 data)
2048 {
2049         s32 status;
2050         struct ixgbe_hic_write_shadow_ram buffer;
2051
2052         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2053
2054         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2055         buffer.hdr.req.buf_lenh = 0;
2056         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2057         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2058
2059          /* one word */
2060         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2061         buffer.data = data;
2062         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2063
2064         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2065                                               sizeof(buffer),
2066                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2067
2068         return status;
2069 }
2070
2071 /**
2072  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2073  *  @hw: pointer to hardware structure
2074  *  @offset: offset of  word in the EEPROM to write
2075  *  @data: word write to the EEPROM
2076  *
2077  *  Write a 16 bit word to the EEPROM using the hostif.
2078  **/
2079 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2080                                u16 data)
2081 {
2082         s32 status = IXGBE_SUCCESS;
2083
2084         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2085
2086         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2087             IXGBE_SUCCESS) {
2088                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2089                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2090         } else {
2091                 DEBUGOUT("write ee hostif failed to get semaphore");
2092                 status = IXGBE_ERR_SWFW_SYNC;
2093         }
2094
2095         return status;
2096 }
2097
2098 /**
2099  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2100  *  @hw: pointer to hardware structure
2101  *  @offset: offset of  word in the EEPROM to write
2102  *  @words: number of words
2103  *  @data: word(s) write to the EEPROM
2104  *
2105  *  Write a 16 bit word(s) to the EEPROM using the hostif.
2106  **/
2107 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2108                                       u16 offset, u16 words, u16 *data)
2109 {
2110         s32 status = IXGBE_SUCCESS;
2111         u32 i = 0;
2112
2113         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2114
2115         /* Take semaphore for the entire operation. */
2116         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2117         if (status != IXGBE_SUCCESS) {
2118                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2119                 goto out;
2120         }
2121
2122         for (i = 0; i < words; i++) {
2123                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2124                                                          data[i]);
2125
2126                 if (status != IXGBE_SUCCESS) {
2127                         DEBUGOUT("Eeprom buffered write failed\n");
2128                         break;
2129                 }
2130         }
2131
2132         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2133 out:
2134
2135         return status;
2136 }
2137
2138 /**
2139  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2140  * @hw: pointer to hardware structure
2141  * @ptr: pointer offset in eeprom
2142  * @size: size of section pointed by ptr, if 0 first word will be used as size
2143  * @csum: address of checksum to update
2144  *
2145  * Returns error status for any failure
2146  */
2147 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2148                                    u16 size, u16 *csum, u16 *buffer,
2149                                    u32 buffer_size)
2150 {
2151         u16 buf[256];
2152         s32 status;
2153         u16 length, bufsz, i, start;
2154         u16 *local_buffer;
2155
2156         bufsz = sizeof(buf) / sizeof(buf[0]);
2157
2158         /* Read a chunk at the pointer location */
2159         if (!buffer) {
2160                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2161                 if (status) {
2162                         DEBUGOUT("Failed to read EEPROM image\n");
2163                         return status;
2164                 }
2165                 local_buffer = buf;
2166         } else {
2167                 if (buffer_size < ptr)
2168                         return  IXGBE_ERR_PARAM;
2169                 local_buffer = &buffer[ptr];
2170         }
2171
2172         if (size) {
2173                 start = 0;
2174                 length = size;
2175         } else {
2176                 start = 1;
2177                 length = local_buffer[0];
2178
2179                 /* Skip pointer section if length is invalid. */
2180                 if (length == 0xFFFF || length == 0 ||
2181                     (ptr + length) >= hw->eeprom.word_size)
2182                         return IXGBE_SUCCESS;
2183         }
2184
2185         if (buffer && ((u32)start + (u32)length > buffer_size))
2186                 return IXGBE_ERR_PARAM;
2187
2188         for (i = start; length; i++, length--) {
2189                 if (i == bufsz && !buffer) {
2190                         ptr += bufsz;
2191                         i = 0;
2192                         if (length < bufsz)
2193                                 bufsz = length;
2194
2195                         /* Read a chunk at the pointer location */
2196                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2197                                                                   bufsz, buf);
2198                         if (status) {
2199                                 DEBUGOUT("Failed to read EEPROM image\n");
2200                                 return status;
2201                         }
2202                 }
2203                 *csum += local_buffer[i];
2204         }
2205         return IXGBE_SUCCESS;
2206 }
2207
2208 /**
2209  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2210  *  @hw: pointer to hardware structure
2211  *  @buffer: pointer to buffer containing calculated checksum
2212  *  @buffer_size: size of buffer
2213  *
2214  *  Returns a negative error code on error, or the 16-bit checksum
2215  **/
2216 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2217 {
2218         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2219         u16 *local_buffer;
2220         s32 status;
2221         u16 checksum = 0;
2222         u16 pointer, i, size;
2223
2224         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2225
2226         hw->eeprom.ops.init_params(hw);
2227
2228         if (!buffer) {
2229                 /* Read pointer area */
2230                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2231                                                      IXGBE_EEPROM_LAST_WORD + 1,
2232                                                      eeprom_ptrs);
2233                 if (status) {
2234                         DEBUGOUT("Failed to read EEPROM image\n");
2235                         return status;
2236                 }
2237                 local_buffer = eeprom_ptrs;
2238         } else {
2239                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2240                         return IXGBE_ERR_PARAM;
2241                 local_buffer = buffer;
2242         }
2243
2244         /*
2245          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2246          * checksum word itself
2247          */
2248         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2249                 if (i != IXGBE_EEPROM_CHECKSUM)
2250                         checksum += local_buffer[i];
2251
2252         /*
2253          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2254          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2255          */
2256         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2257                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2258                         continue;
2259
2260                 pointer = local_buffer[i];
2261
2262                 /* Skip pointer section if the pointer is invalid. */
2263                 if (pointer == 0xFFFF || pointer == 0 ||
2264                     pointer >= hw->eeprom.word_size)
2265                         continue;
2266
2267                 switch (i) {
2268                 case IXGBE_PCIE_GENERAL_PTR:
2269                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2270                         break;
2271                 case IXGBE_PCIE_CONFIG0_PTR:
2272                 case IXGBE_PCIE_CONFIG1_PTR:
2273                         size = IXGBE_PCIE_CONFIG_SIZE;
2274                         break;
2275                 default:
2276                         size = 0;
2277                         break;
2278                 }
2279
2280                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2281                                                 buffer, buffer_size);
2282                 if (status)
2283                         return status;
2284         }
2285
2286         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2287
2288         return (s32)checksum;
2289 }
2290
2291 /**
2292  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2293  *  @hw: pointer to hardware structure
2294  *
2295  *  Returns a negative error code on error, or the 16-bit checksum
2296  **/
2297 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2298 {
2299         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2300 }
2301
2302 /**
2303  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2304  *  @hw: pointer to hardware structure
2305  *  @checksum_val: calculated checksum
2306  *
2307  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2308  *  caller does not need checksum_val, the value can be NULL.
2309  **/
2310 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2311 {
2312         s32 status;
2313         u16 checksum;
2314         u16 read_checksum = 0;
2315
2316         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2317
2318         /* Read the first word from the EEPROM. If this times out or fails, do
2319          * not continue or we could be in for a very long wait while every
2320          * EEPROM read fails
2321          */
2322         status = hw->eeprom.ops.read(hw, 0, &checksum);
2323         if (status) {
2324                 DEBUGOUT("EEPROM read failed\n");
2325                 return status;
2326         }
2327
2328         status = hw->eeprom.ops.calc_checksum(hw);
2329         if (status < 0)
2330                 return status;
2331
2332         checksum = (u16)(status & 0xffff);
2333
2334         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2335                                            &read_checksum);
2336         if (status)
2337                 return status;
2338
2339         /* Verify read checksum from EEPROM is the same as
2340          * calculated checksum
2341          */
2342         if (read_checksum != checksum) {
2343                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2344                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2345                              "Invalid EEPROM checksum");
2346         }
2347
2348         /* If the user cares, return the calculated checksum */
2349         if (checksum_val)
2350                 *checksum_val = checksum;
2351
2352         return status;
2353 }
2354
2355 /**
2356  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2357  * @hw: pointer to hardware structure
2358  *
2359  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2360  * checksum and updates the EEPROM and instructs the hardware to update
2361  * the flash.
2362  **/
2363 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2364 {
2365         s32 status;
2366         u16 checksum = 0;
2367
2368         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2369
2370         /* Read the first word from the EEPROM. If this times out or fails, do
2371          * not continue or we could be in for a very long wait while every
2372          * EEPROM read fails
2373          */
2374         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2375         if (status) {
2376                 DEBUGOUT("EEPROM read failed\n");
2377                 return status;
2378         }
2379
2380         status = ixgbe_calc_eeprom_checksum_X550(hw);
2381         if (status < 0)
2382                 return status;
2383
2384         checksum = (u16)(status & 0xffff);
2385
2386         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2387                                             checksum);
2388         if (status)
2389                 return status;
2390
2391         status = ixgbe_update_flash_X550(hw);
2392
2393         return status;
2394 }
2395
2396 /**
2397  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2398  *  @hw: pointer to hardware structure
2399  *
2400  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2401  **/
2402 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2403 {
2404         s32 status = IXGBE_SUCCESS;
2405         union ixgbe_hic_hdr2 buffer;
2406
2407         DEBUGFUNC("ixgbe_update_flash_X550");
2408
2409         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2410         buffer.req.buf_lenh = 0;
2411         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2412         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2413
2414         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2415                                               sizeof(buffer),
2416                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2417
2418         return status;
2419 }
2420
2421 /**
2422  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2423  *  @hw: pointer to hardware structure
2424  *
2425  *  Determines physical layer capabilities of the current configuration.
2426  **/
2427 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2428 {
2429         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2430         u16 ext_ability = 0;
2431
2432         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2433
2434         hw->phy.ops.identify(hw);
2435
2436         switch (hw->phy.type) {
2437         case ixgbe_phy_x550em_kr:
2438                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2439                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2440                 break;
2441         case ixgbe_phy_x550em_kx4:
2442                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2443                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2444                 break;
2445         case ixgbe_phy_x550em_ext_t:
2446                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2447                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2448                                      &ext_ability);
2449                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2450                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2451                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2452                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2453                 break;
2454         default:
2455                 break;
2456         }
2457
2458         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2459                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2460
2461         return physical_layer;
2462 }
2463
2464 /**
2465  * ixgbe_get_bus_info_x550em - Set PCI bus info
2466  * @hw: pointer to hardware structure
2467  *
2468  * Sets bus link width and speed to unknown because X550em is
2469  * not a PCI device.
2470  **/
2471 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2472 {
2473
2474         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2475
2476         hw->bus.width = ixgbe_bus_width_unknown;
2477         hw->bus.speed = ixgbe_bus_speed_unknown;
2478
2479         hw->mac.ops.set_lan_id(hw);
2480
2481         return IXGBE_SUCCESS;
2482 }
2483
2484 /**
2485  * ixgbe_disable_rx_x550 - Disable RX unit
2486  *
2487  * Enables the Rx DMA unit for x550
2488  **/
2489 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2490 {
2491         u32 rxctrl, pfdtxgswc;
2492         s32 status;
2493         struct ixgbe_hic_disable_rxen fw_cmd;
2494
2495         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2496
2497         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2498         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2499                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2500                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2501                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2502                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2503                         hw->mac.set_lben = true;
2504                 } else {
2505                         hw->mac.set_lben = false;
2506                 }
2507
2508                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2509                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2510                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2511                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2512
2513                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2514                                         sizeof(struct ixgbe_hic_disable_rxen),
2515                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2516
2517                 /* If we fail - disable RX using register write */
2518                 if (status) {
2519                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2520                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2521                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2522                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2523                         }
2524                 }
2525         }
2526 }
2527
2528 /**
2529  * ixgbe_enter_lplu_x550em - Transition to low power states
2530  *  @hw: pointer to hardware structure
2531  *
2532  * Configures Low Power Link Up on transition to low power states
2533  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2534  * X557 PHY immediately prior to entering LPLU.
2535  **/
2536 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2537 {
2538         u16 autoneg_status, an_10g_cntl_reg, autoneg_reg, speed;
2539         s32 status;
2540         ixgbe_link_speed lcd_speed;
2541         u32 save_autoneg;
2542
2543         /* If blocked by MNG FW, then don't restart AN */
2544         if (ixgbe_check_reset_blocked(hw))
2545                 return IXGBE_SUCCESS;
2546
2547         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2548                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2549                                       &autoneg_status);
2550
2551         if (status != IXGBE_SUCCESS)
2552                 return status;
2553
2554         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2555
2556         if (status != IXGBE_SUCCESS)
2557                 return status;
2558
2559         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2560          * disabled, then force link down by entering low power mode.
2561          */
2562         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS) ||
2563             !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2564             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2565                 return ixgbe_set_copper_phy_power(hw, FALSE);
2566
2567         /* Determine LCD */
2568         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2569
2570         if (status != IXGBE_SUCCESS)
2571                 return status;
2572
2573         /* If no valid LCD link speed, then force link down and exit. */
2574         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2575                 return ixgbe_set_copper_phy_power(hw, FALSE);
2576
2577         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2578                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2579                                       &speed);
2580
2581         if (status != IXGBE_SUCCESS)
2582                 return status;
2583
2584         /* clear everything but the speed bits */
2585         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2586
2587         /* If current speed is already LCD, then exit. */
2588         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2589              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2590             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2591              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2592                 return status;
2593
2594         /* Clear AN completed indication */
2595         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2596                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2597                                       &autoneg_status);
2598
2599         if (status != IXGBE_SUCCESS)
2600                 return status;
2601
2602         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2603                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2604                              &an_10g_cntl_reg);
2605
2606         if (status != IXGBE_SUCCESS)
2607                 return status;
2608
2609         status = hw->phy.ops.read_reg(hw,
2610                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2611                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2612                              &autoneg_reg);
2613
2614         if (status != IXGBE_SUCCESS)
2615                 return status;
2616
2617         save_autoneg = hw->phy.autoneg_advertised;
2618
2619         /* Setup link at least common link speed */
2620         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2621
2622         /* restore autoneg from before setting lplu speed */
2623         hw->phy.autoneg_advertised = save_autoneg;
2624
2625         return status;
2626 }
2627
2628 /**
2629  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2630  *  @hw: pointer to hardware structure
2631  *  @lcd_speed: pointer to lowest common link speed
2632  *
2633  * Determine lowest common link speed with link partner.
2634  **/
2635 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2636 {
2637         u16 an_lp_status;
2638         s32 status;
2639         u16 word = hw->eeprom.ctrl_word_3;
2640
2641         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2642
2643         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2644                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2645                                       &an_lp_status);
2646
2647         if (status != IXGBE_SUCCESS)
2648                 return status;
2649
2650         /* If link partner advertised 1G, return 1G */
2651         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2652                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2653                 return status;
2654         }
2655
2656         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2657         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2658             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2659                 return status;
2660
2661         /* Link partner not capable of lower speeds, return 10G */
2662         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2663         return status;
2664 }
2665
2666 /**
2667  *  ixgbe_setup_fc_X550em - Set up flow control
2668  *  @hw: pointer to hardware structure
2669  *
2670  *  Called at init time to set up flow control.
2671  **/
2672 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2673 {
2674         s32 ret_val = IXGBE_SUCCESS;
2675         u32 pause, asm_dir, reg_val;
2676
2677         DEBUGFUNC("ixgbe_setup_fc_X550em");
2678
2679         /* Validate the requested mode */
2680         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2681                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2682                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2683                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2684                 goto out;
2685         }
2686
2687         /* 10gig parts do not have a word in the EEPROM to determine the
2688          * default flow control setting, so we explicitly set it to full.
2689          */
2690         if (hw->fc.requested_mode == ixgbe_fc_default)
2691                 hw->fc.requested_mode = ixgbe_fc_full;
2692
2693         /* Determine PAUSE and ASM_DIR bits. */
2694         switch (hw->fc.requested_mode) {
2695         case ixgbe_fc_none:
2696                 pause = 0;
2697                 asm_dir = 0;
2698                 break;
2699         case ixgbe_fc_tx_pause:
2700                 pause = 0;
2701                 asm_dir = 1;
2702                 break;
2703         case ixgbe_fc_rx_pause:
2704                 /* Rx Flow control is enabled and Tx Flow control is
2705                  * disabled by software override. Since there really
2706                  * isn't a way to advertise that we are capable of RX
2707                  * Pause ONLY, we will advertise that we support both
2708                  * symmetric and asymmetric Rx PAUSE, as such we fall
2709                  * through to the fc_full statement.  Later, we will
2710                  * disable the adapter's ability to send PAUSE frames.
2711                  */
2712         case ixgbe_fc_full:
2713                 pause = 1;
2714                 asm_dir = 1;
2715                 break;
2716         default:
2717                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2718                         "Flow control param set incorrectly\n");
2719                 ret_val = IXGBE_ERR_CONFIG;
2720                 goto out;
2721         }
2722
2723         if (hw->phy.media_type == ixgbe_media_type_backplane) {
2724                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2725                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2726                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2727                 if (ret_val != IXGBE_SUCCESS)
2728                         goto out;
2729                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2730                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2731                 if (pause)
2732                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2733                 if (asm_dir)
2734                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2735                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2736                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2737                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2738
2739                 /* Not all devices fully support AN. */
2740                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR)
2741                         hw->fc.disable_fc_autoneg = true;
2742         }
2743
2744 out:
2745         return ret_val;
2746 }
2747
2748 /**
2749  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2750  * @hw: pointer to hardware structure
2751  * @state: set mux if 1, clear if 0
2752  */
2753 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2754 {
2755         u32 esdp;
2756
2757         if (!hw->bus.lan_id)
2758                 return;
2759         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2760         if (state)
2761                 esdp |= IXGBE_ESDP_SDP1;
2762         else
2763                 esdp &= ~IXGBE_ESDP_SDP1;
2764         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2765         IXGBE_WRITE_FLUSH(hw);
2766 }
2767
2768 /**
2769  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2770  *  @hw: pointer to hardware structure
2771  *  @mask: Mask to specify which semaphore to acquire
2772  *
2773  *  Acquires the SWFW semaphore and sets the I2C MUX
2774  **/
2775 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2776 {
2777         s32 status;
2778
2779         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2780
2781         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2782         if (status)
2783                 return status;
2784
2785         if (mask & IXGBE_GSSR_I2C_MASK)
2786                 ixgbe_set_mux(hw, 1);
2787
2788         return IXGBE_SUCCESS;
2789 }
2790
2791 /**
2792  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2793  *  @hw: pointer to hardware structure
2794  *  @mask: Mask to specify which semaphore to release
2795  *
2796  *  Releases the SWFW semaphore and sets the I2C MUX
2797  **/
2798 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2799 {
2800         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2801
2802         if (mask & IXGBE_GSSR_I2C_MASK)
2803                 ixgbe_set_mux(hw, 0);
2804
2805         ixgbe_release_swfw_sync_X540(hw, mask);
2806 }
2807
2808 /**
2809  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2810  * @hw: pointer to hardware structure
2811  *
2812  * Handle external Base T PHY interrupt. If high temperature
2813  * failure alarm then return error, else if link status change
2814  * then setup internal/external PHY link
2815  *
2816  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2817  * failure alarm, else return PHY access status.
2818  */
2819 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2820 {
2821         bool lsc;
2822         u32 status;
2823
2824         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2825
2826         if (status != IXGBE_SUCCESS)
2827                 return status;
2828
2829         if (lsc)
2830                 return ixgbe_setup_internal_phy_t_x550em(hw);
2831
2832         return IXGBE_SUCCESS;
2833 }
2834
2835 /**
2836  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
2837  * @hw: pointer to hardware structure
2838  * @speed: new link speed
2839  * @autoneg_wait_to_complete: true when waiting for completion is needed
2840  *
2841  * Setup internal/external PHY link speed based on link speed, then set
2842  * external PHY auto advertised link speed.
2843  *
2844  * Returns error status for any failure
2845  **/
2846 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
2847                                   ixgbe_link_speed speed,
2848                                   bool autoneg_wait_to_complete)
2849 {
2850         s32 status;
2851         ixgbe_link_speed force_speed;
2852
2853         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
2854
2855         /* Setup internal/external PHY link speed to iXFI (10G), unless
2856          * only 1G is auto advertised then setup KX link.
2857          */
2858         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2859                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2860         else
2861                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2862
2863         status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
2864
2865         if (status != IXGBE_SUCCESS)
2866                 return status;
2867
2868         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
2869 }
2870
2871 /**
2872  * ixgbe_check_link_t_X550em - Determine link and speed status
2873  * @hw: pointer to hardware structure
2874  * @speed: pointer to link speed
2875  * @link_up: true when link is up
2876  * @link_up_wait_to_complete: bool used to wait for link up or not
2877  *
2878  * Check that both the MAC and X557 external PHY have link.
2879  **/
2880 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
2881                               bool *link_up, bool link_up_wait_to_complete)
2882 {
2883         u32 status;
2884         u16 autoneg_status;
2885
2886         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2887                 return IXGBE_ERR_CONFIG;
2888
2889         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
2890                                               link_up_wait_to_complete);
2891
2892         /* If check link fails or MAC link is not up, then return */
2893         if (status != IXGBE_SUCCESS || !(*link_up))
2894                 return status;
2895
2896         /* MAC link is up, so check external PHY link.
2897          * Read this twice back to back to indicate current status.
2898          */
2899         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2900                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2901                                       &autoneg_status);
2902
2903         if (status != IXGBE_SUCCESS)
2904                 return status;
2905
2906         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2907                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2908                                       &autoneg_status);
2909
2910         if (status != IXGBE_SUCCESS)
2911                 return status;
2912
2913         /* If external PHY link is not up, then indicate link not up */
2914         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
2915                 *link_up = false;
2916
2917         return IXGBE_SUCCESS;
2918 }
2919
2920 /**
2921  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2922  *  @hw: pointer to hardware structure
2923  **/
2924 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2925 {
2926         s32 status;
2927
2928         status = ixgbe_reset_phy_generic(hw);
2929
2930         if (status != IXGBE_SUCCESS)
2931                 return status;
2932
2933         /* Configure Link Status Alarm and Temperature Threshold interrupts */
2934         return ixgbe_enable_lasi_ext_t_x550em(hw);
2935 }