drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
  45
  46 /**
  47  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  48  *  @hw: pointer to hardware structure
  49  *
  50  *  Initialize the function pointers and assign the MAC type for X550.
  51  *  Does not touch the hardware.
  52  **/
  53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  54 {
  55         struct ixgbe_mac_info *mac = &hw->mac;
  56         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  57         s32 ret_val;
  58
  59         DEBUGFUNC("ixgbe_init_ops_X550");
  60
  61         ret_val = ixgbe_init_ops_X540(hw);
  62         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  63         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  64         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  65         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  66         mac->ops.set_source_address_pruning =
  67                         ixgbe_set_source_address_pruning_X550;
  68         mac->ops.set_ethertype_anti_spoofing =
  69                         ixgbe_set_ethertype_anti_spoofing_X550;
  70
  71         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  72         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  73         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  74         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  75         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  76         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  77         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  78         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  79         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  80
  81         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  82         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  83         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  84         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  85         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  86         /* Manageability interface */
  87         mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
  88         switch (hw->device_id) {
  89         case IXGBE_DEV_ID_X550EM_X_10G_T:
  90         case IXGBE_DEV_ID_X550EM_A_10G_T:
  91                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  92                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  93                 break;
  94         default:
  95                 break;
  96         }
  97         return ret_val;
  98 }
  99
 100 /**
 101  * ixgbe_read_cs4227 - Read CS4227 register
 102  * @hw: pointer to hardware structure
 103  * @reg: register number to write
 104  * @value: pointer to receive value read
 105  *
 106  * Returns status code
 107  **/
 108 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 109 {
 110         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 111 }
 112
 113 /**
 114  * ixgbe_write_cs4227 - Write CS4227 register
 115  * @hw: pointer to hardware structure
 116  * @reg: register number to write
 117  * @value: value to write to register
 118  *
 119  * Returns status code
 120  **/
 121 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 122 {
 123         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 124 }
 125
 126 /**
 127  * ixgbe_read_pe - Read register from port expander
 128  * @hw: pointer to hardware structure
 129  * @reg: register number to read
 130  * @value: pointer to receive read value
 131  *
 132  * Returns status code
 133  **/
 134 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 135 {
 136         s32 status;
 137
 138         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 139         if (status != IXGBE_SUCCESS)
 140                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 141                               "port expander access failed with %d\n", status);
 142         return status;
 143 }
 144
 145 /**
 146  * ixgbe_write_pe - Write register to port expander
 147  * @hw: pointer to hardware structure
 148  * @reg: register number to write
 149  * @value: value to write
 150  *
 151  * Returns status code
 152  **/
 153 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 154 {
 155         s32 status;
 156
 157         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 158         if (status != IXGBE_SUCCESS)
 159                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 160                               "port expander access failed with %d\n", status);
 161         return status;
 162 }
 163
 164 /**
 165  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 166  * @hw: pointer to hardware structure
 167  *
 168  * This function assumes that the caller has acquired the proper semaphore.
 169  * Returns error code
 170  **/
 171 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 172 {
 173         s32 status;
 174         u32 retry;
 175         u16 value;
 176         u8 reg;
 177
 178         /* Trigger hard reset. */
 179         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 180         if (status != IXGBE_SUCCESS)
 181                 return status;
 182         reg |= IXGBE_PE_BIT1;
 183         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 184         if (status != IXGBE_SUCCESS)
 185                 return status;
 186
 187         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 188         if (status != IXGBE_SUCCESS)
 189                 return status;
 190         reg &= ~IXGBE_PE_BIT1;
 191         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 192         if (status != IXGBE_SUCCESS)
 193                 return status;
 194
 195         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 196         if (status != IXGBE_SUCCESS)
 197                 return status;
 198         reg &= ~IXGBE_PE_BIT1;
 199         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 200         if (status != IXGBE_SUCCESS)
 201                 return status;
 202
 203         usec_delay(IXGBE_CS4227_RESET_HOLD);
 204
 205         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 206         if (status != IXGBE_SUCCESS)
 207                 return status;
 208         reg |= IXGBE_PE_BIT1;
 209         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 210         if (status != IXGBE_SUCCESS)
 211                 return status;
 212
 213         /* Wait for the reset to complete. */
 214         msec_delay(IXGBE_CS4227_RESET_DELAY);
 215         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 216                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 217                                            &value);
 218                 if (status == IXGBE_SUCCESS &&
 219                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 220                         break;
 221                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 222         }
 223         if (retry == IXGBE_CS4227_RETRIES) {
 224                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 225                         "CS4227 reset did not complete.");
 226                 return IXGBE_ERR_PHY;
 227         }
 228
 229         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 230         if (status != IXGBE_SUCCESS ||
 231             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 232                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 233                         "CS4227 EEPROM did not load successfully.");
 234                 return IXGBE_ERR_PHY;
 235         }
 236
 237         return IXGBE_SUCCESS;
 238 }
 239
 240 /**
 241  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 242  * @hw: pointer to hardware structure
 243  **/
 244 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 245 {
 246         s32 status = IXGBE_SUCCESS;
 247         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 248         u16 value = 0;
 249         u8 retry;
 250
 251         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 252                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 253                 if (status != IXGBE_SUCCESS) {
 254                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 255                                 "semaphore failed with %d", status);
 256                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 257                         continue;
 258                 }
 259
 260                 /* Get status of reset flow. */
 261                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 262
 263                 if (status == IXGBE_SUCCESS &&
 264                     value == IXGBE_CS4227_RESET_COMPLETE)
 265                         goto out;
 266
 267                 if (status != IXGBE_SUCCESS ||
 268                     value != IXGBE_CS4227_RESET_PENDING)
 269                         break;
 270
 271                 /* Reset is pending. Wait and check again. */
 272                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 273                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 274         }
 275
 276         /* If still pending, assume other instance failed. */
 277         if (retry == IXGBE_CS4227_RETRIES) {
 278                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 279                 if (status != IXGBE_SUCCESS) {
 280                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 281                                       "semaphore failed with %d", status);
 282                         return;
 283                 }
 284         }
 285
 286         /* Reset the CS4227. */
 287         status = ixgbe_reset_cs4227(hw);
 288         if (status != IXGBE_SUCCESS) {
 289                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 290                         "CS4227 reset failed: %d", status);
 291                 goto out;
 292         }
 293
 294         /* Reset takes so long, temporarily release semaphore in case the
 295          * other driver instance is waiting for the reset indication.
 296          */
 297         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 298                            IXGBE_CS4227_RESET_PENDING);
 299         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 300         msec_delay(10);
 301         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 302         if (status != IXGBE_SUCCESS) {
 303                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 304                         "semaphore failed with %d", status);
 305                 return;
 306         }
 307
 308         /* Record completion for next time. */
 309         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 310                 IXGBE_CS4227_RESET_COMPLETE);
 311
 312 out:
 313         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 314         msec_delay(hw->eeprom.semaphore_delay);
 315 }
 316
 317 /**
 318  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 319  * @hw: pointer to hardware structure
 320  **/
 321 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 322 {
 323         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 324
 325         if (hw->bus.lan_id) {
 326                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 327                 esdp |= IXGBE_ESDP_SDP1_DIR;
 328         }
 329         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 330         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 331         IXGBE_WRITE_FLUSH(hw);
 332 }
 333
 334 /**
 335  * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
 336  * @hw: pointer to hardware structure
 337  * @reg_addr: 32 bit address of PHY register to read
 338  * @dev_type: always unused
 339  * @phy_data: Pointer to read data from PHY register
 340  */
 341 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 342                                      u32 dev_type, u16 *phy_data)
 343 {
 344         u32 i, data, command;
 345         UNREFERENCED_1PARAMETER(dev_type);
 346
 347         /* Setup and write the read command */
 348         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 349                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 350                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
 351                   IXGBE_MSCA_MDI_COMMAND;
 352
 353         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 354
 355         /* Check every 10 usec to see if the access completed.
 356          * The MDI Command bit will clear when the operation is
 357          * complete
 358          */
 359         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 360                 usec_delay(10);
 361
 362                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 363                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 364                         break;
 365         }
 366
 367         if (command & IXGBE_MSCA_MDI_COMMAND) {
 368                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 369                               "PHY read command did not complete.\n");
 370                 return IXGBE_ERR_PHY;
 371         }
 372
 373         /* Read operation is complete.  Get the data from MSRWD */
 374         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 375         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 376         *phy_data = (u16)data;
 377
 378         return IXGBE_SUCCESS;
 379 }
 380
 381 /**
 382  * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
 383  * @hw: pointer to hardware structure
 384  * @reg_addr: 32 bit PHY register to write
 385  * @dev_type: always unused
 386  * @phy_data: Data to write to the PHY register
 387  */
 388 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 389                                       u32 dev_type, u16 phy_data)
 390 {
 391         u32 i, command;
 392         UNREFERENCED_1PARAMETER(dev_type);
 393
 394         /* Put the data in the MDI single read and write data register*/
 395         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 396
 397         /* Setup and write the write command */
 398         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 399                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 400                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
 401                   IXGBE_MSCA_MDI_COMMAND;
 402
 403         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 404
 405         /* Check every 10 usec to see if the access completed.
 406          * The MDI Command bit will clear when the operation is
 407          * complete
 408          */
 409         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 410                 usec_delay(10);
 411
 412                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 413                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 414                         break;
 415         }
 416
 417         if (command & IXGBE_MSCA_MDI_COMMAND) {
 418                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 419                               "PHY write cmd didn't complete\n");
 420                 return IXGBE_ERR_PHY;
 421         }
 422
 423         return IXGBE_SUCCESS;
 424 }
 425
 426 /**
 427  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 428  * @hw: pointer to hardware structure
 429  *
 430  * Returns error code
 431  */
 432 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 433 {
 434         hw->mac.ops.set_lan_id(hw);
 435
 436         ixgbe_read_mng_if_sel_x550em(hw);
 437
 438         switch (hw->device_id) {
 439         case IXGBE_DEV_ID_X550EM_A_SFP:
 440                 return ixgbe_identify_module_generic(hw);
 441         case IXGBE_DEV_ID_X550EM_X_SFP:
 442                 /* set up for CS4227 usage */
 443                 ixgbe_setup_mux_ctl(hw);
 444                 ixgbe_check_cs4227(hw);
 445                 /* Fallthrough */
 446
 447         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 448                 return ixgbe_identify_module_generic(hw);
 449                 break;
 450         case IXGBE_DEV_ID_X550EM_X_KX4:
 451                 hw->phy.type = ixgbe_phy_x550em_kx4;
 452                 break;
 453         case IXGBE_DEV_ID_X550EM_X_KR:
 454         case IXGBE_DEV_ID_X550EM_A_KR:
 455         case IXGBE_DEV_ID_X550EM_A_KR_L:
 456                 hw->phy.type = ixgbe_phy_x550em_kr;
 457                 break;
 458         case IXGBE_DEV_ID_X550EM_A_10G_T:
 459         case IXGBE_DEV_ID_X550EM_A_1G_T:
 460         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 461         case IXGBE_DEV_ID_X550EM_X_1G_T:
 462         case IXGBE_DEV_ID_X550EM_X_10G_T:
 463                 return ixgbe_identify_phy_generic(hw);
 464         default:
 465                 break;
 466         }
 467         return IXGBE_SUCCESS;
 468 }
 469
 470 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 471                                      u32 device_type, u16 *phy_data)
 472 {
 473         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 474         return IXGBE_NOT_IMPLEMENTED;
 475 }
 476
 477 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 478                                       u32 device_type, u16 phy_data)
 479 {
 480         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 481         return IXGBE_NOT_IMPLEMENTED;
 482 }
 483
 484 /**
 485  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 486  * @hw: pointer to the hardware structure
 487  * @addr: I2C bus address to read from
 488  * @reg: I2C device register to read from
 489  * @val: pointer to location to receive read value
 490  *
 491  * Returns an error code on error.
 492  **/
 493 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 494                                            u16 reg, u16 *val)
 495 {
 496         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 497 }
 498
 499 /**
 500  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 501  * @hw: pointer to the hardware structure
 502  * @addr: I2C bus address to read from
 503  * @reg: I2C device register to read from
 504  * @val: pointer to location to receive read value
 505  *
 506  * Returns an error code on error.
 507  **/
 508 STATIC s32
 509 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 510                                          u16 reg, u16 *val)
 511 {
 512         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 513 }
 514
 515 /**
 516  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 517  * @hw: pointer to the hardware structure
 518  * @addr: I2C bus address to write to
 519  * @reg: I2C device register to write to
 520  * @val: value to write
 521  *
 522  * Returns an error code on error.
 523  **/
 524 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 525                                             u8 addr, u16 reg, u16 val)
 526 {
 527         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 528 }
 529
 530 /**
 531  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 532  * @hw: pointer to the hardware structure
 533  * @addr: I2C bus address to write to
 534  * @reg: I2C device register to write to
 535  * @val: value to write
 536  *
 537  * Returns an error code on error.
 538  **/
 539 STATIC s32
 540 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 541                                           u8 addr, u16 reg, u16 val)
 542 {
 543         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 544 }
 545
 546 /**
 547 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 548 *  @hw: pointer to hardware structure
 549 *
 550 *  Initialize the function pointers and for MAC type X550EM.
 551 *  Does not touch the hardware.
 552 **/
 553 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 554 {
 555         struct ixgbe_mac_info *mac = &hw->mac;
 556         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 557         struct ixgbe_phy_info *phy = &hw->phy;
 558         s32 ret_val;
 559
 560         DEBUGFUNC("ixgbe_init_ops_X550EM");
 561
 562         /* Similar to X550 so start there. */
 563         ret_val = ixgbe_init_ops_X550(hw);
 564
 565         /* Since this function eventually calls
 566          * ixgbe_init_ops_540 by design, we are setting
 567          * the pointers to NULL explicitly here to overwrite
 568          * the values being set in the x540 function.
 569          */
 570         /* Thermal sensor not supported in x550EM */
 571         mac->ops.get_thermal_sensor_data = NULL;
 572         mac->ops.init_thermal_sensor_thresh = NULL;
 573         mac->thermal_sensor_enabled = false;
 574
 575         /* FCOE not supported in x550EM */
 576         mac->ops.get_san_mac_addr = NULL;
 577         mac->ops.set_san_mac_addr = NULL;
 578         mac->ops.get_wwn_prefix = NULL;
 579         mac->ops.get_fcoe_boot_status = NULL;
 580
 581         /* IPsec not supported in x550EM */
 582         mac->ops.disable_sec_rx_path = NULL;
 583         mac->ops.enable_sec_rx_path = NULL;
 584
 585         /* AUTOC register is not present in x550EM. */
 586         mac->ops.prot_autoc_read = NULL;
 587         mac->ops.prot_autoc_write = NULL;
 588
 589         /* X550EM bus type is internal*/
 590         hw->bus.type = ixgbe_bus_type_internal;
 591         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 592
 593
 594         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 595         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 596         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 597         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 598         mac->ops.get_supported_physical_layer =
 599                                     ixgbe_get_supported_physical_layer_X550em;
 600
 601         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 602                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 603         else
 604                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 605
 606         switch (hw->device_id) {
 607         case IXGBE_DEV_ID_X550EM_X_KR:
 608         case IXGBE_DEV_ID_X550EM_A_KR:
 609         case IXGBE_DEV_ID_X550EM_A_KR_L:
 610                 break;
 611         default:
 612                 mac->ops.setup_eee = NULL;
 613         }
 614
 615         /* PHY */
 616         phy->ops.init = ixgbe_init_phy_ops_X550em;
 617         phy->ops.identify = ixgbe_identify_phy_x550em;
 618         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 619                 phy->ops.set_phy_power = NULL;
 620
 621
 622         /* EEPROM */
 623         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 624         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 625         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 626         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 627         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 628         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 629         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 630         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 631
 632         return ret_val;
 633 }
 634
 635 /**
 636 *  ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
 637 *  @hw: pointer to hardware structure
 638 *
 639 *  Initialize the function pointers and for MAC type X550EM_a.
 640 *  Does not touch the hardware.
 641 **/
 642 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
 643 {
 644         struct ixgbe_mac_info *mac = &hw->mac;
 645         s32 ret_val;
 646
 647         DEBUGFUNC("ixgbe_init_ops_X550EM_a");
 648
 649         /* Start with generic X550EM init */
 650         ret_val = ixgbe_init_ops_X550EM(hw);
 651
 652         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
 653             hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
 654                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 655                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 656         } else {
 657                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 658                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 659         }
 660         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 661         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 662
 663         switch (mac->ops.get_media_type(hw)) {
 664         case ixgbe_media_type_fiber:
 665                 mac->ops.setup_fc = NULL;
 666                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
 667                 break;
 668         case ixgbe_media_type_backplane:
 669                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
 670                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
 671                 break;
 672         default:
 673                 break;
 674         }
 675
 676         if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T) ||
 677                 (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)) {
 678                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
 679                 mac->ops.setup_fc = ixgbe_setup_fc_sgmii_x550em_a;
 680         }
 681
 682         return ret_val;
 683 }
 684
 685 /**
 686 *  ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
 687 *  @hw: pointer to hardware structure
 688 *
 689 *  Initialize the function pointers and for MAC type X550EM_x.
 690 *  Does not touch the hardware.
 691 **/
 692 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
 693 {
 694         struct ixgbe_mac_info *mac = &hw->mac;
 695         struct ixgbe_link_info *link = &hw->link;
 696         s32 ret_val;
 697
 698         DEBUGFUNC("ixgbe_init_ops_X550EM_x");
 699
 700         /* Start with generic X550EM init */
 701         ret_val = ixgbe_init_ops_X550EM(hw);
 702
 703         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 704         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 705         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 706         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 707         link->ops.read_link = ixgbe_read_i2c_combined_generic;
 708         link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
 709         link->ops.write_link = ixgbe_write_i2c_combined_generic;
 710         link->ops.write_link_unlocked =
 711                                       ixgbe_write_i2c_combined_generic_unlocked;
 712         link->addr = IXGBE_CS4227;
 713
 714         return ret_val;
 715 }
 716
 717 /**
 718  *  ixgbe_dmac_config_X550
 719  *  @hw: pointer to hardware structure
 720  *
 721  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 722  *  When disabling dmac, dmac enable dmac bit is cleared.
 723  **/
 724 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 725 {
 726         u32 reg, high_pri_tc;
 727
 728         DEBUGFUNC("ixgbe_dmac_config_X550");
 729
 730         /* Disable DMA coalescing before configuring */
 731         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 732         reg &= ~IXGBE_DMACR_DMAC_EN;
 733         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 734
 735         /* Disable DMA Coalescing if the watchdog timer is 0 */
 736         if (!hw->mac.dmac_config.watchdog_timer)
 737                 goto out;
 738
 739         ixgbe_dmac_config_tcs_X550(hw);
 740
 741         /* Configure DMA Coalescing Control Register */
 742         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 743
 744         /* Set the watchdog timer in units of 40.96 usec */
 745         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 746         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 747
 748         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 749         /* If fcoe is enabled, set high priority traffic class */
 750         if (hw->mac.dmac_config.fcoe_en) {
 751                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 752                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 753                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 754         }
 755         reg |= IXGBE_DMACR_EN_MNG_IND;
 756
 757         /* Enable DMA coalescing after configuration */
 758         reg |= IXGBE_DMACR_DMAC_EN;
 759         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 760
 761 out:
 762         return IXGBE_SUCCESS;
 763 }
 764
 765 /**
 766  *  ixgbe_dmac_config_tcs_X550
 767  *  @hw: pointer to hardware structure
 768  *
 769  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 770  *  be cleared before configuring.
 771  **/
 772 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 773 {
 774         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 775
 776         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 777
 778         /* Configure DMA coalescing enabled */
 779         switch (hw->mac.dmac_config.link_speed) {
 780         case IXGBE_LINK_SPEED_10_FULL:
 781         case IXGBE_LINK_SPEED_100_FULL:
 782                 pb_headroom = IXGBE_DMACRXT_100M;
 783                 break;
 784         case IXGBE_LINK_SPEED_1GB_FULL:
 785                 pb_headroom = IXGBE_DMACRXT_1G;
 786                 break;
 787         default:
 788                 pb_headroom = IXGBE_DMACRXT_10G;
 789                 break;
 790         }
 791
 792         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 793                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 794
 795         /* Set the per Rx packet buffer receive threshold */
 796         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 797                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 798                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 799
 800                 if (tc < hw->mac.dmac_config.num_tcs) {
 801                         /* Get Rx PB size */
 802                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 803                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 804                                 IXGBE_RXPBSIZE_SHIFT;
 805
 806                         /* Calculate receive buffer threshold in kilobytes */
 807                         if (rx_pb_size > pb_headroom)
 808                                 rx_pb_size = rx_pb_size - pb_headroom;
 809                         else
 810                                 rx_pb_size = 0;
 811
 812                         /* Minimum of MFS shall be set for DMCTH */
 813                         reg |= (rx_pb_size > maxframe_size_kb) ?
 814                                 rx_pb_size : maxframe_size_kb;
 815                 }
 816                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 817         }
 818         return IXGBE_SUCCESS;
 819 }
 820
 821 /**
 822  *  ixgbe_dmac_update_tcs_X550
 823  *  @hw: pointer to hardware structure
 824  *
 825  *  Disables dmac, updates per TC settings, and then enables dmac.
 826  **/
 827 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 828 {
 829         u32 reg;
 830
 831         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 832
 833         /* Disable DMA coalescing before configuring */
 834         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 835         reg &= ~IXGBE_DMACR_DMAC_EN;
 836         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 837
 838         ixgbe_dmac_config_tcs_X550(hw);
 839
 840         /* Enable DMA coalescing after configuration */
 841         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 842         reg |= IXGBE_DMACR_DMAC_EN;
 843         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 844
 845         return IXGBE_SUCCESS;
 846 }
 847
 848 /**
 849  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 850  *  @hw: pointer to hardware structure
 851  *
 852  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 853  *  ixgbe_hw struct in order to set up EEPROM access.
 854  **/
 855 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 856 {
 857         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 858         u32 eec;
 859         u16 eeprom_size;
 860
 861         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 862
 863         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 864                 eeprom->semaphore_delay = 10;
 865                 eeprom->type = ixgbe_flash;
 866
 867                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 868                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 869                                     IXGBE_EEC_SIZE_SHIFT);
 870                 eeprom->word_size = 1 << (eeprom_size +
 871                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 872
 873                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 874                           eeprom->type, eeprom->word_size);
 875         }
 876
 877         return IXGBE_SUCCESS;
 878 }
 879
 880 /**
 881  * ixgbe_enable_eee_x550 - Enable EEE support
 882  * @hw: pointer to hardware structure
 883  */
 884 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
 885 {
 886         u16 autoneg_eee_reg;
 887         u32 link_reg;
 888         s32 status;
 889
 890         if (hw->mac.type == ixgbe_mac_X550) {
 891                 /* Advertise EEE capability */
 892                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 893                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 894                                      &autoneg_eee_reg);
 895
 896                 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 897                                     IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 898                                     IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 899
 900                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 901                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 902                                       autoneg_eee_reg);
 903                 return IXGBE_SUCCESS;
 904         }
 905
 906         switch (hw->device_id) {
 907         case IXGBE_DEV_ID_X550EM_X_KR:
 908         case IXGBE_DEV_ID_X550EM_A_KR:
 909         case IXGBE_DEV_ID_X550EM_A_KR_L:
 910                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 911                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 912                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 913                 if (status != IXGBE_SUCCESS)
 914                         return status;
 915
 916                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 917                             IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 918
 919                 /* Don't advertise FEC capability when EEE enabled. */
 920                 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 921
 922                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 923                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 924                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 925                 if (status != IXGBE_SUCCESS)
 926                         return status;
 927                 break;
 928         default:
 929                 break;
 930         }
 931
 932         return IXGBE_SUCCESS;
 933 }
 934
 935 /**
 936  * ixgbe_disable_eee_x550 - Disable EEE support
 937  * @hw: pointer to hardware structure
 938  */
 939 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
 940 {
 941         u16 autoneg_eee_reg;
 942         u32 link_reg;
 943         s32 status;
 944
 945         if (hw->mac.type == ixgbe_mac_X550) {
 946                 /* Disable advertised EEE capability */
 947                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 948                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 949                                      &autoneg_eee_reg);
 950
 951                 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 952                                      IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 953                                      IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 954
 955                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 956                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 957                                       autoneg_eee_reg);
 958                 return IXGBE_SUCCESS;
 959         }
 960
 961         switch (hw->device_id) {
 962         case IXGBE_DEV_ID_X550EM_X_KR:
 963         case IXGBE_DEV_ID_X550EM_A_KR:
 964         case IXGBE_DEV_ID_X550EM_A_KR_L:
 965                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 966                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 967                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 968                 if (status != IXGBE_SUCCESS)
 969                         return status;
 970
 971                 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 972                               IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 973
 974                 /* Advertise FEC capability when EEE is disabled. */
 975                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 976
 977                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 978                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 979                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 980                 if (status != IXGBE_SUCCESS)
 981                         return status;
 982                 break;
 983         default:
 984                 break;
 985         }
 986
 987         return IXGBE_SUCCESS;
 988 }
 989
 990 /**
 991  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 992  *  @hw: pointer to the HW structure
 993  *  @enable_eee: boolean flag to enable EEE
 994  *
 995  *  Enable/disable EEE based on enable_eee flag.
 996  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 997  *  are modified.
 998  *
 999  **/
1000 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
1001 {
1002         s32 status;
1003         u32 eeer;
1004
1005         DEBUGFUNC("ixgbe_setup_eee_X550");
1006
1007         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
1008         /* Enable or disable EEE per flag */
1009         if (enable_eee) {
1010                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1011
1012                 /* Not supported on first revision of X550EM_x. */
1013                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1014                     !(IXGBE_FUSES0_REV_MASK &
1015                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1016                         return IXGBE_SUCCESS;
1017
1018                 status = ixgbe_enable_eee_x550(hw);
1019                 if (status)
1020                         return status;
1021         } else {
1022                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1023
1024                 status = ixgbe_disable_eee_x550(hw);
1025                 if (status)
1026                         return status;
1027         }
1028         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1029
1030         return IXGBE_SUCCESS;
1031 }
1032
1033 /**
1034  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1035  * @hw: pointer to hardware structure
1036  * @enable: enable or disable source address pruning
1037  * @pool: Rx pool to set source address pruning for
1038  **/
1039 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1040                                            unsigned int pool)
1041 {
1042         u64 pfflp;
1043
1044         /* max rx pool is 63 */
1045         if (pool > 63)
1046                 return;
1047
1048         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1049         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1050
1051         if (enable)
1052                 pfflp |= (1ULL << pool);
1053         else
1054                 pfflp &= ~(1ULL << pool);
1055
1056         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1057         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1058 }
1059
1060 /**
1061  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1062  *  @hw: pointer to hardware structure
1063  *  @enable: enable or disable switch for Ethertype anti-spoofing
1064  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1065  *
1066  **/
1067 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1068                 bool enable, int vf)
1069 {
1070         int vf_target_reg = vf >> 3;
1071         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1072         u32 pfvfspoof;
1073
1074         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1075
1076         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1077         if (enable)
1078                 pfvfspoof |= (1 << vf_target_shift);
1079         else
1080                 pfvfspoof &= ~(1 << vf_target_shift);
1081
1082         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1083 }
1084
1085 /**
1086  * ixgbe_iosf_wait - Wait for IOSF command completion
1087  * @hw: pointer to hardware structure
1088  * @ctrl: pointer to location to receive final IOSF control value
1089  *
1090  * Returns failing status on timeout
1091  *
1092  * Note: ctrl can be NULL if the IOSF control register value is not needed
1093  **/
1094 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1095 {
1096         u32 i, command = 0;
1097
1098         /* Check every 10 usec to see if the address cycle completed.
1099          * The SB IOSF BUSY bit will clear when the operation is
1100          * complete
1101          */
1102         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1103                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1104                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1105                         break;
1106                 usec_delay(10);
1107         }
1108         if (ctrl)
1109                 *ctrl = command;
1110         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1111                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1112                 return IXGBE_ERR_PHY;
1113         }
1114
1115         return IXGBE_SUCCESS;
1116 }
1117
1118 /**
1119  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1120  *  of the IOSF device
1121  *  @hw: pointer to hardware structure
1122  *  @reg_addr: 32 bit PHY register to write
1123  *  @device_type: 3 bit device type
1124  *  @data: Data to write to the register
1125  **/
1126 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1127                             u32 device_type, u32 data)
1128 {
1129         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1130         u32 command, error;
1131         s32 ret;
1132
1133         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1134         if (ret != IXGBE_SUCCESS)
1135                 return ret;
1136
1137         ret = ixgbe_iosf_wait(hw, NULL);
1138         if (ret != IXGBE_SUCCESS)
1139                 goto out;
1140
1141         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1142                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1143
1144         /* Write IOSF control register */
1145         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1146
1147         /* Write IOSF data register */
1148         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1149
1150         ret = ixgbe_iosf_wait(hw, &command);
1151
1152         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1153                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1154                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1155                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1156                               "Failed to write, error %x\n", error);
1157                 ret = IXGBE_ERR_PHY;
1158         }
1159
1160 out:
1161         ixgbe_release_swfw_semaphore(hw, gssr);
1162         return ret;
1163 }
1164
1165 /**
1166  *  ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1167  *  @hw: pointer to hardware structure
1168  *  @reg_addr: 32 bit PHY register to write
1169  *  @device_type: 3 bit device type
1170  *  @data: Pointer to read data from the register
1171  **/
1172 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1173                            u32 device_type, u32 *data)
1174 {
1175         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1176         u32 command, error;
1177         s32 ret;
1178
1179         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1180         if (ret != IXGBE_SUCCESS)
1181                 return ret;
1182
1183         ret = ixgbe_iosf_wait(hw, NULL);
1184         if (ret != IXGBE_SUCCESS)
1185                 goto out;
1186
1187         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1188                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1189
1190         /* Write IOSF control register */
1191         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1192
1193         ret = ixgbe_iosf_wait(hw, &command);
1194
1195         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1196                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1197                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1198                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1199                                 "Failed to read, error %x\n", error);
1200                 ret = IXGBE_ERR_PHY;
1201         }
1202
1203         if (ret == IXGBE_SUCCESS)
1204                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1205
1206 out:
1207         ixgbe_release_swfw_semaphore(hw, gssr);
1208         return ret;
1209 }
1210
1211 /**
1212  * ixgbe_get_phy_token - Get the token for shared phy access
1213  * @hw: Pointer to hardware structure
1214  */
1215
1216 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1217 {
1218         struct ixgbe_hic_phy_token_req token_cmd;
1219         s32 status;
1220
1221         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1222         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1223         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1224         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1225         token_cmd.port_number = hw->bus.lan_id;
1226         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1227         token_cmd.pad = 0;
1228         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1229                                               sizeof(token_cmd),
1230                                               IXGBE_HI_COMMAND_TIMEOUT,
1231                                               true);
1232         if (status)
1233                 return status;
1234         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1235                 return IXGBE_SUCCESS;
1236         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1237                 return IXGBE_ERR_FW_RESP_INVALID;
1238
1239         return IXGBE_ERR_TOKEN_RETRY;
1240 }
1241
1242 /**
1243  * ixgbe_put_phy_token - Put the token for shared phy access
1244  * @hw: Pointer to hardware structure
1245  */
1246
1247 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1248 {
1249         struct ixgbe_hic_phy_token_req token_cmd;
1250         s32 status;
1251
1252         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1253         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1254         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1255         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1256         token_cmd.port_number = hw->bus.lan_id;
1257         token_cmd.command_type = FW_PHY_TOKEN_REL;
1258         token_cmd.pad = 0;
1259         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1260                                               sizeof(token_cmd),
1261                                               IXGBE_HI_COMMAND_TIMEOUT,
1262                                               true);
1263         if (status)
1264                 return status;
1265         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1266                 return IXGBE_SUCCESS;
1267
1268         DEBUGOUT("Put PHY Token host interface command failed");
1269         return IXGBE_ERR_FW_RESP_INVALID;
1270 }
1271
1272 /**
1273  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1274  *  of the IOSF device
1275  *  @hw: pointer to hardware structure
1276  *  @reg_addr: 32 bit PHY register to write
1277  *  @device_type: 3 bit device type
1278  *  @data: Data to write to the register
1279  **/
1280 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1281                                   u32 device_type, u32 data)
1282 {
1283         struct ixgbe_hic_internal_phy_req write_cmd;
1284         s32 status;
1285         UNREFERENCED_1PARAMETER(device_type);
1286
1287         memset(&write_cmd, 0, sizeof(write_cmd));
1288         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1289         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1290         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1291         write_cmd.port_number = hw->bus.lan_id;
1292         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1293         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1294         write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1295
1296         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1297                                               sizeof(write_cmd),
1298                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1299
1300         return status;
1301 }
1302
1303 /**
1304  *  ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1305  *  @hw: pointer to hardware structure
1306  *  @reg_addr: 32 bit PHY register to write
1307  *  @device_type: 3 bit device type
1308  *  @data: Pointer to read data from the register
1309  **/
1310 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1311                                  u32 device_type, u32 *data)
1312 {
1313         union {
1314                 struct ixgbe_hic_internal_phy_req cmd;
1315                 struct ixgbe_hic_internal_phy_resp rsp;
1316         } hic;
1317         s32 status;
1318         UNREFERENCED_1PARAMETER(device_type);
1319
1320         memset(&hic, 0, sizeof(hic));
1321         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1322         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1323         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1324         hic.cmd.port_number = hw->bus.lan_id;
1325         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1326         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1327
1328         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1329                                               sizeof(hic.cmd),
1330                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1331
1332         /* Extract the register value from the response. */
1333         *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1334
1335         return status;
1336 }
1337
1338 /**
1339  *  ixgbe_disable_mdd_X550
1340  *  @hw: pointer to hardware structure
1341  *
1342  *  Disable malicious driver detection
1343  **/
1344 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1345 {
1346         u32 reg;
1347
1348         DEBUGFUNC("ixgbe_disable_mdd_X550");
1349
1350         /* Disable MDD for TX DMA and interrupt */
1351         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1352         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1353         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1354
1355         /* Disable MDD for RX and interrupt */
1356         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1357         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1358         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1359 }
1360
1361 /**
1362  *  ixgbe_enable_mdd_X550
1363  *  @hw: pointer to hardware structure
1364  *
1365  *  Enable malicious driver detection
1366  **/
1367 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1368 {
1369         u32 reg;
1370
1371         DEBUGFUNC("ixgbe_enable_mdd_X550");
1372
1373         /* Enable MDD for TX DMA and interrupt */
1374         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1375         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1376         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1377
1378         /* Enable MDD for RX and interrupt */
1379         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1380         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1381         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1382 }
1383
1384 /**
1385  *  ixgbe_restore_mdd_vf_X550
1386  *  @hw: pointer to hardware structure
1387  *  @vf: vf index
1388  *
1389  *  Restore VF that was disabled during malicious driver detection event
1390  **/
1391 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1392 {
1393         u32 idx, reg, num_qs, start_q, bitmask;
1394
1395         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1396
1397         /* Map VF to queues */
1398         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1399         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1400         case IXGBE_MRQC_VMDQRT8TCEN:
1401                 num_qs = 8;  /* 16 VFs / pools */
1402                 bitmask = 0x000000FF;
1403                 break;
1404         case IXGBE_MRQC_VMDQRSS32EN:
1405         case IXGBE_MRQC_VMDQRT4TCEN:
1406                 num_qs = 4;  /* 32 VFs / pools */
1407                 bitmask = 0x0000000F;
1408                 break;
1409         default:            /* 64 VFs / pools */
1410                 num_qs = 2;
1411                 bitmask = 0x00000003;
1412                 break;
1413         }
1414         start_q = vf * num_qs;
1415
1416         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1417         idx = start_q / 32;
1418         reg = 0;
1419         reg |= (bitmask << (start_q % 32));
1420         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1421         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1422 }
1423
1424 /**
1425  *  ixgbe_mdd_event_X550
1426  *  @hw: pointer to hardware structure
1427  *  @vf_bitmap: vf bitmap of malicious vfs
1428  *
1429  *  Handle malicious driver detection event.
1430  **/
1431 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1432 {
1433         u32 wqbr;
1434         u32 i, j, reg, q, shift, vf, idx;
1435
1436         DEBUGFUNC("ixgbe_mdd_event_X550");
1437
1438         /* figure out pool size for mapping to vf's */
1439         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1440         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1441         case IXGBE_MRQC_VMDQRT8TCEN:
1442                 shift = 3;  /* 16 VFs / pools */
1443                 break;
1444         case IXGBE_MRQC_VMDQRSS32EN:
1445         case IXGBE_MRQC_VMDQRT4TCEN:
1446                 shift = 2;  /* 32 VFs / pools */
1447                 break;
1448         default:
1449                 shift = 1;  /* 64 VFs / pools */
1450                 break;
1451         }
1452
1453         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1454         for (i = 0; i < 4; i++) {
1455                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1456                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1457
1458                 if (!wqbr)
1459                         continue;
1460
1461                 /* Get malicious queue */
1462                 for (j = 0; j < 32 && wqbr; j++) {
1463
1464                         if (!(wqbr & (1 << j)))
1465                                 continue;
1466
1467                         /* Get queue from bitmask */
1468                         q = j + (i * 32);
1469
1470                         /* Map queue to vf */
1471                         vf = (q >> shift);
1472
1473                         /* Set vf bit in vf_bitmap */
1474                         idx = vf / 32;
1475                         vf_bitmap[idx] |= (1 << (vf % 32));
1476                         wqbr &= ~(1 << j);
1477                 }
1478         }
1479 }
1480
1481 /**
1482  *  ixgbe_get_media_type_X550em - Get media type
1483  *  @hw: pointer to hardware structure
1484  *
1485  *  Returns the media type (fiber, copper, backplane)
1486  */
1487 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1488 {
1489         enum ixgbe_media_type media_type;
1490
1491         DEBUGFUNC("ixgbe_get_media_type_X550em");
1492
1493         /* Detect if there is a copper PHY attached. */
1494         switch (hw->device_id) {
1495         case IXGBE_DEV_ID_X550EM_X_KR:
1496         case IXGBE_DEV_ID_X550EM_X_KX4:
1497         case IXGBE_DEV_ID_X550EM_A_KR:
1498         case IXGBE_DEV_ID_X550EM_A_KR_L:
1499                 media_type = ixgbe_media_type_backplane;
1500                 break;
1501         case IXGBE_DEV_ID_X550EM_X_SFP:
1502         case IXGBE_DEV_ID_X550EM_A_SFP:
1503         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1504         case IXGBE_DEV_ID_X550EM_A_QSFP:
1505         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1506                 media_type = ixgbe_media_type_fiber;
1507                 break;
1508         case IXGBE_DEV_ID_X550EM_X_1G_T:
1509         case IXGBE_DEV_ID_X550EM_X_10G_T:
1510         case IXGBE_DEV_ID_X550EM_A_10G_T:
1511                 media_type = ixgbe_media_type_copper;
1512                 break;
1513         case IXGBE_DEV_ID_X550EM_A_SGMII:
1514         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1515                 media_type = ixgbe_media_type_backplane;
1516                 hw->phy.type = ixgbe_phy_sgmii;
1517                 break;
1518         case IXGBE_DEV_ID_X550EM_A_1G_T:
1519         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1520                 media_type = ixgbe_media_type_copper;
1521                 break;
1522         default:
1523                 media_type = ixgbe_media_type_unknown;
1524                 break;
1525         }
1526         return media_type;
1527 }
1528
1529 /**
1530  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1531  *  @hw: pointer to hardware structure
1532  *  @linear: true if SFP module is linear
1533  */
1534 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1535 {
1536         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1537
1538         switch (hw->phy.sfp_type) {
1539         case ixgbe_sfp_type_not_present:
1540                 return IXGBE_ERR_SFP_NOT_PRESENT;
1541         case ixgbe_sfp_type_da_cu_core0:
1542         case ixgbe_sfp_type_da_cu_core1:
1543                 *linear = true;
1544                 break;
1545         case ixgbe_sfp_type_srlr_core0:
1546         case ixgbe_sfp_type_srlr_core1:
1547         case ixgbe_sfp_type_da_act_lmt_core0:
1548         case ixgbe_sfp_type_da_act_lmt_core1:
1549         case ixgbe_sfp_type_1g_sx_core0:
1550         case ixgbe_sfp_type_1g_sx_core1:
1551         case ixgbe_sfp_type_1g_lx_core0:
1552         case ixgbe_sfp_type_1g_lx_core1:
1553                 *linear = false;
1554                 break;
1555         case ixgbe_sfp_type_unknown:
1556         case ixgbe_sfp_type_1g_cu_core0:
1557         case ixgbe_sfp_type_1g_cu_core1:
1558         default:
1559                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1560         }
1561
1562         return IXGBE_SUCCESS;
1563 }
1564
1565 /**
1566  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1567  *  @hw: pointer to hardware structure
1568  *
1569  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1570  **/
1571 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1572 {
1573         s32 status;
1574         bool linear;
1575
1576         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1577
1578         status = ixgbe_identify_module_generic(hw);
1579
1580         if (status != IXGBE_SUCCESS)
1581                 return status;
1582
1583         /* Check if SFP module is supported */
1584         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1585
1586         return status;
1587 }
1588
1589 /**
1590  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1591  *  @hw: pointer to hardware structure
1592  */
1593 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1594 {
1595         s32 status;
1596         bool linear;
1597
1598         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1599
1600         /* Check if SFP module is supported */
1601         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1602
1603         if (status != IXGBE_SUCCESS)
1604                 return status;
1605
1606         ixgbe_init_mac_link_ops_X550em(hw);
1607         hw->phy.ops.reset = NULL;
1608
1609         return IXGBE_SUCCESS;
1610 }
1611
1612 /**
1613 *  ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1614 *  internal PHY
1615 *  @hw: pointer to hardware structure
1616 **/
1617 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1618 {
1619         s32 status;
1620         u32 link_ctrl;
1621
1622         /* Restart auto-negotiation. */
1623         status = hw->mac.ops.read_iosf_sb_reg(hw,
1624                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1625                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1626
1627         if (status) {
1628                 DEBUGOUT("Auto-negotiation did not complete\n");
1629                 return status;
1630         }
1631
1632         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1633         status = hw->mac.ops.write_iosf_sb_reg(hw,
1634                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1635                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1636
1637         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1638                 u32 flx_mask_st20;
1639
1640                 /* Indicate to FW that AN restart has been asserted */
1641                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1642                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1643                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1644
1645                 if (status) {
1646                         DEBUGOUT("Auto-negotiation did not complete\n");
1647                         return status;
1648                 }
1649
1650                 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1651                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1652                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1653                                 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1654         }
1655
1656         return status;
1657 }
1658
1659 /**
1660  * ixgbe_setup_sgmii - Set up link for sgmii
1661  * @hw: pointer to hardware structure
1662  */
1663 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1664                              bool autoneg_wait)
1665 {
1666         struct ixgbe_mac_info *mac = &hw->mac;
1667         u32 lval, sval, flx_val;
1668         s32 rc;
1669
1670         rc = mac->ops.read_iosf_sb_reg(hw,
1671                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1672                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1673         if (rc)
1674                 return rc;
1675
1676         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1677         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1678         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1679         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1680         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1681         rc = mac->ops.write_iosf_sb_reg(hw,
1682                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1683                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1684         if (rc)
1685                 return rc;
1686
1687         rc = mac->ops.read_iosf_sb_reg(hw,
1688                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1689                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1690         if (rc)
1691                 return rc;
1692
1693         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1694         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1695         rc = mac->ops.write_iosf_sb_reg(hw,
1696                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1697                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1698         if (rc)
1699                 return rc;
1700
1701         rc = mac->ops.read_iosf_sb_reg(hw,
1702                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1703                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1704         if (rc)
1705                 return rc;
1706
1707         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1708         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1709         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1710         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1711         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1712
1713         rc = mac->ops.write_iosf_sb_reg(hw,
1714                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1715                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1716         if (rc)
1717                 return rc;
1718
1719         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1720         if (rc)
1721                 return rc;
1722
1723         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1724 }
1725
1726 /**
1727  * ixgbe_setup_sgmii_m88 - Set up link for sgmii with Marvell PHYs
1728  * @hw: pointer to hardware structure
1729  */
1730 STATIC s32 ixgbe_setup_sgmii_m88(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1731                                  bool autoneg_wait)
1732 {
1733         struct ixgbe_mac_info *mac = &hw->mac;
1734         u32 lval, sval, flx_val;
1735         s32 rc;
1736
1737         rc = mac->ops.read_iosf_sb_reg(hw,
1738                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1739                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1740         if (rc)
1741                 return rc;
1742
1743         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1744         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1745         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1746         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1747         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1748         rc = mac->ops.write_iosf_sb_reg(hw,
1749                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1750                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1751         if (rc)
1752                 return rc;
1753
1754         rc = mac->ops.read_iosf_sb_reg(hw,
1755                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1756                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1757         if (rc)
1758                 return rc;
1759
1760         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1761         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1762         rc = mac->ops.write_iosf_sb_reg(hw,
1763                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1764                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1765         if (rc)
1766                 return rc;
1767
1768         rc = mac->ops.write_iosf_sb_reg(hw,
1769                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1770                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1771         if (rc)
1772                 return rc;
1773
1774         rc = mac->ops.read_iosf_sb_reg(hw,
1775                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1776                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1777         if (rc)
1778                 return rc;
1779
1780         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1781         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1782         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1783         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1784         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1785
1786         rc = mac->ops.write_iosf_sb_reg(hw,
1787                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1788                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1789         if (rc)
1790                 return rc;
1791
1792         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1793
1794         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1795 }
1796
1797 /**
1798  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1799  *  @hw: pointer to hardware structure
1800  */
1801 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1802 {
1803         struct ixgbe_mac_info *mac = &hw->mac;
1804
1805         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1806
1807         switch (hw->mac.ops.get_media_type(hw)) {
1808         case ixgbe_media_type_fiber:
1809                 /* CS4227 does not support autoneg, so disable the laser control
1810                  * functions for SFP+ fiber
1811                  */
1812                 mac->ops.disable_tx_laser = NULL;
1813                 mac->ops.enable_tx_laser = NULL;
1814                 mac->ops.flap_tx_laser = NULL;
1815                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1816                 mac->ops.set_rate_select_speed =
1817                                         ixgbe_set_soft_rate_select_speed;
1818
1819                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1820                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1821                         mac->ops.setup_mac_link =
1822                                                 ixgbe_setup_mac_link_sfp_x550a;
1823                 else
1824                         mac->ops.setup_mac_link =
1825                                                 ixgbe_setup_mac_link_sfp_x550em;
1826                 break;
1827         case ixgbe_media_type_copper:
1828                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1829                         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1830                             hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1831                                 mac->ops.setup_link = ixgbe_setup_sgmii_m88;
1832                         } else {
1833                                 mac->ops.setup_link =
1834                                                   ixgbe_setup_mac_link_t_X550em;
1835                         }
1836                 } else {
1837                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1838                         mac->ops.check_link = ixgbe_check_link_t_X550em;
1839                 }
1840                 break;
1841         case ixgbe_media_type_backplane:
1842                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1843                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1844                         mac->ops.setup_link = ixgbe_setup_sgmii;
1845                 break;
1846         default:
1847                 break;
1848         }
1849 }
1850
1851 /**
1852  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1853  *  @hw: pointer to hardware structure
1854  *  @speed: pointer to link speed
1855  *  @autoneg: true when autoneg or autotry is enabled
1856  */
1857 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1858                                        ixgbe_link_speed *speed,
1859                                        bool *autoneg)
1860 {
1861         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1862
1863
1864         /* SFP */
1865         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1866
1867                 /* CS4227 SFP must not enable auto-negotiation */
1868                 *autoneg = false;
1869
1870                 /* Check if 1G SFP module. */
1871                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1872                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1873                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1874                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1875                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1876                         return IXGBE_SUCCESS;
1877                 }
1878
1879                 /* Link capabilities are based on SFP */
1880                 if (hw->phy.multispeed_fiber)
1881                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1882                                  IXGBE_LINK_SPEED_1GB_FULL;
1883                 else
1884                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1885         } else {
1886                 switch (hw->phy.type) {
1887                 case ixgbe_phy_m88:
1888                         *speed = IXGBE_LINK_SPEED_1GB_FULL |
1889                                  IXGBE_LINK_SPEED_100_FULL |
1890                                  IXGBE_LINK_SPEED_10_FULL;
1891                         break;
1892                 case ixgbe_phy_sgmii:
1893                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1894                         break;
1895                 case ixgbe_phy_x550em_kr:
1896                         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1897                                 /* check different backplane modes */
1898                                 if (hw->phy.nw_mng_if_sel &
1899                                            IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
1900                                         *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
1901                                         break;
1902                                 } else if (hw->device_id ==
1903                                                    IXGBE_DEV_ID_X550EM_A_KR_L) {
1904                                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1905                                         break;
1906                                 }
1907                         }
1908                         /* fall through */
1909                 default:
1910                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1911                                  IXGBE_LINK_SPEED_1GB_FULL;
1912                         break;
1913                 }
1914                 *autoneg = true;
1915         }
1916
1917         return IXGBE_SUCCESS;
1918 }
1919
1920 /**
1921  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1922  * @hw: pointer to hardware structure
1923  * @lsc: pointer to boolean flag which indicates whether external Base T
1924  *       PHY interrupt is lsc
1925  *
1926  * Determime if external Base T PHY interrupt cause is high temperature
1927  * failure alarm or link status change.
1928  *
1929  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1930  * failure alarm, else return PHY access status.
1931  */
1932 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1933 {
1934         u32 status;
1935         u16 reg;
1936
1937         *lsc = false;
1938
1939         /* Vendor alarm triggered */
1940         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1941                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1942                                       &reg);
1943
1944         if (status != IXGBE_SUCCESS ||
1945             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1946                 return status;
1947
1948         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1949         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1950                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1951                                       &reg);
1952
1953         if (status != IXGBE_SUCCESS ||
1954             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1955             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1956                 return status;
1957
1958         /* Global alarm triggered */
1959         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1960                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1961                                       &reg);
1962
1963         if (status != IXGBE_SUCCESS)
1964                 return status;
1965
1966         /* If high temperature failure, then return over temp error and exit */
1967         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1968                 /* power down the PHY in case the PHY FW didn't already */
1969                 ixgbe_set_copper_phy_power(hw, false);
1970                 return IXGBE_ERR_OVERTEMP;
1971         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1972                 /*  device fault alarm triggered */
1973                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1974                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1975                                           &reg);
1976
1977                 if (status != IXGBE_SUCCESS)
1978                         return status;
1979
1980                 /* if device fault was due to high temp alarm handle and exit */
1981                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1982                         /* power down the PHY in case the PHY FW didn't */
1983                         ixgbe_set_copper_phy_power(hw, false);
1984                         return IXGBE_ERR_OVERTEMP;
1985                 }
1986         }
1987
1988         /* Vendor alarm 2 triggered */
1989         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1990                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1991
1992         if (status != IXGBE_SUCCESS ||
1993             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1994                 return status;
1995
1996         /* link connect/disconnect event occurred */
1997         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1998                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1999
2000         if (status != IXGBE_SUCCESS)
2001                 return status;
2002
2003         /* Indicate LSC */
2004         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2005                 *lsc = true;
2006
2007         return IXGBE_SUCCESS;
2008 }
2009
2010 /**
2011  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2012  * @hw: pointer to hardware structure
2013  *
2014  * Enable link status change and temperature failure alarm for the external
2015  * Base T PHY
2016  *
2017  * Returns PHY access status
2018  */
2019 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2020 {
2021         u32 status;
2022         u16 reg;
2023         bool lsc;
2024
2025         /* Clear interrupt flags */
2026         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2027
2028         /* Enable link status change alarm */
2029         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2030                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2031
2032         if (status != IXGBE_SUCCESS)
2033                 return status;
2034
2035         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2036
2037         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2038                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2039
2040         if (status != IXGBE_SUCCESS)
2041                 return status;
2042
2043         /* Enable high temperature failure and global fault alarms */
2044         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2045                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2046                                       &reg);
2047
2048         if (status != IXGBE_SUCCESS)
2049                 return status;
2050
2051         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2052                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2053
2054         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2055                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2056                                        reg);
2057
2058         if (status != IXGBE_SUCCESS)
2059                 return status;
2060
2061         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2062         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2063                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2064                                       &reg);
2065
2066         if (status != IXGBE_SUCCESS)
2067                 return status;
2068
2069         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2070                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2071
2072         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2073                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2074                                        reg);
2075
2076         if (status != IXGBE_SUCCESS)
2077                 return status;
2078
2079         /* Enable chip-wide vendor alarm */
2080         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2081                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2082                                       &reg);
2083
2084         if (status != IXGBE_SUCCESS)
2085                 return status;
2086
2087         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2088
2089         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2090                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2091                                        reg);
2092
2093         return status;
2094 }
2095
2096 /**
2097  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2098  *  @hw: pointer to hardware structure
2099  *  @speed: link speed
2100  *
2101  *  Configures the integrated KR PHY.
2102  **/
2103 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2104                                        ixgbe_link_speed speed)
2105 {
2106         s32 status;
2107         u32 reg_val;
2108
2109         status = hw->mac.ops.read_iosf_sb_reg(hw,
2110                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2111                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2112         if (status)
2113                 return status;
2114
2115         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2116         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2117                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2118
2119         /* Advertise 10G support. */
2120         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2121                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2122
2123         /* Advertise 1G support. */
2124         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2125                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2126
2127         status = hw->mac.ops.write_iosf_sb_reg(hw,
2128                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2129                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2130
2131         if (hw->mac.type == ixgbe_mac_X550EM_a) {
2132                 /* Set lane mode  to KR auto negotiation */
2133                 status = hw->mac.ops.read_iosf_sb_reg(hw,
2134                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2135                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2136
2137                 if (status)
2138                         return status;
2139
2140                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2141                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2142                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2143                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2144                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2145
2146                 status = hw->mac.ops.write_iosf_sb_reg(hw,
2147                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2148                                     IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2149         }
2150
2151         return ixgbe_restart_an_internal_phy_x550em(hw);
2152 }
2153
2154 /**
2155  * ixgbe_setup_m88 - setup m88 PHY
2156  * @hw: pointer to hardware structure
2157  */
2158 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2159 {
2160         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2161         u16 reg;
2162         s32 rc;
2163
2164         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2165                 return IXGBE_SUCCESS;
2166
2167         rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2168         if (rc)
2169                 return rc;
2170
2171         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2172         if (rc)
2173                 goto out;
2174         if (reg & IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN) {
2175                 reg &= ~IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN;
2176                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2177                                           reg);
2178         }
2179
2180         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, &reg);
2181         if (rc)
2182                 goto out;
2183         if (reg & IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN) {
2184                 reg &= ~IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN;
2185                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0,
2186                                           reg);
2187         }
2188
2189         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 2);
2190         if (rc)
2191                 goto out;
2192
2193         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2194                                       &reg);
2195         if (rc)
2196                 goto out;
2197         if (reg & IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN) {
2198                 reg &= ~IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN;
2199                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2200                                           reg);
2201                 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2202                                                0);
2203                 if (rc)
2204                         goto out;
2205                 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2206                                               &reg);
2207                 if (rc)
2208                         goto out;
2209                 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2210                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2211                                           reg);
2212                 usec_delay(50);
2213         } else {
2214                 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2215                                                0);
2216                 if (rc)
2217                         goto out;
2218         }
2219
2220         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2221         if (rc)
2222                 goto out;
2223
2224         if (!(reg & IXGBE_M88E1500_COPPER_CTRL_AN_EN)) {
2225                 reg |= IXGBE_M88E1500_COPPER_CTRL_AN_EN;
2226                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2227                                           reg);
2228         }
2229
2230         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, &reg);
2231         if (rc)
2232                 goto out;
2233         reg &= ~IXGBE_M88E1500_1000T_CTRL_HALF_DUPLEX;
2234         reg &= ~IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2235         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
2236                 reg |= IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2237         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, reg);
2238
2239         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, &reg);
2240         if (rc)
2241                 goto out;
2242         reg &= ~IXGBE_M88E1500_COPPER_AN_T4;
2243         reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_FD;
2244         reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_HD;
2245         reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_FD;
2246         reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_HD;
2247
2248         /* Flow control auto negotiation configuration was moved from here to
2249          * the function ixgbe_setup_fc_sgmii_x550em_a()
2250          */
2251
2252         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
2253                 reg |= IXGBE_M88E1500_COPPER_AN_100TX_FD;
2254         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
2255                 reg |= IXGBE_M88E1500_COPPER_AN_10TX_FD;
2256         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, reg);
2257
2258         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2259         if (rc)
2260                 goto out;
2261         reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
2262         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2263
2264
2265         hw->mac.ops.release_swfw_sync(hw, mask);
2266         return rc;
2267
2268 out:
2269         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2270         hw->mac.ops.release_swfw_sync(hw, mask);
2271         return rc;
2272 }
2273
2274 /**
2275  * ixgbe_reset_phy_m88e1500 - Reset m88e1500 PHY
2276  * @hw: pointer to hardware structure
2277  *
2278  * The PHY token must be held when calling this function.
2279  */
2280 static s32 ixgbe_reset_phy_m88e1500(struct ixgbe_hw *hw)
2281 {
2282         u16 reg;
2283         s32 rc;
2284
2285         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2286         if (rc)
2287                 return rc;
2288
2289         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2290         if (rc)
2291                 return rc;
2292
2293         reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2294         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2295
2296         usec_delay(10);
2297
2298         return rc;
2299 }
2300
2301 /**
2302  * ixgbe_reset_phy_m88e1543 - Reset m88e1543 PHY
2303  * @hw: pointer to hardware structure
2304  *
2305  * The PHY token must be held when calling this function.
2306  */
2307 static s32 ixgbe_reset_phy_m88e1543(struct ixgbe_hw *hw)
2308 {
2309         return hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2310 }
2311
2312 /**
2313  * ixgbe_reset_phy_m88 - Reset m88 PHY
2314  * @hw: pointer to hardware structure
2315  */
2316 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2317 {
2318         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2319         u16 reg;
2320         s32 rc;
2321
2322         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2323                 return IXGBE_SUCCESS;
2324
2325         rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2326         if (rc)
2327                 return rc;
2328
2329         switch (hw->phy.id) {
2330         case IXGBE_M88E1500_E_PHY_ID:
2331                 rc = ixgbe_reset_phy_m88e1500(hw);
2332                 break;
2333         case IXGBE_M88E1543_E_PHY_ID:
2334                 rc = ixgbe_reset_phy_m88e1543(hw);
2335                 break;
2336         default:
2337                 rc = IXGBE_ERR_PHY;
2338                 break;
2339         }
2340
2341         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2342         if (rc)
2343                 goto out;
2344
2345         reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2346               IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2347               IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2348         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2349         if (rc)
2350                 goto out;
2351
2352         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2353         if (rc)
2354                 goto out;
2355
2356         reg = IXGBE_M88E1500_GEN_CTRL_RESET |
2357               IXGBE_M88E1500_GEN_CTRL_MODE_SGMII_COPPER;
2358         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_GEN_CTRL, 0, reg);
2359         if (rc)
2360                 goto out;
2361
2362         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2363         if (rc)
2364                 goto out;
2365
2366         reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2367               IXGBE_M88E1500_FIBER_CTRL_AN_EN |
2368               IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2369               IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2370         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2371         if (rc)
2372                 goto out;
2373
2374         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2375         if (rc)
2376                 goto out;
2377
2378         reg = (IXGBE_M88E1500_MAC_CTRL_1_DWN_4X <<
2379                IXGBE_M88E1500_MAC_CTRL_1_DWN_SHIFT) |
2380               (IXGBE_M88E1500_MAC_CTRL_1_ED_TM <<
2381                IXGBE_M88E1500_MAC_CTRL_1_ED_SHIFT) |
2382               (IXGBE_M88E1500_MAC_CTRL_1_MDIX_AUTO <<
2383                IXGBE_M88E1500_MAC_CTRL_1_MDIX_SHIFT);
2384         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, reg);
2385         if (rc)
2386                 goto out;
2387
2388         reg = IXGBE_M88E1500_COPPER_CTRL_RESET |
2389               IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2390               IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2391               IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2392               IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB;
2393         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2394         if (rc)
2395                 goto out;
2396
2397         hw->mac.ops.release_swfw_sync(hw, mask);
2398
2399         /* In case of first reset set advertised speeds to default value */
2400         if (!hw->phy.autoneg_advertised)
2401                 hw->phy.autoneg_advertised = IXGBE_LINK_SPEED_1GB_FULL |
2402                                              IXGBE_LINK_SPEED_100_FULL |
2403                                              IXGBE_LINK_SPEED_10_FULL;
2404
2405         return ixgbe_setup_m88(hw);
2406
2407 out:
2408         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2409         hw->mac.ops.release_swfw_sync(hw, mask);
2410         return rc;
2411 }
2412
2413 /**
2414  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2415  *  @hw: pointer to hardware structure
2416  *
2417  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2418  *  values.
2419  **/
2420 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2421 {
2422         /* Save NW management interface connected on board. This is used
2423          * to determine internal PHY mode.
2424          */
2425         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2426
2427         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2428          * PHY address. This register field was has only been used for X552.
2429          */
2430         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2431             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2432                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2433                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2434                                IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2435         }
2436
2437         return IXGBE_SUCCESS;
2438 }
2439
2440 /**
2441  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2442  *  @hw: pointer to hardware structure
2443  *
2444  *  Initialize any function pointers that were not able to be
2445  *  set during init_shared_code because the PHY/SFP type was
2446  *  not known.  Perform the SFP init if necessary.
2447  */
2448 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2449 {
2450         struct ixgbe_phy_info *phy = &hw->phy;
2451         s32 ret_val;
2452
2453         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2454
2455         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2456                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2457                 ixgbe_setup_mux_ctl(hw);
2458                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2459         }
2460
2461         switch (hw->device_id) {
2462         case IXGBE_DEV_ID_X550EM_A_1G_T:
2463         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2464                 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2465                 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2466                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2467                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2468                 if (hw->bus.lan_id)
2469                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2470                 else
2471                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2472
2473                 break;
2474         case IXGBE_DEV_ID_X550EM_A_10G_T:
2475         case IXGBE_DEV_ID_X550EM_A_SFP:
2476                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2477                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2478                 if (hw->bus.lan_id)
2479                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2480                 else
2481                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2482                 break;
2483         case IXGBE_DEV_ID_X550EM_X_SFP:
2484                 /* set up for CS4227 usage */
2485                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2486                 break;
2487         default:
2488                 break;
2489         }
2490
2491         /* Identify the PHY or SFP module */
2492         ret_val = phy->ops.identify(hw);
2493         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2494                 return ret_val;
2495
2496         /* Setup function pointers based on detected hardware */
2497         ixgbe_init_mac_link_ops_X550em(hw);
2498         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2499                 phy->ops.reset = NULL;
2500
2501         /* Set functions pointers based on phy type */
2502         switch (hw->phy.type) {
2503         case ixgbe_phy_x550em_kx4:
2504                 phy->ops.setup_link = NULL;
2505                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2506                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2507                 break;
2508         case ixgbe_phy_x550em_kr:
2509                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2510                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2511                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2512                 break;
2513         case ixgbe_phy_x550em_ext_t:
2514                 /* If internal link mode is XFI, then setup iXFI internal link,
2515                  * else setup KR now.
2516                  */
2517                 phy->ops.setup_internal_link =
2518                                               ixgbe_setup_internal_phy_t_x550em;
2519
2520                 /* setup SW LPLU only for first revision of X550EM_x */
2521                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2522                     !(IXGBE_FUSES0_REV_MASK &
2523                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2524                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2525
2526                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2527                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2528                 break;
2529         case ixgbe_phy_sgmii:
2530                 phy->ops.setup_link = NULL;
2531                 break;
2532         case ixgbe_phy_m88:
2533                 phy->ops.setup_link = ixgbe_setup_m88;
2534                 phy->ops.reset = ixgbe_reset_phy_m88;
2535                 break;
2536         default:
2537                 break;
2538         }
2539         return ret_val;
2540 }
2541
2542 /**
2543  * ixgbe_set_mdio_speed - Set MDIO clock speed
2544  *  @hw: pointer to hardware structure
2545  */
2546 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2547 {
2548         u32 hlreg0;
2549
2550         switch (hw->device_id) {
2551         case IXGBE_DEV_ID_X550EM_X_10G_T:
2552         case IXGBE_DEV_ID_X550EM_A_SGMII:
2553         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2554         case IXGBE_DEV_ID_X550EM_A_10G_T:
2555         case IXGBE_DEV_ID_X550EM_A_SFP:
2556         case IXGBE_DEV_ID_X550EM_A_QSFP:
2557                 /* Config MDIO clock speed before the first MDIO PHY access */
2558                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2559                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2560                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2561                 break;
2562         case IXGBE_DEV_ID_X550EM_A_1G_T:
2563         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2564                 /* Select fast MDIO clock speed for these devices */
2565                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2566                 hlreg0 |= IXGBE_HLREG0_MDCSPD;
2567                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2568                 break;
2569         default:
2570                 break;
2571         }
2572 }
2573
2574 /**
2575  *  ixgbe_reset_hw_X550em - Perform hardware reset
2576  *  @hw: pointer to hardware structure
2577  *
2578  *  Resets the hardware by resetting the transmit and receive units, masks
2579  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2580  *  reset.
2581  */
2582 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2583 {
2584         ixgbe_link_speed link_speed;
2585         s32 status;
2586         u32 ctrl = 0;
2587         u32 i;
2588         bool link_up = false;
2589
2590         DEBUGFUNC("ixgbe_reset_hw_X550em");
2591
2592         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2593         status = hw->mac.ops.stop_adapter(hw);
2594         if (status != IXGBE_SUCCESS)
2595                 return status;
2596
2597         /* flush pending Tx transactions */
2598         ixgbe_clear_tx_pending(hw);
2599
2600         ixgbe_set_mdio_speed(hw);
2601
2602         /* PHY ops must be identified and initialized prior to reset */
2603         status = hw->phy.ops.init(hw);
2604
2605         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2606                 return status;
2607
2608         /* start the external PHY */
2609         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2610                 status = ixgbe_init_ext_t_x550em(hw);
2611                 if (status)
2612                         return status;
2613         }
2614
2615         /* Setup SFP module if there is one present. */
2616         if (hw->phy.sfp_setup_needed) {
2617                 status = hw->mac.ops.setup_sfp(hw);
2618                 hw->phy.sfp_setup_needed = false;
2619         }
2620
2621         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2622                 return status;
2623
2624         /* Reset PHY */
2625         if (!hw->phy.reset_disable && hw->phy.ops.reset)
2626                 hw->phy.ops.reset(hw);
2627
2628 mac_reset_top:
2629         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2630          * If link reset is used when link is up, it might reset the PHY when
2631          * mng is using it.  If link is down or the flag to force full link
2632          * reset is set, then perform link reset.
2633          */
2634         ctrl = IXGBE_CTRL_LNK_RST;
2635         if (!hw->force_full_reset) {
2636                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2637                 if (link_up)
2638                         ctrl = IXGBE_CTRL_RST;
2639         }
2640
2641         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2642         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2643         IXGBE_WRITE_FLUSH(hw);
2644
2645         /* Poll for reset bit to self-clear meaning reset is complete */
2646         for (i = 0; i < 10; i++) {
2647                 usec_delay(1);
2648                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2649                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2650                         break;
2651         }
2652
2653         if (ctrl & IXGBE_CTRL_RST_MASK) {
2654                 status = IXGBE_ERR_RESET_FAILED;
2655                 DEBUGOUT("Reset polling failed to complete.\n");
2656         }
2657
2658         msec_delay(50);
2659
2660         /* Double resets are required for recovery from certain error
2661          * conditions.  Between resets, it is necessary to stall to
2662          * allow time for any pending HW events to complete.
2663          */
2664         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2665                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2666                 goto mac_reset_top;
2667         }
2668
2669         /* Store the permanent mac address */
2670         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2671
2672         /* Store MAC address from RAR0, clear receive address registers, and
2673          * clear the multicast table.  Also reset num_rar_entries to 128,
2674          * since we modify this value when programming the SAN MAC address.
2675          */
2676         hw->mac.num_rar_entries = 128;
2677         hw->mac.ops.init_rx_addrs(hw);
2678
2679         ixgbe_set_mdio_speed(hw);
2680
2681         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2682                 ixgbe_setup_mux_ctl(hw);
2683
2684         return status;
2685 }
2686
2687 /**
2688  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2689  * @hw: pointer to hardware structure
2690  */
2691 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2692 {
2693         u32 status;
2694         u16 reg;
2695
2696         status = hw->phy.ops.read_reg(hw,
2697                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2698                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2699                                       &reg);
2700
2701         if (status != IXGBE_SUCCESS)
2702                 return status;
2703
2704         /* If PHY FW reset completed bit is set then this is the first
2705          * SW instance after a power on so the PHY FW must be un-stalled.
2706          */
2707         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2708                 status = hw->phy.ops.read_reg(hw,
2709                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2710                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2711                                         &reg);
2712
2713                 if (status != IXGBE_SUCCESS)
2714                         return status;
2715
2716                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2717
2718                 status = hw->phy.ops.write_reg(hw,
2719                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2720                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2721                                         reg);
2722
2723                 if (status != IXGBE_SUCCESS)
2724                         return status;
2725         }
2726
2727         return status;
2728 }
2729
2730 /**
2731  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2732  *  @hw: pointer to hardware structure
2733  *
2734  *  Configures the integrated KR PHY for X550EM_x.
2735  **/
2736 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2737 {
2738         if (hw->mac.type != ixgbe_mac_X550EM_x)
2739                 return IXGBE_SUCCESS;
2740
2741         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2742 }
2743
2744 /**
2745  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2746  *  @hw: pointer to hardware structure
2747  *
2748  *  Configure the external PHY and the integrated KR PHY for SFP support.
2749  **/
2750 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2751                                     ixgbe_link_speed speed,
2752                                     bool autoneg_wait_to_complete)
2753 {
2754         s32 ret_val;
2755         u16 reg_slice, reg_val;
2756         bool setup_linear = false;
2757         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2758
2759         /* Check if SFP module is supported and linear */
2760         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2761
2762         /* If no SFP module present, then return success. Return success since
2763          * there is no reason to configure CS4227 and SFP not present error is
2764          * not excepted in the setup MAC link flow.
2765          */
2766         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2767                 return IXGBE_SUCCESS;
2768
2769         if (ret_val != IXGBE_SUCCESS)
2770                 return ret_val;
2771
2772         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2773                 /* Configure CS4227 LINE side to 10G SR. */
2774                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2775                             (hw->bus.lan_id << 12);
2776                 reg_val = IXGBE_CS4227_SPEED_10G;
2777                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2778                                                   reg_val);
2779
2780                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2781                             (hw->bus.lan_id << 12);
2782                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2783                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2784                                                   reg_val);
2785
2786                 /* Configure CS4227 for HOST connection rate then type. */
2787                 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2788                             (hw->bus.lan_id << 12);
2789                 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2790                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2791                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2792                                                   reg_val);
2793
2794                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2795                             (hw->bus.lan_id << 12);
2796                 if (setup_linear)
2797                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2798                 else
2799                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2800                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2801                                                   reg_val);
2802
2803                 /* Setup XFI internal link. */
2804                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2805         } else {
2806                 /* Configure internal PHY for KR/KX. */
2807                 ixgbe_setup_kr_speed_x550em(hw, speed);
2808
2809                 /* Configure CS4227 LINE side to proper mode. */
2810                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2811                             (hw->bus.lan_id << 12);
2812                 if (setup_linear)
2813                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2814                 else
2815                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2816                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2817                                                   reg_val);
2818         }
2819         return ret_val;
2820 }
2821
2822 /**
2823  *  ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2824  *  @hw: pointer to hardware structure
2825  *  @speed: the link speed to force
2826  *
2827  *  Configures the integrated PHY for native SFI mode. Used to connect the
2828  *  internal PHY directly to an SFP cage, without autonegotiation.
2829  **/
2830 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2831 {
2832         struct ixgbe_mac_info *mac = &hw->mac;
2833         s32 status;
2834         u32 reg_val;
2835
2836         /* Disable all AN and force speed to 10G Serial. */
2837         status = mac->ops.read_iosf_sb_reg(hw,
2838                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2839                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2840         if (status != IXGBE_SUCCESS)
2841                 return status;
2842
2843         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2844         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2845         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2846         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2847
2848         /* Select forced link speed for internal PHY. */
2849         switch (*speed) {
2850         case IXGBE_LINK_SPEED_10GB_FULL:
2851                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2852                 break;
2853         case IXGBE_LINK_SPEED_1GB_FULL:
2854                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2855                 break;
2856         default:
2857                 /* Other link speeds are not supported by internal PHY. */
2858                 return IXGBE_ERR_LINK_SETUP;
2859         }
2860
2861         status = mac->ops.write_iosf_sb_reg(hw,
2862                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2863                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2864
2865         /* Toggle port SW reset by AN reset. */
2866         status = ixgbe_restart_an_internal_phy_x550em(hw);
2867
2868         return status;
2869 }
2870
2871 /**
2872  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2873  *  @hw: pointer to hardware structure
2874  *
2875  *  Configure the the integrated PHY for SFP support.
2876  **/
2877 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2878                                     ixgbe_link_speed speed,
2879                                     bool autoneg_wait_to_complete)
2880 {
2881         s32 ret_val;
2882         u16 reg_phy_ext;
2883         bool setup_linear = false;
2884         u32 reg_slice, reg_phy_int, slice_offset;
2885
2886         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2887
2888         /* Check if SFP module is supported and linear */
2889         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2890
2891         /* If no SFP module present, then return success. Return success since
2892          * SFP not present error is not excepted in the setup MAC link flow.
2893          */
2894         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2895                 return IXGBE_SUCCESS;
2896
2897         if (ret_val != IXGBE_SUCCESS)
2898                 return ret_val;
2899
2900         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2901                 /* Configure internal PHY for native SFI based on module type */
2902                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2903                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2904                                    IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2905
2906                 if (ret_val != IXGBE_SUCCESS)
2907                         return ret_val;
2908
2909                 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2910                 if (!setup_linear)
2911                         reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2912
2913                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2914                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2915                                    IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2916
2917                 if (ret_val != IXGBE_SUCCESS)
2918                         return ret_val;
2919
2920                 /* Setup SFI internal link. */
2921                 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2922         } else {
2923                 /* Configure internal PHY for KR/KX. */
2924                 ixgbe_setup_kr_speed_x550em(hw, speed);
2925
2926                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2927                         /* Find Address */
2928                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2929                         return IXGBE_ERR_PHY_ADDR_INVALID;
2930                 }
2931
2932                 /* Get external PHY SKU id */
2933                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
2934                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2935
2936                 if (ret_val != IXGBE_SUCCESS)
2937                         return ret_val;
2938
2939                 /* When configuring quad port CS4223, the MAC instance is part
2940                  * of the slice offset.
2941                  */
2942                 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
2943                         slice_offset = (hw->bus.lan_id +
2944                                         (hw->bus.instance_id << 1)) << 12;
2945                 else
2946                         slice_offset = hw->bus.lan_id << 12;
2947
2948                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2949                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2950                 if (setup_linear)
2951                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2952                 else
2953                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2954                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2955                                          IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2956         }
2957         return ret_val;
2958 }
2959
2960 /**
2961  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2962  *  @hw: pointer to hardware structure
2963  *
2964  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2965  **/
2966 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2967 {
2968         struct ixgbe_mac_info *mac = &hw->mac;
2969         s32 status;
2970         u32 reg_val;
2971
2972         /* Disable training protocol FSM. */
2973         status = mac->ops.read_iosf_sb_reg(hw,
2974                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2975                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2976         if (status != IXGBE_SUCCESS)
2977                 return status;
2978         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2979         status = mac->ops.write_iosf_sb_reg(hw,
2980                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2981                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2982         if (status != IXGBE_SUCCESS)
2983                 return status;
2984
2985         /* Disable Flex from training TXFFE. */
2986         status = mac->ops.read_iosf_sb_reg(hw,
2987                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2988                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2989         if (status != IXGBE_SUCCESS)
2990                 return status;
2991         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2992         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2993         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2994         status = mac->ops.write_iosf_sb_reg(hw,
2995                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2996                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2997         if (status != IXGBE_SUCCESS)
2998                 return status;
2999         status = mac->ops.read_iosf_sb_reg(hw,
3000                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
3001                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3002         if (status != IXGBE_SUCCESS)
3003                 return status;
3004         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
3005         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
3006         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
3007         status = mac->ops.write_iosf_sb_reg(hw,
3008                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
3009                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3010         if (status != IXGBE_SUCCESS)
3011                 return status;
3012
3013         /* Enable override for coefficients. */
3014         status = mac->ops.read_iosf_sb_reg(hw,
3015                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
3016                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3017         if (status != IXGBE_SUCCESS)
3018                 return status;
3019         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
3020         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
3021         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
3022         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
3023         status = mac->ops.write_iosf_sb_reg(hw,
3024                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
3025                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3026         return status;
3027 }
3028
3029 /**
3030  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
3031  *  @hw: pointer to hardware structure
3032  *  @speed: the link speed to force
3033  *
3034  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
3035  *  internal and external PHY at a specific speed, without autonegotiation.
3036  **/
3037 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
3038 {
3039         struct ixgbe_mac_info *mac = &hw->mac;
3040         s32 status;
3041         u32 reg_val;
3042
3043         /* Disable AN and force speed to 10G Serial. */
3044         status = mac->ops.read_iosf_sb_reg(hw,
3045                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3046                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3047         if (status != IXGBE_SUCCESS)
3048                 return status;
3049
3050         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3051         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3052
3053         /* Select forced link speed for internal PHY. */
3054         switch (*speed) {
3055         case IXGBE_LINK_SPEED_10GB_FULL:
3056                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3057                 break;
3058         case IXGBE_LINK_SPEED_1GB_FULL:
3059                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
3060                 break;
3061         default:
3062                 /* Other link speeds are not supported by internal KR PHY. */
3063                 return IXGBE_ERR_LINK_SETUP;
3064         }
3065
3066         status = mac->ops.write_iosf_sb_reg(hw,
3067                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3068                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3069         if (status != IXGBE_SUCCESS)
3070                 return status;
3071
3072         /* Additional configuration needed for x550em_x */
3073         if (hw->mac.type == ixgbe_mac_X550EM_x) {
3074                 status = ixgbe_setup_ixfi_x550em_x(hw);
3075                 if (status != IXGBE_SUCCESS)
3076                         return status;
3077         }
3078
3079         /* Toggle port SW reset by AN reset. */
3080         status = ixgbe_restart_an_internal_phy_x550em(hw);
3081
3082         return status;
3083 }
3084
3085 /**
3086  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
3087  * @hw: address of hardware structure
3088  * @link_up: address of boolean to indicate link status
3089  *
3090  * Returns error code if unable to get link status.
3091  */
3092 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
3093 {
3094         u32 ret;
3095         u16 autoneg_status;
3096
3097         *link_up = false;
3098
3099         /* read this twice back to back to indicate current status */
3100         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3101                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3102                                    &autoneg_status);
3103         if (ret != IXGBE_SUCCESS)
3104                 return ret;
3105
3106         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3107                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3108                                    &autoneg_status);
3109         if (ret != IXGBE_SUCCESS)
3110                 return ret;
3111
3112         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
3113
3114         return IXGBE_SUCCESS;
3115 }
3116
3117 /**
3118  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
3119  * @hw: point to hardware structure
3120  *
3121  * Configures the link between the integrated KR PHY and the external X557 PHY
3122  * The driver will call this function when it gets a link status change
3123  * interrupt from the X557 PHY. This function configures the link speed
3124  * between the PHYs to match the link speed of the BASE-T link.
3125  *
3126  * A return of a non-zero value indicates an error, and the base driver should
3127  * not report link up.
3128  */
3129 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
3130 {
3131         ixgbe_link_speed force_speed;
3132         bool link_up;
3133         u32 status;
3134         u16 speed;
3135
3136         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3137                 return IXGBE_ERR_CONFIG;
3138
3139         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3140                 /* If link is down, there is no setup necessary so return  */
3141                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3142                 if (status != IXGBE_SUCCESS)
3143                         return status;
3144
3145                 if (!link_up)
3146                         return IXGBE_SUCCESS;
3147
3148                 status = hw->phy.ops.read_reg(hw,
3149                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3150                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3151                                               &speed);
3152                 if (status != IXGBE_SUCCESS)
3153                         return status;
3154
3155                 /* If link is still down - no setup is required so return */
3156                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3157                 if (status != IXGBE_SUCCESS)
3158                         return status;
3159                 if (!link_up)
3160                         return IXGBE_SUCCESS;
3161
3162                 /* clear everything but the speed and duplex bits */
3163                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3164
3165                 switch (speed) {
3166                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3167                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3168                         break;
3169                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3170                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3171                         break;
3172                 default:
3173                         /* Internal PHY does not support anything else */
3174                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
3175                 }
3176
3177                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3178         } else {
3179                 speed = IXGBE_LINK_SPEED_10GB_FULL |
3180                         IXGBE_LINK_SPEED_1GB_FULL;
3181                 return ixgbe_setup_kr_speed_x550em(hw, speed);
3182         }
3183 }
3184
3185 /**
3186  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3187  *  @hw: pointer to hardware structure
3188  *
3189  *  Configures the integrated KR PHY to use internal loopback mode.
3190  **/
3191 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3192 {
3193         s32 status;
3194         u32 reg_val;
3195
3196         /* Disable AN and force speed to 10G Serial. */
3197         status = hw->mac.ops.read_iosf_sb_reg(hw,
3198                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3199                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3200         if (status != IXGBE_SUCCESS)
3201                 return status;
3202         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3203         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3204         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3205         status = hw->mac.ops.write_iosf_sb_reg(hw,
3206                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3207                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3208         if (status != IXGBE_SUCCESS)
3209                 return status;
3210
3211         /* Set near-end loopback clocks. */
3212         status = hw->mac.ops.read_iosf_sb_reg(hw,
3213                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3214                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3215         if (status != IXGBE_SUCCESS)
3216                 return status;
3217         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3218         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3219         status = hw->mac.ops.write_iosf_sb_reg(hw,
3220                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3221                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3222         if (status != IXGBE_SUCCESS)
3223                 return status;
3224
3225         /* Set loopback enable. */
3226         status = hw->mac.ops.read_iosf_sb_reg(hw,
3227                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3228                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3229         if (status != IXGBE_SUCCESS)
3230                 return status;
3231         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3232         status = hw->mac.ops.write_iosf_sb_reg(hw,
3233                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3234                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3235         if (status != IXGBE_SUCCESS)
3236                 return status;
3237
3238         /* Training bypass. */
3239         status = hw->mac.ops.read_iosf_sb_reg(hw,
3240                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3241                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3242         if (status != IXGBE_SUCCESS)
3243                 return status;
3244         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3245         status = hw->mac.ops.write_iosf_sb_reg(hw,
3246                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3247                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3248
3249         return status;
3250 }
3251
3252 /**
3253  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3254  *  assuming that the semaphore is already obtained.
3255  *  @hw: pointer to hardware structure
3256  *  @offset: offset of  word in the EEPROM to read
3257  *  @data: word read from the EEPROM
3258  *
3259  *  Reads a 16 bit word from the EEPROM using the hostif.
3260  **/
3261 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3262 {
3263         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3264         struct ixgbe_hic_read_shadow_ram buffer;
3265         s32 status;
3266
3267         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3268         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3269         buffer.hdr.req.buf_lenh = 0;
3270         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3271         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3272
3273         /* convert offset from words to bytes */
3274         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3275         /* one word */
3276         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3277
3278         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3279         if (status)
3280                 return status;
3281
3282         status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3283                                     IXGBE_HI_COMMAND_TIMEOUT);
3284         if (!status) {
3285                 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3286                                                   FW_NVM_DATA_OFFSET);
3287         }
3288
3289         hw->mac.ops.release_swfw_sync(hw, mask);
3290         return status;
3291 }
3292
3293 /**
3294  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3295  *  @hw: pointer to hardware structure
3296  *  @offset: offset of  word in the EEPROM to read
3297  *  @words: number of words
3298  *  @data: word(s) read from the EEPROM
3299  *
3300  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
3301  **/
3302 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3303                                      u16 offset, u16 words, u16 *data)
3304 {
3305         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3306         struct ixgbe_hic_read_shadow_ram buffer;
3307         u32 current_word = 0;
3308         u16 words_to_read;
3309         s32 status;
3310         u32 i;
3311
3312         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3313
3314         /* Take semaphore for the entire operation. */
3315         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3316         if (status) {
3317                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3318                 return status;
3319         }
3320
3321         while (words) {
3322                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3323                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3324                 else
3325                         words_to_read = words;
3326
3327                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3328                 buffer.hdr.req.buf_lenh = 0;
3329                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3330                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3331
3332                 /* convert offset from words to bytes */
3333                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3334                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3335
3336                 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3337                                             IXGBE_HI_COMMAND_TIMEOUT);
3338
3339                 if (status) {
3340                         DEBUGOUT("Host interface command failed\n");
3341                         goto out;
3342                 }
3343
3344                 for (i = 0; i < words_to_read; i++) {
3345                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3346                                   2 * i;
3347                         u32 value = IXGBE_READ_REG(hw, reg);
3348
3349                         data[current_word] = (u16)(value & 0xffff);
3350                         current_word++;
3351                         i++;
3352                         if (i < words_to_read) {
3353                                 value >>= 16;
3354                                 data[current_word] = (u16)(value & 0xffff);
3355                                 current_word++;
3356                         }
3357                 }
3358                 words -= words_to_read;
3359         }
3360
3361 out:
3362         hw->mac.ops.release_swfw_sync(hw, mask);
3363         return status;
3364 }
3365
3366 /**
3367  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3368  *  @hw: pointer to hardware structure
3369  *  @offset: offset of  word in the EEPROM to write
3370  *  @data: word write to the EEPROM
3371  *
3372  *  Write a 16 bit word to the EEPROM using the hostif.
3373  **/
3374 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3375                                     u16 data)
3376 {
3377         s32 status;
3378         struct ixgbe_hic_write_shadow_ram buffer;
3379
3380         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3381
3382         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3383         buffer.hdr.req.buf_lenh = 0;
3384         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3385         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3386
3387          /* one word */
3388         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3389         buffer.data = data;
3390         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3391
3392         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3393                                               sizeof(buffer),
3394                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3395
3396         return status;
3397 }
3398
3399 /**
3400  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3401  *  @hw: pointer to hardware structure
3402  *  @offset: offset of  word in the EEPROM to write
3403  *  @data: word write to the EEPROM
3404  *
3405  *  Write a 16 bit word to the EEPROM using the hostif.
3406  **/
3407 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3408                                u16 data)
3409 {
3410         s32 status = IXGBE_SUCCESS;
3411
3412         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3413
3414         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3415             IXGBE_SUCCESS) {
3416                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3417                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3418         } else {
3419                 DEBUGOUT("write ee hostif failed to get semaphore");
3420                 status = IXGBE_ERR_SWFW_SYNC;
3421         }
3422
3423         return status;
3424 }
3425
3426 /**
3427  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3428  *  @hw: pointer to hardware structure
3429  *  @offset: offset of  word in the EEPROM to write
3430  *  @words: number of words
3431  *  @data: word(s) write to the EEPROM
3432  *
3433  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3434  **/
3435 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3436                                       u16 offset, u16 words, u16 *data)
3437 {
3438         s32 status = IXGBE_SUCCESS;
3439         u32 i = 0;
3440
3441         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3442
3443         /* Take semaphore for the entire operation. */
3444         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3445         if (status != IXGBE_SUCCESS) {
3446                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3447                 goto out;
3448         }
3449
3450         for (i = 0; i < words; i++) {
3451                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3452                                                          data[i]);
3453
3454                 if (status != IXGBE_SUCCESS) {
3455                         DEBUGOUT("Eeprom buffered write failed\n");
3456                         break;
3457                 }
3458         }
3459
3460         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3461 out:
3462
3463         return status;
3464 }
3465
3466 /**
3467  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3468  * @hw: pointer to hardware structure
3469  * @ptr: pointer offset in eeprom
3470  * @size: size of section pointed by ptr, if 0 first word will be used as size
3471  * @csum: address of checksum to update
3472  *
3473  * Returns error status for any failure
3474  */
3475 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3476                                    u16 size, u16 *csum, u16 *buffer,
3477                                    u32 buffer_size)
3478 {
3479         u16 buf[256];
3480         s32 status;
3481         u16 length, bufsz, i, start;
3482         u16 *local_buffer;
3483
3484         bufsz = sizeof(buf) / sizeof(buf[0]);
3485
3486         /* Read a chunk at the pointer location */
3487         if (!buffer) {
3488                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3489                 if (status) {
3490                         DEBUGOUT("Failed to read EEPROM image\n");
3491                         return status;
3492                 }
3493                 local_buffer = buf;
3494         } else {
3495                 if (buffer_size < ptr)
3496                         return  IXGBE_ERR_PARAM;
3497                 local_buffer = &buffer[ptr];
3498         }
3499
3500         if (size) {
3501                 start = 0;
3502                 length = size;
3503         } else {
3504                 start = 1;
3505                 length = local_buffer[0];
3506
3507                 /* Skip pointer section if length is invalid. */
3508                 if (length == 0xFFFF || length == 0 ||
3509                     (ptr + length) >= hw->eeprom.word_size)
3510                         return IXGBE_SUCCESS;
3511         }
3512
3513         if (buffer && ((u32)start + (u32)length > buffer_size))
3514                 return IXGBE_ERR_PARAM;
3515
3516         for (i = start; length; i++, length--) {
3517                 if (i == bufsz && !buffer) {
3518                         ptr += bufsz;
3519                         i = 0;
3520                         if (length < bufsz)
3521                                 bufsz = length;
3522
3523                         /* Read a chunk at the pointer location */
3524                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3525                                                                   bufsz, buf);
3526                         if (status) {
3527                                 DEBUGOUT("Failed to read EEPROM image\n");
3528                                 return status;
3529                         }
3530                 }
3531                 *csum += local_buffer[i];
3532         }
3533         return IXGBE_SUCCESS;
3534 }
3535
3536 /**
3537  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3538  *  @hw: pointer to hardware structure
3539  *  @buffer: pointer to buffer containing calculated checksum
3540  *  @buffer_size: size of buffer
3541  *
3542  *  Returns a negative error code on error, or the 16-bit checksum
3543  **/
3544 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3545 {
3546         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3547         u16 *local_buffer;
3548         s32 status;
3549         u16 checksum = 0;
3550         u16 pointer, i, size;
3551
3552         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3553
3554         hw->eeprom.ops.init_params(hw);
3555
3556         if (!buffer) {
3557                 /* Read pointer area */
3558                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3559                                                      IXGBE_EEPROM_LAST_WORD + 1,
3560                                                      eeprom_ptrs);
3561                 if (status) {
3562                         DEBUGOUT("Failed to read EEPROM image\n");
3563                         return status;
3564                 }
3565                 local_buffer = eeprom_ptrs;
3566         } else {
3567                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3568                         return IXGBE_ERR_PARAM;
3569                 local_buffer = buffer;
3570         }
3571
3572         /*
3573          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3574          * checksum word itself
3575          */
3576         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3577                 if (i != IXGBE_EEPROM_CHECKSUM)
3578                         checksum += local_buffer[i];
3579
3580         /*
3581          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3582          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3583          */
3584         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3585                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3586                         continue;
3587
3588                 pointer = local_buffer[i];
3589
3590                 /* Skip pointer section if the pointer is invalid. */
3591                 if (pointer == 0xFFFF || pointer == 0 ||
3592                     pointer >= hw->eeprom.word_size)
3593                         continue;
3594
3595                 switch (i) {
3596                 case IXGBE_PCIE_GENERAL_PTR:
3597                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3598                         break;
3599                 case IXGBE_PCIE_CONFIG0_PTR:
3600                 case IXGBE_PCIE_CONFIG1_PTR:
3601                         size = IXGBE_PCIE_CONFIG_SIZE;
3602                         break;
3603                 default:
3604                         size = 0;
3605                         break;
3606                 }
3607
3608                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3609                                                 buffer, buffer_size);
3610                 if (status)
3611                         return status;
3612         }
3613
3614         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3615
3616         return (s32)checksum;
3617 }
3618
3619 /**
3620  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3621  *  @hw: pointer to hardware structure
3622  *
3623  *  Returns a negative error code on error, or the 16-bit checksum
3624  **/
3625 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3626 {
3627         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3628 }
3629
3630 /**
3631  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3632  *  @hw: pointer to hardware structure
3633  *  @checksum_val: calculated checksum
3634  *
3635  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3636  *  caller does not need checksum_val, the value can be NULL.
3637  **/
3638 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3639 {
3640         s32 status;
3641         u16 checksum;
3642         u16 read_checksum = 0;
3643
3644         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3645
3646         /* Read the first word from the EEPROM. If this times out or fails, do
3647          * not continue or we could be in for a very long wait while every
3648          * EEPROM read fails
3649          */
3650         status = hw->eeprom.ops.read(hw, 0, &checksum);
3651         if (status) {
3652                 DEBUGOUT("EEPROM read failed\n");
3653                 return status;
3654         }
3655
3656         status = hw->eeprom.ops.calc_checksum(hw);
3657         if (status < 0)
3658                 return status;
3659
3660         checksum = (u16)(status & 0xffff);
3661
3662         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3663                                            &read_checksum);
3664         if (status)
3665                 return status;
3666
3667         /* Verify read checksum from EEPROM is the same as
3668          * calculated checksum
3669          */
3670         if (read_checksum != checksum) {
3671                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3672                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3673                              "Invalid EEPROM checksum");
3674         }
3675
3676         /* If the user cares, return the calculated checksum */
3677         if (checksum_val)
3678                 *checksum_val = checksum;
3679
3680         return status;
3681 }
3682
3683 /**
3684  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3685  * @hw: pointer to hardware structure
3686  *
3687  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3688  * checksum and updates the EEPROM and instructs the hardware to update
3689  * the flash.
3690  **/
3691 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3692 {
3693         s32 status;
3694         u16 checksum = 0;
3695
3696         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3697
3698         /* Read the first word from the EEPROM. If this times out or fails, do
3699          * not continue or we could be in for a very long wait while every
3700          * EEPROM read fails
3701          */
3702         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3703         if (status) {
3704                 DEBUGOUT("EEPROM read failed\n");
3705                 return status;
3706         }
3707
3708         status = ixgbe_calc_eeprom_checksum_X550(hw);
3709         if (status < 0)
3710                 return status;
3711
3712         checksum = (u16)(status & 0xffff);
3713
3714         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3715                                             checksum);
3716         if (status)
3717                 return status;
3718
3719         status = ixgbe_update_flash_X550(hw);
3720
3721         return status;
3722 }
3723
3724 /**
3725  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3726  *  @hw: pointer to hardware structure
3727  *
3728  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3729  **/
3730 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3731 {
3732         s32 status = IXGBE_SUCCESS;
3733         union ixgbe_hic_hdr2 buffer;
3734
3735         DEBUGFUNC("ixgbe_update_flash_X550");
3736
3737         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3738         buffer.req.buf_lenh = 0;
3739         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3740         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3741
3742         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3743                                               sizeof(buffer),
3744                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3745
3746         return status;
3747 }
3748
3749 /**
3750  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3751  *  @hw: pointer to hardware structure
3752  *
3753  *  Determines physical layer capabilities of the current configuration.
3754  **/
3755 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3756 {
3757         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3758         u16 ext_ability = 0;
3759
3760         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3761
3762         hw->phy.ops.identify(hw);
3763
3764         switch (hw->phy.type) {
3765         case ixgbe_phy_x550em_kr:
3766                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3767                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3768                 break;
3769         case ixgbe_phy_x550em_kx4:
3770                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3771                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3772                 break;
3773         case ixgbe_phy_x550em_ext_t:
3774                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3775                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3776                                      &ext_ability);
3777                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3778                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3779                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3780                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3781                 break;
3782         default:
3783                 break;
3784         }
3785
3786         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3787                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3788
3789         return physical_layer;
3790 }
3791
3792 /**
3793  * ixgbe_get_bus_info_x550em - Set PCI bus info
3794  * @hw: pointer to hardware structure
3795  *
3796  * Sets bus link width and speed to unknown because X550em is
3797  * not a PCI device.
3798  **/
3799 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3800 {
3801
3802         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3803
3804         hw->bus.width = ixgbe_bus_width_unknown;
3805         hw->bus.speed = ixgbe_bus_speed_unknown;
3806
3807         hw->mac.ops.set_lan_id(hw);
3808
3809         return IXGBE_SUCCESS;
3810 }
3811
3812 /**
3813  * ixgbe_disable_rx_x550 - Disable RX unit
3814  *
3815  * Enables the Rx DMA unit for x550
3816  **/
3817 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3818 {
3819         u32 rxctrl, pfdtxgswc;
3820         s32 status;
3821         struct ixgbe_hic_disable_rxen fw_cmd;
3822
3823         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3824
3825         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3826         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3827                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3828                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3829                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3830                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3831                         hw->mac.set_lben = true;
3832                 } else {
3833                         hw->mac.set_lben = false;
3834                 }
3835
3836                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3837                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3838                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3839                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3840
3841                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3842                                         sizeof(struct ixgbe_hic_disable_rxen),
3843                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3844
3845                 /* If we fail - disable RX using register write */
3846                 if (status) {
3847                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3848                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3849                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3850                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3851                         }
3852                 }
3853         }
3854 }
3855
3856 /**
3857  * ixgbe_enter_lplu_x550em - Transition to low power states
3858  *  @hw: pointer to hardware structure
3859  *
3860  * Configures Low Power Link Up on transition to low power states
3861  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3862  * X557 PHY immediately prior to entering LPLU.
3863  **/
3864 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3865 {
3866         u16 an_10g_cntl_reg, autoneg_reg, speed;
3867         s32 status;
3868         ixgbe_link_speed lcd_speed;
3869         u32 save_autoneg;
3870         bool link_up;
3871
3872         /* SW LPLU not required on later HW revisions. */
3873         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3874             (IXGBE_FUSES0_REV_MASK &
3875              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3876                 return IXGBE_SUCCESS;
3877
3878         /* If blocked by MNG FW, then don't restart AN */
3879         if (ixgbe_check_reset_blocked(hw))
3880                 return IXGBE_SUCCESS;
3881
3882         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3883         if (status != IXGBE_SUCCESS)
3884                 return status;
3885
3886         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3887
3888         if (status != IXGBE_SUCCESS)
3889                 return status;
3890
3891         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3892          * disabled, then force link down by entering low power mode.
3893          */
3894         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3895             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3896                 return ixgbe_set_copper_phy_power(hw, FALSE);
3897
3898         /* Determine LCD */
3899         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3900
3901         if (status != IXGBE_SUCCESS)
3902                 return status;
3903
3904         /* If no valid LCD link speed, then force link down and exit. */
3905         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3906                 return ixgbe_set_copper_phy_power(hw, FALSE);
3907
3908         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3909                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3910                                       &speed);
3911
3912         if (status != IXGBE_SUCCESS)
3913                 return status;
3914
3915         /* If no link now, speed is invalid so take link down */
3916         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3917         if (status != IXGBE_SUCCESS)
3918                 return ixgbe_set_copper_phy_power(hw, false);
3919
3920         /* clear everything but the speed bits */
3921         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3922
3923         /* If current speed is already LCD, then exit. */
3924         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3925              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3926             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3927              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3928                 return status;
3929
3930         /* Clear AN completed indication */
3931         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3932                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3933                                       &autoneg_reg);
3934
3935         if (status != IXGBE_SUCCESS)
3936                 return status;
3937
3938         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3939                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3940                              &an_10g_cntl_reg);
3941
3942         if (status != IXGBE_SUCCESS)
3943                 return status;
3944
3945         status = hw->phy.ops.read_reg(hw,
3946                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3947                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3948                              &autoneg_reg);
3949
3950         if (status != IXGBE_SUCCESS)
3951                 return status;
3952
3953         save_autoneg = hw->phy.autoneg_advertised;
3954
3955         /* Setup link at least common link speed */
3956         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3957
3958         /* restore autoneg from before setting lplu speed */
3959         hw->phy.autoneg_advertised = save_autoneg;
3960
3961         return status;
3962 }
3963
3964 /**
3965  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3966  *  @hw: pointer to hardware structure
3967  *  @lcd_speed: pointer to lowest common link speed
3968  *
3969  * Determine lowest common link speed with link partner.
3970  **/
3971 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3972 {
3973         u16 an_lp_status;
3974         s32 status;
3975         u16 word = hw->eeprom.ctrl_word_3;
3976
3977         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3978
3979         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3980                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3981                                       &an_lp_status);
3982
3983         if (status != IXGBE_SUCCESS)
3984                 return status;
3985
3986         /* If link partner advertised 1G, return 1G */
3987         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3988                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3989                 return status;
3990         }
3991
3992         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3993         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3994             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3995                 return status;
3996
3997         /* Link partner not capable of lower speeds, return 10G */
3998         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3999         return status;
4000 }
4001
4002 /**
4003  *  ixgbe_setup_fc_X550em - Set up flow control
4004  *  @hw: pointer to hardware structure
4005  *
4006  *  Called at init time to set up flow control.
4007  **/
4008 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
4009 {
4010         s32 ret_val = IXGBE_SUCCESS;
4011         u32 pause, asm_dir, reg_val;
4012
4013         DEBUGFUNC("ixgbe_setup_fc_X550em");
4014
4015         /* Validate the requested mode */
4016         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4017                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4018                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4019                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4020                 goto out;
4021         }
4022
4023         /* 10gig parts do not have a word in the EEPROM to determine the
4024          * default flow control setting, so we explicitly set it to full.
4025          */
4026         if (hw->fc.requested_mode == ixgbe_fc_default)
4027                 hw->fc.requested_mode = ixgbe_fc_full;
4028
4029         /* Determine PAUSE and ASM_DIR bits. */
4030         switch (hw->fc.requested_mode) {
4031         case ixgbe_fc_none:
4032                 pause = 0;
4033                 asm_dir = 0;
4034                 break;
4035         case ixgbe_fc_tx_pause:
4036                 pause = 0;
4037                 asm_dir = 1;
4038                 break;
4039         case ixgbe_fc_rx_pause:
4040                 /* Rx Flow control is enabled and Tx Flow control is
4041                  * disabled by software override. Since there really
4042                  * isn't a way to advertise that we are capable of RX
4043                  * Pause ONLY, we will advertise that we support both
4044                  * symmetric and asymmetric Rx PAUSE, as such we fall
4045                  * through to the fc_full statement.  Later, we will
4046                  * disable the adapter's ability to send PAUSE frames.
4047                  */
4048         case ixgbe_fc_full:
4049                 pause = 1;
4050                 asm_dir = 1;
4051                 break;
4052         default:
4053                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4054                         "Flow control param set incorrectly\n");
4055                 ret_val = IXGBE_ERR_CONFIG;
4056                 goto out;
4057         }
4058
4059         switch (hw->device_id) {
4060         case IXGBE_DEV_ID_X550EM_X_KR:
4061         case IXGBE_DEV_ID_X550EM_A_KR:
4062         case IXGBE_DEV_ID_X550EM_A_KR_L:
4063                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
4064                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4065                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
4066                 if (ret_val != IXGBE_SUCCESS)
4067                         goto out;
4068                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4069                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4070                 if (pause)
4071                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4072                 if (asm_dir)
4073                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4074                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
4075                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4076                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
4077
4078                 /* This device does not fully support AN. */
4079                 hw->fc.disable_fc_autoneg = true;
4080                 break;
4081         default:
4082                 break;
4083         }
4084
4085 out:
4086         return ret_val;
4087 }
4088
4089 /**
4090  *  ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
4091  *  @hw: pointer to hardware structure
4092  *
4093  *  Enable flow control according to IEEE clause 37.
4094  **/
4095 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
4096 {
4097         u32 link_s1, lp_an_page_low, an_cntl_1;
4098         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4099         ixgbe_link_speed speed;
4100         bool link_up;
4101
4102         /* AN should have completed when the cable was plugged in.
4103          * Look for reasons to bail out.  Bail out if:
4104          * - FC autoneg is disabled, or if
4105          * - link is not up.
4106          */
4107         if (hw->fc.disable_fc_autoneg) {
4108                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4109                              "Flow control autoneg is disabled");
4110                 goto out;
4111         }
4112
4113         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4114         if (!link_up) {
4115                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4116                 goto out;
4117         }
4118
4119         /* Check at auto-negotiation has completed */
4120         status = hw->mac.ops.read_iosf_sb_reg(hw,
4121                                         IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4122                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4123
4124         if (status != IXGBE_SUCCESS ||
4125             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4126                 DEBUGOUT("Auto-Negotiation did not complete\n");
4127                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4128                 goto out;
4129         }
4130
4131         /* Read the 10g AN autoc and LP ability registers and resolve
4132          * local flow control settings accordingly
4133          */
4134         status = hw->mac.ops.read_iosf_sb_reg(hw,
4135                                 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4136                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4137
4138         if (status != IXGBE_SUCCESS) {
4139                 DEBUGOUT("Auto-Negotiation did not complete\n");
4140                 goto out;
4141         }
4142
4143         status = hw->mac.ops.read_iosf_sb_reg(hw,
4144                                 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4145                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4146
4147         if (status != IXGBE_SUCCESS) {
4148                 DEBUGOUT("Auto-Negotiation did not complete\n");
4149                 goto out;
4150         }
4151
4152         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4153                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4154                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4155                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4156                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4157
4158 out:
4159         if (status == IXGBE_SUCCESS) {
4160                 hw->fc.fc_was_autonegged = true;
4161         } else {
4162                 hw->fc.fc_was_autonegged = false;
4163                 hw->fc.current_mode = hw->fc.requested_mode;
4164         }
4165 }
4166
4167 /**
4168  *  ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4169  *  @hw: pointer to hardware structure
4170  *
4171  **/
4172 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4173 {
4174         hw->fc.fc_was_autonegged = false;
4175         hw->fc.current_mode = hw->fc.requested_mode;
4176 }
4177
4178 /**
4179  *  ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4180  *  @hw: pointer to hardware structure
4181  *
4182  *  Enable flow control according to IEEE clause 37.
4183  **/
4184 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4185 {
4186         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4187         u16 reg, pcs_an_lp, pcs_an;
4188         ixgbe_link_speed speed;
4189         bool link_up;
4190
4191         /* AN should have completed when the cable was plugged in.
4192          * Look for reasons to bail out.  Bail out if:
4193          * - FC autoneg is disabled, or if
4194          * - link is not up.
4195          */
4196         if (hw->fc.disable_fc_autoneg) {
4197                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4198                              "Flow control autoneg is disabled");
4199                 goto out;
4200         }
4201
4202         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4203         if (!link_up) {
4204                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4205                 goto out;
4206         }
4207
4208         /* Check if auto-negotiation has completed */
4209         status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_STATUS,
4210                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg);
4211         if (status != IXGBE_SUCCESS ||
4212             (reg & IXGBE_M88E1500_COPPER_STATUS_AN_DONE) == 0) {
4213                 DEBUGOUT("Auto-Negotiation did not complete\n");
4214                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4215                 goto out;
4216         }
4217
4218         /* Get the advertized flow control */
4219         status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4220                                         IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an);
4221         if (status != IXGBE_SUCCESS)
4222                 goto out;
4223
4224         /* Get link partner's flow control */
4225         status = hw->phy.ops.read_reg(hw,
4226                         IXGBE_M88E1500_COPPER_AN_LP_ABILITY,
4227                                         IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an_lp);
4228         if (status != IXGBE_SUCCESS)
4229                 goto out;
4230
4231         /* Negotiate the flow control */
4232         status = ixgbe_negotiate_fc(hw, (u32)pcs_an, (u32)pcs_an_lp,
4233                                     IXGBE_M88E1500_COPPER_AN_PAUSE,
4234                                     IXGBE_M88E1500_COPPER_AN_AS_PAUSE,
4235                                     IXGBE_M88E1500_COPPER_AN_LP_PAUSE,
4236                                     IXGBE_M88E1500_COPPER_AN_LP_AS_PAUSE);
4237
4238 out:
4239         if (status == IXGBE_SUCCESS) {
4240                 hw->fc.fc_was_autonegged = true;
4241         } else {
4242                 hw->fc.fc_was_autonegged = false;
4243                 hw->fc.current_mode = hw->fc.requested_mode;
4244         }
4245 }
4246
4247 /**
4248  *  ixgbe_setup_fc_sgmii_x550em_a - Set up flow control
4249  *  @hw: pointer to hardware structure
4250  *
4251  *  Called at init time to set up flow control.
4252  **/
4253 s32 ixgbe_setup_fc_sgmii_x550em_a(struct ixgbe_hw *hw)
4254 {
4255         u16 reg;
4256         s32 rc;
4257
4258         /* Validate the requested mode */
4259         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4260                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4261                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4262                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4263         }
4264
4265         if (hw->fc.requested_mode == ixgbe_fc_default)
4266                 hw->fc.requested_mode = ixgbe_fc_full;
4267
4268         /* Read contents of the Auto-Negotiation register, page 0 reg 4 */
4269         rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4270                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg);
4271         if (rc)
4272                 goto out;
4273
4274         /* Disable all the settings related to Flow control Auto-negotiation */
4275         reg &= ~IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4276         reg &= ~IXGBE_M88E1500_COPPER_AN_PAUSE;
4277
4278         /* Configure the Asymmetric and symmetric pause according to the user
4279          * requested mode.
4280          */
4281         switch (hw->fc.requested_mode) {
4282         case ixgbe_fc_full:
4283                 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4284                 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4285                 break;
4286         case ixgbe_fc_rx_pause:
4287                 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4288                 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4289                 break;
4290         case ixgbe_fc_tx_pause:
4291                 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4292                 break;
4293         default:
4294                 break;
4295         }
4296
4297         /* Write back to the Auto-Negotiation register with newly configured
4298          * fields
4299          */
4300         hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_AN,
4301                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4302
4303         /* In this section of the code we restart Auto-negotiation */
4304
4305         /* Read the CONTROL register, Page 0 reg 0 */
4306         rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4307                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg);
4308         if (rc)
4309                 goto out;
4310
4311         /* Set the bit to restart Auto-Neg. The bit to enable Auto-neg is ON
4312          * by default
4313          */
4314         reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
4315
4316         /* write the new values to the register to restart Auto-Negotiation */
4317         hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4318                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4319
4320 out:
4321         return rc;
4322 }
4323
4324 /**
4325  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4326  *  @hw: pointer to hardware structure
4327  *
4328  *  Called at init time to set up flow control.
4329  **/
4330 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4331 {
4332         s32 status = IXGBE_SUCCESS;
4333         u32 an_cntl = 0;
4334
4335         DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4336
4337         /* Validate the requested mode */
4338         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4339                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4340                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4341                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4342         }
4343
4344         if (hw->fc.requested_mode == ixgbe_fc_default)
4345                 hw->fc.requested_mode = ixgbe_fc_full;
4346
4347         /* Set up the 1G and 10G flow control advertisement registers so the
4348          * HW will be able to do FC autoneg once the cable is plugged in.  If
4349          * we link at 10G, the 1G advertisement is harmless and vice versa.
4350          */
4351         status = hw->mac.ops.read_iosf_sb_reg(hw,
4352                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4353                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4354
4355         if (status != IXGBE_SUCCESS) {
4356                 DEBUGOUT("Auto-Negotiation did not complete\n");
4357                 return status;
4358         }
4359
4360         /* The possible values of fc.requested_mode are:
4361          * 0: Flow control is completely disabled
4362          * 1: Rx flow control is enabled (we can receive pause frames,
4363          *    but not send pause frames).
4364          * 2: Tx flow control is enabled (we can send pause frames but
4365          *    we do not support receiving pause frames).
4366          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4367          * other: Invalid.
4368          */
4369         switch (hw->fc.requested_mode) {
4370         case ixgbe_fc_none:
4371                 /* Flow control completely disabled by software override. */
4372                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4373                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4374                 break;
4375         case ixgbe_fc_tx_pause:
4376                 /* Tx Flow control is enabled, and Rx Flow control is
4377                  * disabled by software override.
4378                  */
4379                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4380                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4381                 break;
4382         case ixgbe_fc_rx_pause:
4383                 /* Rx Flow control is enabled and Tx Flow control is
4384                  * disabled by software override. Since there really
4385                  * isn't a way to advertise that we are capable of RX
4386                  * Pause ONLY, we will advertise that we support both
4387                  * symmetric and asymmetric Rx PAUSE, as such we fall
4388                  * through to the fc_full statement.  Later, we will
4389                  * disable the adapter's ability to send PAUSE frames.
4390                  */
4391         case ixgbe_fc_full:
4392                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4393                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4394                            IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4395                 break;
4396         default:
4397                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4398                               "Flow control param set incorrectly\n");
4399                 return IXGBE_ERR_CONFIG;
4400         }
4401
4402         status = hw->mac.ops.write_iosf_sb_reg(hw,
4403                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4404                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4405
4406         /* Restart auto-negotiation. */
4407         status = ixgbe_restart_an_internal_phy_x550em(hw);
4408
4409         return status;
4410 }
4411
4412 /**
4413  * ixgbe_set_mux - Set mux for port 1 access with CS4227
4414  * @hw: pointer to hardware structure
4415  * @state: set mux if 1, clear if 0
4416  */
4417 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4418 {
4419         u32 esdp;
4420
4421         if (!hw->bus.lan_id)
4422                 return;
4423         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4424         if (state)
4425                 esdp |= IXGBE_ESDP_SDP1;
4426         else
4427                 esdp &= ~IXGBE_ESDP_SDP1;
4428         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4429         IXGBE_WRITE_FLUSH(hw);
4430 }
4431
4432 /**
4433  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4434  *  @hw: pointer to hardware structure
4435  *  @mask: Mask to specify which semaphore to acquire
4436  *
4437  *  Acquires the SWFW semaphore and sets the I2C MUX
4438  **/
4439 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4440 {
4441         s32 status;
4442
4443         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4444
4445         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4446         if (status)
4447                 return status;
4448
4449         if (mask & IXGBE_GSSR_I2C_MASK)
4450                 ixgbe_set_mux(hw, 1);
4451
4452         return IXGBE_SUCCESS;
4453 }
4454
4455 /**
4456  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4457  *  @hw: pointer to hardware structure
4458  *  @mask: Mask to specify which semaphore to release
4459  *
4460  *  Releases the SWFW semaphore and sets the I2C MUX
4461  **/
4462 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4463 {
4464         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4465
4466         if (mask & IXGBE_GSSR_I2C_MASK)
4467                 ixgbe_set_mux(hw, 0);
4468
4469         ixgbe_release_swfw_sync_X540(hw, mask);
4470 }
4471
4472 /**
4473  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4474  *  @hw: pointer to hardware structure
4475  *  @mask: Mask to specify which semaphore to acquire
4476  *
4477  *  Acquires the SWFW semaphore and get the shared phy token as needed
4478  */
4479 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4480 {
4481         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4482         int retries = FW_PHY_TOKEN_RETRIES;
4483         s32 status = IXGBE_SUCCESS;
4484
4485         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4486
4487         while (--retries) {
4488                 status = IXGBE_SUCCESS;
4489                 if (hmask)
4490                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4491                 if (status)
4492                         return status;
4493                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4494                         return IXGBE_SUCCESS;
4495
4496                 status = ixgbe_get_phy_token(hw);
4497                 if (status == IXGBE_SUCCESS)
4498                         return IXGBE_SUCCESS;
4499
4500                 if (hmask)
4501                         ixgbe_release_swfw_sync_X540(hw, hmask);
4502                 if (status != IXGBE_ERR_TOKEN_RETRY)
4503                         return status;
4504         }
4505
4506         return status;
4507 }
4508
4509 /**
4510  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4511  *  @hw: pointer to hardware structure
4512  *  @mask: Mask to specify which semaphore to release
4513  *
4514  *  Releases the SWFW semaphore and puts the shared phy token as needed
4515  */
4516 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4517 {
4518         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4519
4520         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4521
4522         if (mask & IXGBE_GSSR_TOKEN_SM)
4523                 ixgbe_put_phy_token(hw);
4524
4525         if (hmask)
4526                 ixgbe_release_swfw_sync_X540(hw, hmask);
4527 }
4528
4529 /**
4530  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4531  *  @hw: pointer to hardware structure
4532  *  @reg_addr: 32 bit address of PHY register to read
4533  *  @phy_data: Pointer to read data from PHY register
4534  *
4535  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4536  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4537  *  instances.
4538  **/
4539 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4540                                u32 device_type, u16 *phy_data)
4541 {
4542         s32 status;
4543         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4544
4545         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4546
4547         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4548                 return IXGBE_ERR_SWFW_SYNC;
4549
4550         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4551
4552         hw->mac.ops.release_swfw_sync(hw, mask);
4553
4554         return status;
4555 }
4556
4557 /**
4558  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4559  *  @hw: pointer to hardware structure
4560  *  @reg_addr: 32 bit PHY register to write
4561  *  @device_type: 5 bit device type
4562  *  @phy_data: Data to write to the PHY register
4563  *
4564  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4565  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4566  **/
4567 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4568                                 u32 device_type, u16 phy_data)
4569 {
4570         s32 status;
4571         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4572
4573         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4574
4575         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4576                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4577                                                  phy_data);
4578                 hw->mac.ops.release_swfw_sync(hw, mask);
4579         } else {
4580                 status = IXGBE_ERR_SWFW_SYNC;
4581         }
4582
4583         return status;
4584 }
4585
4586 /**
4587  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4588  * @hw: pointer to hardware structure
4589  *
4590  * Handle external Base T PHY interrupt. If high temperature
4591  * failure alarm then return error, else if link status change
4592  * then setup internal/external PHY link
4593  *
4594  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4595  * failure alarm, else return PHY access status.
4596  */
4597 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4598 {
4599         bool lsc;
4600         u32 status;
4601
4602         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4603
4604         if (status != IXGBE_SUCCESS)
4605                 return status;
4606
4607         if (lsc)
4608                 return ixgbe_setup_internal_phy(hw);
4609
4610         return IXGBE_SUCCESS;
4611 }
4612
4613 /**
4614  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4615  * @hw: pointer to hardware structure
4616  * @speed: new link speed
4617  * @autoneg_wait_to_complete: true when waiting for completion is needed
4618  *
4619  * Setup internal/external PHY link speed based on link speed, then set
4620  * external PHY auto advertised link speed.
4621  *
4622  * Returns error status for any failure
4623  **/
4624 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4625                                   ixgbe_link_speed speed,
4626                                   bool autoneg_wait_to_complete)
4627 {
4628         s32 status;
4629         ixgbe_link_speed force_speed;
4630
4631         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4632
4633         /* Setup internal/external PHY link speed to iXFI (10G), unless
4634          * only 1G is auto advertised then setup KX link.
4635          */
4636         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4637                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4638         else
4639                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4640
4641         /* If internal link mode is XFI, then setup XFI internal link. */
4642         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4643                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4644
4645                 if (status != IXGBE_SUCCESS)
4646                         return status;
4647         }
4648
4649         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4650 }
4651
4652 /**
4653  * ixgbe_check_link_t_X550em - Determine link and speed status
4654  * @hw: pointer to hardware structure
4655  * @speed: pointer to link speed
4656  * @link_up: true when link is up
4657  * @link_up_wait_to_complete: bool used to wait for link up or not
4658  *
4659  * Check that both the MAC and X557 external PHY have link.
4660  **/
4661 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4662                               bool *link_up, bool link_up_wait_to_complete)
4663 {
4664         u32 status;
4665         u16 i, autoneg_status = 0;
4666
4667         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4668                 return IXGBE_ERR_CONFIG;
4669
4670         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4671                                               link_up_wait_to_complete);
4672
4673         /* If check link fails or MAC link is not up, then return */
4674         if (status != IXGBE_SUCCESS || !(*link_up))
4675                 return status;
4676
4677         /* MAC link is up, so check external PHY link.
4678          * X557 PHY. Link status is latching low, and can only be used to detect
4679          * link drop, and not the current status of the link without performing
4680          * back-to-back reads.
4681          */
4682         for (i = 0; i < 2; i++) {
4683                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4684                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4685                                               &autoneg_status);
4686
4687                 if (status != IXGBE_SUCCESS)
4688                         return status;
4689         }
4690
4691         /* If external PHY link is not up, then indicate link not up */
4692         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4693                 *link_up = false;
4694
4695         return IXGBE_SUCCESS;
4696 }
4697
4698 /**
4699  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4700  *  @hw: pointer to hardware structure
4701  **/
4702 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4703 {
4704         s32 status;
4705
4706         status = ixgbe_reset_phy_generic(hw);
4707
4708         if (status != IXGBE_SUCCESS)
4709                 return status;
4710
4711         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4712         return ixgbe_enable_lasi_ext_t_x550em(hw);
4713 }
4714
4715 /**
4716  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4717  *  @hw: pointer to hardware structure
4718  *  @led_idx: led number to turn on
4719  **/
4720 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4721 {
4722         u16 phy_data;
4723
4724         DEBUGFUNC("ixgbe_led_on_t_X550em");
4725
4726         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4727                 return IXGBE_ERR_PARAM;
4728
4729         /* To turn on the LED, set mode to ON. */
4730         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4731                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4732         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4733         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4734                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4735
4736         return IXGBE_SUCCESS;
4737 }
4738
4739 /**
4740  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4741  *  @hw: pointer to hardware structure
4742  *  @led_idx: led number to turn off
4743  **/
4744 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4745 {
4746         u16 phy_data;
4747
4748         DEBUGFUNC("ixgbe_led_off_t_X550em");
4749
4750         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4751                 return IXGBE_ERR_PARAM;
4752
4753         /* To turn on the LED, set mode to ON. */
4754         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4755                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4756         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4757         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4758                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4759
4760         return IXGBE_SUCCESS;
4761 }
4762
4763 /**
4764  *  ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
4765  *  @hw: pointer to the HW structure
4766  *  @maj: driver version major number
4767  *  @min: driver version minor number
4768  *  @build: driver version build number
4769  *  @sub: driver version sub build number
4770  *  @len: length of driver_ver string
4771  *  @driver_ver: driver string
4772  *
4773  *  Sends driver version number to firmware through the manageability
4774  *  block.  On success return IXGBE_SUCCESS
4775  *  else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4776  *  semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4777  **/
4778 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
4779                               u8 build, u8 sub, u16 len, const char *driver_ver)
4780 {
4781         struct ixgbe_hic_drv_info2 fw_cmd;
4782         s32 ret_val = IXGBE_SUCCESS;
4783         int i;
4784
4785         DEBUGFUNC("ixgbe_set_fw_drv_ver_x550");
4786
4787         if ((len == 0) || (driver_ver == NULL) ||
4788            (len > sizeof(fw_cmd.driver_string)))
4789                 return IXGBE_ERR_INVALID_ARGUMENT;
4790
4791         fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4792         fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
4793         fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4794         fw_cmd.port_num = (u8)hw->bus.func;
4795         fw_cmd.ver_maj = maj;
4796         fw_cmd.ver_min = min;
4797         fw_cmd.ver_build = build;
4798         fw_cmd.ver_sub = sub;
4799         fw_cmd.hdr.checksum = 0;
4800         memcpy(fw_cmd.driver_string, driver_ver, len);
4801         fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4802                                 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4803
4804         for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4805                 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4806                                                        sizeof(fw_cmd),
4807                                                        IXGBE_HI_COMMAND_TIMEOUT,
4808                                                        true);
4809                 if (ret_val != IXGBE_SUCCESS)
4810                         continue;
4811
4812                 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4813                     FW_CEM_RESP_STATUS_SUCCESS)
4814                         ret_val = IXGBE_SUCCESS;
4815                 else
4816                         ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4817
4818                 break;
4819         }
4820
4821         return ret_val;
4822 }