1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
43 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
44 * @hw: pointer to hardware structure
46 * Initialize the function pointers and assign the MAC type for X550.
47 * Does not touch the hardware.
49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
51 struct ixgbe_mac_info *mac = &hw->mac;
52 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
55 DEBUGFUNC("ixgbe_init_ops_X550");
57 ret_val = ixgbe_init_ops_X540(hw);
58 mac->ops.dmac_config = ixgbe_dmac_config_X550;
59 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
60 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
61 mac->ops.setup_eee = ixgbe_setup_eee_X550;
62 mac->ops.set_source_address_pruning =
63 ixgbe_set_source_address_pruning_X550;
64 mac->ops.set_ethertype_anti_spoofing =
65 ixgbe_set_ethertype_anti_spoofing_X550;
67 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
68 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
69 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
70 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
71 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
72 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
73 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
74 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
75 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
77 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
78 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
79 mac->ops.mdd_event = ixgbe_mdd_event_X550;
80 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
81 mac->ops.disable_rx = ixgbe_disable_rx_x550;
86 * ixgbe_read_cs4227 - Read CS4227 register
87 * @hw: pointer to hardware structure
88 * @reg: register number to write
89 * @value: pointer to receive value read
93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
95 return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
99 * ixgbe_write_cs4227 - Write CS4227 register
100 * @hw: pointer to hardware structure
101 * @reg: register number to write
102 * @value: value to write to register
104 * Returns status code
106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
108 return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
112 * ixgbe_get_cs4227_status - Return CS4227 status
113 * @hw: pointer to hardware structure
115 * Returns error if CS4227 not successfully initialized
117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
123 for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
124 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
126 if (status != IXGBE_SUCCESS)
128 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
130 msec_delay(IXGBE_CS4227_CHECK_DELAY);
132 if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
133 return IXGBE_ERR_PHY;
135 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
136 IXGBE_CS4227_SCRATCH_VALUE);
137 if (status != IXGBE_SUCCESS)
139 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
140 if (status != IXGBE_SUCCESS)
142 if (value != IXGBE_CS4227_SCRATCH_VALUE)
143 return IXGBE_ERR_PHY;
144 return IXGBE_SUCCESS;
148 * ixgbe_read_pe - Read register from port expander
149 * @hw: pointer to hardware structure
150 * @reg: register number to read
151 * @value: pointer to receive read value
153 * Returns status code
155 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
159 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
160 if (status != IXGBE_SUCCESS)
161 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
162 "port expander access failed with %d\n", status);
167 * ixgbe_write_pe - Write register to port expander
168 * @hw: pointer to hardware structure
169 * @reg: register number to write
170 * @value: value to write
172 * Returns status code
174 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
178 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
179 if (status != IXGBE_SUCCESS)
180 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
181 "port expander access failed with %d\n", status);
186 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
187 * @hw: pointer to hardware structure
191 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
196 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
197 if (status != IXGBE_SUCCESS)
199 reg |= IXGBE_PE_BIT1;
200 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
201 if (status != IXGBE_SUCCESS)
204 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
205 if (status != IXGBE_SUCCESS)
207 reg &= ~IXGBE_PE_BIT1;
208 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
209 if (status != IXGBE_SUCCESS)
212 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
213 if (status != IXGBE_SUCCESS)
215 reg &= ~IXGBE_PE_BIT1;
216 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
217 if (status != IXGBE_SUCCESS)
220 usec_delay(IXGBE_CS4227_RESET_HOLD);
222 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
223 if (status != IXGBE_SUCCESS)
225 reg |= IXGBE_PE_BIT1;
226 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
227 if (status != IXGBE_SUCCESS)
230 msec_delay(IXGBE_CS4227_RESET_DELAY);
232 return IXGBE_SUCCESS;
236 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
237 * @hw: pointer to hardware structure
239 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
241 u32 swfw_mask = hw->phy.phy_semaphore_mask;
245 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
246 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
247 if (status != IXGBE_SUCCESS) {
248 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
249 "semaphore failed with %d\n", status);
252 status = ixgbe_get_cs4227_status(hw);
253 if (status == IXGBE_SUCCESS) {
254 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
255 msec_delay(hw->eeprom.semaphore_delay);
258 ixgbe_reset_cs4227(hw);
259 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
260 msec_delay(hw->eeprom.semaphore_delay);
262 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
263 "Unable to initialize CS4227, err=%d\n", status);
267 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
268 * @hw: pointer to hardware structure
270 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
272 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
274 if (hw->bus.lan_id) {
275 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
276 esdp |= IXGBE_ESDP_SDP1_DIR;
278 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
279 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
280 IXGBE_WRITE_FLUSH(hw);
284 * ixgbe_identify_phy_x550em - Get PHY type based on device id
285 * @hw: pointer to hardware structure
289 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
291 switch (hw->device_id) {
292 case IXGBE_DEV_ID_X550EM_X_SFP:
293 /* set up for CS4227 usage */
294 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
295 ixgbe_setup_mux_ctl(hw);
296 ixgbe_check_cs4227(hw);
298 return ixgbe_identify_module_generic(hw);
300 case IXGBE_DEV_ID_X550EM_X_KX4:
301 hw->phy.type = ixgbe_phy_x550em_kx4;
303 case IXGBE_DEV_ID_X550EM_X_KR:
304 hw->phy.type = ixgbe_phy_x550em_kr;
306 case IXGBE_DEV_ID_X550EM_X_1G_T:
307 case IXGBE_DEV_ID_X550EM_X_10G_T:
308 return ixgbe_identify_phy_generic(hw);
312 return IXGBE_SUCCESS;
315 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
316 u32 device_type, u16 *phy_data)
318 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
319 return IXGBE_NOT_IMPLEMENTED;
322 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
323 u32 device_type, u16 phy_data)
325 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
326 return IXGBE_NOT_IMPLEMENTED;
330 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
331 * @hw: pointer to hardware structure
333 * Initialize the function pointers and for MAC type X550EM.
334 * Does not touch the hardware.
336 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
338 struct ixgbe_mac_info *mac = &hw->mac;
339 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
340 struct ixgbe_phy_info *phy = &hw->phy;
343 DEBUGFUNC("ixgbe_init_ops_X550EM");
345 /* Similar to X550 so start there. */
346 ret_val = ixgbe_init_ops_X550(hw);
348 /* Since this function eventually calls
349 * ixgbe_init_ops_540 by design, we are setting
350 * the pointers to NULL explicitly here to overwrite
351 * the values being set in the x540 function.
353 /* Thermal sensor not supported in x550EM */
354 mac->ops.get_thermal_sensor_data = NULL;
355 mac->ops.init_thermal_sensor_thresh = NULL;
356 mac->thermal_sensor_enabled = false;
358 /* FCOE not supported in x550EM */
359 mac->ops.get_san_mac_addr = NULL;
360 mac->ops.set_san_mac_addr = NULL;
361 mac->ops.get_wwn_prefix = NULL;
362 mac->ops.get_fcoe_boot_status = NULL;
364 /* IPsec not supported in x550EM */
365 mac->ops.disable_sec_rx_path = NULL;
366 mac->ops.enable_sec_rx_path = NULL;
368 /* AUTOC register is not present in x550EM. */
369 mac->ops.prot_autoc_read = NULL;
370 mac->ops.prot_autoc_write = NULL;
372 /* X550EM bus type is internal*/
373 hw->bus.type = ixgbe_bus_type_internal;
374 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
376 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
377 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
378 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
379 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
380 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
381 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
382 mac->ops.get_supported_physical_layer =
383 ixgbe_get_supported_physical_layer_X550em;
385 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
386 mac->ops.setup_fc = ixgbe_setup_fc_generic;
388 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
390 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
391 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
393 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
394 mac->ops.setup_eee = NULL;
397 phy->ops.init = ixgbe_init_phy_ops_X550em;
398 phy->ops.identify = ixgbe_identify_phy_x550em;
399 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
400 phy->ops.set_phy_power = NULL;
404 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
405 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
406 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
407 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
408 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
409 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
410 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
411 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
417 * ixgbe_dmac_config_X550
418 * @hw: pointer to hardware structure
420 * Configure DMA coalescing. If enabling dmac, dmac is activated.
421 * When disabling dmac, dmac enable dmac bit is cleared.
423 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
425 u32 reg, high_pri_tc;
427 DEBUGFUNC("ixgbe_dmac_config_X550");
429 /* Disable DMA coalescing before configuring */
430 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
431 reg &= ~IXGBE_DMACR_DMAC_EN;
432 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
434 /* Disable DMA Coalescing if the watchdog timer is 0 */
435 if (!hw->mac.dmac_config.watchdog_timer)
438 ixgbe_dmac_config_tcs_X550(hw);
440 /* Configure DMA Coalescing Control Register */
441 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
443 /* Set the watchdog timer in units of 40.96 usec */
444 reg &= ~IXGBE_DMACR_DMACWT_MASK;
445 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
447 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
448 /* If fcoe is enabled, set high priority traffic class */
449 if (hw->mac.dmac_config.fcoe_en) {
450 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
451 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
452 IXGBE_DMACR_HIGH_PRI_TC_MASK);
454 reg |= IXGBE_DMACR_EN_MNG_IND;
456 /* Enable DMA coalescing after configuration */
457 reg |= IXGBE_DMACR_DMAC_EN;
458 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
461 return IXGBE_SUCCESS;
465 * ixgbe_dmac_config_tcs_X550
466 * @hw: pointer to hardware structure
468 * Configure DMA coalescing threshold per TC. The dmac enable bit must
469 * be cleared before configuring.
471 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
473 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
475 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
477 /* Configure DMA coalescing enabled */
478 switch (hw->mac.dmac_config.link_speed) {
479 case IXGBE_LINK_SPEED_100_FULL:
480 pb_headroom = IXGBE_DMACRXT_100M;
482 case IXGBE_LINK_SPEED_1GB_FULL:
483 pb_headroom = IXGBE_DMACRXT_1G;
486 pb_headroom = IXGBE_DMACRXT_10G;
490 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
491 IXGBE_MHADD_MFS_SHIFT) / 1024);
493 /* Set the per Rx packet buffer receive threshold */
494 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
495 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
496 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
498 if (tc < hw->mac.dmac_config.num_tcs) {
500 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
501 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
502 IXGBE_RXPBSIZE_SHIFT;
504 /* Calculate receive buffer threshold in kilobytes */
505 if (rx_pb_size > pb_headroom)
506 rx_pb_size = rx_pb_size - pb_headroom;
510 /* Minimum of MFS shall be set for DMCTH */
511 reg |= (rx_pb_size > maxframe_size_kb) ?
512 rx_pb_size : maxframe_size_kb;
514 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
516 return IXGBE_SUCCESS;
520 * ixgbe_dmac_update_tcs_X550
521 * @hw: pointer to hardware structure
523 * Disables dmac, updates per TC settings, and then enables dmac.
525 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
529 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
531 /* Disable DMA coalescing before configuring */
532 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
533 reg &= ~IXGBE_DMACR_DMAC_EN;
534 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
536 ixgbe_dmac_config_tcs_X550(hw);
538 /* Enable DMA coalescing after configuration */
539 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
540 reg |= IXGBE_DMACR_DMAC_EN;
541 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
543 return IXGBE_SUCCESS;
547 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
548 * @hw: pointer to hardware structure
550 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
551 * ixgbe_hw struct in order to set up EEPROM access.
553 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
555 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
559 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
561 if (eeprom->type == ixgbe_eeprom_uninitialized) {
562 eeprom->semaphore_delay = 10;
563 eeprom->type = ixgbe_flash;
565 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
566 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
567 IXGBE_EEC_SIZE_SHIFT);
568 eeprom->word_size = 1 << (eeprom_size +
569 IXGBE_EEPROM_WORD_SIZE_SHIFT);
571 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
572 eeprom->type, eeprom->word_size);
575 return IXGBE_SUCCESS;
579 * ixgbe_setup_eee_X550 - Enable/disable EEE support
580 * @hw: pointer to the HW structure
581 * @enable_eee: boolean flag to enable EEE
583 * Enable/disable EEE based on enable_eee flag.
584 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
588 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
595 DEBUGFUNC("ixgbe_setup_eee_X550");
597 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
598 /* Enable or disable EEE per flag */
600 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
602 if (hw->device_id == IXGBE_DEV_ID_X550T) {
603 /* Advertise EEE capability */
604 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
605 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
607 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
608 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
609 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
611 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
612 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
613 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
614 status = ixgbe_read_iosf_sb_reg_x550(hw,
615 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
616 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
617 if (status != IXGBE_SUCCESS)
620 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
621 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
623 status = ixgbe_write_iosf_sb_reg_x550(hw,
624 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
625 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
626 if (status != IXGBE_SUCCESS)
630 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
632 if (hw->device_id == IXGBE_DEV_ID_X550T) {
633 /* Disable advertised EEE capability */
634 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
635 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
637 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
638 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
639 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
641 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
642 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
643 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
644 status = ixgbe_read_iosf_sb_reg_x550(hw,
645 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
646 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
647 if (status != IXGBE_SUCCESS)
650 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
651 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
653 status = ixgbe_write_iosf_sb_reg_x550(hw,
654 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
655 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
656 if (status != IXGBE_SUCCESS)
660 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
662 return IXGBE_SUCCESS;
666 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
667 * @hw: pointer to hardware structure
668 * @enable: enable or disable source address pruning
669 * @pool: Rx pool to set source address pruning for
671 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
676 /* max rx pool is 63 */
680 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
681 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
684 pfflp |= (1ULL << pool);
686 pfflp &= ~(1ULL << pool);
688 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
689 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
693 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
694 * @hw: pointer to hardware structure
695 * @enable: enable or disable switch for Ethertype anti-spoofing
696 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
699 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
702 int vf_target_reg = vf >> 3;
703 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
706 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
708 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
710 pfvfspoof |= (1 << vf_target_shift);
712 pfvfspoof &= ~(1 << vf_target_shift);
714 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
718 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
720 * @hw: pointer to hardware structure
721 * @reg_addr: 32 bit PHY register to write
722 * @device_type: 3 bit device type
723 * @data: Data to write to the register
725 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
726 u32 device_type, u32 data)
728 u32 i, command, error;
730 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
731 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
733 /* Write IOSF control register */
734 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
736 /* Write IOSF data register */
737 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
739 * Check every 10 usec to see if the address cycle completed.
740 * The SB IOSF BUSY bit will clear when the operation is
743 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
746 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
747 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
751 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
752 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
753 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
754 ERROR_REPORT2(IXGBE_ERROR_POLLING,
755 "Failed to write, error %x\n", error);
756 return IXGBE_ERR_PHY;
759 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
760 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
761 return IXGBE_ERR_PHY;
764 return IXGBE_SUCCESS;
768 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
770 * @hw: pointer to hardware structure
771 * @reg_addr: 32 bit PHY register to write
772 * @device_type: 3 bit device type
773 * @phy_data: Pointer to read data from the register
775 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
776 u32 device_type, u32 *data)
778 u32 i, command, error;
780 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
781 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
783 /* Write IOSF control register */
784 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
787 * Check every 10 usec to see if the address cycle completed.
788 * The SB IOSF BUSY bit will clear when the operation is
791 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
794 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
795 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
799 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
800 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
801 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
802 ERROR_REPORT2(IXGBE_ERROR_POLLING,
803 "Failed to read, error %x\n", error);
804 return IXGBE_ERR_PHY;
807 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
808 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
809 return IXGBE_ERR_PHY;
812 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
814 return IXGBE_SUCCESS;
818 * ixgbe_disable_mdd_X550
819 * @hw: pointer to hardware structure
821 * Disable malicious driver detection
823 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
827 DEBUGFUNC("ixgbe_disable_mdd_X550");
829 /* Disable MDD for TX DMA and interrupt */
830 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
831 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
832 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
834 /* Disable MDD for RX and interrupt */
835 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
836 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
837 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
841 * ixgbe_enable_mdd_X550
842 * @hw: pointer to hardware structure
844 * Enable malicious driver detection
846 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
850 DEBUGFUNC("ixgbe_enable_mdd_X550");
852 /* Enable MDD for TX DMA and interrupt */
853 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
854 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
855 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
857 /* Enable MDD for RX and interrupt */
858 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
859 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
860 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
864 * ixgbe_restore_mdd_vf_X550
865 * @hw: pointer to hardware structure
868 * Restore VF that was disabled during malicious driver detection event
870 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
872 u32 idx, reg, num_qs, start_q, bitmask;
874 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
876 /* Map VF to queues */
877 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
878 switch (reg & IXGBE_MRQC_MRQE_MASK) {
879 case IXGBE_MRQC_VMDQRT8TCEN:
880 num_qs = 8; /* 16 VFs / pools */
881 bitmask = 0x000000FF;
883 case IXGBE_MRQC_VMDQRSS32EN:
884 case IXGBE_MRQC_VMDQRT4TCEN:
885 num_qs = 4; /* 32 VFs / pools */
886 bitmask = 0x0000000F;
888 default: /* 64 VFs / pools */
890 bitmask = 0x00000003;
893 start_q = vf * num_qs;
895 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
898 reg |= (bitmask << (start_q % 32));
899 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
900 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
904 * ixgbe_mdd_event_X550
905 * @hw: pointer to hardware structure
906 * @vf_bitmap: vf bitmap of malicious vfs
908 * Handle malicious driver detection event.
910 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
913 u32 i, j, reg, q, shift, vf, idx;
915 DEBUGFUNC("ixgbe_mdd_event_X550");
917 /* figure out pool size for mapping to vf's */
918 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
919 switch (reg & IXGBE_MRQC_MRQE_MASK) {
920 case IXGBE_MRQC_VMDQRT8TCEN:
921 shift = 3; /* 16 VFs / pools */
923 case IXGBE_MRQC_VMDQRSS32EN:
924 case IXGBE_MRQC_VMDQRT4TCEN:
925 shift = 2; /* 32 VFs / pools */
928 shift = 1; /* 64 VFs / pools */
932 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
933 for (i = 0; i < 4; i++) {
934 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
935 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
940 /* Get malicious queue */
941 for (j = 0; j < 32 && wqbr; j++) {
943 if (!(wqbr & (1 << j)))
946 /* Get queue from bitmask */
949 /* Map queue to vf */
952 /* Set vf bit in vf_bitmap */
954 vf_bitmap[idx] |= (1 << (vf % 32));
961 * ixgbe_get_media_type_X550em - Get media type
962 * @hw: pointer to hardware structure
964 * Returns the media type (fiber, copper, backplane)
966 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
968 enum ixgbe_media_type media_type;
970 DEBUGFUNC("ixgbe_get_media_type_X550em");
972 /* Detect if there is a copper PHY attached. */
973 switch (hw->device_id) {
974 case IXGBE_DEV_ID_X550EM_X_KR:
975 case IXGBE_DEV_ID_X550EM_X_KX4:
976 media_type = ixgbe_media_type_backplane;
978 case IXGBE_DEV_ID_X550EM_X_SFP:
979 media_type = ixgbe_media_type_fiber;
981 case IXGBE_DEV_ID_X550EM_X_1G_T:
982 case IXGBE_DEV_ID_X550EM_X_10G_T:
983 media_type = ixgbe_media_type_copper;
986 media_type = ixgbe_media_type_unknown;
993 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
994 * @hw: pointer to hardware structure
995 * @linear: true if SFP module is linear
997 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
999 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1001 switch (hw->phy.sfp_type) {
1002 case ixgbe_sfp_type_not_present:
1003 return IXGBE_ERR_SFP_NOT_PRESENT;
1004 case ixgbe_sfp_type_da_cu_core0:
1005 case ixgbe_sfp_type_da_cu_core1:
1008 case ixgbe_sfp_type_srlr_core0:
1009 case ixgbe_sfp_type_srlr_core1:
1010 case ixgbe_sfp_type_da_act_lmt_core0:
1011 case ixgbe_sfp_type_da_act_lmt_core1:
1012 case ixgbe_sfp_type_1g_sx_core0:
1013 case ixgbe_sfp_type_1g_sx_core1:
1014 case ixgbe_sfp_type_1g_lx_core0:
1015 case ixgbe_sfp_type_1g_lx_core1:
1018 case ixgbe_sfp_type_unknown:
1019 case ixgbe_sfp_type_1g_cu_core0:
1020 case ixgbe_sfp_type_1g_cu_core1:
1022 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1025 return IXGBE_SUCCESS;
1029 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1030 * @hw: pointer to hardware structure
1032 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1034 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1039 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1041 status = ixgbe_identify_module_generic(hw);
1043 if (status != IXGBE_SUCCESS)
1046 /* Check if SFP module is supported */
1047 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1053 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1054 * @hw: pointer to hardware structure
1056 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1061 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1063 /* Check if SFP module is supported */
1064 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1066 if (status != IXGBE_SUCCESS)
1069 ixgbe_init_mac_link_ops_X550em(hw);
1070 hw->phy.ops.reset = NULL;
1072 return IXGBE_SUCCESS;
1076 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1077 * @hw: pointer to hardware structure
1079 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1081 struct ixgbe_mac_info *mac = &hw->mac;
1083 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1085 switch (hw->mac.ops.get_media_type(hw)) {
1086 case ixgbe_media_type_fiber:
1087 /* CS4227 does not support autoneg, so disable the laser control
1088 * functions for SFP+ fiber
1090 mac->ops.disable_tx_laser = NULL;
1091 mac->ops.enable_tx_laser = NULL;
1092 mac->ops.flap_tx_laser = NULL;
1093 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1094 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1095 mac->ops.set_rate_select_speed =
1096 ixgbe_set_soft_rate_select_speed;
1098 case ixgbe_media_type_copper:
1099 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1100 mac->ops.check_link = ixgbe_check_link_t_X550em;
1108 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1109 * @hw: pointer to hardware structure
1110 * @speed: pointer to link speed
1111 * @autoneg: true when autoneg or autotry is enabled
1113 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1114 ixgbe_link_speed *speed,
1117 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1120 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1122 /* CS4227 SFP must not enable auto-negotiation */
1125 /* Check if 1G SFP module. */
1126 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1127 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1128 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1129 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1130 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1131 return IXGBE_SUCCESS;
1134 /* Link capabilities are based on SFP */
1135 if (hw->phy.multispeed_fiber)
1136 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1137 IXGBE_LINK_SPEED_1GB_FULL;
1139 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1141 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1142 IXGBE_LINK_SPEED_1GB_FULL;
1146 return IXGBE_SUCCESS;
1150 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1151 * @hw: pointer to hardware structure
1152 * @lsc: pointer to boolean flag which indicates whether external Base T
1153 * PHY interrupt is lsc
1155 * Determime if external Base T PHY interrupt cause is high temperature
1156 * failure alarm or link status change.
1158 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1159 * failure alarm, else return PHY access status.
1161 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1168 /* Vendor alarm triggered */
1169 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1170 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1173 if (status != IXGBE_SUCCESS ||
1174 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1177 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1178 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1179 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1182 if (status != IXGBE_SUCCESS ||
1183 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1184 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1187 /* High temperature failure alarm triggered */
1188 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1189 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1192 if (status != IXGBE_SUCCESS)
1195 /* If high temperature failure, then return over temp error and exit */
1196 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1197 /* power down the PHY in case the PHY FW didn't already */
1198 ixgbe_set_copper_phy_power(hw, false);
1199 return IXGBE_ERR_OVERTEMP;
1202 /* Vendor alarm 2 triggered */
1203 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1204 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1206 if (status != IXGBE_SUCCESS ||
1207 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1210 /* link connect/disconnect event occurred */
1211 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1212 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1214 if (status != IXGBE_SUCCESS)
1218 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1221 return IXGBE_SUCCESS;
1225 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1226 * @hw: pointer to hardware structure
1228 * Enable link status change and temperature failure alarm for the external
1231 * Returns PHY access status
1233 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1239 /* Clear interrupt flags */
1240 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1242 /* Enable link status change alarm */
1243 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1244 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1246 if (status != IXGBE_SUCCESS)
1249 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1251 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1252 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1254 if (status != IXGBE_SUCCESS)
1257 /* Enables high temperature failure alarm */
1258 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1259 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1262 if (status != IXGBE_SUCCESS)
1265 reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1267 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1268 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1271 if (status != IXGBE_SUCCESS)
1274 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1275 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1276 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1279 if (status != IXGBE_SUCCESS)
1282 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1283 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1285 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1286 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1289 if (status != IXGBE_SUCCESS)
1292 /* Enable chip-wide vendor alarm */
1293 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1294 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1297 if (status != IXGBE_SUCCESS)
1300 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1302 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1303 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1310 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1311 * @hw: pointer to hardware structure
1313 * Initialize any function pointers that were not able to be
1314 * set during init_shared_code because the PHY/SFP type was
1315 * not known. Perform the SFP init if necessary.
1317 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1319 struct ixgbe_phy_info *phy = &hw->phy;
1322 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1324 hw->mac.ops.set_lan_id(hw);
1326 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1327 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1328 ixgbe_setup_mux_ctl(hw);
1330 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1333 /* Identify the PHY or SFP module */
1334 ret_val = phy->ops.identify(hw);
1335 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1338 /* Setup function pointers based on detected hardware */
1339 ixgbe_init_mac_link_ops_X550em(hw);
1340 if (phy->sfp_type != ixgbe_sfp_type_unknown)
1341 phy->ops.reset = NULL;
1343 /* Set functions pointers based on phy type */
1344 switch (hw->phy.type) {
1345 case ixgbe_phy_x550em_kx4:
1346 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1347 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1348 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1350 case ixgbe_phy_x550em_kr:
1351 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1352 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1353 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1355 case ixgbe_phy_x550em_ext_t:
1356 phy->ops.setup_internal_link =
1357 ixgbe_setup_internal_phy_t_x550em;
1358 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1359 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1360 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1369 * ixgbe_reset_hw_X550em - Perform hardware reset
1370 * @hw: pointer to hardware structure
1372 * Resets the hardware by resetting the transmit and receive units, masks
1373 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1376 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1378 ixgbe_link_speed link_speed;
1382 bool link_up = false;
1384 DEBUGFUNC("ixgbe_reset_hw_X550em");
1386 /* Call adapter stop to disable Tx/Rx and clear interrupts */
1387 status = hw->mac.ops.stop_adapter(hw);
1388 if (status != IXGBE_SUCCESS)
1391 /* flush pending Tx transactions */
1392 ixgbe_clear_tx_pending(hw);
1394 /* PHY ops must be identified and initialized prior to reset */
1396 /* Identify PHY and related function pointers */
1397 status = hw->phy.ops.init(hw);
1399 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1402 /* start the external PHY */
1403 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1404 status = ixgbe_init_ext_t_x550em(hw);
1409 /* Setup SFP module if there is one present. */
1410 if (hw->phy.sfp_setup_needed) {
1411 status = hw->mac.ops.setup_sfp(hw);
1412 hw->phy.sfp_setup_needed = false;
1415 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1419 if (!hw->phy.reset_disable && hw->phy.ops.reset)
1420 hw->phy.ops.reset(hw);
1423 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
1424 * If link reset is used when link is up, it might reset the PHY when
1425 * mng is using it. If link is down or the flag to force full link
1426 * reset is set, then perform link reset.
1428 ctrl = IXGBE_CTRL_LNK_RST;
1429 if (!hw->force_full_reset) {
1430 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1432 ctrl = IXGBE_CTRL_RST;
1435 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1436 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1437 IXGBE_WRITE_FLUSH(hw);
1439 /* Poll for reset bit to self-clear meaning reset is complete */
1440 for (i = 0; i < 10; i++) {
1442 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1443 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1447 if (ctrl & IXGBE_CTRL_RST_MASK) {
1448 status = IXGBE_ERR_RESET_FAILED;
1449 DEBUGOUT("Reset polling failed to complete.\n");
1454 /* Double resets are required for recovery from certain error
1455 * conditions. Between resets, it is necessary to stall to
1456 * allow time for any pending HW events to complete.
1458 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1459 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1463 /* Store the permanent mac address */
1464 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1466 /* Store MAC address from RAR0, clear receive address registers, and
1467 * clear the multicast table. Also reset num_rar_entries to 128,
1468 * since we modify this value when programming the SAN MAC address.
1470 hw->mac.num_rar_entries = 128;
1471 hw->mac.ops.init_rx_addrs(hw);
1474 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1475 ixgbe_setup_mux_ctl(hw);
1481 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1482 * @hw: pointer to hardware structure
1484 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1489 status = hw->phy.ops.read_reg(hw,
1490 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1491 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1494 if (status != IXGBE_SUCCESS)
1497 /* If PHY FW reset completed bit is set then this is the first
1498 * SW instance after a power on so the PHY FW must be un-stalled.
1500 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1501 status = hw->phy.ops.read_reg(hw,
1502 IXGBE_MDIO_GLOBAL_RES_PR_10,
1503 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1506 if (status != IXGBE_SUCCESS)
1509 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1511 status = hw->phy.ops.write_reg(hw,
1512 IXGBE_MDIO_GLOBAL_RES_PR_10,
1513 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1516 if (status != IXGBE_SUCCESS)
1524 * ixgbe_setup_kr_x550em - Configure the KR PHY.
1525 * @hw: pointer to hardware structure
1527 * Configures the integrated KR PHY.
1529 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1534 status = ixgbe_read_iosf_sb_reg_x550(hw,
1535 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1536 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1540 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1541 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1542 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1543 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1544 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1546 /* Advertise 10G support. */
1547 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1548 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1550 /* Advertise 1G support. */
1551 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1552 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1554 /* Restart auto-negotiation. */
1555 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1556 status = ixgbe_write_iosf_sb_reg_x550(hw,
1557 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1558 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1564 * ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1565 * @hw: pointer to hardware structure
1567 * Configures the integrated KX4 PHY.
1569 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1574 status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1575 IXGBE_SB_IOSF_TARGET_KX4_PCS, ®_val);
1579 reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1580 IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1582 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1584 /* Advertise 10G support. */
1585 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1586 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1588 /* Advertise 1G support. */
1589 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1590 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1592 /* Restart auto-negotiation. */
1593 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1594 status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1595 IXGBE_SB_IOSF_TARGET_KX4_PCS, reg_val);
1601 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1602 * @hw: pointer to hardware structure
1603 * @speed: the link speed to force
1605 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1606 * internal and external PHY at a specific speed, without autonegotiation.
1608 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1613 /* Disable AN and force speed to 10G Serial. */
1614 status = ixgbe_read_iosf_sb_reg_x550(hw,
1615 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1616 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1617 if (status != IXGBE_SUCCESS)
1620 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1621 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1623 /* Select forced link speed for internal PHY. */
1625 case IXGBE_LINK_SPEED_10GB_FULL:
1626 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1628 case IXGBE_LINK_SPEED_1GB_FULL:
1629 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1632 /* Other link speeds are not supported by internal KR PHY. */
1633 return IXGBE_ERR_LINK_SETUP;
1636 status = ixgbe_write_iosf_sb_reg_x550(hw,
1637 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1638 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1639 if (status != IXGBE_SUCCESS)
1642 /* Disable training protocol FSM. */
1643 status = ixgbe_read_iosf_sb_reg_x550(hw,
1644 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1645 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1646 if (status != IXGBE_SUCCESS)
1648 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1649 status = ixgbe_write_iosf_sb_reg_x550(hw,
1650 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1651 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1652 if (status != IXGBE_SUCCESS)
1655 /* Disable Flex from training TXFFE. */
1656 status = ixgbe_read_iosf_sb_reg_x550(hw,
1657 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1658 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1659 if (status != IXGBE_SUCCESS)
1661 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1662 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1663 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1664 status = ixgbe_write_iosf_sb_reg_x550(hw,
1665 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1666 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1667 if (status != IXGBE_SUCCESS)
1669 status = ixgbe_read_iosf_sb_reg_x550(hw,
1670 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1671 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1672 if (status != IXGBE_SUCCESS)
1674 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1675 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1676 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1677 status = ixgbe_write_iosf_sb_reg_x550(hw,
1678 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1679 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1680 if (status != IXGBE_SUCCESS)
1683 /* Enable override for coefficients. */
1684 status = ixgbe_read_iosf_sb_reg_x550(hw,
1685 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1686 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1687 if (status != IXGBE_SUCCESS)
1689 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1690 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1691 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1692 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1693 status = ixgbe_write_iosf_sb_reg_x550(hw,
1694 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1695 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1696 if (status != IXGBE_SUCCESS)
1699 /* Toggle port SW reset by AN reset. */
1700 status = ixgbe_read_iosf_sb_reg_x550(hw,
1701 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1702 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1703 if (status != IXGBE_SUCCESS)
1705 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1706 status = ixgbe_write_iosf_sb_reg_x550(hw,
1707 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1708 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1714 * ixgbe_setup_mac_link_sfp_x550em - Configure the CS4227 & KR PHY for SFP
1715 * @hw: pointer to hardware structure
1717 * Configure the external CS4227 PHY and the integrated KR PHY for SFP support.
1719 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1720 ixgbe_link_speed speed,
1721 bool autoneg_wait_to_complete)
1724 u16 reg_slice, reg_val;
1725 bool setup_linear = false;
1726 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1728 /* Check if SFP module is supported and linear */
1729 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1731 /* If no SFP module present, then return success. Return success since
1732 * there is no reason to configure CS4227 and SFP not present error is
1733 * not excepted in the setup MAC link flow.
1735 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1736 return IXGBE_SUCCESS;
1738 if (ret_val != IXGBE_SUCCESS)
1741 /* Configure CS4227 for connection rate. */
1742 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1743 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1744 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1747 /* Configure CS4227 for connection type. */
1748 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1750 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1752 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1753 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1756 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1757 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1758 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1761 /* Configure CS4227 for connection type. */
1762 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1764 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1766 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1767 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1770 /* Configure the internal PHY. */
1771 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1777 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1778 * @hw: point to hardware structure
1780 * Configures the link between the integrated KR PHY and the external X557 PHY
1781 * The driver will call this function when it gets a link status change
1782 * interrupt from the X557 PHY. This function configures the link speed
1783 * between the PHYs to match the link speed of the BASE-T link.
1785 * A return of a non-zero value indicates an error, and the base driver should
1786 * not report link up.
1788 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1791 u16 autoneg_status, speed;
1792 ixgbe_link_speed force_speed;
1794 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1795 return IXGBE_ERR_CONFIG;
1797 /* read this twice back to back to indicate current status */
1798 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1799 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1801 if (status != IXGBE_SUCCESS)
1804 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1805 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1807 if (status != IXGBE_SUCCESS)
1810 /* If link is not up, then there is no setup necessary so return */
1811 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1812 return IXGBE_SUCCESS;
1814 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1815 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1818 /* clear everything but the speed and duplex bits */
1819 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1822 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1823 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1825 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1826 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1829 /* Internal PHY does not support anything else */
1830 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1833 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1837 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1838 * @hw: pointer to hardware structure
1840 * Configures the integrated KR PHY to use internal loopback mode.
1842 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1847 /* Disable AN and force speed to 10G Serial. */
1848 status = ixgbe_read_iosf_sb_reg_x550(hw,
1849 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1850 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1851 if (status != IXGBE_SUCCESS)
1853 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1854 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1855 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1856 status = ixgbe_write_iosf_sb_reg_x550(hw,
1857 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1858 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1859 if (status != IXGBE_SUCCESS)
1862 /* Set near-end loopback clocks. */
1863 status = ixgbe_read_iosf_sb_reg_x550(hw,
1864 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1865 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1866 if (status != IXGBE_SUCCESS)
1868 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1869 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1870 status = ixgbe_write_iosf_sb_reg_x550(hw,
1871 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1872 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1873 if (status != IXGBE_SUCCESS)
1876 /* Set loopback enable. */
1877 status = ixgbe_read_iosf_sb_reg_x550(hw,
1878 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1879 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1880 if (status != IXGBE_SUCCESS)
1882 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1883 status = ixgbe_write_iosf_sb_reg_x550(hw,
1884 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1885 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1886 if (status != IXGBE_SUCCESS)
1889 /* Training bypass. */
1890 status = ixgbe_read_iosf_sb_reg_x550(hw,
1891 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1892 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1893 if (status != IXGBE_SUCCESS)
1895 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1896 status = ixgbe_write_iosf_sb_reg_x550(hw,
1897 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1898 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1904 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1905 * assuming that the semaphore is already obtained.
1906 * @hw: pointer to hardware structure
1907 * @offset: offset of word in the EEPROM to read
1908 * @data: word read from the EEPROM
1910 * Reads a 16 bit word from the EEPROM using the hostif.
1912 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1916 struct ixgbe_hic_read_shadow_ram buffer;
1918 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1919 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1920 buffer.hdr.req.buf_lenh = 0;
1921 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1922 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1924 /* convert offset from words to bytes */
1925 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1927 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1929 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1931 IXGBE_HI_COMMAND_TIMEOUT, false);
1936 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1937 FW_NVM_DATA_OFFSET);
1943 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1944 * @hw: pointer to hardware structure
1945 * @offset: offset of word in the EEPROM to read
1946 * @data: word read from the EEPROM
1948 * Reads a 16 bit word from the EEPROM using the hostif.
1950 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1953 s32 status = IXGBE_SUCCESS;
1955 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1957 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1959 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1960 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1962 status = IXGBE_ERR_SWFW_SYNC;
1969 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1970 * @hw: pointer to hardware structure
1971 * @offset: offset of word in the EEPROM to read
1972 * @words: number of words
1973 * @data: word(s) read from the EEPROM
1975 * Reads a 16 bit word(s) from the EEPROM using the hostif.
1977 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1978 u16 offset, u16 words, u16 *data)
1980 struct ixgbe_hic_read_shadow_ram buffer;
1981 u32 current_word = 0;
1986 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1988 /* Take semaphore for the entire operation. */
1989 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1991 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1995 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1996 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1998 words_to_read = words;
2000 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2001 buffer.hdr.req.buf_lenh = 0;
2002 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2003 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2005 /* convert offset from words to bytes */
2006 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2007 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2009 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2011 IXGBE_HI_COMMAND_TIMEOUT,
2015 DEBUGOUT("Host interface command failed\n");
2019 for (i = 0; i < words_to_read; i++) {
2020 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2022 u32 value = IXGBE_READ_REG(hw, reg);
2024 data[current_word] = (u16)(value & 0xffff);
2027 if (i < words_to_read) {
2029 data[current_word] = (u16)(value & 0xffff);
2033 words -= words_to_read;
2037 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2042 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2043 * @hw: pointer to hardware structure
2044 * @offset: offset of word in the EEPROM to write
2045 * @data: word write to the EEPROM
2047 * Write a 16 bit word to the EEPROM using the hostif.
2049 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2053 struct ixgbe_hic_write_shadow_ram buffer;
2055 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2057 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2058 buffer.hdr.req.buf_lenh = 0;
2059 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2060 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2063 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2065 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2067 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2069 IXGBE_HI_COMMAND_TIMEOUT, false);
2075 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2076 * @hw: pointer to hardware structure
2077 * @offset: offset of word in the EEPROM to write
2078 * @data: word write to the EEPROM
2080 * Write a 16 bit word to the EEPROM using the hostif.
2082 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2085 s32 status = IXGBE_SUCCESS;
2087 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2089 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2091 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2092 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2094 DEBUGOUT("write ee hostif failed to get semaphore");
2095 status = IXGBE_ERR_SWFW_SYNC;
2102 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2103 * @hw: pointer to hardware structure
2104 * @offset: offset of word in the EEPROM to write
2105 * @words: number of words
2106 * @data: word(s) write to the EEPROM
2108 * Write a 16 bit word(s) to the EEPROM using the hostif.
2110 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2111 u16 offset, u16 words, u16 *data)
2113 s32 status = IXGBE_SUCCESS;
2116 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2118 /* Take semaphore for the entire operation. */
2119 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2120 if (status != IXGBE_SUCCESS) {
2121 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2125 for (i = 0; i < words; i++) {
2126 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2129 if (status != IXGBE_SUCCESS) {
2130 DEBUGOUT("Eeprom buffered write failed\n");
2135 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2142 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2143 * @hw: pointer to hardware structure
2144 * @ptr: pointer offset in eeprom
2145 * @size: size of section pointed by ptr, if 0 first word will be used as size
2146 * @csum: address of checksum to update
2148 * Returns error status for any failure
2150 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2151 u16 size, u16 *csum, u16 *buffer,
2156 u16 length, bufsz, i, start;
2159 bufsz = sizeof(buf) / sizeof(buf[0]);
2161 /* Read a chunk at the pointer location */
2163 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2165 DEBUGOUT("Failed to read EEPROM image\n");
2170 if (buffer_size < ptr)
2171 return IXGBE_ERR_PARAM;
2172 local_buffer = &buffer[ptr];
2180 length = local_buffer[0];
2182 /* Skip pointer section if length is invalid. */
2183 if (length == 0xFFFF || length == 0 ||
2184 (ptr + length) >= hw->eeprom.word_size)
2185 return IXGBE_SUCCESS;
2188 if (buffer && ((u32)start + (u32)length > buffer_size))
2189 return IXGBE_ERR_PARAM;
2191 for (i = start; length; i++, length--) {
2192 if (i == bufsz && !buffer) {
2198 /* Read a chunk at the pointer location */
2199 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2202 DEBUGOUT("Failed to read EEPROM image\n");
2206 *csum += local_buffer[i];
2208 return IXGBE_SUCCESS;
2212 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2213 * @hw: pointer to hardware structure
2214 * @buffer: pointer to buffer containing calculated checksum
2215 * @buffer_size: size of buffer
2217 * Returns a negative error code on error, or the 16-bit checksum
2219 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2221 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2225 u16 pointer, i, size;
2227 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2229 hw->eeprom.ops.init_params(hw);
2232 /* Read pointer area */
2233 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2234 IXGBE_EEPROM_LAST_WORD + 1,
2237 DEBUGOUT("Failed to read EEPROM image\n");
2240 local_buffer = eeprom_ptrs;
2242 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2243 return IXGBE_ERR_PARAM;
2244 local_buffer = buffer;
2248 * For X550 hardware include 0x0-0x41 in the checksum, skip the
2249 * checksum word itself
2251 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2252 if (i != IXGBE_EEPROM_CHECKSUM)
2253 checksum += local_buffer[i];
2256 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
2257 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2259 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2260 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2263 pointer = local_buffer[i];
2265 /* Skip pointer section if the pointer is invalid. */
2266 if (pointer == 0xFFFF || pointer == 0 ||
2267 pointer >= hw->eeprom.word_size)
2271 case IXGBE_PCIE_GENERAL_PTR:
2272 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2274 case IXGBE_PCIE_CONFIG0_PTR:
2275 case IXGBE_PCIE_CONFIG1_PTR:
2276 size = IXGBE_PCIE_CONFIG_SIZE;
2283 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2284 buffer, buffer_size);
2289 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2291 return (s32)checksum;
2295 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2296 * @hw: pointer to hardware structure
2298 * Returns a negative error code on error, or the 16-bit checksum
2300 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2302 return ixgbe_calc_checksum_X550(hw, NULL, 0);
2306 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2307 * @hw: pointer to hardware structure
2308 * @checksum_val: calculated checksum
2310 * Performs checksum calculation and validates the EEPROM checksum. If the
2311 * caller does not need checksum_val, the value can be NULL.
2313 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2317 u16 read_checksum = 0;
2319 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2321 /* Read the first word from the EEPROM. If this times out or fails, do
2322 * not continue or we could be in for a very long wait while every
2325 status = hw->eeprom.ops.read(hw, 0, &checksum);
2327 DEBUGOUT("EEPROM read failed\n");
2331 status = hw->eeprom.ops.calc_checksum(hw);
2335 checksum = (u16)(status & 0xffff);
2337 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2342 /* Verify read checksum from EEPROM is the same as
2343 * calculated checksum
2345 if (read_checksum != checksum) {
2346 status = IXGBE_ERR_EEPROM_CHECKSUM;
2347 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2348 "Invalid EEPROM checksum");
2351 /* If the user cares, return the calculated checksum */
2353 *checksum_val = checksum;
2359 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2360 * @hw: pointer to hardware structure
2362 * After writing EEPROM to shadow RAM using EEWR register, software calculates
2363 * checksum and updates the EEPROM and instructs the hardware to update
2366 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2371 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2373 /* Read the first word from the EEPROM. If this times out or fails, do
2374 * not continue or we could be in for a very long wait while every
2377 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2379 DEBUGOUT("EEPROM read failed\n");
2383 status = ixgbe_calc_eeprom_checksum_X550(hw);
2387 checksum = (u16)(status & 0xffff);
2389 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2394 status = ixgbe_update_flash_X550(hw);
2400 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2401 * @hw: pointer to hardware structure
2403 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2405 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2407 s32 status = IXGBE_SUCCESS;
2408 union ixgbe_hic_hdr2 buffer;
2410 DEBUGFUNC("ixgbe_update_flash_X550");
2412 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2413 buffer.req.buf_lenh = 0;
2414 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2415 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2417 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2419 IXGBE_HI_COMMAND_TIMEOUT, false);
2425 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2426 * @hw: pointer to hardware structure
2428 * Determines physical layer capabilities of the current configuration.
2430 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2432 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2433 u16 ext_ability = 0;
2435 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2437 hw->phy.ops.identify(hw);
2439 switch (hw->phy.type) {
2440 case ixgbe_phy_x550em_kr:
2441 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2442 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2444 case ixgbe_phy_x550em_kx4:
2445 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2446 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2448 case ixgbe_phy_x550em_ext_t:
2449 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2450 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2452 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2453 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2454 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2455 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2461 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2462 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2464 return physical_layer;
2468 * ixgbe_get_bus_info_x550em - Set PCI bus info
2469 * @hw: pointer to hardware structure
2471 * Sets bus link width and speed to unknown because X550em is
2474 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2477 DEBUGFUNC("ixgbe_get_bus_info_x550em");
2479 hw->bus.width = ixgbe_bus_width_unknown;
2480 hw->bus.speed = ixgbe_bus_speed_unknown;
2482 hw->mac.ops.set_lan_id(hw);
2484 return IXGBE_SUCCESS;
2488 * ixgbe_disable_rx_x550 - Disable RX unit
2490 * Enables the Rx DMA unit for x550
2492 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2494 u32 rxctrl, pfdtxgswc;
2496 struct ixgbe_hic_disable_rxen fw_cmd;
2498 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2500 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2501 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2502 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2503 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2504 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2505 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2506 hw->mac.set_lben = true;
2508 hw->mac.set_lben = false;
2511 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2512 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2513 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2514 fw_cmd.port_number = (u8)hw->bus.lan_id;
2516 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2517 sizeof(struct ixgbe_hic_disable_rxen),
2518 IXGBE_HI_COMMAND_TIMEOUT, true);
2520 /* If we fail - disable RX using register write */
2522 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2523 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2524 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2525 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2532 * ixgbe_enter_lplu_x550em - Transition to low power states
2533 * @hw: pointer to hardware structure
2535 * Configures Low Power Link Up on transition to low power states
2536 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2537 * X557 PHY immediately prior to entering LPLU.
2539 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2541 u16 autoneg_status, an_10g_cntl_reg, autoneg_reg, speed;
2543 ixgbe_link_speed lcd_speed;
2546 /* If blocked by MNG FW, then don't restart AN */
2547 if (ixgbe_check_reset_blocked(hw))
2548 return IXGBE_SUCCESS;
2550 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2551 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2554 if (status != IXGBE_SUCCESS)
2557 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2559 if (status != IXGBE_SUCCESS)
2562 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2563 * disabled, then force link down by entering low power mode.
2565 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS) ||
2566 !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2567 !(hw->wol_enabled || ixgbe_mng_present(hw)))
2568 return ixgbe_set_copper_phy_power(hw, FALSE);
2571 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2573 if (status != IXGBE_SUCCESS)
2576 /* If no valid LCD link speed, then force link down and exit. */
2577 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2578 return ixgbe_set_copper_phy_power(hw, FALSE);
2580 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2581 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2584 if (status != IXGBE_SUCCESS)
2587 /* clear everything but the speed bits */
2588 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2590 /* If current speed is already LCD, then exit. */
2591 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2592 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2593 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2594 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2597 /* Clear AN completed indication */
2598 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2599 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2602 if (status != IXGBE_SUCCESS)
2605 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2606 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2609 if (status != IXGBE_SUCCESS)
2612 status = hw->phy.ops.read_reg(hw,
2613 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2614 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2617 if (status != IXGBE_SUCCESS)
2620 save_autoneg = hw->phy.autoneg_advertised;
2622 /* Setup link at least common link speed */
2623 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2625 /* restore autoneg from before setting lplu speed */
2626 hw->phy.autoneg_advertised = save_autoneg;
2632 * ixgbe_get_lcd_x550em - Determine lowest common denominator
2633 * @hw: pointer to hardware structure
2634 * @lcd_speed: pointer to lowest common link speed
2636 * Determine lowest common link speed with link partner.
2638 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2642 u16 word = hw->eeprom.ctrl_word_3;
2644 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2646 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2647 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2650 if (status != IXGBE_SUCCESS)
2653 /* If link partner advertised 1G, return 1G */
2654 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2655 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2659 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2660 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2661 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2664 /* Link partner not capable of lower speeds, return 10G */
2665 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2670 * ixgbe_setup_fc_X550em - Set up flow control
2671 * @hw: pointer to hardware structure
2673 * Called at init time to set up flow control.
2675 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2677 s32 ret_val = IXGBE_SUCCESS;
2678 u32 pause, asm_dir, reg_val;
2680 DEBUGFUNC("ixgbe_setup_fc_X550em");
2682 /* Validate the requested mode */
2683 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2684 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2685 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2686 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2690 /* 10gig parts do not have a word in the EEPROM to determine the
2691 * default flow control setting, so we explicitly set it to full.
2693 if (hw->fc.requested_mode == ixgbe_fc_default)
2694 hw->fc.requested_mode = ixgbe_fc_full;
2696 /* Determine PAUSE and ASM_DIR bits. */
2697 switch (hw->fc.requested_mode) {
2702 case ixgbe_fc_tx_pause:
2706 case ixgbe_fc_rx_pause:
2707 /* Rx Flow control is enabled and Tx Flow control is
2708 * disabled by software override. Since there really
2709 * isn't a way to advertise that we are capable of RX
2710 * Pause ONLY, we will advertise that we support both
2711 * symmetric and asymmetric Rx PAUSE, as such we fall
2712 * through to the fc_full statement. Later, we will
2713 * disable the adapter's ability to send PAUSE frames.
2720 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2721 "Flow control param set incorrectly\n");
2722 ret_val = IXGBE_ERR_CONFIG;
2726 if (hw->phy.media_type == ixgbe_media_type_backplane) {
2727 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2728 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2729 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2730 if (ret_val != IXGBE_SUCCESS)
2732 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2733 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2735 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2737 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2738 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2739 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2740 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2742 /* Not all devices fully support AN. */
2743 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR)
2744 hw->fc.disable_fc_autoneg = true;
2752 * ixgbe_set_mux - Set mux for port 1 access with CS4227
2753 * @hw: pointer to hardware structure
2754 * @state: set mux if 1, clear if 0
2756 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2760 if (!hw->bus.lan_id)
2762 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2764 esdp |= IXGBE_ESDP_SDP1;
2766 esdp &= ~IXGBE_ESDP_SDP1;
2767 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2768 IXGBE_WRITE_FLUSH(hw);
2772 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2773 * @hw: pointer to hardware structure
2774 * @mask: Mask to specify which semaphore to acquire
2776 * Acquires the SWFW semaphore and sets the I2C MUX
2778 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2782 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2784 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2788 if (mask & IXGBE_GSSR_I2C_MASK)
2789 ixgbe_set_mux(hw, 1);
2791 return IXGBE_SUCCESS;
2795 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2796 * @hw: pointer to hardware structure
2797 * @mask: Mask to specify which semaphore to release
2799 * Releases the SWFW semaphore and sets the I2C MUX
2801 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2803 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2805 if (mask & IXGBE_GSSR_I2C_MASK)
2806 ixgbe_set_mux(hw, 0);
2808 ixgbe_release_swfw_sync_X540(hw, mask);
2812 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2813 * @hw: pointer to hardware structure
2815 * Handle external Base T PHY interrupt. If high temperature
2816 * failure alarm then return error, else if link status change
2817 * then setup internal/external PHY link
2819 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2820 * failure alarm, else return PHY access status.
2822 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2827 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2829 if (status != IXGBE_SUCCESS)
2833 return ixgbe_setup_internal_phy_t_x550em(hw);
2835 return IXGBE_SUCCESS;
2839 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
2840 * @hw: pointer to hardware structure
2841 * @speed: new link speed
2842 * @autoneg_wait_to_complete: true when waiting for completion is needed
2844 * Setup internal/external PHY link speed based on link speed, then set
2845 * external PHY auto advertised link speed.
2847 * Returns error status for any failure
2849 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
2850 ixgbe_link_speed speed,
2851 bool autoneg_wait_to_complete)
2854 ixgbe_link_speed force_speed;
2856 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
2858 /* Setup internal/external PHY link speed to iXFI (10G), unless
2859 * only 1G is auto advertised then setup KX link.
2861 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2862 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2864 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2866 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
2868 if (status != IXGBE_SUCCESS)
2871 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
2875 * ixgbe_check_link_t_X550em - Determine link and speed status
2876 * @hw: pointer to hardware structure
2877 * @speed: pointer to link speed
2878 * @link_up: true when link is up
2879 * @link_up_wait_to_complete: bool used to wait for link up or not
2881 * Check that both the MAC and X557 external PHY have link.
2883 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
2884 bool *link_up, bool link_up_wait_to_complete)
2889 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2890 return IXGBE_ERR_CONFIG;
2892 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
2893 link_up_wait_to_complete);
2895 /* If check link fails or MAC link is not up, then return */
2896 if (status != IXGBE_SUCCESS || !(*link_up))
2899 /* MAC link is up, so check external PHY link.
2900 * Read this twice back to back to indicate current status.
2902 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2903 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2906 if (status != IXGBE_SUCCESS)
2909 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2910 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2913 if (status != IXGBE_SUCCESS)
2916 /* If external PHY link is not up, then indicate link not up */
2917 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
2920 return IXGBE_SUCCESS;
2924 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2925 * @hw: pointer to hardware structure
2927 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2931 status = ixgbe_reset_phy_generic(hw);
2933 if (status != IXGBE_SUCCESS)
2936 /* Configure Link Status Alarm and Temperature Threshold interrupts */
2937 return ixgbe_enable_lasi_ext_t_x550em(hw);