drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42
  43 /**
  44  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  45  *  @hw: pointer to hardware structure
  46  *
  47  *  Initialize the function pointers and assign the MAC type for X550.
  48  *  Does not touch the hardware.
  49  **/
  50 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  51 {
  52         struct ixgbe_mac_info *mac = &hw->mac;
  53         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  54         s32 ret_val;
  55
  56         DEBUGFUNC("ixgbe_init_ops_X550");
  57
  58         ret_val = ixgbe_init_ops_X540(hw);
  59         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  60         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  61         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  62         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  63         mac->ops.set_source_address_pruning =
  64                         ixgbe_set_source_address_pruning_X550;
  65         mac->ops.set_ethertype_anti_spoofing =
  66                         ixgbe_set_ethertype_anti_spoofing_X550;
  67
  68         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  69         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  70         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  71         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  72         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  73         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  74         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  75         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  76         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  77
  78         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  79         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  80         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  81         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  82         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  83         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
  84                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  85                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  86         }
  87         return ret_val;
  88 }
  89
  90 /**
  91  * ixgbe_read_cs4227 - Read CS4227 register
  92  * @hw: pointer to hardware structure
  93  * @reg: register number to write
  94  * @value: pointer to receive value read
  95  *
  96  * Returns status code
  97  **/
  98 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  99 {
 100         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 101 }
 102
 103 /**
 104  * ixgbe_write_cs4227 - Write CS4227 register
 105  * @hw: pointer to hardware structure
 106  * @reg: register number to write
 107  * @value: value to write to register
 108  *
 109  * Returns status code
 110  **/
 111 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 112 {
 113         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 114 }
 115
 116 /**
 117  * ixgbe_get_cs4227_status - Return CS4227 status
 118  * @hw: pointer to hardware structure
 119  *
 120  * Performs a diagnostic on the CS4227 chip. Returns an error if it is
 121  * not operating correctly.
 122  * This function assumes that the caller has acquired the proper semaphore.
 123  **/
 124 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
 125 {
 126         s32 status;
 127         u16 value = 0;
 128         u16 reg_slice, reg_val;
 129         u8 retry;
 130
 131         /* Check register reads. */
 132         for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
 133                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
 134                                            &value);
 135                 if (status != IXGBE_SUCCESS)
 136                         return status;
 137                 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
 138                         break;
 139                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 140         }
 141         if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
 142                 return IXGBE_ERR_PHY;
 143
 144         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 145         if (status != IXGBE_SUCCESS)
 146                 return status;
 147
 148         /* If this is the first time after power-on, check the ucode.
 149          * Otherwise, this will disrupt link on all ports. Because we
 150          * can only do this the first time, we must check all ports,
 151          * not just our own.
 152          * While we are at it, set the LINE side to 10G SR, which is
 153          * what it needs to be regardless of the actual link.
 154          */
 155         if (value != IXGBE_CS4227_SCRATCH_VALUE) {
 156                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB;
 157                 reg_val = IXGBE_CS4227_SPEED_10G;
 158                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 159                 if (status != IXGBE_SUCCESS)
 160                         return status;
 161
 162                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB;
 163                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
 164                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 165                 if (status != IXGBE_SUCCESS)
 166                         return status;
 167
 168                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB;
 169                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
 170                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 171                 if (status != IXGBE_SUCCESS)
 172                         return status;
 173
 174                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (1 << 12);
 175                 reg_val = IXGBE_CS4227_SPEED_10G;
 176                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 177                 if (status != IXGBE_SUCCESS)
 178                         return status;
 179
 180                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12);
 181                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
 182                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 183                 if (status != IXGBE_SUCCESS)
 184                         return status;
 185
 186                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12);
 187                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
 188                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 189                 if (status != IXGBE_SUCCESS)
 190                         return status;
 191
 192                 msec_delay(10);
 193         }
 194
 195         /* Verify that the ucode is operational on all ports. */
 196         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB;
 197         reg_val = 0xFFFF;
 198         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 199         if (status != IXGBE_SUCCESS)
 200                 return status;
 201         if (reg_val != 0)
 202                 return IXGBE_ERR_PHY;
 203
 204         reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB;
 205         reg_val = 0xFFFF;
 206         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 207         if (status != IXGBE_SUCCESS)
 208                 return status;
 209         if (reg_val != 0)
 210                 return IXGBE_ERR_PHY;
 211
 212         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12);
 213         reg_val = 0xFFFF;
 214         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 215         if (status != IXGBE_SUCCESS)
 216                 return status;
 217         if (reg_val != 0)
 218                 return IXGBE_ERR_PHY;
 219
 220         reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12);
 221         reg_val = 0xFFFF;
 222         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 223         if (status != IXGBE_SUCCESS)
 224                 return status;
 225         if (reg_val != 0)
 226                 return IXGBE_ERR_PHY;
 227
 228         /* Set scratch indicating that the diagnostic was successful. */
 229         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 230                                     IXGBE_CS4227_SCRATCH_VALUE);
 231         if (status != IXGBE_SUCCESS)
 232                 return status;
 233         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 234         if (status != IXGBE_SUCCESS)
 235                 return status;
 236         if (value != IXGBE_CS4227_SCRATCH_VALUE)
 237                 return IXGBE_ERR_PHY;
 238
 239         return IXGBE_SUCCESS;
 240 }
 241
 242 /**
 243  * ixgbe_read_pe - Read register from port expander
 244  * @hw: pointer to hardware structure
 245  * @reg: register number to read
 246  * @value: pointer to receive read value
 247  *
 248  * Returns status code
 249  **/
 250 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 251 {
 252         s32 status;
 253
 254         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 255         if (status != IXGBE_SUCCESS)
 256                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 257                               "port expander access failed with %d\n", status);
 258         return status;
 259 }
 260
 261 /**
 262  * ixgbe_write_pe - Write register to port expander
 263  * @hw: pointer to hardware structure
 264  * @reg: register number to write
 265  * @value: value to write
 266  *
 267  * Returns status code
 268  **/
 269 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 270 {
 271         s32 status;
 272
 273         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 274         if (status != IXGBE_SUCCESS)
 275                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 276                               "port expander access failed with %d\n", status);
 277         return status;
 278 }
 279
 280 /**
 281  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 282  * @hw: pointer to hardware structure
 283  *
 284  * Returns error code
 285  **/
 286 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 287 {
 288         s32 status;
 289         u8 reg;
 290
 291         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 292         if (status != IXGBE_SUCCESS)
 293                 return status;
 294         reg |= IXGBE_PE_BIT1;
 295         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 296         if (status != IXGBE_SUCCESS)
 297                 return status;
 298
 299         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 300         if (status != IXGBE_SUCCESS)
 301                 return status;
 302         reg &= ~IXGBE_PE_BIT1;
 303         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 304         if (status != IXGBE_SUCCESS)
 305                 return status;
 306
 307         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 308         if (status != IXGBE_SUCCESS)
 309                 return status;
 310         reg &= ~IXGBE_PE_BIT1;
 311         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 312         if (status != IXGBE_SUCCESS)
 313                 return status;
 314
 315         usec_delay(IXGBE_CS4227_RESET_HOLD);
 316
 317         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 318         if (status != IXGBE_SUCCESS)
 319                 return status;
 320         reg |= IXGBE_PE_BIT1;
 321         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 322         if (status != IXGBE_SUCCESS)
 323                 return status;
 324
 325         msec_delay(IXGBE_CS4227_RESET_DELAY);
 326
 327         return IXGBE_SUCCESS;
 328 }
 329
 330 /**
 331  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 332  * @hw: pointer to hardware structure
 333  **/
 334 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 335 {
 336         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 337         s32 status;
 338         u8 retry;
 339
 340         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 341                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 342                 if (status != IXGBE_SUCCESS) {
 343                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 344                                       "semaphore failed with %d\n", status);
 345                         return;
 346                 }
 347                 status = ixgbe_get_cs4227_status(hw);
 348                 if (status == IXGBE_SUCCESS) {
 349                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 350                         msec_delay(hw->eeprom.semaphore_delay);
 351                         return;
 352                 }
 353                 ixgbe_reset_cs4227(hw);
 354                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 355                 msec_delay(hw->eeprom.semaphore_delay);
 356         }
 357         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 358                       "Unable to initialize CS4227, err=%d\n", status);
 359 }
 360
 361 /**
 362  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 363  * @hw: pointer to hardware structure
 364  **/
 365 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 366 {
 367         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 368
 369         if (hw->bus.lan_id) {
 370                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 371                 esdp |= IXGBE_ESDP_SDP1_DIR;
 372         }
 373         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 374         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 375         IXGBE_WRITE_FLUSH(hw);
 376 }
 377
 378 /**
 379  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 380  * @hw: pointer to hardware structure
 381  *
 382  * Returns error code
 383  */
 384 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 385 {
 386         switch (hw->device_id) {
 387         case IXGBE_DEV_ID_X550EM_X_SFP:
 388                 /* set up for CS4227 usage */
 389                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 390                 ixgbe_setup_mux_ctl(hw);
 391                 ixgbe_check_cs4227(hw);
 392
 393                 return ixgbe_identify_module_generic(hw);
 394                 break;
 395         case IXGBE_DEV_ID_X550EM_X_KX4:
 396                 hw->phy.type = ixgbe_phy_x550em_kx4;
 397                 break;
 398         case IXGBE_DEV_ID_X550EM_X_KR:
 399                 hw->phy.type = ixgbe_phy_x550em_kr;
 400                 break;
 401         case IXGBE_DEV_ID_X550EM_X_1G_T:
 402         case IXGBE_DEV_ID_X550EM_X_10G_T:
 403                 return ixgbe_identify_phy_generic(hw);
 404         default:
 405                 break;
 406         }
 407         return IXGBE_SUCCESS;
 408 }
 409
 410 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 411                                      u32 device_type, u16 *phy_data)
 412 {
 413         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 414         return IXGBE_NOT_IMPLEMENTED;
 415 }
 416
 417 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 418                                       u32 device_type, u16 phy_data)
 419 {
 420         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 421         return IXGBE_NOT_IMPLEMENTED;
 422 }
 423
 424 /**
 425 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 426 *  @hw: pointer to hardware structure
 427 *
 428 *  Initialize the function pointers and for MAC type X550EM.
 429 *  Does not touch the hardware.
 430 **/
 431 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 432 {
 433         struct ixgbe_mac_info *mac = &hw->mac;
 434         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 435         struct ixgbe_phy_info *phy = &hw->phy;
 436         s32 ret_val;
 437
 438         DEBUGFUNC("ixgbe_init_ops_X550EM");
 439
 440         /* Similar to X550 so start there. */
 441         ret_val = ixgbe_init_ops_X550(hw);
 442
 443         /* Since this function eventually calls
 444          * ixgbe_init_ops_540 by design, we are setting
 445          * the pointers to NULL explicitly here to overwrite
 446          * the values being set in the x540 function.
 447          */
 448         /* Thermal sensor not supported in x550EM */
 449         mac->ops.get_thermal_sensor_data = NULL;
 450         mac->ops.init_thermal_sensor_thresh = NULL;
 451         mac->thermal_sensor_enabled = false;
 452
 453         /* FCOE not supported in x550EM */
 454         mac->ops.get_san_mac_addr = NULL;
 455         mac->ops.set_san_mac_addr = NULL;
 456         mac->ops.get_wwn_prefix = NULL;
 457         mac->ops.get_fcoe_boot_status = NULL;
 458
 459         /* IPsec not supported in x550EM */
 460         mac->ops.disable_sec_rx_path = NULL;
 461         mac->ops.enable_sec_rx_path = NULL;
 462
 463         /* AUTOC register is not present in x550EM. */
 464         mac->ops.prot_autoc_read = NULL;
 465         mac->ops.prot_autoc_write = NULL;
 466
 467         /* X550EM bus type is internal*/
 468         hw->bus.type = ixgbe_bus_type_internal;
 469         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 470
 471         if (hw->mac.type == ixgbe_mac_X550EM_x) {
 472                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 473                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 474                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 475                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 476         }
 477
 478         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 479         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 480         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 481         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 482         mac->ops.get_supported_physical_layer =
 483                                     ixgbe_get_supported_physical_layer_X550em;
 484
 485         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 486                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 487         else
 488                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 489
 490
 491         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
 492                 mac->ops.setup_eee = NULL;
 493
 494         /* PHY */
 495         phy->ops.init = ixgbe_init_phy_ops_X550em;
 496         phy->ops.identify = ixgbe_identify_phy_x550em;
 497         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 498                 phy->ops.set_phy_power = NULL;
 499
 500
 501         /* EEPROM */
 502         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 503         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 504         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 505         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 506         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 507         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 508         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 509         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 510
 511         return ret_val;
 512 }
 513
 514 /**
 515  *  ixgbe_dmac_config_X550
 516  *  @hw: pointer to hardware structure
 517  *
 518  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 519  *  When disabling dmac, dmac enable dmac bit is cleared.
 520  **/
 521 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 522 {
 523         u32 reg, high_pri_tc;
 524
 525         DEBUGFUNC("ixgbe_dmac_config_X550");
 526
 527         /* Disable DMA coalescing before configuring */
 528         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 529         reg &= ~IXGBE_DMACR_DMAC_EN;
 530         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 531
 532         /* Disable DMA Coalescing if the watchdog timer is 0 */
 533         if (!hw->mac.dmac_config.watchdog_timer)
 534                 goto out;
 535
 536         ixgbe_dmac_config_tcs_X550(hw);
 537
 538         /* Configure DMA Coalescing Control Register */
 539         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 540
 541         /* Set the watchdog timer in units of 40.96 usec */
 542         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 543         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 544
 545         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 546         /* If fcoe is enabled, set high priority traffic class */
 547         if (hw->mac.dmac_config.fcoe_en) {
 548                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 549                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 550                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 551         }
 552         reg |= IXGBE_DMACR_EN_MNG_IND;
 553
 554         /* Enable DMA coalescing after configuration */
 555         reg |= IXGBE_DMACR_DMAC_EN;
 556         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 557
 558 out:
 559         return IXGBE_SUCCESS;
 560 }
 561
 562 /**
 563  *  ixgbe_dmac_config_tcs_X550
 564  *  @hw: pointer to hardware structure
 565  *
 566  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 567  *  be cleared before configuring.
 568  **/
 569 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 570 {
 571         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 572
 573         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 574
 575         /* Configure DMA coalescing enabled */
 576         switch (hw->mac.dmac_config.link_speed) {
 577         case IXGBE_LINK_SPEED_100_FULL:
 578                 pb_headroom = IXGBE_DMACRXT_100M;
 579                 break;
 580         case IXGBE_LINK_SPEED_1GB_FULL:
 581                 pb_headroom = IXGBE_DMACRXT_1G;
 582                 break;
 583         default:
 584                 pb_headroom = IXGBE_DMACRXT_10G;
 585                 break;
 586         }
 587
 588         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 589                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 590
 591         /* Set the per Rx packet buffer receive threshold */
 592         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 593                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 594                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 595
 596                 if (tc < hw->mac.dmac_config.num_tcs) {
 597                         /* Get Rx PB size */
 598                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 599                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 600                                 IXGBE_RXPBSIZE_SHIFT;
 601
 602                         /* Calculate receive buffer threshold in kilobytes */
 603                         if (rx_pb_size > pb_headroom)
 604                                 rx_pb_size = rx_pb_size - pb_headroom;
 605                         else
 606                                 rx_pb_size = 0;
 607
 608                         /* Minimum of MFS shall be set for DMCTH */
 609                         reg |= (rx_pb_size > maxframe_size_kb) ?
 610                                 rx_pb_size : maxframe_size_kb;
 611                 }
 612                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 613         }
 614         return IXGBE_SUCCESS;
 615 }
 616
 617 /**
 618  *  ixgbe_dmac_update_tcs_X550
 619  *  @hw: pointer to hardware structure
 620  *
 621  *  Disables dmac, updates per TC settings, and then enables dmac.
 622  **/
 623 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 624 {
 625         u32 reg;
 626
 627         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 628
 629         /* Disable DMA coalescing before configuring */
 630         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 631         reg &= ~IXGBE_DMACR_DMAC_EN;
 632         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 633
 634         ixgbe_dmac_config_tcs_X550(hw);
 635
 636         /* Enable DMA coalescing after configuration */
 637         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 638         reg |= IXGBE_DMACR_DMAC_EN;
 639         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 640
 641         return IXGBE_SUCCESS;
 642 }
 643
 644 /**
 645  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 646  *  @hw: pointer to hardware structure
 647  *
 648  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 649  *  ixgbe_hw struct in order to set up EEPROM access.
 650  **/
 651 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 652 {
 653         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 654         u32 eec;
 655         u16 eeprom_size;
 656
 657         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 658
 659         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 660                 eeprom->semaphore_delay = 10;
 661                 eeprom->type = ixgbe_flash;
 662
 663                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 664                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 665                                     IXGBE_EEC_SIZE_SHIFT);
 666                 eeprom->word_size = 1 << (eeprom_size +
 667                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 668
 669                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 670                           eeprom->type, eeprom->word_size);
 671         }
 672
 673         return IXGBE_SUCCESS;
 674 }
 675
 676 /**
 677  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 678  *  @hw: pointer to the HW structure
 679  *  @enable_eee: boolean flag to enable EEE
 680  *
 681  *  Enable/disable EEE based on enable_eee flag.
 682  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 683  *  are modified.
 684  *
 685  **/
 686 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 687 {
 688         u32 eeer;
 689         u16 autoneg_eee_reg;
 690         u32 link_reg;
 691         s32 status;
 692         u32 fuse;
 693
 694         DEBUGFUNC("ixgbe_setup_eee_X550");
 695
 696         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 697         /* Enable or disable EEE per flag */
 698         if (enable_eee) {
 699                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 700
 701                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 702                         /* Advertise EEE capability */
 703                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 704                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 705
 706                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 707                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 708                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 709
 710                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 711                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 712                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 713                         /* Not supported on first revision. */
 714                         fuse = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
 715                         if (!(fuse & IXGBE_FUSES0_REV1))
 716                                 return IXGBE_SUCCESS;
 717
 718                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 719                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 720                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 721                         if (status != IXGBE_SUCCESS)
 722                                 return status;
 723
 724                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 725                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 726
 727                         /* Don't advertise FEC capability when EEE enabled. */
 728                         link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 729
 730                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 731                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 732                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 733                         if (status != IXGBE_SUCCESS)
 734                                 return status;
 735                 }
 736         } else {
 737                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 738
 739                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 740                         /* Disable advertised EEE capability */
 741                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 742                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 743
 744                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 745                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 746                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 747
 748                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 749                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 750                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 751                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 752                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 753                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 754                         if (status != IXGBE_SUCCESS)
 755                                 return status;
 756
 757                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 758                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 759
 760                         /* Advertise FEC capability when EEE is disabled. */
 761                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 762
 763                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 764                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 765                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 766                         if (status != IXGBE_SUCCESS)
 767                                 return status;
 768                 }
 769         }
 770         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 771
 772         return IXGBE_SUCCESS;
 773 }
 774
 775 /**
 776  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 777  * @hw: pointer to hardware structure
 778  * @enable: enable or disable source address pruning
 779  * @pool: Rx pool to set source address pruning for
 780  **/
 781 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 782                                            unsigned int pool)
 783 {
 784         u64 pfflp;
 785
 786         /* max rx pool is 63 */
 787         if (pool > 63)
 788                 return;
 789
 790         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 791         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 792
 793         if (enable)
 794                 pfflp |= (1ULL << pool);
 795         else
 796                 pfflp &= ~(1ULL << pool);
 797
 798         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 799         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 800 }
 801
 802 /**
 803  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 804  *  @hw: pointer to hardware structure
 805  *  @enable: enable or disable switch for Ethertype anti-spoofing
 806  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 807  *
 808  **/
 809 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 810                 bool enable, int vf)
 811 {
 812         int vf_target_reg = vf >> 3;
 813         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 814         u32 pfvfspoof;
 815
 816         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 817
 818         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 819         if (enable)
 820                 pfvfspoof |= (1 << vf_target_shift);
 821         else
 822                 pfvfspoof &= ~(1 << vf_target_shift);
 823
 824         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 825 }
 826
 827 /**
 828  * ixgbe_iosf_wait - Wait for IOSF command completion
 829  * @hw: pointer to hardware structure
 830  * @ctrl: pointer to location to receive final IOSF control value
 831  *
 832  * Returns failing status on timeout
 833  *
 834  * Note: ctrl can be NULL if the IOSF control register value is not needed
 835  **/
 836 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 837 {
 838         u32 i, command = 0;
 839
 840         /* Check every 10 usec to see if the address cycle completed.
 841          * The SB IOSF BUSY bit will clear when the operation is
 842          * complete
 843          */
 844         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 845                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 846                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 847                         break;
 848                 usec_delay(10);
 849         }
 850         if (ctrl)
 851                 *ctrl = command;
 852         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 853                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
 854                 return IXGBE_ERR_PHY;
 855         }
 856
 857         return IXGBE_SUCCESS;
 858 }
 859
 860 /**
 861  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 862  *  device
 863  *  @hw: pointer to hardware structure
 864  *  @reg_addr: 32 bit PHY register to write
 865  *  @device_type: 3 bit device type
 866  *  @data: Data to write to the register
 867  **/
 868 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 869                             u32 device_type, u32 data)
 870 {
 871         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 872         u32 command, error;
 873         s32 ret;
 874
 875         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 876         if (ret != IXGBE_SUCCESS)
 877                 return ret;
 878
 879         ret = ixgbe_iosf_wait(hw, NULL);
 880         if (ret != IXGBE_SUCCESS)
 881                 goto out;
 882
 883         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 884                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 885
 886         /* Write IOSF control register */
 887         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 888
 889         /* Write IOSF data register */
 890         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 891
 892         ret = ixgbe_iosf_wait(hw, &command);
 893
 894         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 895                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 896                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 897                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 898                               "Failed to write, error %x\n", error);
 899                 ret = IXGBE_ERR_PHY;
 900         }
 901
 902 out:
 903         ixgbe_release_swfw_semaphore(hw, gssr);
 904         return ret;
 905 }
 906
 907 /**
 908  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 909  *  device
 910  *  @hw: pointer to hardware structure
 911  *  @reg_addr: 32 bit PHY register to write
 912  *  @device_type: 3 bit device type
 913  *  @phy_data: Pointer to read data from the register
 914  **/
 915 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 916                            u32 device_type, u32 *data)
 917 {
 918         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 919         u32 command, error;
 920         s32 ret;
 921
 922         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 923         if (ret != IXGBE_SUCCESS)
 924                 return ret;
 925
 926         ret = ixgbe_iosf_wait(hw, NULL);
 927         if (ret != IXGBE_SUCCESS)
 928                 goto out;
 929
 930         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 931                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 932
 933         /* Write IOSF control register */
 934         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 935
 936         ret = ixgbe_iosf_wait(hw, &command);
 937
 938         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 939                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 940                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 941                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 942                                 "Failed to read, error %x\n", error);
 943                 ret = IXGBE_ERR_PHY;
 944         }
 945
 946         if (ret == IXGBE_SUCCESS)
 947                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 948
 949 out:
 950         ixgbe_release_swfw_semaphore(hw, gssr);
 951         return ret;
 952 }
 953
 954 /**
 955  *  ixgbe_disable_mdd_X550
 956  *  @hw: pointer to hardware structure
 957  *
 958  *  Disable malicious driver detection
 959  **/
 960 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 961 {
 962         u32 reg;
 963
 964         DEBUGFUNC("ixgbe_disable_mdd_X550");
 965
 966         /* Disable MDD for TX DMA and interrupt */
 967         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 968         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 969         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 970
 971         /* Disable MDD for RX and interrupt */
 972         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 973         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 974         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 975 }
 976
 977 /**
 978  *  ixgbe_enable_mdd_X550
 979  *  @hw: pointer to hardware structure
 980  *
 981  *  Enable malicious driver detection
 982  **/
 983 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 984 {
 985         u32 reg;
 986
 987         DEBUGFUNC("ixgbe_enable_mdd_X550");
 988
 989         /* Enable MDD for TX DMA and interrupt */
 990         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 991         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 992         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 993
 994         /* Enable MDD for RX and interrupt */
 995         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 996         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 997         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 998 }
 999
1000 /**
1001  *  ixgbe_restore_mdd_vf_X550
1002  *  @hw: pointer to hardware structure
1003  *  @vf: vf index
1004  *
1005  *  Restore VF that was disabled during malicious driver detection event
1006  **/
1007 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1008 {
1009         u32 idx, reg, num_qs, start_q, bitmask;
1010
1011         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1012
1013         /* Map VF to queues */
1014         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1015         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1016         case IXGBE_MRQC_VMDQRT8TCEN:
1017                 num_qs = 8;  /* 16 VFs / pools */
1018                 bitmask = 0x000000FF;
1019                 break;
1020         case IXGBE_MRQC_VMDQRSS32EN:
1021         case IXGBE_MRQC_VMDQRT4TCEN:
1022                 num_qs = 4;  /* 32 VFs / pools */
1023                 bitmask = 0x0000000F;
1024                 break;
1025         default:            /* 64 VFs / pools */
1026                 num_qs = 2;
1027                 bitmask = 0x00000003;
1028                 break;
1029         }
1030         start_q = vf * num_qs;
1031
1032         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1033         idx = start_q / 32;
1034         reg = 0;
1035         reg |= (bitmask << (start_q % 32));
1036         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1037         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1038 }
1039
1040 /**
1041  *  ixgbe_mdd_event_X550
1042  *  @hw: pointer to hardware structure
1043  *  @vf_bitmap: vf bitmap of malicious vfs
1044  *
1045  *  Handle malicious driver detection event.
1046  **/
1047 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1048 {
1049         u32 wqbr;
1050         u32 i, j, reg, q, shift, vf, idx;
1051
1052         DEBUGFUNC("ixgbe_mdd_event_X550");
1053
1054         /* figure out pool size for mapping to vf's */
1055         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1056         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1057         case IXGBE_MRQC_VMDQRT8TCEN:
1058                 shift = 3;  /* 16 VFs / pools */
1059                 break;
1060         case IXGBE_MRQC_VMDQRSS32EN:
1061         case IXGBE_MRQC_VMDQRT4TCEN:
1062                 shift = 2;  /* 32 VFs / pools */
1063                 break;
1064         default:
1065                 shift = 1;  /* 64 VFs / pools */
1066                 break;
1067         }
1068
1069         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1070         for (i = 0; i < 4; i++) {
1071                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1072                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1073
1074                 if (!wqbr)
1075                         continue;
1076
1077                 /* Get malicious queue */
1078                 for (j = 0; j < 32 && wqbr; j++) {
1079
1080                         if (!(wqbr & (1 << j)))
1081                                 continue;
1082
1083                         /* Get queue from bitmask */
1084                         q = j + (i * 32);
1085
1086                         /* Map queue to vf */
1087                         vf = (q >> shift);
1088
1089                         /* Set vf bit in vf_bitmap */
1090                         idx = vf / 32;
1091                         vf_bitmap[idx] |= (1 << (vf % 32));
1092                         wqbr &= ~(1 << j);
1093                 }
1094         }
1095 }
1096
1097 /**
1098  *  ixgbe_get_media_type_X550em - Get media type
1099  *  @hw: pointer to hardware structure
1100  *
1101  *  Returns the media type (fiber, copper, backplane)
1102  */
1103 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1104 {
1105         enum ixgbe_media_type media_type;
1106
1107         DEBUGFUNC("ixgbe_get_media_type_X550em");
1108
1109         /* Detect if there is a copper PHY attached. */
1110         switch (hw->device_id) {
1111         case IXGBE_DEV_ID_X550EM_X_KR:
1112         case IXGBE_DEV_ID_X550EM_X_KX4:
1113                 media_type = ixgbe_media_type_backplane;
1114                 break;
1115         case IXGBE_DEV_ID_X550EM_X_SFP:
1116                 media_type = ixgbe_media_type_fiber;
1117                 break;
1118         case IXGBE_DEV_ID_X550EM_X_1G_T:
1119         case IXGBE_DEV_ID_X550EM_X_10G_T:
1120                 media_type = ixgbe_media_type_copper;
1121                 break;
1122         default:
1123                 media_type = ixgbe_media_type_unknown;
1124                 break;
1125         }
1126         return media_type;
1127 }
1128
1129 /**
1130  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1131  *  @hw: pointer to hardware structure
1132  *  @linear: true if SFP module is linear
1133  */
1134 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1135 {
1136         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1137
1138         switch (hw->phy.sfp_type) {
1139         case ixgbe_sfp_type_not_present:
1140                 return IXGBE_ERR_SFP_NOT_PRESENT;
1141         case ixgbe_sfp_type_da_cu_core0:
1142         case ixgbe_sfp_type_da_cu_core1:
1143                 *linear = true;
1144                 break;
1145         case ixgbe_sfp_type_srlr_core0:
1146         case ixgbe_sfp_type_srlr_core1:
1147         case ixgbe_sfp_type_da_act_lmt_core0:
1148         case ixgbe_sfp_type_da_act_lmt_core1:
1149         case ixgbe_sfp_type_1g_sx_core0:
1150         case ixgbe_sfp_type_1g_sx_core1:
1151         case ixgbe_sfp_type_1g_lx_core0:
1152         case ixgbe_sfp_type_1g_lx_core1:
1153                 *linear = false;
1154                 break;
1155         case ixgbe_sfp_type_unknown:
1156         case ixgbe_sfp_type_1g_cu_core0:
1157         case ixgbe_sfp_type_1g_cu_core1:
1158         default:
1159                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1160         }
1161
1162         return IXGBE_SUCCESS;
1163 }
1164
1165 /**
1166  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1167  *  @hw: pointer to hardware structure
1168  *
1169  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1170  **/
1171 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1172 {
1173         s32 status;
1174         bool linear;
1175
1176         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1177
1178         status = ixgbe_identify_module_generic(hw);
1179
1180         if (status != IXGBE_SUCCESS)
1181                 return status;
1182
1183         /* Check if SFP module is supported */
1184         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1185
1186         return status;
1187 }
1188
1189 /**
1190  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1191  *  @hw: pointer to hardware structure
1192  */
1193 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1194 {
1195         s32 status;
1196         bool linear;
1197
1198         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1199
1200         /* Check if SFP module is supported */
1201         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1202
1203         if (status != IXGBE_SUCCESS)
1204                 return status;
1205
1206         ixgbe_init_mac_link_ops_X550em(hw);
1207         hw->phy.ops.reset = NULL;
1208
1209         return IXGBE_SUCCESS;
1210 }
1211
1212 /**
1213  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1214  *  @hw: pointer to hardware structure
1215  */
1216 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1217 {
1218         struct ixgbe_mac_info *mac = &hw->mac;
1219
1220         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1221
1222          switch (hw->mac.ops.get_media_type(hw)) {
1223          case ixgbe_media_type_fiber:
1224                 /* CS4227 does not support autoneg, so disable the laser control
1225                  * functions for SFP+ fiber
1226                  */
1227                 mac->ops.disable_tx_laser = NULL;
1228                 mac->ops.enable_tx_laser = NULL;
1229                 mac->ops.flap_tx_laser = NULL;
1230                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1231                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1232                 mac->ops.set_rate_select_speed =
1233                                         ixgbe_set_soft_rate_select_speed;
1234                 break;
1235         case ixgbe_media_type_copper:
1236                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1237                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1238                 break;
1239         default:
1240                 break;
1241          }
1242 }
1243
1244 /**
1245  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1246  *  @hw: pointer to hardware structure
1247  *  @speed: pointer to link speed
1248  *  @autoneg: true when autoneg or autotry is enabled
1249  */
1250 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1251                                        ixgbe_link_speed *speed,
1252                                        bool *autoneg)
1253 {
1254         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1255
1256         /* SFP */
1257         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1258
1259                 /* CS4227 SFP must not enable auto-negotiation */
1260                 *autoneg = false;
1261
1262                 /* Check if 1G SFP module. */
1263                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1264                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1265                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1266                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1267                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1268                         return IXGBE_SUCCESS;
1269                 }
1270
1271                 /* Link capabilities are based on SFP */
1272                 if (hw->phy.multispeed_fiber)
1273                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1274                                  IXGBE_LINK_SPEED_1GB_FULL;
1275                 else
1276                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1277         } else {
1278                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1279                          IXGBE_LINK_SPEED_1GB_FULL;
1280                 *autoneg = true;
1281         }
1282
1283         return IXGBE_SUCCESS;
1284 }
1285
1286 /**
1287  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1288  * @hw: pointer to hardware structure
1289  * @lsc: pointer to boolean flag which indicates whether external Base T
1290  *       PHY interrupt is lsc
1291  *
1292  * Determime if external Base T PHY interrupt cause is high temperature
1293  * failure alarm or link status change.
1294  *
1295  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1296  * failure alarm, else return PHY access status.
1297  */
1298 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1299 {
1300         u32 status;
1301         u16 reg;
1302
1303         *lsc = false;
1304
1305         /* Vendor alarm triggered */
1306         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1307                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1308                                       &reg);
1309
1310         if (status != IXGBE_SUCCESS ||
1311             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1312                 return status;
1313
1314         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1315         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1316                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1317                                       &reg);
1318
1319         if (status != IXGBE_SUCCESS ||
1320             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1321             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1322                 return status;
1323
1324         /* High temperature failure alarm triggered */
1325         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1326                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1327                                       &reg);
1328
1329         if (status != IXGBE_SUCCESS)
1330                 return status;
1331
1332         /* If high temperature failure, then return over temp error and exit */
1333         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1334                 /* power down the PHY in case the PHY FW didn't already */
1335                 ixgbe_set_copper_phy_power(hw, false);
1336                 return IXGBE_ERR_OVERTEMP;
1337         }
1338
1339         /* Vendor alarm 2 triggered */
1340         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1341                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1342
1343         if (status != IXGBE_SUCCESS ||
1344             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1345                 return status;
1346
1347         /* link connect/disconnect event occurred */
1348         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1349                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1350
1351         if (status != IXGBE_SUCCESS)
1352                 return status;
1353
1354         /* Indicate LSC */
1355         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1356                 *lsc = true;
1357
1358         return IXGBE_SUCCESS;
1359 }
1360
1361 /**
1362  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1363  * @hw: pointer to hardware structure
1364  *
1365  * Enable link status change and temperature failure alarm for the external
1366  * Base T PHY
1367  *
1368  * Returns PHY access status
1369  */
1370 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1371 {
1372         u32 status;
1373         u16 reg;
1374         bool lsc;
1375
1376         /* Clear interrupt flags */
1377         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1378
1379         /* Enable link status change alarm */
1380         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1381                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1382
1383         if (status != IXGBE_SUCCESS)
1384                 return status;
1385
1386         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1387
1388         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1389                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1390
1391         if (status != IXGBE_SUCCESS)
1392                 return status;
1393
1394         /* Enables high temperature failure alarm */
1395         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1396                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1397                                       &reg);
1398
1399         if (status != IXGBE_SUCCESS)
1400                 return status;
1401
1402         reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1403
1404         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1405                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1406                                        reg);
1407
1408         if (status != IXGBE_SUCCESS)
1409                 return status;
1410
1411         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1412         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1413                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1414                                       &reg);
1415
1416         if (status != IXGBE_SUCCESS)
1417                 return status;
1418
1419         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1420                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1421
1422         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1423                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1424                                        reg);
1425
1426         if (status != IXGBE_SUCCESS)
1427                 return status;
1428
1429         /* Enable chip-wide vendor alarm */
1430         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1431                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1432                                       &reg);
1433
1434         if (status != IXGBE_SUCCESS)
1435                 return status;
1436
1437         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1438
1439         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1440                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1441                                        reg);
1442
1443         return status;
1444 }
1445
1446 /**
1447  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1448  *  @hw: pointer to hardware structure
1449  *  @speed: link speed
1450  *
1451  *  Configures the integrated KR PHY.
1452  **/
1453 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1454                                        ixgbe_link_speed speed)
1455 {
1456         s32 status;
1457         u32 reg_val;
1458
1459         status = ixgbe_read_iosf_sb_reg_x550(hw,
1460                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1461                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1462         if (status)
1463                 return status;
1464
1465         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1466         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1467                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1468
1469         /* Advertise 10G support. */
1470         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1471                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1472
1473         /* Advertise 1G support. */
1474         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1475                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1476
1477         /* Restart auto-negotiation. */
1478         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1479         status = ixgbe_write_iosf_sb_reg_x550(hw,
1480                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1481                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1482
1483         return status;
1484 }
1485
1486 /**
1487  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1488  *  @hw: pointer to hardware structure
1489  *
1490  *  Initialize any function pointers that were not able to be
1491  *  set during init_shared_code because the PHY/SFP type was
1492  *  not known.  Perform the SFP init if necessary.
1493  */
1494 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1495 {
1496         struct ixgbe_phy_info *phy = &hw->phy;
1497         ixgbe_link_speed speed;
1498         s32 ret_val;
1499
1500         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1501
1502         hw->mac.ops.set_lan_id(hw);
1503
1504         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1505                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1506                 ixgbe_setup_mux_ctl(hw);
1507
1508                 /* Save NW management interface connected on board. This is used
1509                  * to determine internal PHY mode.
1510                  */
1511                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1512
1513                 /* If internal PHY mode is KR, then initialize KR link */
1514                 if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
1515                         speed = IXGBE_LINK_SPEED_10GB_FULL |
1516                                 IXGBE_LINK_SPEED_1GB_FULL;
1517                         ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1518                 }
1519
1520                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1521         }
1522
1523         /* Identify the PHY or SFP module */
1524         ret_val = phy->ops.identify(hw);
1525         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1526                 return ret_val;
1527
1528         /* Setup function pointers based on detected hardware */
1529         ixgbe_init_mac_link_ops_X550em(hw);
1530         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1531                 phy->ops.reset = NULL;
1532
1533         /* Set functions pointers based on phy type */
1534         switch (hw->phy.type) {
1535         case ixgbe_phy_x550em_kx4:
1536                 phy->ops.setup_link = NULL;
1537                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1538                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1539                 break;
1540         case ixgbe_phy_x550em_kr:
1541                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1542                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1543                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1544                 break;
1545         case ixgbe_phy_x550em_ext_t:
1546                 /* Save NW management interface connected on board. This is used
1547                  * to determine internal PHY mode
1548                  */
1549                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1550
1551                 /* If internal link mode is XFI, then setup iXFI internal link,
1552                  * else setup KR now.
1553                  */
1554                 if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1555                         phy->ops.setup_internal_link =
1556                                               ixgbe_setup_internal_phy_t_x550em;
1557                 } else {
1558                         speed = IXGBE_LINK_SPEED_10GB_FULL |
1559                                 IXGBE_LINK_SPEED_1GB_FULL;
1560                         ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1561                 }
1562
1563                 /* setup SW LPLU only for first revision */
1564                 if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw,
1565                                                        IXGBE_FUSES0_GROUP(0))))
1566                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1567
1568                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1569                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1570                 break;
1571         default:
1572                 break;
1573         }
1574         return ret_val;
1575 }
1576
1577 /**
1578  *  ixgbe_reset_hw_X550em - Perform hardware reset
1579  *  @hw: pointer to hardware structure
1580  *
1581  *  Resets the hardware by resetting the transmit and receive units, masks
1582  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1583  *  reset.
1584  */
1585 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1586 {
1587         ixgbe_link_speed link_speed;
1588         s32 status;
1589         u32 ctrl = 0;
1590         u32 i;
1591         u32 hlreg0;
1592         bool link_up = false;
1593
1594         DEBUGFUNC("ixgbe_reset_hw_X550em");
1595
1596         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1597         status = hw->mac.ops.stop_adapter(hw);
1598         if (status != IXGBE_SUCCESS)
1599                 return status;
1600
1601         /* flush pending Tx transactions */
1602         ixgbe_clear_tx_pending(hw);
1603
1604         /* PHY ops must be identified and initialized prior to reset */
1605
1606         /* Identify PHY and related function pointers */
1607         status = hw->phy.ops.init(hw);
1608
1609         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1610                 return status;
1611
1612         /* start the external PHY */
1613         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1614                 status = ixgbe_init_ext_t_x550em(hw);
1615                 if (status)
1616                         return status;
1617         }
1618
1619         /* Setup SFP module if there is one present. */
1620         if (hw->phy.sfp_setup_needed) {
1621                 status = hw->mac.ops.setup_sfp(hw);
1622                 hw->phy.sfp_setup_needed = false;
1623         }
1624
1625         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1626                 return status;
1627
1628         /* Reset PHY */
1629         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1630                 hw->phy.ops.reset(hw);
1631
1632 mac_reset_top:
1633         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1634          * If link reset is used when link is up, it might reset the PHY when
1635          * mng is using it.  If link is down or the flag to force full link
1636          * reset is set, then perform link reset.
1637          */
1638         ctrl = IXGBE_CTRL_LNK_RST;
1639         if (!hw->force_full_reset) {
1640                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1641                 if (link_up)
1642                         ctrl = IXGBE_CTRL_RST;
1643         }
1644
1645         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1646         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1647         IXGBE_WRITE_FLUSH(hw);
1648
1649         /* Poll for reset bit to self-clear meaning reset is complete */
1650         for (i = 0; i < 10; i++) {
1651                 usec_delay(1);
1652                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1653                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1654                         break;
1655         }
1656
1657         if (ctrl & IXGBE_CTRL_RST_MASK) {
1658                 status = IXGBE_ERR_RESET_FAILED;
1659                 DEBUGOUT("Reset polling failed to complete.\n");
1660         }
1661
1662         msec_delay(50);
1663
1664         /* Double resets are required for recovery from certain error
1665          * conditions.  Between resets, it is necessary to stall to
1666          * allow time for any pending HW events to complete.
1667          */
1668         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1669                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1670                 goto mac_reset_top;
1671         }
1672
1673         /* Store the permanent mac address */
1674         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1675
1676         /* Store MAC address from RAR0, clear receive address registers, and
1677          * clear the multicast table.  Also reset num_rar_entries to 128,
1678          * since we modify this value when programming the SAN MAC address.
1679          */
1680         hw->mac.num_rar_entries = 128;
1681         hw->mac.ops.init_rx_addrs(hw);
1682
1683         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
1684                 /* Config MDIO clock speed. */
1685                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1686                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1687                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1688         }
1689
1690         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1691                 ixgbe_setup_mux_ctl(hw);
1692
1693         return status;
1694 }
1695
1696 /**
1697  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1698  * @hw: pointer to hardware structure
1699  */
1700 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1701 {
1702         u32 status;
1703         u16 reg;
1704
1705         status = hw->phy.ops.read_reg(hw,
1706                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1707                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1708                                       &reg);
1709
1710         if (status != IXGBE_SUCCESS)
1711                 return status;
1712
1713         /* If PHY FW reset completed bit is set then this is the first
1714          * SW instance after a power on so the PHY FW must be un-stalled.
1715          */
1716         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1717                 status = hw->phy.ops.read_reg(hw,
1718                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1719                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1720                                         &reg);
1721
1722                 if (status != IXGBE_SUCCESS)
1723                         return status;
1724
1725                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1726
1727                 status = hw->phy.ops.write_reg(hw,
1728                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1729                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1730                                         reg);
1731
1732                 if (status != IXGBE_SUCCESS)
1733                         return status;
1734         }
1735
1736         return status;
1737 }
1738
1739 /**
1740  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1741  *  @hw: pointer to hardware structure
1742  *
1743  *  Configures the integrated KR PHY.
1744  **/
1745 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1746 {
1747         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1748 }
1749
1750 /**
1751  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
1752  *  @hw: pointer to hardware structure
1753  *
1754  *  Configure the external PHY and the integrated KR PHY for SFP support.
1755  **/
1756 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1757                                     ixgbe_link_speed speed,
1758                                     bool autoneg_wait_to_complete)
1759 {
1760         s32 ret_val;
1761         u16 reg_slice, reg_val;
1762         bool setup_linear = false;
1763         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1764
1765         /* Check if SFP module is supported and linear */
1766         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1767
1768         /* If no SFP module present, then return success. Return success since
1769          * there is no reason to configure CS4227 and SFP not present error is
1770          * not excepted in the setup MAC link flow.
1771          */
1772         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1773                 return IXGBE_SUCCESS;
1774
1775         if (ret_val != IXGBE_SUCCESS)
1776                 return ret_val;
1777
1778         /* Configure CS4227 LINE side to 10G SR. */
1779         reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1780         reg_val = IXGBE_CS4227_SPEED_10G;
1781         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1782                 reg_val);
1783
1784         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1785         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1786         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1787                 reg_val);
1788
1789         /* Configure CS4227 for HOST connection rate then type. */
1790         reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1791         reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
1792                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1793         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1794                                            reg_val);
1795
1796         reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1797         if (setup_linear)
1798                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1799         else
1800                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1801         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1802                                            reg_val);
1803
1804         /* If internal link mode is XFI, then setup XFI internal link. */
1805         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))
1806                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1807
1808         return ret_val;
1809 }
1810
1811 /**
1812  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1813  *  @hw: pointer to hardware structure
1814  *  @speed: the link speed to force
1815  *
1816  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1817  *  internal and external PHY at a specific speed, without autonegotiation.
1818  **/
1819 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1820 {
1821         s32 status;
1822         u32 reg_val;
1823
1824         /* Disable AN and force speed to 10G Serial. */
1825         status = ixgbe_read_iosf_sb_reg_x550(hw,
1826                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1827                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1828         if (status != IXGBE_SUCCESS)
1829                 return status;
1830
1831         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1832         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1833
1834         /* Select forced link speed for internal PHY. */
1835         switch (*speed) {
1836         case IXGBE_LINK_SPEED_10GB_FULL:
1837                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1838                 break;
1839         case IXGBE_LINK_SPEED_1GB_FULL:
1840                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1841                 break;
1842         default:
1843                 /* Other link speeds are not supported by internal KR PHY. */
1844                 return IXGBE_ERR_LINK_SETUP;
1845         }
1846
1847         status = ixgbe_write_iosf_sb_reg_x550(hw,
1848                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1849                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1850         if (status != IXGBE_SUCCESS)
1851                 return status;
1852
1853         /* Disable training protocol FSM. */
1854         status = ixgbe_read_iosf_sb_reg_x550(hw,
1855                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1856                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1857         if (status != IXGBE_SUCCESS)
1858                 return status;
1859         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1860         status = ixgbe_write_iosf_sb_reg_x550(hw,
1861                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1862                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1863         if (status != IXGBE_SUCCESS)
1864                 return status;
1865
1866         /* Disable Flex from training TXFFE. */
1867         status = ixgbe_read_iosf_sb_reg_x550(hw,
1868                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1869                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1870         if (status != IXGBE_SUCCESS)
1871                 return status;
1872         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1873         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1874         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1875         status = ixgbe_write_iosf_sb_reg_x550(hw,
1876                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1877                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1878         if (status != IXGBE_SUCCESS)
1879                 return status;
1880         status = ixgbe_read_iosf_sb_reg_x550(hw,
1881                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1882                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1883         if (status != IXGBE_SUCCESS)
1884                 return status;
1885         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1886         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1887         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1888         status = ixgbe_write_iosf_sb_reg_x550(hw,
1889                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1890                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1891         if (status != IXGBE_SUCCESS)
1892                 return status;
1893
1894         /* Enable override for coefficients. */
1895         status = ixgbe_read_iosf_sb_reg_x550(hw,
1896                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1897                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1898         if (status != IXGBE_SUCCESS)
1899                 return status;
1900         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1901         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1902         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1903         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1904         status = ixgbe_write_iosf_sb_reg_x550(hw,
1905                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1906                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1907         if (status != IXGBE_SUCCESS)
1908                 return status;
1909
1910         /* Toggle port SW reset by AN reset. */
1911         status = ixgbe_read_iosf_sb_reg_x550(hw,
1912                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1913                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1914         if (status != IXGBE_SUCCESS)
1915                 return status;
1916         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1917         status = ixgbe_write_iosf_sb_reg_x550(hw,
1918                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1919                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1920
1921         return status;
1922 }
1923
1924 /**
1925  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
1926  * @hw: address of hardware structure
1927  * @link_up: address of boolean to indicate link status
1928  *
1929  * Returns error code if unable to get link status.
1930  */
1931 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
1932 {
1933         u32 ret;
1934         u16 autoneg_status;
1935
1936         *link_up = false;
1937
1938         /* read this twice back to back to indicate current status */
1939         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1940                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1941                                    &autoneg_status);
1942         if (ret != IXGBE_SUCCESS)
1943                 return ret;
1944
1945         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1946                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1947                                    &autoneg_status);
1948         if (ret != IXGBE_SUCCESS)
1949                 return ret;
1950
1951         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
1952
1953         return IXGBE_SUCCESS;
1954 }
1955
1956 /**
1957  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1958  * @hw: point to hardware structure
1959  *
1960  * Configures the link between the integrated KR PHY and the external X557 PHY
1961  * The driver will call this function when it gets a link status change
1962  * interrupt from the X557 PHY. This function configures the link speed
1963  * between the PHYs to match the link speed of the BASE-T link.
1964  *
1965  * A return of a non-zero value indicates an error, and the base driver should
1966  * not report link up.
1967  */
1968 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1969 {
1970         ixgbe_link_speed force_speed;
1971         bool link_up;
1972         u32 status;
1973         u16 speed;
1974
1975         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1976                 return IXGBE_ERR_CONFIG;
1977
1978         /* If link is not up, then there is no setup necessary so return  */
1979         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1980         if (status != IXGBE_SUCCESS)
1981                 return status;
1982
1983         if (!link_up)
1984                 return IXGBE_SUCCESS;
1985
1986         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1987                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1988                                       &speed);
1989         if (status != IXGBE_SUCCESS)
1990                 return status;
1991
1992         /* If link is not still up, then no setup is necessary so return */
1993         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1994         if (status != IXGBE_SUCCESS)
1995                 return status;
1996         if (!link_up)
1997                 return IXGBE_SUCCESS;
1998
1999         /* clear everything but the speed and duplex bits */
2000         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2001
2002         switch (speed) {
2003         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2004                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2005                 break;
2006         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2007                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2008                 break;
2009         default:
2010                 /* Internal PHY does not support anything else */
2011                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2012         }
2013
2014         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2015 }
2016
2017 /**
2018  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2019  *  @hw: pointer to hardware structure
2020  *
2021  *  Configures the integrated KR PHY to use internal loopback mode.
2022  **/
2023 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2024 {
2025         s32 status;
2026         u32 reg_val;
2027
2028         /* Disable AN and force speed to 10G Serial. */
2029         status = ixgbe_read_iosf_sb_reg_x550(hw,
2030                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2031                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2032         if (status != IXGBE_SUCCESS)
2033                 return status;
2034         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2035         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2036         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2037         status = ixgbe_write_iosf_sb_reg_x550(hw,
2038                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2039                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2040         if (status != IXGBE_SUCCESS)
2041                 return status;
2042
2043         /* Set near-end loopback clocks. */
2044         status = ixgbe_read_iosf_sb_reg_x550(hw,
2045                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2046                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2047         if (status != IXGBE_SUCCESS)
2048                 return status;
2049         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2050         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2051         status = ixgbe_write_iosf_sb_reg_x550(hw,
2052                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2053                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2054         if (status != IXGBE_SUCCESS)
2055                 return status;
2056
2057         /* Set loopback enable. */
2058         status = ixgbe_read_iosf_sb_reg_x550(hw,
2059                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2060                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2061         if (status != IXGBE_SUCCESS)
2062                 return status;
2063         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2064         status = ixgbe_write_iosf_sb_reg_x550(hw,
2065                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2066                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2067         if (status != IXGBE_SUCCESS)
2068                 return status;
2069
2070         /* Training bypass. */
2071         status = ixgbe_read_iosf_sb_reg_x550(hw,
2072                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2073                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2074         if (status != IXGBE_SUCCESS)
2075                 return status;
2076         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2077         status = ixgbe_write_iosf_sb_reg_x550(hw,
2078                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2079                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2080
2081         return status;
2082 }
2083
2084 /**
2085  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2086  *  assuming that the semaphore is already obtained.
2087  *  @hw: pointer to hardware structure
2088  *  @offset: offset of  word in the EEPROM to read
2089  *  @data: word read from the EEPROM
2090  *
2091  *  Reads a 16 bit word from the EEPROM using the hostif.
2092  **/
2093 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2094                                    u16 *data)
2095 {
2096         s32 status;
2097         struct ixgbe_hic_read_shadow_ram buffer;
2098
2099         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2100         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2101         buffer.hdr.req.buf_lenh = 0;
2102         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2103         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2104
2105         /* convert offset from words to bytes */
2106         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2107         /* one word */
2108         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2109
2110         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2111                                               sizeof(buffer),
2112                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2113
2114         if (status)
2115                 return status;
2116
2117         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2118                                           FW_NVM_DATA_OFFSET);
2119
2120         return 0;
2121 }
2122
2123 /**
2124  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2125  *  @hw: pointer to hardware structure
2126  *  @offset: offset of  word in the EEPROM to read
2127  *  @data: word read from the EEPROM
2128  *
2129  *  Reads a 16 bit word from the EEPROM using the hostif.
2130  **/
2131 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2132                               u16 *data)
2133 {
2134         s32 status = IXGBE_SUCCESS;
2135
2136         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2137
2138         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2139             IXGBE_SUCCESS) {
2140                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2141                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2142         } else {
2143                 status = IXGBE_ERR_SWFW_SYNC;
2144         }
2145
2146         return status;
2147 }
2148
2149 /**
2150  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2151  *  @hw: pointer to hardware structure
2152  *  @offset: offset of  word in the EEPROM to read
2153  *  @words: number of words
2154  *  @data: word(s) read from the EEPROM
2155  *
2156  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
2157  **/
2158 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2159                                      u16 offset, u16 words, u16 *data)
2160 {
2161         struct ixgbe_hic_read_shadow_ram buffer;
2162         u32 current_word = 0;
2163         u16 words_to_read;
2164         s32 status;
2165         u32 i;
2166
2167         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2168
2169         /* Take semaphore for the entire operation. */
2170         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2171         if (status) {
2172                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2173                 return status;
2174         }
2175         while (words) {
2176                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2177                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2178                 else
2179                         words_to_read = words;
2180
2181                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2182                 buffer.hdr.req.buf_lenh = 0;
2183                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2184                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2185
2186                 /* convert offset from words to bytes */
2187                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2188                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2189
2190                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2191                                                       sizeof(buffer),
2192                                                       IXGBE_HI_COMMAND_TIMEOUT,
2193                                                       false);
2194
2195                 if (status) {
2196                         DEBUGOUT("Host interface command failed\n");
2197                         goto out;
2198                 }
2199
2200                 for (i = 0; i < words_to_read; i++) {
2201                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2202                                   2 * i;
2203                         u32 value = IXGBE_READ_REG(hw, reg);
2204
2205                         data[current_word] = (u16)(value & 0xffff);
2206                         current_word++;
2207                         i++;
2208                         if (i < words_to_read) {
2209                                 value >>= 16;
2210                                 data[current_word] = (u16)(value & 0xffff);
2211                                 current_word++;
2212                         }
2213                 }
2214                 words -= words_to_read;
2215         }
2216
2217 out:
2218         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2219         return status;
2220 }
2221
2222 /**
2223  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2224  *  @hw: pointer to hardware structure
2225  *  @offset: offset of  word in the EEPROM to write
2226  *  @data: word write to the EEPROM
2227  *
2228  *  Write a 16 bit word to the EEPROM using the hostif.
2229  **/
2230 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2231                                     u16 data)
2232 {
2233         s32 status;
2234         struct ixgbe_hic_write_shadow_ram buffer;
2235
2236         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2237
2238         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2239         buffer.hdr.req.buf_lenh = 0;
2240         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2241         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2242
2243          /* one word */
2244         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2245         buffer.data = data;
2246         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2247
2248         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2249                                               sizeof(buffer),
2250                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2251
2252         return status;
2253 }
2254
2255 /**
2256  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2257  *  @hw: pointer to hardware structure
2258  *  @offset: offset of  word in the EEPROM to write
2259  *  @data: word write to the EEPROM
2260  *
2261  *  Write a 16 bit word to the EEPROM using the hostif.
2262  **/
2263 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2264                                u16 data)
2265 {
2266         s32 status = IXGBE_SUCCESS;
2267
2268         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2269
2270         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2271             IXGBE_SUCCESS) {
2272                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2273                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2274         } else {
2275                 DEBUGOUT("write ee hostif failed to get semaphore");
2276                 status = IXGBE_ERR_SWFW_SYNC;
2277         }
2278
2279         return status;
2280 }
2281
2282 /**
2283  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2284  *  @hw: pointer to hardware structure
2285  *  @offset: offset of  word in the EEPROM to write
2286  *  @words: number of words
2287  *  @data: word(s) write to the EEPROM
2288  *
2289  *  Write a 16 bit word(s) to the EEPROM using the hostif.
2290  **/
2291 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2292                                       u16 offset, u16 words, u16 *data)
2293 {
2294         s32 status = IXGBE_SUCCESS;
2295         u32 i = 0;
2296
2297         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2298
2299         /* Take semaphore for the entire operation. */
2300         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2301         if (status != IXGBE_SUCCESS) {
2302                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2303                 goto out;
2304         }
2305
2306         for (i = 0; i < words; i++) {
2307                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2308                                                          data[i]);
2309
2310                 if (status != IXGBE_SUCCESS) {
2311                         DEBUGOUT("Eeprom buffered write failed\n");
2312                         break;
2313                 }
2314         }
2315
2316         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2317 out:
2318
2319         return status;
2320 }
2321
2322 /**
2323  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2324  * @hw: pointer to hardware structure
2325  * @ptr: pointer offset in eeprom
2326  * @size: size of section pointed by ptr, if 0 first word will be used as size
2327  * @csum: address of checksum to update
2328  *
2329  * Returns error status for any failure
2330  */
2331 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2332                                    u16 size, u16 *csum, u16 *buffer,
2333                                    u32 buffer_size)
2334 {
2335         u16 buf[256];
2336         s32 status;
2337         u16 length, bufsz, i, start;
2338         u16 *local_buffer;
2339
2340         bufsz = sizeof(buf) / sizeof(buf[0]);
2341
2342         /* Read a chunk at the pointer location */
2343         if (!buffer) {
2344                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2345                 if (status) {
2346                         DEBUGOUT("Failed to read EEPROM image\n");
2347                         return status;
2348                 }
2349                 local_buffer = buf;
2350         } else {
2351                 if (buffer_size < ptr)
2352                         return  IXGBE_ERR_PARAM;
2353                 local_buffer = &buffer[ptr];
2354         }
2355
2356         if (size) {
2357                 start = 0;
2358                 length = size;
2359         } else {
2360                 start = 1;
2361                 length = local_buffer[0];
2362
2363                 /* Skip pointer section if length is invalid. */
2364                 if (length == 0xFFFF || length == 0 ||
2365                     (ptr + length) >= hw->eeprom.word_size)
2366                         return IXGBE_SUCCESS;
2367         }
2368
2369         if (buffer && ((u32)start + (u32)length > buffer_size))
2370                 return IXGBE_ERR_PARAM;
2371
2372         for (i = start; length; i++, length--) {
2373                 if (i == bufsz && !buffer) {
2374                         ptr += bufsz;
2375                         i = 0;
2376                         if (length < bufsz)
2377                                 bufsz = length;
2378
2379                         /* Read a chunk at the pointer location */
2380                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2381                                                                   bufsz, buf);
2382                         if (status) {
2383                                 DEBUGOUT("Failed to read EEPROM image\n");
2384                                 return status;
2385                         }
2386                 }
2387                 *csum += local_buffer[i];
2388         }
2389         return IXGBE_SUCCESS;
2390 }
2391
2392 /**
2393  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2394  *  @hw: pointer to hardware structure
2395  *  @buffer: pointer to buffer containing calculated checksum
2396  *  @buffer_size: size of buffer
2397  *
2398  *  Returns a negative error code on error, or the 16-bit checksum
2399  **/
2400 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2401 {
2402         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2403         u16 *local_buffer;
2404         s32 status;
2405         u16 checksum = 0;
2406         u16 pointer, i, size;
2407
2408         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2409
2410         hw->eeprom.ops.init_params(hw);
2411
2412         if (!buffer) {
2413                 /* Read pointer area */
2414                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2415                                                      IXGBE_EEPROM_LAST_WORD + 1,
2416                                                      eeprom_ptrs);
2417                 if (status) {
2418                         DEBUGOUT("Failed to read EEPROM image\n");
2419                         return status;
2420                 }
2421                 local_buffer = eeprom_ptrs;
2422         } else {
2423                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2424                         return IXGBE_ERR_PARAM;
2425                 local_buffer = buffer;
2426         }
2427
2428         /*
2429          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2430          * checksum word itself
2431          */
2432         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2433                 if (i != IXGBE_EEPROM_CHECKSUM)
2434                         checksum += local_buffer[i];
2435
2436         /*
2437          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2438          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2439          */
2440         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2441                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2442                         continue;
2443
2444                 pointer = local_buffer[i];
2445
2446                 /* Skip pointer section if the pointer is invalid. */
2447                 if (pointer == 0xFFFF || pointer == 0 ||
2448                     pointer >= hw->eeprom.word_size)
2449                         continue;
2450
2451                 switch (i) {
2452                 case IXGBE_PCIE_GENERAL_PTR:
2453                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2454                         break;
2455                 case IXGBE_PCIE_CONFIG0_PTR:
2456                 case IXGBE_PCIE_CONFIG1_PTR:
2457                         size = IXGBE_PCIE_CONFIG_SIZE;
2458                         break;
2459                 default:
2460                         size = 0;
2461                         break;
2462                 }
2463
2464                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2465                                                 buffer, buffer_size);
2466                 if (status)
2467                         return status;
2468         }
2469
2470         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2471
2472         return (s32)checksum;
2473 }
2474
2475 /**
2476  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2477  *  @hw: pointer to hardware structure
2478  *
2479  *  Returns a negative error code on error, or the 16-bit checksum
2480  **/
2481 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2482 {
2483         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2484 }
2485
2486 /**
2487  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2488  *  @hw: pointer to hardware structure
2489  *  @checksum_val: calculated checksum
2490  *
2491  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2492  *  caller does not need checksum_val, the value can be NULL.
2493  **/
2494 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2495 {
2496         s32 status;
2497         u16 checksum;
2498         u16 read_checksum = 0;
2499
2500         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2501
2502         /* Read the first word from the EEPROM. If this times out or fails, do
2503          * not continue or we could be in for a very long wait while every
2504          * EEPROM read fails
2505          */
2506         status = hw->eeprom.ops.read(hw, 0, &checksum);
2507         if (status) {
2508                 DEBUGOUT("EEPROM read failed\n");
2509                 return status;
2510         }
2511
2512         status = hw->eeprom.ops.calc_checksum(hw);
2513         if (status < 0)
2514                 return status;
2515
2516         checksum = (u16)(status & 0xffff);
2517
2518         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2519                                            &read_checksum);
2520         if (status)
2521                 return status;
2522
2523         /* Verify read checksum from EEPROM is the same as
2524          * calculated checksum
2525          */
2526         if (read_checksum != checksum) {
2527                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2528                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2529                              "Invalid EEPROM checksum");
2530         }
2531
2532         /* If the user cares, return the calculated checksum */
2533         if (checksum_val)
2534                 *checksum_val = checksum;
2535
2536         return status;
2537 }
2538
2539 /**
2540  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2541  * @hw: pointer to hardware structure
2542  *
2543  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2544  * checksum and updates the EEPROM and instructs the hardware to update
2545  * the flash.
2546  **/
2547 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2548 {
2549         s32 status;
2550         u16 checksum = 0;
2551
2552         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2553
2554         /* Read the first word from the EEPROM. If this times out or fails, do
2555          * not continue or we could be in for a very long wait while every
2556          * EEPROM read fails
2557          */
2558         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2559         if (status) {
2560                 DEBUGOUT("EEPROM read failed\n");
2561                 return status;
2562         }
2563
2564         status = ixgbe_calc_eeprom_checksum_X550(hw);
2565         if (status < 0)
2566                 return status;
2567
2568         checksum = (u16)(status & 0xffff);
2569
2570         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2571                                             checksum);
2572         if (status)
2573                 return status;
2574
2575         status = ixgbe_update_flash_X550(hw);
2576
2577         return status;
2578 }
2579
2580 /**
2581  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2582  *  @hw: pointer to hardware structure
2583  *
2584  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2585  **/
2586 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2587 {
2588         s32 status = IXGBE_SUCCESS;
2589         union ixgbe_hic_hdr2 buffer;
2590
2591         DEBUGFUNC("ixgbe_update_flash_X550");
2592
2593         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2594         buffer.req.buf_lenh = 0;
2595         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2596         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2597
2598         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2599                                               sizeof(buffer),
2600                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2601
2602         return status;
2603 }
2604
2605 /**
2606  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2607  *  @hw: pointer to hardware structure
2608  *
2609  *  Determines physical layer capabilities of the current configuration.
2610  **/
2611 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2612 {
2613         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2614         u16 ext_ability = 0;
2615
2616         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2617
2618         hw->phy.ops.identify(hw);
2619
2620         switch (hw->phy.type) {
2621         case ixgbe_phy_x550em_kr:
2622                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2623                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2624                 break;
2625         case ixgbe_phy_x550em_kx4:
2626                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2627                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2628                 break;
2629         case ixgbe_phy_x550em_ext_t:
2630                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2631                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2632                                      &ext_ability);
2633                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2634                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2635                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2636                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2637                 break;
2638         default:
2639                 break;
2640         }
2641
2642         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2643                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2644
2645         return physical_layer;
2646 }
2647
2648 /**
2649  * ixgbe_get_bus_info_x550em - Set PCI bus info
2650  * @hw: pointer to hardware structure
2651  *
2652  * Sets bus link width and speed to unknown because X550em is
2653  * not a PCI device.
2654  **/
2655 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2656 {
2657
2658         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2659
2660         hw->bus.width = ixgbe_bus_width_unknown;
2661         hw->bus.speed = ixgbe_bus_speed_unknown;
2662
2663         hw->mac.ops.set_lan_id(hw);
2664
2665         return IXGBE_SUCCESS;
2666 }
2667
2668 /**
2669  * ixgbe_disable_rx_x550 - Disable RX unit
2670  *
2671  * Enables the Rx DMA unit for x550
2672  **/
2673 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2674 {
2675         u32 rxctrl, pfdtxgswc;
2676         s32 status;
2677         struct ixgbe_hic_disable_rxen fw_cmd;
2678
2679         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2680
2681         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2682         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2683                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2684                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2685                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2686                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2687                         hw->mac.set_lben = true;
2688                 } else {
2689                         hw->mac.set_lben = false;
2690                 }
2691
2692                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2693                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2694                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2695                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2696
2697                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2698                                         sizeof(struct ixgbe_hic_disable_rxen),
2699                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2700
2701                 /* If we fail - disable RX using register write */
2702                 if (status) {
2703                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2704                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2705                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2706                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2707                         }
2708                 }
2709         }
2710 }
2711
2712 /**
2713  * ixgbe_enter_lplu_x550em - Transition to low power states
2714  *  @hw: pointer to hardware structure
2715  *
2716  * Configures Low Power Link Up on transition to low power states
2717  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2718  * X557 PHY immediately prior to entering LPLU.
2719  **/
2720 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2721 {
2722         u16 an_10g_cntl_reg, autoneg_reg, speed;
2723         s32 status;
2724         ixgbe_link_speed lcd_speed;
2725         u32 save_autoneg;
2726         bool link_up;
2727
2728         /* SW LPLU not required on later HW revisions. */
2729         if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))
2730                 return IXGBE_SUCCESS;
2731
2732         /* If blocked by MNG FW, then don't restart AN */
2733         if (ixgbe_check_reset_blocked(hw))
2734                 return IXGBE_SUCCESS;
2735
2736         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2737         if (status != IXGBE_SUCCESS)
2738                 return status;
2739
2740         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2741
2742         if (status != IXGBE_SUCCESS)
2743                 return status;
2744
2745         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2746          * disabled, then force link down by entering low power mode.
2747          */
2748         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2749             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2750                 return ixgbe_set_copper_phy_power(hw, FALSE);
2751
2752         /* Determine LCD */
2753         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2754
2755         if (status != IXGBE_SUCCESS)
2756                 return status;
2757
2758         /* If no valid LCD link speed, then force link down and exit. */
2759         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2760                 return ixgbe_set_copper_phy_power(hw, FALSE);
2761
2762         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2763                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2764                                       &speed);
2765
2766         if (status != IXGBE_SUCCESS)
2767                 return status;
2768
2769         /* If no link now, speed is invalid so take link down */
2770         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2771         if (status != IXGBE_SUCCESS)
2772                 return ixgbe_set_copper_phy_power(hw, false);
2773
2774         /* clear everything but the speed bits */
2775         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2776
2777         /* If current speed is already LCD, then exit. */
2778         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2779              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2780             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2781              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2782                 return status;
2783
2784         /* Clear AN completed indication */
2785         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2786                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2787                                       &autoneg_reg);
2788
2789         if (status != IXGBE_SUCCESS)
2790                 return status;
2791
2792         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2793                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2794                              &an_10g_cntl_reg);
2795
2796         if (status != IXGBE_SUCCESS)
2797                 return status;
2798
2799         status = hw->phy.ops.read_reg(hw,
2800                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2801                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2802                              &autoneg_reg);
2803
2804         if (status != IXGBE_SUCCESS)
2805                 return status;
2806
2807         save_autoneg = hw->phy.autoneg_advertised;
2808
2809         /* Setup link at least common link speed */
2810         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2811
2812         /* restore autoneg from before setting lplu speed */
2813         hw->phy.autoneg_advertised = save_autoneg;
2814
2815         return status;
2816 }
2817
2818 /**
2819  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2820  *  @hw: pointer to hardware structure
2821  *  @lcd_speed: pointer to lowest common link speed
2822  *
2823  * Determine lowest common link speed with link partner.
2824  **/
2825 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2826 {
2827         u16 an_lp_status;
2828         s32 status;
2829         u16 word = hw->eeprom.ctrl_word_3;
2830
2831         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2832
2833         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2834                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2835                                       &an_lp_status);
2836
2837         if (status != IXGBE_SUCCESS)
2838                 return status;
2839
2840         /* If link partner advertised 1G, return 1G */
2841         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2842                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2843                 return status;
2844         }
2845
2846         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2847         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2848             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2849                 return status;
2850
2851         /* Link partner not capable of lower speeds, return 10G */
2852         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2853         return status;
2854 }
2855
2856 /**
2857  *  ixgbe_setup_fc_X550em - Set up flow control
2858  *  @hw: pointer to hardware structure
2859  *
2860  *  Called at init time to set up flow control.
2861  **/
2862 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2863 {
2864         s32 ret_val = IXGBE_SUCCESS;
2865         u32 pause, asm_dir, reg_val;
2866
2867         DEBUGFUNC("ixgbe_setup_fc_X550em");
2868
2869         /* Validate the requested mode */
2870         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2871                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2872                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2873                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2874                 goto out;
2875         }
2876
2877         /* 10gig parts do not have a word in the EEPROM to determine the
2878          * default flow control setting, so we explicitly set it to full.
2879          */
2880         if (hw->fc.requested_mode == ixgbe_fc_default)
2881                 hw->fc.requested_mode = ixgbe_fc_full;
2882
2883         /* Determine PAUSE and ASM_DIR bits. */
2884         switch (hw->fc.requested_mode) {
2885         case ixgbe_fc_none:
2886                 pause = 0;
2887                 asm_dir = 0;
2888                 break;
2889         case ixgbe_fc_tx_pause:
2890                 pause = 0;
2891                 asm_dir = 1;
2892                 break;
2893         case ixgbe_fc_rx_pause:
2894                 /* Rx Flow control is enabled and Tx Flow control is
2895                  * disabled by software override. Since there really
2896                  * isn't a way to advertise that we are capable of RX
2897                  * Pause ONLY, we will advertise that we support both
2898                  * symmetric and asymmetric Rx PAUSE, as such we fall
2899                  * through to the fc_full statement.  Later, we will
2900                  * disable the adapter's ability to send PAUSE frames.
2901                  */
2902         case ixgbe_fc_full:
2903                 pause = 1;
2904                 asm_dir = 1;
2905                 break;
2906         default:
2907                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2908                         "Flow control param set incorrectly\n");
2909                 ret_val = IXGBE_ERR_CONFIG;
2910                 goto out;
2911         }
2912
2913         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
2914                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2915                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2916                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2917                 if (ret_val != IXGBE_SUCCESS)
2918                         goto out;
2919                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2920                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2921                 if (pause)
2922                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2923                 if (asm_dir)
2924                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2925                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2926                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2927                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2928
2929                 /* This device does not fully support AN. */
2930                 hw->fc.disable_fc_autoneg = true;
2931         }
2932
2933 out:
2934         return ret_val;
2935 }
2936
2937 /**
2938  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2939  * @hw: pointer to hardware structure
2940  * @state: set mux if 1, clear if 0
2941  */
2942 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2943 {
2944         u32 esdp;
2945
2946         if (!hw->bus.lan_id)
2947                 return;
2948         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2949         if (state)
2950                 esdp |= IXGBE_ESDP_SDP1;
2951         else
2952                 esdp &= ~IXGBE_ESDP_SDP1;
2953         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2954         IXGBE_WRITE_FLUSH(hw);
2955 }
2956
2957 /**
2958  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2959  *  @hw: pointer to hardware structure
2960  *  @mask: Mask to specify which semaphore to acquire
2961  *
2962  *  Acquires the SWFW semaphore and sets the I2C MUX
2963  **/
2964 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2965 {
2966         s32 status;
2967
2968         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2969
2970         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2971         if (status)
2972                 return status;
2973
2974         if (mask & IXGBE_GSSR_I2C_MASK)
2975                 ixgbe_set_mux(hw, 1);
2976
2977         return IXGBE_SUCCESS;
2978 }
2979
2980 /**
2981  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2982  *  @hw: pointer to hardware structure
2983  *  @mask: Mask to specify which semaphore to release
2984  *
2985  *  Releases the SWFW semaphore and sets the I2C MUX
2986  **/
2987 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2988 {
2989         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2990
2991         if (mask & IXGBE_GSSR_I2C_MASK)
2992                 ixgbe_set_mux(hw, 0);
2993
2994         ixgbe_release_swfw_sync_X540(hw, mask);
2995 }
2996
2997 /**
2998  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2999  * @hw: pointer to hardware structure
3000  *
3001  * Handle external Base T PHY interrupt. If high temperature
3002  * failure alarm then return error, else if link status change
3003  * then setup internal/external PHY link
3004  *
3005  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
3006  * failure alarm, else return PHY access status.
3007  */
3008 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
3009 {
3010         bool lsc;
3011         u32 status;
3012
3013         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
3014
3015         if (status != IXGBE_SUCCESS)
3016                 return status;
3017
3018         if (lsc)
3019                 return ixgbe_setup_internal_phy(hw);
3020
3021         return IXGBE_SUCCESS;
3022 }
3023
3024 /**
3025  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
3026  * @hw: pointer to hardware structure
3027  * @speed: new link speed
3028  * @autoneg_wait_to_complete: true when waiting for completion is needed
3029  *
3030  * Setup internal/external PHY link speed based on link speed, then set
3031  * external PHY auto advertised link speed.
3032  *
3033  * Returns error status for any failure
3034  **/
3035 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3036                                   ixgbe_link_speed speed,
3037                                   bool autoneg_wait_to_complete)
3038 {
3039         s32 status;
3040         ixgbe_link_speed force_speed;
3041
3042         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3043
3044         /* Setup internal/external PHY link speed to iXFI (10G), unless
3045          * only 1G is auto advertised then setup KX link.
3046          */
3047         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3048                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3049         else
3050                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3051
3052         /* If internal link mode is XFI, then setup XFI internal link. */
3053         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3054                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3055
3056                 if (status != IXGBE_SUCCESS)
3057                         return status;
3058         }
3059
3060         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3061 }
3062
3063 /**
3064  * ixgbe_check_link_t_X550em - Determine link and speed status
3065  * @hw: pointer to hardware structure
3066  * @speed: pointer to link speed
3067  * @link_up: true when link is up
3068  * @link_up_wait_to_complete: bool used to wait for link up or not
3069  *
3070  * Check that both the MAC and X557 external PHY have link.
3071  **/
3072 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3073                               bool *link_up, bool link_up_wait_to_complete)
3074 {
3075         u32 status;
3076         u16 autoneg_status;
3077
3078         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3079                 return IXGBE_ERR_CONFIG;
3080
3081         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3082                                               link_up_wait_to_complete);
3083
3084         /* If check link fails or MAC link is not up, then return */
3085         if (status != IXGBE_SUCCESS || !(*link_up))
3086                 return status;
3087
3088         /* MAC link is up, so check external PHY link.
3089          * Read this twice back to back to indicate current status.
3090          */
3091         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3092                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3093                                       &autoneg_status);
3094
3095         if (status != IXGBE_SUCCESS)
3096                 return status;
3097
3098         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3099                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3100                                       &autoneg_status);
3101
3102         if (status != IXGBE_SUCCESS)
3103                 return status;
3104
3105         /* If external PHY link is not up, then indicate link not up */
3106         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3107                 *link_up = false;
3108
3109         return IXGBE_SUCCESS;
3110 }
3111
3112 /**
3113  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3114  *  @hw: pointer to hardware structure
3115  **/
3116 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3117 {
3118         s32 status;
3119
3120         status = ixgbe_reset_phy_generic(hw);
3121
3122         if (status != IXGBE_SUCCESS)
3123                 return status;
3124
3125         /* Configure Link Status Alarm and Temperature Threshold interrupts */
3126         return ixgbe_enable_lasi_ext_t_x550em(hw);
3127 }
3128
3129 /**
3130  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
3131  *  @hw: pointer to hardware structure
3132  *  @led_idx: led number to turn on
3133  **/
3134 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3135 {
3136         u16 phy_data;
3137
3138         DEBUGFUNC("ixgbe_led_on_t_X550em");
3139
3140         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3141                 return IXGBE_ERR_PARAM;
3142
3143         /* To turn on the LED, set mode to ON. */
3144         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3145                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3146         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3147         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3148                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3149
3150         return IXGBE_SUCCESS;
3151 }
3152
3153 /**
3154  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3155  *  @hw: pointer to hardware structure
3156  *  @led_idx: led number to turn off
3157  **/
3158 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3159 {
3160         u16 phy_data;
3161
3162         DEBUGFUNC("ixgbe_led_off_t_X550em");
3163
3164         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3165                 return IXGBE_ERR_PARAM;
3166
3167         /* To turn on the LED, set mode to ON. */
3168         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3169                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3170         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3171         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3172                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3173
3174         return IXGBE_SUCCESS;
3175 }