drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44
  45 /**
  46  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  47  *  @hw: pointer to hardware structure
  48  *
  49  *  Initialize the function pointers and assign the MAC type for X550.
  50  *  Does not touch the hardware.
  51  **/
  52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  53 {
  54         struct ixgbe_mac_info *mac = &hw->mac;
  55         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  56         s32 ret_val;
  57
  58         DEBUGFUNC("ixgbe_init_ops_X550");
  59
  60         ret_val = ixgbe_init_ops_X540(hw);
  61         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  62         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  63         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  64         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  65         mac->ops.set_source_address_pruning =
  66                         ixgbe_set_source_address_pruning_X550;
  67         mac->ops.set_ethertype_anti_spoofing =
  68                         ixgbe_set_ethertype_anti_spoofing_X550;
  69
  70         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  71         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  72         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  73         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  74         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  75         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  76         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  77         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  78         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  79
  80         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  81         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  82         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  83         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  84         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  85         switch (hw->device_id) {
  86         case IXGBE_DEV_ID_X550EM_X_10G_T:
  87         case IXGBE_DEV_ID_X550EM_A_10G_T:
  88                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  89                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  90                 break;
  91         default:
  92                 break;
  93         }
  94         return ret_val;
  95 }
  96
  97 /**
  98  * ixgbe_read_cs4227 - Read CS4227 register
  99  * @hw: pointer to hardware structure
 100  * @reg: register number to write
 101  * @value: pointer to receive value read
 102  *
 103  * Returns status code
 104  **/
 105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 106 {
 107         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 108 }
 109
 110 /**
 111  * ixgbe_write_cs4227 - Write CS4227 register
 112  * @hw: pointer to hardware structure
 113  * @reg: register number to write
 114  * @value: value to write to register
 115  *
 116  * Returns status code
 117  **/
 118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 119 {
 120         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 121 }
 122
 123 /**
 124  * ixgbe_read_pe - Read register from port expander
 125  * @hw: pointer to hardware structure
 126  * @reg: register number to read
 127  * @value: pointer to receive read value
 128  *
 129  * Returns status code
 130  **/
 131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 132 {
 133         s32 status;
 134
 135         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 136         if (status != IXGBE_SUCCESS)
 137                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 138                               "port expander access failed with %d\n", status);
 139         return status;
 140 }
 141
 142 /**
 143  * ixgbe_write_pe - Write register to port expander
 144  * @hw: pointer to hardware structure
 145  * @reg: register number to write
 146  * @value: value to write
 147  *
 148  * Returns status code
 149  **/
 150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 151 {
 152         s32 status;
 153
 154         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 155         if (status != IXGBE_SUCCESS)
 156                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 157                               "port expander access failed with %d\n", status);
 158         return status;
 159 }
 160
 161 /**
 162  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 163  * @hw: pointer to hardware structure
 164  *
 165  * This function assumes that the caller has acquired the proper semaphore.
 166  * Returns error code
 167  **/
 168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 169 {
 170         s32 status;
 171         u32 retry;
 172         u16 value;
 173         u8 reg;
 174
 175         /* Trigger hard reset. */
 176         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 177         if (status != IXGBE_SUCCESS)
 178                 return status;
 179         reg |= IXGBE_PE_BIT1;
 180         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 181         if (status != IXGBE_SUCCESS)
 182                 return status;
 183
 184         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 185         if (status != IXGBE_SUCCESS)
 186                 return status;
 187         reg &= ~IXGBE_PE_BIT1;
 188         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 189         if (status != IXGBE_SUCCESS)
 190                 return status;
 191
 192         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 193         if (status != IXGBE_SUCCESS)
 194                 return status;
 195         reg &= ~IXGBE_PE_BIT1;
 196         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199
 200         usec_delay(IXGBE_CS4227_RESET_HOLD);
 201
 202         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 203         if (status != IXGBE_SUCCESS)
 204                 return status;
 205         reg |= IXGBE_PE_BIT1;
 206         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 207         if (status != IXGBE_SUCCESS)
 208                 return status;
 209
 210         /* Wait for the reset to complete. */
 211         msec_delay(IXGBE_CS4227_RESET_DELAY);
 212         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 213                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 214                                            &value);
 215                 if (status == IXGBE_SUCCESS &&
 216                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 217                         break;
 218                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 219         }
 220         if (retry == IXGBE_CS4227_RETRIES) {
 221                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 222                         "CS4227 reset did not complete.");
 223                 return IXGBE_ERR_PHY;
 224         }
 225
 226         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 227         if (status != IXGBE_SUCCESS ||
 228             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 229                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 230                         "CS4227 EEPROM did not load successfully.");
 231                 return IXGBE_ERR_PHY;
 232         }
 233
 234         return IXGBE_SUCCESS;
 235 }
 236
 237 /**
 238  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 239  * @hw: pointer to hardware structure
 240  **/
 241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 242 {
 243         s32 status = IXGBE_SUCCESS;
 244         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 245         u16 value = 0;
 246         u8 retry;
 247
 248         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 249                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 250                 if (status != IXGBE_SUCCESS) {
 251                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 252                                 "semaphore failed with %d", status);
 253                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 254                         continue;
 255                 }
 256
 257                 /* Get status of reset flow. */
 258                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 259
 260                 if (status == IXGBE_SUCCESS &&
 261                     value == IXGBE_CS4227_RESET_COMPLETE)
 262                         goto out;
 263
 264                 if (status != IXGBE_SUCCESS ||
 265                     value != IXGBE_CS4227_RESET_PENDING)
 266                         break;
 267
 268                 /* Reset is pending. Wait and check again. */
 269                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 270                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 271         }
 272
 273         /* If still pending, assume other instance failed. */
 274         if (retry == IXGBE_CS4227_RETRIES) {
 275                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 276                 if (status != IXGBE_SUCCESS) {
 277                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 278                                       "semaphore failed with %d", status);
 279                         return;
 280                 }
 281         }
 282
 283         /* Reset the CS4227. */
 284         status = ixgbe_reset_cs4227(hw);
 285         if (status != IXGBE_SUCCESS) {
 286                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 287                         "CS4227 reset failed: %d", status);
 288                 goto out;
 289         }
 290
 291         /* Reset takes so long, temporarily release semaphore in case the
 292          * other driver instance is waiting for the reset indication.
 293          */
 294         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 295                            IXGBE_CS4227_RESET_PENDING);
 296         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 297         msec_delay(10);
 298         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 299         if (status != IXGBE_SUCCESS) {
 300                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 301                         "semaphore failed with %d", status);
 302                 return;
 303         }
 304
 305         /* Record completion for next time. */
 306         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 307                 IXGBE_CS4227_RESET_COMPLETE);
 308
 309 out:
 310         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 311         msec_delay(hw->eeprom.semaphore_delay);
 312 }
 313
 314 /**
 315  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 316  * @hw: pointer to hardware structure
 317  **/
 318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 319 {
 320         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 321
 322         if (hw->bus.lan_id) {
 323                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 324                 esdp |= IXGBE_ESDP_SDP1_DIR;
 325         }
 326         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 327         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 328         IXGBE_WRITE_FLUSH(hw);
 329 }
 330
 331 /**
 332  * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
 333  * @hw: pointer to hardware structure
 334  * @reg_addr: 32 bit address of PHY register to read
 335  * @dev_type: always unused
 336  * @phy_data: Pointer to read data from PHY register
 337  */
 338 static s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 339                                      u32 dev_type, u16 *phy_data)
 340 {
 341         u32 i, data, command;
 342         UNREFERENCED_1PARAMETER(dev_type);
 343
 344         /* Setup and write the read command */
 345         command = (reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 346                 (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 347                 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 348                 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ |
 349                 IXGBE_MSCA_MDI_COMMAND;
 350
 351         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 352
 353         /* Check every 10 usec to see if the access completed.
 354          * The MDI Command bit will clear when the operation is
 355          * complete
 356          */
 357         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 358                 usec_delay(10);
 359
 360                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 361                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 362                         break;
 363         }
 364
 365         if (command & IXGBE_MSCA_MDI_COMMAND) {
 366                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 367                               "PHY read command did not complete.\n");
 368                 return IXGBE_ERR_PHY;
 369         }
 370
 371         /* Read operation is complete.  Get the data from MSRWD */
 372         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 373         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 374         *phy_data = (u16)data;
 375
 376         return IXGBE_SUCCESS;
 377 }
 378
 379 /**
 380  * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
 381  * @hw: pointer to hardware structure
 382  * @reg_addr: 32 bit PHY register to write
 383  * @dev_type: always unused
 384  * @phy_data: Data to write to the PHY register
 385  */
 386 static s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 387                                       u32 dev_type, u16 phy_data)
 388 {
 389         u32 i, command;
 390         UNREFERENCED_1PARAMETER(dev_type);
 391
 392         /* Put the data in the MDI single read and write data register*/
 393         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 394
 395         /* Setup and write the write command */
 396         command = (reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 397                 (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 398                 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 399                 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
 400                 IXGBE_MSCA_MDI_COMMAND;
 401
 402         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 403
 404         /* Check every 10 usec to see if the access completed.
 405          * The MDI Command bit will clear when the operation is
 406          * complete
 407          */
 408         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 409                 usec_delay(10);
 410
 411                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 412                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 413                         break;
 414         }
 415
 416         if (command & IXGBE_MSCA_MDI_COMMAND) {
 417                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 418                               "PHY write cmd didn't complete\n");
 419                 return IXGBE_ERR_PHY;
 420         }
 421
 422         return IXGBE_SUCCESS;
 423 }
 424
 425 /**
 426  * ixgbe_identify_phy_1g - Get 1g PHY type based on device id
 427  * @hw: pointer to hardware structure
 428  *
 429  * Returns error code
 430  */
 431 static s32 ixgbe_identify_phy_1g(struct ixgbe_hw *hw)
 432 {
 433         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 434         u16 phy_id_high;
 435         u16 phy_id_low;
 436         s32 rc;
 437
 438         rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 439         if (rc)
 440                 return rc;
 441
 442         rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_MDIO_PHY_ID_HIGH, 0,
 443                                        &phy_id_high);
 444         if (rc)
 445                 goto rel_out;
 446
 447         rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_MDIO_PHY_ID_LOW, 0,
 448                                        &phy_id_low);
 449         if (rc)
 450                 goto rel_out;
 451
 452         hw->phy.id = (u32)phy_id_high << 16;
 453         hw->phy.id |= phy_id_low & IXGBE_PHY_REVISION_MASK;
 454         hw->phy.revision = (u32)phy_id_low & ~IXGBE_PHY_REVISION_MASK;
 455
 456 rel_out:
 457         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 458
 459         return rc;
 460 }
 461
 462 /**
 463  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 464  * @hw: pointer to hardware structure
 465  *
 466  * Returns error code
 467  */
 468 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 469 {
 470         switch (hw->device_id) {
 471         case IXGBE_DEV_ID_X550EM_A_SFP:
 472                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
 473                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
 474                 if (hw->bus.lan_id)
 475                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 476                 else
 477                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 478                 return ixgbe_identify_module_generic(hw);
 479         case IXGBE_DEV_ID_X550EM_X_SFP:
 480                 /* set up for CS4227 usage */
 481                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 482                 ixgbe_setup_mux_ctl(hw);
 483                 ixgbe_check_cs4227(hw);
 484                 /* Fallthrough */
 485
 486         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 487                 return ixgbe_identify_module_generic(hw);
 488                 break;
 489         case IXGBE_DEV_ID_X550EM_X_KX4:
 490                 hw->phy.type = ixgbe_phy_x550em_kx4;
 491                 break;
 492         case IXGBE_DEV_ID_X550EM_X_KR:
 493         case IXGBE_DEV_ID_X550EM_A_KR:
 494         case IXGBE_DEV_ID_X550EM_A_KR_L:
 495                 hw->phy.type = ixgbe_phy_x550em_kr;
 496                 break;
 497         case IXGBE_DEV_ID_X550EM_X_1G_T:
 498         case IXGBE_DEV_ID_X550EM_X_10G_T:
 499         case IXGBE_DEV_ID_X550EM_A_10G_T:
 500                 return ixgbe_identify_phy_generic(hw);
 501         case IXGBE_DEV_ID_X550EM_A_1G_T:
 502         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 503                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
 504                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
 505                 if (hw->bus.lan_id)
 506                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 507                 else
 508                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 509                 return ixgbe_identify_phy_1g(hw);
 510         default:
 511                 break;
 512         }
 513         return IXGBE_SUCCESS;
 514 }
 515
 516 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 517                                      u32 device_type, u16 *phy_data)
 518 {
 519         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 520         return IXGBE_NOT_IMPLEMENTED;
 521 }
 522
 523 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 524                                       u32 device_type, u16 phy_data)
 525 {
 526         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 527         return IXGBE_NOT_IMPLEMENTED;
 528 }
 529
 530 /**
 531  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 532  * @hw: pointer to the hardware structure
 533  * @addr: I2C bus address to read from
 534  * @reg: I2C device register to read from
 535  * @val: pointer to location to receive read value
 536  *
 537  * Returns an error code on error.
 538  **/
 539 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 540                                            u16 reg, u16 *val)
 541 {
 542         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 543 }
 544
 545 /**
 546  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 547  * @hw: pointer to the hardware structure
 548  * @addr: I2C bus address to read from
 549  * @reg: I2C device register to read from
 550  * @val: pointer to location to receive read value
 551  *
 552  * Returns an error code on error.
 553  **/
 554 static s32
 555 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 556                                          u16 reg, u16 *val)
 557 {
 558         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 559 }
 560
 561 /**
 562  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 563  * @hw: pointer to the hardware structure
 564  * @addr: I2C bus address to write to
 565  * @reg: I2C device register to write to
 566  * @val: value to write
 567  *
 568  * Returns an error code on error.
 569  **/
 570 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 571                                             u8 addr, u16 reg, u16 val)
 572 {
 573         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 574 }
 575
 576 /**
 577  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 578  * @hw: pointer to the hardware structure
 579  * @addr: I2C bus address to write to
 580  * @reg: I2C device register to write to
 581  * @val: value to write
 582  *
 583  * Returns an error code on error.
 584  **/
 585 static s32
 586 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 587                                           u8 addr, u16 reg, u16 val)
 588 {
 589         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 590 }
 591
 592 /**
 593 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 594 *  @hw: pointer to hardware structure
 595 *
 596 *  Initialize the function pointers and for MAC type X550EM.
 597 *  Does not touch the hardware.
 598 **/
 599 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 600 {
 601         struct ixgbe_mac_info *mac = &hw->mac;
 602         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 603         struct ixgbe_phy_info *phy = &hw->phy;
 604         struct ixgbe_link_info *link = &hw->link;
 605         s32 ret_val;
 606
 607         DEBUGFUNC("ixgbe_init_ops_X550EM");
 608
 609         /* Similar to X550 so start there. */
 610         ret_val = ixgbe_init_ops_X550(hw);
 611
 612         /* Since this function eventually calls
 613          * ixgbe_init_ops_540 by design, we are setting
 614          * the pointers to NULL explicitly here to overwrite
 615          * the values being set in the x540 function.
 616          */
 617         /* Thermal sensor not supported in x550EM */
 618         mac->ops.get_thermal_sensor_data = NULL;
 619         mac->ops.init_thermal_sensor_thresh = NULL;
 620         mac->thermal_sensor_enabled = false;
 621
 622         /* FCOE not supported in x550EM */
 623         mac->ops.get_san_mac_addr = NULL;
 624         mac->ops.set_san_mac_addr = NULL;
 625         mac->ops.get_wwn_prefix = NULL;
 626         mac->ops.get_fcoe_boot_status = NULL;
 627
 628         /* IPsec not supported in x550EM */
 629         mac->ops.disable_sec_rx_path = NULL;
 630         mac->ops.enable_sec_rx_path = NULL;
 631
 632         /* AUTOC register is not present in x550EM. */
 633         mac->ops.prot_autoc_read = NULL;
 634         mac->ops.prot_autoc_write = NULL;
 635
 636         /* X550EM bus type is internal*/
 637         hw->bus.type = ixgbe_bus_type_internal;
 638         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 639
 640         if (hw->mac.type == ixgbe_mac_X550EM_x) {
 641                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 642                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 643                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 644                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 645                 link->ops.read_link = ixgbe_read_i2c_combined_generic;
 646                 link->ops.read_link_unlocked =
 647                                 ixgbe_read_i2c_combined_generic_unlocked;
 648                 link->ops.write_link = ixgbe_write_i2c_combined_generic;
 649                 link->ops.write_link_unlocked =
 650                                 ixgbe_write_i2c_combined_generic_unlocked;
 651                 link->addr = IXGBE_CS4227;
 652         }
 653         if (hw->mac.type == ixgbe_mac_X550EM_a) {
 654                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 655                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 656                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 657                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 658         }
 659
 660         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 661         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 662         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 663         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 664         mac->ops.get_supported_physical_layer =
 665                                     ixgbe_get_supported_physical_layer_X550em;
 666
 667         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 668                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 669         else
 670                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 671
 672         switch (hw->device_id) {
 673         case IXGBE_DEV_ID_X550EM_X_KR:
 674         case IXGBE_DEV_ID_X550EM_A_KR:
 675         case IXGBE_DEV_ID_X550EM_A_KR_L:
 676                 break;
 677         default:
 678                 mac->ops.setup_eee = NULL;
 679         }
 680
 681         /* PHY */
 682         phy->ops.init = ixgbe_init_phy_ops_X550em;
 683         phy->ops.identify = ixgbe_identify_phy_x550em;
 684         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 685                 phy->ops.set_phy_power = NULL;
 686
 687
 688         /* EEPROM */
 689         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 690         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 691         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 692         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 693         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 694         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 695         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 696         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 697
 698         return ret_val;
 699 }
 700
 701 /**
 702  *  ixgbe_dmac_config_X550
 703  *  @hw: pointer to hardware structure
 704  *
 705  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 706  *  When disabling dmac, dmac enable dmac bit is cleared.
 707  **/
 708 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 709 {
 710         u32 reg, high_pri_tc;
 711
 712         DEBUGFUNC("ixgbe_dmac_config_X550");
 713
 714         /* Disable DMA coalescing before configuring */
 715         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 716         reg &= ~IXGBE_DMACR_DMAC_EN;
 717         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 718
 719         /* Disable DMA Coalescing if the watchdog timer is 0 */
 720         if (!hw->mac.dmac_config.watchdog_timer)
 721                 goto out;
 722
 723         ixgbe_dmac_config_tcs_X550(hw);
 724
 725         /* Configure DMA Coalescing Control Register */
 726         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 727
 728         /* Set the watchdog timer in units of 40.96 usec */
 729         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 730         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 731
 732         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 733         /* If fcoe is enabled, set high priority traffic class */
 734         if (hw->mac.dmac_config.fcoe_en) {
 735                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 736                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 737                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 738         }
 739         reg |= IXGBE_DMACR_EN_MNG_IND;
 740
 741         /* Enable DMA coalescing after configuration */
 742         reg |= IXGBE_DMACR_DMAC_EN;
 743         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 744
 745 out:
 746         return IXGBE_SUCCESS;
 747 }
 748
 749 /**
 750  *  ixgbe_dmac_config_tcs_X550
 751  *  @hw: pointer to hardware structure
 752  *
 753  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 754  *  be cleared before configuring.
 755  **/
 756 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 757 {
 758         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 759
 760         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 761
 762         /* Configure DMA coalescing enabled */
 763         switch (hw->mac.dmac_config.link_speed) {
 764         case IXGBE_LINK_SPEED_100_FULL:
 765                 pb_headroom = IXGBE_DMACRXT_100M;
 766                 break;
 767         case IXGBE_LINK_SPEED_1GB_FULL:
 768                 pb_headroom = IXGBE_DMACRXT_1G;
 769                 break;
 770         default:
 771                 pb_headroom = IXGBE_DMACRXT_10G;
 772                 break;
 773         }
 774
 775         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 776                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 777
 778         /* Set the per Rx packet buffer receive threshold */
 779         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 780                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 781                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 782
 783                 if (tc < hw->mac.dmac_config.num_tcs) {
 784                         /* Get Rx PB size */
 785                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 786                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 787                                 IXGBE_RXPBSIZE_SHIFT;
 788
 789                         /* Calculate receive buffer threshold in kilobytes */
 790                         if (rx_pb_size > pb_headroom)
 791                                 rx_pb_size = rx_pb_size - pb_headroom;
 792                         else
 793                                 rx_pb_size = 0;
 794
 795                         /* Minimum of MFS shall be set for DMCTH */
 796                         reg |= (rx_pb_size > maxframe_size_kb) ?
 797                                 rx_pb_size : maxframe_size_kb;
 798                 }
 799                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 800         }
 801         return IXGBE_SUCCESS;
 802 }
 803
 804 /**
 805  *  ixgbe_dmac_update_tcs_X550
 806  *  @hw: pointer to hardware structure
 807  *
 808  *  Disables dmac, updates per TC settings, and then enables dmac.
 809  **/
 810 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 811 {
 812         u32 reg;
 813
 814         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 815
 816         /* Disable DMA coalescing before configuring */
 817         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 818         reg &= ~IXGBE_DMACR_DMAC_EN;
 819         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 820
 821         ixgbe_dmac_config_tcs_X550(hw);
 822
 823         /* Enable DMA coalescing after configuration */
 824         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 825         reg |= IXGBE_DMACR_DMAC_EN;
 826         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 827
 828         return IXGBE_SUCCESS;
 829 }
 830
 831 /**
 832  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 833  *  @hw: pointer to hardware structure
 834  *
 835  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 836  *  ixgbe_hw struct in order to set up EEPROM access.
 837  **/
 838 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 839 {
 840         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 841         u32 eec;
 842         u16 eeprom_size;
 843
 844         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 845
 846         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 847                 eeprom->semaphore_delay = 10;
 848                 eeprom->type = ixgbe_flash;
 849
 850                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 851                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 852                                     IXGBE_EEC_SIZE_SHIFT);
 853                 eeprom->word_size = 1 << (eeprom_size +
 854                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 855
 856                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 857                           eeprom->type, eeprom->word_size);
 858         }
 859
 860         return IXGBE_SUCCESS;
 861 }
 862
 863 /**
 864  * ixgbe_enable_eee_x550 - Enable EEE support
 865  * @hw: pointer to hardware structure
 866  */
 867 static s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
 868 {
 869         u16 autoneg_eee_reg;
 870         u32 link_reg;
 871         s32 status;
 872
 873         if (hw->mac.type == ixgbe_mac_X550) {
 874                 /* Advertise EEE capability */
 875                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 876                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 877                                      &autoneg_eee_reg);
 878
 879                 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 880                                     IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 881                                     IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 882
 883                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 884                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 885                                       autoneg_eee_reg);
 886                 return IXGBE_SUCCESS;
 887         }
 888
 889         switch (hw->device_id) {
 890         case IXGBE_DEV_ID_X550EM_X_KR:
 891         case IXGBE_DEV_ID_X550EM_A_KR:
 892         case IXGBE_DEV_ID_X550EM_A_KR_L:
 893                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 894                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 895                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 896                 if (status != IXGBE_SUCCESS)
 897                         return status;
 898
 899                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 900                         IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 901
 902                 /* Don't advertise FEC capability when EEE enabled. */
 903                 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 904
 905                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 906                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 907                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 908                 if (status != IXGBE_SUCCESS)
 909                         return status;
 910                 break;
 911         default:
 912                 break;
 913         }
 914
 915         return IXGBE_SUCCESS;
 916 }
 917
 918 /**
 919  * ixgbe_disable_eee_x550 - Disable EEE support
 920  * @hw: pointer to hardware structure
 921  */
 922 static s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
 923 {
 924         u16 autoneg_eee_reg;
 925         u32 link_reg;
 926         s32 status;
 927
 928         if (hw->mac.type == ixgbe_mac_X550) {
 929                 /* Disable advertised EEE capability */
 930                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 931                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 932                                      &autoneg_eee_reg);
 933
 934                 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 935                                      IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 936                                      IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 937
 938                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 939                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 940                                       autoneg_eee_reg);
 941                 return IXGBE_SUCCESS;
 942         }
 943
 944         switch (hw->device_id) {
 945         case IXGBE_DEV_ID_X550EM_X_KR:
 946         case IXGBE_DEV_ID_X550EM_A_KR:
 947         case IXGBE_DEV_ID_X550EM_A_KR_L:
 948                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 949                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 950                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 951                 if (status != IXGBE_SUCCESS)
 952                         return status;
 953
 954                 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 955                               IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 956
 957                 /* Advertise FEC capability when EEE is disabled. */
 958                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 959
 960                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 961                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 962                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 963                 if (status != IXGBE_SUCCESS)
 964                         return status;
 965                 break;
 966         default:
 967                 break;
 968         }
 969
 970         return IXGBE_SUCCESS;
 971 }
 972
 973 /**
 974  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 975  *  @hw: pointer to the HW structure
 976  *  @enable_eee: boolean flag to enable EEE
 977  *
 978  *  Enable/disable EEE based on enable_eee flag.
 979  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 980  *  are modified.
 981  *
 982  **/
 983 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 984 {
 985         s32 status;
 986         u32 eeer;
 987
 988         DEBUGFUNC("ixgbe_setup_eee_X550");
 989
 990         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 991         /* Enable or disable EEE per flag */
 992         if (enable_eee) {
 993                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 994
 995                 /* Not supported on first revision of X550EM_x. */
 996                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
 997                     !(IXGBE_FUSES0_REV_MASK &
 998                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
 999                         return IXGBE_SUCCESS;
1000                 status = ixgbe_enable_eee_x550(hw);
1001                 if (status)
1002                         return status;
1003         } else {
1004                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1005
1006                 status = ixgbe_disable_eee_x550(hw);
1007                 if (status)
1008                         return status;
1009         }
1010         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1011
1012         return IXGBE_SUCCESS;
1013 }
1014
1015 /**
1016  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1017  * @hw: pointer to hardware structure
1018  * @enable: enable or disable source address pruning
1019  * @pool: Rx pool to set source address pruning for
1020  **/
1021 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1022                                            unsigned int pool)
1023 {
1024         u64 pfflp;
1025
1026         /* max rx pool is 63 */
1027         if (pool > 63)
1028                 return;
1029
1030         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1031         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1032
1033         if (enable)
1034                 pfflp |= (1ULL << pool);
1035         else
1036                 pfflp &= ~(1ULL << pool);
1037
1038         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1039         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1040 }
1041
1042 /**
1043  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1044  *  @hw: pointer to hardware structure
1045  *  @enable: enable or disable switch for Ethertype anti-spoofing
1046  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1047  *
1048  **/
1049 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1050                 bool enable, int vf)
1051 {
1052         int vf_target_reg = vf >> 3;
1053         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1054         u32 pfvfspoof;
1055
1056         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1057
1058         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1059         if (enable)
1060                 pfvfspoof |= (1 << vf_target_shift);
1061         else
1062                 pfvfspoof &= ~(1 << vf_target_shift);
1063
1064         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1065 }
1066
1067 /**
1068  * ixgbe_iosf_wait - Wait for IOSF command completion
1069  * @hw: pointer to hardware structure
1070  * @ctrl: pointer to location to receive final IOSF control value
1071  *
1072  * Returns failing status on timeout
1073  *
1074  * Note: ctrl can be NULL if the IOSF control register value is not needed
1075  **/
1076 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1077 {
1078         u32 i, command = 0;
1079
1080         /* Check every 10 usec to see if the address cycle completed.
1081          * The SB IOSF BUSY bit will clear when the operation is
1082          * complete
1083          */
1084         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1085                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1086                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1087                         break;
1088                 usec_delay(10);
1089         }
1090         if (ctrl)
1091                 *ctrl = command;
1092         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1093                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1094                 return IXGBE_ERR_PHY;
1095         }
1096
1097         return IXGBE_SUCCESS;
1098 }
1099
1100 /**
1101  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1102  *  device
1103  *  @hw: pointer to hardware structure
1104  *  @reg_addr: 32 bit PHY register to write
1105  *  @device_type: 3 bit device type
1106  *  @data: Data to write to the register
1107  **/
1108 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1109                             u32 device_type, u32 data)
1110 {
1111         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1112         u32 command, error;
1113         s32 ret;
1114
1115         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1116         if (ret != IXGBE_SUCCESS)
1117                 return ret;
1118
1119         ret = ixgbe_iosf_wait(hw, NULL);
1120         if (ret != IXGBE_SUCCESS)
1121                 goto out;
1122
1123         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1124                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1125
1126         /* Write IOSF control register */
1127         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1128
1129         /* Write IOSF data register */
1130         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1131
1132         ret = ixgbe_iosf_wait(hw, &command);
1133
1134         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1135                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1136                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1137                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1138                               "Failed to write, error %x\n", error);
1139                 ret = IXGBE_ERR_PHY;
1140         }
1141
1142 out:
1143         ixgbe_release_swfw_semaphore(hw, gssr);
1144         return ret;
1145 }
1146
1147 /**
1148  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1149  *  device
1150  *  @hw: pointer to hardware structure
1151  *  @reg_addr: 32 bit PHY register to write
1152  *  @device_type: 3 bit device type
1153  *  @phy_data: Pointer to read data from the register
1154  **/
1155 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1156                            u32 device_type, u32 *data)
1157 {
1158         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1159         u32 command, error;
1160         s32 ret;
1161
1162         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1163         if (ret != IXGBE_SUCCESS)
1164                 return ret;
1165
1166         ret = ixgbe_iosf_wait(hw, NULL);
1167         if (ret != IXGBE_SUCCESS)
1168                 goto out;
1169
1170         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1171                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1172
1173         /* Write IOSF control register */
1174         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1175
1176         ret = ixgbe_iosf_wait(hw, &command);
1177
1178         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1179                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1180                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1181                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1182                                 "Failed to read, error %x\n", error);
1183                 ret = IXGBE_ERR_PHY;
1184         }
1185
1186         if (ret == IXGBE_SUCCESS)
1187                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1188
1189 out:
1190         ixgbe_release_swfw_semaphore(hw, gssr);
1191         return ret;
1192 }
1193
1194 /**
1195  * ixgbe_get_phy_token - Get the token for shared phy access
1196  * @hw: Pointer to hardware structure
1197  */
1198
1199 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1200 {
1201         struct ixgbe_hic_phy_token_req token_cmd;
1202         s32 status;
1203
1204         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1205         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1206         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1207         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1208         token_cmd.port_number = hw->bus.lan_id;
1209         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1210         token_cmd.pad = 0;
1211         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1212                                               sizeof(token_cmd),
1213                                               IXGBE_HI_COMMAND_TIMEOUT,
1214                                               true);
1215         if (status)
1216                 return status;
1217         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1218                 return IXGBE_SUCCESS;
1219         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1220                 return IXGBE_ERR_FW_RESP_INVALID;
1221
1222         return IXGBE_ERR_TOKEN_RETRY;
1223 }
1224
1225 /**
1226  * ixgbe_put_phy_token - Put the token for shared phy access
1227  * @hw: Pointer to hardware structure
1228  */
1229
1230 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1231 {
1232         struct ixgbe_hic_phy_token_req token_cmd;
1233         s32 status;
1234
1235         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1236         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1237         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1238         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1239         token_cmd.port_number = hw->bus.lan_id;
1240         token_cmd.command_type = FW_PHY_TOKEN_REL;
1241         token_cmd.pad = 0;
1242         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1243                                               sizeof(token_cmd),
1244                                               IXGBE_HI_COMMAND_TIMEOUT,
1245                                               true);
1246         if (status)
1247                 return status;
1248         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1249                 return IXGBE_SUCCESS;
1250
1251         DEBUGOUT("Put PHY Token host interface command failed");
1252         return IXGBE_ERR_FW_RESP_INVALID;
1253 }
1254
1255 /**
1256  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1257  *  of the IOSF device
1258  *  @hw: pointer to hardware structure
1259  *  @reg_addr: 32 bit PHY register to write
1260  *  @device_type: 3 bit device type
1261  *  @data: Data to write to the register
1262  **/
1263 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1264                                   u32 device_type, u32 data)
1265 {
1266         struct ixgbe_hic_internal_phy_req write_cmd;
1267         s32 status;
1268         UNREFERENCED_1PARAMETER(device_type);
1269
1270         memset(&write_cmd, 0, sizeof(write_cmd));
1271         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1272         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1273         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1274         write_cmd.port_number = hw->bus.lan_id;
1275         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1276         write_cmd.address = (u16)reg_addr;
1277         write_cmd.write_data = data;
1278
1279         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1280                                               sizeof(write_cmd),
1281                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1282
1283         return status;
1284 }
1285
1286 /**
1287  *  ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
1288  *  of the IOSF device.
1289  *  @hw: pointer to hardware structure
1290  *  @reg_addr: 32 bit PHY register to write
1291  *  @device_type: 3 bit device type
1292  *  @data: Pointer to read data from the register
1293  **/
1294 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1295                                  u32 device_type, u32 *data)
1296 {
1297         struct ixgbe_hic_internal_phy_req read_cmd;
1298         s32 status;
1299         UNREFERENCED_1PARAMETER(device_type);
1300
1301         memset(&read_cmd, 0, sizeof(read_cmd));
1302         read_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1303         read_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1304         read_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1305         read_cmd.port_number = hw->bus.lan_id;
1306         read_cmd.command_type = FW_INT_PHY_REQ_READ;
1307         read_cmd.address = (u16)reg_addr;
1308
1309         status = ixgbe_host_interface_command(hw, (u32 *)&read_cmd,
1310                                               sizeof(read_cmd),
1311                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1312
1313         /* Extract the register value from the response. */
1314         *data = ((struct ixgbe_hic_internal_phy_resp *)&read_cmd)->read_data;
1315
1316         return status;
1317 }
1318
1319 /**
1320  *  ixgbe_disable_mdd_X550
1321  *  @hw: pointer to hardware structure
1322  *
1323  *  Disable malicious driver detection
1324  **/
1325 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1326 {
1327         u32 reg;
1328
1329         DEBUGFUNC("ixgbe_disable_mdd_X550");
1330
1331         /* Disable MDD for TX DMA and interrupt */
1332         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1333         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1334         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1335
1336         /* Disable MDD for RX and interrupt */
1337         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1338         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1339         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1340 }
1341
1342 /**
1343  *  ixgbe_enable_mdd_X550
1344  *  @hw: pointer to hardware structure
1345  *
1346  *  Enable malicious driver detection
1347  **/
1348 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1349 {
1350         u32 reg;
1351
1352         DEBUGFUNC("ixgbe_enable_mdd_X550");
1353
1354         /* Enable MDD for TX DMA and interrupt */
1355         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1356         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1357         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1358
1359         /* Enable MDD for RX and interrupt */
1360         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1361         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1362         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1363 }
1364
1365 /**
1366  *  ixgbe_restore_mdd_vf_X550
1367  *  @hw: pointer to hardware structure
1368  *  @vf: vf index
1369  *
1370  *  Restore VF that was disabled during malicious driver detection event
1371  **/
1372 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1373 {
1374         u32 idx, reg, num_qs, start_q, bitmask;
1375
1376         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1377
1378         /* Map VF to queues */
1379         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1380         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1381         case IXGBE_MRQC_VMDQRT8TCEN:
1382                 num_qs = 8;  /* 16 VFs / pools */
1383                 bitmask = 0x000000FF;
1384                 break;
1385         case IXGBE_MRQC_VMDQRSS32EN:
1386         case IXGBE_MRQC_VMDQRT4TCEN:
1387                 num_qs = 4;  /* 32 VFs / pools */
1388                 bitmask = 0x0000000F;
1389                 break;
1390         default:            /* 64 VFs / pools */
1391                 num_qs = 2;
1392                 bitmask = 0x00000003;
1393                 break;
1394         }
1395         start_q = vf * num_qs;
1396
1397         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1398         idx = start_q / 32;
1399         reg = 0;
1400         reg |= (bitmask << (start_q % 32));
1401         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1402         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1403 }
1404
1405 /**
1406  *  ixgbe_mdd_event_X550
1407  *  @hw: pointer to hardware structure
1408  *  @vf_bitmap: vf bitmap of malicious vfs
1409  *
1410  *  Handle malicious driver detection event.
1411  **/
1412 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1413 {
1414         u32 wqbr;
1415         u32 i, j, reg, q, shift, vf, idx;
1416
1417         DEBUGFUNC("ixgbe_mdd_event_X550");
1418
1419         /* figure out pool size for mapping to vf's */
1420         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1421         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1422         case IXGBE_MRQC_VMDQRT8TCEN:
1423                 shift = 3;  /* 16 VFs / pools */
1424                 break;
1425         case IXGBE_MRQC_VMDQRSS32EN:
1426         case IXGBE_MRQC_VMDQRT4TCEN:
1427                 shift = 2;  /* 32 VFs / pools */
1428                 break;
1429         default:
1430                 shift = 1;  /* 64 VFs / pools */
1431                 break;
1432         }
1433
1434         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1435         for (i = 0; i < 4; i++) {
1436                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1437                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1438
1439                 if (!wqbr)
1440                         continue;
1441
1442                 /* Get malicious queue */
1443                 for (j = 0; j < 32 && wqbr; j++) {
1444
1445                         if (!(wqbr & (1 << j)))
1446                                 continue;
1447
1448                         /* Get queue from bitmask */
1449                         q = j + (i * 32);
1450
1451                         /* Map queue to vf */
1452                         vf = (q >> shift);
1453
1454                         /* Set vf bit in vf_bitmap */
1455                         idx = vf / 32;
1456                         vf_bitmap[idx] |= (1 << (vf % 32));
1457                         wqbr &= ~(1 << j);
1458                 }
1459         }
1460 }
1461
1462 /**
1463  *  ixgbe_get_media_type_X550em - Get media type
1464  *  @hw: pointer to hardware structure
1465  *
1466  *  Returns the media type (fiber, copper, backplane)
1467  */
1468 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1469 {
1470         enum ixgbe_media_type media_type;
1471
1472         DEBUGFUNC("ixgbe_get_media_type_X550em");
1473
1474         /* Detect if there is a copper PHY attached. */
1475         switch (hw->device_id) {
1476         case IXGBE_DEV_ID_X550EM_X_KR:
1477         case IXGBE_DEV_ID_X550EM_X_KX4:
1478         case IXGBE_DEV_ID_X550EM_A_KR:
1479         case IXGBE_DEV_ID_X550EM_A_KR_L:
1480                 media_type = ixgbe_media_type_backplane;
1481                 break;
1482         case IXGBE_DEV_ID_X550EM_X_SFP:
1483         case IXGBE_DEV_ID_X550EM_A_SFP:
1484         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1485         case IXGBE_DEV_ID_X550EM_A_QSFP:
1486         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1487                 media_type = ixgbe_media_type_fiber;
1488                 break;
1489         case IXGBE_DEV_ID_X550EM_X_1G_T:
1490         case IXGBE_DEV_ID_X550EM_X_10G_T:
1491         case IXGBE_DEV_ID_X550EM_A_10G_T:
1492                 media_type = ixgbe_media_type_copper;
1493                 break;
1494         case IXGBE_DEV_ID_X550EM_A_SGMII:
1495         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1496                 media_type = ixgbe_media_type_backplane;
1497                 hw->phy.type = ixgbe_phy_sgmii;
1498                 break;
1499         case IXGBE_DEV_ID_X550EM_A_1G_T:
1500         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1501                 media_type = ixgbe_media_type_copper;
1502                 hw->phy.type = ixgbe_phy_m88;
1503                 break;
1504         default:
1505                 media_type = ixgbe_media_type_unknown;
1506                 break;
1507         }
1508         return media_type;
1509 }
1510
1511 /**
1512  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1513  *  @hw: pointer to hardware structure
1514  *  @linear: true if SFP module is linear
1515  */
1516 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1517 {
1518         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1519
1520         switch (hw->phy.sfp_type) {
1521         case ixgbe_sfp_type_not_present:
1522                 return IXGBE_ERR_SFP_NOT_PRESENT;
1523         case ixgbe_sfp_type_da_cu_core0:
1524         case ixgbe_sfp_type_da_cu_core1:
1525                 *linear = true;
1526                 break;
1527         case ixgbe_sfp_type_srlr_core0:
1528         case ixgbe_sfp_type_srlr_core1:
1529         case ixgbe_sfp_type_da_act_lmt_core0:
1530         case ixgbe_sfp_type_da_act_lmt_core1:
1531         case ixgbe_sfp_type_1g_sx_core0:
1532         case ixgbe_sfp_type_1g_sx_core1:
1533         case ixgbe_sfp_type_1g_lx_core0:
1534         case ixgbe_sfp_type_1g_lx_core1:
1535                 *linear = false;
1536                 break;
1537         case ixgbe_sfp_type_unknown:
1538         case ixgbe_sfp_type_1g_cu_core0:
1539         case ixgbe_sfp_type_1g_cu_core1:
1540         default:
1541                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1542         }
1543
1544         return IXGBE_SUCCESS;
1545 }
1546
1547 /**
1548  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1549  *  @hw: pointer to hardware structure
1550  *
1551  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1552  **/
1553 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1554 {
1555         s32 status;
1556         bool linear;
1557
1558         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1559
1560         status = ixgbe_identify_module_generic(hw);
1561
1562         if (status != IXGBE_SUCCESS)
1563                 return status;
1564
1565         /* Check if SFP module is supported */
1566         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1567
1568         return status;
1569 }
1570
1571 /**
1572  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1573  *  @hw: pointer to hardware structure
1574  */
1575 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1576 {
1577         s32 status;
1578         bool linear;
1579
1580         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1581
1582         /* Check if SFP module is supported */
1583         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1584
1585         if (status != IXGBE_SUCCESS)
1586                 return status;
1587
1588         ixgbe_init_mac_link_ops_X550em(hw);
1589         hw->phy.ops.reset = NULL;
1590
1591         return IXGBE_SUCCESS;
1592 }
1593
1594 /**
1595  * ixgbe_setup_sgmii - Set up link for sgmii
1596  * @hw: pointer to hardware structure
1597  */
1598 static s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1599                              bool autoneg_wait_to_complete)
1600 {
1601         struct ixgbe_mac_info *mac = &hw->mac;
1602         u32 lval, sval;
1603         s32 rc;
1604         UNREFERENCED_2PARAMETER(speed, autoneg_wait_to_complete);
1605
1606         rc = mac->ops.read_iosf_sb_reg(hw,
1607                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1608                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1609         if (rc)
1610                 return rc;
1611
1612         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1613         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1614         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1615         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1616         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1617         rc = mac->ops.write_iosf_sb_reg(hw,
1618                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1619                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1620         if (rc)
1621                 return rc;
1622
1623         rc = mac->ops.read_iosf_sb_reg(hw,
1624                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1625                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1626         if (rc)
1627                 return rc;
1628
1629         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1630         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1631         rc = mac->ops.write_iosf_sb_reg(hw,
1632                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1633                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1634         if (rc)
1635                 return rc;
1636
1637         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1638         rc = mac->ops.write_iosf_sb_reg(hw,
1639                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1640                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1641
1642         return rc;
1643 }
1644
1645 /**
1646  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1647  *  @hw: pointer to hardware structure
1648  */
1649 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1650 {
1651         struct ixgbe_mac_info *mac = &hw->mac;
1652
1653         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1654
1655         switch (hw->mac.ops.get_media_type(hw)) {
1656         case ixgbe_media_type_fiber:
1657                 /* CS4227 does not support autoneg, so disable the laser control
1658                  * functions for SFP+ fiber
1659                  */
1660                 mac->ops.disable_tx_laser = NULL;
1661                 mac->ops.enable_tx_laser = NULL;
1662                 mac->ops.flap_tx_laser = NULL;
1663                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1664                 mac->ops.set_rate_select_speed =
1665                                         ixgbe_set_soft_rate_select_speed;
1666                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1667                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1668                         mac->ops.setup_mac_link =
1669                                 ixgbe_setup_mac_link_sfp_x550a;
1670                 else
1671                         mac->ops.setup_mac_link =
1672                                 ixgbe_setup_mac_link_sfp_x550em;
1673                 break;
1674         case ixgbe_media_type_copper:
1675                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1676                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1677                 break;
1678         case ixgbe_media_type_backplane:
1679                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1680                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1681                         mac->ops.setup_link = ixgbe_setup_sgmii;
1682                 break;
1683         default:
1684                 break;
1685         }
1686 }
1687
1688 /**
1689  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1690  *  @hw: pointer to hardware structure
1691  *  @speed: pointer to link speed
1692  *  @autoneg: true when autoneg or autotry is enabled
1693  */
1694 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1695                                        ixgbe_link_speed *speed,
1696                                        bool *autoneg)
1697 {
1698         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1699
1700         /* SFP */
1701         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1702
1703                 /* CS4227 SFP must not enable auto-negotiation */
1704                 *autoneg = false;
1705
1706                 /* Check if 1G SFP module. */
1707                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1708                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1709                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1710                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1711                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1712                         return IXGBE_SUCCESS;
1713                 }
1714
1715                 /* Link capabilities are based on SFP */
1716                 if (hw->phy.multispeed_fiber)
1717                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1718                                  IXGBE_LINK_SPEED_1GB_FULL;
1719                 else
1720                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1721         } else {
1722                 switch (hw->phy.type) {
1723                 case ixgbe_phy_m88:
1724                         *speed = IXGBE_LINK_SPEED_100_FULL |
1725                                  IXGBE_LINK_SPEED_1GB_FULL;
1726                         break;
1727                 case ixgbe_phy_sgmii:
1728                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1729                         break;
1730                 default:
1731                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1732                                  IXGBE_LINK_SPEED_1GB_FULL;
1733                         break;
1734                 }
1735                 *autoneg = true;
1736         }
1737
1738         return IXGBE_SUCCESS;
1739 }
1740
1741 /**
1742  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1743  * @hw: pointer to hardware structure
1744  * @lsc: pointer to boolean flag which indicates whether external Base T
1745  *       PHY interrupt is lsc
1746  *
1747  * Determime if external Base T PHY interrupt cause is high temperature
1748  * failure alarm or link status change.
1749  *
1750  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1751  * failure alarm, else return PHY access status.
1752  */
1753 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1754 {
1755         u32 status;
1756         u16 reg;
1757
1758         *lsc = false;
1759
1760         /* Vendor alarm triggered */
1761         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1762                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1763                                       &reg);
1764
1765         if (status != IXGBE_SUCCESS ||
1766             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1767                 return status;
1768
1769         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1770         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1771                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1772                                       &reg);
1773
1774         if (status != IXGBE_SUCCESS ||
1775             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1776             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1777                 return status;
1778
1779         /* Global alarm triggered */
1780         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1781                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1782                                       &reg);
1783
1784         if (status != IXGBE_SUCCESS)
1785                 return status;
1786
1787         /* If high temperature failure, then return over temp error and exit */
1788         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1789                 /* power down the PHY in case the PHY FW didn't already */
1790                 ixgbe_set_copper_phy_power(hw, false);
1791                 return IXGBE_ERR_OVERTEMP;
1792         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1793                 /*  device fault alarm triggered */
1794                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1795                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1796                                           &reg);
1797
1798                 if (status != IXGBE_SUCCESS)
1799                         return status;
1800
1801                 /* if device fault was due to high temp alarm handle and exit */
1802                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1803                         /* power down the PHY in case the PHY FW didn't */
1804                         ixgbe_set_copper_phy_power(hw, false);
1805                         return IXGBE_ERR_OVERTEMP;
1806                 }
1807         }
1808
1809         /* Vendor alarm 2 triggered */
1810         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1811                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1812
1813         if (status != IXGBE_SUCCESS ||
1814             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1815                 return status;
1816
1817         /* link connect/disconnect event occurred */
1818         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1819                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1820
1821         if (status != IXGBE_SUCCESS)
1822                 return status;
1823
1824         /* Indicate LSC */
1825         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1826                 *lsc = true;
1827
1828         return IXGBE_SUCCESS;
1829 }
1830
1831 /**
1832  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1833  * @hw: pointer to hardware structure
1834  *
1835  * Enable link status change and temperature failure alarm for the external
1836  * Base T PHY
1837  *
1838  * Returns PHY access status
1839  */
1840 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1841 {
1842         u32 status;
1843         u16 reg;
1844         bool lsc;
1845
1846         /* Clear interrupt flags */
1847         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1848
1849         /* Enable link status change alarm */
1850         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1851                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1852
1853         if (status != IXGBE_SUCCESS)
1854                 return status;
1855
1856         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1857
1858         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1859                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1860
1861         if (status != IXGBE_SUCCESS)
1862                 return status;
1863
1864         /* Enable high temperature failure and global fault alarms */
1865         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1866                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1867                                       &reg);
1868
1869         if (status != IXGBE_SUCCESS)
1870                 return status;
1871
1872         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1873                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1874
1875         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1876                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1877                                        reg);
1878
1879         if (status != IXGBE_SUCCESS)
1880                 return status;
1881
1882         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1883         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1884                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1885                                       &reg);
1886
1887         if (status != IXGBE_SUCCESS)
1888                 return status;
1889
1890         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1891                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1892
1893         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1894                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1895                                        reg);
1896
1897         if (status != IXGBE_SUCCESS)
1898                 return status;
1899
1900         /* Enable chip-wide vendor alarm */
1901         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1902                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1903                                       &reg);
1904
1905         if (status != IXGBE_SUCCESS)
1906                 return status;
1907
1908         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1909
1910         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1911                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1912                                        reg);
1913
1914         return status;
1915 }
1916
1917 /**
1918  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1919  *  @hw: pointer to hardware structure
1920  *  @speed: link speed
1921  *
1922  *  Configures the integrated KR PHY.
1923  **/
1924 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1925                                        ixgbe_link_speed speed)
1926 {
1927         s32 status;
1928         u32 reg_val;
1929
1930         status = hw->mac.ops.read_iosf_sb_reg(hw,
1931                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1932                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1933         if (status)
1934                 return status;
1935
1936         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1937         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1938                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1939
1940         /* Advertise 10G support. */
1941         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1942                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1943
1944         /* Advertise 1G support. */
1945         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1946                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1947
1948         /* Restart auto-negotiation. */
1949         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1950         status = hw->mac.ops.write_iosf_sb_reg(hw,
1951                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1952                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1953
1954         return status;
1955 }
1956
1957 /**
1958  * ixgbe_set_master_slave_mode - Set up PHY for master/slave mode
1959  * @hw: pointer to hardware structure
1960  *
1961  * Must be called while holding the PHY semaphore and token
1962  */
1963 static s32 ixgbe_set_master_slave_mode(struct ixgbe_hw *hw)
1964 {
1965         u16 phy_data;
1966         s32 rc;
1967
1968         /* Resolve master/slave mode */
1969         rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_M88E1500_1000T_CTRL, 0,
1970                                        &phy_data);
1971         if (rc)
1972                 return rc;
1973
1974         /* load defaults for future use */
1975         if (phy_data & IXGBE_M88E1500_1000T_CTRL_MS_ENABLE) {
1976                 if (phy_data & IXGBE_M88E1500_1000T_CTRL_MS_VALUE)
1977                         hw->phy.original_ms_type = ixgbe_ms_force_master;
1978                 else
1979                         hw->phy.original_ms_type = ixgbe_ms_force_slave;
1980         } else {
1981                 hw->phy.original_ms_type = ixgbe_ms_auto;
1982         }
1983
1984         switch (hw->phy.ms_type) {
1985         case ixgbe_ms_force_master:
1986                 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
1987                 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_VALUE;
1988                 break;
1989         case ixgbe_ms_force_slave:
1990                 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
1991                 phy_data &= ~IXGBE_M88E1500_1000T_CTRL_MS_VALUE;
1992                 break;
1993         case ixgbe_ms_auto:
1994                 phy_data &= ~IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
1995                 break;
1996         default:
1997                 break;
1998         }
1999
2000         return ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_1000T_CTRL, 0,
2001                                           phy_data);
2002 }
2003
2004 /**
2005  * ixgbe_reset_phy_m88_nolock - Reset m88 PHY without locking
2006  * @hw: pointer to hardware structure
2007  *
2008  * Must be called while holding the PHY semaphore and token
2009  */
2010 static s32 ixgbe_reset_phy_m88_nolock(struct ixgbe_hw *hw)
2011 {
2012         s32 rc;
2013
2014         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2015         if (rc)
2016                 return rc;
2017
2018         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_FIBER_CTRL, 0,
2019                                         IXGBE_M88E1500_FIBER_CTRL_RESET |
2020                                         IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2021                                         IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB);
2022         if (rc)
2023                 goto res_out;
2024
2025         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2026         if (rc)
2027                 goto res_out;
2028
2029         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_GEN_CTRL, 0,
2030                                         IXGBE_M88E1500_GEN_CTRL_RESET |
2031                                         IXGBE_M88E1500_GEN_CTRL_SGMII_COPPER);
2032         if (rc)
2033                 goto res_out;
2034
2035         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2036         if (rc)
2037                 goto res_out;
2038
2039         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2040                                         IXGBE_M88E1500_COPPER_CTRL_RESET |
2041                                         IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2042                                         IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2043                                         IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2044                                         IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB);
2045
2046 res_out:
2047         ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2048         return rc;
2049 }
2050
2051 /**
2052  * ixgbe_reset_phy_m88 - Reset m88 PHY
2053  * @hw: pointer to hardware structure
2054  */
2055 static s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2056 {
2057         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2058         s32 rc;
2059
2060         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2061                 return IXGBE_SUCCESS;
2062
2063         rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2064         if (rc)
2065                 return rc;
2066
2067         rc = ixgbe_reset_phy_m88_nolock(hw);
2068
2069         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2070         return rc;
2071 }
2072
2073 /**
2074  * ixgbe_setup_m88 - setup m88 PHY
2075  * @hw: pointer to hardware structure
2076  */
2077 static s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2078 {
2079         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2080         struct ixgbe_phy_info *phy = &hw->phy;
2081         u16 phy_data;
2082         s32 rc;
2083
2084         if (phy->reset_disable || ixgbe_check_reset_blocked(hw))
2085                 return IXGBE_SUCCESS;
2086
2087         rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2088         if (rc)
2089                 return rc;
2090
2091         rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_M88E1500_PHY_SPEC_CTRL, 0,
2092                                        &phy_data);
2093         if (rc)
2094                 goto rel_out;
2095
2096         /* Enable downshift and setting it to X6 */
2097         phy_data &= ~IXGBE_M88E1500_PSCR_DOWNSHIFT_ENABLE;
2098         phy_data |= IXGBE_M88E1500_PSCR_DOWNSHIFT_6X;
2099         phy_data |= IXGBE_M88E1500_PSCR_DOWNSHIFT_ENABLE;
2100         rc = ixgbe_write_phy_reg_mdi_22(hw,
2101                                         IXGBE_M88E1500_PHY_SPEC_CTRL, 0,
2102                                         phy_data);
2103         if (rc)
2104                 goto rel_out;
2105
2106         ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2107
2108         /* Commit the changes */
2109         rc = ixgbe_reset_phy_m88_nolock(hw);
2110         if (rc) {
2111                 DEBUGOUT("Error committing the PHY changes\n");
2112                 goto rel_out;
2113         }
2114
2115         rc = ixgbe_set_master_slave_mode(hw);
2116
2117         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2118         return rc;
2119
2120 rel_out:
2121         ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2122         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2123         return rc;
2124 }
2125
2126 /**
2127  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2128  *  @hw: pointer to hardware structure
2129  *
2130  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2131  *  values.
2132  **/
2133 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2134 {
2135         /* Save NW management interface connected on board. This is used
2136          * to determine internal PHY mode.
2137          */
2138         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2139
2140         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2141          * PHY address. This register field was has only been used for X552.
2142          */
2143         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2144             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2145                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2146                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2147                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2148         }
2149
2150         return IXGBE_SUCCESS;
2151 }
2152
2153 /**
2154  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2155  *  @hw: pointer to hardware structure
2156  *
2157  *  Initialize any function pointers that were not able to be
2158  *  set during init_shared_code because the PHY/SFP type was
2159  *  not known.  Perform the SFP init if necessary.
2160  */
2161 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2162 {
2163         struct ixgbe_phy_info *phy = &hw->phy;
2164         s32 ret_val;
2165
2166         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2167
2168         hw->mac.ops.set_lan_id(hw);
2169
2170         ixgbe_read_mng_if_sel_x550em(hw);
2171
2172         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2173                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2174                 ixgbe_setup_mux_ctl(hw);
2175                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2176         }
2177
2178         /* Identify the PHY or SFP module */
2179         ret_val = phy->ops.identify(hw);
2180         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2181                 return ret_val;
2182
2183         /* Setup function pointers based on detected hardware */
2184         ixgbe_init_mac_link_ops_X550em(hw);
2185         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2186                 phy->ops.reset = NULL;
2187
2188         /* Set functions pointers based on phy type */
2189         switch (hw->phy.type) {
2190         case ixgbe_phy_x550em_kx4:
2191                 phy->ops.setup_link = NULL;
2192                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2193                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2194                 break;
2195         case ixgbe_phy_x550em_kr:
2196                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2197                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2198                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2199                 break;
2200         case ixgbe_phy_x550em_ext_t:
2201                 /* If internal link mode is XFI, then setup iXFI internal link,
2202                  * else setup KR now.
2203                  */
2204                 phy->ops.setup_internal_link =
2205                                               ixgbe_setup_internal_phy_t_x550em;
2206
2207                 /* setup SW LPLU only for first revision of X550EM_x */
2208                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2209                     !(IXGBE_FUSES0_REV_MASK &
2210                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2211                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2212
2213                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2214                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2215                 break;
2216         case ixgbe_phy_sgmii:
2217                 phy->ops.setup_link = NULL;
2218                 break;
2219         case ixgbe_phy_m88:
2220                 phy->ops.setup_link = ixgbe_setup_m88;
2221                 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2222                 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2223                 phy->ops.reset = ixgbe_reset_phy_m88;
2224                 break;
2225         default:
2226                 break;
2227         }
2228         return ret_val;
2229 }
2230
2231 /**
2232  * ixgbe_set_mdio_speed - Set MDIO clock speed
2233  *  @hw: pointer to hardware structure
2234  */
2235 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2236 {
2237         u32 hlreg0;
2238
2239         switch (hw->device_id) {
2240         case IXGBE_DEV_ID_X550EM_X_10G_T:
2241         case IXGBE_DEV_ID_X550EM_A_SGMII:
2242         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2243         case IXGBE_DEV_ID_X550EM_A_1G_T:
2244         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2245         case IXGBE_DEV_ID_X550EM_A_10G_T:
2246         case IXGBE_DEV_ID_X550EM_A_SFP:
2247         case IXGBE_DEV_ID_X550EM_A_QSFP:
2248                 /* Config MDIO clock speed before the first MDIO PHY access */
2249                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2250                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2251                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2252                 break;
2253         default:
2254                 break;
2255         }
2256 }
2257
2258 /**
2259  *  ixgbe_reset_hw_X550em - Perform hardware reset
2260  *  @hw: pointer to hardware structure
2261  *
2262  *  Resets the hardware by resetting the transmit and receive units, masks
2263  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2264  *  reset.
2265  */
2266 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2267 {
2268         ixgbe_link_speed link_speed;
2269         s32 status;
2270         u32 ctrl = 0;
2271         u32 i;
2272         bool link_up = false;
2273
2274         DEBUGFUNC("ixgbe_reset_hw_X550em");
2275
2276         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2277         status = hw->mac.ops.stop_adapter(hw);
2278         if (status != IXGBE_SUCCESS)
2279                 return status;
2280
2281         /* flush pending Tx transactions */
2282         ixgbe_clear_tx_pending(hw);
2283
2284         ixgbe_set_mdio_speed(hw);
2285
2286         /* PHY ops must be identified and initialized prior to reset */
2287         status = hw->phy.ops.init(hw);
2288
2289         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2290                 return status;
2291
2292         /* start the external PHY */
2293         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2294                 status = ixgbe_init_ext_t_x550em(hw);
2295                 if (status)
2296                         return status;
2297         }
2298
2299         /* Setup SFP module if there is one present. */
2300         if (hw->phy.sfp_setup_needed) {
2301                 status = hw->mac.ops.setup_sfp(hw);
2302                 hw->phy.sfp_setup_needed = false;
2303         }
2304
2305         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2306                 return status;
2307
2308         /* Reset PHY */
2309         if (!hw->phy.reset_disable && hw->phy.ops.reset)
2310                 hw->phy.ops.reset(hw);
2311
2312 mac_reset_top:
2313         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2314          * If link reset is used when link is up, it might reset the PHY when
2315          * mng is using it.  If link is down or the flag to force full link
2316          * reset is set, then perform link reset.
2317          */
2318         ctrl = IXGBE_CTRL_LNK_RST;
2319         if (!hw->force_full_reset) {
2320                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2321                 if (link_up)
2322                         ctrl = IXGBE_CTRL_RST;
2323         }
2324
2325         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2326         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2327         IXGBE_WRITE_FLUSH(hw);
2328
2329         /* Poll for reset bit to self-clear meaning reset is complete */
2330         for (i = 0; i < 10; i++) {
2331                 usec_delay(1);
2332                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2333                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2334                         break;
2335         }
2336
2337         if (ctrl & IXGBE_CTRL_RST_MASK) {
2338                 status = IXGBE_ERR_RESET_FAILED;
2339                 DEBUGOUT("Reset polling failed to complete.\n");
2340         }
2341
2342         msec_delay(50);
2343
2344         /* Double resets are required for recovery from certain error
2345          * conditions.  Between resets, it is necessary to stall to
2346          * allow time for any pending HW events to complete.
2347          */
2348         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2349                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2350                 goto mac_reset_top;
2351         }
2352
2353         /* Store the permanent mac address */
2354         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2355
2356         /* Store MAC address from RAR0, clear receive address registers, and
2357          * clear the multicast table.  Also reset num_rar_entries to 128,
2358          * since we modify this value when programming the SAN MAC address.
2359          */
2360         hw->mac.num_rar_entries = 128;
2361         hw->mac.ops.init_rx_addrs(hw);
2362
2363         ixgbe_set_mdio_speed(hw);
2364
2365         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2366                 ixgbe_setup_mux_ctl(hw);
2367
2368         return status;
2369 }
2370
2371 /**
2372  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2373  * @hw: pointer to hardware structure
2374  */
2375 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2376 {
2377         u32 status;
2378         u16 reg;
2379
2380         status = hw->phy.ops.read_reg(hw,
2381                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2382                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2383                                       &reg);
2384
2385         if (status != IXGBE_SUCCESS)
2386                 return status;
2387
2388         /* If PHY FW reset completed bit is set then this is the first
2389          * SW instance after a power on so the PHY FW must be un-stalled.
2390          */
2391         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2392                 status = hw->phy.ops.read_reg(hw,
2393                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2394                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2395                                         &reg);
2396
2397                 if (status != IXGBE_SUCCESS)
2398                         return status;
2399
2400                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2401
2402                 status = hw->phy.ops.write_reg(hw,
2403                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2404                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2405                                         reg);
2406
2407                 if (status != IXGBE_SUCCESS)
2408                         return status;
2409         }
2410
2411         return status;
2412 }
2413
2414 /**
2415  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2416  *  @hw: pointer to hardware structure
2417  *
2418  *  Configures the integrated KR PHY for X550EM_x.
2419  **/
2420 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2421 {
2422         if (hw->mac.type != ixgbe_mac_X550EM_x)
2423                 return IXGBE_SUCCESS;
2424
2425         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2426 }
2427
2428 /**
2429  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2430  *  @hw: pointer to hardware structure
2431  *
2432  *  Configure the external PHY and the integrated KR PHY for SFP support.
2433  **/
2434 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2435                                     ixgbe_link_speed speed,
2436                                     bool autoneg_wait_to_complete)
2437 {
2438         s32 ret_val;
2439         u16 reg_slice, reg_val;
2440         bool setup_linear = false;
2441         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2442
2443         /* Check if SFP module is supported and linear */
2444         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2445
2446         /* If no SFP module present, then return success. Return success since
2447          * there is no reason to configure CS4227 and SFP not present error is
2448          * not excepted in the setup MAC link flow.
2449          */
2450         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2451                 return IXGBE_SUCCESS;
2452
2453         if (ret_val != IXGBE_SUCCESS)
2454                 return ret_val;
2455
2456         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2457                 /* Configure CS4227 LINE side to 10G SR. */
2458                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2459                             (hw->bus.lan_id << 12);
2460                 reg_val = IXGBE_CS4227_SPEED_10G;
2461                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2462                                                   reg_val);
2463
2464                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2465                             (hw->bus.lan_id << 12);
2466                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2467                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2468                                                   reg_val);
2469
2470                 /* Configure CS4227 for HOST connection rate then type. */
2471                 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2472                             (hw->bus.lan_id << 12);
2473                 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2474                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2475                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2476                                                   reg_val);
2477
2478                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2479                             (hw->bus.lan_id << 12);
2480                 if (setup_linear)
2481                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2482                 else
2483                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2484                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2485                                                   reg_val);
2486
2487                 /* Setup XFI internal link. */
2488                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2489         } else {
2490                 /* Configure internal PHY for KR/KX. */
2491                 ixgbe_setup_kr_speed_x550em(hw, speed);
2492
2493                 /* Configure CS4227 LINE side to proper mode. */
2494                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2495                             (hw->bus.lan_id << 12);
2496                 if (setup_linear)
2497                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2498                 else
2499                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2500                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2501                                                   reg_val);
2502         }
2503         return ret_val;
2504 }
2505
2506 /**
2507  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2508  *  @hw: pointer to hardware structure
2509  *
2510  *  Configure the the integrated PHY for SFP support.
2511  **/
2512 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2513                                    ixgbe_link_speed speed,
2514                                    bool autoneg_wait_to_complete)
2515 {
2516         s32 ret_val;
2517         u16 reg_phy_ext;
2518         bool setup_linear = false;
2519         u32 reg_slice, reg_phy_int, slice_offset;
2520
2521         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2522
2523         /* Check if SFP module is supported and linear */
2524         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2525
2526         /* If no SFP module present, then return success. Return success since
2527          * SFP not present error is not excepted in the setup MAC link flow.
2528          */
2529         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2530                 return IXGBE_SUCCESS;
2531
2532         if (ret_val != IXGBE_SUCCESS)
2533                 return ret_val;
2534
2535         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2536                 /* Configure internal PHY for native SFI */
2537                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2538                                IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2539                                IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2540
2541                 if (ret_val != IXGBE_SUCCESS)
2542                         return ret_val;
2543
2544                 if (setup_linear) {
2545                         reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2546                         reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2547                 } else {
2548                         reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2549                         reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2550                 }
2551
2552                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2553                                 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2554                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2555
2556                 if (ret_val != IXGBE_SUCCESS)
2557                         return ret_val;
2558
2559                 /* Setup XFI/SFI internal link. */
2560                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2561         } else {
2562                 /* Configure internal PHY for KR/KX. */
2563                 ixgbe_setup_kr_speed_x550em(hw, speed);
2564
2565                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2566                         /* Find Address */
2567                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2568                         return IXGBE_ERR_PHY_ADDR_INVALID;
2569                 }
2570
2571                 /* Get external PHY device id */
2572                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2573                                        IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2574
2575                 if (ret_val != IXGBE_SUCCESS)
2576                         return ret_val;
2577
2578                 /* When configuring quad port CS4223, the MAC instance is part
2579                  * of the slice offset.
2580                  */
2581                 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2582                         slice_offset = (hw->bus.lan_id +
2583                                         (hw->bus.instance_id << 1)) << 12;
2584                 else
2585                         slice_offset = hw->bus.lan_id << 12;
2586
2587                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2588                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2589                 if (setup_linear)
2590                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2591                 else
2592                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2593                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2594                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2595         }
2596         return ret_val;
2597 }
2598
2599 /**
2600  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2601  *  @hw: pointer to hardware structure
2602  *
2603  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2604  **/
2605 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2606 {
2607         s32 status;
2608         u32 reg_val;
2609
2610         /* Disable training protocol FSM. */
2611         status = ixgbe_read_iosf_sb_reg_x550(hw,
2612                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2613                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2614         if (status != IXGBE_SUCCESS)
2615                 return status;
2616         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2617         status = ixgbe_write_iosf_sb_reg_x550(hw,
2618                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2619                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2620         if (status != IXGBE_SUCCESS)
2621                 return status;
2622
2623         /* Disable Flex from training TXFFE. */
2624         status = ixgbe_read_iosf_sb_reg_x550(hw,
2625                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2626                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2627         if (status != IXGBE_SUCCESS)
2628                 return status;
2629         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2630         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2631         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2632         status = ixgbe_write_iosf_sb_reg_x550(hw,
2633                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2634                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2635         if (status != IXGBE_SUCCESS)
2636                 return status;
2637         status = ixgbe_read_iosf_sb_reg_x550(hw,
2638                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2639                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2640         if (status != IXGBE_SUCCESS)
2641                 return status;
2642         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2643         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2644         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2645         status = ixgbe_write_iosf_sb_reg_x550(hw,
2646                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2647                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2648         if (status != IXGBE_SUCCESS)
2649                 return status;
2650
2651         /* Enable override for coefficients. */
2652         status = ixgbe_read_iosf_sb_reg_x550(hw,
2653                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2654                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2655         if (status != IXGBE_SUCCESS)
2656                 return status;
2657         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2658         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2659         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2660         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2661         status = ixgbe_write_iosf_sb_reg_x550(hw,
2662                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2663                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2664         return status;
2665 }
2666
2667 /**
2668  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2669  *  @hw: pointer to hardware structure
2670  *  @speed: the link speed to force
2671  *
2672  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2673  *  internal and external PHY at a specific speed, without autonegotiation.
2674  **/
2675 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2676 {
2677         s32 status;
2678         u32 reg_val;
2679
2680         /* Disable AN and force speed to 10G Serial. */
2681         status = ixgbe_read_iosf_sb_reg_x550(hw,
2682                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2683                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2684         if (status != IXGBE_SUCCESS)
2685                 return status;
2686
2687         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2688         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2689
2690         /* Select forced link speed for internal PHY. */
2691         switch (*speed) {
2692         case IXGBE_LINK_SPEED_10GB_FULL:
2693                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2694                 break;
2695         case IXGBE_LINK_SPEED_1GB_FULL:
2696                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2697                 break;
2698         default:
2699                 /* Other link speeds are not supported by internal KR PHY. */
2700                 return IXGBE_ERR_LINK_SETUP;
2701         }
2702
2703         status = ixgbe_write_iosf_sb_reg_x550(hw,
2704                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2705                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2706         if (status != IXGBE_SUCCESS)
2707                 return status;
2708
2709         /* Additional configuration needed for x550em_x */
2710         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2711                 status = ixgbe_setup_ixfi_x550em_x(hw);
2712                 if (status != IXGBE_SUCCESS)
2713                         return status;
2714         }
2715
2716         /* Toggle port SW reset by AN reset. */
2717         status = ixgbe_read_iosf_sb_reg_x550(hw,
2718                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2719                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2720         if (status != IXGBE_SUCCESS)
2721                 return status;
2722         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2723         status = ixgbe_write_iosf_sb_reg_x550(hw,
2724                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2725                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2726
2727         return status;
2728 }
2729
2730 /**
2731  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2732  * @hw: address of hardware structure
2733  * @link_up: address of boolean to indicate link status
2734  *
2735  * Returns error code if unable to get link status.
2736  */
2737 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2738 {
2739         u32 ret;
2740         u16 autoneg_status;
2741
2742         *link_up = false;
2743
2744         /* read this twice back to back to indicate current status */
2745         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2746                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2747                                    &autoneg_status);
2748         if (ret != IXGBE_SUCCESS)
2749                 return ret;
2750
2751         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2752                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2753                                    &autoneg_status);
2754         if (ret != IXGBE_SUCCESS)
2755                 return ret;
2756
2757         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2758
2759         return IXGBE_SUCCESS;
2760 }
2761
2762 /**
2763  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2764  * @hw: point to hardware structure
2765  *
2766  * Configures the link between the integrated KR PHY and the external X557 PHY
2767  * The driver will call this function when it gets a link status change
2768  * interrupt from the X557 PHY. This function configures the link speed
2769  * between the PHYs to match the link speed of the BASE-T link.
2770  *
2771  * A return of a non-zero value indicates an error, and the base driver should
2772  * not report link up.
2773  */
2774 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2775 {
2776         ixgbe_link_speed force_speed;
2777         bool link_up;
2778         u32 status;
2779         u16 speed;
2780
2781         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2782                 return IXGBE_ERR_CONFIG;
2783
2784         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2785                 /* If link is down, there is no setup necessary so return  */
2786                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2787                 if (status != IXGBE_SUCCESS)
2788                         return status;
2789
2790                 if (!link_up)
2791                         return IXGBE_SUCCESS;
2792
2793                 status = hw->phy.ops.read_reg(hw,
2794                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2795                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2796                                               &speed);
2797                 if (status != IXGBE_SUCCESS)
2798                         return status;
2799
2800                 /* If link is still down - no setup is required so return */
2801                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2802                 if (status != IXGBE_SUCCESS)
2803                         return status;
2804                 if (!link_up)
2805                         return IXGBE_SUCCESS;
2806
2807                 /* clear everything but the speed and duplex bits */
2808                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2809
2810                 switch (speed) {
2811                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2812                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2813                         break;
2814                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2815                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2816                         break;
2817                 default:
2818                         /* Internal PHY does not support anything else */
2819                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
2820                 }
2821
2822                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2823         } else {
2824                 speed = IXGBE_LINK_SPEED_10GB_FULL |
2825                         IXGBE_LINK_SPEED_1GB_FULL;
2826                 return ixgbe_setup_kr_speed_x550em(hw, speed);
2827         }
2828 }
2829
2830 /**
2831  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2832  *  @hw: pointer to hardware structure
2833  *
2834  *  Configures the integrated KR PHY to use internal loopback mode.
2835  **/
2836 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2837 {
2838         s32 status;
2839         u32 reg_val;
2840
2841         /* Disable AN and force speed to 10G Serial. */
2842         status = hw->mac.ops.read_iosf_sb_reg(hw,
2843                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2844                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2845         if (status != IXGBE_SUCCESS)
2846                 return status;
2847         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2848         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2849         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2850         status = hw->mac.ops.write_iosf_sb_reg(hw,
2851                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2852                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2853         if (status != IXGBE_SUCCESS)
2854                 return status;
2855
2856         /* Set near-end loopback clocks. */
2857         status = hw->mac.ops.read_iosf_sb_reg(hw,
2858                       IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2859                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2860         if (status != IXGBE_SUCCESS)
2861                 return status;
2862         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2863         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2864         status = hw->mac.ops.write_iosf_sb_reg(hw,
2865                        IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2866                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2867         if (status != IXGBE_SUCCESS)
2868                 return status;
2869
2870         /* Set loopback enable. */
2871         status = hw->mac.ops.read_iosf_sb_reg(hw,
2872                       IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2873                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2874         if (status != IXGBE_SUCCESS)
2875                 return status;
2876         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2877         status = hw->mac.ops.write_iosf_sb_reg(hw,
2878                        IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2879                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2880         if (status != IXGBE_SUCCESS)
2881                 return status;
2882
2883         /* Training bypass. */
2884         status = hw->mac.ops.read_iosf_sb_reg(hw,
2885                       IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2886                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2887         if (status != IXGBE_SUCCESS)
2888                 return status;
2889         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2890         status = hw->mac.ops.write_iosf_sb_reg(hw,
2891                        IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2892                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2893
2894         return status;
2895 }
2896
2897 /**
2898  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2899  *  assuming that the semaphore is already obtained.
2900  *  @hw: pointer to hardware structure
2901  *  @offset: offset of  word in the EEPROM to read
2902  *  @data: word read from the EEPROM
2903  *
2904  *  Reads a 16 bit word from the EEPROM using the hostif.
2905  **/
2906 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2907                                    u16 *data)
2908 {
2909         s32 status;
2910         struct ixgbe_hic_read_shadow_ram buffer;
2911
2912         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2913         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2914         buffer.hdr.req.buf_lenh = 0;
2915         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2916         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2917
2918         /* convert offset from words to bytes */
2919         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2920         /* one word */
2921         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2922
2923         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2924                                               sizeof(buffer),
2925                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2926
2927         if (status)
2928                 return status;
2929
2930         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2931                                           FW_NVM_DATA_OFFSET);
2932
2933         return 0;
2934 }
2935
2936 /**
2937  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2938  *  @hw: pointer to hardware structure
2939  *  @offset: offset of  word in the EEPROM to read
2940  *  @data: word read from the EEPROM
2941  *
2942  *  Reads a 16 bit word from the EEPROM using the hostif.
2943  **/
2944 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2945                               u16 *data)
2946 {
2947         s32 status = IXGBE_SUCCESS;
2948
2949         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2950
2951         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2952             IXGBE_SUCCESS) {
2953                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2954                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2955         } else {
2956                 status = IXGBE_ERR_SWFW_SYNC;
2957         }
2958
2959         return status;
2960 }
2961
2962 /**
2963  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2964  *  @hw: pointer to hardware structure
2965  *  @offset: offset of  word in the EEPROM to read
2966  *  @words: number of words
2967  *  @data: word(s) read from the EEPROM
2968  *
2969  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
2970  **/
2971 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2972                                      u16 offset, u16 words, u16 *data)
2973 {
2974         struct ixgbe_hic_read_shadow_ram buffer;
2975         u32 current_word = 0;
2976         u16 words_to_read;
2977         s32 status;
2978         u32 i;
2979
2980         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2981
2982         /* Take semaphore for the entire operation. */
2983         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2984         if (status) {
2985                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2986                 return status;
2987         }
2988         while (words) {
2989                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2990                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2991                 else
2992                         words_to_read = words;
2993
2994                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2995                 buffer.hdr.req.buf_lenh = 0;
2996                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2997                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2998
2999                 /* convert offset from words to bytes */
3000                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3001                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3002
3003                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3004                                                       sizeof(buffer),
3005                                                       IXGBE_HI_COMMAND_TIMEOUT,
3006                                                       false);
3007
3008                 if (status) {
3009                         DEBUGOUT("Host interface command failed\n");
3010                         goto out;
3011                 }
3012
3013                 for (i = 0; i < words_to_read; i++) {
3014                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3015                                   2 * i;
3016                         u32 value = IXGBE_READ_REG(hw, reg);
3017
3018                         data[current_word] = (u16)(value & 0xffff);
3019                         current_word++;
3020                         i++;
3021                         if (i < words_to_read) {
3022                                 value >>= 16;
3023                                 data[current_word] = (u16)(value & 0xffff);
3024                                 current_word++;
3025                         }
3026                 }
3027                 words -= words_to_read;
3028         }
3029
3030 out:
3031         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3032         return status;
3033 }
3034
3035 /**
3036  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3037  *  @hw: pointer to hardware structure
3038  *  @offset: offset of  word in the EEPROM to write
3039  *  @data: word write to the EEPROM
3040  *
3041  *  Write a 16 bit word to the EEPROM using the hostif.
3042  **/
3043 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3044                                     u16 data)
3045 {
3046         s32 status;
3047         struct ixgbe_hic_write_shadow_ram buffer;
3048
3049         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3050
3051         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3052         buffer.hdr.req.buf_lenh = 0;
3053         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3054         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3055
3056          /* one word */
3057         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3058         buffer.data = data;
3059         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3060
3061         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3062                                               sizeof(buffer),
3063                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3064
3065         return status;
3066 }
3067
3068 /**
3069  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3070  *  @hw: pointer to hardware structure
3071  *  @offset: offset of  word in the EEPROM to write
3072  *  @data: word write to the EEPROM
3073  *
3074  *  Write a 16 bit word to the EEPROM using the hostif.
3075  **/
3076 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3077                                u16 data)
3078 {
3079         s32 status = IXGBE_SUCCESS;
3080
3081         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3082
3083         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3084             IXGBE_SUCCESS) {
3085                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3086                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3087         } else {
3088                 DEBUGOUT("write ee hostif failed to get semaphore");
3089                 status = IXGBE_ERR_SWFW_SYNC;
3090         }
3091
3092         return status;
3093 }
3094
3095 /**
3096  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3097  *  @hw: pointer to hardware structure
3098  *  @offset: offset of  word in the EEPROM to write
3099  *  @words: number of words
3100  *  @data: word(s) write to the EEPROM
3101  *
3102  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3103  **/
3104 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3105                                       u16 offset, u16 words, u16 *data)
3106 {
3107         s32 status = IXGBE_SUCCESS;
3108         u32 i = 0;
3109
3110         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3111
3112         /* Take semaphore for the entire operation. */
3113         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3114         if (status != IXGBE_SUCCESS) {
3115                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3116                 goto out;
3117         }
3118
3119         for (i = 0; i < words; i++) {
3120                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3121                                                          data[i]);
3122
3123                 if (status != IXGBE_SUCCESS) {
3124                         DEBUGOUT("Eeprom buffered write failed\n");
3125                         break;
3126                 }
3127         }
3128
3129         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3130 out:
3131
3132         return status;
3133 }
3134
3135 /**
3136  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3137  * @hw: pointer to hardware structure
3138  * @ptr: pointer offset in eeprom
3139  * @size: size of section pointed by ptr, if 0 first word will be used as size
3140  * @csum: address of checksum to update
3141  *
3142  * Returns error status for any failure
3143  */
3144 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3145                                    u16 size, u16 *csum, u16 *buffer,
3146                                    u32 buffer_size)
3147 {
3148         u16 buf[256];
3149         s32 status;
3150         u16 length, bufsz, i, start;
3151         u16 *local_buffer;
3152
3153         bufsz = sizeof(buf) / sizeof(buf[0]);
3154
3155         /* Read a chunk at the pointer location */
3156         if (!buffer) {
3157                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3158                 if (status) {
3159                         DEBUGOUT("Failed to read EEPROM image\n");
3160                         return status;
3161                 }
3162                 local_buffer = buf;
3163         } else {
3164                 if (buffer_size < ptr)
3165                         return  IXGBE_ERR_PARAM;
3166                 local_buffer = &buffer[ptr];
3167         }
3168
3169         if (size) {
3170                 start = 0;
3171                 length = size;
3172         } else {
3173                 start = 1;
3174                 length = local_buffer[0];
3175
3176                 /* Skip pointer section if length is invalid. */
3177                 if (length == 0xFFFF || length == 0 ||
3178                     (ptr + length) >= hw->eeprom.word_size)
3179                         return IXGBE_SUCCESS;
3180         }
3181
3182         if (buffer && ((u32)start + (u32)length > buffer_size))
3183                 return IXGBE_ERR_PARAM;
3184
3185         for (i = start; length; i++, length--) {
3186                 if (i == bufsz && !buffer) {
3187                         ptr += bufsz;
3188                         i = 0;
3189                         if (length < bufsz)
3190                                 bufsz = length;
3191
3192                         /* Read a chunk at the pointer location */
3193                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3194                                                                   bufsz, buf);
3195                         if (status) {
3196                                 DEBUGOUT("Failed to read EEPROM image\n");
3197                                 return status;
3198                         }
3199                 }
3200                 *csum += local_buffer[i];
3201         }
3202         return IXGBE_SUCCESS;
3203 }
3204
3205 /**
3206  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3207  *  @hw: pointer to hardware structure
3208  *  @buffer: pointer to buffer containing calculated checksum
3209  *  @buffer_size: size of buffer
3210  *
3211  *  Returns a negative error code on error, or the 16-bit checksum
3212  **/
3213 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3214 {
3215         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3216         u16 *local_buffer;
3217         s32 status;
3218         u16 checksum = 0;
3219         u16 pointer, i, size;
3220
3221         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3222
3223         hw->eeprom.ops.init_params(hw);
3224
3225         if (!buffer) {
3226                 /* Read pointer area */
3227                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3228                                                      IXGBE_EEPROM_LAST_WORD + 1,
3229                                                      eeprom_ptrs);
3230                 if (status) {
3231                         DEBUGOUT("Failed to read EEPROM image\n");
3232                         return status;
3233                 }
3234                 local_buffer = eeprom_ptrs;
3235         } else {
3236                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3237                         return IXGBE_ERR_PARAM;
3238                 local_buffer = buffer;
3239         }
3240
3241         /*
3242          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3243          * checksum word itself
3244          */
3245         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3246                 if (i != IXGBE_EEPROM_CHECKSUM)
3247                         checksum += local_buffer[i];
3248
3249         /*
3250          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3251          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3252          */
3253         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3254                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3255                         continue;
3256
3257                 pointer = local_buffer[i];
3258
3259                 /* Skip pointer section if the pointer is invalid. */
3260                 if (pointer == 0xFFFF || pointer == 0 ||
3261                     pointer >= hw->eeprom.word_size)
3262                         continue;
3263
3264                 switch (i) {
3265                 case IXGBE_PCIE_GENERAL_PTR:
3266                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3267                         break;
3268                 case IXGBE_PCIE_CONFIG0_PTR:
3269                 case IXGBE_PCIE_CONFIG1_PTR:
3270                         size = IXGBE_PCIE_CONFIG_SIZE;
3271                         break;
3272                 default:
3273                         size = 0;
3274                         break;
3275                 }
3276
3277                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3278                                                 buffer, buffer_size);
3279                 if (status)
3280                         return status;
3281         }
3282
3283         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3284
3285         return (s32)checksum;
3286 }
3287
3288 /**
3289  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3290  *  @hw: pointer to hardware structure
3291  *
3292  *  Returns a negative error code on error, or the 16-bit checksum
3293  **/
3294 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3295 {
3296         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3297 }
3298
3299 /**
3300  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3301  *  @hw: pointer to hardware structure
3302  *  @checksum_val: calculated checksum
3303  *
3304  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3305  *  caller does not need checksum_val, the value can be NULL.
3306  **/
3307 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3308 {
3309         s32 status;
3310         u16 checksum;
3311         u16 read_checksum = 0;
3312
3313         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3314
3315         /* Read the first word from the EEPROM. If this times out or fails, do
3316          * not continue or we could be in for a very long wait while every
3317          * EEPROM read fails
3318          */
3319         status = hw->eeprom.ops.read(hw, 0, &checksum);
3320         if (status) {
3321                 DEBUGOUT("EEPROM read failed\n");
3322                 return status;
3323         }
3324
3325         status = hw->eeprom.ops.calc_checksum(hw);
3326         if (status < 0)
3327                 return status;
3328
3329         checksum = (u16)(status & 0xffff);
3330
3331         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3332                                            &read_checksum);
3333         if (status)
3334                 return status;
3335
3336         /* Verify read checksum from EEPROM is the same as
3337          * calculated checksum
3338          */
3339         if (read_checksum != checksum) {
3340                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3341                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3342                              "Invalid EEPROM checksum");
3343         }
3344
3345         /* If the user cares, return the calculated checksum */
3346         if (checksum_val)
3347                 *checksum_val = checksum;
3348
3349         return status;
3350 }
3351
3352 /**
3353  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3354  * @hw: pointer to hardware structure
3355  *
3356  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3357  * checksum and updates the EEPROM and instructs the hardware to update
3358  * the flash.
3359  **/
3360 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3361 {
3362         s32 status;
3363         u16 checksum = 0;
3364
3365         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3366
3367         /* Read the first word from the EEPROM. If this times out or fails, do
3368          * not continue or we could be in for a very long wait while every
3369          * EEPROM read fails
3370          */
3371         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3372         if (status) {
3373                 DEBUGOUT("EEPROM read failed\n");
3374                 return status;
3375         }
3376
3377         status = ixgbe_calc_eeprom_checksum_X550(hw);
3378         if (status < 0)
3379                 return status;
3380
3381         checksum = (u16)(status & 0xffff);
3382
3383         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3384                                             checksum);
3385         if (status)
3386                 return status;
3387
3388         status = ixgbe_update_flash_X550(hw);
3389
3390         return status;
3391 }
3392
3393 /**
3394  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3395  *  @hw: pointer to hardware structure
3396  *
3397  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3398  **/
3399 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3400 {
3401         s32 status = IXGBE_SUCCESS;
3402         union ixgbe_hic_hdr2 buffer;
3403
3404         DEBUGFUNC("ixgbe_update_flash_X550");
3405
3406         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3407         buffer.req.buf_lenh = 0;
3408         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3409         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3410
3411         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3412                                               sizeof(buffer),
3413                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3414
3415         return status;
3416 }
3417
3418 /**
3419  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3420  *  @hw: pointer to hardware structure
3421  *
3422  *  Determines physical layer capabilities of the current configuration.
3423  **/
3424 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3425 {
3426         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3427         u16 ext_ability = 0;
3428
3429         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3430
3431         hw->phy.ops.identify(hw);
3432
3433         switch (hw->phy.type) {
3434         case ixgbe_phy_x550em_kr:
3435                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3436                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3437                 break;
3438         case ixgbe_phy_x550em_kx4:
3439                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3440                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3441                 break;
3442         case ixgbe_phy_x550em_ext_t:
3443                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3444                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3445                                      &ext_ability);
3446                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3447                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3448                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3449                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3450                 break;
3451         default:
3452                 break;
3453         }
3454
3455         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3456                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3457
3458         return physical_layer;
3459 }
3460
3461 /**
3462  * ixgbe_get_bus_info_x550em - Set PCI bus info
3463  * @hw: pointer to hardware structure
3464  *
3465  * Sets bus link width and speed to unknown because X550em is
3466  * not a PCI device.
3467  **/
3468 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3469 {
3470
3471         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3472
3473         hw->bus.width = ixgbe_bus_width_unknown;
3474         hw->bus.speed = ixgbe_bus_speed_unknown;
3475
3476         hw->mac.ops.set_lan_id(hw);
3477
3478         return IXGBE_SUCCESS;
3479 }
3480
3481 /**
3482  * ixgbe_disable_rx_x550 - Disable RX unit
3483  *
3484  * Enables the Rx DMA unit for x550
3485  **/
3486 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3487 {
3488         u32 rxctrl, pfdtxgswc;
3489         s32 status;
3490         struct ixgbe_hic_disable_rxen fw_cmd;
3491
3492         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3493
3494         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3495         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3496                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3497                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3498                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3499                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3500                         hw->mac.set_lben = true;
3501                 } else {
3502                         hw->mac.set_lben = false;
3503                 }
3504
3505                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3506                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3507                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3508                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3509
3510                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3511                                         sizeof(struct ixgbe_hic_disable_rxen),
3512                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3513
3514                 /* If we fail - disable RX using register write */
3515                 if (status) {
3516                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3517                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3518                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3519                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3520                         }
3521                 }
3522         }
3523 }
3524
3525 /**
3526  * ixgbe_enter_lplu_x550em - Transition to low power states
3527  *  @hw: pointer to hardware structure
3528  *
3529  * Configures Low Power Link Up on transition to low power states
3530  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3531  * X557 PHY immediately prior to entering LPLU.
3532  **/
3533 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3534 {
3535         u16 an_10g_cntl_reg, autoneg_reg, speed;
3536         s32 status;
3537         ixgbe_link_speed lcd_speed;
3538         u32 save_autoneg;
3539         bool link_up;
3540
3541         /* SW LPLU not required on later HW revisions. */
3542         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3543             (IXGBE_FUSES0_REV_MASK &
3544              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3545                 return IXGBE_SUCCESS;
3546
3547         /* If blocked by MNG FW, then don't restart AN */
3548         if (ixgbe_check_reset_blocked(hw))
3549                 return IXGBE_SUCCESS;
3550
3551         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3552         if (status != IXGBE_SUCCESS)
3553                 return status;
3554
3555         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3556
3557         if (status != IXGBE_SUCCESS)
3558                 return status;
3559
3560         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3561          * disabled, then force link down by entering low power mode.
3562          */
3563         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3564             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3565                 return ixgbe_set_copper_phy_power(hw, FALSE);
3566
3567         /* Determine LCD */
3568         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3569
3570         if (status != IXGBE_SUCCESS)
3571                 return status;
3572
3573         /* If no valid LCD link speed, then force link down and exit. */
3574         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3575                 return ixgbe_set_copper_phy_power(hw, FALSE);
3576
3577         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3578                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3579                                       &speed);
3580
3581         if (status != IXGBE_SUCCESS)
3582                 return status;
3583
3584         /* If no link now, speed is invalid so take link down */
3585         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3586         if (status != IXGBE_SUCCESS)
3587                 return ixgbe_set_copper_phy_power(hw, false);
3588
3589         /* clear everything but the speed bits */
3590         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3591
3592         /* If current speed is already LCD, then exit. */
3593         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3594              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3595             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3596              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3597                 return status;
3598
3599         /* Clear AN completed indication */
3600         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3601                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3602                                       &autoneg_reg);
3603
3604         if (status != IXGBE_SUCCESS)
3605                 return status;
3606
3607         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3608                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3609                              &an_10g_cntl_reg);
3610
3611         if (status != IXGBE_SUCCESS)
3612                 return status;
3613
3614         status = hw->phy.ops.read_reg(hw,
3615                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3616                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3617                              &autoneg_reg);
3618
3619         if (status != IXGBE_SUCCESS)
3620                 return status;
3621
3622         save_autoneg = hw->phy.autoneg_advertised;
3623
3624         /* Setup link at least common link speed */
3625         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3626
3627         /* restore autoneg from before setting lplu speed */
3628         hw->phy.autoneg_advertised = save_autoneg;
3629
3630         return status;
3631 }
3632
3633 /**
3634  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3635  *  @hw: pointer to hardware structure
3636  *  @lcd_speed: pointer to lowest common link speed
3637  *
3638  * Determine lowest common link speed with link partner.
3639  **/
3640 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3641 {
3642         u16 an_lp_status;
3643         s32 status;
3644         u16 word = hw->eeprom.ctrl_word_3;
3645
3646         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3647
3648         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3649                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3650                                       &an_lp_status);
3651
3652         if (status != IXGBE_SUCCESS)
3653                 return status;
3654
3655         /* If link partner advertised 1G, return 1G */
3656         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3657                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3658                 return status;
3659         }
3660
3661         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3662         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3663             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3664                 return status;
3665
3666         /* Link partner not capable of lower speeds, return 10G */
3667         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3668         return status;
3669 }
3670
3671 /**
3672  *  ixgbe_setup_fc_X550em - Set up flow control
3673  *  @hw: pointer to hardware structure
3674  *
3675  *  Called at init time to set up flow control.
3676  **/
3677 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3678 {
3679         s32 ret_val = IXGBE_SUCCESS;
3680         u32 pause, asm_dir, reg_val;
3681
3682         DEBUGFUNC("ixgbe_setup_fc_X550em");
3683
3684         /* Validate the requested mode */
3685         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3686                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3687                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3688                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3689                 goto out;
3690         }
3691
3692         /* 10gig parts do not have a word in the EEPROM to determine the
3693          * default flow control setting, so we explicitly set it to full.
3694          */
3695         if (hw->fc.requested_mode == ixgbe_fc_default)
3696                 hw->fc.requested_mode = ixgbe_fc_full;
3697
3698         /* Determine PAUSE and ASM_DIR bits. */
3699         switch (hw->fc.requested_mode) {
3700         case ixgbe_fc_none:
3701                 pause = 0;
3702                 asm_dir = 0;
3703                 break;
3704         case ixgbe_fc_tx_pause:
3705                 pause = 0;
3706                 asm_dir = 1;
3707                 break;
3708         case ixgbe_fc_rx_pause:
3709                 /* Rx Flow control is enabled and Tx Flow control is
3710                  * disabled by software override. Since there really
3711                  * isn't a way to advertise that we are capable of RX
3712                  * Pause ONLY, we will advertise that we support both
3713                  * symmetric and asymmetric Rx PAUSE, as such we fall
3714                  * through to the fc_full statement.  Later, we will
3715                  * disable the adapter's ability to send PAUSE frames.
3716                  */
3717         case ixgbe_fc_full:
3718                 pause = 1;
3719                 asm_dir = 1;
3720                 break;
3721         default:
3722                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3723                         "Flow control param set incorrectly\n");
3724                 ret_val = IXGBE_ERR_CONFIG;
3725                 goto out;
3726         }
3727
3728         switch (hw->device_id) {
3729         case IXGBE_DEV_ID_X550EM_X_KR:
3730         case IXGBE_DEV_ID_X550EM_A_KR:
3731         case IXGBE_DEV_ID_X550EM_A_KR_L:
3732                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3733                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3734                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3735                 if (ret_val != IXGBE_SUCCESS)
3736                         goto out;
3737                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3738                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3739                 if (pause)
3740                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3741                 if (asm_dir)
3742                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3743                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3744                                        IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3745                                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3746
3747                 /* This device does not fully support AN. */
3748                 hw->fc.disable_fc_autoneg = true;
3749                 break;
3750         default:
3751                 break;
3752         }
3753
3754 out:
3755         return ret_val;
3756 }
3757
3758 /**
3759  * ixgbe_set_mux - Set mux for port 1 access with CS4227
3760  * @hw: pointer to hardware structure
3761  * @state: set mux if 1, clear if 0
3762  */
3763 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3764 {
3765         u32 esdp;
3766
3767         if (!hw->bus.lan_id)
3768                 return;
3769         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3770         if (state)
3771                 esdp |= IXGBE_ESDP_SDP1;
3772         else
3773                 esdp &= ~IXGBE_ESDP_SDP1;
3774         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3775         IXGBE_WRITE_FLUSH(hw);
3776 }
3777
3778 /**
3779  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3780  *  @hw: pointer to hardware structure
3781  *  @mask: Mask to specify which semaphore to acquire
3782  *
3783  *  Acquires the SWFW semaphore and sets the I2C MUX
3784  **/
3785 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3786 {
3787         s32 status;
3788
3789         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
3790
3791         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3792         if (status)
3793                 return status;
3794
3795         if (mask & IXGBE_GSSR_I2C_MASK)
3796                 ixgbe_set_mux(hw, 1);
3797
3798         return IXGBE_SUCCESS;
3799 }
3800
3801 /**
3802  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3803  *  @hw: pointer to hardware structure
3804  *  @mask: Mask to specify which semaphore to release
3805  *
3806  *  Releases the SWFW semaphore and sets the I2C MUX
3807  **/
3808 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3809 {
3810         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3811
3812         if (mask & IXGBE_GSSR_I2C_MASK)
3813                 ixgbe_set_mux(hw, 0);
3814
3815         ixgbe_release_swfw_sync_X540(hw, mask);
3816 }
3817
3818 /**
3819  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
3820  *  @hw: pointer to hardware structure
3821  *  @mask: Mask to specify which semaphore to acquire
3822  *
3823  *  Acquires the SWFW semaphore and get the shared phy token as needed
3824  */
3825 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3826 {
3827         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3828         int retries = FW_PHY_TOKEN_RETRIES;
3829         s32 status = IXGBE_SUCCESS;
3830
3831         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
3832
3833         while (--retries) {
3834                 status = IXGBE_SUCCESS;
3835                 if (hmask)
3836                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3837                 if (status)
3838                         return status;
3839                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3840                         return IXGBE_SUCCESS;
3841
3842                 status = ixgbe_get_phy_token(hw);
3843                 if (status == IXGBE_SUCCESS)
3844                         return IXGBE_SUCCESS;
3845
3846                 if (hmask)
3847                         ixgbe_release_swfw_sync_X540(hw, hmask);
3848                 if (status != IXGBE_ERR_TOKEN_RETRY)
3849                         return status;
3850                 msec_delay(FW_PHY_TOKEN_DELAY);
3851         }
3852
3853         return status;
3854 }
3855
3856 /**
3857  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
3858  *  @hw: pointer to hardware structure
3859  *  @mask: Mask to specify which semaphore to release
3860  *
3861  *  Releases the SWFW semaphore and puts the shared phy token as needed
3862  */
3863 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3864 {
3865         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3866
3867         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
3868
3869         if (mask & IXGBE_GSSR_TOKEN_SM)
3870                 ixgbe_put_phy_token(hw);
3871
3872         if (hmask)
3873                 ixgbe_release_swfw_sync_X540(hw, hmask);
3874 }
3875
3876 /**
3877  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
3878  *  @hw: pointer to hardware structure
3879  *  @reg_addr: 32 bit address of PHY register to read
3880  *  @phy_data: Pointer to read data from PHY register
3881  *
3882  *  Reads a value from a specified PHY register using the SWFW lock and PHY
3883  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
3884  *  instances.
3885  **/
3886 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3887                              u32 device_type, u16 *phy_data)
3888 {
3889         s32 status;
3890         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3891
3892         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
3893
3894         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3895                 return IXGBE_ERR_SWFW_SYNC;
3896
3897         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
3898
3899         hw->mac.ops.release_swfw_sync(hw, mask);
3900
3901         return status;
3902 }
3903
3904 /**
3905  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
3906  *  @hw: pointer to hardware structure
3907  *  @reg_addr: 32 bit PHY register to write
3908  *  @device_type: 5 bit device type
3909  *  @phy_data: Data to write to the PHY register
3910  *
3911  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
3912  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
3913  **/
3914 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3915                               u32 device_type, u16 phy_data)
3916 {
3917         s32 status;
3918         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3919
3920         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
3921
3922         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
3923                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
3924                                                  phy_data);
3925                 hw->mac.ops.release_swfw_sync(hw, mask);
3926         } else {
3927                 status = IXGBE_ERR_SWFW_SYNC;
3928         }
3929
3930         return status;
3931 }
3932
3933 /**
3934  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
3935  * @hw: pointer to hardware structure
3936  *
3937  * Handle external Base T PHY interrupt. If high temperature
3938  * failure alarm then return error, else if link status change
3939  * then setup internal/external PHY link
3940  *
3941  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
3942  * failure alarm, else return PHY access status.
3943  */
3944 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
3945 {
3946         bool lsc;
3947         u32 status;
3948
3949         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
3950
3951         if (status != IXGBE_SUCCESS)
3952                 return status;
3953
3954         if (lsc)
3955                 return ixgbe_setup_internal_phy(hw);
3956
3957         return IXGBE_SUCCESS;
3958 }
3959
3960 /**
3961  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
3962  * @hw: pointer to hardware structure
3963  * @speed: new link speed
3964  * @autoneg_wait_to_complete: true when waiting for completion is needed
3965  *
3966  * Setup internal/external PHY link speed based on link speed, then set
3967  * external PHY auto advertised link speed.
3968  *
3969  * Returns error status for any failure
3970  **/
3971 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3972                                   ixgbe_link_speed speed,
3973                                   bool autoneg_wait_to_complete)
3974 {
3975         s32 status;
3976         ixgbe_link_speed force_speed;
3977
3978         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3979
3980         /* Setup internal/external PHY link speed to iXFI (10G), unless
3981          * only 1G is auto advertised then setup KX link.
3982          */
3983         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3984                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3985         else
3986                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3987
3988         /* If internal link mode is XFI, then setup XFI internal link. */
3989         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3990                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3991
3992                 if (status != IXGBE_SUCCESS)
3993                         return status;
3994         }
3995
3996         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3997 }
3998
3999 /**
4000  * ixgbe_check_link_t_X550em - Determine link and speed status
4001  * @hw: pointer to hardware structure
4002  * @speed: pointer to link speed
4003  * @link_up: true when link is up
4004  * @link_up_wait_to_complete: bool used to wait for link up or not
4005  *
4006  * Check that both the MAC and X557 external PHY have link.
4007  **/
4008 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4009                               bool *link_up, bool link_up_wait_to_complete)
4010 {
4011         u32 status;
4012         u16 autoneg_status;
4013
4014         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4015                 return IXGBE_ERR_CONFIG;
4016
4017         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4018                                               link_up_wait_to_complete);
4019
4020         /* If check link fails or MAC link is not up, then return */
4021         if (status != IXGBE_SUCCESS || !(*link_up))
4022                 return status;
4023
4024         /* MAC link is up, so check external PHY link.
4025          * Read this twice back to back to indicate current status.
4026          */
4027         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4028                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4029                                       &autoneg_status);
4030
4031         if (status != IXGBE_SUCCESS)
4032                 return status;
4033
4034         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4035                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4036                                       &autoneg_status);
4037
4038         if (status != IXGBE_SUCCESS)
4039                 return status;
4040
4041         /* If external PHY link is not up, then indicate link not up */
4042         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4043                 *link_up = false;
4044
4045         return IXGBE_SUCCESS;
4046 }
4047
4048 /**
4049  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4050  *  @hw: pointer to hardware structure
4051  **/
4052 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4053 {
4054         s32 status;
4055
4056         status = ixgbe_reset_phy_generic(hw);
4057
4058         if (status != IXGBE_SUCCESS)
4059                 return status;
4060
4061         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4062         return ixgbe_enable_lasi_ext_t_x550em(hw);
4063 }
4064
4065 /**
4066  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4067  *  @hw: pointer to hardware structure
4068  *  @led_idx: led number to turn on
4069  **/
4070 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4071 {
4072         u16 phy_data;
4073
4074         DEBUGFUNC("ixgbe_led_on_t_X550em");
4075
4076         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4077                 return IXGBE_ERR_PARAM;
4078
4079         /* To turn on the LED, set mode to ON. */
4080         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4081                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4082         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4083         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4084                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4085
4086         return IXGBE_SUCCESS;
4087 }
4088
4089 /**
4090  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4091  *  @hw: pointer to hardware structure
4092  *  @led_idx: led number to turn off
4093  **/
4094 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4095 {
4096         u16 phy_data;
4097
4098         DEBUGFUNC("ixgbe_led_off_t_X550em");
4099
4100         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4101                 return IXGBE_ERR_PARAM;
4102
4103         /* To turn on the LED, set mode to ON. */
4104         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4105                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4106         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4107         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4108                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4109
4110         return IXGBE_SUCCESS;
4111 }
4112