1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
47 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
48 * @hw: pointer to hardware structure
50 * Initialize the function pointers and assign the MAC type for X550.
51 * Does not touch the hardware.
53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
55 struct ixgbe_mac_info *mac = &hw->mac;
56 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
59 DEBUGFUNC("ixgbe_init_ops_X550");
61 ret_val = ixgbe_init_ops_X540(hw);
62 mac->ops.dmac_config = ixgbe_dmac_config_X550;
63 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
64 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
65 mac->ops.setup_eee = ixgbe_setup_eee_X550;
66 mac->ops.set_source_address_pruning =
67 ixgbe_set_source_address_pruning_X550;
68 mac->ops.set_ethertype_anti_spoofing =
69 ixgbe_set_ethertype_anti_spoofing_X550;
71 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
72 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
73 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
74 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
75 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
76 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
77 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
78 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
79 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
81 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
82 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
83 mac->ops.mdd_event = ixgbe_mdd_event_X550;
84 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
85 mac->ops.disable_rx = ixgbe_disable_rx_x550;
86 switch (hw->device_id) {
87 case IXGBE_DEV_ID_X550EM_X_10G_T:
88 case IXGBE_DEV_ID_X550EM_A_10G_T:
89 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
90 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
99 * ixgbe_read_cs4227 - Read CS4227 register
100 * @hw: pointer to hardware structure
101 * @reg: register number to write
102 * @value: pointer to receive value read
104 * Returns status code
106 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
108 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
112 * ixgbe_write_cs4227 - Write CS4227 register
113 * @hw: pointer to hardware structure
114 * @reg: register number to write
115 * @value: value to write to register
117 * Returns status code
119 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
121 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
125 * ixgbe_read_pe - Read register from port expander
126 * @hw: pointer to hardware structure
127 * @reg: register number to read
128 * @value: pointer to receive read value
130 * Returns status code
132 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
136 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
137 if (status != IXGBE_SUCCESS)
138 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
139 "port expander access failed with %d\n", status);
144 * ixgbe_write_pe - Write register to port expander
145 * @hw: pointer to hardware structure
146 * @reg: register number to write
147 * @value: value to write
149 * Returns status code
151 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
155 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
156 if (status != IXGBE_SUCCESS)
157 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
158 "port expander access failed with %d\n", status);
163 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
164 * @hw: pointer to hardware structure
166 * This function assumes that the caller has acquired the proper semaphore.
169 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
176 /* Trigger hard reset. */
177 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
178 if (status != IXGBE_SUCCESS)
180 reg |= IXGBE_PE_BIT1;
181 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
182 if (status != IXGBE_SUCCESS)
185 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
186 if (status != IXGBE_SUCCESS)
188 reg &= ~IXGBE_PE_BIT1;
189 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
190 if (status != IXGBE_SUCCESS)
193 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
194 if (status != IXGBE_SUCCESS)
196 reg &= ~IXGBE_PE_BIT1;
197 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
198 if (status != IXGBE_SUCCESS)
201 usec_delay(IXGBE_CS4227_RESET_HOLD);
203 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
204 if (status != IXGBE_SUCCESS)
206 reg |= IXGBE_PE_BIT1;
207 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
208 if (status != IXGBE_SUCCESS)
211 /* Wait for the reset to complete. */
212 msec_delay(IXGBE_CS4227_RESET_DELAY);
213 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
214 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
216 if (status == IXGBE_SUCCESS &&
217 value == IXGBE_CS4227_EEPROM_LOAD_OK)
219 msec_delay(IXGBE_CS4227_CHECK_DELAY);
221 if (retry == IXGBE_CS4227_RETRIES) {
222 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
223 "CS4227 reset did not complete.");
224 return IXGBE_ERR_PHY;
227 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
228 if (status != IXGBE_SUCCESS ||
229 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
230 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
231 "CS4227 EEPROM did not load successfully.");
232 return IXGBE_ERR_PHY;
235 return IXGBE_SUCCESS;
239 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
240 * @hw: pointer to hardware structure
242 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
244 s32 status = IXGBE_SUCCESS;
245 u32 swfw_mask = hw->phy.phy_semaphore_mask;
249 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
250 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
251 if (status != IXGBE_SUCCESS) {
252 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
253 "semaphore failed with %d", status);
254 msec_delay(IXGBE_CS4227_CHECK_DELAY);
258 /* Get status of reset flow. */
259 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
261 if (status == IXGBE_SUCCESS &&
262 value == IXGBE_CS4227_RESET_COMPLETE)
265 if (status != IXGBE_SUCCESS ||
266 value != IXGBE_CS4227_RESET_PENDING)
269 /* Reset is pending. Wait and check again. */
270 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
271 msec_delay(IXGBE_CS4227_CHECK_DELAY);
274 /* If still pending, assume other instance failed. */
275 if (retry == IXGBE_CS4227_RETRIES) {
276 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
277 if (status != IXGBE_SUCCESS) {
278 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
279 "semaphore failed with %d", status);
284 /* Reset the CS4227. */
285 status = ixgbe_reset_cs4227(hw);
286 if (status != IXGBE_SUCCESS) {
287 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
288 "CS4227 reset failed: %d", status);
292 /* Reset takes so long, temporarily release semaphore in case the
293 * other driver instance is waiting for the reset indication.
295 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
296 IXGBE_CS4227_RESET_PENDING);
297 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
299 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
300 if (status != IXGBE_SUCCESS) {
301 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
302 "semaphore failed with %d", status);
306 /* Record completion for next time. */
307 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
308 IXGBE_CS4227_RESET_COMPLETE);
311 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
312 msec_delay(hw->eeprom.semaphore_delay);
316 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
317 * @hw: pointer to hardware structure
319 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
321 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
323 if (hw->bus.lan_id) {
324 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
325 esdp |= IXGBE_ESDP_SDP1_DIR;
327 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
328 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
329 IXGBE_WRITE_FLUSH(hw);
333 * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
334 * @hw: pointer to hardware structure
335 * @reg_addr: 32 bit address of PHY register to read
336 * @dev_type: always unused
337 * @phy_data: Pointer to read data from PHY register
339 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
340 u32 dev_type, u16 *phy_data)
342 u32 i, data, command;
343 UNREFERENCED_1PARAMETER(dev_type);
345 /* Setup and write the read command */
346 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
347 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
348 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
349 IXGBE_MSCA_MDI_COMMAND;
351 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
353 /* Check every 10 usec to see if the access completed.
354 * The MDI Command bit will clear when the operation is
357 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
360 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
361 if (!(command & IXGBE_MSCA_MDI_COMMAND))
365 if (command & IXGBE_MSCA_MDI_COMMAND) {
366 ERROR_REPORT1(IXGBE_ERROR_POLLING,
367 "PHY read command did not complete.\n");
368 return IXGBE_ERR_PHY;
371 /* Read operation is complete. Get the data from MSRWD */
372 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
373 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
374 *phy_data = (u16)data;
376 return IXGBE_SUCCESS;
380 * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
381 * @hw: pointer to hardware structure
382 * @reg_addr: 32 bit PHY register to write
383 * @dev_type: always unused
384 * @phy_data: Data to write to the PHY register
386 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
387 u32 dev_type, u16 phy_data)
390 UNREFERENCED_1PARAMETER(dev_type);
392 /* Put the data in the MDI single read and write data register*/
393 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
395 /* Setup and write the write command */
396 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
397 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
398 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
399 IXGBE_MSCA_MDI_COMMAND;
401 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
403 /* Check every 10 usec to see if the access completed.
404 * The MDI Command bit will clear when the operation is
407 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
410 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
411 if (!(command & IXGBE_MSCA_MDI_COMMAND))
415 if (command & IXGBE_MSCA_MDI_COMMAND) {
416 ERROR_REPORT1(IXGBE_ERROR_POLLING,
417 "PHY write cmd didn't complete\n");
418 return IXGBE_ERR_PHY;
421 return IXGBE_SUCCESS;
425 * ixgbe_identify_phy_x550em - Get PHY type based on device id
426 * @hw: pointer to hardware structure
430 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
432 hw->mac.ops.set_lan_id(hw);
434 ixgbe_read_mng_if_sel_x550em(hw);
436 switch (hw->device_id) {
437 case IXGBE_DEV_ID_X550EM_A_SFP:
438 return ixgbe_identify_module_generic(hw);
439 case IXGBE_DEV_ID_X550EM_X_SFP:
440 /* set up for CS4227 usage */
441 ixgbe_setup_mux_ctl(hw);
442 ixgbe_check_cs4227(hw);
445 case IXGBE_DEV_ID_X550EM_A_SFP_N:
446 return ixgbe_identify_module_generic(hw);
448 case IXGBE_DEV_ID_X550EM_X_KX4:
449 hw->phy.type = ixgbe_phy_x550em_kx4;
451 case IXGBE_DEV_ID_X550EM_X_KR:
452 case IXGBE_DEV_ID_X550EM_A_KR:
453 case IXGBE_DEV_ID_X550EM_A_KR_L:
454 hw->phy.type = ixgbe_phy_x550em_kr;
456 case IXGBE_DEV_ID_X550EM_A_10G_T:
457 case IXGBE_DEV_ID_X550EM_A_1G_T:
458 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
459 case IXGBE_DEV_ID_X550EM_X_1G_T:
460 case IXGBE_DEV_ID_X550EM_X_10G_T:
461 return ixgbe_identify_phy_generic(hw);
465 return IXGBE_SUCCESS;
468 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
469 u32 device_type, u16 *phy_data)
471 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
472 return IXGBE_NOT_IMPLEMENTED;
475 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
476 u32 device_type, u16 phy_data)
478 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
479 return IXGBE_NOT_IMPLEMENTED;
483 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
484 * @hw: pointer to the hardware structure
485 * @addr: I2C bus address to read from
486 * @reg: I2C device register to read from
487 * @val: pointer to location to receive read value
489 * Returns an error code on error.
491 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
494 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
498 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
499 * @hw: pointer to the hardware structure
500 * @addr: I2C bus address to read from
501 * @reg: I2C device register to read from
502 * @val: pointer to location to receive read value
504 * Returns an error code on error.
507 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
510 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
514 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
515 * @hw: pointer to the hardware structure
516 * @addr: I2C bus address to write to
517 * @reg: I2C device register to write to
518 * @val: value to write
520 * Returns an error code on error.
522 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
523 u8 addr, u16 reg, u16 val)
525 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
529 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
530 * @hw: pointer to the hardware structure
531 * @addr: I2C bus address to write to
532 * @reg: I2C device register to write to
533 * @val: value to write
535 * Returns an error code on error.
538 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
539 u8 addr, u16 reg, u16 val)
541 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
545 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
546 * @hw: pointer to hardware structure
548 * Initialize the function pointers and for MAC type X550EM.
549 * Does not touch the hardware.
551 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
553 struct ixgbe_mac_info *mac = &hw->mac;
554 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
555 struct ixgbe_phy_info *phy = &hw->phy;
558 DEBUGFUNC("ixgbe_init_ops_X550EM");
560 /* Similar to X550 so start there. */
561 ret_val = ixgbe_init_ops_X550(hw);
563 /* Since this function eventually calls
564 * ixgbe_init_ops_540 by design, we are setting
565 * the pointers to NULL explicitly here to overwrite
566 * the values being set in the x540 function.
568 /* Thermal sensor not supported in x550EM */
569 mac->ops.get_thermal_sensor_data = NULL;
570 mac->ops.init_thermal_sensor_thresh = NULL;
571 mac->thermal_sensor_enabled = false;
573 /* FCOE not supported in x550EM */
574 mac->ops.get_san_mac_addr = NULL;
575 mac->ops.set_san_mac_addr = NULL;
576 mac->ops.get_wwn_prefix = NULL;
577 mac->ops.get_fcoe_boot_status = NULL;
579 /* IPsec not supported in x550EM */
580 mac->ops.disable_sec_rx_path = NULL;
581 mac->ops.enable_sec_rx_path = NULL;
583 /* AUTOC register is not present in x550EM. */
584 mac->ops.prot_autoc_read = NULL;
585 mac->ops.prot_autoc_write = NULL;
587 /* X550EM bus type is internal*/
588 hw->bus.type = ixgbe_bus_type_internal;
589 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
592 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
593 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
594 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
595 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
596 mac->ops.get_supported_physical_layer =
597 ixgbe_get_supported_physical_layer_X550em;
599 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
600 mac->ops.setup_fc = ixgbe_setup_fc_generic;
602 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
604 switch (hw->device_id) {
605 case IXGBE_DEV_ID_X550EM_X_KR:
606 case IXGBE_DEV_ID_X550EM_A_KR:
607 case IXGBE_DEV_ID_X550EM_A_KR_L:
610 mac->ops.setup_eee = NULL;
614 phy->ops.init = ixgbe_init_phy_ops_X550em;
615 phy->ops.identify = ixgbe_identify_phy_x550em;
616 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
617 phy->ops.set_phy_power = NULL;
621 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
622 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
623 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
624 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
625 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
626 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
627 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
628 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
634 * ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
635 * @hw: pointer to hardware structure
637 * Initialize the function pointers and for MAC type X550EM_a.
638 * Does not touch the hardware.
640 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
642 struct ixgbe_mac_info *mac = &hw->mac;
645 DEBUGFUNC("ixgbe_init_ops_X550EM_a");
647 /* Start with generic X550EM init */
648 ret_val = ixgbe_init_ops_X550EM(hw);
650 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
651 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
652 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
653 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
655 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
656 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
658 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
659 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
661 switch (mac->ops.get_media_type(hw)) {
662 case ixgbe_media_type_fiber:
663 mac->ops.setup_fc = NULL;
664 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
666 case ixgbe_media_type_backplane:
667 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
668 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
674 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T) ||
675 (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)) {
676 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
677 mac->ops.setup_fc = ixgbe_setup_fc_sgmii_x550em_a;
684 * ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
685 * @hw: pointer to hardware structure
687 * Initialize the function pointers and for MAC type X550EM_x.
688 * Does not touch the hardware.
690 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
692 struct ixgbe_mac_info *mac = &hw->mac;
693 struct ixgbe_link_info *link = &hw->link;
696 DEBUGFUNC("ixgbe_init_ops_X550EM_x");
698 /* Start with generic X550EM init */
699 ret_val = ixgbe_init_ops_X550EM(hw);
701 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
702 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
703 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
704 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
705 link->ops.read_link = ixgbe_read_i2c_combined_generic;
706 link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
707 link->ops.write_link = ixgbe_write_i2c_combined_generic;
708 link->ops.write_link_unlocked =
709 ixgbe_write_i2c_combined_generic_unlocked;
710 link->addr = IXGBE_CS4227;
716 * ixgbe_dmac_config_X550
717 * @hw: pointer to hardware structure
719 * Configure DMA coalescing. If enabling dmac, dmac is activated.
720 * When disabling dmac, dmac enable dmac bit is cleared.
722 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
724 u32 reg, high_pri_tc;
726 DEBUGFUNC("ixgbe_dmac_config_X550");
728 /* Disable DMA coalescing before configuring */
729 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
730 reg &= ~IXGBE_DMACR_DMAC_EN;
731 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
733 /* Disable DMA Coalescing if the watchdog timer is 0 */
734 if (!hw->mac.dmac_config.watchdog_timer)
737 ixgbe_dmac_config_tcs_X550(hw);
739 /* Configure DMA Coalescing Control Register */
740 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
742 /* Set the watchdog timer in units of 40.96 usec */
743 reg &= ~IXGBE_DMACR_DMACWT_MASK;
744 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
746 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
747 /* If fcoe is enabled, set high priority traffic class */
748 if (hw->mac.dmac_config.fcoe_en) {
749 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
750 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
751 IXGBE_DMACR_HIGH_PRI_TC_MASK);
753 reg |= IXGBE_DMACR_EN_MNG_IND;
755 /* Enable DMA coalescing after configuration */
756 reg |= IXGBE_DMACR_DMAC_EN;
757 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
760 return IXGBE_SUCCESS;
764 * ixgbe_dmac_config_tcs_X550
765 * @hw: pointer to hardware structure
767 * Configure DMA coalescing threshold per TC. The dmac enable bit must
768 * be cleared before configuring.
770 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
772 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
774 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
776 /* Configure DMA coalescing enabled */
777 switch (hw->mac.dmac_config.link_speed) {
778 case IXGBE_LINK_SPEED_10_FULL:
779 case IXGBE_LINK_SPEED_100_FULL:
780 pb_headroom = IXGBE_DMACRXT_100M;
782 case IXGBE_LINK_SPEED_1GB_FULL:
783 pb_headroom = IXGBE_DMACRXT_1G;
786 pb_headroom = IXGBE_DMACRXT_10G;
790 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
791 IXGBE_MHADD_MFS_SHIFT) / 1024);
793 /* Set the per Rx packet buffer receive threshold */
794 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
795 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
796 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
798 if (tc < hw->mac.dmac_config.num_tcs) {
800 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
801 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
802 IXGBE_RXPBSIZE_SHIFT;
804 /* Calculate receive buffer threshold in kilobytes */
805 if (rx_pb_size > pb_headroom)
806 rx_pb_size = rx_pb_size - pb_headroom;
810 /* Minimum of MFS shall be set for DMCTH */
811 reg |= (rx_pb_size > maxframe_size_kb) ?
812 rx_pb_size : maxframe_size_kb;
814 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
816 return IXGBE_SUCCESS;
820 * ixgbe_dmac_update_tcs_X550
821 * @hw: pointer to hardware structure
823 * Disables dmac, updates per TC settings, and then enables dmac.
825 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
829 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
831 /* Disable DMA coalescing before configuring */
832 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
833 reg &= ~IXGBE_DMACR_DMAC_EN;
834 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
836 ixgbe_dmac_config_tcs_X550(hw);
838 /* Enable DMA coalescing after configuration */
839 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
840 reg |= IXGBE_DMACR_DMAC_EN;
841 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
843 return IXGBE_SUCCESS;
847 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
848 * @hw: pointer to hardware structure
850 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
851 * ixgbe_hw struct in order to set up EEPROM access.
853 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
855 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
859 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
861 if (eeprom->type == ixgbe_eeprom_uninitialized) {
862 eeprom->semaphore_delay = 10;
863 eeprom->type = ixgbe_flash;
865 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
866 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
867 IXGBE_EEC_SIZE_SHIFT);
868 eeprom->word_size = 1 << (eeprom_size +
869 IXGBE_EEPROM_WORD_SIZE_SHIFT);
871 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
872 eeprom->type, eeprom->word_size);
875 return IXGBE_SUCCESS;
879 * ixgbe_enable_eee_x550 - Enable EEE support
880 * @hw: pointer to hardware structure
882 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
888 if (hw->mac.type == ixgbe_mac_X550) {
889 /* Advertise EEE capability */
890 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
891 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
894 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
895 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
896 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
898 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
899 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
901 return IXGBE_SUCCESS;
904 switch (hw->device_id) {
905 case IXGBE_DEV_ID_X550EM_X_KR:
906 case IXGBE_DEV_ID_X550EM_A_KR:
907 case IXGBE_DEV_ID_X550EM_A_KR_L:
908 status = hw->mac.ops.read_iosf_sb_reg(hw,
909 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
910 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
911 if (status != IXGBE_SUCCESS)
914 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
915 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
917 /* Don't advertise FEC capability when EEE enabled. */
918 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
920 status = hw->mac.ops.write_iosf_sb_reg(hw,
921 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
922 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
923 if (status != IXGBE_SUCCESS)
930 return IXGBE_SUCCESS;
934 * ixgbe_disable_eee_x550 - Disable EEE support
935 * @hw: pointer to hardware structure
937 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
943 if (hw->mac.type == ixgbe_mac_X550) {
944 /* Disable advertised EEE capability */
945 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
946 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
949 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
950 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
951 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
953 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
954 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
956 return IXGBE_SUCCESS;
959 switch (hw->device_id) {
960 case IXGBE_DEV_ID_X550EM_X_KR:
961 case IXGBE_DEV_ID_X550EM_A_KR:
962 case IXGBE_DEV_ID_X550EM_A_KR_L:
963 status = hw->mac.ops.read_iosf_sb_reg(hw,
964 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
965 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
966 if (status != IXGBE_SUCCESS)
969 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
970 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
972 /* Advertise FEC capability when EEE is disabled. */
973 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
975 status = hw->mac.ops.write_iosf_sb_reg(hw,
976 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
977 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
978 if (status != IXGBE_SUCCESS)
985 return IXGBE_SUCCESS;
989 * ixgbe_setup_eee_X550 - Enable/disable EEE support
990 * @hw: pointer to the HW structure
991 * @enable_eee: boolean flag to enable EEE
993 * Enable/disable EEE based on enable_eee flag.
994 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
998 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
1003 DEBUGFUNC("ixgbe_setup_eee_X550");
1005 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
1006 /* Enable or disable EEE per flag */
1008 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1010 /* Not supported on first revision of X550EM_x. */
1011 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1012 !(IXGBE_FUSES0_REV_MASK &
1013 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1014 return IXGBE_SUCCESS;
1016 status = ixgbe_enable_eee_x550(hw);
1020 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1022 status = ixgbe_disable_eee_x550(hw);
1026 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1028 return IXGBE_SUCCESS;
1032 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1033 * @hw: pointer to hardware structure
1034 * @enable: enable or disable source address pruning
1035 * @pool: Rx pool to set source address pruning for
1037 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1042 /* max rx pool is 63 */
1046 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1047 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1050 pfflp |= (1ULL << pool);
1052 pfflp &= ~(1ULL << pool);
1054 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1055 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1059 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1060 * @hw: pointer to hardware structure
1061 * @enable: enable or disable switch for Ethertype anti-spoofing
1062 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1065 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1066 bool enable, int vf)
1068 int vf_target_reg = vf >> 3;
1069 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1072 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1074 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1076 pfvfspoof |= (1 << vf_target_shift);
1078 pfvfspoof &= ~(1 << vf_target_shift);
1080 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1084 * ixgbe_iosf_wait - Wait for IOSF command completion
1085 * @hw: pointer to hardware structure
1086 * @ctrl: pointer to location to receive final IOSF control value
1088 * Returns failing status on timeout
1090 * Note: ctrl can be NULL if the IOSF control register value is not needed
1092 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1096 /* Check every 10 usec to see if the address cycle completed.
1097 * The SB IOSF BUSY bit will clear when the operation is
1100 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1101 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1102 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1108 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1109 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1110 return IXGBE_ERR_PHY;
1113 return IXGBE_SUCCESS;
1117 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1118 * of the IOSF device
1119 * @hw: pointer to hardware structure
1120 * @reg_addr: 32 bit PHY register to write
1121 * @device_type: 3 bit device type
1122 * @data: Data to write to the register
1124 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1125 u32 device_type, u32 data)
1127 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1131 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1132 if (ret != IXGBE_SUCCESS)
1135 ret = ixgbe_iosf_wait(hw, NULL);
1136 if (ret != IXGBE_SUCCESS)
1139 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1140 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1142 /* Write IOSF control register */
1143 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1145 /* Write IOSF data register */
1146 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1148 ret = ixgbe_iosf_wait(hw, &command);
1150 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1151 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1152 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1153 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1154 "Failed to write, error %x\n", error);
1155 ret = IXGBE_ERR_PHY;
1159 ixgbe_release_swfw_semaphore(hw, gssr);
1164 * ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1165 * @hw: pointer to hardware structure
1166 * @reg_addr: 32 bit PHY register to write
1167 * @device_type: 3 bit device type
1168 * @data: Pointer to read data from the register
1170 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1171 u32 device_type, u32 *data)
1173 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1177 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1178 if (ret != IXGBE_SUCCESS)
1181 ret = ixgbe_iosf_wait(hw, NULL);
1182 if (ret != IXGBE_SUCCESS)
1185 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1186 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1188 /* Write IOSF control register */
1189 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1191 ret = ixgbe_iosf_wait(hw, &command);
1193 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1194 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1195 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1196 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1197 "Failed to read, error %x\n", error);
1198 ret = IXGBE_ERR_PHY;
1201 if (ret == IXGBE_SUCCESS)
1202 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1205 ixgbe_release_swfw_semaphore(hw, gssr);
1210 * ixgbe_get_phy_token - Get the token for shared phy access
1211 * @hw: Pointer to hardware structure
1214 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1216 struct ixgbe_hic_phy_token_req token_cmd;
1219 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1220 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1221 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1222 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1223 token_cmd.port_number = hw->bus.lan_id;
1224 token_cmd.command_type = FW_PHY_TOKEN_REQ;
1226 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1228 IXGBE_HI_COMMAND_TIMEOUT,
1232 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1233 return IXGBE_SUCCESS;
1234 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1235 return IXGBE_ERR_FW_RESP_INVALID;
1237 return IXGBE_ERR_TOKEN_RETRY;
1241 * ixgbe_put_phy_token - Put the token for shared phy access
1242 * @hw: Pointer to hardware structure
1245 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1247 struct ixgbe_hic_phy_token_req token_cmd;
1250 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1251 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1252 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1253 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1254 token_cmd.port_number = hw->bus.lan_id;
1255 token_cmd.command_type = FW_PHY_TOKEN_REL;
1257 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1259 IXGBE_HI_COMMAND_TIMEOUT,
1263 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1264 return IXGBE_SUCCESS;
1266 DEBUGOUT("Put PHY Token host interface command failed");
1267 return IXGBE_ERR_FW_RESP_INVALID;
1271 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1272 * of the IOSF device
1273 * @hw: pointer to hardware structure
1274 * @reg_addr: 32 bit PHY register to write
1275 * @device_type: 3 bit device type
1276 * @data: Data to write to the register
1278 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1279 u32 device_type, u32 data)
1281 struct ixgbe_hic_internal_phy_req write_cmd;
1283 UNREFERENCED_1PARAMETER(device_type);
1285 memset(&write_cmd, 0, sizeof(write_cmd));
1286 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1287 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1288 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1289 write_cmd.port_number = hw->bus.lan_id;
1290 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1291 write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1292 write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1294 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1296 IXGBE_HI_COMMAND_TIMEOUT, false);
1302 * ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1303 * @hw: pointer to hardware structure
1304 * @reg_addr: 32 bit PHY register to write
1305 * @device_type: 3 bit device type
1306 * @data: Pointer to read data from the register
1308 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1309 u32 device_type, u32 *data)
1312 struct ixgbe_hic_internal_phy_req cmd;
1313 struct ixgbe_hic_internal_phy_resp rsp;
1316 UNREFERENCED_1PARAMETER(device_type);
1318 memset(&hic, 0, sizeof(hic));
1319 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1320 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1321 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1322 hic.cmd.port_number = hw->bus.lan_id;
1323 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1324 hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1326 status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1328 IXGBE_HI_COMMAND_TIMEOUT, true);
1330 /* Extract the register value from the response. */
1331 *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1337 * ixgbe_disable_mdd_X550
1338 * @hw: pointer to hardware structure
1340 * Disable malicious driver detection
1342 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1346 DEBUGFUNC("ixgbe_disable_mdd_X550");
1348 /* Disable MDD for TX DMA and interrupt */
1349 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1350 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1351 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1353 /* Disable MDD for RX and interrupt */
1354 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1355 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1356 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1360 * ixgbe_enable_mdd_X550
1361 * @hw: pointer to hardware structure
1363 * Enable malicious driver detection
1365 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1369 DEBUGFUNC("ixgbe_enable_mdd_X550");
1371 /* Enable MDD for TX DMA and interrupt */
1372 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1373 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1374 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1376 /* Enable MDD for RX and interrupt */
1377 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1378 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1379 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1383 * ixgbe_restore_mdd_vf_X550
1384 * @hw: pointer to hardware structure
1387 * Restore VF that was disabled during malicious driver detection event
1389 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1391 u32 idx, reg, num_qs, start_q, bitmask;
1393 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1395 /* Map VF to queues */
1396 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1397 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1398 case IXGBE_MRQC_VMDQRT8TCEN:
1399 num_qs = 8; /* 16 VFs / pools */
1400 bitmask = 0x000000FF;
1402 case IXGBE_MRQC_VMDQRSS32EN:
1403 case IXGBE_MRQC_VMDQRT4TCEN:
1404 num_qs = 4; /* 32 VFs / pools */
1405 bitmask = 0x0000000F;
1407 default: /* 64 VFs / pools */
1409 bitmask = 0x00000003;
1412 start_q = vf * num_qs;
1414 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1417 reg |= (bitmask << (start_q % 32));
1418 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1419 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1423 * ixgbe_mdd_event_X550
1424 * @hw: pointer to hardware structure
1425 * @vf_bitmap: vf bitmap of malicious vfs
1427 * Handle malicious driver detection event.
1429 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1432 u32 i, j, reg, q, shift, vf, idx;
1434 DEBUGFUNC("ixgbe_mdd_event_X550");
1436 /* figure out pool size for mapping to vf's */
1437 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1438 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1439 case IXGBE_MRQC_VMDQRT8TCEN:
1440 shift = 3; /* 16 VFs / pools */
1442 case IXGBE_MRQC_VMDQRSS32EN:
1443 case IXGBE_MRQC_VMDQRT4TCEN:
1444 shift = 2; /* 32 VFs / pools */
1447 shift = 1; /* 64 VFs / pools */
1451 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1452 for (i = 0; i < 4; i++) {
1453 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1454 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1459 /* Get malicious queue */
1460 for (j = 0; j < 32 && wqbr; j++) {
1462 if (!(wqbr & (1 << j)))
1465 /* Get queue from bitmask */
1468 /* Map queue to vf */
1471 /* Set vf bit in vf_bitmap */
1473 vf_bitmap[idx] |= (1 << (vf % 32));
1480 * ixgbe_get_media_type_X550em - Get media type
1481 * @hw: pointer to hardware structure
1483 * Returns the media type (fiber, copper, backplane)
1485 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1487 enum ixgbe_media_type media_type;
1489 DEBUGFUNC("ixgbe_get_media_type_X550em");
1491 /* Detect if there is a copper PHY attached. */
1492 switch (hw->device_id) {
1493 case IXGBE_DEV_ID_X550EM_X_KR:
1494 case IXGBE_DEV_ID_X550EM_X_KX4:
1495 case IXGBE_DEV_ID_X550EM_A_KR:
1496 case IXGBE_DEV_ID_X550EM_A_KR_L:
1497 media_type = ixgbe_media_type_backplane;
1499 case IXGBE_DEV_ID_X550EM_X_SFP:
1500 case IXGBE_DEV_ID_X550EM_A_SFP:
1501 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1502 case IXGBE_DEV_ID_X550EM_A_QSFP:
1503 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1504 media_type = ixgbe_media_type_fiber;
1506 case IXGBE_DEV_ID_X550EM_X_1G_T:
1507 case IXGBE_DEV_ID_X550EM_X_10G_T:
1508 case IXGBE_DEV_ID_X550EM_A_10G_T:
1509 media_type = ixgbe_media_type_copper;
1511 case IXGBE_DEV_ID_X550EM_A_SGMII:
1512 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1513 media_type = ixgbe_media_type_backplane;
1514 hw->phy.type = ixgbe_phy_sgmii;
1516 case IXGBE_DEV_ID_X550EM_A_1G_T:
1517 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1518 media_type = ixgbe_media_type_copper;
1521 media_type = ixgbe_media_type_unknown;
1528 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1529 * @hw: pointer to hardware structure
1530 * @linear: true if SFP module is linear
1532 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1534 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1536 switch (hw->phy.sfp_type) {
1537 case ixgbe_sfp_type_not_present:
1538 return IXGBE_ERR_SFP_NOT_PRESENT;
1539 case ixgbe_sfp_type_da_cu_core0:
1540 case ixgbe_sfp_type_da_cu_core1:
1543 case ixgbe_sfp_type_srlr_core0:
1544 case ixgbe_sfp_type_srlr_core1:
1545 case ixgbe_sfp_type_da_act_lmt_core0:
1546 case ixgbe_sfp_type_da_act_lmt_core1:
1547 case ixgbe_sfp_type_1g_sx_core0:
1548 case ixgbe_sfp_type_1g_sx_core1:
1549 case ixgbe_sfp_type_1g_lx_core0:
1550 case ixgbe_sfp_type_1g_lx_core1:
1553 case ixgbe_sfp_type_unknown:
1554 case ixgbe_sfp_type_1g_cu_core0:
1555 case ixgbe_sfp_type_1g_cu_core1:
1557 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1560 return IXGBE_SUCCESS;
1564 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1565 * @hw: pointer to hardware structure
1567 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1569 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1574 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1576 status = ixgbe_identify_module_generic(hw);
1578 if (status != IXGBE_SUCCESS)
1581 /* Check if SFP module is supported */
1582 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1588 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1589 * @hw: pointer to hardware structure
1591 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1596 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1598 /* Check if SFP module is supported */
1599 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1601 if (status != IXGBE_SUCCESS)
1604 ixgbe_init_mac_link_ops_X550em(hw);
1605 hw->phy.ops.reset = NULL;
1607 return IXGBE_SUCCESS;
1611 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1613 * @hw: pointer to hardware structure
1615 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1620 /* Restart auto-negotiation. */
1621 status = hw->mac.ops.read_iosf_sb_reg(hw,
1622 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1623 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1626 DEBUGOUT("Auto-negotiation did not complete\n");
1630 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1631 status = hw->mac.ops.write_iosf_sb_reg(hw,
1632 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1633 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1635 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1638 /* Indicate to FW that AN restart has been asserted */
1639 status = hw->mac.ops.read_iosf_sb_reg(hw,
1640 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1641 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1644 DEBUGOUT("Auto-negotiation did not complete\n");
1648 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1649 status = hw->mac.ops.write_iosf_sb_reg(hw,
1650 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1651 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1658 * ixgbe_setup_sgmii - Set up link for sgmii
1659 * @hw: pointer to hardware structure
1661 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1664 struct ixgbe_mac_info *mac = &hw->mac;
1665 u32 lval, sval, flx_val;
1668 rc = mac->ops.read_iosf_sb_reg(hw,
1669 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1670 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1674 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1675 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1676 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1677 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1678 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1679 rc = mac->ops.write_iosf_sb_reg(hw,
1680 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1681 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1685 rc = mac->ops.read_iosf_sb_reg(hw,
1686 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1687 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1691 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1692 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1693 rc = mac->ops.write_iosf_sb_reg(hw,
1694 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1695 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1699 rc = mac->ops.read_iosf_sb_reg(hw,
1700 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1701 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1705 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1706 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1707 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1708 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1709 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1711 rc = mac->ops.write_iosf_sb_reg(hw,
1712 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1713 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1717 rc = ixgbe_restart_an_internal_phy_x550em(hw);
1721 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1725 * ixgbe_setup_sgmii_m88 - Set up link for sgmii with Marvell PHYs
1726 * @hw: pointer to hardware structure
1728 STATIC s32 ixgbe_setup_sgmii_m88(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1731 struct ixgbe_mac_info *mac = &hw->mac;
1732 u32 lval, sval, flx_val;
1735 rc = mac->ops.read_iosf_sb_reg(hw,
1736 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1737 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1741 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1742 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1743 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1744 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1745 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1746 rc = mac->ops.write_iosf_sb_reg(hw,
1747 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1748 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1752 rc = mac->ops.read_iosf_sb_reg(hw,
1753 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1754 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1758 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1759 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1760 rc = mac->ops.write_iosf_sb_reg(hw,
1761 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1762 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1766 rc = mac->ops.write_iosf_sb_reg(hw,
1767 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1768 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1772 rc = mac->ops.read_iosf_sb_reg(hw,
1773 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1774 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1778 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1779 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1780 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1781 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1782 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1784 rc = mac->ops.write_iosf_sb_reg(hw,
1785 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1786 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1790 rc = ixgbe_restart_an_internal_phy_x550em(hw);
1792 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1796 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1797 * @hw: pointer to hardware structure
1799 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1801 struct ixgbe_mac_info *mac = &hw->mac;
1803 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1805 switch (hw->mac.ops.get_media_type(hw)) {
1806 case ixgbe_media_type_fiber:
1807 /* CS4227 does not support autoneg, so disable the laser control
1808 * functions for SFP+ fiber
1810 mac->ops.disable_tx_laser = NULL;
1811 mac->ops.enable_tx_laser = NULL;
1812 mac->ops.flap_tx_laser = NULL;
1813 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1814 mac->ops.set_rate_select_speed =
1815 ixgbe_set_soft_rate_select_speed;
1817 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1818 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1819 mac->ops.setup_mac_link =
1820 ixgbe_setup_mac_link_sfp_x550a;
1822 mac->ops.setup_mac_link =
1823 ixgbe_setup_mac_link_sfp_x550em;
1825 case ixgbe_media_type_copper:
1826 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1827 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1828 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1829 mac->ops.setup_link = ixgbe_setup_sgmii_m88;
1831 mac->ops.setup_link =
1832 ixgbe_setup_mac_link_t_X550em;
1835 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1836 mac->ops.check_link = ixgbe_check_link_t_X550em;
1839 case ixgbe_media_type_backplane:
1840 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1841 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1842 mac->ops.setup_link = ixgbe_setup_sgmii;
1850 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1851 * @hw: pointer to hardware structure
1852 * @speed: pointer to link speed
1853 * @autoneg: true when autoneg or autotry is enabled
1855 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1856 ixgbe_link_speed *speed,
1859 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1863 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1865 /* CS4227 SFP must not enable auto-negotiation */
1868 /* Check if 1G SFP module. */
1869 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1870 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1871 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1872 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1873 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1874 return IXGBE_SUCCESS;
1877 /* Link capabilities are based on SFP */
1878 if (hw->phy.multispeed_fiber)
1879 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1880 IXGBE_LINK_SPEED_1GB_FULL;
1882 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1884 switch (hw->phy.type) {
1886 *speed = IXGBE_LINK_SPEED_1GB_FULL |
1887 IXGBE_LINK_SPEED_100_FULL |
1888 IXGBE_LINK_SPEED_10_FULL;
1890 case ixgbe_phy_sgmii:
1891 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1893 case ixgbe_phy_x550em_kr:
1894 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1895 /* check different backplane modes */
1896 if (hw->phy.nw_mng_if_sel &
1897 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
1898 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
1900 } else if (hw->device_id ==
1901 IXGBE_DEV_ID_X550EM_A_KR_L) {
1902 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1908 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1909 IXGBE_LINK_SPEED_1GB_FULL;
1915 return IXGBE_SUCCESS;
1919 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1920 * @hw: pointer to hardware structure
1921 * @lsc: pointer to boolean flag which indicates whether external Base T
1922 * PHY interrupt is lsc
1924 * Determime if external Base T PHY interrupt cause is high temperature
1925 * failure alarm or link status change.
1927 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1928 * failure alarm, else return PHY access status.
1930 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1937 /* Vendor alarm triggered */
1938 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1939 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1942 if (status != IXGBE_SUCCESS ||
1943 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1946 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1947 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1948 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1951 if (status != IXGBE_SUCCESS ||
1952 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1953 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1956 /* Global alarm triggered */
1957 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1958 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1961 if (status != IXGBE_SUCCESS)
1964 /* If high temperature failure, then return over temp error and exit */
1965 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1966 /* power down the PHY in case the PHY FW didn't already */
1967 ixgbe_set_copper_phy_power(hw, false);
1968 return IXGBE_ERR_OVERTEMP;
1969 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1970 /* device fault alarm triggered */
1971 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1972 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1975 if (status != IXGBE_SUCCESS)
1978 /* if device fault was due to high temp alarm handle and exit */
1979 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1980 /* power down the PHY in case the PHY FW didn't */
1981 ixgbe_set_copper_phy_power(hw, false);
1982 return IXGBE_ERR_OVERTEMP;
1986 /* Vendor alarm 2 triggered */
1987 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1988 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1990 if (status != IXGBE_SUCCESS ||
1991 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1994 /* link connect/disconnect event occurred */
1995 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1996 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1998 if (status != IXGBE_SUCCESS)
2002 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2005 return IXGBE_SUCCESS;
2009 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2010 * @hw: pointer to hardware structure
2012 * Enable link status change and temperature failure alarm for the external
2015 * Returns PHY access status
2017 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2023 /* Clear interrupt flags */
2024 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2026 /* Enable link status change alarm */
2027 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2028 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
2030 if (status != IXGBE_SUCCESS)
2033 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2035 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2036 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2038 if (status != IXGBE_SUCCESS)
2041 /* Enable high temperature failure and global fault alarms */
2042 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2043 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2046 if (status != IXGBE_SUCCESS)
2049 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2050 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2052 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2053 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2056 if (status != IXGBE_SUCCESS)
2059 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2060 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2061 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2064 if (status != IXGBE_SUCCESS)
2067 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2068 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2070 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2071 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2074 if (status != IXGBE_SUCCESS)
2077 /* Enable chip-wide vendor alarm */
2078 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2079 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2082 if (status != IXGBE_SUCCESS)
2085 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2087 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2088 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2095 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2096 * @hw: pointer to hardware structure
2097 * @speed: link speed
2099 * Configures the integrated KR PHY.
2101 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2102 ixgbe_link_speed speed)
2107 status = hw->mac.ops.read_iosf_sb_reg(hw,
2108 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2109 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2113 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2114 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2115 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2117 /* Advertise 10G support. */
2118 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2119 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2121 /* Advertise 1G support. */
2122 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2123 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2125 status = hw->mac.ops.write_iosf_sb_reg(hw,
2126 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2127 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2129 if (hw->mac.type == ixgbe_mac_X550EM_a) {
2130 /* Set lane mode to KR auto negotiation */
2131 status = hw->mac.ops.read_iosf_sb_reg(hw,
2132 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2133 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2138 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2139 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2140 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2141 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2142 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2144 status = hw->mac.ops.write_iosf_sb_reg(hw,
2145 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2146 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2149 return ixgbe_restart_an_internal_phy_x550em(hw);
2153 * ixgbe_setup_m88 - setup m88 PHY
2154 * @hw: pointer to hardware structure
2156 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2158 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2162 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2163 return IXGBE_SUCCESS;
2165 rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2169 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2172 if (reg & IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN) {
2173 reg &= ~IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN;
2174 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2178 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, ®);
2181 if (reg & IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN) {
2182 reg &= ~IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN;
2183 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0,
2187 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 2);
2191 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2195 if (reg & IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN) {
2196 reg &= ~IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN;
2197 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2199 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2203 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2207 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2208 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2212 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2218 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2222 if (!(reg & IXGBE_M88E1500_COPPER_CTRL_AN_EN)) {
2223 reg |= IXGBE_M88E1500_COPPER_CTRL_AN_EN;
2224 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2228 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, ®);
2231 reg &= ~IXGBE_M88E1500_1000T_CTRL_HALF_DUPLEX;
2232 reg &= ~IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2233 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
2234 reg |= IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2235 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, reg);
2237 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, ®);
2240 reg &= ~IXGBE_M88E1500_COPPER_AN_T4;
2241 reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_FD;
2242 reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_HD;
2243 reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_FD;
2244 reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_HD;
2246 /* Flow control auto negotiation configuration was moved from here to
2247 * the function ixgbe_setup_fc_sgmii_x550em_a()
2250 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
2251 reg |= IXGBE_M88E1500_COPPER_AN_100TX_FD;
2252 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
2253 reg |= IXGBE_M88E1500_COPPER_AN_10TX_FD;
2254 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, reg);
2256 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2259 reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
2260 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2263 hw->mac.ops.release_swfw_sync(hw, mask);
2267 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2268 hw->mac.ops.release_swfw_sync(hw, mask);
2273 * ixgbe_reset_phy_m88e1500 - Reset m88e1500 PHY
2274 * @hw: pointer to hardware structure
2276 * The PHY token must be held when calling this function.
2278 static s32 ixgbe_reset_phy_m88e1500(struct ixgbe_hw *hw)
2283 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2287 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2291 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2292 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2300 * ixgbe_reset_phy_m88e1543 - Reset m88e1543 PHY
2301 * @hw: pointer to hardware structure
2303 * The PHY token must be held when calling this function.
2305 static s32 ixgbe_reset_phy_m88e1543(struct ixgbe_hw *hw)
2307 return hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2311 * ixgbe_reset_phy_m88 - Reset m88 PHY
2312 * @hw: pointer to hardware structure
2314 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2316 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2320 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2321 return IXGBE_SUCCESS;
2323 rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2327 switch (hw->phy.id) {
2328 case IXGBE_M88E1500_E_PHY_ID:
2329 rc = ixgbe_reset_phy_m88e1500(hw);
2331 case IXGBE_M88E1543_E_PHY_ID:
2332 rc = ixgbe_reset_phy_m88e1543(hw);
2339 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2343 reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2344 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2345 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2346 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2350 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2354 reg = IXGBE_M88E1500_GEN_CTRL_RESET |
2355 IXGBE_M88E1500_GEN_CTRL_MODE_SGMII_COPPER;
2356 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_GEN_CTRL, 0, reg);
2360 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2364 reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2365 IXGBE_M88E1500_FIBER_CTRL_AN_EN |
2366 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2367 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2368 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2372 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2376 reg = (IXGBE_M88E1500_MAC_CTRL_1_DWN_4X <<
2377 IXGBE_M88E1500_MAC_CTRL_1_DWN_SHIFT) |
2378 (IXGBE_M88E1500_MAC_CTRL_1_ED_TM <<
2379 IXGBE_M88E1500_MAC_CTRL_1_ED_SHIFT) |
2380 (IXGBE_M88E1500_MAC_CTRL_1_MDIX_AUTO <<
2381 IXGBE_M88E1500_MAC_CTRL_1_MDIX_SHIFT);
2382 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, reg);
2386 reg = IXGBE_M88E1500_COPPER_CTRL_RESET |
2387 IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2388 IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2389 IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2390 IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB;
2391 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2395 hw->mac.ops.release_swfw_sync(hw, mask);
2397 /* In case of first reset set advertised speeds to default value */
2398 if (!hw->phy.autoneg_advertised)
2399 hw->phy.autoneg_advertised = IXGBE_LINK_SPEED_1GB_FULL |
2400 IXGBE_LINK_SPEED_100_FULL |
2401 IXGBE_LINK_SPEED_10_FULL;
2403 return ixgbe_setup_m88(hw);
2406 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2407 hw->mac.ops.release_swfw_sync(hw, mask);
2412 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2413 * @hw: pointer to hardware structure
2415 * Read NW_MNG_IF_SEL register and save field values, and check for valid field
2418 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2420 /* Save NW management interface connected on board. This is used
2421 * to determine internal PHY mode.
2423 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2425 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2426 * PHY address. This register field was has only been used for X552.
2428 if (hw->mac.type == ixgbe_mac_X550EM_a &&
2429 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2430 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2431 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2432 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2435 return IXGBE_SUCCESS;
2439 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2440 * @hw: pointer to hardware structure
2442 * Initialize any function pointers that were not able to be
2443 * set during init_shared_code because the PHY/SFP type was
2444 * not known. Perform the SFP init if necessary.
2446 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2448 struct ixgbe_phy_info *phy = &hw->phy;
2451 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2453 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2454 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2455 ixgbe_setup_mux_ctl(hw);
2456 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2459 switch (hw->device_id) {
2460 case IXGBE_DEV_ID_X550EM_A_1G_T:
2461 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2462 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2463 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2464 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2465 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2467 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2469 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2472 case IXGBE_DEV_ID_X550EM_A_10G_T:
2473 case IXGBE_DEV_ID_X550EM_A_SFP:
2474 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2475 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2477 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2479 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2481 case IXGBE_DEV_ID_X550EM_X_SFP:
2482 /* set up for CS4227 usage */
2483 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2489 /* Identify the PHY or SFP module */
2490 ret_val = phy->ops.identify(hw);
2491 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2494 /* Setup function pointers based on detected hardware */
2495 ixgbe_init_mac_link_ops_X550em(hw);
2496 if (phy->sfp_type != ixgbe_sfp_type_unknown)
2497 phy->ops.reset = NULL;
2499 /* Set functions pointers based on phy type */
2500 switch (hw->phy.type) {
2501 case ixgbe_phy_x550em_kx4:
2502 phy->ops.setup_link = NULL;
2503 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2504 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2506 case ixgbe_phy_x550em_kr:
2507 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2508 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2509 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2511 case ixgbe_phy_x550em_ext_t:
2512 /* If internal link mode is XFI, then setup iXFI internal link,
2513 * else setup KR now.
2515 phy->ops.setup_internal_link =
2516 ixgbe_setup_internal_phy_t_x550em;
2518 /* setup SW LPLU only for first revision of X550EM_x */
2519 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2520 !(IXGBE_FUSES0_REV_MASK &
2521 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2522 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2524 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2525 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2527 case ixgbe_phy_sgmii:
2528 phy->ops.setup_link = NULL;
2531 phy->ops.setup_link = ixgbe_setup_m88;
2532 phy->ops.reset = ixgbe_reset_phy_m88;
2541 * ixgbe_set_mdio_speed - Set MDIO clock speed
2542 * @hw: pointer to hardware structure
2544 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2548 switch (hw->device_id) {
2549 case IXGBE_DEV_ID_X550EM_X_10G_T:
2550 case IXGBE_DEV_ID_X550EM_A_SGMII:
2551 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2552 case IXGBE_DEV_ID_X550EM_A_10G_T:
2553 case IXGBE_DEV_ID_X550EM_A_SFP:
2554 case IXGBE_DEV_ID_X550EM_A_QSFP:
2555 /* Config MDIO clock speed before the first MDIO PHY access */
2556 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2557 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2558 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2560 case IXGBE_DEV_ID_X550EM_A_1G_T:
2561 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2562 /* Select fast MDIO clock speed for these devices */
2563 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2564 hlreg0 |= IXGBE_HLREG0_MDCSPD;
2565 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2573 * ixgbe_reset_hw_X550em - Perform hardware reset
2574 * @hw: pointer to hardware structure
2576 * Resets the hardware by resetting the transmit and receive units, masks
2577 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2580 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2582 ixgbe_link_speed link_speed;
2586 bool link_up = false;
2588 DEBUGFUNC("ixgbe_reset_hw_X550em");
2590 /* Call adapter stop to disable Tx/Rx and clear interrupts */
2591 status = hw->mac.ops.stop_adapter(hw);
2592 if (status != IXGBE_SUCCESS)
2595 /* flush pending Tx transactions */
2596 ixgbe_clear_tx_pending(hw);
2598 ixgbe_set_mdio_speed(hw);
2600 /* PHY ops must be identified and initialized prior to reset */
2601 status = hw->phy.ops.init(hw);
2603 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2606 /* start the external PHY */
2607 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2608 status = ixgbe_init_ext_t_x550em(hw);
2613 /* Setup SFP module if there is one present. */
2614 if (hw->phy.sfp_setup_needed) {
2615 status = hw->mac.ops.setup_sfp(hw);
2616 hw->phy.sfp_setup_needed = false;
2619 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2623 if (!hw->phy.reset_disable && hw->phy.ops.reset)
2624 hw->phy.ops.reset(hw);
2627 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
2628 * If link reset is used when link is up, it might reset the PHY when
2629 * mng is using it. If link is down or the flag to force full link
2630 * reset is set, then perform link reset.
2632 ctrl = IXGBE_CTRL_LNK_RST;
2633 if (!hw->force_full_reset) {
2634 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2636 ctrl = IXGBE_CTRL_RST;
2639 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2640 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2641 IXGBE_WRITE_FLUSH(hw);
2643 /* Poll for reset bit to self-clear meaning reset is complete */
2644 for (i = 0; i < 10; i++) {
2646 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2647 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2651 if (ctrl & IXGBE_CTRL_RST_MASK) {
2652 status = IXGBE_ERR_RESET_FAILED;
2653 DEBUGOUT("Reset polling failed to complete.\n");
2658 /* Double resets are required for recovery from certain error
2659 * conditions. Between resets, it is necessary to stall to
2660 * allow time for any pending HW events to complete.
2662 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2663 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2667 /* Store the permanent mac address */
2668 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2670 /* Store MAC address from RAR0, clear receive address registers, and
2671 * clear the multicast table. Also reset num_rar_entries to 128,
2672 * since we modify this value when programming the SAN MAC address.
2674 hw->mac.num_rar_entries = 128;
2675 hw->mac.ops.init_rx_addrs(hw);
2677 ixgbe_set_mdio_speed(hw);
2679 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2680 ixgbe_setup_mux_ctl(hw);
2686 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2687 * @hw: pointer to hardware structure
2689 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2694 status = hw->phy.ops.read_reg(hw,
2695 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2696 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2699 if (status != IXGBE_SUCCESS)
2702 /* If PHY FW reset completed bit is set then this is the first
2703 * SW instance after a power on so the PHY FW must be un-stalled.
2705 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2706 status = hw->phy.ops.read_reg(hw,
2707 IXGBE_MDIO_GLOBAL_RES_PR_10,
2708 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2711 if (status != IXGBE_SUCCESS)
2714 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2716 status = hw->phy.ops.write_reg(hw,
2717 IXGBE_MDIO_GLOBAL_RES_PR_10,
2718 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2721 if (status != IXGBE_SUCCESS)
2729 * ixgbe_setup_kr_x550em - Configure the KR PHY.
2730 * @hw: pointer to hardware structure
2732 * Configures the integrated KR PHY for X550EM_x.
2734 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2736 if (hw->mac.type != ixgbe_mac_X550EM_x)
2737 return IXGBE_SUCCESS;
2739 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2743 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2744 * @hw: pointer to hardware structure
2746 * Configure the external PHY and the integrated KR PHY for SFP support.
2748 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2749 ixgbe_link_speed speed,
2750 bool autoneg_wait_to_complete)
2753 u16 reg_slice, reg_val;
2754 bool setup_linear = false;
2755 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2757 /* Check if SFP module is supported and linear */
2758 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2760 /* If no SFP module present, then return success. Return success since
2761 * there is no reason to configure CS4227 and SFP not present error is
2762 * not excepted in the setup MAC link flow.
2764 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2765 return IXGBE_SUCCESS;
2767 if (ret_val != IXGBE_SUCCESS)
2770 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2771 /* Configure CS4227 LINE side to 10G SR. */
2772 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2773 (hw->bus.lan_id << 12);
2774 reg_val = IXGBE_CS4227_SPEED_10G;
2775 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2778 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2779 (hw->bus.lan_id << 12);
2780 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2781 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2784 /* Configure CS4227 for HOST connection rate then type. */
2785 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2786 (hw->bus.lan_id << 12);
2787 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2788 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2789 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2792 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2793 (hw->bus.lan_id << 12);
2795 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2797 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2798 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2801 /* Setup XFI internal link. */
2802 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2804 /* Configure internal PHY for KR/KX. */
2805 ixgbe_setup_kr_speed_x550em(hw, speed);
2807 /* Configure CS4227 LINE side to proper mode. */
2808 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2809 (hw->bus.lan_id << 12);
2811 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2813 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2814 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2821 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2822 * @hw: pointer to hardware structure
2823 * @speed: the link speed to force
2825 * Configures the integrated PHY for native SFI mode. Used to connect the
2826 * internal PHY directly to an SFP cage, without autonegotiation.
2828 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2830 struct ixgbe_mac_info *mac = &hw->mac;
2834 /* Disable all AN and force speed to 10G Serial. */
2835 status = mac->ops.read_iosf_sb_reg(hw,
2836 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2837 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2838 if (status != IXGBE_SUCCESS)
2841 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2842 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2843 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2844 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2846 /* Select forced link speed for internal PHY. */
2848 case IXGBE_LINK_SPEED_10GB_FULL:
2849 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2851 case IXGBE_LINK_SPEED_1GB_FULL:
2852 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2855 /* Other link speeds are not supported by internal PHY. */
2856 return IXGBE_ERR_LINK_SETUP;
2859 status = mac->ops.write_iosf_sb_reg(hw,
2860 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2861 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2863 /* Toggle port SW reset by AN reset. */
2864 status = ixgbe_restart_an_internal_phy_x550em(hw);
2870 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2871 * @hw: pointer to hardware structure
2873 * Configure the the integrated PHY for SFP support.
2875 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2876 ixgbe_link_speed speed,
2877 bool autoneg_wait_to_complete)
2881 bool setup_linear = false;
2882 u32 reg_slice, reg_phy_int, slice_offset;
2884 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2886 /* Check if SFP module is supported and linear */
2887 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2889 /* If no SFP module present, then return success. Return success since
2890 * SFP not present error is not excepted in the setup MAC link flow.
2892 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2893 return IXGBE_SUCCESS;
2895 if (ret_val != IXGBE_SUCCESS)
2898 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2899 /* Configure internal PHY for native SFI based on module type */
2900 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2901 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2902 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
2904 if (ret_val != IXGBE_SUCCESS)
2907 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2909 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2911 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2912 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2913 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2915 if (ret_val != IXGBE_SUCCESS)
2918 /* Setup SFI internal link. */
2919 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2921 /* Configure internal PHY for KR/KX. */
2922 ixgbe_setup_kr_speed_x550em(hw, speed);
2924 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2926 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2927 return IXGBE_ERR_PHY_ADDR_INVALID;
2930 /* Get external PHY device id */
2931 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2932 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2934 if (ret_val != IXGBE_SUCCESS)
2937 /* When configuring quad port CS4223, the MAC instance is part
2938 * of the slice offset.
2940 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2941 slice_offset = (hw->bus.lan_id +
2942 (hw->bus.instance_id << 1)) << 12;
2944 slice_offset = hw->bus.lan_id << 12;
2946 /* Configure CS4227/CS4223 LINE side to proper mode. */
2947 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2949 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2951 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2952 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2953 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2959 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2960 * @hw: pointer to hardware structure
2962 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2964 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2966 struct ixgbe_mac_info *mac = &hw->mac;
2970 /* Disable training protocol FSM. */
2971 status = mac->ops.read_iosf_sb_reg(hw,
2972 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2973 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2974 if (status != IXGBE_SUCCESS)
2976 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2977 status = mac->ops.write_iosf_sb_reg(hw,
2978 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2979 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2980 if (status != IXGBE_SUCCESS)
2983 /* Disable Flex from training TXFFE. */
2984 status = mac->ops.read_iosf_sb_reg(hw,
2985 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2986 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2987 if (status != IXGBE_SUCCESS)
2989 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2990 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2991 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2992 status = mac->ops.write_iosf_sb_reg(hw,
2993 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2994 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2995 if (status != IXGBE_SUCCESS)
2997 status = mac->ops.read_iosf_sb_reg(hw,
2998 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2999 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3000 if (status != IXGBE_SUCCESS)
3002 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
3003 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
3004 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
3005 status = mac->ops.write_iosf_sb_reg(hw,
3006 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
3007 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3008 if (status != IXGBE_SUCCESS)
3011 /* Enable override for coefficients. */
3012 status = mac->ops.read_iosf_sb_reg(hw,
3013 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
3014 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3015 if (status != IXGBE_SUCCESS)
3017 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
3018 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
3019 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
3020 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
3021 status = mac->ops.write_iosf_sb_reg(hw,
3022 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
3023 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3028 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
3029 * @hw: pointer to hardware structure
3030 * @speed: the link speed to force
3032 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
3033 * internal and external PHY at a specific speed, without autonegotiation.
3035 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
3037 struct ixgbe_mac_info *mac = &hw->mac;
3041 /* Disable AN and force speed to 10G Serial. */
3042 status = mac->ops.read_iosf_sb_reg(hw,
3043 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3044 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3045 if (status != IXGBE_SUCCESS)
3048 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3049 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3051 /* Select forced link speed for internal PHY. */
3053 case IXGBE_LINK_SPEED_10GB_FULL:
3054 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3056 case IXGBE_LINK_SPEED_1GB_FULL:
3057 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
3060 /* Other link speeds are not supported by internal KR PHY. */
3061 return IXGBE_ERR_LINK_SETUP;
3064 status = mac->ops.write_iosf_sb_reg(hw,
3065 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3066 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3067 if (status != IXGBE_SUCCESS)
3070 /* Additional configuration needed for x550em_x */
3071 if (hw->mac.type == ixgbe_mac_X550EM_x) {
3072 status = ixgbe_setup_ixfi_x550em_x(hw);
3073 if (status != IXGBE_SUCCESS)
3077 /* Toggle port SW reset by AN reset. */
3078 status = ixgbe_restart_an_internal_phy_x550em(hw);
3084 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
3085 * @hw: address of hardware structure
3086 * @link_up: address of boolean to indicate link status
3088 * Returns error code if unable to get link status.
3090 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
3097 /* read this twice back to back to indicate current status */
3098 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3099 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3101 if (ret != IXGBE_SUCCESS)
3104 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3105 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3107 if (ret != IXGBE_SUCCESS)
3110 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
3112 return IXGBE_SUCCESS;
3116 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
3117 * @hw: point to hardware structure
3119 * Configures the link between the integrated KR PHY and the external X557 PHY
3120 * The driver will call this function when it gets a link status change
3121 * interrupt from the X557 PHY. This function configures the link speed
3122 * between the PHYs to match the link speed of the BASE-T link.
3124 * A return of a non-zero value indicates an error, and the base driver should
3125 * not report link up.
3127 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
3129 ixgbe_link_speed force_speed;
3134 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3135 return IXGBE_ERR_CONFIG;
3137 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3138 /* If link is down, there is no setup necessary so return */
3139 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3140 if (status != IXGBE_SUCCESS)
3144 return IXGBE_SUCCESS;
3146 status = hw->phy.ops.read_reg(hw,
3147 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3148 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3150 if (status != IXGBE_SUCCESS)
3153 /* If link is still down - no setup is required so return */
3154 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3155 if (status != IXGBE_SUCCESS)
3158 return IXGBE_SUCCESS;
3160 /* clear everything but the speed and duplex bits */
3161 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3164 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3165 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3167 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3168 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3171 /* Internal PHY does not support anything else */
3172 return IXGBE_ERR_INVALID_LINK_SETTINGS;
3175 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3177 speed = IXGBE_LINK_SPEED_10GB_FULL |
3178 IXGBE_LINK_SPEED_1GB_FULL;
3179 return ixgbe_setup_kr_speed_x550em(hw, speed);
3184 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3185 * @hw: pointer to hardware structure
3187 * Configures the integrated KR PHY to use internal loopback mode.
3189 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3194 /* Disable AN and force speed to 10G Serial. */
3195 status = hw->mac.ops.read_iosf_sb_reg(hw,
3196 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3197 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3198 if (status != IXGBE_SUCCESS)
3200 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3201 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3202 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3203 status = hw->mac.ops.write_iosf_sb_reg(hw,
3204 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3205 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3206 if (status != IXGBE_SUCCESS)
3209 /* Set near-end loopback clocks. */
3210 status = hw->mac.ops.read_iosf_sb_reg(hw,
3211 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3212 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3213 if (status != IXGBE_SUCCESS)
3215 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3216 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3217 status = hw->mac.ops.write_iosf_sb_reg(hw,
3218 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3219 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3220 if (status != IXGBE_SUCCESS)
3223 /* Set loopback enable. */
3224 status = hw->mac.ops.read_iosf_sb_reg(hw,
3225 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3226 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3227 if (status != IXGBE_SUCCESS)
3229 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3230 status = hw->mac.ops.write_iosf_sb_reg(hw,
3231 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3232 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3233 if (status != IXGBE_SUCCESS)
3236 /* Training bypass. */
3237 status = hw->mac.ops.read_iosf_sb_reg(hw,
3238 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3239 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3240 if (status != IXGBE_SUCCESS)
3242 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3243 status = hw->mac.ops.write_iosf_sb_reg(hw,
3244 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3245 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3251 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3252 * assuming that the semaphore is already obtained.
3253 * @hw: pointer to hardware structure
3254 * @offset: offset of word in the EEPROM to read
3255 * @data: word read from the EEPROM
3257 * Reads a 16 bit word from the EEPROM using the hostif.
3259 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3261 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3262 struct ixgbe_hic_read_shadow_ram buffer;
3265 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3266 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3267 buffer.hdr.req.buf_lenh = 0;
3268 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3269 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3271 /* convert offset from words to bytes */
3272 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3274 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3276 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3280 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3281 IXGBE_HI_COMMAND_TIMEOUT);
3283 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3284 FW_NVM_DATA_OFFSET);
3287 hw->mac.ops.release_swfw_sync(hw, mask);
3292 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3293 * @hw: pointer to hardware structure
3294 * @offset: offset of word in the EEPROM to read
3295 * @words: number of words
3296 * @data: word(s) read from the EEPROM
3298 * Reads a 16 bit word(s) from the EEPROM using the hostif.
3300 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3301 u16 offset, u16 words, u16 *data)
3303 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3304 struct ixgbe_hic_read_shadow_ram buffer;
3305 u32 current_word = 0;
3310 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3312 /* Take semaphore for the entire operation. */
3313 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3315 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3320 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3321 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3323 words_to_read = words;
3325 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3326 buffer.hdr.req.buf_lenh = 0;
3327 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3328 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3330 /* convert offset from words to bytes */
3331 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3332 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3334 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3335 IXGBE_HI_COMMAND_TIMEOUT);
3338 DEBUGOUT("Host interface command failed\n");
3342 for (i = 0; i < words_to_read; i++) {
3343 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3345 u32 value = IXGBE_READ_REG(hw, reg);
3347 data[current_word] = (u16)(value & 0xffff);
3350 if (i < words_to_read) {
3352 data[current_word] = (u16)(value & 0xffff);
3356 words -= words_to_read;
3360 hw->mac.ops.release_swfw_sync(hw, mask);
3365 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3366 * @hw: pointer to hardware structure
3367 * @offset: offset of word in the EEPROM to write
3368 * @data: word write to the EEPROM
3370 * Write a 16 bit word to the EEPROM using the hostif.
3372 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3376 struct ixgbe_hic_write_shadow_ram buffer;
3378 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3380 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3381 buffer.hdr.req.buf_lenh = 0;
3382 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3383 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3386 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3388 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3390 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3392 IXGBE_HI_COMMAND_TIMEOUT, false);
3398 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3399 * @hw: pointer to hardware structure
3400 * @offset: offset of word in the EEPROM to write
3401 * @data: word write to the EEPROM
3403 * Write a 16 bit word to the EEPROM using the hostif.
3405 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3408 s32 status = IXGBE_SUCCESS;
3410 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3412 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3414 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3415 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3417 DEBUGOUT("write ee hostif failed to get semaphore");
3418 status = IXGBE_ERR_SWFW_SYNC;
3425 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3426 * @hw: pointer to hardware structure
3427 * @offset: offset of word in the EEPROM to write
3428 * @words: number of words
3429 * @data: word(s) write to the EEPROM
3431 * Write a 16 bit word(s) to the EEPROM using the hostif.
3433 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3434 u16 offset, u16 words, u16 *data)
3436 s32 status = IXGBE_SUCCESS;
3439 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3441 /* Take semaphore for the entire operation. */
3442 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3443 if (status != IXGBE_SUCCESS) {
3444 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3448 for (i = 0; i < words; i++) {
3449 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3452 if (status != IXGBE_SUCCESS) {
3453 DEBUGOUT("Eeprom buffered write failed\n");
3458 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3465 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3466 * @hw: pointer to hardware structure
3467 * @ptr: pointer offset in eeprom
3468 * @size: size of section pointed by ptr, if 0 first word will be used as size
3469 * @csum: address of checksum to update
3471 * Returns error status for any failure
3473 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3474 u16 size, u16 *csum, u16 *buffer,
3479 u16 length, bufsz, i, start;
3482 bufsz = sizeof(buf) / sizeof(buf[0]);
3484 /* Read a chunk at the pointer location */
3486 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3488 DEBUGOUT("Failed to read EEPROM image\n");
3493 if (buffer_size < ptr)
3494 return IXGBE_ERR_PARAM;
3495 local_buffer = &buffer[ptr];
3503 length = local_buffer[0];
3505 /* Skip pointer section if length is invalid. */
3506 if (length == 0xFFFF || length == 0 ||
3507 (ptr + length) >= hw->eeprom.word_size)
3508 return IXGBE_SUCCESS;
3511 if (buffer && ((u32)start + (u32)length > buffer_size))
3512 return IXGBE_ERR_PARAM;
3514 for (i = start; length; i++, length--) {
3515 if (i == bufsz && !buffer) {
3521 /* Read a chunk at the pointer location */
3522 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3525 DEBUGOUT("Failed to read EEPROM image\n");
3529 *csum += local_buffer[i];
3531 return IXGBE_SUCCESS;
3535 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3536 * @hw: pointer to hardware structure
3537 * @buffer: pointer to buffer containing calculated checksum
3538 * @buffer_size: size of buffer
3540 * Returns a negative error code on error, or the 16-bit checksum
3542 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3544 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3548 u16 pointer, i, size;
3550 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3552 hw->eeprom.ops.init_params(hw);
3555 /* Read pointer area */
3556 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3557 IXGBE_EEPROM_LAST_WORD + 1,
3560 DEBUGOUT("Failed to read EEPROM image\n");
3563 local_buffer = eeprom_ptrs;
3565 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3566 return IXGBE_ERR_PARAM;
3567 local_buffer = buffer;
3571 * For X550 hardware include 0x0-0x41 in the checksum, skip the
3572 * checksum word itself
3574 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3575 if (i != IXGBE_EEPROM_CHECKSUM)
3576 checksum += local_buffer[i];
3579 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
3580 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3582 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3583 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3586 pointer = local_buffer[i];
3588 /* Skip pointer section if the pointer is invalid. */
3589 if (pointer == 0xFFFF || pointer == 0 ||
3590 pointer >= hw->eeprom.word_size)
3594 case IXGBE_PCIE_GENERAL_PTR:
3595 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3597 case IXGBE_PCIE_CONFIG0_PTR:
3598 case IXGBE_PCIE_CONFIG1_PTR:
3599 size = IXGBE_PCIE_CONFIG_SIZE;
3606 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3607 buffer, buffer_size);
3612 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3614 return (s32)checksum;
3618 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3619 * @hw: pointer to hardware structure
3621 * Returns a negative error code on error, or the 16-bit checksum
3623 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3625 return ixgbe_calc_checksum_X550(hw, NULL, 0);
3629 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3630 * @hw: pointer to hardware structure
3631 * @checksum_val: calculated checksum
3633 * Performs checksum calculation and validates the EEPROM checksum. If the
3634 * caller does not need checksum_val, the value can be NULL.
3636 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3640 u16 read_checksum = 0;
3642 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3644 /* Read the first word from the EEPROM. If this times out or fails, do
3645 * not continue or we could be in for a very long wait while every
3648 status = hw->eeprom.ops.read(hw, 0, &checksum);
3650 DEBUGOUT("EEPROM read failed\n");
3654 status = hw->eeprom.ops.calc_checksum(hw);
3658 checksum = (u16)(status & 0xffff);
3660 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3665 /* Verify read checksum from EEPROM is the same as
3666 * calculated checksum
3668 if (read_checksum != checksum) {
3669 status = IXGBE_ERR_EEPROM_CHECKSUM;
3670 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3671 "Invalid EEPROM checksum");
3674 /* If the user cares, return the calculated checksum */
3676 *checksum_val = checksum;
3682 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3683 * @hw: pointer to hardware structure
3685 * After writing EEPROM to shadow RAM using EEWR register, software calculates
3686 * checksum and updates the EEPROM and instructs the hardware to update
3689 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3694 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3696 /* Read the first word from the EEPROM. If this times out or fails, do
3697 * not continue or we could be in for a very long wait while every
3700 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3702 DEBUGOUT("EEPROM read failed\n");
3706 status = ixgbe_calc_eeprom_checksum_X550(hw);
3710 checksum = (u16)(status & 0xffff);
3712 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3717 status = ixgbe_update_flash_X550(hw);
3723 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3724 * @hw: pointer to hardware structure
3726 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3728 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3730 s32 status = IXGBE_SUCCESS;
3731 union ixgbe_hic_hdr2 buffer;
3733 DEBUGFUNC("ixgbe_update_flash_X550");
3735 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3736 buffer.req.buf_lenh = 0;
3737 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3738 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3740 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3742 IXGBE_HI_COMMAND_TIMEOUT, false);
3748 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3749 * @hw: pointer to hardware structure
3751 * Determines physical layer capabilities of the current configuration.
3753 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3755 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3756 u16 ext_ability = 0;
3758 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3760 hw->phy.ops.identify(hw);
3762 switch (hw->phy.type) {
3763 case ixgbe_phy_x550em_kr:
3764 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3765 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3767 case ixgbe_phy_x550em_kx4:
3768 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3769 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3771 case ixgbe_phy_x550em_ext_t:
3772 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3773 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3775 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3776 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3777 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3778 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3784 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3785 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3787 return physical_layer;
3791 * ixgbe_get_bus_info_x550em - Set PCI bus info
3792 * @hw: pointer to hardware structure
3794 * Sets bus link width and speed to unknown because X550em is
3797 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3800 DEBUGFUNC("ixgbe_get_bus_info_x550em");
3802 hw->bus.width = ixgbe_bus_width_unknown;
3803 hw->bus.speed = ixgbe_bus_speed_unknown;
3805 hw->mac.ops.set_lan_id(hw);
3807 return IXGBE_SUCCESS;
3811 * ixgbe_disable_rx_x550 - Disable RX unit
3813 * Enables the Rx DMA unit for x550
3815 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3817 u32 rxctrl, pfdtxgswc;
3819 struct ixgbe_hic_disable_rxen fw_cmd;
3821 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3823 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3824 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3825 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3826 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3827 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3828 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3829 hw->mac.set_lben = true;
3831 hw->mac.set_lben = false;
3834 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3835 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3836 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3837 fw_cmd.port_number = (u8)hw->bus.lan_id;
3839 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3840 sizeof(struct ixgbe_hic_disable_rxen),
3841 IXGBE_HI_COMMAND_TIMEOUT, true);
3843 /* If we fail - disable RX using register write */
3845 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3846 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3847 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3848 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3855 * ixgbe_enter_lplu_x550em - Transition to low power states
3856 * @hw: pointer to hardware structure
3858 * Configures Low Power Link Up on transition to low power states
3859 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3860 * X557 PHY immediately prior to entering LPLU.
3862 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3864 u16 an_10g_cntl_reg, autoneg_reg, speed;
3866 ixgbe_link_speed lcd_speed;
3870 /* SW LPLU not required on later HW revisions. */
3871 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3872 (IXGBE_FUSES0_REV_MASK &
3873 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3874 return IXGBE_SUCCESS;
3876 /* If blocked by MNG FW, then don't restart AN */
3877 if (ixgbe_check_reset_blocked(hw))
3878 return IXGBE_SUCCESS;
3880 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3881 if (status != IXGBE_SUCCESS)
3884 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3886 if (status != IXGBE_SUCCESS)
3889 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3890 * disabled, then force link down by entering low power mode.
3892 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3893 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3894 return ixgbe_set_copper_phy_power(hw, FALSE);
3897 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3899 if (status != IXGBE_SUCCESS)
3902 /* If no valid LCD link speed, then force link down and exit. */
3903 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3904 return ixgbe_set_copper_phy_power(hw, FALSE);
3906 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3907 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3910 if (status != IXGBE_SUCCESS)
3913 /* If no link now, speed is invalid so take link down */
3914 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3915 if (status != IXGBE_SUCCESS)
3916 return ixgbe_set_copper_phy_power(hw, false);
3918 /* clear everything but the speed bits */
3919 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3921 /* If current speed is already LCD, then exit. */
3922 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3923 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3924 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3925 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3928 /* Clear AN completed indication */
3929 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3930 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3933 if (status != IXGBE_SUCCESS)
3936 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3937 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3940 if (status != IXGBE_SUCCESS)
3943 status = hw->phy.ops.read_reg(hw,
3944 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3945 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3948 if (status != IXGBE_SUCCESS)
3951 save_autoneg = hw->phy.autoneg_advertised;
3953 /* Setup link at least common link speed */
3954 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3956 /* restore autoneg from before setting lplu speed */
3957 hw->phy.autoneg_advertised = save_autoneg;
3963 * ixgbe_get_lcd_x550em - Determine lowest common denominator
3964 * @hw: pointer to hardware structure
3965 * @lcd_speed: pointer to lowest common link speed
3967 * Determine lowest common link speed with link partner.
3969 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3973 u16 word = hw->eeprom.ctrl_word_3;
3975 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3977 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3978 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3981 if (status != IXGBE_SUCCESS)
3984 /* If link partner advertised 1G, return 1G */
3985 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3986 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3990 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3991 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3992 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3995 /* Link partner not capable of lower speeds, return 10G */
3996 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
4001 * ixgbe_setup_fc_X550em - Set up flow control
4002 * @hw: pointer to hardware structure
4004 * Called at init time to set up flow control.
4006 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
4008 s32 ret_val = IXGBE_SUCCESS;
4009 u32 pause, asm_dir, reg_val;
4011 DEBUGFUNC("ixgbe_setup_fc_X550em");
4013 /* Validate the requested mode */
4014 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4015 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4016 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4017 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4021 /* 10gig parts do not have a word in the EEPROM to determine the
4022 * default flow control setting, so we explicitly set it to full.
4024 if (hw->fc.requested_mode == ixgbe_fc_default)
4025 hw->fc.requested_mode = ixgbe_fc_full;
4027 /* Determine PAUSE and ASM_DIR bits. */
4028 switch (hw->fc.requested_mode) {
4033 case ixgbe_fc_tx_pause:
4037 case ixgbe_fc_rx_pause:
4038 /* Rx Flow control is enabled and Tx Flow control is
4039 * disabled by software override. Since there really
4040 * isn't a way to advertise that we are capable of RX
4041 * Pause ONLY, we will advertise that we support both
4042 * symmetric and asymmetric Rx PAUSE, as such we fall
4043 * through to the fc_full statement. Later, we will
4044 * disable the adapter's ability to send PAUSE frames.
4051 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4052 "Flow control param set incorrectly\n");
4053 ret_val = IXGBE_ERR_CONFIG;
4057 switch (hw->device_id) {
4058 case IXGBE_DEV_ID_X550EM_X_KR:
4059 case IXGBE_DEV_ID_X550EM_A_KR:
4060 case IXGBE_DEV_ID_X550EM_A_KR_L:
4061 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
4062 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4063 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
4064 if (ret_val != IXGBE_SUCCESS)
4066 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4067 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4069 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4071 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4072 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
4073 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4074 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
4076 /* This device does not fully support AN. */
4077 hw->fc.disable_fc_autoneg = true;
4088 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
4089 * @hw: pointer to hardware structure
4091 * Enable flow control according to IEEE clause 37.
4093 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
4095 u32 link_s1, lp_an_page_low, an_cntl_1;
4096 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4097 ixgbe_link_speed speed;
4100 /* AN should have completed when the cable was plugged in.
4101 * Look for reasons to bail out. Bail out if:
4102 * - FC autoneg is disabled, or if
4105 if (hw->fc.disable_fc_autoneg) {
4106 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4107 "Flow control autoneg is disabled");
4111 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4113 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4117 /* Check at auto-negotiation has completed */
4118 status = hw->mac.ops.read_iosf_sb_reg(hw,
4119 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4120 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4122 if (status != IXGBE_SUCCESS ||
4123 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4124 DEBUGOUT("Auto-Negotiation did not complete\n");
4125 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4129 /* Read the 10g AN autoc and LP ability registers and resolve
4130 * local flow control settings accordingly
4132 status = hw->mac.ops.read_iosf_sb_reg(hw,
4133 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4134 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4136 if (status != IXGBE_SUCCESS) {
4137 DEBUGOUT("Auto-Negotiation did not complete\n");
4141 status = hw->mac.ops.read_iosf_sb_reg(hw,
4142 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4143 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4145 if (status != IXGBE_SUCCESS) {
4146 DEBUGOUT("Auto-Negotiation did not complete\n");
4150 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4151 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4152 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4153 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4154 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4157 if (status == IXGBE_SUCCESS) {
4158 hw->fc.fc_was_autonegged = true;
4160 hw->fc.fc_was_autonegged = false;
4161 hw->fc.current_mode = hw->fc.requested_mode;
4166 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4167 * @hw: pointer to hardware structure
4170 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4172 hw->fc.fc_was_autonegged = false;
4173 hw->fc.current_mode = hw->fc.requested_mode;
4177 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4178 * @hw: pointer to hardware structure
4180 * Enable flow control according to IEEE clause 37.
4182 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4184 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4185 u16 reg, pcs_an_lp, pcs_an;
4186 ixgbe_link_speed speed;
4189 /* AN should have completed when the cable was plugged in.
4190 * Look for reasons to bail out. Bail out if:
4191 * - FC autoneg is disabled, or if
4194 if (hw->fc.disable_fc_autoneg) {
4195 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4196 "Flow control autoneg is disabled");
4200 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4202 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4206 /* Check if auto-negotiation has completed */
4207 status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_STATUS,
4208 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4209 if (status != IXGBE_SUCCESS ||
4210 (reg & IXGBE_M88E1500_COPPER_STATUS_AN_DONE) == 0) {
4211 DEBUGOUT("Auto-Negotiation did not complete\n");
4212 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4216 /* Get the advertized flow control */
4217 status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4218 IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an);
4219 if (status != IXGBE_SUCCESS)
4222 /* Get link partner's flow control */
4223 status = hw->phy.ops.read_reg(hw,
4224 IXGBE_M88E1500_COPPER_AN_LP_ABILITY,
4225 IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an_lp);
4226 if (status != IXGBE_SUCCESS)
4229 /* Negotiate the flow control */
4230 status = ixgbe_negotiate_fc(hw, (u32)pcs_an, (u32)pcs_an_lp,
4231 IXGBE_M88E1500_COPPER_AN_PAUSE,
4232 IXGBE_M88E1500_COPPER_AN_AS_PAUSE,
4233 IXGBE_M88E1500_COPPER_AN_LP_PAUSE,
4234 IXGBE_M88E1500_COPPER_AN_LP_AS_PAUSE);
4237 if (status == IXGBE_SUCCESS) {
4238 hw->fc.fc_was_autonegged = true;
4240 hw->fc.fc_was_autonegged = false;
4241 hw->fc.current_mode = hw->fc.requested_mode;
4246 * ixgbe_setup_fc_sgmii_x550em_a - Set up flow control
4247 * @hw: pointer to hardware structure
4249 * Called at init time to set up flow control.
4251 s32 ixgbe_setup_fc_sgmii_x550em_a(struct ixgbe_hw *hw)
4256 /* Validate the requested mode */
4257 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4258 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4259 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4260 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4263 if (hw->fc.requested_mode == ixgbe_fc_default)
4264 hw->fc.requested_mode = ixgbe_fc_full;
4266 /* Read contents of the Auto-Negotiation register, page 0 reg 4 */
4267 rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4268 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4272 /* Disable all the settings related to Flow control Auto-negotiation */
4273 reg &= ~IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4274 reg &= ~IXGBE_M88E1500_COPPER_AN_PAUSE;
4276 /* Configure the Asymmetric and symmetric pause according to the user
4279 switch (hw->fc.requested_mode) {
4281 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4282 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4284 case ixgbe_fc_rx_pause:
4285 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4286 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4288 case ixgbe_fc_tx_pause:
4289 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4295 /* Write back to the Auto-Negotiation register with newly configured
4298 hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_AN,
4299 IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4301 /* In this section of the code we restart Auto-negotiation */
4303 /* Read the CONTROL register, Page 0 reg 0 */
4304 rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4305 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4309 /* Set the bit to restart Auto-Neg. The bit to enable Auto-neg is ON
4312 reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
4314 /* write the new values to the register to restart Auto-Negotiation */
4315 hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4316 IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4323 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4324 * @hw: pointer to hardware structure
4326 * Called at init time to set up flow control.
4328 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4330 s32 status = IXGBE_SUCCESS;
4333 DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4335 /* Validate the requested mode */
4336 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4337 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4338 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4339 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4342 if (hw->fc.requested_mode == ixgbe_fc_default)
4343 hw->fc.requested_mode = ixgbe_fc_full;
4345 /* Set up the 1G and 10G flow control advertisement registers so the
4346 * HW will be able to do FC autoneg once the cable is plugged in. If
4347 * we link at 10G, the 1G advertisement is harmless and vice versa.
4349 status = hw->mac.ops.read_iosf_sb_reg(hw,
4350 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4351 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4353 if (status != IXGBE_SUCCESS) {
4354 DEBUGOUT("Auto-Negotiation did not complete\n");
4358 /* The possible values of fc.requested_mode are:
4359 * 0: Flow control is completely disabled
4360 * 1: Rx flow control is enabled (we can receive pause frames,
4361 * but not send pause frames).
4362 * 2: Tx flow control is enabled (we can send pause frames but
4363 * we do not support receiving pause frames).
4364 * 3: Both Rx and Tx flow control (symmetric) are enabled.
4367 switch (hw->fc.requested_mode) {
4369 /* Flow control completely disabled by software override. */
4370 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4371 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4373 case ixgbe_fc_tx_pause:
4374 /* Tx Flow control is enabled, and Rx Flow control is
4375 * disabled by software override.
4377 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4378 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4380 case ixgbe_fc_rx_pause:
4381 /* Rx Flow control is enabled and Tx Flow control is
4382 * disabled by software override. Since there really
4383 * isn't a way to advertise that we are capable of RX
4384 * Pause ONLY, we will advertise that we support both
4385 * symmetric and asymmetric Rx PAUSE, as such we fall
4386 * through to the fc_full statement. Later, we will
4387 * disable the adapter's ability to send PAUSE frames.
4390 /* Flow control (both Rx and Tx) is enabled by SW override. */
4391 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4392 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4395 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4396 "Flow control param set incorrectly\n");
4397 return IXGBE_ERR_CONFIG;
4400 status = hw->mac.ops.write_iosf_sb_reg(hw,
4401 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4402 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4404 /* Restart auto-negotiation. */
4405 status = ixgbe_restart_an_internal_phy_x550em(hw);
4411 * ixgbe_set_mux - Set mux for port 1 access with CS4227
4412 * @hw: pointer to hardware structure
4413 * @state: set mux if 1, clear if 0
4415 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4419 if (!hw->bus.lan_id)
4421 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4423 esdp |= IXGBE_ESDP_SDP1;
4425 esdp &= ~IXGBE_ESDP_SDP1;
4426 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4427 IXGBE_WRITE_FLUSH(hw);
4431 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4432 * @hw: pointer to hardware structure
4433 * @mask: Mask to specify which semaphore to acquire
4435 * Acquires the SWFW semaphore and sets the I2C MUX
4437 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4441 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4443 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4447 if (mask & IXGBE_GSSR_I2C_MASK)
4448 ixgbe_set_mux(hw, 1);
4450 return IXGBE_SUCCESS;
4454 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4455 * @hw: pointer to hardware structure
4456 * @mask: Mask to specify which semaphore to release
4458 * Releases the SWFW semaphore and sets the I2C MUX
4460 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4462 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4464 if (mask & IXGBE_GSSR_I2C_MASK)
4465 ixgbe_set_mux(hw, 0);
4467 ixgbe_release_swfw_sync_X540(hw, mask);
4471 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4472 * @hw: pointer to hardware structure
4473 * @mask: Mask to specify which semaphore to acquire
4475 * Acquires the SWFW semaphore and get the shared phy token as needed
4477 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4479 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4480 int retries = FW_PHY_TOKEN_RETRIES;
4481 s32 status = IXGBE_SUCCESS;
4483 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4486 status = IXGBE_SUCCESS;
4488 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4491 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4492 return IXGBE_SUCCESS;
4494 status = ixgbe_get_phy_token(hw);
4495 if (status == IXGBE_SUCCESS)
4496 return IXGBE_SUCCESS;
4499 ixgbe_release_swfw_sync_X540(hw, hmask);
4500 if (status != IXGBE_ERR_TOKEN_RETRY)
4508 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4509 * @hw: pointer to hardware structure
4510 * @mask: Mask to specify which semaphore to release
4512 * Releases the SWFW semaphore and puts the shared phy token as needed
4514 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4516 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4518 DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4520 if (mask & IXGBE_GSSR_TOKEN_SM)
4521 ixgbe_put_phy_token(hw);
4524 ixgbe_release_swfw_sync_X540(hw, hmask);
4528 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
4529 * @hw: pointer to hardware structure
4530 * @reg_addr: 32 bit address of PHY register to read
4531 * @phy_data: Pointer to read data from PHY register
4533 * Reads a value from a specified PHY register using the SWFW lock and PHY
4534 * Token. The PHY Token is needed since the MDIO is shared between to MAC
4537 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4538 u32 device_type, u16 *phy_data)
4541 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4543 DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4545 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4546 return IXGBE_ERR_SWFW_SYNC;
4548 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4550 hw->mac.ops.release_swfw_sync(hw, mask);
4556 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
4557 * @hw: pointer to hardware structure
4558 * @reg_addr: 32 bit PHY register to write
4559 * @device_type: 5 bit device type
4560 * @phy_data: Data to write to the PHY register
4562 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
4563 * The PHY Token is needed since the MDIO is shared between to MAC instances.
4565 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4566 u32 device_type, u16 phy_data)
4569 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4571 DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4573 if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4574 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4576 hw->mac.ops.release_swfw_sync(hw, mask);
4578 status = IXGBE_ERR_SWFW_SYNC;
4585 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4586 * @hw: pointer to hardware structure
4588 * Handle external Base T PHY interrupt. If high temperature
4589 * failure alarm then return error, else if link status change
4590 * then setup internal/external PHY link
4592 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4593 * failure alarm, else return PHY access status.
4595 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4600 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4602 if (status != IXGBE_SUCCESS)
4606 return ixgbe_setup_internal_phy(hw);
4608 return IXGBE_SUCCESS;
4612 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4613 * @hw: pointer to hardware structure
4614 * @speed: new link speed
4615 * @autoneg_wait_to_complete: true when waiting for completion is needed
4617 * Setup internal/external PHY link speed based on link speed, then set
4618 * external PHY auto advertised link speed.
4620 * Returns error status for any failure
4622 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4623 ixgbe_link_speed speed,
4624 bool autoneg_wait_to_complete)
4627 ixgbe_link_speed force_speed;
4629 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4631 /* Setup internal/external PHY link speed to iXFI (10G), unless
4632 * only 1G is auto advertised then setup KX link.
4634 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4635 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4637 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4639 /* If internal link mode is XFI, then setup XFI internal link. */
4640 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4641 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4643 if (status != IXGBE_SUCCESS)
4647 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4651 * ixgbe_check_link_t_X550em - Determine link and speed status
4652 * @hw: pointer to hardware structure
4653 * @speed: pointer to link speed
4654 * @link_up: true when link is up
4655 * @link_up_wait_to_complete: bool used to wait for link up or not
4657 * Check that both the MAC and X557 external PHY have link.
4659 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4660 bool *link_up, bool link_up_wait_to_complete)
4665 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4666 return IXGBE_ERR_CONFIG;
4668 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4669 link_up_wait_to_complete);
4671 /* If check link fails or MAC link is not up, then return */
4672 if (status != IXGBE_SUCCESS || !(*link_up))
4675 /* MAC link is up, so check external PHY link.
4676 * Read this twice back to back to indicate current status.
4678 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4679 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4682 if (status != IXGBE_SUCCESS)
4685 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4686 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4689 if (status != IXGBE_SUCCESS)
4692 /* If external PHY link is not up, then indicate link not up */
4693 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4696 return IXGBE_SUCCESS;
4700 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4701 * @hw: pointer to hardware structure
4703 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4707 status = ixgbe_reset_phy_generic(hw);
4709 if (status != IXGBE_SUCCESS)
4712 /* Configure Link Status Alarm and Temperature Threshold interrupts */
4713 return ixgbe_enable_lasi_ext_t_x550em(hw);
4717 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4718 * @hw: pointer to hardware structure
4719 * @led_idx: led number to turn on
4721 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4725 DEBUGFUNC("ixgbe_led_on_t_X550em");
4727 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4728 return IXGBE_ERR_PARAM;
4730 /* To turn on the LED, set mode to ON. */
4731 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4732 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4733 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4734 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4735 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4737 return IXGBE_SUCCESS;
4741 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4742 * @hw: pointer to hardware structure
4743 * @led_idx: led number to turn off
4745 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4749 DEBUGFUNC("ixgbe_led_off_t_X550em");
4751 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4752 return IXGBE_ERR_PARAM;
4754 /* To turn on the LED, set mode to ON. */
4755 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4756 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4757 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4758 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4759 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4761 return IXGBE_SUCCESS;