drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44
  45 /**
  46  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  47  *  @hw: pointer to hardware structure
  48  *
  49  *  Initialize the function pointers and assign the MAC type for X550.
  50  *  Does not touch the hardware.
  51  **/
  52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  53 {
  54         struct ixgbe_mac_info *mac = &hw->mac;
  55         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  56         s32 ret_val;
  57
  58         DEBUGFUNC("ixgbe_init_ops_X550");
  59
  60         ret_val = ixgbe_init_ops_X540(hw);
  61         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  62         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  63         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  64         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  65         mac->ops.set_source_address_pruning =
  66                         ixgbe_set_source_address_pruning_X550;
  67         mac->ops.set_ethertype_anti_spoofing =
  68                         ixgbe_set_ethertype_anti_spoofing_X550;
  69
  70         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  71         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  72         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  73         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  74         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  75         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  76         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  77         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  78         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  79
  80         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  81         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  82         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  83         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  84         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  85         switch (hw->device_id) {
  86         case IXGBE_DEV_ID_X550EM_X_10G_T:
  87         case IXGBE_DEV_ID_X550EM_A_10G_T:
  88                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  89                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  90                 break;
  91         default:
  92                 break;
  93         }
  94         return ret_val;
  95 }
  96
  97 /**
  98  * ixgbe_read_cs4227 - Read CS4227 register
  99  * @hw: pointer to hardware structure
 100  * @reg: register number to write
 101  * @value: pointer to receive value read
 102  *
 103  * Returns status code
 104  **/
 105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 106 {
 107         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 108 }
 109
 110 /**
 111  * ixgbe_write_cs4227 - Write CS4227 register
 112  * @hw: pointer to hardware structure
 113  * @reg: register number to write
 114  * @value: value to write to register
 115  *
 116  * Returns status code
 117  **/
 118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 119 {
 120         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 121 }
 122
 123 /**
 124  * ixgbe_read_pe - Read register from port expander
 125  * @hw: pointer to hardware structure
 126  * @reg: register number to read
 127  * @value: pointer to receive read value
 128  *
 129  * Returns status code
 130  **/
 131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 132 {
 133         s32 status;
 134
 135         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 136         if (status != IXGBE_SUCCESS)
 137                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 138                               "port expander access failed with %d\n", status);
 139         return status;
 140 }
 141
 142 /**
 143  * ixgbe_write_pe - Write register to port expander
 144  * @hw: pointer to hardware structure
 145  * @reg: register number to write
 146  * @value: value to write
 147  *
 148  * Returns status code
 149  **/
 150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 151 {
 152         s32 status;
 153
 154         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 155         if (status != IXGBE_SUCCESS)
 156                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 157                               "port expander access failed with %d\n", status);
 158         return status;
 159 }
 160
 161 /**
 162  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 163  * @hw: pointer to hardware structure
 164  *
 165  * This function assumes that the caller has acquired the proper semaphore.
 166  * Returns error code
 167  **/
 168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 169 {
 170         s32 status;
 171         u32 retry;
 172         u16 value;
 173         u8 reg;
 174
 175         /* Trigger hard reset. */
 176         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 177         if (status != IXGBE_SUCCESS)
 178                 return status;
 179         reg |= IXGBE_PE_BIT1;
 180         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 181         if (status != IXGBE_SUCCESS)
 182                 return status;
 183
 184         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 185         if (status != IXGBE_SUCCESS)
 186                 return status;
 187         reg &= ~IXGBE_PE_BIT1;
 188         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 189         if (status != IXGBE_SUCCESS)
 190                 return status;
 191
 192         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 193         if (status != IXGBE_SUCCESS)
 194                 return status;
 195         reg &= ~IXGBE_PE_BIT1;
 196         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199
 200         usec_delay(IXGBE_CS4227_RESET_HOLD);
 201
 202         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 203         if (status != IXGBE_SUCCESS)
 204                 return status;
 205         reg |= IXGBE_PE_BIT1;
 206         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 207         if (status != IXGBE_SUCCESS)
 208                 return status;
 209
 210         /* Wait for the reset to complete. */
 211         msec_delay(IXGBE_CS4227_RESET_DELAY);
 212         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 213                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 214                                            &value);
 215                 if (status == IXGBE_SUCCESS &&
 216                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 217                         break;
 218                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 219         }
 220         if (retry == IXGBE_CS4227_RETRIES) {
 221                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 222                         "CS4227 reset did not complete.");
 223                 return IXGBE_ERR_PHY;
 224         }
 225
 226         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 227         if (status != IXGBE_SUCCESS ||
 228             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 229                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 230                         "CS4227 EEPROM did not load successfully.");
 231                 return IXGBE_ERR_PHY;
 232         }
 233
 234         return IXGBE_SUCCESS;
 235 }
 236
 237 /**
 238  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 239  * @hw: pointer to hardware structure
 240  **/
 241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 242 {
 243         s32 status = IXGBE_SUCCESS;
 244         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 245         u16 value = 0;
 246         u8 retry;
 247
 248         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 249                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 250                 if (status != IXGBE_SUCCESS) {
 251                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 252                                 "semaphore failed with %d", status);
 253                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 254                         continue;
 255                 }
 256
 257                 /* Get status of reset flow. */
 258                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 259
 260                 if (status == IXGBE_SUCCESS &&
 261                     value == IXGBE_CS4227_RESET_COMPLETE)
 262                         goto out;
 263
 264                 if (status != IXGBE_SUCCESS ||
 265                     value != IXGBE_CS4227_RESET_PENDING)
 266                         break;
 267
 268                 /* Reset is pending. Wait and check again. */
 269                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 270                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 271         }
 272
 273         /* If still pending, assume other instance failed. */
 274         if (retry == IXGBE_CS4227_RETRIES) {
 275                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 276                 if (status != IXGBE_SUCCESS) {
 277                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 278                                       "semaphore failed with %d", status);
 279                         return;
 280                 }
 281         }
 282
 283         /* Reset the CS4227. */
 284         status = ixgbe_reset_cs4227(hw);
 285         if (status != IXGBE_SUCCESS) {
 286                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 287                         "CS4227 reset failed: %d", status);
 288                 goto out;
 289         }
 290
 291         /* Reset takes so long, temporarily release semaphore in case the
 292          * other driver instance is waiting for the reset indication.
 293          */
 294         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 295                            IXGBE_CS4227_RESET_PENDING);
 296         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 297         msec_delay(10);
 298         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 299         if (status != IXGBE_SUCCESS) {
 300                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 301                         "semaphore failed with %d", status);
 302                 return;
 303         }
 304
 305         /* Record completion for next time. */
 306         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 307                 IXGBE_CS4227_RESET_COMPLETE);
 308
 309 out:
 310         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 311         msec_delay(hw->eeprom.semaphore_delay);
 312 }
 313
 314 /**
 315  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 316  * @hw: pointer to hardware structure
 317  **/
 318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 319 {
 320         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 321
 322         if (hw->bus.lan_id) {
 323                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 324                 esdp |= IXGBE_ESDP_SDP1_DIR;
 325         }
 326         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 327         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 328         IXGBE_WRITE_FLUSH(hw);
 329 }
 330
 331 /**
 332  * ixgbe_identify_phy_1g - Get 1g PHY type based on device id
 333  * @hw: pointer to hardware structure
 334  *
 335  * Returns error code
 336  */
 337 static s32 ixgbe_identify_phy_1g(struct ixgbe_hw *hw)
 338 {
 339         u16 phy_id_high;
 340         u16 phy_id_low;
 341         u32 val = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
 342
 343         hw->phy.addr = (val >> 3) & 0x1F;
 344         val = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 345                                    hw->phy.addr, &phy_id_high);
 346         if (val || phy_id_high == 0xFFFF) {
 347                 hw->phy.type = ixgbe_phy_sgmii;
 348                 return 0;
 349         }
 350
 351         val = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 352                                    hw->phy.addr, &phy_id_low);
 353         if (val)
 354                 return val;
 355
 356         hw->phy.id = (u32)phy_id_high << 16;
 357         hw->phy.id |= phy_id_low & IXGBE_PHY_REVISION_MASK;
 358         hw->phy.revision = (u32)phy_id_low & ~IXGBE_PHY_REVISION_MASK;
 359         hw->phy.type = ixgbe_phy_m88;
 360
 361         return 0;
 362 }
 363
 364 /**
 365  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 366  * @hw: pointer to hardware structure
 367  *
 368  * Returns error code
 369  */
 370 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 371 {
 372         switch (hw->device_id) {
 373         case IXGBE_DEV_ID_X550EM_A_SFP:
 374                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_TOKEN_SM;
 375                 if (hw->bus.lan_id)
 376                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 377                 else
 378                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 379                 return ixgbe_identify_module_generic(hw);
 380         case IXGBE_DEV_ID_X550EM_X_SFP:
 381                 /* set up for CS4227 usage */
 382                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 383                 ixgbe_setup_mux_ctl(hw);
 384                 ixgbe_check_cs4227(hw);
 385                 /* Fallthrough */
 386
 387         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 388                 return ixgbe_identify_module_generic(hw);
 389                 break;
 390         case IXGBE_DEV_ID_X550EM_X_KX4:
 391                 hw->phy.type = ixgbe_phy_x550em_kx4;
 392                 break;
 393         case IXGBE_DEV_ID_X550EM_X_KR:
 394         case IXGBE_DEV_ID_X550EM_A_KR:
 395         case IXGBE_DEV_ID_X550EM_A_KR_L:
 396                 hw->phy.type = ixgbe_phy_x550em_kr;
 397                 break;
 398         case IXGBE_DEV_ID_X550EM_X_1G_T:
 399         case IXGBE_DEV_ID_X550EM_X_10G_T:
 400         case IXGBE_DEV_ID_X550EM_A_10G_T:
 401                 return ixgbe_identify_phy_generic(hw);
 402         case IXGBE_DEV_ID_X550EM_A_1G_T:
 403         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 404                 return ixgbe_identify_phy_1g(hw);
 405         default:
 406                 break;
 407         }
 408         return IXGBE_SUCCESS;
 409 }
 410
 411 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 412                                      u32 device_type, u16 *phy_data)
 413 {
 414         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 415         return IXGBE_NOT_IMPLEMENTED;
 416 }
 417
 418 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 419                                       u32 device_type, u16 phy_data)
 420 {
 421         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 422         return IXGBE_NOT_IMPLEMENTED;
 423 }
 424
 425 /**
 426  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 427  * @hw: pointer to the hardware structure
 428  * @addr: I2C bus address to read from
 429  * @reg: I2C device register to read from
 430  * @val: pointer to location to receive read value
 431  *
 432  * Returns an error code on error.
 433  **/
 434 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 435                                            u16 reg, u16 *val)
 436 {
 437         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 438 }
 439
 440 /**
 441  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 442  * @hw: pointer to the hardware structure
 443  * @addr: I2C bus address to read from
 444  * @reg: I2C device register to read from
 445  * @val: pointer to location to receive read value
 446  *
 447  * Returns an error code on error.
 448  **/
 449 static s32
 450 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 451                                          u16 reg, u16 *val)
 452 {
 453         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 454 }
 455
 456 /**
 457  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 458  * @hw: pointer to the hardware structure
 459  * @addr: I2C bus address to write to
 460  * @reg: I2C device register to write to
 461  * @val: value to write
 462  *
 463  * Returns an error code on error.
 464  **/
 465 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 466                                             u8 addr, u16 reg, u16 val)
 467 {
 468         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 469 }
 470
 471 /**
 472  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 473  * @hw: pointer to the hardware structure
 474  * @addr: I2C bus address to write to
 475  * @reg: I2C device register to write to
 476  * @val: value to write
 477  *
 478  * Returns an error code on error.
 479  **/
 480 static s32
 481 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 482                                           u8 addr, u16 reg, u16 val)
 483 {
 484         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 485 }
 486
 487 /**
 488 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 489 *  @hw: pointer to hardware structure
 490 *
 491 *  Initialize the function pointers and for MAC type X550EM.
 492 *  Does not touch the hardware.
 493 **/
 494 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 495 {
 496         struct ixgbe_mac_info *mac = &hw->mac;
 497         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 498         struct ixgbe_phy_info *phy = &hw->phy;
 499         struct ixgbe_link_info *link = &hw->link;
 500         s32 ret_val;
 501
 502         DEBUGFUNC("ixgbe_init_ops_X550EM");
 503
 504         /* Similar to X550 so start there. */
 505         ret_val = ixgbe_init_ops_X550(hw);
 506
 507         /* Since this function eventually calls
 508          * ixgbe_init_ops_540 by design, we are setting
 509          * the pointers to NULL explicitly here to overwrite
 510          * the values being set in the x540 function.
 511          */
 512         /* Thermal sensor not supported in x550EM */
 513         mac->ops.get_thermal_sensor_data = NULL;
 514         mac->ops.init_thermal_sensor_thresh = NULL;
 515         mac->thermal_sensor_enabled = false;
 516
 517         /* FCOE not supported in x550EM */
 518         mac->ops.get_san_mac_addr = NULL;
 519         mac->ops.set_san_mac_addr = NULL;
 520         mac->ops.get_wwn_prefix = NULL;
 521         mac->ops.get_fcoe_boot_status = NULL;
 522
 523         /* IPsec not supported in x550EM */
 524         mac->ops.disable_sec_rx_path = NULL;
 525         mac->ops.enable_sec_rx_path = NULL;
 526
 527         /* AUTOC register is not present in x550EM. */
 528         mac->ops.prot_autoc_read = NULL;
 529         mac->ops.prot_autoc_write = NULL;
 530
 531         /* X550EM bus type is internal*/
 532         hw->bus.type = ixgbe_bus_type_internal;
 533         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 534
 535         if (hw->mac.type == ixgbe_mac_X550EM_x) {
 536                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 537                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 538                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 539                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 540                 link->ops.read_link = ixgbe_read_i2c_combined_generic;
 541                 link->ops.read_link_unlocked =
 542                                 ixgbe_read_i2c_combined_generic_unlocked;
 543                 link->ops.write_link = ixgbe_write_i2c_combined_generic;
 544                 link->ops.write_link_unlocked =
 545                                 ixgbe_write_i2c_combined_generic_unlocked;
 546                 link->addr = IXGBE_CS4227;
 547         }
 548         if (hw->mac.type == ixgbe_mac_X550EM_a) {
 549                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 550                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 551                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 552                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 553         }
 554
 555         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 556         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 557         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 558         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 559         mac->ops.get_supported_physical_layer =
 560                                     ixgbe_get_supported_physical_layer_X550em;
 561
 562         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 563                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 564         else
 565                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 566
 567
 568         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
 569                 mac->ops.setup_eee = NULL;
 570
 571         /* PHY */
 572         phy->ops.init = ixgbe_init_phy_ops_X550em;
 573         phy->ops.identify = ixgbe_identify_phy_x550em;
 574         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 575                 phy->ops.set_phy_power = NULL;
 576
 577
 578         /* EEPROM */
 579         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 580         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 581         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 582         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 583         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 584         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 585         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 586         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 587
 588         return ret_val;
 589 }
 590
 591 /**
 592  *  ixgbe_dmac_config_X550
 593  *  @hw: pointer to hardware structure
 594  *
 595  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 596  *  When disabling dmac, dmac enable dmac bit is cleared.
 597  **/
 598 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 599 {
 600         u32 reg, high_pri_tc;
 601
 602         DEBUGFUNC("ixgbe_dmac_config_X550");
 603
 604         /* Disable DMA coalescing before configuring */
 605         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 606         reg &= ~IXGBE_DMACR_DMAC_EN;
 607         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 608
 609         /* Disable DMA Coalescing if the watchdog timer is 0 */
 610         if (!hw->mac.dmac_config.watchdog_timer)
 611                 goto out;
 612
 613         ixgbe_dmac_config_tcs_X550(hw);
 614
 615         /* Configure DMA Coalescing Control Register */
 616         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 617
 618         /* Set the watchdog timer in units of 40.96 usec */
 619         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 620         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 621
 622         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 623         /* If fcoe is enabled, set high priority traffic class */
 624         if (hw->mac.dmac_config.fcoe_en) {
 625                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 626                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 627                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 628         }
 629         reg |= IXGBE_DMACR_EN_MNG_IND;
 630
 631         /* Enable DMA coalescing after configuration */
 632         reg |= IXGBE_DMACR_DMAC_EN;
 633         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 634
 635 out:
 636         return IXGBE_SUCCESS;
 637 }
 638
 639 /**
 640  *  ixgbe_dmac_config_tcs_X550
 641  *  @hw: pointer to hardware structure
 642  *
 643  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 644  *  be cleared before configuring.
 645  **/
 646 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 647 {
 648         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 649
 650         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 651
 652         /* Configure DMA coalescing enabled */
 653         switch (hw->mac.dmac_config.link_speed) {
 654         case IXGBE_LINK_SPEED_100_FULL:
 655                 pb_headroom = IXGBE_DMACRXT_100M;
 656                 break;
 657         case IXGBE_LINK_SPEED_1GB_FULL:
 658                 pb_headroom = IXGBE_DMACRXT_1G;
 659                 break;
 660         default:
 661                 pb_headroom = IXGBE_DMACRXT_10G;
 662                 break;
 663         }
 664
 665         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 666                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 667
 668         /* Set the per Rx packet buffer receive threshold */
 669         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 670                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 671                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 672
 673                 if (tc < hw->mac.dmac_config.num_tcs) {
 674                         /* Get Rx PB size */
 675                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 676                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 677                                 IXGBE_RXPBSIZE_SHIFT;
 678
 679                         /* Calculate receive buffer threshold in kilobytes */
 680                         if (rx_pb_size > pb_headroom)
 681                                 rx_pb_size = rx_pb_size - pb_headroom;
 682                         else
 683                                 rx_pb_size = 0;
 684
 685                         /* Minimum of MFS shall be set for DMCTH */
 686                         reg |= (rx_pb_size > maxframe_size_kb) ?
 687                                 rx_pb_size : maxframe_size_kb;
 688                 }
 689                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 690         }
 691         return IXGBE_SUCCESS;
 692 }
 693
 694 /**
 695  *  ixgbe_dmac_update_tcs_X550
 696  *  @hw: pointer to hardware structure
 697  *
 698  *  Disables dmac, updates per TC settings, and then enables dmac.
 699  **/
 700 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 701 {
 702         u32 reg;
 703
 704         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 705
 706         /* Disable DMA coalescing before configuring */
 707         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 708         reg &= ~IXGBE_DMACR_DMAC_EN;
 709         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 710
 711         ixgbe_dmac_config_tcs_X550(hw);
 712
 713         /* Enable DMA coalescing after configuration */
 714         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 715         reg |= IXGBE_DMACR_DMAC_EN;
 716         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 717
 718         return IXGBE_SUCCESS;
 719 }
 720
 721 /**
 722  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 723  *  @hw: pointer to hardware structure
 724  *
 725  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 726  *  ixgbe_hw struct in order to set up EEPROM access.
 727  **/
 728 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 729 {
 730         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 731         u32 eec;
 732         u16 eeprom_size;
 733
 734         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 735
 736         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 737                 eeprom->semaphore_delay = 10;
 738                 eeprom->type = ixgbe_flash;
 739
 740                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 741                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 742                                     IXGBE_EEC_SIZE_SHIFT);
 743                 eeprom->word_size = 1 << (eeprom_size +
 744                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 745
 746                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 747                           eeprom->type, eeprom->word_size);
 748         }
 749
 750         return IXGBE_SUCCESS;
 751 }
 752
 753 /**
 754  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 755  *  @hw: pointer to the HW structure
 756  *  @enable_eee: boolean flag to enable EEE
 757  *
 758  *  Enable/disable EEE based on enable_eee flag.
 759  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 760  *  are modified.
 761  *
 762  **/
 763 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 764 {
 765         u32 eeer;
 766         u16 autoneg_eee_reg;
 767         u32 link_reg;
 768         s32 status;
 769
 770         DEBUGFUNC("ixgbe_setup_eee_X550");
 771
 772         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 773         /* Enable or disable EEE per flag */
 774         if (enable_eee) {
 775                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 776
 777                 if (hw->mac.type == ixgbe_mac_X550) {
 778                         /* Advertise EEE capability */
 779                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 780                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 781
 782                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 783                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 784                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 785
 786                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 787                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 788                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 789                         /* Not supported on first revision of X550EM_x. */
 790                         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
 791                             !(IXGBE_FUSES0_REV_MASK &
 792                               IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
 793                                 return IXGBE_SUCCESS;
 794
 795                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 796                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 797                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 798                         if (status != IXGBE_SUCCESS)
 799                                 return status;
 800
 801                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 802                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 803
 804                         /* Don't advertise FEC capability when EEE enabled. */
 805                         link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 806
 807                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 808                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 809                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 810                         if (status != IXGBE_SUCCESS)
 811                                 return status;
 812                 }
 813         } else {
 814                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 815
 816                 if (hw->mac.type == ixgbe_mac_X550) {
 817                         /* Disable advertised EEE capability */
 818                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 819                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 820
 821                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 822                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 823                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 824
 825                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 826                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 827                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 828                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 829                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 830                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 831                         if (status != IXGBE_SUCCESS)
 832                                 return status;
 833
 834                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 835                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 836
 837                         /* Advertise FEC capability when EEE is disabled. */
 838                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 839
 840                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 841                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 842                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 843                         if (status != IXGBE_SUCCESS)
 844                                 return status;
 845                 }
 846         }
 847         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 848
 849         return IXGBE_SUCCESS;
 850 }
 851
 852 /**
 853  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 854  * @hw: pointer to hardware structure
 855  * @enable: enable or disable source address pruning
 856  * @pool: Rx pool to set source address pruning for
 857  **/
 858 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 859                                            unsigned int pool)
 860 {
 861         u64 pfflp;
 862
 863         /* max rx pool is 63 */
 864         if (pool > 63)
 865                 return;
 866
 867         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 868         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 869
 870         if (enable)
 871                 pfflp |= (1ULL << pool);
 872         else
 873                 pfflp &= ~(1ULL << pool);
 874
 875         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 876         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 877 }
 878
 879 /**
 880  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 881  *  @hw: pointer to hardware structure
 882  *  @enable: enable or disable switch for Ethertype anti-spoofing
 883  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 884  *
 885  **/
 886 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 887                 bool enable, int vf)
 888 {
 889         int vf_target_reg = vf >> 3;
 890         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 891         u32 pfvfspoof;
 892
 893         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 894
 895         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 896         if (enable)
 897                 pfvfspoof |= (1 << vf_target_shift);
 898         else
 899                 pfvfspoof &= ~(1 << vf_target_shift);
 900
 901         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 902 }
 903
 904 /**
 905  * ixgbe_iosf_wait - Wait for IOSF command completion
 906  * @hw: pointer to hardware structure
 907  * @ctrl: pointer to location to receive final IOSF control value
 908  *
 909  * Returns failing status on timeout
 910  *
 911  * Note: ctrl can be NULL if the IOSF control register value is not needed
 912  **/
 913 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 914 {
 915         u32 i, command = 0;
 916
 917         /* Check every 10 usec to see if the address cycle completed.
 918          * The SB IOSF BUSY bit will clear when the operation is
 919          * complete
 920          */
 921         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 922                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 923                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 924                         break;
 925                 usec_delay(10);
 926         }
 927         if (ctrl)
 928                 *ctrl = command;
 929         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 930                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
 931                 return IXGBE_ERR_PHY;
 932         }
 933
 934         return IXGBE_SUCCESS;
 935 }
 936
 937 /**
 938  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 939  *  device
 940  *  @hw: pointer to hardware structure
 941  *  @reg_addr: 32 bit PHY register to write
 942  *  @device_type: 3 bit device type
 943  *  @data: Data to write to the register
 944  **/
 945 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 946                             u32 device_type, u32 data)
 947 {
 948         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 949         u32 command, error;
 950         s32 ret;
 951
 952         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 953         if (ret != IXGBE_SUCCESS)
 954                 return ret;
 955
 956         ret = ixgbe_iosf_wait(hw, NULL);
 957         if (ret != IXGBE_SUCCESS)
 958                 goto out;
 959
 960         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 961                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 962
 963         /* Write IOSF control register */
 964         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 965
 966         /* Write IOSF data register */
 967         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 968
 969         ret = ixgbe_iosf_wait(hw, &command);
 970
 971         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 972                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 973                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 974                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 975                               "Failed to write, error %x\n", error);
 976                 ret = IXGBE_ERR_PHY;
 977         }
 978
 979 out:
 980         ixgbe_release_swfw_semaphore(hw, gssr);
 981         return ret;
 982 }
 983
 984 /**
 985  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 986  *  device
 987  *  @hw: pointer to hardware structure
 988  *  @reg_addr: 32 bit PHY register to write
 989  *  @device_type: 3 bit device type
 990  *  @phy_data: Pointer to read data from the register
 991  **/
 992 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 993                            u32 device_type, u32 *data)
 994 {
 995         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 996         u32 command, error;
 997         s32 ret;
 998
 999         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1000         if (ret != IXGBE_SUCCESS)
1001                 return ret;
1002
1003         ret = ixgbe_iosf_wait(hw, NULL);
1004         if (ret != IXGBE_SUCCESS)
1005                 goto out;
1006
1007         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1008                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1009
1010         /* Write IOSF control register */
1011         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1012
1013         ret = ixgbe_iosf_wait(hw, &command);
1014
1015         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1016                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1017                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1018                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1019                                 "Failed to read, error %x\n", error);
1020                 ret = IXGBE_ERR_PHY;
1021         }
1022
1023         if (ret == IXGBE_SUCCESS)
1024                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1025
1026 out:
1027         ixgbe_release_swfw_semaphore(hw, gssr);
1028         return ret;
1029 }
1030
1031 /**
1032  * ixgbe_get_phy_token - Get the token for shared phy access
1033  * @hw: Pointer to hardware structure
1034  */
1035
1036 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1037 {
1038         struct ixgbe_hic_phy_token_req token_cmd;
1039         s32 status;
1040
1041         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1042         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1043         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1044         token_cmd.port_number = hw->bus.lan_id;
1045         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1046         token_cmd.pad = 0;
1047         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1048                                               sizeof(token_cmd),
1049                                               IXGBE_HI_COMMAND_TIMEOUT,
1050                                               true);
1051         if (status)
1052                 return status;
1053         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1054                 return IXGBE_SUCCESS;
1055         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1056                 return IXGBE_ERR_FW_RESP_INVALID;
1057
1058         return IXGBE_ERR_TOKEN_RETRY;
1059 }
1060
1061 /**
1062  * ixgbe_put_phy_token - Put the token for shared phy access
1063  * @hw: Pointer to hardware structure
1064  */
1065
1066 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1067 {
1068         struct ixgbe_hic_phy_token_req token_cmd;
1069         s32 status;
1070
1071         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1072         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1073         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1074         token_cmd.port_number = hw->bus.lan_id;
1075         token_cmd.command_type = FW_PHY_TOKEN_REL;
1076         token_cmd.pad = 0;
1077         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1078                                               sizeof(token_cmd),
1079                                               IXGBE_HI_COMMAND_TIMEOUT,
1080                                               true);
1081         if (status)
1082                 return status;
1083         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1084                 return IXGBE_SUCCESS;
1085         return IXGBE_ERR_FW_RESP_INVALID;
1086 }
1087
1088 /**
1089  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1090  *  of the IOSF device
1091  *  @hw: pointer to hardware structure
1092  *  @reg_addr: 32 bit PHY register to write
1093  *  @device_type: 3 bit device type
1094  *  @data: Data to write to the register
1095  **/
1096 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1097         u32 device_type, u32 data)
1098 {
1099         struct ixgbe_hic_internal_phy_req write_cmd;
1100         s32 status;
1101         UNREFERENCED_1PARAMETER(device_type);
1102
1103         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1104         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1105         write_cmd.port_number = hw->bus.lan_id;
1106         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1107         write_cmd.address = (u16)reg_addr;
1108         write_cmd.rsv1 = 0;
1109         write_cmd.write_data = data;
1110         write_cmd.pad = 0;
1111
1112         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1113                 sizeof(write_cmd), IXGBE_HI_COMMAND_TIMEOUT, false);
1114
1115         return status;
1116 }
1117
1118 /**
1119  *  ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
1120  *  of the IOSF device.
1121  *  @hw: pointer to hardware structure
1122  *  @reg_addr: 32 bit PHY register to write
1123  *  @device_type: 3 bit device type
1124  *  @data: Pointer to read data from the register
1125  **/
1126 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1127         u32 device_type, u32 *data)
1128 {
1129         struct ixgbe_hic_internal_phy_req read_cmd;
1130         s32 status;
1131         UNREFERENCED_1PARAMETER(device_type);
1132
1133         read_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1134         read_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1135         read_cmd.port_number = hw->bus.lan_id;
1136         read_cmd.command_type = FW_INT_PHY_REQ_READ;
1137         read_cmd.address = (u16)reg_addr;
1138         read_cmd.rsv1 = 0;
1139         read_cmd.write_data = 0;
1140         read_cmd.pad = 0;
1141
1142         status = ixgbe_host_interface_command(hw, (u32 *)&read_cmd,
1143                 sizeof(read_cmd), IXGBE_HI_COMMAND_TIMEOUT, true);
1144
1145         /* Extract the register value from the response. */
1146         *data = ((struct ixgbe_hic_internal_phy_resp *)&read_cmd)->read_data;
1147
1148         return status;
1149 }
1150
1151 /**
1152  *  ixgbe_disable_mdd_X550
1153  *  @hw: pointer to hardware structure
1154  *
1155  *  Disable malicious driver detection
1156  **/
1157 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1158 {
1159         u32 reg;
1160
1161         DEBUGFUNC("ixgbe_disable_mdd_X550");
1162
1163         /* Disable MDD for TX DMA and interrupt */
1164         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1165         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1166         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1167
1168         /* Disable MDD for RX and interrupt */
1169         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1170         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1171         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1172 }
1173
1174 /**
1175  *  ixgbe_enable_mdd_X550
1176  *  @hw: pointer to hardware structure
1177  *
1178  *  Enable malicious driver detection
1179  **/
1180 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1181 {
1182         u32 reg;
1183
1184         DEBUGFUNC("ixgbe_enable_mdd_X550");
1185
1186         /* Enable MDD for TX DMA and interrupt */
1187         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1188         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1189         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1190
1191         /* Enable MDD for RX and interrupt */
1192         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1193         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1194         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1195 }
1196
1197 /**
1198  *  ixgbe_restore_mdd_vf_X550
1199  *  @hw: pointer to hardware structure
1200  *  @vf: vf index
1201  *
1202  *  Restore VF that was disabled during malicious driver detection event
1203  **/
1204 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1205 {
1206         u32 idx, reg, num_qs, start_q, bitmask;
1207
1208         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1209
1210         /* Map VF to queues */
1211         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1212         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1213         case IXGBE_MRQC_VMDQRT8TCEN:
1214                 num_qs = 8;  /* 16 VFs / pools */
1215                 bitmask = 0x000000FF;
1216                 break;
1217         case IXGBE_MRQC_VMDQRSS32EN:
1218         case IXGBE_MRQC_VMDQRT4TCEN:
1219                 num_qs = 4;  /* 32 VFs / pools */
1220                 bitmask = 0x0000000F;
1221                 break;
1222         default:            /* 64 VFs / pools */
1223                 num_qs = 2;
1224                 bitmask = 0x00000003;
1225                 break;
1226         }
1227         start_q = vf * num_qs;
1228
1229         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1230         idx = start_q / 32;
1231         reg = 0;
1232         reg |= (bitmask << (start_q % 32));
1233         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1234         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1235 }
1236
1237 /**
1238  *  ixgbe_mdd_event_X550
1239  *  @hw: pointer to hardware structure
1240  *  @vf_bitmap: vf bitmap of malicious vfs
1241  *
1242  *  Handle malicious driver detection event.
1243  **/
1244 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1245 {
1246         u32 wqbr;
1247         u32 i, j, reg, q, shift, vf, idx;
1248
1249         DEBUGFUNC("ixgbe_mdd_event_X550");
1250
1251         /* figure out pool size for mapping to vf's */
1252         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1253         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1254         case IXGBE_MRQC_VMDQRT8TCEN:
1255                 shift = 3;  /* 16 VFs / pools */
1256                 break;
1257         case IXGBE_MRQC_VMDQRSS32EN:
1258         case IXGBE_MRQC_VMDQRT4TCEN:
1259                 shift = 2;  /* 32 VFs / pools */
1260                 break;
1261         default:
1262                 shift = 1;  /* 64 VFs / pools */
1263                 break;
1264         }
1265
1266         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1267         for (i = 0; i < 4; i++) {
1268                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1269                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1270
1271                 if (!wqbr)
1272                         continue;
1273
1274                 /* Get malicious queue */
1275                 for (j = 0; j < 32 && wqbr; j++) {
1276
1277                         if (!(wqbr & (1 << j)))
1278                                 continue;
1279
1280                         /* Get queue from bitmask */
1281                         q = j + (i * 32);
1282
1283                         /* Map queue to vf */
1284                         vf = (q >> shift);
1285
1286                         /* Set vf bit in vf_bitmap */
1287                         idx = vf / 32;
1288                         vf_bitmap[idx] |= (1 << (vf % 32));
1289                         wqbr &= ~(1 << j);
1290                 }
1291         }
1292 }
1293
1294 /**
1295  *  ixgbe_get_media_type_X550em - Get media type
1296  *  @hw: pointer to hardware structure
1297  *
1298  *  Returns the media type (fiber, copper, backplane)
1299  */
1300 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1301 {
1302         enum ixgbe_media_type media_type;
1303
1304         DEBUGFUNC("ixgbe_get_media_type_X550em");
1305
1306         /* Detect if there is a copper PHY attached. */
1307         switch (hw->device_id) {
1308         case IXGBE_DEV_ID_X550EM_X_KR:
1309         case IXGBE_DEV_ID_X550EM_X_KX4:
1310         case IXGBE_DEV_ID_X550EM_A_KR:
1311         case IXGBE_DEV_ID_X550EM_A_KR_L:
1312                 media_type = ixgbe_media_type_backplane;
1313                 break;
1314         case IXGBE_DEV_ID_X550EM_X_SFP:
1315         case IXGBE_DEV_ID_X550EM_A_SFP:
1316         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1317         case IXGBE_DEV_ID_X550EM_A_QSFP:
1318         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1319                 media_type = ixgbe_media_type_fiber;
1320                 break;
1321         case IXGBE_DEV_ID_X550EM_X_1G_T:
1322         case IXGBE_DEV_ID_X550EM_X_10G_T:
1323         case IXGBE_DEV_ID_X550EM_A_10G_T:
1324                 media_type = ixgbe_media_type_copper;
1325                 break;
1326         case IXGBE_DEV_ID_X550EM_A_1G_T:
1327         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1328                 media_type = ixgbe_media_type_sgmii;
1329                 hw->phy.type = ixgbe_phy_sgmii;
1330                 break;
1331         default:
1332                 media_type = ixgbe_media_type_unknown;
1333                 break;
1334         }
1335         return media_type;
1336 }
1337
1338 /**
1339  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1340  *  @hw: pointer to hardware structure
1341  *  @linear: true if SFP module is linear
1342  */
1343 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1344 {
1345         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1346
1347         switch (hw->phy.sfp_type) {
1348         case ixgbe_sfp_type_not_present:
1349                 return IXGBE_ERR_SFP_NOT_PRESENT;
1350         case ixgbe_sfp_type_da_cu_core0:
1351         case ixgbe_sfp_type_da_cu_core1:
1352                 *linear = true;
1353                 break;
1354         case ixgbe_sfp_type_srlr_core0:
1355         case ixgbe_sfp_type_srlr_core1:
1356         case ixgbe_sfp_type_da_act_lmt_core0:
1357         case ixgbe_sfp_type_da_act_lmt_core1:
1358         case ixgbe_sfp_type_1g_sx_core0:
1359         case ixgbe_sfp_type_1g_sx_core1:
1360         case ixgbe_sfp_type_1g_lx_core0:
1361         case ixgbe_sfp_type_1g_lx_core1:
1362                 *linear = false;
1363                 break;
1364         case ixgbe_sfp_type_unknown:
1365         case ixgbe_sfp_type_1g_cu_core0:
1366         case ixgbe_sfp_type_1g_cu_core1:
1367         default:
1368                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1369         }
1370
1371         return IXGBE_SUCCESS;
1372 }
1373
1374 /**
1375  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1376  *  @hw: pointer to hardware structure
1377  *
1378  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1379  **/
1380 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1381 {
1382         s32 status;
1383         bool linear;
1384
1385         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1386
1387         status = ixgbe_identify_module_generic(hw);
1388
1389         if (status != IXGBE_SUCCESS)
1390                 return status;
1391
1392         /* Check if SFP module is supported */
1393         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1394
1395         return status;
1396 }
1397
1398 /**
1399  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1400  *  @hw: pointer to hardware structure
1401  */
1402 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1403 {
1404         s32 status;
1405         bool linear;
1406
1407         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1408
1409         /* Check if SFP module is supported */
1410         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1411
1412         if (status != IXGBE_SUCCESS)
1413                 return status;
1414
1415         ixgbe_init_mac_link_ops_X550em(hw);
1416         hw->phy.ops.reset = NULL;
1417
1418         return IXGBE_SUCCESS;
1419 }
1420
1421 /**
1422  * ixgbe_setup_sgmii - Set up link for sgmii
1423  * @hw: pointer to hardware structure
1424  */
1425 static s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1426                              bool autoneg_wait_to_complete)
1427 {
1428         struct ixgbe_mac_info *mac = &hw->mac;
1429         u32 lval, sval;
1430         s32 rc;
1431         UNREFERENCED_2PARAMETER(speed, autoneg_wait_to_complete);
1432
1433         rc = mac->ops.read_iosf_sb_reg(hw,
1434                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1435                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1436         if (rc)
1437                 return rc;
1438
1439         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1440         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1441         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1442         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1443         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1444         rc = mac->ops.write_iosf_sb_reg(hw,
1445                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1446                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1447         if (rc)
1448                 return rc;
1449
1450         rc = mac->ops.read_iosf_sb_reg(hw,
1451                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1452                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1453         if (rc)
1454                 return rc;
1455
1456         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1457         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1458         rc = mac->ops.write_iosf_sb_reg(hw,
1459                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1460                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1461         if (rc)
1462                 return rc;
1463
1464         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1465         rc = mac->ops.write_iosf_sb_reg(hw,
1466                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1467                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1468
1469         return rc;
1470 }
1471
1472 /**
1473  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1474  *  @hw: pointer to hardware structure
1475  */
1476 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1477 {
1478         struct ixgbe_mac_info *mac = &hw->mac;
1479
1480         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1481
1482         switch (hw->mac.ops.get_media_type(hw)) {
1483         case ixgbe_media_type_fiber:
1484                 /* CS4227 does not support autoneg, so disable the laser control
1485                  * functions for SFP+ fiber
1486                  */
1487                 mac->ops.disable_tx_laser = NULL;
1488                 mac->ops.enable_tx_laser = NULL;
1489                 mac->ops.flap_tx_laser = NULL;
1490                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1491                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1492                 mac->ops.set_rate_select_speed =
1493                                         ixgbe_set_soft_rate_select_speed;
1494                 break;
1495         case ixgbe_media_type_copper:
1496                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1497                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1498                 break;
1499         case ixgbe_media_type_backplane:
1500                 break;
1501         case ixgbe_media_type_sgmii:
1502                 mac->ops.setup_link = ixgbe_setup_sgmii;
1503                 break;
1504         default:
1505                 break;
1506         }
1507 }
1508
1509 /**
1510  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1511  *  @hw: pointer to hardware structure
1512  *  @speed: pointer to link speed
1513  *  @autoneg: true when autoneg or autotry is enabled
1514  */
1515 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1516                                        ixgbe_link_speed *speed,
1517                                        bool *autoneg)
1518 {
1519         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1520
1521         /* SFP */
1522         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1523
1524                 /* CS4227 SFP must not enable auto-negotiation */
1525                 *autoneg = false;
1526
1527                 /* Check if 1G SFP module. */
1528                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1529                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1530                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1531                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1532                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1533                         return IXGBE_SUCCESS;
1534                 }
1535
1536                 /* Link capabilities are based on SFP */
1537                 if (hw->phy.multispeed_fiber)
1538                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1539                                  IXGBE_LINK_SPEED_1GB_FULL;
1540                 else
1541                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1542         } else {
1543                 switch (hw->phy.type) {
1544                 case ixgbe_phy_m88:
1545                         *speed = IXGBE_LINK_SPEED_100_FULL |
1546                                  IXGBE_LINK_SPEED_1GB_FULL;
1547                         break;
1548                 case ixgbe_phy_sgmii:
1549                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1550                         break;
1551                 default:
1552                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1553                                  IXGBE_LINK_SPEED_1GB_FULL;
1554                         break;
1555                 }
1556                 *autoneg = true;
1557         }
1558
1559         return IXGBE_SUCCESS;
1560 }
1561
1562 /**
1563  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1564  * @hw: pointer to hardware structure
1565  * @lsc: pointer to boolean flag which indicates whether external Base T
1566  *       PHY interrupt is lsc
1567  *
1568  * Determime if external Base T PHY interrupt cause is high temperature
1569  * failure alarm or link status change.
1570  *
1571  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1572  * failure alarm, else return PHY access status.
1573  */
1574 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1575 {
1576         u32 status;
1577         u16 reg;
1578
1579         *lsc = false;
1580
1581         /* Vendor alarm triggered */
1582         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1583                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1584                                       &reg);
1585
1586         if (status != IXGBE_SUCCESS ||
1587             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1588                 return status;
1589
1590         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1591         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1592                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1593                                       &reg);
1594
1595         if (status != IXGBE_SUCCESS ||
1596             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1597             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1598                 return status;
1599
1600         /* Global alarm triggered */
1601         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1602                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1603                                       &reg);
1604
1605         if (status != IXGBE_SUCCESS)
1606                 return status;
1607
1608         /* If high temperature failure, then return over temp error and exit */
1609         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1610                 /* power down the PHY in case the PHY FW didn't already */
1611                 ixgbe_set_copper_phy_power(hw, false);
1612                 return IXGBE_ERR_OVERTEMP;
1613         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1614                 /*  device fault alarm triggered */
1615                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1616                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1617                                           &reg);
1618
1619                 if (status != IXGBE_SUCCESS)
1620                         return status;
1621
1622                 /* if device fault was due to high temp alarm handle and exit */
1623                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1624                         /* power down the PHY in case the PHY FW didn't */
1625                         ixgbe_set_copper_phy_power(hw, false);
1626                         return IXGBE_ERR_OVERTEMP;
1627                 }
1628         }
1629
1630         /* Vendor alarm 2 triggered */
1631         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1632                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1633
1634         if (status != IXGBE_SUCCESS ||
1635             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1636                 return status;
1637
1638         /* link connect/disconnect event occurred */
1639         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1640                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1641
1642         if (status != IXGBE_SUCCESS)
1643                 return status;
1644
1645         /* Indicate LSC */
1646         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1647                 *lsc = true;
1648
1649         return IXGBE_SUCCESS;
1650 }
1651
1652 /**
1653  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1654  * @hw: pointer to hardware structure
1655  *
1656  * Enable link status change and temperature failure alarm for the external
1657  * Base T PHY
1658  *
1659  * Returns PHY access status
1660  */
1661 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1662 {
1663         u32 status;
1664         u16 reg;
1665         bool lsc;
1666
1667         /* Clear interrupt flags */
1668         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1669
1670         /* Enable link status change alarm */
1671         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1672                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1673
1674         if (status != IXGBE_SUCCESS)
1675                 return status;
1676
1677         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1678
1679         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1680                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1681
1682         if (status != IXGBE_SUCCESS)
1683                 return status;
1684
1685         /* Enable high temperature failure and global fault alarms */
1686         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1687                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1688                                       &reg);
1689
1690         if (status != IXGBE_SUCCESS)
1691                 return status;
1692
1693         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1694                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1695
1696         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1697                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1698                                        reg);
1699
1700         if (status != IXGBE_SUCCESS)
1701                 return status;
1702
1703         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1704         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1705                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1706                                       &reg);
1707
1708         if (status != IXGBE_SUCCESS)
1709                 return status;
1710
1711         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1712                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1713
1714         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1715                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1716                                        reg);
1717
1718         if (status != IXGBE_SUCCESS)
1719                 return status;
1720
1721         /* Enable chip-wide vendor alarm */
1722         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1723                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1724                                       &reg);
1725
1726         if (status != IXGBE_SUCCESS)
1727                 return status;
1728
1729         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1730
1731         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1732                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1733                                        reg);
1734
1735         return status;
1736 }
1737
1738 /**
1739  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1740  *  @hw: pointer to hardware structure
1741  *  @speed: link speed
1742  *
1743  *  Configures the integrated KR PHY.
1744  **/
1745 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1746                                        ixgbe_link_speed speed)
1747 {
1748         s32 status;
1749         u32 reg_val;
1750
1751         status = ixgbe_read_iosf_sb_reg_x550(hw,
1752                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1753                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1754         if (status)
1755                 return status;
1756
1757         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1758         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1759                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1760
1761         /* Advertise 10G support. */
1762         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1763                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1764
1765         /* Advertise 1G support. */
1766         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1767                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1768
1769         /* Restart auto-negotiation. */
1770         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1771         status = ixgbe_write_iosf_sb_reg_x550(hw,
1772                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1773                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1774
1775         return status;
1776 }
1777
1778 /**
1779  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1780  *  @hw: pointer to hardware structure
1781  *
1782  *  Initialize any function pointers that were not able to be
1783  *  set during init_shared_code because the PHY/SFP type was
1784  *  not known.  Perform the SFP init if necessary.
1785  */
1786 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1787 {
1788         struct ixgbe_phy_info *phy = &hw->phy;
1789         s32 ret_val;
1790
1791         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1792
1793         hw->mac.ops.set_lan_id(hw);
1794
1795         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1796                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1797                 ixgbe_setup_mux_ctl(hw);
1798
1799                 /* Save NW management interface connected on board. This is used
1800                  * to determine internal PHY mode.
1801                  */
1802                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1803                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1804         }
1805
1806         /* Identify the PHY or SFP module */
1807         ret_val = phy->ops.identify(hw);
1808         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1809                 return ret_val;
1810
1811         /* Setup function pointers based on detected hardware */
1812         ixgbe_init_mac_link_ops_X550em(hw);
1813         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1814                 phy->ops.reset = NULL;
1815
1816         /* Set functions pointers based on phy type */
1817         switch (hw->phy.type) {
1818         case ixgbe_phy_x550em_kx4:
1819                 phy->ops.setup_link = NULL;
1820                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1821                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1822                 break;
1823         case ixgbe_phy_x550em_kr:
1824                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1825                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1826                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1827                 break;
1828         case ixgbe_phy_x550em_ext_t:
1829                 /* Save NW management interface connected on board. This is used
1830                  * to determine internal PHY mode
1831                  */
1832                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1833
1834                 /* If internal link mode is XFI, then setup iXFI internal link,
1835                  * else setup KR now.
1836                  */
1837                 phy->ops.setup_internal_link =
1838                                               ixgbe_setup_internal_phy_t_x550em;
1839
1840                 /* setup SW LPLU only for first revision of X550EM_x */
1841                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1842                     !(IXGBE_FUSES0_REV_MASK &
1843                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1844                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1845
1846                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1847                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1848                 break;
1849         case ixgbe_phy_sgmii:
1850                 phy->ops.setup_link = NULL;
1851                 break;
1852         case ixgbe_phy_m88:
1853                 break;
1854         default:
1855                 break;
1856         }
1857         return ret_val;
1858 }
1859
1860 /**
1861  * ixgbe_set_mdio_speed - Set MDIO clock speed
1862  *  @hw: pointer to hardware structure
1863  */
1864 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
1865 {
1866         u32 hlreg0;
1867
1868         switch (hw->device_id) {
1869         case IXGBE_DEV_ID_X550EM_X_10G_T:
1870         case IXGBE_DEV_ID_X550EM_A_1G_T:
1871         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1872         case IXGBE_DEV_ID_X550EM_A_10G_T:
1873         case IXGBE_DEV_ID_X550EM_A_SFP:
1874         case IXGBE_DEV_ID_X550EM_A_QSFP:
1875                 /* Config MDIO clock speed before the first MDIO PHY access */
1876                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1877                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1878                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1879                 break;
1880         default:
1881                 break;
1882         }
1883 }
1884
1885 /**
1886  *  ixgbe_reset_hw_X550em - Perform hardware reset
1887  *  @hw: pointer to hardware structure
1888  *
1889  *  Resets the hardware by resetting the transmit and receive units, masks
1890  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1891  *  reset.
1892  */
1893 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1894 {
1895         ixgbe_link_speed link_speed;
1896         s32 status;
1897         u32 ctrl = 0;
1898         u32 i;
1899         bool link_up = false;
1900
1901         DEBUGFUNC("ixgbe_reset_hw_X550em");
1902
1903         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1904         status = hw->mac.ops.stop_adapter(hw);
1905         if (status != IXGBE_SUCCESS)
1906                 return status;
1907
1908         /* flush pending Tx transactions */
1909         ixgbe_clear_tx_pending(hw);
1910
1911         ixgbe_set_mdio_speed(hw);
1912
1913         /* PHY ops must be identified and initialized prior to reset */
1914         status = hw->phy.ops.init(hw);
1915
1916         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1917                 return status;
1918
1919         /* start the external PHY */
1920         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1921                 status = ixgbe_init_ext_t_x550em(hw);
1922                 if (status)
1923                         return status;
1924         }
1925
1926         /* Setup SFP module if there is one present. */
1927         if (hw->phy.sfp_setup_needed) {
1928                 status = hw->mac.ops.setup_sfp(hw);
1929                 hw->phy.sfp_setup_needed = false;
1930         }
1931
1932         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1933                 return status;
1934
1935         /* Reset PHY */
1936         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1937                 hw->phy.ops.reset(hw);
1938
1939 mac_reset_top:
1940         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1941          * If link reset is used when link is up, it might reset the PHY when
1942          * mng is using it.  If link is down or the flag to force full link
1943          * reset is set, then perform link reset.
1944          */
1945         ctrl = IXGBE_CTRL_LNK_RST;
1946         if (!hw->force_full_reset) {
1947                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1948                 if (link_up)
1949                         ctrl = IXGBE_CTRL_RST;
1950         }
1951
1952         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1953         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1954         IXGBE_WRITE_FLUSH(hw);
1955
1956         /* Poll for reset bit to self-clear meaning reset is complete */
1957         for (i = 0; i < 10; i++) {
1958                 usec_delay(1);
1959                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1960                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1961                         break;
1962         }
1963
1964         if (ctrl & IXGBE_CTRL_RST_MASK) {
1965                 status = IXGBE_ERR_RESET_FAILED;
1966                 DEBUGOUT("Reset polling failed to complete.\n");
1967         }
1968
1969         msec_delay(50);
1970
1971         /* Double resets are required for recovery from certain error
1972          * conditions.  Between resets, it is necessary to stall to
1973          * allow time for any pending HW events to complete.
1974          */
1975         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1976                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1977                 goto mac_reset_top;
1978         }
1979
1980         /* Store the permanent mac address */
1981         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1982
1983         /* Store MAC address from RAR0, clear receive address registers, and
1984          * clear the multicast table.  Also reset num_rar_entries to 128,
1985          * since we modify this value when programming the SAN MAC address.
1986          */
1987         hw->mac.num_rar_entries = 128;
1988         hw->mac.ops.init_rx_addrs(hw);
1989
1990         ixgbe_set_mdio_speed(hw);
1991
1992         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1993                 ixgbe_setup_mux_ctl(hw);
1994
1995         return status;
1996 }
1997
1998 /**
1999  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2000  * @hw: pointer to hardware structure
2001  */
2002 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2003 {
2004         u32 status;
2005         u16 reg;
2006
2007         status = hw->phy.ops.read_reg(hw,
2008                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2009                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2010                                       &reg);
2011
2012         if (status != IXGBE_SUCCESS)
2013                 return status;
2014
2015         /* If PHY FW reset completed bit is set then this is the first
2016          * SW instance after a power on so the PHY FW must be un-stalled.
2017          */
2018         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2019                 status = hw->phy.ops.read_reg(hw,
2020                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2021                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2022                                         &reg);
2023
2024                 if (status != IXGBE_SUCCESS)
2025                         return status;
2026
2027                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2028
2029                 status = hw->phy.ops.write_reg(hw,
2030                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2031                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2032                                         reg);
2033
2034                 if (status != IXGBE_SUCCESS)
2035                         return status;
2036         }
2037
2038         return status;
2039 }
2040
2041 /**
2042  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2043  *  @hw: pointer to hardware structure
2044  *
2045  *  Configures the integrated KR PHY.
2046  **/
2047 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2048 {
2049         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2050 }
2051
2052 /**
2053  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2054  *  @hw: pointer to hardware structure
2055  *
2056  *  Configure the external PHY and the integrated KR PHY for SFP support.
2057  **/
2058 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2059                                     ixgbe_link_speed speed,
2060                                     bool autoneg_wait_to_complete)
2061 {
2062         s32 ret_val;
2063         u16 reg_slice, reg_val;
2064         bool setup_linear = false;
2065         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2066
2067         /* Check if SFP module is supported and linear */
2068         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2069
2070         /* If no SFP module present, then return success. Return success since
2071          * there is no reason to configure CS4227 and SFP not present error is
2072          * not excepted in the setup MAC link flow.
2073          */
2074         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2075                 return IXGBE_SUCCESS;
2076
2077         if (ret_val != IXGBE_SUCCESS)
2078                 return ret_val;
2079
2080         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2081                 /* Configure CS4227 LINE side to 10G SR. */
2082                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2083                             (hw->bus.lan_id << 12);
2084                 reg_val = IXGBE_CS4227_SPEED_10G;
2085                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2086                                                   reg_val);
2087
2088                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2089                             (hw->bus.lan_id << 12);
2090                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2091                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2092                                                   reg_val);
2093
2094                 /* Configure CS4227 for HOST connection rate then type. */
2095                 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2096                             (hw->bus.lan_id << 12);
2097                 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2098                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2099                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2100                                                   reg_val);
2101
2102                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2103                             (hw->bus.lan_id << 12);
2104                 if (setup_linear)
2105                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2106                 else
2107                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2108                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2109                                                   reg_val);
2110
2111                 /* Setup XFI internal link. */
2112                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2113         } else {
2114                 /* Configure internal PHY for KR/KX. */
2115                 ixgbe_setup_kr_speed_x550em(hw, speed);
2116
2117                 /* Configure CS4227 LINE side to proper mode. */
2118                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2119                             (hw->bus.lan_id << 12);
2120                 if (setup_linear)
2121                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2122                 else
2123                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2124                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2125                                                   reg_val);
2126         }
2127         return ret_val;
2128 }
2129
2130 /**
2131  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2132  *  @hw: pointer to hardware structure
2133  *
2134  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2135  **/
2136 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2137 {
2138         s32 status;
2139         u32 reg_val;
2140
2141         /* Disable training protocol FSM. */
2142         status = ixgbe_read_iosf_sb_reg_x550(hw,
2143                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2144                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2145         if (status != IXGBE_SUCCESS)
2146                 return status;
2147         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2148         status = ixgbe_write_iosf_sb_reg_x550(hw,
2149                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2150                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2151         if (status != IXGBE_SUCCESS)
2152                 return status;
2153
2154         /* Disable Flex from training TXFFE. */
2155         status = ixgbe_read_iosf_sb_reg_x550(hw,
2156                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2157                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2158         if (status != IXGBE_SUCCESS)
2159                 return status;
2160         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2161         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2162         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2163         status = ixgbe_write_iosf_sb_reg_x550(hw,
2164                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2165                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2166         if (status != IXGBE_SUCCESS)
2167                 return status;
2168         status = ixgbe_read_iosf_sb_reg_x550(hw,
2169                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2170                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2171         if (status != IXGBE_SUCCESS)
2172                 return status;
2173         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2174         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2175         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2176         status = ixgbe_write_iosf_sb_reg_x550(hw,
2177                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2178                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2179         if (status != IXGBE_SUCCESS)
2180                 return status;
2181
2182         /* Enable override for coefficients. */
2183         status = ixgbe_read_iosf_sb_reg_x550(hw,
2184                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2185                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2186         if (status != IXGBE_SUCCESS)
2187                 return status;
2188         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2189         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2190         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2191         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2192         status = ixgbe_write_iosf_sb_reg_x550(hw,
2193                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2194                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2195         return status;
2196 }
2197
2198 /**
2199  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2200  *  @hw: pointer to hardware structure
2201  *  @speed: the link speed to force
2202  *
2203  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2204  *  internal and external PHY at a specific speed, without autonegotiation.
2205  **/
2206 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2207 {
2208         s32 status;
2209         u32 reg_val;
2210
2211         /* Disable AN and force speed to 10G Serial. */
2212         status = ixgbe_read_iosf_sb_reg_x550(hw,
2213                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2214                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2215         if (status != IXGBE_SUCCESS)
2216                 return status;
2217
2218         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2219         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2220
2221         /* Select forced link speed for internal PHY. */
2222         switch (*speed) {
2223         case IXGBE_LINK_SPEED_10GB_FULL:
2224                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2225                 break;
2226         case IXGBE_LINK_SPEED_1GB_FULL:
2227                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2228                 break;
2229         default:
2230                 /* Other link speeds are not supported by internal KR PHY. */
2231                 return IXGBE_ERR_LINK_SETUP;
2232         }
2233
2234         status = ixgbe_write_iosf_sb_reg_x550(hw,
2235                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2236                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2237         if (status != IXGBE_SUCCESS)
2238                 return status;
2239
2240         /* Additional configuration needed for x550em_x */
2241         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2242                 status = ixgbe_setup_ixfi_x550em_x(hw);
2243                 if (status != IXGBE_SUCCESS)
2244                         return status;
2245         }
2246
2247         /* Toggle port SW reset by AN reset. */
2248         status = ixgbe_read_iosf_sb_reg_x550(hw,
2249                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2250                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2251         if (status != IXGBE_SUCCESS)
2252                 return status;
2253         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2254         status = ixgbe_write_iosf_sb_reg_x550(hw,
2255                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2256                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2257
2258         return status;
2259 }
2260
2261 /**
2262  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2263  * @hw: address of hardware structure
2264  * @link_up: address of boolean to indicate link status
2265  *
2266  * Returns error code if unable to get link status.
2267  */
2268 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2269 {
2270         u32 ret;
2271         u16 autoneg_status;
2272
2273         *link_up = false;
2274
2275         /* read this twice back to back to indicate current status */
2276         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2277                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2278                                    &autoneg_status);
2279         if (ret != IXGBE_SUCCESS)
2280                 return ret;
2281
2282         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2283                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2284                                    &autoneg_status);
2285         if (ret != IXGBE_SUCCESS)
2286                 return ret;
2287
2288         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2289
2290         return IXGBE_SUCCESS;
2291 }
2292
2293 /**
2294  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2295  * @hw: point to hardware structure
2296  *
2297  * Configures the link between the integrated KR PHY and the external X557 PHY
2298  * The driver will call this function when it gets a link status change
2299  * interrupt from the X557 PHY. This function configures the link speed
2300  * between the PHYs to match the link speed of the BASE-T link.
2301  *
2302  * A return of a non-zero value indicates an error, and the base driver should
2303  * not report link up.
2304  */
2305 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2306 {
2307         ixgbe_link_speed force_speed;
2308         bool link_up;
2309         u32 status;
2310         u16 speed;
2311
2312         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2313                 return IXGBE_ERR_CONFIG;
2314
2315         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2316                 /* If link is down, there is no setup necessary so return  */
2317                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2318                 if (status != IXGBE_SUCCESS)
2319                         return status;
2320
2321                 if (!link_up)
2322                         return IXGBE_SUCCESS;
2323
2324                 status = hw->phy.ops.read_reg(hw,
2325                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2326                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2327                                               &speed);
2328                 if (status != IXGBE_SUCCESS)
2329                         return status;
2330
2331                 /* If link is still down - no setup is required so return */
2332                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2333                 if (status != IXGBE_SUCCESS)
2334                         return status;
2335                 if (!link_up)
2336                         return IXGBE_SUCCESS;
2337
2338                 /* clear everything but the speed and duplex bits */
2339                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2340
2341                 switch (speed) {
2342                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2343                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2344                         break;
2345                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2346                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2347                         break;
2348                 default:
2349                         /* Internal PHY does not support anything else */
2350                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
2351                 }
2352
2353                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2354         } else {
2355                 speed = IXGBE_LINK_SPEED_10GB_FULL |
2356                         IXGBE_LINK_SPEED_1GB_FULL;
2357                 return ixgbe_setup_kr_speed_x550em(hw, speed);
2358         }
2359 }
2360
2361 /**
2362  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2363  *  @hw: pointer to hardware structure
2364  *
2365  *  Configures the integrated KR PHY to use internal loopback mode.
2366  **/
2367 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2368 {
2369         s32 status;
2370         u32 reg_val;
2371
2372         /* Disable AN and force speed to 10G Serial. */
2373         status = ixgbe_read_iosf_sb_reg_x550(hw,
2374                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2375                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2376         if (status != IXGBE_SUCCESS)
2377                 return status;
2378         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2379         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2380         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2381         status = ixgbe_write_iosf_sb_reg_x550(hw,
2382                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2383                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2384         if (status != IXGBE_SUCCESS)
2385                 return status;
2386
2387         /* Set near-end loopback clocks. */
2388         status = ixgbe_read_iosf_sb_reg_x550(hw,
2389                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2390                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2391         if (status != IXGBE_SUCCESS)
2392                 return status;
2393         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2394         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2395         status = ixgbe_write_iosf_sb_reg_x550(hw,
2396                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2397                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2398         if (status != IXGBE_SUCCESS)
2399                 return status;
2400
2401         /* Set loopback enable. */
2402         status = ixgbe_read_iosf_sb_reg_x550(hw,
2403                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2404                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2405         if (status != IXGBE_SUCCESS)
2406                 return status;
2407         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2408         status = ixgbe_write_iosf_sb_reg_x550(hw,
2409                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2410                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2411         if (status != IXGBE_SUCCESS)
2412                 return status;
2413
2414         /* Training bypass. */
2415         status = ixgbe_read_iosf_sb_reg_x550(hw,
2416                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2417                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2418         if (status != IXGBE_SUCCESS)
2419                 return status;
2420         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2421         status = ixgbe_write_iosf_sb_reg_x550(hw,
2422                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2423                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2424
2425         return status;
2426 }
2427
2428 /**
2429  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2430  *  assuming that the semaphore is already obtained.
2431  *  @hw: pointer to hardware structure
2432  *  @offset: offset of  word in the EEPROM to read
2433  *  @data: word read from the EEPROM
2434  *
2435  *  Reads a 16 bit word from the EEPROM using the hostif.
2436  **/
2437 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2438                                    u16 *data)
2439 {
2440         s32 status;
2441         struct ixgbe_hic_read_shadow_ram buffer;
2442
2443         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2444         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2445         buffer.hdr.req.buf_lenh = 0;
2446         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2447         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2448
2449         /* convert offset from words to bytes */
2450         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2451         /* one word */
2452         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2453
2454         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2455                                               sizeof(buffer),
2456                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2457
2458         if (status)
2459                 return status;
2460
2461         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2462                                           FW_NVM_DATA_OFFSET);
2463
2464         return 0;
2465 }
2466
2467 /**
2468  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2469  *  @hw: pointer to hardware structure
2470  *  @offset: offset of  word in the EEPROM to read
2471  *  @data: word read from the EEPROM
2472  *
2473  *  Reads a 16 bit word from the EEPROM using the hostif.
2474  **/
2475 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2476                               u16 *data)
2477 {
2478         s32 status = IXGBE_SUCCESS;
2479
2480         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2481
2482         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2483             IXGBE_SUCCESS) {
2484                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2485                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2486         } else {
2487                 status = IXGBE_ERR_SWFW_SYNC;
2488         }
2489
2490         return status;
2491 }
2492
2493 /**
2494  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2495  *  @hw: pointer to hardware structure
2496  *  @offset: offset of  word in the EEPROM to read
2497  *  @words: number of words
2498  *  @data: word(s) read from the EEPROM
2499  *
2500  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
2501  **/
2502 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2503                                      u16 offset, u16 words, u16 *data)
2504 {
2505         struct ixgbe_hic_read_shadow_ram buffer;
2506         u32 current_word = 0;
2507         u16 words_to_read;
2508         s32 status;
2509         u32 i;
2510
2511         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2512
2513         /* Take semaphore for the entire operation. */
2514         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2515         if (status) {
2516                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2517                 return status;
2518         }
2519         while (words) {
2520                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2521                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2522                 else
2523                         words_to_read = words;
2524
2525                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2526                 buffer.hdr.req.buf_lenh = 0;
2527                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2528                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2529
2530                 /* convert offset from words to bytes */
2531                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2532                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2533
2534                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2535                                                       sizeof(buffer),
2536                                                       IXGBE_HI_COMMAND_TIMEOUT,
2537                                                       false);
2538
2539                 if (status) {
2540                         DEBUGOUT("Host interface command failed\n");
2541                         goto out;
2542                 }
2543
2544                 for (i = 0; i < words_to_read; i++) {
2545                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2546                                   2 * i;
2547                         u32 value = IXGBE_READ_REG(hw, reg);
2548
2549                         data[current_word] = (u16)(value & 0xffff);
2550                         current_word++;
2551                         i++;
2552                         if (i < words_to_read) {
2553                                 value >>= 16;
2554                                 data[current_word] = (u16)(value & 0xffff);
2555                                 current_word++;
2556                         }
2557                 }
2558                 words -= words_to_read;
2559         }
2560
2561 out:
2562         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2563         return status;
2564 }
2565
2566 /**
2567  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2568  *  @hw: pointer to hardware structure
2569  *  @offset: offset of  word in the EEPROM to write
2570  *  @data: word write to the EEPROM
2571  *
2572  *  Write a 16 bit word to the EEPROM using the hostif.
2573  **/
2574 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2575                                     u16 data)
2576 {
2577         s32 status;
2578         struct ixgbe_hic_write_shadow_ram buffer;
2579
2580         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2581
2582         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2583         buffer.hdr.req.buf_lenh = 0;
2584         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2585         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2586
2587          /* one word */
2588         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2589         buffer.data = data;
2590         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2591
2592         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2593                                               sizeof(buffer),
2594                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2595
2596         return status;
2597 }
2598
2599 /**
2600  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2601  *  @hw: pointer to hardware structure
2602  *  @offset: offset of  word in the EEPROM to write
2603  *  @data: word write to the EEPROM
2604  *
2605  *  Write a 16 bit word to the EEPROM using the hostif.
2606  **/
2607 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2608                                u16 data)
2609 {
2610         s32 status = IXGBE_SUCCESS;
2611
2612         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2613
2614         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2615             IXGBE_SUCCESS) {
2616                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2617                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2618         } else {
2619                 DEBUGOUT("write ee hostif failed to get semaphore");
2620                 status = IXGBE_ERR_SWFW_SYNC;
2621         }
2622
2623         return status;
2624 }
2625
2626 /**
2627  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2628  *  @hw: pointer to hardware structure
2629  *  @offset: offset of  word in the EEPROM to write
2630  *  @words: number of words
2631  *  @data: word(s) write to the EEPROM
2632  *
2633  *  Write a 16 bit word(s) to the EEPROM using the hostif.
2634  **/
2635 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2636                                       u16 offset, u16 words, u16 *data)
2637 {
2638         s32 status = IXGBE_SUCCESS;
2639         u32 i = 0;
2640
2641         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2642
2643         /* Take semaphore for the entire operation. */
2644         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2645         if (status != IXGBE_SUCCESS) {
2646                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2647                 goto out;
2648         }
2649
2650         for (i = 0; i < words; i++) {
2651                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2652                                                          data[i]);
2653
2654                 if (status != IXGBE_SUCCESS) {
2655                         DEBUGOUT("Eeprom buffered write failed\n");
2656                         break;
2657                 }
2658         }
2659
2660         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2661 out:
2662
2663         return status;
2664 }
2665
2666 /**
2667  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2668  * @hw: pointer to hardware structure
2669  * @ptr: pointer offset in eeprom
2670  * @size: size of section pointed by ptr, if 0 first word will be used as size
2671  * @csum: address of checksum to update
2672  *
2673  * Returns error status for any failure
2674  */
2675 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2676                                    u16 size, u16 *csum, u16 *buffer,
2677                                    u32 buffer_size)
2678 {
2679         u16 buf[256];
2680         s32 status;
2681         u16 length, bufsz, i, start;
2682         u16 *local_buffer;
2683
2684         bufsz = sizeof(buf) / sizeof(buf[0]);
2685
2686         /* Read a chunk at the pointer location */
2687         if (!buffer) {
2688                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2689                 if (status) {
2690                         DEBUGOUT("Failed to read EEPROM image\n");
2691                         return status;
2692                 }
2693                 local_buffer = buf;
2694         } else {
2695                 if (buffer_size < ptr)
2696                         return  IXGBE_ERR_PARAM;
2697                 local_buffer = &buffer[ptr];
2698         }
2699
2700         if (size) {
2701                 start = 0;
2702                 length = size;
2703         } else {
2704                 start = 1;
2705                 length = local_buffer[0];
2706
2707                 /* Skip pointer section if length is invalid. */
2708                 if (length == 0xFFFF || length == 0 ||
2709                     (ptr + length) >= hw->eeprom.word_size)
2710                         return IXGBE_SUCCESS;
2711         }
2712
2713         if (buffer && ((u32)start + (u32)length > buffer_size))
2714                 return IXGBE_ERR_PARAM;
2715
2716         for (i = start; length; i++, length--) {
2717                 if (i == bufsz && !buffer) {
2718                         ptr += bufsz;
2719                         i = 0;
2720                         if (length < bufsz)
2721                                 bufsz = length;
2722
2723                         /* Read a chunk at the pointer location */
2724                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2725                                                                   bufsz, buf);
2726                         if (status) {
2727                                 DEBUGOUT("Failed to read EEPROM image\n");
2728                                 return status;
2729                         }
2730                 }
2731                 *csum += local_buffer[i];
2732         }
2733         return IXGBE_SUCCESS;
2734 }
2735
2736 /**
2737  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2738  *  @hw: pointer to hardware structure
2739  *  @buffer: pointer to buffer containing calculated checksum
2740  *  @buffer_size: size of buffer
2741  *
2742  *  Returns a negative error code on error, or the 16-bit checksum
2743  **/
2744 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2745 {
2746         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2747         u16 *local_buffer;
2748         s32 status;
2749         u16 checksum = 0;
2750         u16 pointer, i, size;
2751
2752         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2753
2754         hw->eeprom.ops.init_params(hw);
2755
2756         if (!buffer) {
2757                 /* Read pointer area */
2758                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2759                                                      IXGBE_EEPROM_LAST_WORD + 1,
2760                                                      eeprom_ptrs);
2761                 if (status) {
2762                         DEBUGOUT("Failed to read EEPROM image\n");
2763                         return status;
2764                 }
2765                 local_buffer = eeprom_ptrs;
2766         } else {
2767                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2768                         return IXGBE_ERR_PARAM;
2769                 local_buffer = buffer;
2770         }
2771
2772         /*
2773          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2774          * checksum word itself
2775          */
2776         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2777                 if (i != IXGBE_EEPROM_CHECKSUM)
2778                         checksum += local_buffer[i];
2779
2780         /*
2781          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2782          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2783          */
2784         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2785                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2786                         continue;
2787
2788                 pointer = local_buffer[i];
2789
2790                 /* Skip pointer section if the pointer is invalid. */
2791                 if (pointer == 0xFFFF || pointer == 0 ||
2792                     pointer >= hw->eeprom.word_size)
2793                         continue;
2794
2795                 switch (i) {
2796                 case IXGBE_PCIE_GENERAL_PTR:
2797                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2798                         break;
2799                 case IXGBE_PCIE_CONFIG0_PTR:
2800                 case IXGBE_PCIE_CONFIG1_PTR:
2801                         size = IXGBE_PCIE_CONFIG_SIZE;
2802                         break;
2803                 default:
2804                         size = 0;
2805                         break;
2806                 }
2807
2808                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2809                                                 buffer, buffer_size);
2810                 if (status)
2811                         return status;
2812         }
2813
2814         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2815
2816         return (s32)checksum;
2817 }
2818
2819 /**
2820  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2821  *  @hw: pointer to hardware structure
2822  *
2823  *  Returns a negative error code on error, or the 16-bit checksum
2824  **/
2825 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2826 {
2827         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2828 }
2829
2830 /**
2831  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2832  *  @hw: pointer to hardware structure
2833  *  @checksum_val: calculated checksum
2834  *
2835  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2836  *  caller does not need checksum_val, the value can be NULL.
2837  **/
2838 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2839 {
2840         s32 status;
2841         u16 checksum;
2842         u16 read_checksum = 0;
2843
2844         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2845
2846         /* Read the first word from the EEPROM. If this times out or fails, do
2847          * not continue or we could be in for a very long wait while every
2848          * EEPROM read fails
2849          */
2850         status = hw->eeprom.ops.read(hw, 0, &checksum);
2851         if (status) {
2852                 DEBUGOUT("EEPROM read failed\n");
2853                 return status;
2854         }
2855
2856         status = hw->eeprom.ops.calc_checksum(hw);
2857         if (status < 0)
2858                 return status;
2859
2860         checksum = (u16)(status & 0xffff);
2861
2862         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2863                                            &read_checksum);
2864         if (status)
2865                 return status;
2866
2867         /* Verify read checksum from EEPROM is the same as
2868          * calculated checksum
2869          */
2870         if (read_checksum != checksum) {
2871                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2872                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2873                              "Invalid EEPROM checksum");
2874         }
2875
2876         /* If the user cares, return the calculated checksum */
2877         if (checksum_val)
2878                 *checksum_val = checksum;
2879
2880         return status;
2881 }
2882
2883 /**
2884  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2885  * @hw: pointer to hardware structure
2886  *
2887  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2888  * checksum and updates the EEPROM and instructs the hardware to update
2889  * the flash.
2890  **/
2891 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2892 {
2893         s32 status;
2894         u16 checksum = 0;
2895
2896         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2897
2898         /* Read the first word from the EEPROM. If this times out or fails, do
2899          * not continue or we could be in for a very long wait while every
2900          * EEPROM read fails
2901          */
2902         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2903         if (status) {
2904                 DEBUGOUT("EEPROM read failed\n");
2905                 return status;
2906         }
2907
2908         status = ixgbe_calc_eeprom_checksum_X550(hw);
2909         if (status < 0)
2910                 return status;
2911
2912         checksum = (u16)(status & 0xffff);
2913
2914         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2915                                             checksum);
2916         if (status)
2917                 return status;
2918
2919         status = ixgbe_update_flash_X550(hw);
2920
2921         return status;
2922 }
2923
2924 /**
2925  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2926  *  @hw: pointer to hardware structure
2927  *
2928  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2929  **/
2930 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2931 {
2932         s32 status = IXGBE_SUCCESS;
2933         union ixgbe_hic_hdr2 buffer;
2934
2935         DEBUGFUNC("ixgbe_update_flash_X550");
2936
2937         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2938         buffer.req.buf_lenh = 0;
2939         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2940         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2941
2942         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2943                                               sizeof(buffer),
2944                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2945
2946         return status;
2947 }
2948
2949 /**
2950  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2951  *  @hw: pointer to hardware structure
2952  *
2953  *  Determines physical layer capabilities of the current configuration.
2954  **/
2955 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2956 {
2957         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2958         u16 ext_ability = 0;
2959
2960         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2961
2962         hw->phy.ops.identify(hw);
2963
2964         switch (hw->phy.type) {
2965         case ixgbe_phy_x550em_kr:
2966                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2967                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2968                 break;
2969         case ixgbe_phy_x550em_kx4:
2970                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2971                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2972                 break;
2973         case ixgbe_phy_x550em_ext_t:
2974                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2975                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2976                                      &ext_ability);
2977                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2978                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2979                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2980                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2981                 break;
2982         default:
2983                 break;
2984         }
2985
2986         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2987                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2988
2989         return physical_layer;
2990 }
2991
2992 /**
2993  * ixgbe_get_bus_info_x550em - Set PCI bus info
2994  * @hw: pointer to hardware structure
2995  *
2996  * Sets bus link width and speed to unknown because X550em is
2997  * not a PCI device.
2998  **/
2999 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3000 {
3001
3002         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3003
3004         hw->bus.width = ixgbe_bus_width_unknown;
3005         hw->bus.speed = ixgbe_bus_speed_unknown;
3006
3007         hw->mac.ops.set_lan_id(hw);
3008
3009         return IXGBE_SUCCESS;
3010 }
3011
3012 /**
3013  * ixgbe_disable_rx_x550 - Disable RX unit
3014  *
3015  * Enables the Rx DMA unit for x550
3016  **/
3017 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3018 {
3019         u32 rxctrl, pfdtxgswc;
3020         s32 status;
3021         struct ixgbe_hic_disable_rxen fw_cmd;
3022
3023         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3024
3025         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3026         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3027                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3028                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3029                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3030                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3031                         hw->mac.set_lben = true;
3032                 } else {
3033                         hw->mac.set_lben = false;
3034                 }
3035
3036                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3037                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3038                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3039                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3040
3041                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3042                                         sizeof(struct ixgbe_hic_disable_rxen),
3043                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3044
3045                 /* If we fail - disable RX using register write */
3046                 if (status) {
3047                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3048                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3049                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3050                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3051                         }
3052                 }
3053         }
3054 }
3055
3056 /**
3057  * ixgbe_enter_lplu_x550em - Transition to low power states
3058  *  @hw: pointer to hardware structure
3059  *
3060  * Configures Low Power Link Up on transition to low power states
3061  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3062  * X557 PHY immediately prior to entering LPLU.
3063  **/
3064 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3065 {
3066         u16 an_10g_cntl_reg, autoneg_reg, speed;
3067         s32 status;
3068         ixgbe_link_speed lcd_speed;
3069         u32 save_autoneg;
3070         bool link_up;
3071
3072         /* SW LPLU not required on later HW revisions. */
3073         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3074             (IXGBE_FUSES0_REV_MASK &
3075              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3076                 return IXGBE_SUCCESS;
3077
3078         /* If blocked by MNG FW, then don't restart AN */
3079         if (ixgbe_check_reset_blocked(hw))
3080                 return IXGBE_SUCCESS;
3081
3082         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3083         if (status != IXGBE_SUCCESS)
3084                 return status;
3085
3086         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3087
3088         if (status != IXGBE_SUCCESS)
3089                 return status;
3090
3091         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3092          * disabled, then force link down by entering low power mode.
3093          */
3094         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3095             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3096                 return ixgbe_set_copper_phy_power(hw, FALSE);
3097
3098         /* Determine LCD */
3099         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3100
3101         if (status != IXGBE_SUCCESS)
3102                 return status;
3103
3104         /* If no valid LCD link speed, then force link down and exit. */
3105         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3106                 return ixgbe_set_copper_phy_power(hw, FALSE);
3107
3108         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3109                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3110                                       &speed);
3111
3112         if (status != IXGBE_SUCCESS)
3113                 return status;
3114
3115         /* If no link now, speed is invalid so take link down */
3116         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3117         if (status != IXGBE_SUCCESS)
3118                 return ixgbe_set_copper_phy_power(hw, false);
3119
3120         /* clear everything but the speed bits */
3121         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3122
3123         /* If current speed is already LCD, then exit. */
3124         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3125              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3126             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3127              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3128                 return status;
3129
3130         /* Clear AN completed indication */
3131         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3132                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3133                                       &autoneg_reg);
3134
3135         if (status != IXGBE_SUCCESS)
3136                 return status;
3137
3138         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3139                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3140                              &an_10g_cntl_reg);
3141
3142         if (status != IXGBE_SUCCESS)
3143                 return status;
3144
3145         status = hw->phy.ops.read_reg(hw,
3146                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3147                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3148                              &autoneg_reg);
3149
3150         if (status != IXGBE_SUCCESS)
3151                 return status;
3152
3153         save_autoneg = hw->phy.autoneg_advertised;
3154
3155         /* Setup link at least common link speed */
3156         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3157
3158         /* restore autoneg from before setting lplu speed */
3159         hw->phy.autoneg_advertised = save_autoneg;
3160
3161         return status;
3162 }
3163
3164 /**
3165  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3166  *  @hw: pointer to hardware structure
3167  *  @lcd_speed: pointer to lowest common link speed
3168  *
3169  * Determine lowest common link speed with link partner.
3170  **/
3171 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3172 {
3173         u16 an_lp_status;
3174         s32 status;
3175         u16 word = hw->eeprom.ctrl_word_3;
3176
3177         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3178
3179         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3180                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3181                                       &an_lp_status);
3182
3183         if (status != IXGBE_SUCCESS)
3184                 return status;
3185
3186         /* If link partner advertised 1G, return 1G */
3187         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3188                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3189                 return status;
3190         }
3191
3192         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3193         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3194             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3195                 return status;
3196
3197         /* Link partner not capable of lower speeds, return 10G */
3198         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3199         return status;
3200 }
3201
3202 /**
3203  *  ixgbe_setup_fc_X550em - Set up flow control
3204  *  @hw: pointer to hardware structure
3205  *
3206  *  Called at init time to set up flow control.
3207  **/
3208 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3209 {
3210         s32 ret_val = IXGBE_SUCCESS;
3211         u32 pause, asm_dir, reg_val;
3212
3213         DEBUGFUNC("ixgbe_setup_fc_X550em");
3214
3215         /* Validate the requested mode */
3216         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3217                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3218                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3219                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3220                 goto out;
3221         }
3222
3223         /* 10gig parts do not have a word in the EEPROM to determine the
3224          * default flow control setting, so we explicitly set it to full.
3225          */
3226         if (hw->fc.requested_mode == ixgbe_fc_default)
3227                 hw->fc.requested_mode = ixgbe_fc_full;
3228
3229         /* Determine PAUSE and ASM_DIR bits. */
3230         switch (hw->fc.requested_mode) {
3231         case ixgbe_fc_none:
3232                 pause = 0;
3233                 asm_dir = 0;
3234                 break;
3235         case ixgbe_fc_tx_pause:
3236                 pause = 0;
3237                 asm_dir = 1;
3238                 break;
3239         case ixgbe_fc_rx_pause:
3240                 /* Rx Flow control is enabled and Tx Flow control is
3241                  * disabled by software override. Since there really
3242                  * isn't a way to advertise that we are capable of RX
3243                  * Pause ONLY, we will advertise that we support both
3244                  * symmetric and asymmetric Rx PAUSE, as such we fall
3245                  * through to the fc_full statement.  Later, we will
3246                  * disable the adapter's ability to send PAUSE frames.
3247                  */
3248         case ixgbe_fc_full:
3249                 pause = 1;
3250                 asm_dir = 1;
3251                 break;
3252         default:
3253                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3254                         "Flow control param set incorrectly\n");
3255                 ret_val = IXGBE_ERR_CONFIG;
3256                 goto out;
3257         }
3258
3259         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
3260                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
3261                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3262                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3263                 if (ret_val != IXGBE_SUCCESS)
3264                         goto out;
3265                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3266                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3267                 if (pause)
3268                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3269                 if (asm_dir)
3270                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3271                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
3272                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3273                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3274
3275                 /* This device does not fully support AN. */
3276                 hw->fc.disable_fc_autoneg = true;
3277         }
3278
3279 out:
3280         return ret_val;
3281 }
3282
3283 /**
3284  * ixgbe_set_mux - Set mux for port 1 access with CS4227
3285  * @hw: pointer to hardware structure
3286  * @state: set mux if 1, clear if 0
3287  */
3288 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3289 {
3290         u32 esdp;
3291
3292         if (!hw->bus.lan_id)
3293                 return;
3294         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3295         if (state)
3296                 esdp |= IXGBE_ESDP_SDP1;
3297         else
3298                 esdp &= ~IXGBE_ESDP_SDP1;
3299         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3300         IXGBE_WRITE_FLUSH(hw);
3301 }
3302
3303 /**
3304  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3305  *  @hw: pointer to hardware structure
3306  *  @mask: Mask to specify which semaphore to acquire
3307  *
3308  *  Acquires the SWFW semaphore and sets the I2C MUX
3309  **/
3310 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3311 {
3312         s32 status;
3313
3314         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
3315
3316         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3317         if (status)
3318                 return status;
3319
3320         if (mask & IXGBE_GSSR_I2C_MASK)
3321                 ixgbe_set_mux(hw, 1);
3322
3323         return IXGBE_SUCCESS;
3324 }
3325
3326 /**
3327  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3328  *  @hw: pointer to hardware structure
3329  *  @mask: Mask to specify which semaphore to release
3330  *
3331  *  Releases the SWFW semaphore and sets the I2C MUX
3332  **/
3333 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3334 {
3335         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3336
3337         if (mask & IXGBE_GSSR_I2C_MASK)
3338                 ixgbe_set_mux(hw, 0);
3339
3340         ixgbe_release_swfw_sync_X540(hw, mask);
3341 }
3342
3343 /**
3344  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
3345  *  @hw: pointer to hardware structure
3346  *  @mask: Mask to specify which semaphore to acquire
3347  *
3348  *  Acquires the SWFW semaphore and get the shared phy token as needed
3349  */
3350 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3351 {
3352         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3353         int retries = FW_PHY_TOKEN_RETRIES;
3354         s32 status = IXGBE_SUCCESS;
3355
3356         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
3357
3358         while (--retries) {
3359                 if (hmask)
3360                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3361                 if (status)
3362                         break;
3363                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3364                         break;
3365                 status = ixgbe_get_phy_token(hw);
3366                 if (status != IXGBE_ERR_TOKEN_RETRY)
3367                         break;
3368                 if (hmask)
3369                         ixgbe_release_swfw_sync_X540(hw, hmask);
3370                 msec_delay(FW_PHY_TOKEN_DELAY);
3371         }
3372
3373         return status;
3374 }
3375
3376 /**
3377  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
3378  *  @hw: pointer to hardware structure
3379  *  @mask: Mask to specify which semaphore to release
3380  *
3381  *  Releases the SWFW semaphore and puts the shared phy token as needed
3382  */
3383 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3384 {
3385         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3386
3387         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
3388
3389         if (mask & IXGBE_GSSR_TOKEN_SM)
3390                 ixgbe_put_phy_token(hw);
3391
3392         if (hmask)
3393                 ixgbe_release_swfw_sync_X540(hw, hmask);
3394 }
3395
3396 /**
3397  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
3398  * @hw: pointer to hardware structure
3399  *
3400  * Handle external Base T PHY interrupt. If high temperature
3401  * failure alarm then return error, else if link status change
3402  * then setup internal/external PHY link
3403  *
3404  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
3405  * failure alarm, else return PHY access status.
3406  */
3407 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
3408 {
3409         bool lsc;
3410         u32 status;
3411
3412         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
3413
3414         if (status != IXGBE_SUCCESS)
3415                 return status;
3416
3417         if (lsc)
3418                 return ixgbe_setup_internal_phy(hw);
3419
3420         return IXGBE_SUCCESS;
3421 }
3422
3423 /**
3424  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
3425  * @hw: pointer to hardware structure
3426  * @speed: new link speed
3427  * @autoneg_wait_to_complete: true when waiting for completion is needed
3428  *
3429  * Setup internal/external PHY link speed based on link speed, then set
3430  * external PHY auto advertised link speed.
3431  *
3432  * Returns error status for any failure
3433  **/
3434 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3435                                   ixgbe_link_speed speed,
3436                                   bool autoneg_wait_to_complete)
3437 {
3438         s32 status;
3439         ixgbe_link_speed force_speed;
3440
3441         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3442
3443         /* Setup internal/external PHY link speed to iXFI (10G), unless
3444          * only 1G is auto advertised then setup KX link.
3445          */
3446         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3447                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3448         else
3449                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3450
3451         /* If internal link mode is XFI, then setup XFI internal link. */
3452         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3453                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3454
3455                 if (status != IXGBE_SUCCESS)
3456                         return status;
3457         }
3458
3459         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3460 }
3461
3462 /**
3463  * ixgbe_check_link_t_X550em - Determine link and speed status
3464  * @hw: pointer to hardware structure
3465  * @speed: pointer to link speed
3466  * @link_up: true when link is up
3467  * @link_up_wait_to_complete: bool used to wait for link up or not
3468  *
3469  * Check that both the MAC and X557 external PHY have link.
3470  **/
3471 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3472                               bool *link_up, bool link_up_wait_to_complete)
3473 {
3474         u32 status;
3475         u16 autoneg_status;
3476
3477         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3478                 return IXGBE_ERR_CONFIG;
3479
3480         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3481                                               link_up_wait_to_complete);
3482
3483         /* If check link fails or MAC link is not up, then return */
3484         if (status != IXGBE_SUCCESS || !(*link_up))
3485                 return status;
3486
3487         /* MAC link is up, so check external PHY link.
3488          * Read this twice back to back to indicate current status.
3489          */
3490         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3491                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3492                                       &autoneg_status);
3493
3494         if (status != IXGBE_SUCCESS)
3495                 return status;
3496
3497         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3498                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3499                                       &autoneg_status);
3500
3501         if (status != IXGBE_SUCCESS)
3502                 return status;
3503
3504         /* If external PHY link is not up, then indicate link not up */
3505         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3506                 *link_up = false;
3507
3508         return IXGBE_SUCCESS;
3509 }
3510
3511 /**
3512  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3513  *  @hw: pointer to hardware structure
3514  **/
3515 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3516 {
3517         s32 status;
3518
3519         status = ixgbe_reset_phy_generic(hw);
3520
3521         if (status != IXGBE_SUCCESS)
3522                 return status;
3523
3524         /* Configure Link Status Alarm and Temperature Threshold interrupts */
3525         return ixgbe_enable_lasi_ext_t_x550em(hw);
3526 }
3527
3528 /**
3529  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
3530  *  @hw: pointer to hardware structure
3531  *  @led_idx: led number to turn on
3532  **/
3533 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3534 {
3535         u16 phy_data;
3536
3537         DEBUGFUNC("ixgbe_led_on_t_X550em");
3538
3539         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3540                 return IXGBE_ERR_PARAM;
3541
3542         /* To turn on the LED, set mode to ON. */
3543         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3544                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3545         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3546         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3547                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3548
3549         return IXGBE_SUCCESS;
3550 }
3551
3552 /**
3553  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3554  *  @hw: pointer to hardware structure
3555  *  @led_idx: led number to turn off
3556  **/
3557 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3558 {
3559         u16 phy_data;
3560
3561         DEBUGFUNC("ixgbe_led_off_t_X550em");
3562
3563         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3564                 return IXGBE_ERR_PARAM;
3565
3566         /* To turn on the LED, set mode to ON. */
3567         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3568                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3569         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3570         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3571                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3572
3573         return IXGBE_SUCCESS;
3574 }
3575