drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41
  42 /**
  43  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  44  *  @hw: pointer to hardware structure
  45  *
  46  *  Initialize the function pointers and assign the MAC type for X550.
  47  *  Does not touch the hardware.
  48  **/
  49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  50 {
  51         struct ixgbe_mac_info *mac = &hw->mac;
  52         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  53         s32 ret_val;
  54
  55         DEBUGFUNC("ixgbe_init_ops_X550");
  56
  57         ret_val = ixgbe_init_ops_X540(hw);
  58         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  59         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  60         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  61         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  62         mac->ops.set_source_address_pruning =
  63                         ixgbe_set_source_address_pruning_X550;
  64         mac->ops.set_ethertype_anti_spoofing =
  65                         ixgbe_set_ethertype_anti_spoofing_X550;
  66
  67         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  68         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  69         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  70         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  71         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  72         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  73         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  74         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  75         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  76
  77         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  78         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  79         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  80         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  81         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  82         return ret_val;
  83 }
  84
  85 /**
  86  * ixgbe_read_cs4227 - Read CS4227 register
  87  * @hw: pointer to hardware structure
  88  * @reg: register number to write
  89  * @value: pointer to receive value read
  90  *
  91  * Returns status code
  92  **/
  93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  94 {
  95         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
  96 }
  97
  98 /**
  99  * ixgbe_write_cs4227 - Write CS4227 register
 100  * @hw: pointer to hardware structure
 101  * @reg: register number to write
 102  * @value: value to write to register
 103  *
 104  * Returns status code
 105  **/
 106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 107 {
 108         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 109 }
 110
 111 /**
 112  * ixgbe_get_cs4227_status - Return CS4227 status
 113  * @hw: pointer to hardware structure
 114  *
 115  * Returns error if CS4227 not successfully initialized
 116  **/
 117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
 118 {
 119         s32 status;
 120         u16 value = 0;
 121         u8 retry;
 122
 123         for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
 124                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
 125                                            &value);
 126                 if (status != IXGBE_SUCCESS)
 127                         return status;
 128                 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
 129                         break;
 130                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 131         }
 132         if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
 133                 return IXGBE_ERR_PHY;
 134
 135         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 136                                     IXGBE_CS4227_SCRATCH_VALUE);
 137         if (status != IXGBE_SUCCESS)
 138                 return status;
 139         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 140         if (status != IXGBE_SUCCESS)
 141                 return status;
 142         if (value != IXGBE_CS4227_SCRATCH_VALUE)
 143                 return IXGBE_ERR_PHY;
 144         return IXGBE_SUCCESS;
 145 }
 146
 147 /**
 148  * ixgbe_read_pe - Read register from port expander
 149  * @hw: pointer to hardware structure
 150  * @reg: register number to read
 151  * @value: pointer to receive read value
 152  *
 153  * Returns status code
 154  **/
 155 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 156 {
 157         s32 status;
 158
 159         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 160         if (status != IXGBE_SUCCESS)
 161                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 162                               "port expander access failed with %d\n", status);
 163         return status;
 164 }
 165
 166 /**
 167  * ixgbe_write_pe - Write register to port expander
 168  * @hw: pointer to hardware structure
 169  * @reg: register number to write
 170  * @value: value to write
 171  *
 172  * Returns status code
 173  **/
 174 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 175 {
 176         s32 status;
 177
 178         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 179         if (status != IXGBE_SUCCESS)
 180                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 181                               "port expander access failed with %d\n", status);
 182         return status;
 183 }
 184
 185 /**
 186  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 187  * @hw: pointer to hardware structure
 188  *
 189  * Returns error code
 190  **/
 191 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 192 {
 193         s32 status;
 194         u8 reg;
 195
 196         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199         reg |= IXGBE_PE_BIT1;
 200         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 201         if (status != IXGBE_SUCCESS)
 202                 return status;
 203
 204         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 205         if (status != IXGBE_SUCCESS)
 206                 return status;
 207         reg &= ~IXGBE_PE_BIT1;
 208         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 209         if (status != IXGBE_SUCCESS)
 210                 return status;
 211
 212         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 213         if (status != IXGBE_SUCCESS)
 214                 return status;
 215         reg &= ~IXGBE_PE_BIT1;
 216         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 217         if (status != IXGBE_SUCCESS)
 218                 return status;
 219
 220         usec_delay(IXGBE_CS4227_RESET_HOLD);
 221
 222         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 223         if (status != IXGBE_SUCCESS)
 224                 return status;
 225         reg |= IXGBE_PE_BIT1;
 226         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 227         if (status != IXGBE_SUCCESS)
 228                 return status;
 229
 230         msec_delay(IXGBE_CS4227_RESET_DELAY);
 231
 232         return IXGBE_SUCCESS;
 233 }
 234
 235 /**
 236  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 237  * @hw: pointer to hardware structure
 238  **/
 239 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 240 {
 241         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 242         s32 status;
 243         u8 retry;
 244
 245         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 246                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 247                 if (status != IXGBE_SUCCESS) {
 248                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 249                                       "semaphore failed with %d\n", status);
 250                         return;
 251                 }
 252                 status = ixgbe_get_cs4227_status(hw);
 253                 if (status == IXGBE_SUCCESS) {
 254                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 255                         msec_delay(hw->eeprom.semaphore_delay);
 256                         return;
 257                 }
 258                 ixgbe_reset_cs4227(hw);
 259                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 260                 msec_delay(hw->eeprom.semaphore_delay);
 261         }
 262         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 263                       "Unable to initialize CS4227, err=%d\n", status);
 264 }
 265
 266 /**
 267  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 268  * @hw: pointer to hardware structure
 269  **/
 270 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 271 {
 272         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 273
 274         if (hw->bus.lan_id) {
 275                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 276                 esdp |= IXGBE_ESDP_SDP1_DIR;
 277         }
 278         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 279         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 280         IXGBE_WRITE_FLUSH(hw);
 281 }
 282
 283 /**
 284  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 285  * @hw: pointer to hardware structure
 286  *
 287  * Returns error code
 288  */
 289 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 290 {
 291         switch (hw->device_id) {
 292         case IXGBE_DEV_ID_X550EM_X_SFP:
 293                 /* set up for CS4227 usage */
 294                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 295                 ixgbe_setup_mux_ctl(hw);
 296                 ixgbe_check_cs4227(hw);
 297
 298                 return ixgbe_identify_module_generic(hw);
 299                 break;
 300         case IXGBE_DEV_ID_X550EM_X_KX4:
 301                 hw->phy.type = ixgbe_phy_x550em_kx4;
 302                 break;
 303         case IXGBE_DEV_ID_X550EM_X_KR:
 304                 hw->phy.type = ixgbe_phy_x550em_kr;
 305                 break;
 306         case IXGBE_DEV_ID_X550EM_X_1G_T:
 307         case IXGBE_DEV_ID_X550EM_X_10G_T:
 308                 return ixgbe_identify_phy_generic(hw);
 309         default:
 310                 break;
 311         }
 312         return IXGBE_SUCCESS;
 313 }
 314
 315 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 316                                      u32 device_type, u16 *phy_data)
 317 {
 318         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 319         return IXGBE_NOT_IMPLEMENTED;
 320 }
 321
 322 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 323                                       u32 device_type, u16 phy_data)
 324 {
 325         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 326         return IXGBE_NOT_IMPLEMENTED;
 327 }
 328
 329 /**
 330 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 331 *  @hw: pointer to hardware structure
 332 *
 333 *  Initialize the function pointers and for MAC type X550EM.
 334 *  Does not touch the hardware.
 335 **/
 336 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 337 {
 338         struct ixgbe_mac_info *mac = &hw->mac;
 339         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 340         struct ixgbe_phy_info *phy = &hw->phy;
 341         s32 ret_val;
 342
 343         DEBUGFUNC("ixgbe_init_ops_X550EM");
 344
 345         /* Similar to X550 so start there. */
 346         ret_val = ixgbe_init_ops_X550(hw);
 347
 348         /* Since this function eventually calls
 349          * ixgbe_init_ops_540 by design, we are setting
 350          * the pointers to NULL explicitly here to overwrite
 351          * the values being set in the x540 function.
 352          */
 353         /* Thermal sensor not supported in x550EM */
 354         mac->ops.get_thermal_sensor_data = NULL;
 355         mac->ops.init_thermal_sensor_thresh = NULL;
 356         mac->thermal_sensor_enabled = false;
 357
 358         /* FCOE not supported in x550EM */
 359         mac->ops.get_san_mac_addr = NULL;
 360         mac->ops.set_san_mac_addr = NULL;
 361         mac->ops.get_wwn_prefix = NULL;
 362         mac->ops.get_fcoe_boot_status = NULL;
 363
 364         /* IPsec not supported in x550EM */
 365         mac->ops.disable_sec_rx_path = NULL;
 366         mac->ops.enable_sec_rx_path = NULL;
 367
 368         /* AUTOC register is not present in x550EM. */
 369         mac->ops.prot_autoc_read = NULL;
 370         mac->ops.prot_autoc_write = NULL;
 371
 372         /* X550EM bus type is internal*/
 373         hw->bus.type = ixgbe_bus_type_internal;
 374         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 375
 376         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 377         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 378         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 379         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 380         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 381         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 382         mac->ops.get_supported_physical_layer =
 383                                     ixgbe_get_supported_physical_layer_X550em;
 384
 385         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 386                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 387         else
 388                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 389
 390         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 391         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 392
 393         /* PHY */
 394         phy->ops.init = ixgbe_init_phy_ops_X550em;
 395         phy->ops.identify = ixgbe_identify_phy_x550em;
 396         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 397                 phy->ops.set_phy_power = NULL;
 398
 399
 400         /* EEPROM */
 401         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 402         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 403         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 404         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 405         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 406         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 407         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 408         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 409
 410         return ret_val;
 411 }
 412
 413 /**
 414  *  ixgbe_dmac_config_X550
 415  *  @hw: pointer to hardware structure
 416  *
 417  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 418  *  When disabling dmac, dmac enable dmac bit is cleared.
 419  **/
 420 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 421 {
 422         u32 reg, high_pri_tc;
 423
 424         DEBUGFUNC("ixgbe_dmac_config_X550");
 425
 426         /* Disable DMA coalescing before configuring */
 427         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 428         reg &= ~IXGBE_DMACR_DMAC_EN;
 429         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 430
 431         /* Disable DMA Coalescing if the watchdog timer is 0 */
 432         if (!hw->mac.dmac_config.watchdog_timer)
 433                 goto out;
 434
 435         ixgbe_dmac_config_tcs_X550(hw);
 436
 437         /* Configure DMA Coalescing Control Register */
 438         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 439
 440         /* Set the watchdog timer in units of 40.96 usec */
 441         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 442         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 443
 444         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 445         /* If fcoe is enabled, set high priority traffic class */
 446         if (hw->mac.dmac_config.fcoe_en) {
 447                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 448                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 449                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 450         }
 451         reg |= IXGBE_DMACR_EN_MNG_IND;
 452
 453         /* Enable DMA coalescing after configuration */
 454         reg |= IXGBE_DMACR_DMAC_EN;
 455         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 456
 457 out:
 458         return IXGBE_SUCCESS;
 459 }
 460
 461 /**
 462  *  ixgbe_dmac_config_tcs_X550
 463  *  @hw: pointer to hardware structure
 464  *
 465  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 466  *  be cleared before configuring.
 467  **/
 468 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 469 {
 470         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 471
 472         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 473
 474         /* Configure DMA coalescing enabled */
 475         switch (hw->mac.dmac_config.link_speed) {
 476         case IXGBE_LINK_SPEED_100_FULL:
 477                 pb_headroom = IXGBE_DMACRXT_100M;
 478                 break;
 479         case IXGBE_LINK_SPEED_1GB_FULL:
 480                 pb_headroom = IXGBE_DMACRXT_1G;
 481                 break;
 482         default:
 483                 pb_headroom = IXGBE_DMACRXT_10G;
 484                 break;
 485         }
 486
 487         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 488                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 489
 490         /* Set the per Rx packet buffer receive threshold */
 491         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 492                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 493                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 494
 495                 if (tc < hw->mac.dmac_config.num_tcs) {
 496                         /* Get Rx PB size */
 497                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 498                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 499                                 IXGBE_RXPBSIZE_SHIFT;
 500
 501                         /* Calculate receive buffer threshold in kilobytes */
 502                         if (rx_pb_size > pb_headroom)
 503                                 rx_pb_size = rx_pb_size - pb_headroom;
 504                         else
 505                                 rx_pb_size = 0;
 506
 507                         /* Minimum of MFS shall be set for DMCTH */
 508                         reg |= (rx_pb_size > maxframe_size_kb) ?
 509                                 rx_pb_size : maxframe_size_kb;
 510                 }
 511                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 512         }
 513         return IXGBE_SUCCESS;
 514 }
 515
 516 /**
 517  *  ixgbe_dmac_update_tcs_X550
 518  *  @hw: pointer to hardware structure
 519  *
 520  *  Disables dmac, updates per TC settings, and then enables dmac.
 521  **/
 522 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 523 {
 524         u32 reg;
 525
 526         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 527
 528         /* Disable DMA coalescing before configuring */
 529         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 530         reg &= ~IXGBE_DMACR_DMAC_EN;
 531         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 532
 533         ixgbe_dmac_config_tcs_X550(hw);
 534
 535         /* Enable DMA coalescing after configuration */
 536         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 537         reg |= IXGBE_DMACR_DMAC_EN;
 538         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 539
 540         return IXGBE_SUCCESS;
 541 }
 542
 543 /**
 544  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 545  *  @hw: pointer to hardware structure
 546  *
 547  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 548  *  ixgbe_hw struct in order to set up EEPROM access.
 549  **/
 550 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 551 {
 552         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 553         u32 eec;
 554         u16 eeprom_size;
 555
 556         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 557
 558         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 559                 eeprom->semaphore_delay = 10;
 560                 eeprom->type = ixgbe_flash;
 561
 562                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 563                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 564                                     IXGBE_EEC_SIZE_SHIFT);
 565                 eeprom->word_size = 1 << (eeprom_size +
 566                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 567
 568                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 569                           eeprom->type, eeprom->word_size);
 570         }
 571
 572         return IXGBE_SUCCESS;
 573 }
 574
 575 /**
 576  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 577  *  @hw: pointer to the HW structure
 578  *  @enable_eee: boolean flag to enable EEE
 579  *
 580  *  Enable/disable EEE based on enable_eee flag.
 581  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 582  *  are modified.
 583  *
 584  **/
 585 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 586 {
 587         u32 eeer;
 588         u16 autoneg_eee_reg;
 589         u32 link_reg;
 590         s32 status;
 591
 592         DEBUGFUNC("ixgbe_setup_eee_X550");
 593
 594         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 595         /* Enable or disable EEE per flag */
 596         if (enable_eee) {
 597                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 598
 599                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 600                         /* Advertise EEE capability */
 601                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 602                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 603
 604                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 605                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 606                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 607
 608                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 609                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 610                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 611                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 612                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 613                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 614                         if (status != IXGBE_SUCCESS)
 615                                 return status;
 616
 617                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 618                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 619
 620                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 621                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 622                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 623                         if (status != IXGBE_SUCCESS)
 624                                 return status;
 625                 }
 626         } else {
 627                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 628
 629                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 630                         /* Disable advertised EEE capability */
 631                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 632                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 633
 634                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 635                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 636                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 637
 638                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 639                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 640                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 641                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 642                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 643                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 644                         if (status != IXGBE_SUCCESS)
 645                                 return status;
 646
 647                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 648                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 649
 650                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 651                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 652                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 653                         if (status != IXGBE_SUCCESS)
 654                                 return status;
 655                 }
 656         }
 657         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 658
 659         return IXGBE_SUCCESS;
 660 }
 661
 662 /**
 663  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 664  * @hw: pointer to hardware structure
 665  * @enable: enable or disable source address pruning
 666  * @pool: Rx pool to set source address pruning for
 667  **/
 668 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 669                                            unsigned int pool)
 670 {
 671         u64 pfflp;
 672
 673         /* max rx pool is 63 */
 674         if (pool > 63)
 675                 return;
 676
 677         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 678         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 679
 680         if (enable)
 681                 pfflp |= (1ULL << pool);
 682         else
 683                 pfflp &= ~(1ULL << pool);
 684
 685         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 686         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 687 }
 688
 689 /**
 690  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 691  *  @hw: pointer to hardware structure
 692  *  @enable: enable or disable switch for Ethertype anti-spoofing
 693  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 694  *
 695  **/
 696 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 697                 bool enable, int vf)
 698 {
 699         int vf_target_reg = vf >> 3;
 700         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 701         u32 pfvfspoof;
 702
 703         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 704
 705         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 706         if (enable)
 707                 pfvfspoof |= (1 << vf_target_shift);
 708         else
 709                 pfvfspoof &= ~(1 << vf_target_shift);
 710
 711         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 712 }
 713
 714 /**
 715  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 716  *  device
 717  *  @hw: pointer to hardware structure
 718  *  @reg_addr: 32 bit PHY register to write
 719  *  @device_type: 3 bit device type
 720  *  @data: Data to write to the register
 721  **/
 722 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 723                             u32 device_type, u32 data)
 724 {
 725         u32 i, command, error;
 726
 727         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 728                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 729
 730         /* Write IOSF control register */
 731         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 732
 733         /* Write IOSF data register */
 734         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 735         /*
 736          * Check every 10 usec to see if the address cycle completed.
 737          * The SB IOSF BUSY bit will clear when the operation is
 738          * complete
 739          */
 740         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 741                 usec_delay(10);
 742
 743                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 744                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 745                         break;
 746         }
 747
 748         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 749                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 750                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 751                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 752                               "Failed to write, error %x\n", error);
 753                 return IXGBE_ERR_PHY;
 754         }
 755
 756         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 757                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
 758                 return IXGBE_ERR_PHY;
 759         }
 760
 761         return IXGBE_SUCCESS;
 762 }
 763
 764 /**
 765  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 766  *  device
 767  *  @hw: pointer to hardware structure
 768  *  @reg_addr: 32 bit PHY register to write
 769  *  @device_type: 3 bit device type
 770  *  @phy_data: Pointer to read data from the register
 771  **/
 772 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 773                            u32 device_type, u32 *data)
 774 {
 775         u32 i, command, error;
 776
 777         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 778                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 779
 780         /* Write IOSF control register */
 781         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 782
 783         /*
 784          * Check every 10 usec to see if the address cycle completed.
 785          * The SB IOSF BUSY bit will clear when the operation is
 786          * complete
 787          */
 788         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 789                 usec_delay(10);
 790
 791                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 792                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 793                         break;
 794         }
 795
 796         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 797                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 798                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 799                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 800                                 "Failed to read, error %x\n", error);
 801                 return IXGBE_ERR_PHY;
 802         }
 803
 804         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 805                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
 806                 return IXGBE_ERR_PHY;
 807         }
 808
 809         *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 810
 811         return IXGBE_SUCCESS;
 812 }
 813
 814 /**
 815  *  ixgbe_disable_mdd_X550
 816  *  @hw: pointer to hardware structure
 817  *
 818  *  Disable malicious driver detection
 819  **/
 820 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 821 {
 822         u32 reg;
 823
 824         DEBUGFUNC("ixgbe_disable_mdd_X550");
 825
 826         /* Disable MDD for TX DMA and interrupt */
 827         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 828         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 829         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 830
 831         /* Disable MDD for RX and interrupt */
 832         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 833         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 834         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 835 }
 836
 837 /**
 838  *  ixgbe_enable_mdd_X550
 839  *  @hw: pointer to hardware structure
 840  *
 841  *  Enable malicious driver detection
 842  **/
 843 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 844 {
 845         u32 reg;
 846
 847         DEBUGFUNC("ixgbe_enable_mdd_X550");
 848
 849         /* Enable MDD for TX DMA and interrupt */
 850         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 851         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 852         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 853
 854         /* Enable MDD for RX and interrupt */
 855         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 856         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 857         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 858 }
 859
 860 /**
 861  *  ixgbe_restore_mdd_vf_X550
 862  *  @hw: pointer to hardware structure
 863  *  @vf: vf index
 864  *
 865  *  Restore VF that was disabled during malicious driver detection event
 866  **/
 867 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 868 {
 869         u32 idx, reg, num_qs, start_q, bitmask;
 870
 871         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 872
 873         /* Map VF to queues */
 874         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 875         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 876         case IXGBE_MRQC_VMDQRT8TCEN:
 877                 num_qs = 8;  /* 16 VFs / pools */
 878                 bitmask = 0x000000FF;
 879                 break;
 880         case IXGBE_MRQC_VMDQRSS32EN:
 881         case IXGBE_MRQC_VMDQRT4TCEN:
 882                 num_qs = 4;  /* 32 VFs / pools */
 883                 bitmask = 0x0000000F;
 884                 break;
 885         default:            /* 64 VFs / pools */
 886                 num_qs = 2;
 887                 bitmask = 0x00000003;
 888                 break;
 889         }
 890         start_q = vf * num_qs;
 891
 892         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 893         idx = start_q / 32;
 894         reg = 0;
 895         reg |= (bitmask << (start_q % 32));
 896         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 897         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 898 }
 899
 900 /**
 901  *  ixgbe_mdd_event_X550
 902  *  @hw: pointer to hardware structure
 903  *  @vf_bitmap: vf bitmap of malicious vfs
 904  *
 905  *  Handle malicious driver detection event.
 906  **/
 907 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 908 {
 909         u32 wqbr;
 910         u32 i, j, reg, q, shift, vf, idx;
 911
 912         DEBUGFUNC("ixgbe_mdd_event_X550");
 913
 914         /* figure out pool size for mapping to vf's */
 915         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 916         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 917         case IXGBE_MRQC_VMDQRT8TCEN:
 918                 shift = 3;  /* 16 VFs / pools */
 919                 break;
 920         case IXGBE_MRQC_VMDQRSS32EN:
 921         case IXGBE_MRQC_VMDQRT4TCEN:
 922                 shift = 2;  /* 32 VFs / pools */
 923                 break;
 924         default:
 925                 shift = 1;  /* 64 VFs / pools */
 926                 break;
 927         }
 928
 929         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
 930         for (i = 0; i < 4; i++) {
 931                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
 932                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
 933
 934                 if (!wqbr)
 935                         continue;
 936
 937                 /* Get malicious queue */
 938                 for (j = 0; j < 32 && wqbr; j++) {
 939
 940                         if (!(wqbr & (1 << j)))
 941                                 continue;
 942
 943                         /* Get queue from bitmask */
 944                         q = j + (i * 32);
 945
 946                         /* Map queue to vf */
 947                         vf = (q >> shift);
 948
 949                         /* Set vf bit in vf_bitmap */
 950                         idx = vf / 32;
 951                         vf_bitmap[idx] |= (1 << (vf % 32));
 952                         wqbr &= ~(1 << j);
 953                 }
 954         }
 955 }
 956
 957 /**
 958  *  ixgbe_get_media_type_X550em - Get media type
 959  *  @hw: pointer to hardware structure
 960  *
 961  *  Returns the media type (fiber, copper, backplane)
 962  */
 963 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
 964 {
 965         enum ixgbe_media_type media_type;
 966
 967         DEBUGFUNC("ixgbe_get_media_type_X550em");
 968
 969         /* Detect if there is a copper PHY attached. */
 970         switch (hw->device_id) {
 971         case IXGBE_DEV_ID_X550EM_X_KR:
 972         case IXGBE_DEV_ID_X550EM_X_KX4:
 973                 media_type = ixgbe_media_type_backplane;
 974                 break;
 975         case IXGBE_DEV_ID_X550EM_X_SFP:
 976                 media_type = ixgbe_media_type_fiber;
 977                 break;
 978         case IXGBE_DEV_ID_X550EM_X_1G_T:
 979         case IXGBE_DEV_ID_X550EM_X_10G_T:
 980                 media_type = ixgbe_media_type_copper;
 981                 break;
 982         default:
 983                 media_type = ixgbe_media_type_unknown;
 984                 break;
 985         }
 986         return media_type;
 987 }
 988
 989 /**
 990  *  ixgbe_setup_sfp_modules_X550em - Setup SFP module
 991  *  @hw: pointer to hardware structure
 992  */
 993 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
 994 {
 995         bool setup_linear;
 996         u16 reg_slice, edc_mode;
 997         s32 ret_val;
 998
 999         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1000
1001         switch (hw->phy.sfp_type) {
1002         case ixgbe_sfp_type_unknown:
1003                 return IXGBE_SUCCESS;
1004         case ixgbe_sfp_type_not_present:
1005                 return IXGBE_ERR_SFP_NOT_PRESENT;
1006         case ixgbe_sfp_type_da_cu_core0:
1007         case ixgbe_sfp_type_da_cu_core1:
1008                 setup_linear = true;
1009                 break;
1010         case ixgbe_sfp_type_srlr_core0:
1011         case ixgbe_sfp_type_srlr_core1:
1012         case ixgbe_sfp_type_da_act_lmt_core0:
1013         case ixgbe_sfp_type_da_act_lmt_core1:
1014         case ixgbe_sfp_type_1g_sx_core0:
1015         case ixgbe_sfp_type_1g_sx_core1:
1016         case ixgbe_sfp_type_1g_lx_core0:
1017         case ixgbe_sfp_type_1g_lx_core1:
1018                 setup_linear = false;
1019                 break;
1020         default:
1021                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1022         }
1023
1024         ixgbe_init_mac_link_ops_X550em(hw);
1025         hw->phy.ops.reset = NULL;
1026
1027         /* The CS4227 slice address is the base address + the port-pair reg
1028          * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
1029          */
1030         reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12);
1031
1032         if (setup_linear)
1033                 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1034         else
1035                 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1036
1037         /* Configure CS4227 for connection type. */
1038         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1039                                            edc_mode);
1040
1041         if (ret_val != IXGBE_SUCCESS)
1042                 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
1043                                                    edc_mode);
1044
1045         return ret_val;
1046 }
1047
1048 /**
1049  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1050  *  @hw: pointer to hardware structure
1051  */
1052 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1053 {
1054         struct ixgbe_mac_info *mac = &hw->mac;
1055
1056         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1057
1058          switch (hw->mac.ops.get_media_type(hw)) {
1059          case ixgbe_media_type_fiber:
1060                 /* CS4227 does not support autoneg, so disable the laser control
1061                  * functions for SFP+ fiber
1062                  */
1063                 mac->ops.disable_tx_laser = NULL;
1064                 mac->ops.enable_tx_laser = NULL;
1065                 mac->ops.flap_tx_laser = NULL;
1066                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1067                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1068                 mac->ops.set_rate_select_speed =
1069                                         ixgbe_set_soft_rate_select_speed;
1070                 break;
1071         case ixgbe_media_type_copper:
1072                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1073                 break;
1074         default:
1075                 break;
1076          }
1077 }
1078
1079 /**
1080  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1081  *  @hw: pointer to hardware structure
1082  *  @speed: pointer to link speed
1083  *  @autoneg: true when autoneg or autotry is enabled
1084  */
1085 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1086                                        ixgbe_link_speed *speed,
1087                                        bool *autoneg)
1088 {
1089         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1090
1091         /* SFP */
1092         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1093
1094                 /* CS4227 SFP must not enable auto-negotiation */
1095                 *autoneg = false;
1096
1097                 /* Check if 1G SFP module. */
1098                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1099                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1100                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1101                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1102                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1103                         return IXGBE_SUCCESS;
1104                 }
1105
1106                 /* Link capabilities are based on SFP */
1107                 if (hw->phy.multispeed_fiber)
1108                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1109                                  IXGBE_LINK_SPEED_1GB_FULL;
1110                 else
1111                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1112         } else {
1113                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1114                          IXGBE_LINK_SPEED_1GB_FULL;
1115                 *autoneg = true;
1116         }
1117
1118         return IXGBE_SUCCESS;
1119 }
1120
1121 /**
1122  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1123  * @hw: pointer to hardware structure
1124  * @lsc: pointer to boolean flag which indicates whether external Base T
1125  *       PHY interrupt is lsc
1126  *
1127  * Determime if external Base T PHY interrupt cause is high temperature
1128  * failure alarm or link status change.
1129  *
1130  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1131  * failure alarm, else return PHY access status.
1132  */
1133 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1134 {
1135         u32 status;
1136         u16 reg;
1137
1138         *lsc = false;
1139
1140         /* Vendor alarm triggered */
1141         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1142                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1143                                       &reg);
1144
1145         if (status != IXGBE_SUCCESS ||
1146             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1147                 return status;
1148
1149         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1150         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1151                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1152                                       &reg);
1153
1154         if (status != IXGBE_SUCCESS ||
1155             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1156             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1157                 return status;
1158
1159         /* High temperature failure alarm triggered */
1160         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1161                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1162                                       &reg);
1163
1164         if (status != IXGBE_SUCCESS)
1165                 return status;
1166
1167         /* If high temperature failure, then return over temp error and exit */
1168         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL)
1169                 return IXGBE_ERR_OVERTEMP;
1170
1171         /* Vendor alarm 2 triggered */
1172         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1173                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1174
1175         if (status != IXGBE_SUCCESS ||
1176             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1177                 return status;
1178
1179         /* link connect/disconnect event occurred */
1180         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1181                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1182
1183         if (status != IXGBE_SUCCESS)
1184                 return status;
1185
1186         /* Indicate LSC */
1187         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1188                 *lsc = true;
1189
1190         return IXGBE_SUCCESS;
1191 }
1192
1193 /**
1194  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1195  * @hw: pointer to hardware structure
1196  *
1197  * Enable link status change and temperature failure alarm for the external
1198  * Base T PHY
1199  *
1200  * Returns PHY access status
1201  */
1202 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1203 {
1204         u32 status;
1205         u16 reg;
1206         bool lsc;
1207
1208         /* Clear interrupt flags */
1209         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1210
1211         /* Enable link status change alarm */
1212         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1213                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1214
1215         if (status != IXGBE_SUCCESS)
1216                 return status;
1217
1218         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1219
1220         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1221                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1222
1223         if (status != IXGBE_SUCCESS)
1224                 return status;
1225
1226         /* Enables high temperature failure alarm */
1227         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1228                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1229                                       &reg);
1230
1231         if (status != IXGBE_SUCCESS)
1232                 return status;
1233
1234         reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1235
1236         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1237                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1238                                        reg);
1239
1240         if (status != IXGBE_SUCCESS)
1241                 return status;
1242
1243         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1244         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1245                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1246                                       &reg);
1247
1248         if (status != IXGBE_SUCCESS)
1249                 return status;
1250
1251         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1252                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1253
1254         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1255                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1256                                        reg);
1257
1258         if (status != IXGBE_SUCCESS)
1259                 return status;
1260
1261         /* Enable chip-wide vendor alarm */
1262         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1263                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1264                                       &reg);
1265
1266         if (status != IXGBE_SUCCESS)
1267                 return status;
1268
1269         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1270
1271         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1272                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1273                                        reg);
1274
1275         return status;
1276 }
1277
1278 /**
1279  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1280  *  @hw: pointer to hardware structure
1281  *
1282  *  Initialize any function pointers that were not able to be
1283  *  set during init_shared_code because the PHY/SFP type was
1284  *  not known.  Perform the SFP init if necessary.
1285  */
1286 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1287 {
1288         struct ixgbe_phy_info *phy = &hw->phy;
1289         s32 ret_val;
1290
1291         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1292
1293         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1294                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1295                 ixgbe_setup_mux_ctl(hw);
1296         }
1297
1298         /* Identify the PHY or SFP module */
1299         ret_val = phy->ops.identify(hw);
1300         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1301                 return ret_val;
1302
1303         /* Setup function pointers based on detected hardware */
1304         ixgbe_init_mac_link_ops_X550em(hw);
1305         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1306                 phy->ops.reset = NULL;
1307
1308         /* Set functions pointers based on phy type */
1309         switch (hw->phy.type) {
1310         case ixgbe_phy_x550em_kx4:
1311                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1312                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1313                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1314                 break;
1315         case ixgbe_phy_x550em_kr:
1316                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1317                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1318                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1319                 break;
1320         case ixgbe_phy_x550em_ext_t:
1321                 phy->ops.setup_internal_link =
1322                                          ixgbe_setup_internal_phy_t_x550em;
1323                 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1324                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1325                 break;
1326         default:
1327                 break;
1328         }
1329         return ret_val;
1330 }
1331
1332 /**
1333  *  ixgbe_reset_hw_X550em - Perform hardware reset
1334  *  @hw: pointer to hardware structure
1335  *
1336  *  Resets the hardware by resetting the transmit and receive units, masks
1337  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1338  *  reset.
1339  */
1340 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1341 {
1342         struct ixgbe_hic_hdr fw_cmd;
1343         ixgbe_link_speed link_speed;
1344         s32 status;
1345         u32 ctrl = 0;
1346         u32 i;
1347         bool link_up = false;
1348
1349         DEBUGFUNC("ixgbe_reset_hw_X550em");
1350
1351         fw_cmd.cmd = FW_PHY_MGMT_REQ_CMD;
1352         fw_cmd.buf_len = 0;
1353         fw_cmd.cmd_or_resp.cmd_resv = 0;
1354         fw_cmd.checksum = FW_DEFAULT_CHECKSUM;
1355         status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
1356                                               sizeof(fw_cmd),
1357                                               IXGBE_HI_PHY_MGMT_REQ_TIMEOUT,
1358                                               true);
1359         if (status)
1360                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1361                               "PHY mgmt command failed with %d\n", status);
1362         else if (fw_cmd.cmd_or_resp.ret_status != FW_CEM_RESP_STATUS_SUCCESS)
1363                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1364                               "PHY mgmt command returned %d\n",
1365                               fw_cmd.cmd_or_resp.ret_status);
1366
1367         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1368         status = hw->mac.ops.stop_adapter(hw);
1369         if (status != IXGBE_SUCCESS)
1370                 return status;
1371
1372         /* flush pending Tx transactions */
1373         ixgbe_clear_tx_pending(hw);
1374
1375         /* PHY ops must be identified and initialized prior to reset */
1376
1377         /* Identify PHY and related function pointers */
1378         status = hw->phy.ops.init(hw);
1379
1380         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1381                 return status;
1382
1383         /* start the external PHY */
1384         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1385                 status = ixgbe_init_ext_t_x550em(hw);
1386                 if (status)
1387                         return status;
1388         }
1389
1390         /* Setup SFP module if there is one present. */
1391         if (hw->phy.sfp_setup_needed) {
1392                 status = hw->mac.ops.setup_sfp(hw);
1393                 hw->phy.sfp_setup_needed = false;
1394         }
1395
1396         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1397                 return status;
1398
1399         /* Reset PHY */
1400         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1401                 hw->phy.ops.reset(hw);
1402
1403 mac_reset_top:
1404         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1405          * If link reset is used when link is up, it might reset the PHY when
1406          * mng is using it.  If link is down or the flag to force full link
1407          * reset is set, then perform link reset.
1408          */
1409         ctrl = IXGBE_CTRL_LNK_RST;
1410         if (!hw->force_full_reset) {
1411                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1412                 if (link_up)
1413                         ctrl = IXGBE_CTRL_RST;
1414         }
1415
1416         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1417         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1418         IXGBE_WRITE_FLUSH(hw);
1419
1420         /* Poll for reset bit to self-clear meaning reset is complete */
1421         for (i = 0; i < 10; i++) {
1422                 usec_delay(1);
1423                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1424                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1425                         break;
1426         }
1427
1428         if (ctrl & IXGBE_CTRL_RST_MASK) {
1429                 status = IXGBE_ERR_RESET_FAILED;
1430                 DEBUGOUT("Reset polling failed to complete.\n");
1431         }
1432
1433         msec_delay(50);
1434
1435         /* Double resets are required for recovery from certain error
1436          * conditions.  Between resets, it is necessary to stall to
1437          * allow time for any pending HW events to complete.
1438          */
1439         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1440                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1441                 goto mac_reset_top;
1442         }
1443
1444         /* Store the permanent mac address */
1445         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1446
1447         /* Store MAC address from RAR0, clear receive address registers, and
1448          * clear the multicast table.  Also reset num_rar_entries to 128,
1449          * since we modify this value when programming the SAN MAC address.
1450          */
1451         hw->mac.num_rar_entries = 128;
1452         hw->mac.ops.init_rx_addrs(hw);
1453
1454
1455         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1456                 ixgbe_setup_mux_ctl(hw);
1457
1458         return status;
1459 }
1460
1461 /**
1462  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1463  * @hw: pointer to hardware structure
1464  */
1465 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1466 {
1467         u32 status;
1468         u16 reg;
1469
1470         status = hw->phy.ops.read_reg(hw,
1471                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1472                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1473                                       &reg);
1474
1475         if (status != IXGBE_SUCCESS)
1476                 return status;
1477
1478         /* If PHY FW reset completed bit is set then this is the first
1479          * SW instance after a power on so the PHY FW must be un-stalled.
1480          */
1481         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1482                 status = hw->phy.ops.read_reg(hw,
1483                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1484                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1485                                         &reg);
1486
1487                 if (status != IXGBE_SUCCESS)
1488                         return status;
1489
1490                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1491
1492                 status = hw->phy.ops.write_reg(hw,
1493                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1494                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1495                                         reg);
1496
1497                 if (status != IXGBE_SUCCESS)
1498                         return status;
1499         }
1500
1501         /* Configure Link Status Alarm and Temperature Threshold interrupts */
1502         status = ixgbe_enable_lasi_ext_t_x550em(hw);
1503
1504         return status;
1505 }
1506
1507 /**
1508  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1509  *  @hw: pointer to hardware structure
1510  *
1511  *  Configures the integrated KR PHY.
1512  **/
1513 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1514 {
1515         s32 status;
1516         u32 reg_val;
1517
1518         status = ixgbe_read_iosf_sb_reg_x550(hw,
1519                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1520                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1521         if (status)
1522                 return status;
1523
1524         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1525         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1526                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1527         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1528                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1529
1530         /* Advertise 10G support. */
1531         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1532                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1533
1534         /* Advertise 1G support. */
1535         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1536                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1537
1538         /* Restart auto-negotiation. */
1539         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1540         status = ixgbe_write_iosf_sb_reg_x550(hw,
1541                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1542                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1543
1544         return status;
1545 }
1546
1547 /**
1548  *  ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1549  *  @hw: pointer to hardware structure
1550  *
1551  *  Configures the integrated KX4 PHY.
1552  **/
1553 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1554 {
1555         s32 status;
1556         u32 reg_val;
1557
1558         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1559                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, &reg_val);
1560         if (status)
1561                 return status;
1562
1563         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1564                         IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1565
1566         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1567
1568         /* Advertise 10G support. */
1569         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1570                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1571
1572         /* Advertise 1G support. */
1573         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1574                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1575
1576         /* Restart auto-negotiation. */
1577         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1578         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1579                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, reg_val);
1580
1581         return status;
1582 }
1583
1584 /**
1585  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1586  *  @hw: pointer to hardware structure
1587  *  @speed: the link speed to force
1588  *
1589  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1590  *  internal and external PHY at a specific speed, without autonegotiation.
1591  **/
1592 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1593 {
1594         s32 status;
1595         u32 reg_val;
1596
1597         /* Disable AN and force speed to 10G Serial. */
1598         status = ixgbe_read_iosf_sb_reg_x550(hw,
1599                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1600                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1601         if (status != IXGBE_SUCCESS)
1602                 return status;
1603
1604         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1605         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1606
1607         /* Select forced link speed for internal PHY. */
1608         switch (*speed) {
1609         case IXGBE_LINK_SPEED_10GB_FULL:
1610                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1611                 break;
1612         case IXGBE_LINK_SPEED_1GB_FULL:
1613                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1614                 break;
1615         default:
1616                 /* Other link speeds are not supported by internal KR PHY. */
1617                 return IXGBE_ERR_LINK_SETUP;
1618         }
1619
1620         status = ixgbe_write_iosf_sb_reg_x550(hw,
1621                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1622                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1623         if (status != IXGBE_SUCCESS)
1624                 return status;
1625
1626         /* Disable training protocol FSM. */
1627         status = ixgbe_read_iosf_sb_reg_x550(hw,
1628                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1629                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1630         if (status != IXGBE_SUCCESS)
1631                 return status;
1632         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1633         status = ixgbe_write_iosf_sb_reg_x550(hw,
1634                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1635                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1636         if (status != IXGBE_SUCCESS)
1637                 return status;
1638
1639         /* Disable Flex from training TXFFE. */
1640         status = ixgbe_read_iosf_sb_reg_x550(hw,
1641                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1642                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1643         if (status != IXGBE_SUCCESS)
1644                 return status;
1645         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1646         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1647         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1648         status = ixgbe_write_iosf_sb_reg_x550(hw,
1649                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1650                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1651         if (status != IXGBE_SUCCESS)
1652                 return status;
1653         status = ixgbe_read_iosf_sb_reg_x550(hw,
1654                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1655                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1656         if (status != IXGBE_SUCCESS)
1657                 return status;
1658         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1659         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1660         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1661         status = ixgbe_write_iosf_sb_reg_x550(hw,
1662                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1663                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1664         if (status != IXGBE_SUCCESS)
1665                 return status;
1666
1667         /* Enable override for coefficients. */
1668         status = ixgbe_read_iosf_sb_reg_x550(hw,
1669                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1670                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1671         if (status != IXGBE_SUCCESS)
1672                 return status;
1673         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1674         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1675         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1676         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1677         status = ixgbe_write_iosf_sb_reg_x550(hw,
1678                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1679                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1680         if (status != IXGBE_SUCCESS)
1681                 return status;
1682
1683         /* Toggle port SW reset by AN reset. */
1684         status = ixgbe_read_iosf_sb_reg_x550(hw,
1685                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1686                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1687         if (status != IXGBE_SUCCESS)
1688                 return status;
1689         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1690         status = ixgbe_write_iosf_sb_reg_x550(hw,
1691                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1692                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1693
1694         return status;
1695 }
1696
1697 /**
1698  *  ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1699  *  @hw: pointer to hardware structure
1700  *
1701  *  Configures the integrated KR PHY for SFP support.
1702  **/
1703 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1704                                     ixgbe_link_speed speed,
1705                                     bool autoneg_wait_to_complete)
1706 {
1707         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1708
1709         return ixgbe_setup_ixfi_x550em(hw, &speed);
1710 }
1711
1712 /**
1713  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1714  * @hw: point to hardware structure
1715  *
1716  * Configures the link between the integrated KR PHY and the external X557 PHY
1717  * The driver will call this function when it gets a link status change
1718  * interrupt from the X557 PHY. This function configures the link speed
1719  * between the PHYs to match the link speed of the BASE-T link.
1720  *
1721  * A return of a non-zero value indicates an error, and the base driver should
1722  * not report link up.
1723  */
1724 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1725 {
1726         u32 status;
1727         u16 autoneg_status, speed;
1728         ixgbe_link_speed force_speed;
1729
1730         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1731                 return IXGBE_ERR_CONFIG;
1732
1733         /* read this twice back to back to indicate current status */
1734         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1735                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1736                                       &autoneg_status);
1737         if (status != IXGBE_SUCCESS)
1738                 return status;
1739
1740         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1741                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1742                                       &autoneg_status);
1743         if (status != IXGBE_SUCCESS)
1744                 return status;
1745
1746         /* If link is not up, then there is no setup necessary so return  */
1747         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1748                 return IXGBE_SUCCESS;
1749
1750         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1751                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1752                                       &speed);
1753
1754         /* clear everything but the speed and duplex bits */
1755         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1756
1757         switch (speed) {
1758         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1759                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1760                 break;
1761         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1762                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1763                 break;
1764         default:
1765                 /* Internal PHY does not support anything else */
1766                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1767         }
1768
1769         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1770 }
1771
1772 /**
1773  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1774  *  @hw: pointer to hardware structure
1775  *
1776  *  Configures the integrated KR PHY to use internal loopback mode.
1777  **/
1778 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1779 {
1780         s32 status;
1781         u32 reg_val;
1782
1783         /* Disable AN and force speed to 10G Serial. */
1784         status = ixgbe_read_iosf_sb_reg_x550(hw,
1785                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1786                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1787         if (status != IXGBE_SUCCESS)
1788                 return status;
1789         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1790         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1791         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1792         status = ixgbe_write_iosf_sb_reg_x550(hw,
1793                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1794                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1795         if (status != IXGBE_SUCCESS)
1796                 return status;
1797
1798         /* Set near-end loopback clocks. */
1799         status = ixgbe_read_iosf_sb_reg_x550(hw,
1800                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1801                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1802         if (status != IXGBE_SUCCESS)
1803                 return status;
1804         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1805         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1806         status = ixgbe_write_iosf_sb_reg_x550(hw,
1807                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1808                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1809         if (status != IXGBE_SUCCESS)
1810                 return status;
1811
1812         /* Set loopback enable. */
1813         status = ixgbe_read_iosf_sb_reg_x550(hw,
1814                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1815                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1816         if (status != IXGBE_SUCCESS)
1817                 return status;
1818         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1819         status = ixgbe_write_iosf_sb_reg_x550(hw,
1820                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1821                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1822         if (status != IXGBE_SUCCESS)
1823                 return status;
1824
1825         /* Training bypass. */
1826         status = ixgbe_read_iosf_sb_reg_x550(hw,
1827                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1828                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1829         if (status != IXGBE_SUCCESS)
1830                 return status;
1831         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1832         status = ixgbe_write_iosf_sb_reg_x550(hw,
1833                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1834                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1835
1836         return status;
1837 }
1838
1839 /**
1840  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1841  *  assuming that the semaphore is already obtained.
1842  *  @hw: pointer to hardware structure
1843  *  @offset: offset of  word in the EEPROM to read
1844  *  @data: word read from the EEPROM
1845  *
1846  *  Reads a 16 bit word from the EEPROM using the hostif.
1847  **/
1848 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1849                                    u16 *data)
1850 {
1851         s32 status;
1852         struct ixgbe_hic_read_shadow_ram buffer;
1853
1854         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1855         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1856         buffer.hdr.req.buf_lenh = 0;
1857         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1858         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1859
1860         /* convert offset from words to bytes */
1861         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1862         /* one word */
1863         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1864
1865         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1866                                               sizeof(buffer),
1867                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1868
1869         if (status)
1870                 return status;
1871
1872         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1873                                           FW_NVM_DATA_OFFSET);
1874
1875         return 0;
1876 }
1877
1878 /**
1879  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1880  *  @hw: pointer to hardware structure
1881  *  @offset: offset of  word in the EEPROM to read
1882  *  @data: word read from the EEPROM
1883  *
1884  *  Reads a 16 bit word from the EEPROM using the hostif.
1885  **/
1886 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1887                               u16 *data)
1888 {
1889         s32 status = IXGBE_SUCCESS;
1890
1891         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1892
1893         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1894             IXGBE_SUCCESS) {
1895                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1896                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1897         } else {
1898                 status = IXGBE_ERR_SWFW_SYNC;
1899         }
1900
1901         return status;
1902 }
1903
1904 /**
1905  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1906  *  @hw: pointer to hardware structure
1907  *  @offset: offset of  word in the EEPROM to read
1908  *  @words: number of words
1909  *  @data: word(s) read from the EEPROM
1910  *
1911  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
1912  **/
1913 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1914                                      u16 offset, u16 words, u16 *data)
1915 {
1916         struct ixgbe_hic_read_shadow_ram buffer;
1917         u32 current_word = 0;
1918         u16 words_to_read;
1919         s32 status;
1920         u32 i;
1921
1922         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1923
1924         /* Take semaphore for the entire operation. */
1925         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1926         if (status) {
1927                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1928                 return status;
1929         }
1930         while (words) {
1931                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1932                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1933                 else
1934                         words_to_read = words;
1935
1936                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1937                 buffer.hdr.req.buf_lenh = 0;
1938                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1939                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1940
1941                 /* convert offset from words to bytes */
1942                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1943                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1944
1945                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1946                                                       sizeof(buffer),
1947                                                       IXGBE_HI_COMMAND_TIMEOUT,
1948                                                       false);
1949
1950                 if (status) {
1951                         DEBUGOUT("Host interface command failed\n");
1952                         goto out;
1953                 }
1954
1955                 for (i = 0; i < words_to_read; i++) {
1956                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1957                                   2 * i;
1958                         u32 value = IXGBE_READ_REG(hw, reg);
1959
1960                         data[current_word] = (u16)(value & 0xffff);
1961                         current_word++;
1962                         i++;
1963                         if (i < words_to_read) {
1964                                 value >>= 16;
1965                                 data[current_word] = (u16)(value & 0xffff);
1966                                 current_word++;
1967                         }
1968                 }
1969                 words -= words_to_read;
1970         }
1971
1972 out:
1973         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1974         return status;
1975 }
1976
1977 /**
1978  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1979  *  @hw: pointer to hardware structure
1980  *  @offset: offset of  word in the EEPROM to write
1981  *  @data: word write to the EEPROM
1982  *
1983  *  Write a 16 bit word to the EEPROM using the hostif.
1984  **/
1985 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1986                                     u16 data)
1987 {
1988         s32 status;
1989         struct ixgbe_hic_write_shadow_ram buffer;
1990
1991         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1992
1993         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1994         buffer.hdr.req.buf_lenh = 0;
1995         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1996         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1997
1998          /* one word */
1999         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2000         buffer.data = data;
2001         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2002
2003         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2004                                               sizeof(buffer),
2005                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2006
2007         return status;
2008 }
2009
2010 /**
2011  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2012  *  @hw: pointer to hardware structure
2013  *  @offset: offset of  word in the EEPROM to write
2014  *  @data: word write to the EEPROM
2015  *
2016  *  Write a 16 bit word to the EEPROM using the hostif.
2017  **/
2018 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2019                                u16 data)
2020 {
2021         s32 status = IXGBE_SUCCESS;
2022
2023         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2024
2025         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2026             IXGBE_SUCCESS) {
2027                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2028                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2029         } else {
2030                 DEBUGOUT("write ee hostif failed to get semaphore");
2031                 status = IXGBE_ERR_SWFW_SYNC;
2032         }
2033
2034         return status;
2035 }
2036
2037 /**
2038  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2039  *  @hw: pointer to hardware structure
2040  *  @offset: offset of  word in the EEPROM to write
2041  *  @words: number of words
2042  *  @data: word(s) write to the EEPROM
2043  *
2044  *  Write a 16 bit word(s) to the EEPROM using the hostif.
2045  **/
2046 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2047                                       u16 offset, u16 words, u16 *data)
2048 {
2049         s32 status = IXGBE_SUCCESS;
2050         u32 i = 0;
2051
2052         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2053
2054         /* Take semaphore for the entire operation. */
2055         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2056         if (status != IXGBE_SUCCESS) {
2057                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2058                 goto out;
2059         }
2060
2061         for (i = 0; i < words; i++) {
2062                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2063                                                          data[i]);
2064
2065                 if (status != IXGBE_SUCCESS) {
2066                         DEBUGOUT("Eeprom buffered write failed\n");
2067                         break;
2068                 }
2069         }
2070
2071         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2072 out:
2073
2074         return status;
2075 }
2076
2077 /**
2078  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2079  * @hw: pointer to hardware structure
2080  * @ptr: pointer offset in eeprom
2081  * @size: size of section pointed by ptr, if 0 first word will be used as size
2082  * @csum: address of checksum to update
2083  *
2084  * Returns error status for any failure
2085  */
2086 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2087                                    u16 size, u16 *csum, u16 *buffer,
2088                                    u32 buffer_size)
2089 {
2090         u16 buf[256];
2091         s32 status;
2092         u16 length, bufsz, i, start;
2093         u16 *local_buffer;
2094
2095         bufsz = sizeof(buf) / sizeof(buf[0]);
2096
2097         /* Read a chunk at the pointer location */
2098         if (!buffer) {
2099                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2100                 if (status) {
2101                         DEBUGOUT("Failed to read EEPROM image\n");
2102                         return status;
2103                 }
2104                 local_buffer = buf;
2105         } else {
2106                 if (buffer_size < ptr)
2107                         return  IXGBE_ERR_PARAM;
2108                 local_buffer = &buffer[ptr];
2109         }
2110
2111         if (size) {
2112                 start = 0;
2113                 length = size;
2114         } else {
2115                 start = 1;
2116                 length = local_buffer[0];
2117
2118                 /* Skip pointer section if length is invalid. */
2119                 if (length == 0xFFFF || length == 0 ||
2120                     (ptr + length) >= hw->eeprom.word_size)
2121                         return IXGBE_SUCCESS;
2122         }
2123
2124         if (buffer && ((u32)start + (u32)length > buffer_size))
2125                 return IXGBE_ERR_PARAM;
2126
2127         for (i = start; length; i++, length--) {
2128                 if (i == bufsz && !buffer) {
2129                         ptr += bufsz;
2130                         i = 0;
2131                         if (length < bufsz)
2132                                 bufsz = length;
2133
2134                         /* Read a chunk at the pointer location */
2135                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2136                                                                   bufsz, buf);
2137                         if (status) {
2138                                 DEBUGOUT("Failed to read EEPROM image\n");
2139                                 return status;
2140                         }
2141                 }
2142                 *csum += local_buffer[i];
2143         }
2144         return IXGBE_SUCCESS;
2145 }
2146
2147 /**
2148  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2149  *  @hw: pointer to hardware structure
2150  *  @buffer: pointer to buffer containing calculated checksum
2151  *  @buffer_size: size of buffer
2152  *
2153  *  Returns a negative error code on error, or the 16-bit checksum
2154  **/
2155 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2156 {
2157         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2158         u16 *local_buffer;
2159         s32 status;
2160         u16 checksum = 0;
2161         u16 pointer, i, size;
2162
2163         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2164
2165         hw->eeprom.ops.init_params(hw);
2166
2167         if (!buffer) {
2168                 /* Read pointer area */
2169                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2170                                                      IXGBE_EEPROM_LAST_WORD + 1,
2171                                                      eeprom_ptrs);
2172                 if (status) {
2173                         DEBUGOUT("Failed to read EEPROM image\n");
2174                         return status;
2175                 }
2176                 local_buffer = eeprom_ptrs;
2177         } else {
2178                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2179                         return IXGBE_ERR_PARAM;
2180                 local_buffer = buffer;
2181         }
2182
2183         /*
2184          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2185          * checksum word itself
2186          */
2187         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2188                 if (i != IXGBE_EEPROM_CHECKSUM)
2189                         checksum += local_buffer[i];
2190
2191         /*
2192          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2193          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2194          */
2195         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2196                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2197                         continue;
2198
2199                 pointer = local_buffer[i];
2200
2201                 /* Skip pointer section if the pointer is invalid. */
2202                 if (pointer == 0xFFFF || pointer == 0 ||
2203                     pointer >= hw->eeprom.word_size)
2204                         continue;
2205
2206                 switch (i) {
2207                 case IXGBE_PCIE_GENERAL_PTR:
2208                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2209                         break;
2210                 case IXGBE_PCIE_CONFIG0_PTR:
2211                 case IXGBE_PCIE_CONFIG1_PTR:
2212                         size = IXGBE_PCIE_CONFIG_SIZE;
2213                         break;
2214                 default:
2215                         size = 0;
2216                         break;
2217                 }
2218
2219                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2220                                                 buffer, buffer_size);
2221                 if (status)
2222                         return status;
2223         }
2224
2225         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2226
2227         return (s32)checksum;
2228 }
2229
2230 /**
2231  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2232  *  @hw: pointer to hardware structure
2233  *
2234  *  Returns a negative error code on error, or the 16-bit checksum
2235  **/
2236 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2237 {
2238         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2239 }
2240
2241 /**
2242  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2243  *  @hw: pointer to hardware structure
2244  *  @checksum_val: calculated checksum
2245  *
2246  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2247  *  caller does not need checksum_val, the value can be NULL.
2248  **/
2249 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2250 {
2251         s32 status;
2252         u16 checksum;
2253         u16 read_checksum = 0;
2254
2255         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2256
2257         /* Read the first word from the EEPROM. If this times out or fails, do
2258          * not continue or we could be in for a very long wait while every
2259          * EEPROM read fails
2260          */
2261         status = hw->eeprom.ops.read(hw, 0, &checksum);
2262         if (status) {
2263                 DEBUGOUT("EEPROM read failed\n");
2264                 return status;
2265         }
2266
2267         status = hw->eeprom.ops.calc_checksum(hw);
2268         if (status < 0)
2269                 return status;
2270
2271         checksum = (u16)(status & 0xffff);
2272
2273         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2274                                            &read_checksum);
2275         if (status)
2276                 return status;
2277
2278         /* Verify read checksum from EEPROM is the same as
2279          * calculated checksum
2280          */
2281         if (read_checksum != checksum) {
2282                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2283                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2284                              "Invalid EEPROM checksum");
2285         }
2286
2287         /* If the user cares, return the calculated checksum */
2288         if (checksum_val)
2289                 *checksum_val = checksum;
2290
2291         return status;
2292 }
2293
2294 /**
2295  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2296  * @hw: pointer to hardware structure
2297  *
2298  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2299  * checksum and updates the EEPROM and instructs the hardware to update
2300  * the flash.
2301  **/
2302 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2303 {
2304         s32 status;
2305         u16 checksum = 0;
2306
2307         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2308
2309         /* Read the first word from the EEPROM. If this times out or fails, do
2310          * not continue or we could be in for a very long wait while every
2311          * EEPROM read fails
2312          */
2313         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2314         if (status) {
2315                 DEBUGOUT("EEPROM read failed\n");
2316                 return status;
2317         }
2318
2319         status = ixgbe_calc_eeprom_checksum_X550(hw);
2320         if (status < 0)
2321                 return status;
2322
2323         checksum = (u16)(status & 0xffff);
2324
2325         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2326                                             checksum);
2327         if (status)
2328                 return status;
2329
2330         status = ixgbe_update_flash_X550(hw);
2331
2332         return status;
2333 }
2334
2335 /**
2336  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2337  *  @hw: pointer to hardware structure
2338  *
2339  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2340  **/
2341 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2342 {
2343         s32 status = IXGBE_SUCCESS;
2344         union ixgbe_hic_hdr2 buffer;
2345
2346         DEBUGFUNC("ixgbe_update_flash_X550");
2347
2348         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2349         buffer.req.buf_lenh = 0;
2350         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2351         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2352
2353         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2354                                               sizeof(buffer),
2355                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2356
2357         return status;
2358 }
2359
2360 /**
2361  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2362  *  @hw: pointer to hardware structure
2363  *
2364  *  Determines physical layer capabilities of the current configuration.
2365  **/
2366 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2367 {
2368         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2369         u16 ext_ability = 0;
2370
2371         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2372
2373         hw->phy.ops.identify(hw);
2374
2375         switch (hw->phy.type) {
2376         case ixgbe_phy_x550em_kr:
2377                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2378                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2379                 break;
2380         case ixgbe_phy_x550em_kx4:
2381                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2382                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2383                 break;
2384         case ixgbe_phy_x550em_ext_t:
2385                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2386                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2387                                      &ext_ability);
2388                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2389                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2390                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2391                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2392                 break;
2393         default:
2394                 break;
2395         }
2396
2397         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2398                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2399
2400         return physical_layer;
2401 }
2402
2403 /**
2404  * ixgbe_get_bus_info_x550em - Set PCI bus info
2405  * @hw: pointer to hardware structure
2406  *
2407  * Sets bus link width and speed to unknown because X550em is
2408  * not a PCI device.
2409  **/
2410 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2411 {
2412
2413         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2414
2415         hw->bus.width = ixgbe_bus_width_unknown;
2416         hw->bus.speed = ixgbe_bus_speed_unknown;
2417
2418         return IXGBE_SUCCESS;
2419 }
2420
2421 /**
2422  * ixgbe_disable_rx_x550 - Disable RX unit
2423  *
2424  * Enables the Rx DMA unit for x550
2425  **/
2426 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2427 {
2428         u32 rxctrl, pfdtxgswc;
2429         s32 status;
2430         struct ixgbe_hic_disable_rxen fw_cmd;
2431
2432         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2433
2434         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2435         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2436                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2437                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2438                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2439                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2440                         hw->mac.set_lben = true;
2441                 } else {
2442                         hw->mac.set_lben = false;
2443                 }
2444
2445                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2446                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2447                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2448                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2449
2450                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2451                                         sizeof(struct ixgbe_hic_disable_rxen),
2452                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2453
2454                 /* If we fail - disable RX using register write */
2455                 if (status) {
2456                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2457                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2458                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2459                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2460                         }
2461                 }
2462         }
2463 }
2464
2465 /**
2466  * ixgbe_enter_lplu_x550em - Transition to low power states
2467  *  @hw: pointer to hardware structure
2468  *
2469  * Configures Low Power Link Up on transition to low power states
2470  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2471  * X557 PHY immediately prior to entering LPLU.
2472  **/
2473 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2474 {
2475         u16 autoneg_status, an_10g_cntl_reg, autoneg_reg, speed;
2476         s32 status;
2477         ixgbe_link_speed lcd_speed;
2478
2479         /* If blocked by MNG FW, then don't restart AN */
2480         if (ixgbe_check_reset_blocked(hw))
2481                 return IXGBE_SUCCESS;
2482
2483         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2484                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2485                                       &autoneg_status);
2486
2487         if (status != IXGBE_SUCCESS)
2488                 return status;
2489
2490         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2491
2492         if (status != IXGBE_SUCCESS)
2493                 return status;
2494
2495         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2496          * disabled, then force link down by entering low power mode.
2497          */
2498         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS) ||
2499             !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2500             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2501                 return ixgbe_set_copper_phy_power(hw, FALSE);
2502
2503         /* Determine LCD */
2504         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2505
2506         if (status != IXGBE_SUCCESS)
2507                 return status;
2508
2509         /* If no valid LCD link speed, then force link down and exit. */
2510         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2511                 return ixgbe_set_copper_phy_power(hw, FALSE);
2512
2513         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2514                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2515                                       &speed);
2516
2517         if (status != IXGBE_SUCCESS)
2518                 return status;
2519
2520         /* clear everything but the speed bits */
2521         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2522
2523         /* If current speed is already LCD, then exit. */
2524         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2525              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2526             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2527              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2528                 return status;
2529
2530         /* Clear AN completed indication */
2531         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2532                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2533                                       &autoneg_status);
2534
2535         if (status != IXGBE_SUCCESS)
2536                 return status;
2537
2538         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2539                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2540                              &an_10g_cntl_reg);
2541
2542         if (status != IXGBE_SUCCESS)
2543                 return status;
2544
2545         status = hw->phy.ops.read_reg(hw,
2546                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2547                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2548                              &autoneg_reg);
2549
2550         if (status != IXGBE_SUCCESS)
2551                 return status;
2552
2553         /* Set AN advertizement to only include LCD  */
2554         if (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL) {
2555                 an_10g_cntl_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
2556                 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
2557         }
2558
2559         if (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL) {
2560                 an_10g_cntl_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
2561                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
2562         }
2563
2564         status = hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2565                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2566                               an_10g_cntl_reg);
2567
2568         if (status != IXGBE_SUCCESS)
2569                 return status;
2570
2571         status = hw->phy.ops.write_reg(hw,
2572                               IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2573                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2574                               autoneg_reg);
2575
2576         if (status != IXGBE_SUCCESS)
2577                 return status;
2578
2579         /* Restart PHY auto-negotiation. */
2580         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
2581                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
2582
2583         if (status != IXGBE_SUCCESS)
2584                 return status;
2585
2586         autoneg_reg |= IXGBE_MII_RESTART;
2587
2588         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
2589                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
2590
2591         if (status != IXGBE_SUCCESS)
2592                 return status;
2593
2594         status = ixgbe_setup_ixfi_x550em(hw, &lcd_speed);
2595
2596         return status;
2597 }
2598
2599 /**
2600  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2601  *  @hw: pointer to hardware structure
2602  *  @lcd_speed: pointer to lowest common link speed
2603  *
2604  * Determine lowest common link speed with link partner.
2605  **/
2606 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2607 {
2608         u16 an_lp_status;
2609         s32 status;
2610         u16 word = hw->eeprom.ctrl_word_3;
2611
2612         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2613
2614         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2615                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2616                                       &an_lp_status);
2617
2618         if (status != IXGBE_SUCCESS)
2619                 return status;
2620
2621         /* If link partner advertised 1G, return 1G */
2622         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2623                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2624                 return status;
2625         }
2626
2627         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2628         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2629             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2630                 return status;
2631
2632         /* Link partner not capable of lower speeds, return 10G */
2633         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2634         return status;
2635 }
2636
2637 /**
2638  *  ixgbe_setup_fc_X550em - Set up flow control
2639  *  @hw: pointer to hardware structure
2640  *
2641  *  Called at init time to set up flow control.
2642  **/
2643 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2644 {
2645         s32 ret_val = IXGBE_SUCCESS;
2646         u32 pause, asm_dir, reg_val;
2647
2648         DEBUGFUNC("ixgbe_setup_fc_X550em");
2649
2650         /* Validate the requested mode */
2651         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2652                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2653                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2654                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2655                 goto out;
2656         }
2657
2658         /* 10gig parts do not have a word in the EEPROM to determine the
2659          * default flow control setting, so we explicitly set it to full.
2660          */
2661         if (hw->fc.requested_mode == ixgbe_fc_default)
2662                 hw->fc.requested_mode = ixgbe_fc_full;
2663
2664         /* Determine PAUSE and ASM_DIR bits. */
2665         switch (hw->fc.requested_mode) {
2666         case ixgbe_fc_none:
2667                 pause = 0;
2668                 asm_dir = 0;
2669                 break;
2670         case ixgbe_fc_tx_pause:
2671                 pause = 0;
2672                 asm_dir = 1;
2673                 break;
2674         case ixgbe_fc_rx_pause:
2675                 /* Rx Flow control is enabled and Tx Flow control is
2676                  * disabled by software override. Since there really
2677                  * isn't a way to advertise that we are capable of RX
2678                  * Pause ONLY, we will advertise that we support both
2679                  * symmetric and asymmetric Rx PAUSE, as such we fall
2680                  * through to the fc_full statement.  Later, we will
2681                  * disable the adapter's ability to send PAUSE frames.
2682                  */
2683         case ixgbe_fc_full:
2684                 pause = 1;
2685                 asm_dir = 1;
2686                 break;
2687         default:
2688                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2689                         "Flow control param set incorrectly\n");
2690                 ret_val = IXGBE_ERR_CONFIG;
2691                 goto out;
2692         }
2693
2694         if (hw->phy.media_type == ixgbe_media_type_backplane) {
2695                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2696                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2697                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2698                 if (ret_val != IXGBE_SUCCESS)
2699                         goto out;
2700                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2701                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2702                 if (pause)
2703                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2704                 if (asm_dir)
2705                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2706                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2707                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2708                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2709
2710                 /* Not all devices fully support AN. */
2711                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR)
2712                         hw->fc.disable_fc_autoneg = true;
2713         }
2714
2715 out:
2716         return ret_val;
2717 }
2718
2719 /**
2720  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2721  * @hw: pointer to hardware structure
2722  * @state: set mux if 1, clear if 0
2723  */
2724 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2725 {
2726         u32 esdp;
2727
2728         if (!hw->bus.lan_id)
2729                 return;
2730         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2731         if (state)
2732                 esdp |= IXGBE_ESDP_SDP1;
2733         else
2734                 esdp &= ~IXGBE_ESDP_SDP1;
2735         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2736         IXGBE_WRITE_FLUSH(hw);
2737 }
2738
2739 /**
2740  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2741  *  @hw: pointer to hardware structure
2742  *  @mask: Mask to specify which semaphore to acquire
2743  *
2744  *  Acquires the SWFW semaphore and sets the I2C MUX
2745  **/
2746 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2747 {
2748         s32 status;
2749
2750         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2751
2752         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2753         if (status)
2754                 return status;
2755
2756         if (mask & IXGBE_GSSR_I2C_MASK)
2757                 ixgbe_set_mux(hw, 1);
2758
2759         return IXGBE_SUCCESS;
2760 }
2761
2762 /**
2763  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2764  *  @hw: pointer to hardware structure
2765  *  @mask: Mask to specify which semaphore to release
2766  *
2767  *  Releases the SWFW semaphore and sets the I2C MUX
2768  **/
2769 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2770 {
2771         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2772
2773         if (mask & IXGBE_GSSR_I2C_MASK)
2774                 ixgbe_set_mux(hw, 0);
2775
2776         ixgbe_release_swfw_sync_X540(hw, mask);
2777 }
2778
2779 /**
2780  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2781  * @hw: pointer to hardware structure
2782  *
2783  * Handle external Base T PHY interrupt. If high temperature
2784  * failure alarm then return error, else if link status change
2785  * then setup internal/external PHY link
2786  *
2787  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2788  * failure alarm, else return PHY access status.
2789  */
2790 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2791 {
2792         bool lsc;
2793         u32 status;
2794
2795         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2796
2797         if (status != IXGBE_SUCCESS)
2798                 return status;
2799
2800         if (lsc)
2801                 return ixgbe_setup_internal_phy_t_x550em(hw);
2802
2803         return IXGBE_SUCCESS;
2804 }
2805
2806 /**
2807  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
2808  * @hw: pointer to hardware structure
2809  * @speed: new link speed
2810  * @autoneg_wait_to_complete: true when waiting for completion is needed
2811  *
2812  * Setup internal/external PHY link speed based on link speed, then set
2813  * external PHY auto advertised link speed.
2814  *
2815  * Returns error status for any failure
2816  **/
2817 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
2818                                   ixgbe_link_speed speed,
2819                                   bool autoneg_wait_to_complete)
2820 {
2821         s32 status;
2822         ixgbe_link_speed force_speed;
2823
2824         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
2825
2826         /* Setup internal/external PHY link speed to iXFI (10G), unless
2827          * only 1G is auto advertised then setup KX link.
2828          */
2829         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2830                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2831         else
2832                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2833
2834         status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
2835
2836         if (status != IXGBE_SUCCESS)
2837                 return status;
2838
2839         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
2840 }