drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42
  43 /**
  44  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  45  *  @hw: pointer to hardware structure
  46  *
  47  *  Initialize the function pointers and assign the MAC type for X550.
  48  *  Does not touch the hardware.
  49  **/
  50 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  51 {
  52         struct ixgbe_mac_info *mac = &hw->mac;
  53         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  54         s32 ret_val;
  55
  56         DEBUGFUNC("ixgbe_init_ops_X550");
  57
  58         ret_val = ixgbe_init_ops_X540(hw);
  59         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  60         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  61         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  62         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  63         mac->ops.set_source_address_pruning =
  64                         ixgbe_set_source_address_pruning_X550;
  65         mac->ops.set_ethertype_anti_spoofing =
  66                         ixgbe_set_ethertype_anti_spoofing_X550;
  67
  68         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  69         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  70         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  71         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  72         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  73         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  74         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  75         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  76         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  77
  78         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  79         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  80         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  81         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  82         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  83         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
  84                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  85                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  86         }
  87         return ret_val;
  88 }
  89
  90 /**
  91  * ixgbe_read_cs4227 - Read CS4227 register
  92  * @hw: pointer to hardware structure
  93  * @reg: register number to write
  94  * @value: pointer to receive value read
  95  *
  96  * Returns status code
  97  **/
  98 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  99 {
 100         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 101 }
 102
 103 /**
 104  * ixgbe_write_cs4227 - Write CS4227 register
 105  * @hw: pointer to hardware structure
 106  * @reg: register number to write
 107  * @value: value to write to register
 108  *
 109  * Returns status code
 110  **/
 111 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 112 {
 113         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 114 }
 115
 116 /**
 117  * ixgbe_get_cs4227_status - Return CS4227 status
 118  * @hw: pointer to hardware structure
 119  *
 120  * Returns error if CS4227 not successfully initialized
 121  **/
 122 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
 123 {
 124         s32 status;
 125         u16 value = 0;
 126         u16 reg_slice, reg_val;
 127         u8 retry;
 128
 129         for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
 130                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
 131                                            &value);
 132                 if (status != IXGBE_SUCCESS)
 133                         return status;
 134                 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
 135                         break;
 136                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 137         }
 138         if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
 139                 return IXGBE_ERR_PHY;
 140
 141         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 142         if (status != IXGBE_SUCCESS)
 143                 return status;
 144
 145         /* If this is the first time after power-on, check the ucode.
 146          * Otherwise, this will disrupt link on all ports. Because we
 147          * can only do this the first time, we must check all ports,
 148          * not just our own.
 149          */
 150         if (value != IXGBE_CS4227_SCRATCH_VALUE) {
 151                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB;
 152                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
 153                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 154                 if (status != IXGBE_SUCCESS)
 155                         return status;
 156
 157                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB;
 158                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
 159                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 160                 if (status != IXGBE_SUCCESS)
 161                         return status;
 162
 163                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12);
 164                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
 165                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 166                 if (status != IXGBE_SUCCESS)
 167                         return status;
 168
 169                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12);
 170                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
 171                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 172                 if (status != IXGBE_SUCCESS)
 173                         return status;
 174
 175                 msec_delay(10);
 176         }
 177
 178         /* Verify that the ucode is operational on all ports. */
 179         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB;
 180         reg_val = 0xFFFF;
 181         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 182         if (status != IXGBE_SUCCESS)
 183                 return status;
 184         if (reg_val != 0)
 185                 return IXGBE_ERR_PHY;
 186
 187         reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB;
 188         reg_val = 0xFFFF;
 189         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 190         if (status != IXGBE_SUCCESS)
 191                 return status;
 192         if (reg_val != 0)
 193                 return IXGBE_ERR_PHY;
 194
 195         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12);
 196         reg_val = 0xFFFF;
 197         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 198         if (status != IXGBE_SUCCESS)
 199                 return status;
 200         if (reg_val != 0)
 201                 return IXGBE_ERR_PHY;
 202
 203         reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12);
 204         reg_val = 0xFFFF;
 205         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 206         if (status != IXGBE_SUCCESS)
 207                 return status;
 208         if (reg_val != 0)
 209                 return IXGBE_ERR_PHY;
 210
 211         /* Set scratch indicating that the diagnostic was successful. */
 212         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 213                                     IXGBE_CS4227_SCRATCH_VALUE);
 214         if (status != IXGBE_SUCCESS)
 215                 return status;
 216         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 217         if (status != IXGBE_SUCCESS)
 218                 return status;
 219         if (value != IXGBE_CS4227_SCRATCH_VALUE)
 220                 return IXGBE_ERR_PHY;
 221
 222         return IXGBE_SUCCESS;
 223 }
 224
 225 /**
 226  * ixgbe_read_pe - Read register from port expander
 227  * @hw: pointer to hardware structure
 228  * @reg: register number to read
 229  * @value: pointer to receive read value
 230  *
 231  * Returns status code
 232  **/
 233 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 234 {
 235         s32 status;
 236
 237         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 238         if (status != IXGBE_SUCCESS)
 239                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 240                               "port expander access failed with %d\n", status);
 241         return status;
 242 }
 243
 244 /**
 245  * ixgbe_write_pe - Write register to port expander
 246  * @hw: pointer to hardware structure
 247  * @reg: register number to write
 248  * @value: value to write
 249  *
 250  * Returns status code
 251  **/
 252 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 253 {
 254         s32 status;
 255
 256         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 257         if (status != IXGBE_SUCCESS)
 258                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 259                               "port expander access failed with %d\n", status);
 260         return status;
 261 }
 262
 263 /**
 264  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 265  * @hw: pointer to hardware structure
 266  *
 267  * Returns error code
 268  **/
 269 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 270 {
 271         s32 status;
 272         u8 reg;
 273
 274         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 275         if (status != IXGBE_SUCCESS)
 276                 return status;
 277         reg |= IXGBE_PE_BIT1;
 278         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 279         if (status != IXGBE_SUCCESS)
 280                 return status;
 281
 282         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 283         if (status != IXGBE_SUCCESS)
 284                 return status;
 285         reg &= ~IXGBE_PE_BIT1;
 286         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 287         if (status != IXGBE_SUCCESS)
 288                 return status;
 289
 290         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 291         if (status != IXGBE_SUCCESS)
 292                 return status;
 293         reg &= ~IXGBE_PE_BIT1;
 294         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 295         if (status != IXGBE_SUCCESS)
 296                 return status;
 297
 298         usec_delay(IXGBE_CS4227_RESET_HOLD);
 299
 300         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 301         if (status != IXGBE_SUCCESS)
 302                 return status;
 303         reg |= IXGBE_PE_BIT1;
 304         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 305         if (status != IXGBE_SUCCESS)
 306                 return status;
 307
 308         msec_delay(IXGBE_CS4227_RESET_DELAY);
 309
 310         return IXGBE_SUCCESS;
 311 }
 312
 313 /**
 314  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 315  * @hw: pointer to hardware structure
 316  **/
 317 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 318 {
 319         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 320         s32 status;
 321         u8 retry;
 322
 323         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 324                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 325                 if (status != IXGBE_SUCCESS) {
 326                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 327                                       "semaphore failed with %d\n", status);
 328                         return;
 329                 }
 330                 status = ixgbe_get_cs4227_status(hw);
 331                 if (status == IXGBE_SUCCESS) {
 332                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 333                         msec_delay(hw->eeprom.semaphore_delay);
 334                         return;
 335                 }
 336                 ixgbe_reset_cs4227(hw);
 337                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 338                 msec_delay(hw->eeprom.semaphore_delay);
 339         }
 340         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 341                       "Unable to initialize CS4227, err=%d\n", status);
 342 }
 343
 344 /**
 345  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 346  * @hw: pointer to hardware structure
 347  **/
 348 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 349 {
 350         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 351
 352         if (hw->bus.lan_id) {
 353                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 354                 esdp |= IXGBE_ESDP_SDP1_DIR;
 355         }
 356         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 357         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 358         IXGBE_WRITE_FLUSH(hw);
 359 }
 360
 361 /**
 362  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 363  * @hw: pointer to hardware structure
 364  *
 365  * Returns error code
 366  */
 367 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 368 {
 369         switch (hw->device_id) {
 370         case IXGBE_DEV_ID_X550EM_X_SFP:
 371                 /* set up for CS4227 usage */
 372                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 373                 ixgbe_setup_mux_ctl(hw);
 374                 ixgbe_check_cs4227(hw);
 375
 376                 return ixgbe_identify_module_generic(hw);
 377                 break;
 378         case IXGBE_DEV_ID_X550EM_X_KX4:
 379                 hw->phy.type = ixgbe_phy_x550em_kx4;
 380                 break;
 381         case IXGBE_DEV_ID_X550EM_X_KR:
 382                 hw->phy.type = ixgbe_phy_x550em_kr;
 383                 break;
 384         case IXGBE_DEV_ID_X550EM_X_1G_T:
 385         case IXGBE_DEV_ID_X550EM_X_10G_T:
 386                 return ixgbe_identify_phy_generic(hw);
 387         default:
 388                 break;
 389         }
 390         return IXGBE_SUCCESS;
 391 }
 392
 393 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 394                                      u32 device_type, u16 *phy_data)
 395 {
 396         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 397         return IXGBE_NOT_IMPLEMENTED;
 398 }
 399
 400 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 401                                       u32 device_type, u16 phy_data)
 402 {
 403         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 404         return IXGBE_NOT_IMPLEMENTED;
 405 }
 406
 407 /**
 408 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 409 *  @hw: pointer to hardware structure
 410 *
 411 *  Initialize the function pointers and for MAC type X550EM.
 412 *  Does not touch the hardware.
 413 **/
 414 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 415 {
 416         struct ixgbe_mac_info *mac = &hw->mac;
 417         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 418         struct ixgbe_phy_info *phy = &hw->phy;
 419         s32 ret_val;
 420
 421         DEBUGFUNC("ixgbe_init_ops_X550EM");
 422
 423         /* Similar to X550 so start there. */
 424         ret_val = ixgbe_init_ops_X550(hw);
 425
 426         /* Since this function eventually calls
 427          * ixgbe_init_ops_540 by design, we are setting
 428          * the pointers to NULL explicitly here to overwrite
 429          * the values being set in the x540 function.
 430          */
 431         /* Thermal sensor not supported in x550EM */
 432         mac->ops.get_thermal_sensor_data = NULL;
 433         mac->ops.init_thermal_sensor_thresh = NULL;
 434         mac->thermal_sensor_enabled = false;
 435
 436         /* FCOE not supported in x550EM */
 437         mac->ops.get_san_mac_addr = NULL;
 438         mac->ops.set_san_mac_addr = NULL;
 439         mac->ops.get_wwn_prefix = NULL;
 440         mac->ops.get_fcoe_boot_status = NULL;
 441
 442         /* IPsec not supported in x550EM */
 443         mac->ops.disable_sec_rx_path = NULL;
 444         mac->ops.enable_sec_rx_path = NULL;
 445
 446         /* AUTOC register is not present in x550EM. */
 447         mac->ops.prot_autoc_read = NULL;
 448         mac->ops.prot_autoc_write = NULL;
 449
 450         /* X550EM bus type is internal*/
 451         hw->bus.type = ixgbe_bus_type_internal;
 452         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 453
 454         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 455         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 456         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 457         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 458         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 459         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 460         mac->ops.get_supported_physical_layer =
 461                                     ixgbe_get_supported_physical_layer_X550em;
 462
 463         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 464                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 465         else
 466                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 467
 468         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 469         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 470
 471         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
 472                 mac->ops.setup_eee = NULL;
 473
 474         /* PHY */
 475         phy->ops.init = ixgbe_init_phy_ops_X550em;
 476         phy->ops.identify = ixgbe_identify_phy_x550em;
 477         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 478                 phy->ops.set_phy_power = NULL;
 479
 480
 481         /* EEPROM */
 482         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 483         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 484         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 485         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 486         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 487         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 488         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 489         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 490
 491         return ret_val;
 492 }
 493
 494 /**
 495  *  ixgbe_dmac_config_X550
 496  *  @hw: pointer to hardware structure
 497  *
 498  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 499  *  When disabling dmac, dmac enable dmac bit is cleared.
 500  **/
 501 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 502 {
 503         u32 reg, high_pri_tc;
 504
 505         DEBUGFUNC("ixgbe_dmac_config_X550");
 506
 507         /* Disable DMA coalescing before configuring */
 508         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 509         reg &= ~IXGBE_DMACR_DMAC_EN;
 510         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 511
 512         /* Disable DMA Coalescing if the watchdog timer is 0 */
 513         if (!hw->mac.dmac_config.watchdog_timer)
 514                 goto out;
 515
 516         ixgbe_dmac_config_tcs_X550(hw);
 517
 518         /* Configure DMA Coalescing Control Register */
 519         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 520
 521         /* Set the watchdog timer in units of 40.96 usec */
 522         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 523         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 524
 525         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 526         /* If fcoe is enabled, set high priority traffic class */
 527         if (hw->mac.dmac_config.fcoe_en) {
 528                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 529                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 530                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 531         }
 532         reg |= IXGBE_DMACR_EN_MNG_IND;
 533
 534         /* Enable DMA coalescing after configuration */
 535         reg |= IXGBE_DMACR_DMAC_EN;
 536         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 537
 538 out:
 539         return IXGBE_SUCCESS;
 540 }
 541
 542 /**
 543  *  ixgbe_dmac_config_tcs_X550
 544  *  @hw: pointer to hardware structure
 545  *
 546  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 547  *  be cleared before configuring.
 548  **/
 549 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 550 {
 551         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 552
 553         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 554
 555         /* Configure DMA coalescing enabled */
 556         switch (hw->mac.dmac_config.link_speed) {
 557         case IXGBE_LINK_SPEED_100_FULL:
 558                 pb_headroom = IXGBE_DMACRXT_100M;
 559                 break;
 560         case IXGBE_LINK_SPEED_1GB_FULL:
 561                 pb_headroom = IXGBE_DMACRXT_1G;
 562                 break;
 563         default:
 564                 pb_headroom = IXGBE_DMACRXT_10G;
 565                 break;
 566         }
 567
 568         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 569                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 570
 571         /* Set the per Rx packet buffer receive threshold */
 572         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 573                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 574                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 575
 576                 if (tc < hw->mac.dmac_config.num_tcs) {
 577                         /* Get Rx PB size */
 578                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 579                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 580                                 IXGBE_RXPBSIZE_SHIFT;
 581
 582                         /* Calculate receive buffer threshold in kilobytes */
 583                         if (rx_pb_size > pb_headroom)
 584                                 rx_pb_size = rx_pb_size - pb_headroom;
 585                         else
 586                                 rx_pb_size = 0;
 587
 588                         /* Minimum of MFS shall be set for DMCTH */
 589                         reg |= (rx_pb_size > maxframe_size_kb) ?
 590                                 rx_pb_size : maxframe_size_kb;
 591                 }
 592                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 593         }
 594         return IXGBE_SUCCESS;
 595 }
 596
 597 /**
 598  *  ixgbe_dmac_update_tcs_X550
 599  *  @hw: pointer to hardware structure
 600  *
 601  *  Disables dmac, updates per TC settings, and then enables dmac.
 602  **/
 603 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 604 {
 605         u32 reg;
 606
 607         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 608
 609         /* Disable DMA coalescing before configuring */
 610         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 611         reg &= ~IXGBE_DMACR_DMAC_EN;
 612         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 613
 614         ixgbe_dmac_config_tcs_X550(hw);
 615
 616         /* Enable DMA coalescing after configuration */
 617         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 618         reg |= IXGBE_DMACR_DMAC_EN;
 619         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 620
 621         return IXGBE_SUCCESS;
 622 }
 623
 624 /**
 625  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 626  *  @hw: pointer to hardware structure
 627  *
 628  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 629  *  ixgbe_hw struct in order to set up EEPROM access.
 630  **/
 631 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 632 {
 633         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 634         u32 eec;
 635         u16 eeprom_size;
 636
 637         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 638
 639         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 640                 eeprom->semaphore_delay = 10;
 641                 eeprom->type = ixgbe_flash;
 642
 643                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 644                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 645                                     IXGBE_EEC_SIZE_SHIFT);
 646                 eeprom->word_size = 1 << (eeprom_size +
 647                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 648
 649                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 650                           eeprom->type, eeprom->word_size);
 651         }
 652
 653         return IXGBE_SUCCESS;
 654 }
 655
 656 /**
 657  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 658  *  @hw: pointer to the HW structure
 659  *  @enable_eee: boolean flag to enable EEE
 660  *
 661  *  Enable/disable EEE based on enable_eee flag.
 662  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 663  *  are modified.
 664  *
 665  **/
 666 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 667 {
 668         u32 eeer;
 669         u16 autoneg_eee_reg;
 670         u32 link_reg;
 671         s32 status;
 672         u32 fuse;
 673
 674         DEBUGFUNC("ixgbe_setup_eee_X550");
 675
 676         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 677         /* Enable or disable EEE per flag */
 678         if (enable_eee) {
 679                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 680
 681                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 682                         /* Advertise EEE capability */
 683                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 684                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 685
 686                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 687                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 688                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 689
 690                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 691                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 692                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 693                         /* Not supported on first revision. */
 694                         fuse = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
 695                         if (!(fuse & IXGBE_FUSES0_REV1))
 696                                 return IXGBE_SUCCESS;
 697
 698                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 699                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 700                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 701                         if (status != IXGBE_SUCCESS)
 702                                 return status;
 703
 704                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 705                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 706
 707                         /* Don't advertise FEC capability when EEE enabled. */
 708                         link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 709
 710                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 711                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 712                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 713                         if (status != IXGBE_SUCCESS)
 714                                 return status;
 715                 }
 716         } else {
 717                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 718
 719                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 720                         /* Disable advertised EEE capability */
 721                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 722                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 723
 724                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 725                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 726                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 727
 728                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 729                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 730                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 731                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 732                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 733                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 734                         if (status != IXGBE_SUCCESS)
 735                                 return status;
 736
 737                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 738                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 739
 740                         /* Advertise FEC capability when EEE is disabled. */
 741                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 742
 743                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 744                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 745                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 746                         if (status != IXGBE_SUCCESS)
 747                                 return status;
 748                 }
 749         }
 750         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 751
 752         return IXGBE_SUCCESS;
 753 }
 754
 755 /**
 756  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 757  * @hw: pointer to hardware structure
 758  * @enable: enable or disable source address pruning
 759  * @pool: Rx pool to set source address pruning for
 760  **/
 761 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 762                                            unsigned int pool)
 763 {
 764         u64 pfflp;
 765
 766         /* max rx pool is 63 */
 767         if (pool > 63)
 768                 return;
 769
 770         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 771         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 772
 773         if (enable)
 774                 pfflp |= (1ULL << pool);
 775         else
 776                 pfflp &= ~(1ULL << pool);
 777
 778         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 779         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 780 }
 781
 782 /**
 783  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 784  *  @hw: pointer to hardware structure
 785  *  @enable: enable or disable switch for Ethertype anti-spoofing
 786  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 787  *
 788  **/
 789 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 790                 bool enable, int vf)
 791 {
 792         int vf_target_reg = vf >> 3;
 793         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 794         u32 pfvfspoof;
 795
 796         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 797
 798         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 799         if (enable)
 800                 pfvfspoof |= (1 << vf_target_shift);
 801         else
 802                 pfvfspoof &= ~(1 << vf_target_shift);
 803
 804         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 805 }
 806
 807 /**
 808  * ixgbe_iosf_wait - Wait for IOSF command completion
 809  * @hw: pointer to hardware structure
 810  * @ctrl: pointer to location to receive final IOSF control value
 811  *
 812  * Returns failing status on timeout
 813  *
 814  * Note: ctrl can be NULL if the IOSF control register value is not needed
 815  **/
 816 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 817 {
 818         u32 i, command = 0;
 819
 820         /* Check every 10 usec to see if the address cycle completed.
 821          * The SB IOSF BUSY bit will clear when the operation is
 822          * complete
 823          */
 824         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 825                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 826                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 827                         break;
 828                 usec_delay(10);
 829         }
 830         if (ctrl)
 831                 *ctrl = command;
 832         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 833                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
 834                 return IXGBE_ERR_PHY;
 835         }
 836
 837         return IXGBE_SUCCESS;
 838 }
 839
 840 /**
 841  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 842  *  device
 843  *  @hw: pointer to hardware structure
 844  *  @reg_addr: 32 bit PHY register to write
 845  *  @device_type: 3 bit device type
 846  *  @data: Data to write to the register
 847  **/
 848 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 849                             u32 device_type, u32 data)
 850 {
 851         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 852         u32 command, error;
 853         s32 ret;
 854
 855         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 856         if (ret != IXGBE_SUCCESS)
 857                 return ret;
 858
 859         ret = ixgbe_iosf_wait(hw, NULL);
 860         if (ret != IXGBE_SUCCESS)
 861                 goto out;
 862
 863         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 864                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 865
 866         /* Write IOSF control register */
 867         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 868
 869         /* Write IOSF data register */
 870         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 871
 872         ret = ixgbe_iosf_wait(hw, &command);
 873
 874         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 875                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 876                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 877                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 878                               "Failed to write, error %x\n", error);
 879                 ret = IXGBE_ERR_PHY;
 880         }
 881
 882 out:
 883         ixgbe_release_swfw_semaphore(hw, gssr);
 884         return ret;
 885 }
 886
 887 /**
 888  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 889  *  device
 890  *  @hw: pointer to hardware structure
 891  *  @reg_addr: 32 bit PHY register to write
 892  *  @device_type: 3 bit device type
 893  *  @phy_data: Pointer to read data from the register
 894  **/
 895 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 896                            u32 device_type, u32 *data)
 897 {
 898         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 899         u32 command, error;
 900         s32 ret;
 901
 902         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 903         if (ret != IXGBE_SUCCESS)
 904                 return ret;
 905
 906         ret = ixgbe_iosf_wait(hw, NULL);
 907         if (ret != IXGBE_SUCCESS)
 908                 goto out;
 909
 910         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 911                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 912
 913         /* Write IOSF control register */
 914         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 915
 916         ret = ixgbe_iosf_wait(hw, &command);
 917
 918         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 919                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 920                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 921                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 922                                 "Failed to read, error %x\n", error);
 923                 ret = IXGBE_ERR_PHY;
 924         }
 925
 926         if (ret == IXGBE_SUCCESS)
 927                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 928
 929 out:
 930         ixgbe_release_swfw_semaphore(hw, gssr);
 931         return ret;
 932 }
 933
 934 /**
 935  *  ixgbe_disable_mdd_X550
 936  *  @hw: pointer to hardware structure
 937  *
 938  *  Disable malicious driver detection
 939  **/
 940 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 941 {
 942         u32 reg;
 943
 944         DEBUGFUNC("ixgbe_disable_mdd_X550");
 945
 946         /* Disable MDD for TX DMA and interrupt */
 947         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 948         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 949         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 950
 951         /* Disable MDD for RX and interrupt */
 952         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 953         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 954         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 955 }
 956
 957 /**
 958  *  ixgbe_enable_mdd_X550
 959  *  @hw: pointer to hardware structure
 960  *
 961  *  Enable malicious driver detection
 962  **/
 963 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 964 {
 965         u32 reg;
 966
 967         DEBUGFUNC("ixgbe_enable_mdd_X550");
 968
 969         /* Enable MDD for TX DMA and interrupt */
 970         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 971         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 972         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 973
 974         /* Enable MDD for RX and interrupt */
 975         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 976         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 977         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 978 }
 979
 980 /**
 981  *  ixgbe_restore_mdd_vf_X550
 982  *  @hw: pointer to hardware structure
 983  *  @vf: vf index
 984  *
 985  *  Restore VF that was disabled during malicious driver detection event
 986  **/
 987 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 988 {
 989         u32 idx, reg, num_qs, start_q, bitmask;
 990
 991         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 992
 993         /* Map VF to queues */
 994         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 995         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 996         case IXGBE_MRQC_VMDQRT8TCEN:
 997                 num_qs = 8;  /* 16 VFs / pools */
 998                 bitmask = 0x000000FF;
 999                 break;
1000         case IXGBE_MRQC_VMDQRSS32EN:
1001         case IXGBE_MRQC_VMDQRT4TCEN:
1002                 num_qs = 4;  /* 32 VFs / pools */
1003                 bitmask = 0x0000000F;
1004                 break;
1005         default:            /* 64 VFs / pools */
1006                 num_qs = 2;
1007                 bitmask = 0x00000003;
1008                 break;
1009         }
1010         start_q = vf * num_qs;
1011
1012         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1013         idx = start_q / 32;
1014         reg = 0;
1015         reg |= (bitmask << (start_q % 32));
1016         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1017         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1018 }
1019
1020 /**
1021  *  ixgbe_mdd_event_X550
1022  *  @hw: pointer to hardware structure
1023  *  @vf_bitmap: vf bitmap of malicious vfs
1024  *
1025  *  Handle malicious driver detection event.
1026  **/
1027 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1028 {
1029         u32 wqbr;
1030         u32 i, j, reg, q, shift, vf, idx;
1031
1032         DEBUGFUNC("ixgbe_mdd_event_X550");
1033
1034         /* figure out pool size for mapping to vf's */
1035         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1036         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1037         case IXGBE_MRQC_VMDQRT8TCEN:
1038                 shift = 3;  /* 16 VFs / pools */
1039                 break;
1040         case IXGBE_MRQC_VMDQRSS32EN:
1041         case IXGBE_MRQC_VMDQRT4TCEN:
1042                 shift = 2;  /* 32 VFs / pools */
1043                 break;
1044         default:
1045                 shift = 1;  /* 64 VFs / pools */
1046                 break;
1047         }
1048
1049         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1050         for (i = 0; i < 4; i++) {
1051                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1052                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1053
1054                 if (!wqbr)
1055                         continue;
1056
1057                 /* Get malicious queue */
1058                 for (j = 0; j < 32 && wqbr; j++) {
1059
1060                         if (!(wqbr & (1 << j)))
1061                                 continue;
1062
1063                         /* Get queue from bitmask */
1064                         q = j + (i * 32);
1065
1066                         /* Map queue to vf */
1067                         vf = (q >> shift);
1068
1069                         /* Set vf bit in vf_bitmap */
1070                         idx = vf / 32;
1071                         vf_bitmap[idx] |= (1 << (vf % 32));
1072                         wqbr &= ~(1 << j);
1073                 }
1074         }
1075 }
1076
1077 /**
1078  *  ixgbe_get_media_type_X550em - Get media type
1079  *  @hw: pointer to hardware structure
1080  *
1081  *  Returns the media type (fiber, copper, backplane)
1082  */
1083 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1084 {
1085         enum ixgbe_media_type media_type;
1086
1087         DEBUGFUNC("ixgbe_get_media_type_X550em");
1088
1089         /* Detect if there is a copper PHY attached. */
1090         switch (hw->device_id) {
1091         case IXGBE_DEV_ID_X550EM_X_KR:
1092         case IXGBE_DEV_ID_X550EM_X_KX4:
1093                 media_type = ixgbe_media_type_backplane;
1094                 break;
1095         case IXGBE_DEV_ID_X550EM_X_SFP:
1096                 media_type = ixgbe_media_type_fiber;
1097                 break;
1098         case IXGBE_DEV_ID_X550EM_X_1G_T:
1099         case IXGBE_DEV_ID_X550EM_X_10G_T:
1100                 media_type = ixgbe_media_type_copper;
1101                 break;
1102         default:
1103                 media_type = ixgbe_media_type_unknown;
1104                 break;
1105         }
1106         return media_type;
1107 }
1108
1109 /**
1110  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1111  *  @hw: pointer to hardware structure
1112  *  @linear: true if SFP module is linear
1113  */
1114 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1115 {
1116         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1117
1118         switch (hw->phy.sfp_type) {
1119         case ixgbe_sfp_type_not_present:
1120                 return IXGBE_ERR_SFP_NOT_PRESENT;
1121         case ixgbe_sfp_type_da_cu_core0:
1122         case ixgbe_sfp_type_da_cu_core1:
1123                 *linear = true;
1124                 break;
1125         case ixgbe_sfp_type_srlr_core0:
1126         case ixgbe_sfp_type_srlr_core1:
1127         case ixgbe_sfp_type_da_act_lmt_core0:
1128         case ixgbe_sfp_type_da_act_lmt_core1:
1129         case ixgbe_sfp_type_1g_sx_core0:
1130         case ixgbe_sfp_type_1g_sx_core1:
1131         case ixgbe_sfp_type_1g_lx_core0:
1132         case ixgbe_sfp_type_1g_lx_core1:
1133                 *linear = false;
1134                 break;
1135         case ixgbe_sfp_type_unknown:
1136         case ixgbe_sfp_type_1g_cu_core0:
1137         case ixgbe_sfp_type_1g_cu_core1:
1138         default:
1139                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1140         }
1141
1142         return IXGBE_SUCCESS;
1143 }
1144
1145 /**
1146  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1147  *  @hw: pointer to hardware structure
1148  *
1149  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1150  **/
1151 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1152 {
1153         s32 status;
1154         bool linear;
1155
1156         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1157
1158         status = ixgbe_identify_module_generic(hw);
1159
1160         if (status != IXGBE_SUCCESS)
1161                 return status;
1162
1163         /* Check if SFP module is supported */
1164         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1165
1166         return status;
1167 }
1168
1169 /**
1170  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1171  *  @hw: pointer to hardware structure
1172  */
1173 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1174 {
1175         s32 status;
1176         bool linear;
1177
1178         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1179
1180         /* Check if SFP module is supported */
1181         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1182
1183         if (status != IXGBE_SUCCESS)
1184                 return status;
1185
1186         ixgbe_init_mac_link_ops_X550em(hw);
1187         hw->phy.ops.reset = NULL;
1188
1189         return IXGBE_SUCCESS;
1190 }
1191
1192 /**
1193  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1194  *  @hw: pointer to hardware structure
1195  */
1196 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1197 {
1198         struct ixgbe_mac_info *mac = &hw->mac;
1199
1200         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1201
1202          switch (hw->mac.ops.get_media_type(hw)) {
1203          case ixgbe_media_type_fiber:
1204                 /* CS4227 does not support autoneg, so disable the laser control
1205                  * functions for SFP+ fiber
1206                  */
1207                 mac->ops.disable_tx_laser = NULL;
1208                 mac->ops.enable_tx_laser = NULL;
1209                 mac->ops.flap_tx_laser = NULL;
1210                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1211                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1212                 mac->ops.set_rate_select_speed =
1213                                         ixgbe_set_soft_rate_select_speed;
1214                 break;
1215         case ixgbe_media_type_copper:
1216                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1217                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1218                 break;
1219         default:
1220                 break;
1221          }
1222 }
1223
1224 /**
1225  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1226  *  @hw: pointer to hardware structure
1227  *  @speed: pointer to link speed
1228  *  @autoneg: true when autoneg or autotry is enabled
1229  */
1230 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1231                                        ixgbe_link_speed *speed,
1232                                        bool *autoneg)
1233 {
1234         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1235
1236         /* SFP */
1237         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1238
1239                 /* CS4227 SFP must not enable auto-negotiation */
1240                 *autoneg = false;
1241
1242                 /* Check if 1G SFP module. */
1243                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1244                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1245                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1246                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1247                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1248                         return IXGBE_SUCCESS;
1249                 }
1250
1251                 /* Link capabilities are based on SFP */
1252                 if (hw->phy.multispeed_fiber)
1253                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1254                                  IXGBE_LINK_SPEED_1GB_FULL;
1255                 else
1256                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1257         } else {
1258                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1259                          IXGBE_LINK_SPEED_1GB_FULL;
1260                 *autoneg = true;
1261         }
1262
1263         return IXGBE_SUCCESS;
1264 }
1265
1266 /**
1267  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1268  * @hw: pointer to hardware structure
1269  * @lsc: pointer to boolean flag which indicates whether external Base T
1270  *       PHY interrupt is lsc
1271  *
1272  * Determime if external Base T PHY interrupt cause is high temperature
1273  * failure alarm or link status change.
1274  *
1275  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1276  * failure alarm, else return PHY access status.
1277  */
1278 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1279 {
1280         u32 status;
1281         u16 reg;
1282
1283         *lsc = false;
1284
1285         /* Vendor alarm triggered */
1286         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1287                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1288                                       &reg);
1289
1290         if (status != IXGBE_SUCCESS ||
1291             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1292                 return status;
1293
1294         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1295         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1296                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1297                                       &reg);
1298
1299         if (status != IXGBE_SUCCESS ||
1300             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1301             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1302                 return status;
1303
1304         /* High temperature failure alarm triggered */
1305         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1306                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1307                                       &reg);
1308
1309         if (status != IXGBE_SUCCESS)
1310                 return status;
1311
1312         /* If high temperature failure, then return over temp error and exit */
1313         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1314                 /* power down the PHY in case the PHY FW didn't already */
1315                 ixgbe_set_copper_phy_power(hw, false);
1316                 return IXGBE_ERR_OVERTEMP;
1317         }
1318
1319         /* Vendor alarm 2 triggered */
1320         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1321                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1322
1323         if (status != IXGBE_SUCCESS ||
1324             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1325                 return status;
1326
1327         /* link connect/disconnect event occurred */
1328         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1329                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1330
1331         if (status != IXGBE_SUCCESS)
1332                 return status;
1333
1334         /* Indicate LSC */
1335         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1336                 *lsc = true;
1337
1338         return IXGBE_SUCCESS;
1339 }
1340
1341 /**
1342  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1343  * @hw: pointer to hardware structure
1344  *
1345  * Enable link status change and temperature failure alarm for the external
1346  * Base T PHY
1347  *
1348  * Returns PHY access status
1349  */
1350 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1351 {
1352         u32 status;
1353         u16 reg;
1354         bool lsc;
1355
1356         /* Clear interrupt flags */
1357         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1358
1359         /* Enable link status change alarm */
1360         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1361                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1362
1363         if (status != IXGBE_SUCCESS)
1364                 return status;
1365
1366         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1367
1368         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1369                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1370
1371         if (status != IXGBE_SUCCESS)
1372                 return status;
1373
1374         /* Enables high temperature failure alarm */
1375         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1376                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1377                                       &reg);
1378
1379         if (status != IXGBE_SUCCESS)
1380                 return status;
1381
1382         reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1383
1384         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1385                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1386                                        reg);
1387
1388         if (status != IXGBE_SUCCESS)
1389                 return status;
1390
1391         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1392         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1393                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1394                                       &reg);
1395
1396         if (status != IXGBE_SUCCESS)
1397                 return status;
1398
1399         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1400                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1401
1402         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1403                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1404                                        reg);
1405
1406         if (status != IXGBE_SUCCESS)
1407                 return status;
1408
1409         /* Enable chip-wide vendor alarm */
1410         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1411                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1412                                       &reg);
1413
1414         if (status != IXGBE_SUCCESS)
1415                 return status;
1416
1417         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1418
1419         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1420                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1421                                        reg);
1422
1423         return status;
1424 }
1425
1426 /**
1427  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1428  *  @hw: pointer to hardware structure
1429  *  @speed: link speed
1430  *
1431  *  Configures the integrated KR PHY.
1432  **/
1433 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1434                                        ixgbe_link_speed speed)
1435 {
1436         s32 status;
1437         u32 reg_val;
1438
1439         status = ixgbe_read_iosf_sb_reg_x550(hw,
1440                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1441                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1442         if (status)
1443                 return status;
1444
1445         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1446         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1447                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1448
1449         /* Advertise 10G support. */
1450         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1451                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1452
1453         /* Advertise 1G support. */
1454         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1455                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1456
1457         /* Restart auto-negotiation. */
1458         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1459         status = ixgbe_write_iosf_sb_reg_x550(hw,
1460                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1461                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1462
1463         return status;
1464 }
1465
1466 /**
1467  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1468  *  @hw: pointer to hardware structure
1469  *
1470  *  Initialize any function pointers that were not able to be
1471  *  set during init_shared_code because the PHY/SFP type was
1472  *  not known.  Perform the SFP init if necessary.
1473  */
1474 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1475 {
1476         struct ixgbe_phy_info *phy = &hw->phy;
1477         ixgbe_link_speed speed;
1478         s32 ret_val;
1479
1480         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1481
1482         hw->mac.ops.set_lan_id(hw);
1483
1484         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1485                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1486                 ixgbe_setup_mux_ctl(hw);
1487
1488                 /* Save NW management interface connected on board. This is used
1489                  * to determine internal PHY mode.
1490                  */
1491                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1492
1493                 /* If internal PHY mode is KR, then initialize KR link */
1494                 if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
1495                         speed = IXGBE_LINK_SPEED_10GB_FULL |
1496                                 IXGBE_LINK_SPEED_1GB_FULL;
1497                         ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1498                 }
1499
1500                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1501         }
1502
1503         /* Identify the PHY or SFP module */
1504         ret_val = phy->ops.identify(hw);
1505         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1506                 return ret_val;
1507
1508         /* Setup function pointers based on detected hardware */
1509         ixgbe_init_mac_link_ops_X550em(hw);
1510         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1511                 phy->ops.reset = NULL;
1512
1513         /* Set functions pointers based on phy type */
1514         switch (hw->phy.type) {
1515         case ixgbe_phy_x550em_kx4:
1516                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1517                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1518                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1519                 break;
1520         case ixgbe_phy_x550em_kr:
1521                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1522                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1523                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1524                 break;
1525         case ixgbe_phy_x550em_ext_t:
1526                 /* Save NW management interface connected on board. This is used
1527                  * to determine internal PHY mode
1528                  */
1529                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1530
1531                 /* If internal link mode is XFI, then setup iXFI internal link,
1532                  * else setup KR now.
1533                  */
1534                 if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1535                         phy->ops.setup_internal_link =
1536                                               ixgbe_setup_internal_phy_t_x550em;
1537                 } else {
1538                         speed = IXGBE_LINK_SPEED_10GB_FULL |
1539                                 IXGBE_LINK_SPEED_1GB_FULL;
1540                         ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1541                 }
1542
1543                 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1544                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1545                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1546                 break;
1547         default:
1548                 break;
1549         }
1550         return ret_val;
1551 }
1552
1553 /**
1554  *  ixgbe_reset_hw_X550em - Perform hardware reset
1555  *  @hw: pointer to hardware structure
1556  *
1557  *  Resets the hardware by resetting the transmit and receive units, masks
1558  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1559  *  reset.
1560  */
1561 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1562 {
1563         ixgbe_link_speed link_speed;
1564         s32 status;
1565         u32 ctrl = 0;
1566         u32 i;
1567         u32 hlreg0;
1568         bool link_up = false;
1569
1570         DEBUGFUNC("ixgbe_reset_hw_X550em");
1571
1572         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1573         status = hw->mac.ops.stop_adapter(hw);
1574         if (status != IXGBE_SUCCESS)
1575                 return status;
1576
1577         /* flush pending Tx transactions */
1578         ixgbe_clear_tx_pending(hw);
1579
1580         /* PHY ops must be identified and initialized prior to reset */
1581
1582         /* Identify PHY and related function pointers */
1583         status = hw->phy.ops.init(hw);
1584
1585         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1586                 return status;
1587
1588         /* start the external PHY */
1589         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1590                 status = ixgbe_init_ext_t_x550em(hw);
1591                 if (status)
1592                         return status;
1593         }
1594
1595         /* Setup SFP module if there is one present. */
1596         if (hw->phy.sfp_setup_needed) {
1597                 status = hw->mac.ops.setup_sfp(hw);
1598                 hw->phy.sfp_setup_needed = false;
1599         }
1600
1601         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1602                 return status;
1603
1604         /* Reset PHY */
1605         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1606                 hw->phy.ops.reset(hw);
1607
1608 mac_reset_top:
1609         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1610          * If link reset is used when link is up, it might reset the PHY when
1611          * mng is using it.  If link is down or the flag to force full link
1612          * reset is set, then perform link reset.
1613          */
1614         ctrl = IXGBE_CTRL_LNK_RST;
1615         if (!hw->force_full_reset) {
1616                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1617                 if (link_up)
1618                         ctrl = IXGBE_CTRL_RST;
1619         }
1620
1621         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1622         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1623         IXGBE_WRITE_FLUSH(hw);
1624
1625         /* Poll for reset bit to self-clear meaning reset is complete */
1626         for (i = 0; i < 10; i++) {
1627                 usec_delay(1);
1628                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1629                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1630                         break;
1631         }
1632
1633         if (ctrl & IXGBE_CTRL_RST_MASK) {
1634                 status = IXGBE_ERR_RESET_FAILED;
1635                 DEBUGOUT("Reset polling failed to complete.\n");
1636         }
1637
1638         msec_delay(50);
1639
1640         /* Double resets are required for recovery from certain error
1641          * conditions.  Between resets, it is necessary to stall to
1642          * allow time for any pending HW events to complete.
1643          */
1644         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1645                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1646                 goto mac_reset_top;
1647         }
1648
1649         /* Store the permanent mac address */
1650         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1651
1652         /* Store MAC address from RAR0, clear receive address registers, and
1653          * clear the multicast table.  Also reset num_rar_entries to 128,
1654          * since we modify this value when programming the SAN MAC address.
1655          */
1656         hw->mac.num_rar_entries = 128;
1657         hw->mac.ops.init_rx_addrs(hw);
1658
1659         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
1660                 /* Config MDIO clock speed. */
1661                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1662                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1663                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1664         }
1665
1666         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1667                 ixgbe_setup_mux_ctl(hw);
1668
1669         return status;
1670 }
1671
1672 /**
1673  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1674  * @hw: pointer to hardware structure
1675  */
1676 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1677 {
1678         u32 status;
1679         u16 reg;
1680
1681         status = hw->phy.ops.read_reg(hw,
1682                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1683                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1684                                       &reg);
1685
1686         if (status != IXGBE_SUCCESS)
1687                 return status;
1688
1689         /* If PHY FW reset completed bit is set then this is the first
1690          * SW instance after a power on so the PHY FW must be un-stalled.
1691          */
1692         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1693                 status = hw->phy.ops.read_reg(hw,
1694                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1695                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1696                                         &reg);
1697
1698                 if (status != IXGBE_SUCCESS)
1699                         return status;
1700
1701                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1702
1703                 status = hw->phy.ops.write_reg(hw,
1704                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1705                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1706                                         reg);
1707
1708                 if (status != IXGBE_SUCCESS)
1709                         return status;
1710         }
1711
1712         return status;
1713 }
1714
1715 /**
1716  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1717  *  @hw: pointer to hardware structure
1718  *
1719  *  Configures the integrated KR PHY.
1720  **/
1721 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1722 {
1723         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1724 }
1725
1726 /**
1727  *  ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1728  *  @hw: pointer to hardware structure
1729  *
1730  *  Configures the integrated KX4 PHY.
1731  **/
1732 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1733 {
1734         s32 status;
1735         u32 reg_val;
1736
1737         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1738                 IXGBE_SB_IOSF_TARGET_KX4_PCS, &reg_val);
1739         if (status)
1740                 return status;
1741
1742         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1743                         IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1744
1745         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1746
1747         /* Advertise 10G support. */
1748         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1749                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1750
1751         /* Advertise 1G support. */
1752         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1753                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1754
1755         /* Restart auto-negotiation. */
1756         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1757         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1758                 IXGBE_SB_IOSF_TARGET_KX4_PCS, reg_val);
1759
1760         return status;
1761 }
1762
1763 /**
1764  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1765  *  @hw: pointer to hardware structure
1766  *  @speed: the link speed to force
1767  *
1768  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1769  *  internal and external PHY at a specific speed, without autonegotiation.
1770  **/
1771 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1772 {
1773         s32 status;
1774         u32 reg_val;
1775
1776         /* Disable AN and force speed to 10G Serial. */
1777         status = ixgbe_read_iosf_sb_reg_x550(hw,
1778                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1779                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1780         if (status != IXGBE_SUCCESS)
1781                 return status;
1782
1783         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1784         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1785
1786         /* Select forced link speed for internal PHY. */
1787         switch (*speed) {
1788         case IXGBE_LINK_SPEED_10GB_FULL:
1789                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1790                 break;
1791         case IXGBE_LINK_SPEED_1GB_FULL:
1792                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1793                 break;
1794         default:
1795                 /* Other link speeds are not supported by internal KR PHY. */
1796                 return IXGBE_ERR_LINK_SETUP;
1797         }
1798
1799         status = ixgbe_write_iosf_sb_reg_x550(hw,
1800                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1801                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1802         if (status != IXGBE_SUCCESS)
1803                 return status;
1804
1805         /* Disable training protocol FSM. */
1806         status = ixgbe_read_iosf_sb_reg_x550(hw,
1807                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1808                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1809         if (status != IXGBE_SUCCESS)
1810                 return status;
1811         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1812         status = ixgbe_write_iosf_sb_reg_x550(hw,
1813                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1814                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1815         if (status != IXGBE_SUCCESS)
1816                 return status;
1817
1818         /* Disable Flex from training TXFFE. */
1819         status = ixgbe_read_iosf_sb_reg_x550(hw,
1820                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1821                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1822         if (status != IXGBE_SUCCESS)
1823                 return status;
1824         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1825         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1826         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1827         status = ixgbe_write_iosf_sb_reg_x550(hw,
1828                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1829                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1830         if (status != IXGBE_SUCCESS)
1831                 return status;
1832         status = ixgbe_read_iosf_sb_reg_x550(hw,
1833                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1834                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1835         if (status != IXGBE_SUCCESS)
1836                 return status;
1837         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1838         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1839         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1840         status = ixgbe_write_iosf_sb_reg_x550(hw,
1841                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1842                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1843         if (status != IXGBE_SUCCESS)
1844                 return status;
1845
1846         /* Enable override for coefficients. */
1847         status = ixgbe_read_iosf_sb_reg_x550(hw,
1848                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1849                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1850         if (status != IXGBE_SUCCESS)
1851                 return status;
1852         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1853         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1854         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1855         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1856         status = ixgbe_write_iosf_sb_reg_x550(hw,
1857                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1858                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1859         if (status != IXGBE_SUCCESS)
1860                 return status;
1861
1862         /* Toggle port SW reset by AN reset. */
1863         status = ixgbe_read_iosf_sb_reg_x550(hw,
1864                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1865                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1866         if (status != IXGBE_SUCCESS)
1867                 return status;
1868         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1869         status = ixgbe_write_iosf_sb_reg_x550(hw,
1870                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1871                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1872
1873         return status;
1874 }
1875
1876 /**
1877  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
1878  * @hw: address of hardware structure
1879  * @link_up: address of boolean to indicate link status
1880  *
1881  * Returns error code if unable to get link status.
1882  */
1883 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
1884 {
1885         u32 ret;
1886         u16 autoneg_status;
1887
1888         *link_up = false;
1889
1890         /* read this twice back to back to indicate current status */
1891         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1892                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1893                                    &autoneg_status);
1894         if (ret != IXGBE_SUCCESS)
1895                 return ret;
1896
1897         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1898                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1899                                    &autoneg_status);
1900         if (ret != IXGBE_SUCCESS)
1901                 return ret;
1902
1903         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
1904
1905         return IXGBE_SUCCESS;
1906 }
1907
1908 /**
1909  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
1910  *  @hw: pointer to hardware structure
1911  *
1912  *  Configure the external PHY and the integrated KR PHY for SFP support.
1913  **/
1914 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1915                                     ixgbe_link_speed speed,
1916                                     bool autoneg_wait_to_complete)
1917 {
1918         s32 ret_val;
1919         u16 reg_slice, reg_val;
1920         bool setup_linear = false;
1921         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1922
1923         /* Check if SFP module is supported and linear */
1924         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1925
1926         /* If no SFP module present, then return success. Return success since
1927          * there is no reason to configure CS4227 and SFP not present error is
1928          * not excepted in the setup MAC link flow.
1929          */
1930         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1931                 return IXGBE_SUCCESS;
1932
1933         if (ret_val != IXGBE_SUCCESS)
1934                 return ret_val;
1935
1936         /* Configure CS4227 for LINE connection rate then type. */
1937         reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1938         reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1939         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1940                                            reg_val);
1941
1942         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1943         if (setup_linear)
1944                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1945         else
1946                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1947         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1948                                            reg_val);
1949
1950         /* Configure CS4227 for HOST connection rate then type. */
1951         reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1952         reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1953         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1954                                            reg_val);
1955
1956         reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1957         if (setup_linear)
1958                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1959         else
1960                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1961         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1962                                            reg_val);
1963
1964         /* If internal link mode is XFI, then setup XFI internal link. */
1965         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))
1966                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1967
1968         return ret_val;
1969 }
1970
1971 /**
1972  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1973  * @hw: point to hardware structure
1974  *
1975  * Configures the link between the integrated KR PHY and the external X557 PHY
1976  * The driver will call this function when it gets a link status change
1977  * interrupt from the X557 PHY. This function configures the link speed
1978  * between the PHYs to match the link speed of the BASE-T link.
1979  *
1980  * A return of a non-zero value indicates an error, and the base driver should
1981  * not report link up.
1982  */
1983 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1984 {
1985         ixgbe_link_speed force_speed;
1986         bool link_up;
1987         u32 status;
1988         u16 speed;
1989
1990         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1991                 return IXGBE_ERR_CONFIG;
1992
1993         /* If link is not up, then there is no setup necessary so return  */
1994         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1995         if (status != IXGBE_SUCCESS)
1996                 return status;
1997
1998         if (!link_up)
1999                 return IXGBE_SUCCESS;
2000
2001         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2002                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2003                                       &speed);
2004         if (status != IXGBE_SUCCESS)
2005                 return status;
2006
2007         /* If link is not still up, then no setup is necessary so return */
2008         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2009         if (status != IXGBE_SUCCESS)
2010                 return status;
2011         if (!link_up)
2012                 return IXGBE_SUCCESS;
2013
2014         /* clear everything but the speed and duplex bits */
2015         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2016
2017         switch (speed) {
2018         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2019                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2020                 break;
2021         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2022                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2023                 break;
2024         default:
2025                 /* Internal PHY does not support anything else */
2026                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2027         }
2028
2029         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2030 }
2031
2032 /**
2033  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2034  *  @hw: pointer to hardware structure
2035  *
2036  *  Configures the integrated KR PHY to use internal loopback mode.
2037  **/
2038 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2039 {
2040         s32 status;
2041         u32 reg_val;
2042
2043         /* Disable AN and force speed to 10G Serial. */
2044         status = ixgbe_read_iosf_sb_reg_x550(hw,
2045                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2046                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2047         if (status != IXGBE_SUCCESS)
2048                 return status;
2049         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2050         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2051         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2052         status = ixgbe_write_iosf_sb_reg_x550(hw,
2053                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2054                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2055         if (status != IXGBE_SUCCESS)
2056                 return status;
2057
2058         /* Set near-end loopback clocks. */
2059         status = ixgbe_read_iosf_sb_reg_x550(hw,
2060                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2061                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2062         if (status != IXGBE_SUCCESS)
2063                 return status;
2064         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2065         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2066         status = ixgbe_write_iosf_sb_reg_x550(hw,
2067                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2068                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2069         if (status != IXGBE_SUCCESS)
2070                 return status;
2071
2072         /* Set loopback enable. */
2073         status = ixgbe_read_iosf_sb_reg_x550(hw,
2074                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2075                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2076         if (status != IXGBE_SUCCESS)
2077                 return status;
2078         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2079         status = ixgbe_write_iosf_sb_reg_x550(hw,
2080                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2081                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2082         if (status != IXGBE_SUCCESS)
2083                 return status;
2084
2085         /* Training bypass. */
2086         status = ixgbe_read_iosf_sb_reg_x550(hw,
2087                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2088                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2089         if (status != IXGBE_SUCCESS)
2090                 return status;
2091         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2092         status = ixgbe_write_iosf_sb_reg_x550(hw,
2093                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2094                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2095
2096         return status;
2097 }
2098
2099 /**
2100  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2101  *  assuming that the semaphore is already obtained.
2102  *  @hw: pointer to hardware structure
2103  *  @offset: offset of  word in the EEPROM to read
2104  *  @data: word read from the EEPROM
2105  *
2106  *  Reads a 16 bit word from the EEPROM using the hostif.
2107  **/
2108 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2109                                    u16 *data)
2110 {
2111         s32 status;
2112         struct ixgbe_hic_read_shadow_ram buffer;
2113
2114         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2115         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2116         buffer.hdr.req.buf_lenh = 0;
2117         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2118         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2119
2120         /* convert offset from words to bytes */
2121         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2122         /* one word */
2123         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2124
2125         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2126                                               sizeof(buffer),
2127                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2128
2129         if (status)
2130                 return status;
2131
2132         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2133                                           FW_NVM_DATA_OFFSET);
2134
2135         return 0;
2136 }
2137
2138 /**
2139  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2140  *  @hw: pointer to hardware structure
2141  *  @offset: offset of  word in the EEPROM to read
2142  *  @data: word read from the EEPROM
2143  *
2144  *  Reads a 16 bit word from the EEPROM using the hostif.
2145  **/
2146 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2147                               u16 *data)
2148 {
2149         s32 status = IXGBE_SUCCESS;
2150
2151         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2152
2153         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2154             IXGBE_SUCCESS) {
2155                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2156                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2157         } else {
2158                 status = IXGBE_ERR_SWFW_SYNC;
2159         }
2160
2161         return status;
2162 }
2163
2164 /**
2165  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2166  *  @hw: pointer to hardware structure
2167  *  @offset: offset of  word in the EEPROM to read
2168  *  @words: number of words
2169  *  @data: word(s) read from the EEPROM
2170  *
2171  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
2172  **/
2173 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2174                                      u16 offset, u16 words, u16 *data)
2175 {
2176         struct ixgbe_hic_read_shadow_ram buffer;
2177         u32 current_word = 0;
2178         u16 words_to_read;
2179         s32 status;
2180         u32 i;
2181
2182         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2183
2184         /* Take semaphore for the entire operation. */
2185         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2186         if (status) {
2187                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2188                 return status;
2189         }
2190         while (words) {
2191                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2192                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2193                 else
2194                         words_to_read = words;
2195
2196                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2197                 buffer.hdr.req.buf_lenh = 0;
2198                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2199                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2200
2201                 /* convert offset from words to bytes */
2202                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2203                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2204
2205                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2206                                                       sizeof(buffer),
2207                                                       IXGBE_HI_COMMAND_TIMEOUT,
2208                                                       false);
2209
2210                 if (status) {
2211                         DEBUGOUT("Host interface command failed\n");
2212                         goto out;
2213                 }
2214
2215                 for (i = 0; i < words_to_read; i++) {
2216                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2217                                   2 * i;
2218                         u32 value = IXGBE_READ_REG(hw, reg);
2219
2220                         data[current_word] = (u16)(value & 0xffff);
2221                         current_word++;
2222                         i++;
2223                         if (i < words_to_read) {
2224                                 value >>= 16;
2225                                 data[current_word] = (u16)(value & 0xffff);
2226                                 current_word++;
2227                         }
2228                 }
2229                 words -= words_to_read;
2230         }
2231
2232 out:
2233         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2234         return status;
2235 }
2236
2237 /**
2238  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2239  *  @hw: pointer to hardware structure
2240  *  @offset: offset of  word in the EEPROM to write
2241  *  @data: word write to the EEPROM
2242  *
2243  *  Write a 16 bit word to the EEPROM using the hostif.
2244  **/
2245 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2246                                     u16 data)
2247 {
2248         s32 status;
2249         struct ixgbe_hic_write_shadow_ram buffer;
2250
2251         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2252
2253         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2254         buffer.hdr.req.buf_lenh = 0;
2255         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2256         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2257
2258          /* one word */
2259         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2260         buffer.data = data;
2261         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2262
2263         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2264                                               sizeof(buffer),
2265                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2266
2267         return status;
2268 }
2269
2270 /**
2271  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2272  *  @hw: pointer to hardware structure
2273  *  @offset: offset of  word in the EEPROM to write
2274  *  @data: word write to the EEPROM
2275  *
2276  *  Write a 16 bit word to the EEPROM using the hostif.
2277  **/
2278 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2279                                u16 data)
2280 {
2281         s32 status = IXGBE_SUCCESS;
2282
2283         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2284
2285         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2286             IXGBE_SUCCESS) {
2287                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2288                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2289         } else {
2290                 DEBUGOUT("write ee hostif failed to get semaphore");
2291                 status = IXGBE_ERR_SWFW_SYNC;
2292         }
2293
2294         return status;
2295 }
2296
2297 /**
2298  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2299  *  @hw: pointer to hardware structure
2300  *  @offset: offset of  word in the EEPROM to write
2301  *  @words: number of words
2302  *  @data: word(s) write to the EEPROM
2303  *
2304  *  Write a 16 bit word(s) to the EEPROM using the hostif.
2305  **/
2306 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2307                                       u16 offset, u16 words, u16 *data)
2308 {
2309         s32 status = IXGBE_SUCCESS;
2310         u32 i = 0;
2311
2312         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2313
2314         /* Take semaphore for the entire operation. */
2315         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2316         if (status != IXGBE_SUCCESS) {
2317                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2318                 goto out;
2319         }
2320
2321         for (i = 0; i < words; i++) {
2322                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2323                                                          data[i]);
2324
2325                 if (status != IXGBE_SUCCESS) {
2326                         DEBUGOUT("Eeprom buffered write failed\n");
2327                         break;
2328                 }
2329         }
2330
2331         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2332 out:
2333
2334         return status;
2335 }
2336
2337 /**
2338  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2339  * @hw: pointer to hardware structure
2340  * @ptr: pointer offset in eeprom
2341  * @size: size of section pointed by ptr, if 0 first word will be used as size
2342  * @csum: address of checksum to update
2343  *
2344  * Returns error status for any failure
2345  */
2346 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2347                                    u16 size, u16 *csum, u16 *buffer,
2348                                    u32 buffer_size)
2349 {
2350         u16 buf[256];
2351         s32 status;
2352         u16 length, bufsz, i, start;
2353         u16 *local_buffer;
2354
2355         bufsz = sizeof(buf) / sizeof(buf[0]);
2356
2357         /* Read a chunk at the pointer location */
2358         if (!buffer) {
2359                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2360                 if (status) {
2361                         DEBUGOUT("Failed to read EEPROM image\n");
2362                         return status;
2363                 }
2364                 local_buffer = buf;
2365         } else {
2366                 if (buffer_size < ptr)
2367                         return  IXGBE_ERR_PARAM;
2368                 local_buffer = &buffer[ptr];
2369         }
2370
2371         if (size) {
2372                 start = 0;
2373                 length = size;
2374         } else {
2375                 start = 1;
2376                 length = local_buffer[0];
2377
2378                 /* Skip pointer section if length is invalid. */
2379                 if (length == 0xFFFF || length == 0 ||
2380                     (ptr + length) >= hw->eeprom.word_size)
2381                         return IXGBE_SUCCESS;
2382         }
2383
2384         if (buffer && ((u32)start + (u32)length > buffer_size))
2385                 return IXGBE_ERR_PARAM;
2386
2387         for (i = start; length; i++, length--) {
2388                 if (i == bufsz && !buffer) {
2389                         ptr += bufsz;
2390                         i = 0;
2391                         if (length < bufsz)
2392                                 bufsz = length;
2393
2394                         /* Read a chunk at the pointer location */
2395                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2396                                                                   bufsz, buf);
2397                         if (status) {
2398                                 DEBUGOUT("Failed to read EEPROM image\n");
2399                                 return status;
2400                         }
2401                 }
2402                 *csum += local_buffer[i];
2403         }
2404         return IXGBE_SUCCESS;
2405 }
2406
2407 /**
2408  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2409  *  @hw: pointer to hardware structure
2410  *  @buffer: pointer to buffer containing calculated checksum
2411  *  @buffer_size: size of buffer
2412  *
2413  *  Returns a negative error code on error, or the 16-bit checksum
2414  **/
2415 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2416 {
2417         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2418         u16 *local_buffer;
2419         s32 status;
2420         u16 checksum = 0;
2421         u16 pointer, i, size;
2422
2423         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2424
2425         hw->eeprom.ops.init_params(hw);
2426
2427         if (!buffer) {
2428                 /* Read pointer area */
2429                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2430                                                      IXGBE_EEPROM_LAST_WORD + 1,
2431                                                      eeprom_ptrs);
2432                 if (status) {
2433                         DEBUGOUT("Failed to read EEPROM image\n");
2434                         return status;
2435                 }
2436                 local_buffer = eeprom_ptrs;
2437         } else {
2438                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2439                         return IXGBE_ERR_PARAM;
2440                 local_buffer = buffer;
2441         }
2442
2443         /*
2444          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2445          * checksum word itself
2446          */
2447         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2448                 if (i != IXGBE_EEPROM_CHECKSUM)
2449                         checksum += local_buffer[i];
2450
2451         /*
2452          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2453          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2454          */
2455         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2456                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2457                         continue;
2458
2459                 pointer = local_buffer[i];
2460
2461                 /* Skip pointer section if the pointer is invalid. */
2462                 if (pointer == 0xFFFF || pointer == 0 ||
2463                     pointer >= hw->eeprom.word_size)
2464                         continue;
2465
2466                 switch (i) {
2467                 case IXGBE_PCIE_GENERAL_PTR:
2468                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2469                         break;
2470                 case IXGBE_PCIE_CONFIG0_PTR:
2471                 case IXGBE_PCIE_CONFIG1_PTR:
2472                         size = IXGBE_PCIE_CONFIG_SIZE;
2473                         break;
2474                 default:
2475                         size = 0;
2476                         break;
2477                 }
2478
2479                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2480                                                 buffer, buffer_size);
2481                 if (status)
2482                         return status;
2483         }
2484
2485         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2486
2487         return (s32)checksum;
2488 }
2489
2490 /**
2491  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2492  *  @hw: pointer to hardware structure
2493  *
2494  *  Returns a negative error code on error, or the 16-bit checksum
2495  **/
2496 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2497 {
2498         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2499 }
2500
2501 /**
2502  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2503  *  @hw: pointer to hardware structure
2504  *  @checksum_val: calculated checksum
2505  *
2506  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2507  *  caller does not need checksum_val, the value can be NULL.
2508  **/
2509 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2510 {
2511         s32 status;
2512         u16 checksum;
2513         u16 read_checksum = 0;
2514
2515         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2516
2517         /* Read the first word from the EEPROM. If this times out or fails, do
2518          * not continue or we could be in for a very long wait while every
2519          * EEPROM read fails
2520          */
2521         status = hw->eeprom.ops.read(hw, 0, &checksum);
2522         if (status) {
2523                 DEBUGOUT("EEPROM read failed\n");
2524                 return status;
2525         }
2526
2527         status = hw->eeprom.ops.calc_checksum(hw);
2528         if (status < 0)
2529                 return status;
2530
2531         checksum = (u16)(status & 0xffff);
2532
2533         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2534                                            &read_checksum);
2535         if (status)
2536                 return status;
2537
2538         /* Verify read checksum from EEPROM is the same as
2539          * calculated checksum
2540          */
2541         if (read_checksum != checksum) {
2542                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2543                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2544                              "Invalid EEPROM checksum");
2545         }
2546
2547         /* If the user cares, return the calculated checksum */
2548         if (checksum_val)
2549                 *checksum_val = checksum;
2550
2551         return status;
2552 }
2553
2554 /**
2555  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2556  * @hw: pointer to hardware structure
2557  *
2558  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2559  * checksum and updates the EEPROM and instructs the hardware to update
2560  * the flash.
2561  **/
2562 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2563 {
2564         s32 status;
2565         u16 checksum = 0;
2566
2567         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2568
2569         /* Read the first word from the EEPROM. If this times out or fails, do
2570          * not continue or we could be in for a very long wait while every
2571          * EEPROM read fails
2572          */
2573         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2574         if (status) {
2575                 DEBUGOUT("EEPROM read failed\n");
2576                 return status;
2577         }
2578
2579         status = ixgbe_calc_eeprom_checksum_X550(hw);
2580         if (status < 0)
2581                 return status;
2582
2583         checksum = (u16)(status & 0xffff);
2584
2585         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2586                                             checksum);
2587         if (status)
2588                 return status;
2589
2590         status = ixgbe_update_flash_X550(hw);
2591
2592         return status;
2593 }
2594
2595 /**
2596  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2597  *  @hw: pointer to hardware structure
2598  *
2599  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2600  **/
2601 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2602 {
2603         s32 status = IXGBE_SUCCESS;
2604         union ixgbe_hic_hdr2 buffer;
2605
2606         DEBUGFUNC("ixgbe_update_flash_X550");
2607
2608         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2609         buffer.req.buf_lenh = 0;
2610         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2611         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2612
2613         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2614                                               sizeof(buffer),
2615                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2616
2617         return status;
2618 }
2619
2620 /**
2621  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2622  *  @hw: pointer to hardware structure
2623  *
2624  *  Determines physical layer capabilities of the current configuration.
2625  **/
2626 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2627 {
2628         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2629         u16 ext_ability = 0;
2630
2631         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2632
2633         hw->phy.ops.identify(hw);
2634
2635         switch (hw->phy.type) {
2636         case ixgbe_phy_x550em_kr:
2637                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2638                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2639                 break;
2640         case ixgbe_phy_x550em_kx4:
2641                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2642                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2643                 break;
2644         case ixgbe_phy_x550em_ext_t:
2645                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2646                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2647                                      &ext_ability);
2648                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2649                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2650                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2651                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2652                 break;
2653         default:
2654                 break;
2655         }
2656
2657         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2658                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2659
2660         return physical_layer;
2661 }
2662
2663 /**
2664  * ixgbe_get_bus_info_x550em - Set PCI bus info
2665  * @hw: pointer to hardware structure
2666  *
2667  * Sets bus link width and speed to unknown because X550em is
2668  * not a PCI device.
2669  **/
2670 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2671 {
2672
2673         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2674
2675         hw->bus.width = ixgbe_bus_width_unknown;
2676         hw->bus.speed = ixgbe_bus_speed_unknown;
2677
2678         hw->mac.ops.set_lan_id(hw);
2679
2680         return IXGBE_SUCCESS;
2681 }
2682
2683 /**
2684  * ixgbe_disable_rx_x550 - Disable RX unit
2685  *
2686  * Enables the Rx DMA unit for x550
2687  **/
2688 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2689 {
2690         u32 rxctrl, pfdtxgswc;
2691         s32 status;
2692         struct ixgbe_hic_disable_rxen fw_cmd;
2693
2694         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2695
2696         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2697         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2698                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2699                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2700                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2701                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2702                         hw->mac.set_lben = true;
2703                 } else {
2704                         hw->mac.set_lben = false;
2705                 }
2706
2707                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2708                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2709                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2710                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2711
2712                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2713                                         sizeof(struct ixgbe_hic_disable_rxen),
2714                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2715
2716                 /* If we fail - disable RX using register write */
2717                 if (status) {
2718                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2719                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2720                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2721                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2722                         }
2723                 }
2724         }
2725 }
2726
2727 /**
2728  * ixgbe_enter_lplu_x550em - Transition to low power states
2729  *  @hw: pointer to hardware structure
2730  *
2731  * Configures Low Power Link Up on transition to low power states
2732  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2733  * X557 PHY immediately prior to entering LPLU.
2734  **/
2735 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2736 {
2737         u16 an_10g_cntl_reg, autoneg_reg, speed;
2738         s32 status;
2739         ixgbe_link_speed lcd_speed;
2740         u32 save_autoneg;
2741         bool link_up;
2742
2743         /* If blocked by MNG FW, then don't restart AN */
2744         if (ixgbe_check_reset_blocked(hw))
2745                 return IXGBE_SUCCESS;
2746
2747         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2748         if (status != IXGBE_SUCCESS)
2749                 return status;
2750
2751         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2752
2753         if (status != IXGBE_SUCCESS)
2754                 return status;
2755
2756         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2757          * disabled, then force link down by entering low power mode.
2758          */
2759         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2760             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2761                 return ixgbe_set_copper_phy_power(hw, FALSE);
2762
2763         /* Determine LCD */
2764         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2765
2766         if (status != IXGBE_SUCCESS)
2767                 return status;
2768
2769         /* If no valid LCD link speed, then force link down and exit. */
2770         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2771                 return ixgbe_set_copper_phy_power(hw, FALSE);
2772
2773         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2774                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2775                                       &speed);
2776
2777         if (status != IXGBE_SUCCESS)
2778                 return status;
2779
2780         /* If no link now, speed is invalid so take link down */
2781         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2782         if (status != IXGBE_SUCCESS)
2783                 return ixgbe_set_copper_phy_power(hw, false);
2784
2785         /* clear everything but the speed bits */
2786         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2787
2788         /* If current speed is already LCD, then exit. */
2789         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2790              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2791             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2792              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2793                 return status;
2794
2795         /* Clear AN completed indication */
2796         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2797                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2798                                       &autoneg_reg);
2799
2800         if (status != IXGBE_SUCCESS)
2801                 return status;
2802
2803         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2804                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2805                              &an_10g_cntl_reg);
2806
2807         if (status != IXGBE_SUCCESS)
2808                 return status;
2809
2810         status = hw->phy.ops.read_reg(hw,
2811                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2812                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2813                              &autoneg_reg);
2814
2815         if (status != IXGBE_SUCCESS)
2816                 return status;
2817
2818         save_autoneg = hw->phy.autoneg_advertised;
2819
2820         /* Setup link at least common link speed */
2821         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2822
2823         /* restore autoneg from before setting lplu speed */
2824         hw->phy.autoneg_advertised = save_autoneg;
2825
2826         return status;
2827 }
2828
2829 /**
2830  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2831  *  @hw: pointer to hardware structure
2832  *  @lcd_speed: pointer to lowest common link speed
2833  *
2834  * Determine lowest common link speed with link partner.
2835  **/
2836 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2837 {
2838         u16 an_lp_status;
2839         s32 status;
2840         u16 word = hw->eeprom.ctrl_word_3;
2841
2842         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2843
2844         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2845                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2846                                       &an_lp_status);
2847
2848         if (status != IXGBE_SUCCESS)
2849                 return status;
2850
2851         /* If link partner advertised 1G, return 1G */
2852         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2853                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2854                 return status;
2855         }
2856
2857         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2858         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2859             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2860                 return status;
2861
2862         /* Link partner not capable of lower speeds, return 10G */
2863         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2864         return status;
2865 }
2866
2867 /**
2868  *  ixgbe_setup_fc_X550em - Set up flow control
2869  *  @hw: pointer to hardware structure
2870  *
2871  *  Called at init time to set up flow control.
2872  **/
2873 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2874 {
2875         s32 ret_val = IXGBE_SUCCESS;
2876         u32 pause, asm_dir, reg_val;
2877
2878         DEBUGFUNC("ixgbe_setup_fc_X550em");
2879
2880         /* Validate the requested mode */
2881         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2882                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2883                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2884                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2885                 goto out;
2886         }
2887
2888         /* 10gig parts do not have a word in the EEPROM to determine the
2889          * default flow control setting, so we explicitly set it to full.
2890          */
2891         if (hw->fc.requested_mode == ixgbe_fc_default)
2892                 hw->fc.requested_mode = ixgbe_fc_full;
2893
2894         /* Determine PAUSE and ASM_DIR bits. */
2895         switch (hw->fc.requested_mode) {
2896         case ixgbe_fc_none:
2897                 pause = 0;
2898                 asm_dir = 0;
2899                 break;
2900         case ixgbe_fc_tx_pause:
2901                 pause = 0;
2902                 asm_dir = 1;
2903                 break;
2904         case ixgbe_fc_rx_pause:
2905                 /* Rx Flow control is enabled and Tx Flow control is
2906                  * disabled by software override. Since there really
2907                  * isn't a way to advertise that we are capable of RX
2908                  * Pause ONLY, we will advertise that we support both
2909                  * symmetric and asymmetric Rx PAUSE, as such we fall
2910                  * through to the fc_full statement.  Later, we will
2911                  * disable the adapter's ability to send PAUSE frames.
2912                  */
2913         case ixgbe_fc_full:
2914                 pause = 1;
2915                 asm_dir = 1;
2916                 break;
2917         default:
2918                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2919                         "Flow control param set incorrectly\n");
2920                 ret_val = IXGBE_ERR_CONFIG;
2921                 goto out;
2922         }
2923
2924         if (hw->phy.media_type == ixgbe_media_type_backplane) {
2925                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2926                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2927                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2928                 if (ret_val != IXGBE_SUCCESS)
2929                         goto out;
2930                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2931                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2932                 if (pause)
2933                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2934                 if (asm_dir)
2935                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2936                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2937                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2938                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2939
2940                 /* Not all devices fully support AN. */
2941                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR)
2942                         hw->fc.disable_fc_autoneg = true;
2943         }
2944
2945 out:
2946         return ret_val;
2947 }
2948
2949 /**
2950  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2951  * @hw: pointer to hardware structure
2952  * @state: set mux if 1, clear if 0
2953  */
2954 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2955 {
2956         u32 esdp;
2957
2958         if (!hw->bus.lan_id)
2959                 return;
2960         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2961         if (state)
2962                 esdp |= IXGBE_ESDP_SDP1;
2963         else
2964                 esdp &= ~IXGBE_ESDP_SDP1;
2965         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2966         IXGBE_WRITE_FLUSH(hw);
2967 }
2968
2969 /**
2970  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2971  *  @hw: pointer to hardware structure
2972  *  @mask: Mask to specify which semaphore to acquire
2973  *
2974  *  Acquires the SWFW semaphore and sets the I2C MUX
2975  **/
2976 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2977 {
2978         s32 status;
2979
2980         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2981
2982         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2983         if (status)
2984                 return status;
2985
2986         if (mask & IXGBE_GSSR_I2C_MASK)
2987                 ixgbe_set_mux(hw, 1);
2988
2989         return IXGBE_SUCCESS;
2990 }
2991
2992 /**
2993  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2994  *  @hw: pointer to hardware structure
2995  *  @mask: Mask to specify which semaphore to release
2996  *
2997  *  Releases the SWFW semaphore and sets the I2C MUX
2998  **/
2999 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3000 {
3001         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3002
3003         if (mask & IXGBE_GSSR_I2C_MASK)
3004                 ixgbe_set_mux(hw, 0);
3005
3006         ixgbe_release_swfw_sync_X540(hw, mask);
3007 }
3008
3009 /**
3010  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
3011  * @hw: pointer to hardware structure
3012  *
3013  * Handle external Base T PHY interrupt. If high temperature
3014  * failure alarm then return error, else if link status change
3015  * then setup internal/external PHY link
3016  *
3017  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
3018  * failure alarm, else return PHY access status.
3019  */
3020 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
3021 {
3022         bool lsc;
3023         u32 status;
3024
3025         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
3026
3027         if (status != IXGBE_SUCCESS)
3028                 return status;
3029
3030         if (lsc)
3031                 return ixgbe_setup_internal_phy(hw);
3032
3033         return IXGBE_SUCCESS;
3034 }
3035
3036 /**
3037  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
3038  * @hw: pointer to hardware structure
3039  * @speed: new link speed
3040  * @autoneg_wait_to_complete: true when waiting for completion is needed
3041  *
3042  * Setup internal/external PHY link speed based on link speed, then set
3043  * external PHY auto advertised link speed.
3044  *
3045  * Returns error status for any failure
3046  **/
3047 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3048                                   ixgbe_link_speed speed,
3049                                   bool autoneg_wait_to_complete)
3050 {
3051         s32 status;
3052         ixgbe_link_speed force_speed;
3053
3054         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3055
3056         /* Setup internal/external PHY link speed to iXFI (10G), unless
3057          * only 1G is auto advertised then setup KX link.
3058          */
3059         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3060                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3061         else
3062                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3063
3064         /* If internal link mode is XFI, then setup XFI internal link. */
3065         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3066                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3067
3068                 if (status != IXGBE_SUCCESS)
3069                         return status;
3070         }
3071
3072         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3073 }
3074
3075 /**
3076  * ixgbe_check_link_t_X550em - Determine link and speed status
3077  * @hw: pointer to hardware structure
3078  * @speed: pointer to link speed
3079  * @link_up: true when link is up
3080  * @link_up_wait_to_complete: bool used to wait for link up or not
3081  *
3082  * Check that both the MAC and X557 external PHY have link.
3083  **/
3084 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3085                               bool *link_up, bool link_up_wait_to_complete)
3086 {
3087         u32 status;
3088         u16 autoneg_status;
3089
3090         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3091                 return IXGBE_ERR_CONFIG;
3092
3093         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3094                                               link_up_wait_to_complete);
3095
3096         /* If check link fails or MAC link is not up, then return */
3097         if (status != IXGBE_SUCCESS || !(*link_up))
3098                 return status;
3099
3100         /* MAC link is up, so check external PHY link.
3101          * Read this twice back to back to indicate current status.
3102          */
3103         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3104                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3105                                       &autoneg_status);
3106
3107         if (status != IXGBE_SUCCESS)
3108                 return status;
3109
3110         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3111                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3112                                       &autoneg_status);
3113
3114         if (status != IXGBE_SUCCESS)
3115                 return status;
3116
3117         /* If external PHY link is not up, then indicate link not up */
3118         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3119                 *link_up = false;
3120
3121         return IXGBE_SUCCESS;
3122 }
3123
3124 /**
3125  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3126  *  @hw: pointer to hardware structure
3127  **/
3128 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3129 {
3130         s32 status;
3131
3132         status = ixgbe_reset_phy_generic(hw);
3133
3134         if (status != IXGBE_SUCCESS)
3135                 return status;
3136
3137         /* Configure Link Status Alarm and Temperature Threshold interrupts */
3138         return ixgbe_enable_lasi_ext_t_x550em(hw);
3139 }
3140
3141 /**
3142  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
3143  *  @hw: pointer to hardware structure
3144  *  @led_idx: led number to turn on
3145  **/
3146 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3147 {
3148         u16 phy_data;
3149
3150         DEBUGFUNC("ixgbe_led_on_t_X550em");
3151
3152         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3153                 return IXGBE_ERR_PARAM;
3154
3155         /* To turn on the LED, set mode to ON. */
3156         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3157                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3158         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3159         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3160                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3161
3162         return IXGBE_SUCCESS;
3163 }
3164
3165 /**
3166  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3167  *  @hw: pointer to hardware structure
3168  *  @led_idx: led number to turn off
3169  **/
3170 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3171 {
3172         u16 phy_data;
3173
3174         DEBUGFUNC("ixgbe_led_off_t_X550em");
3175
3176         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3177                 return IXGBE_ERR_PARAM;
3178
3179         /* To turn on the LED, set mode to ON. */
3180         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3181                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3182         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3183         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3184                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3185
3186         return IXGBE_SUCCESS;
3187 }