drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41
  42 /**
  43  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  44  *  @hw: pointer to hardware structure
  45  *
  46  *  Initialize the function pointers and assign the MAC type for X550.
  47  *  Does not touch the hardware.
  48  **/
  49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  50 {
  51         struct ixgbe_mac_info *mac = &hw->mac;
  52         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  53         s32 ret_val;
  54
  55         DEBUGFUNC("ixgbe_init_ops_X550");
  56
  57         ret_val = ixgbe_init_ops_X540(hw);
  58         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  59         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  60         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  61         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  62         mac->ops.set_source_address_pruning =
  63                         ixgbe_set_source_address_pruning_X550;
  64         mac->ops.set_ethertype_anti_spoofing =
  65                         ixgbe_set_ethertype_anti_spoofing_X550;
  66
  67         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  68         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  69         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  70         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  71         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  72         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  73         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  74         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  75         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  76
  77         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  78         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  79         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  80         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  81         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  82         return ret_val;
  83 }
  84
  85 /**
  86  * ixgbe_read_cs4227 - Read CS4227 register
  87  * @hw: pointer to hardware structure
  88  * @reg: register number to write
  89  * @value: pointer to receive value read
  90  *
  91  * Returns status code
  92  **/
  93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  94 {
  95         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
  96 }
  97
  98 /**
  99  * ixgbe_write_cs4227 - Write CS4227 register
 100  * @hw: pointer to hardware structure
 101  * @reg: register number to write
 102  * @value: value to write to register
 103  *
 104  * Returns status code
 105  **/
 106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 107 {
 108         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 109 }
 110
 111 /**
 112  * ixgbe_get_cs4227_status - Return CS4227 status
 113  * @hw: pointer to hardware structure
 114  *
 115  * Returns error if CS4227 not successfully initialized
 116  **/
 117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
 118 {
 119         s32 status;
 120         u16 value = 0;
 121         u8 retry;
 122
 123         for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
 124                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
 125                                            &value);
 126                 if (status != IXGBE_SUCCESS)
 127                         return status;
 128                 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
 129                         break;
 130                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 131         }
 132         if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
 133                 return IXGBE_ERR_PHY;
 134
 135         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 136                                     IXGBE_CS4227_SCRATCH_VALUE);
 137         if (status != IXGBE_SUCCESS)
 138                 return status;
 139         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 140         if (status != IXGBE_SUCCESS)
 141                 return status;
 142         if (value != IXGBE_CS4227_SCRATCH_VALUE)
 143                 return IXGBE_ERR_PHY;
 144         return IXGBE_SUCCESS;
 145 }
 146
 147 /**
 148  * ixgbe_read_pe - Read register from port expander
 149  * @hw: pointer to hardware structure
 150  * @reg: register number to read
 151  * @value: pointer to receive read value
 152  *
 153  * Returns status code
 154  **/
 155 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 156 {
 157         s32 status;
 158
 159         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 160         if (status != IXGBE_SUCCESS)
 161                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 162                               "port expander access failed with %d\n", status);
 163         return status;
 164 }
 165
 166 /**
 167  * ixgbe_write_pe - Write register to port expander
 168  * @hw: pointer to hardware structure
 169  * @reg: register number to write
 170  * @value: value to write
 171  *
 172  * Returns status code
 173  **/
 174 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 175 {
 176         s32 status;
 177
 178         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 179         if (status != IXGBE_SUCCESS)
 180                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 181                               "port expander access failed with %d\n", status);
 182         return status;
 183 }
 184
 185 /**
 186  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 187  * @hw: pointer to hardware structure
 188  *
 189  * Returns error code
 190  **/
 191 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 192 {
 193         s32 status;
 194         u8 reg;
 195
 196         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199         reg |= IXGBE_PE_BIT1;
 200         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 201         if (status != IXGBE_SUCCESS)
 202                 return status;
 203
 204         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 205         if (status != IXGBE_SUCCESS)
 206                 return status;
 207         reg &= ~IXGBE_PE_BIT1;
 208         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 209         if (status != IXGBE_SUCCESS)
 210                 return status;
 211
 212         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 213         if (status != IXGBE_SUCCESS)
 214                 return status;
 215         reg &= ~IXGBE_PE_BIT1;
 216         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 217         if (status != IXGBE_SUCCESS)
 218                 return status;
 219
 220         usec_delay(IXGBE_CS4227_RESET_HOLD);
 221
 222         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 223         if (status != IXGBE_SUCCESS)
 224                 return status;
 225         reg |= IXGBE_PE_BIT1;
 226         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 227         if (status != IXGBE_SUCCESS)
 228                 return status;
 229
 230         msec_delay(IXGBE_CS4227_RESET_DELAY);
 231
 232         return IXGBE_SUCCESS;
 233 }
 234
 235 /**
 236  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 237  * @hw: pointer to hardware structure
 238  **/
 239 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 240 {
 241         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 242         s32 status;
 243         u8 retry;
 244
 245         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 246                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 247                 if (status != IXGBE_SUCCESS) {
 248                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 249                                       "semaphore failed with %d\n", status);
 250                         return;
 251                 }
 252                 status = ixgbe_get_cs4227_status(hw);
 253                 if (status == IXGBE_SUCCESS) {
 254                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 255                         msec_delay(hw->eeprom.semaphore_delay);
 256                         return;
 257                 }
 258                 ixgbe_reset_cs4227(hw);
 259                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 260                 msec_delay(hw->eeprom.semaphore_delay);
 261         }
 262         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 263                       "Unable to initialize CS4227, err=%d\n", status);
 264 }
 265
 266 /**
 267  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 268  * @hw: pointer to hardware structure
 269  **/
 270 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 271 {
 272         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 273
 274         if (hw->bus.lan_id) {
 275                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 276                 esdp |= IXGBE_ESDP_SDP1_DIR;
 277         }
 278         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 279         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 280         IXGBE_WRITE_FLUSH(hw);
 281 }
 282
 283 /**
 284  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 285  * @hw: pointer to hardware structure
 286  *
 287  * Returns error code
 288  */
 289 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 290 {
 291         switch (hw->device_id) {
 292         case IXGBE_DEV_ID_X550EM_X_SFP:
 293                 /* set up for CS4227 usage */
 294                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 295                 ixgbe_setup_mux_ctl(hw);
 296                 ixgbe_check_cs4227(hw);
 297
 298                 return ixgbe_identify_module_generic(hw);
 299                 break;
 300         case IXGBE_DEV_ID_X550EM_X_KX4:
 301                 hw->phy.type = ixgbe_phy_x550em_kx4;
 302                 break;
 303         case IXGBE_DEV_ID_X550EM_X_KR:
 304                 hw->phy.type = ixgbe_phy_x550em_kr;
 305                 break;
 306         case IXGBE_DEV_ID_X550EM_X_1G_T:
 307         case IXGBE_DEV_ID_X550EM_X_10G_T:
 308                 return ixgbe_identify_phy_generic(hw);
 309         default:
 310                 break;
 311         }
 312         return IXGBE_SUCCESS;
 313 }
 314
 315 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 316                                      u32 device_type, u16 *phy_data)
 317 {
 318         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 319         return IXGBE_NOT_IMPLEMENTED;
 320 }
 321
 322 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 323                                       u32 device_type, u16 phy_data)
 324 {
 325         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 326         return IXGBE_NOT_IMPLEMENTED;
 327 }
 328
 329 /**
 330 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 331 *  @hw: pointer to hardware structure
 332 *
 333 *  Initialize the function pointers and for MAC type X550EM.
 334 *  Does not touch the hardware.
 335 **/
 336 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 337 {
 338         struct ixgbe_mac_info *mac = &hw->mac;
 339         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 340         struct ixgbe_phy_info *phy = &hw->phy;
 341         s32 ret_val;
 342
 343         DEBUGFUNC("ixgbe_init_ops_X550EM");
 344
 345         /* Similar to X550 so start there. */
 346         ret_val = ixgbe_init_ops_X550(hw);
 347
 348         /* Since this function eventually calls
 349          * ixgbe_init_ops_540 by design, we are setting
 350          * the pointers to NULL explicitly here to overwrite
 351          * the values being set in the x540 function.
 352          */
 353         /* Thermal sensor not supported in x550EM */
 354         mac->ops.get_thermal_sensor_data = NULL;
 355         mac->ops.init_thermal_sensor_thresh = NULL;
 356         mac->thermal_sensor_enabled = false;
 357
 358         /* FCOE not supported in x550EM */
 359         mac->ops.get_san_mac_addr = NULL;
 360         mac->ops.set_san_mac_addr = NULL;
 361         mac->ops.get_wwn_prefix = NULL;
 362         mac->ops.get_fcoe_boot_status = NULL;
 363
 364         /* IPsec not supported in x550EM */
 365         mac->ops.disable_sec_rx_path = NULL;
 366         mac->ops.enable_sec_rx_path = NULL;
 367
 368         /* AUTOC register is not present in x550EM. */
 369         mac->ops.prot_autoc_read = NULL;
 370         mac->ops.prot_autoc_write = NULL;
 371
 372         /* X550EM bus type is internal*/
 373         hw->bus.type = ixgbe_bus_type_internal;
 374         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 375
 376         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 377         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 378         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 379         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 380         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 381         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 382         mac->ops.get_supported_physical_layer =
 383                                     ixgbe_get_supported_physical_layer_X550em;
 384
 385         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 386                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 387         else
 388                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 389
 390         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 391         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 392
 393         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
 394                 mac->ops.setup_eee = NULL;
 395
 396         /* PHY */
 397         phy->ops.init = ixgbe_init_phy_ops_X550em;
 398         phy->ops.identify = ixgbe_identify_phy_x550em;
 399         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 400                 phy->ops.set_phy_power = NULL;
 401
 402
 403         /* EEPROM */
 404         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 405         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 406         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 407         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 408         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 409         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 410         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 411         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 412
 413         return ret_val;
 414 }
 415
 416 /**
 417  *  ixgbe_dmac_config_X550
 418  *  @hw: pointer to hardware structure
 419  *
 420  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 421  *  When disabling dmac, dmac enable dmac bit is cleared.
 422  **/
 423 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 424 {
 425         u32 reg, high_pri_tc;
 426
 427         DEBUGFUNC("ixgbe_dmac_config_X550");
 428
 429         /* Disable DMA coalescing before configuring */
 430         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 431         reg &= ~IXGBE_DMACR_DMAC_EN;
 432         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 433
 434         /* Disable DMA Coalescing if the watchdog timer is 0 */
 435         if (!hw->mac.dmac_config.watchdog_timer)
 436                 goto out;
 437
 438         ixgbe_dmac_config_tcs_X550(hw);
 439
 440         /* Configure DMA Coalescing Control Register */
 441         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 442
 443         /* Set the watchdog timer in units of 40.96 usec */
 444         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 445         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 446
 447         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 448         /* If fcoe is enabled, set high priority traffic class */
 449         if (hw->mac.dmac_config.fcoe_en) {
 450                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 451                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 452                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 453         }
 454         reg |= IXGBE_DMACR_EN_MNG_IND;
 455
 456         /* Enable DMA coalescing after configuration */
 457         reg |= IXGBE_DMACR_DMAC_EN;
 458         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 459
 460 out:
 461         return IXGBE_SUCCESS;
 462 }
 463
 464 /**
 465  *  ixgbe_dmac_config_tcs_X550
 466  *  @hw: pointer to hardware structure
 467  *
 468  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 469  *  be cleared before configuring.
 470  **/
 471 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 472 {
 473         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 474
 475         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 476
 477         /* Configure DMA coalescing enabled */
 478         switch (hw->mac.dmac_config.link_speed) {
 479         case IXGBE_LINK_SPEED_100_FULL:
 480                 pb_headroom = IXGBE_DMACRXT_100M;
 481                 break;
 482         case IXGBE_LINK_SPEED_1GB_FULL:
 483                 pb_headroom = IXGBE_DMACRXT_1G;
 484                 break;
 485         default:
 486                 pb_headroom = IXGBE_DMACRXT_10G;
 487                 break;
 488         }
 489
 490         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 491                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 492
 493         /* Set the per Rx packet buffer receive threshold */
 494         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 495                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 496                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 497
 498                 if (tc < hw->mac.dmac_config.num_tcs) {
 499                         /* Get Rx PB size */
 500                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 501                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 502                                 IXGBE_RXPBSIZE_SHIFT;
 503
 504                         /* Calculate receive buffer threshold in kilobytes */
 505                         if (rx_pb_size > pb_headroom)
 506                                 rx_pb_size = rx_pb_size - pb_headroom;
 507                         else
 508                                 rx_pb_size = 0;
 509
 510                         /* Minimum of MFS shall be set for DMCTH */
 511                         reg |= (rx_pb_size > maxframe_size_kb) ?
 512                                 rx_pb_size : maxframe_size_kb;
 513                 }
 514                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 515         }
 516         return IXGBE_SUCCESS;
 517 }
 518
 519 /**
 520  *  ixgbe_dmac_update_tcs_X550
 521  *  @hw: pointer to hardware structure
 522  *
 523  *  Disables dmac, updates per TC settings, and then enables dmac.
 524  **/
 525 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 526 {
 527         u32 reg;
 528
 529         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 530
 531         /* Disable DMA coalescing before configuring */
 532         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 533         reg &= ~IXGBE_DMACR_DMAC_EN;
 534         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 535
 536         ixgbe_dmac_config_tcs_X550(hw);
 537
 538         /* Enable DMA coalescing after configuration */
 539         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 540         reg |= IXGBE_DMACR_DMAC_EN;
 541         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 542
 543         return IXGBE_SUCCESS;
 544 }
 545
 546 /**
 547  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 548  *  @hw: pointer to hardware structure
 549  *
 550  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 551  *  ixgbe_hw struct in order to set up EEPROM access.
 552  **/
 553 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 554 {
 555         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 556         u32 eec;
 557         u16 eeprom_size;
 558
 559         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 560
 561         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 562                 eeprom->semaphore_delay = 10;
 563                 eeprom->type = ixgbe_flash;
 564
 565                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 566                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 567                                     IXGBE_EEC_SIZE_SHIFT);
 568                 eeprom->word_size = 1 << (eeprom_size +
 569                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 570
 571                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 572                           eeprom->type, eeprom->word_size);
 573         }
 574
 575         return IXGBE_SUCCESS;
 576 }
 577
 578 /**
 579  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 580  *  @hw: pointer to the HW structure
 581  *  @enable_eee: boolean flag to enable EEE
 582  *
 583  *  Enable/disable EEE based on enable_eee flag.
 584  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 585  *  are modified.
 586  *
 587  **/
 588 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 589 {
 590         u32 eeer;
 591         u16 autoneg_eee_reg;
 592         u32 link_reg;
 593         s32 status;
 594
 595         DEBUGFUNC("ixgbe_setup_eee_X550");
 596
 597         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 598         /* Enable or disable EEE per flag */
 599         if (enable_eee) {
 600                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 601
 602                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 603                         /* Advertise EEE capability */
 604                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 605                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 606
 607                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 608                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 609                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 610
 611                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 612                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 613                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 614                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 615                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 616                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 617                         if (status != IXGBE_SUCCESS)
 618                                 return status;
 619
 620                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 621                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 622
 623                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 624                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 625                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 626                         if (status != IXGBE_SUCCESS)
 627                                 return status;
 628                 }
 629         } else {
 630                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 631
 632                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 633                         /* Disable advertised EEE capability */
 634                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 635                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 636
 637                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 638                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 639                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 640
 641                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 642                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 643                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 644                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 645                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 646                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 647                         if (status != IXGBE_SUCCESS)
 648                                 return status;
 649
 650                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 651                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 652
 653                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 654                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 655                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 656                         if (status != IXGBE_SUCCESS)
 657                                 return status;
 658                 }
 659         }
 660         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 661
 662         return IXGBE_SUCCESS;
 663 }
 664
 665 /**
 666  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 667  * @hw: pointer to hardware structure
 668  * @enable: enable or disable source address pruning
 669  * @pool: Rx pool to set source address pruning for
 670  **/
 671 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 672                                            unsigned int pool)
 673 {
 674         u64 pfflp;
 675
 676         /* max rx pool is 63 */
 677         if (pool > 63)
 678                 return;
 679
 680         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 681         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 682
 683         if (enable)
 684                 pfflp |= (1ULL << pool);
 685         else
 686                 pfflp &= ~(1ULL << pool);
 687
 688         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 689         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 690 }
 691
 692 /**
 693  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 694  *  @hw: pointer to hardware structure
 695  *  @enable: enable or disable switch for Ethertype anti-spoofing
 696  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 697  *
 698  **/
 699 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 700                 bool enable, int vf)
 701 {
 702         int vf_target_reg = vf >> 3;
 703         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 704         u32 pfvfspoof;
 705
 706         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 707
 708         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 709         if (enable)
 710                 pfvfspoof |= (1 << vf_target_shift);
 711         else
 712                 pfvfspoof &= ~(1 << vf_target_shift);
 713
 714         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 715 }
 716
 717 /**
 718  * ixgbe_iosf_wait - Wait for IOSF command completion
 719  * @hw: pointer to hardware structure
 720  * @ctrl: pointer to location to receive final IOSF control value
 721  *
 722  * Returns failing status on timeout
 723  *
 724  * Note: ctrl can be NULL if the IOSF control register value is not needed
 725  **/
 726 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 727 {
 728         u32 i, command = 0;
 729
 730         /* Check every 10 usec to see if the address cycle completed.
 731          * The SB IOSF BUSY bit will clear when the operation is
 732          * complete
 733          */
 734         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 735                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 736                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 737                         break;
 738                 usec_delay(10);
 739         }
 740         if (ctrl)
 741                 *ctrl = command;
 742         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 743                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
 744                 return IXGBE_ERR_PHY;
 745         }
 746
 747         return IXGBE_SUCCESS;
 748 }
 749
 750 /**
 751  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 752  *  device
 753  *  @hw: pointer to hardware structure
 754  *  @reg_addr: 32 bit PHY register to write
 755  *  @device_type: 3 bit device type
 756  *  @data: Data to write to the register
 757  **/
 758 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 759                             u32 device_type, u32 data)
 760 {
 761         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 762         u32 command, error;
 763         s32 ret;
 764
 765         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 766         if (ret != IXGBE_SUCCESS)
 767                 return ret;
 768
 769         ret = ixgbe_iosf_wait(hw, NULL);
 770         if (ret != IXGBE_SUCCESS)
 771                 goto out;
 772
 773         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 774                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 775
 776         /* Write IOSF control register */
 777         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 778
 779         /* Write IOSF data register */
 780         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 781
 782         ret = ixgbe_iosf_wait(hw, &command);
 783
 784         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 785                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 786                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 787                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 788                               "Failed to write, error %x\n", error);
 789                 ret = IXGBE_ERR_PHY;
 790         }
 791
 792 out:
 793         ixgbe_release_swfw_semaphore(hw, gssr);
 794         return ret;
 795 }
 796
 797 /**
 798  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 799  *  device
 800  *  @hw: pointer to hardware structure
 801  *  @reg_addr: 32 bit PHY register to write
 802  *  @device_type: 3 bit device type
 803  *  @phy_data: Pointer to read data from the register
 804  **/
 805 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 806                            u32 device_type, u32 *data)
 807 {
 808         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 809         u32 command, error;
 810         s32 ret;
 811
 812         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 813         if (ret != IXGBE_SUCCESS)
 814                 return ret;
 815
 816         ret = ixgbe_iosf_wait(hw, NULL);
 817         if (ret != IXGBE_SUCCESS)
 818                 goto out;
 819
 820         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 821                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 822
 823         /* Write IOSF control register */
 824         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 825
 826         ret = ixgbe_iosf_wait(hw, &command);
 827
 828         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 829                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 830                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 831                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 832                                 "Failed to read, error %x\n", error);
 833                 ret = IXGBE_ERR_PHY;
 834         }
 835
 836         if (ret == IXGBE_SUCCESS)
 837                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 838
 839 out:
 840         ixgbe_release_swfw_semaphore(hw, gssr);
 841         return ret;
 842 }
 843
 844 /**
 845  *  ixgbe_disable_mdd_X550
 846  *  @hw: pointer to hardware structure
 847  *
 848  *  Disable malicious driver detection
 849  **/
 850 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 851 {
 852         u32 reg;
 853
 854         DEBUGFUNC("ixgbe_disable_mdd_X550");
 855
 856         /* Disable MDD for TX DMA and interrupt */
 857         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 858         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 859         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 860
 861         /* Disable MDD for RX and interrupt */
 862         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 863         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 864         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 865 }
 866
 867 /**
 868  *  ixgbe_enable_mdd_X550
 869  *  @hw: pointer to hardware structure
 870  *
 871  *  Enable malicious driver detection
 872  **/
 873 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 874 {
 875         u32 reg;
 876
 877         DEBUGFUNC("ixgbe_enable_mdd_X550");
 878
 879         /* Enable MDD for TX DMA and interrupt */
 880         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 881         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 882         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 883
 884         /* Enable MDD for RX and interrupt */
 885         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 886         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 887         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 888 }
 889
 890 /**
 891  *  ixgbe_restore_mdd_vf_X550
 892  *  @hw: pointer to hardware structure
 893  *  @vf: vf index
 894  *
 895  *  Restore VF that was disabled during malicious driver detection event
 896  **/
 897 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 898 {
 899         u32 idx, reg, num_qs, start_q, bitmask;
 900
 901         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 902
 903         /* Map VF to queues */
 904         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 905         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 906         case IXGBE_MRQC_VMDQRT8TCEN:
 907                 num_qs = 8;  /* 16 VFs / pools */
 908                 bitmask = 0x000000FF;
 909                 break;
 910         case IXGBE_MRQC_VMDQRSS32EN:
 911         case IXGBE_MRQC_VMDQRT4TCEN:
 912                 num_qs = 4;  /* 32 VFs / pools */
 913                 bitmask = 0x0000000F;
 914                 break;
 915         default:            /* 64 VFs / pools */
 916                 num_qs = 2;
 917                 bitmask = 0x00000003;
 918                 break;
 919         }
 920         start_q = vf * num_qs;
 921
 922         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 923         idx = start_q / 32;
 924         reg = 0;
 925         reg |= (bitmask << (start_q % 32));
 926         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 927         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 928 }
 929
 930 /**
 931  *  ixgbe_mdd_event_X550
 932  *  @hw: pointer to hardware structure
 933  *  @vf_bitmap: vf bitmap of malicious vfs
 934  *
 935  *  Handle malicious driver detection event.
 936  **/
 937 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 938 {
 939         u32 wqbr;
 940         u32 i, j, reg, q, shift, vf, idx;
 941
 942         DEBUGFUNC("ixgbe_mdd_event_X550");
 943
 944         /* figure out pool size for mapping to vf's */
 945         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 946         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 947         case IXGBE_MRQC_VMDQRT8TCEN:
 948                 shift = 3;  /* 16 VFs / pools */
 949                 break;
 950         case IXGBE_MRQC_VMDQRSS32EN:
 951         case IXGBE_MRQC_VMDQRT4TCEN:
 952                 shift = 2;  /* 32 VFs / pools */
 953                 break;
 954         default:
 955                 shift = 1;  /* 64 VFs / pools */
 956                 break;
 957         }
 958
 959         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
 960         for (i = 0; i < 4; i++) {
 961                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
 962                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
 963
 964                 if (!wqbr)
 965                         continue;
 966
 967                 /* Get malicious queue */
 968                 for (j = 0; j < 32 && wqbr; j++) {
 969
 970                         if (!(wqbr & (1 << j)))
 971                                 continue;
 972
 973                         /* Get queue from bitmask */
 974                         q = j + (i * 32);
 975
 976                         /* Map queue to vf */
 977                         vf = (q >> shift);
 978
 979                         /* Set vf bit in vf_bitmap */
 980                         idx = vf / 32;
 981                         vf_bitmap[idx] |= (1 << (vf % 32));
 982                         wqbr &= ~(1 << j);
 983                 }
 984         }
 985 }
 986
 987 /**
 988  *  ixgbe_get_media_type_X550em - Get media type
 989  *  @hw: pointer to hardware structure
 990  *
 991  *  Returns the media type (fiber, copper, backplane)
 992  */
 993 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
 994 {
 995         enum ixgbe_media_type media_type;
 996
 997         DEBUGFUNC("ixgbe_get_media_type_X550em");
 998
 999         /* Detect if there is a copper PHY attached. */
1000         switch (hw->device_id) {
1001         case IXGBE_DEV_ID_X550EM_X_KR:
1002         case IXGBE_DEV_ID_X550EM_X_KX4:
1003                 media_type = ixgbe_media_type_backplane;
1004                 break;
1005         case IXGBE_DEV_ID_X550EM_X_SFP:
1006                 media_type = ixgbe_media_type_fiber;
1007                 break;
1008         case IXGBE_DEV_ID_X550EM_X_1G_T:
1009         case IXGBE_DEV_ID_X550EM_X_10G_T:
1010                 media_type = ixgbe_media_type_copper;
1011                 break;
1012         default:
1013                 media_type = ixgbe_media_type_unknown;
1014                 break;
1015         }
1016         return media_type;
1017 }
1018
1019 /**
1020  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1021  *  @hw: pointer to hardware structure
1022  *  @linear: true if SFP module is linear
1023  */
1024 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1025 {
1026         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1027
1028         switch (hw->phy.sfp_type) {
1029         case ixgbe_sfp_type_not_present:
1030                 return IXGBE_ERR_SFP_NOT_PRESENT;
1031         case ixgbe_sfp_type_da_cu_core0:
1032         case ixgbe_sfp_type_da_cu_core1:
1033                 *linear = true;
1034                 break;
1035         case ixgbe_sfp_type_srlr_core0:
1036         case ixgbe_sfp_type_srlr_core1:
1037         case ixgbe_sfp_type_da_act_lmt_core0:
1038         case ixgbe_sfp_type_da_act_lmt_core1:
1039         case ixgbe_sfp_type_1g_sx_core0:
1040         case ixgbe_sfp_type_1g_sx_core1:
1041         case ixgbe_sfp_type_1g_lx_core0:
1042         case ixgbe_sfp_type_1g_lx_core1:
1043                 *linear = false;
1044                 break;
1045         case ixgbe_sfp_type_unknown:
1046         case ixgbe_sfp_type_1g_cu_core0:
1047         case ixgbe_sfp_type_1g_cu_core1:
1048         default:
1049                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1050         }
1051
1052         return IXGBE_SUCCESS;
1053 }
1054
1055 /**
1056  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1057  *  @hw: pointer to hardware structure
1058  *
1059  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1060  **/
1061 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1062 {
1063         s32 status;
1064         bool linear;
1065
1066         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1067
1068         status = ixgbe_identify_module_generic(hw);
1069
1070         if (status != IXGBE_SUCCESS)
1071                 return status;
1072
1073         /* Check if SFP module is supported */
1074         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1075
1076         return status;
1077 }
1078
1079 /**
1080  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1081  *  @hw: pointer to hardware structure
1082  */
1083 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1084 {
1085         s32 status;
1086         bool linear;
1087
1088         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1089
1090         /* Check if SFP module is supported */
1091         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1092
1093         if (status != IXGBE_SUCCESS)
1094                 return status;
1095
1096         ixgbe_init_mac_link_ops_X550em(hw);
1097         hw->phy.ops.reset = NULL;
1098
1099         return IXGBE_SUCCESS;
1100 }
1101
1102 /**
1103  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1104  *  @hw: pointer to hardware structure
1105  */
1106 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1107 {
1108         struct ixgbe_mac_info *mac = &hw->mac;
1109
1110         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1111
1112          switch (hw->mac.ops.get_media_type(hw)) {
1113          case ixgbe_media_type_fiber:
1114                 /* CS4227 does not support autoneg, so disable the laser control
1115                  * functions for SFP+ fiber
1116                  */
1117                 mac->ops.disable_tx_laser = NULL;
1118                 mac->ops.enable_tx_laser = NULL;
1119                 mac->ops.flap_tx_laser = NULL;
1120                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1121                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1122                 mac->ops.set_rate_select_speed =
1123                                         ixgbe_set_soft_rate_select_speed;
1124                 break;
1125         case ixgbe_media_type_copper:
1126                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1127                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1128                 break;
1129         default:
1130                 break;
1131          }
1132 }
1133
1134 /**
1135  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1136  *  @hw: pointer to hardware structure
1137  *  @speed: pointer to link speed
1138  *  @autoneg: true when autoneg or autotry is enabled
1139  */
1140 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1141                                        ixgbe_link_speed *speed,
1142                                        bool *autoneg)
1143 {
1144         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1145
1146         /* SFP */
1147         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1148
1149                 /* CS4227 SFP must not enable auto-negotiation */
1150                 *autoneg = false;
1151
1152                 /* Check if 1G SFP module. */
1153                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1154                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1155                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1156                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1157                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1158                         return IXGBE_SUCCESS;
1159                 }
1160
1161                 /* Link capabilities are based on SFP */
1162                 if (hw->phy.multispeed_fiber)
1163                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1164                                  IXGBE_LINK_SPEED_1GB_FULL;
1165                 else
1166                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1167         } else {
1168                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1169                          IXGBE_LINK_SPEED_1GB_FULL;
1170                 *autoneg = true;
1171         }
1172
1173         return IXGBE_SUCCESS;
1174 }
1175
1176 /**
1177  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1178  * @hw: pointer to hardware structure
1179  * @lsc: pointer to boolean flag which indicates whether external Base T
1180  *       PHY interrupt is lsc
1181  *
1182  * Determime if external Base T PHY interrupt cause is high temperature
1183  * failure alarm or link status change.
1184  *
1185  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1186  * failure alarm, else return PHY access status.
1187  */
1188 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1189 {
1190         u32 status;
1191         u16 reg;
1192
1193         *lsc = false;
1194
1195         /* Vendor alarm triggered */
1196         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1197                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1198                                       &reg);
1199
1200         if (status != IXGBE_SUCCESS ||
1201             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1202                 return status;
1203
1204         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1205         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1206                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1207                                       &reg);
1208
1209         if (status != IXGBE_SUCCESS ||
1210             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1211             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1212                 return status;
1213
1214         /* High temperature failure alarm triggered */
1215         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1216                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1217                                       &reg);
1218
1219         if (status != IXGBE_SUCCESS)
1220                 return status;
1221
1222         /* If high temperature failure, then return over temp error and exit */
1223         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1224                 /* power down the PHY in case the PHY FW didn't already */
1225                 ixgbe_set_copper_phy_power(hw, false);
1226                 return IXGBE_ERR_OVERTEMP;
1227         }
1228
1229         /* Vendor alarm 2 triggered */
1230         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1231                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1232
1233         if (status != IXGBE_SUCCESS ||
1234             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1235                 return status;
1236
1237         /* link connect/disconnect event occurred */
1238         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1239                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1240
1241         if (status != IXGBE_SUCCESS)
1242                 return status;
1243
1244         /* Indicate LSC */
1245         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1246                 *lsc = true;
1247
1248         return IXGBE_SUCCESS;
1249 }
1250
1251 /**
1252  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1253  * @hw: pointer to hardware structure
1254  *
1255  * Enable link status change and temperature failure alarm for the external
1256  * Base T PHY
1257  *
1258  * Returns PHY access status
1259  */
1260 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1261 {
1262         u32 status;
1263         u16 reg;
1264         bool lsc;
1265
1266         /* Clear interrupt flags */
1267         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1268
1269         /* Enable link status change alarm */
1270         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1271                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1272
1273         if (status != IXGBE_SUCCESS)
1274                 return status;
1275
1276         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1277
1278         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1279                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1280
1281         if (status != IXGBE_SUCCESS)
1282                 return status;
1283
1284         /* Enables high temperature failure alarm */
1285         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1286                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1287                                       &reg);
1288
1289         if (status != IXGBE_SUCCESS)
1290                 return status;
1291
1292         reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1293
1294         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1295                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1296                                        reg);
1297
1298         if (status != IXGBE_SUCCESS)
1299                 return status;
1300
1301         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1302         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1303                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1304                                       &reg);
1305
1306         if (status != IXGBE_SUCCESS)
1307                 return status;
1308
1309         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1310                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1311
1312         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1313                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1314                                        reg);
1315
1316         if (status != IXGBE_SUCCESS)
1317                 return status;
1318
1319         /* Enable chip-wide vendor alarm */
1320         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1321                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1322                                       &reg);
1323
1324         if (status != IXGBE_SUCCESS)
1325                 return status;
1326
1327         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1328
1329         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1330                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1331                                        reg);
1332
1333         return status;
1334 }
1335
1336 /**
1337  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1338  *  @hw: pointer to hardware structure
1339  *
1340  *  Initialize any function pointers that were not able to be
1341  *  set during init_shared_code because the PHY/SFP type was
1342  *  not known.  Perform the SFP init if necessary.
1343  */
1344 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1345 {
1346         struct ixgbe_phy_info *phy = &hw->phy;
1347         s32 ret_val;
1348
1349         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1350
1351         hw->mac.ops.set_lan_id(hw);
1352
1353         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1354                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1355                 ixgbe_setup_mux_ctl(hw);
1356
1357                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1358         }
1359
1360         /* Identify the PHY or SFP module */
1361         ret_val = phy->ops.identify(hw);
1362         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1363                 return ret_val;
1364
1365         /* Setup function pointers based on detected hardware */
1366         ixgbe_init_mac_link_ops_X550em(hw);
1367         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1368                 phy->ops.reset = NULL;
1369
1370         /* Set functions pointers based on phy type */
1371         switch (hw->phy.type) {
1372         case ixgbe_phy_x550em_kx4:
1373                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1374                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1375                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1376                 break;
1377         case ixgbe_phy_x550em_kr:
1378                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1379                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1380                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1381                 break;
1382         case ixgbe_phy_x550em_ext_t:
1383                 phy->ops.setup_internal_link =
1384                                          ixgbe_setup_internal_phy_t_x550em;
1385                 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1386                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1387                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1388                 break;
1389         default:
1390                 break;
1391         }
1392         return ret_val;
1393 }
1394
1395 /**
1396  *  ixgbe_reset_hw_X550em - Perform hardware reset
1397  *  @hw: pointer to hardware structure
1398  *
1399  *  Resets the hardware by resetting the transmit and receive units, masks
1400  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1401  *  reset.
1402  */
1403 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1404 {
1405         ixgbe_link_speed link_speed;
1406         s32 status;
1407         u32 ctrl = 0;
1408         u32 i;
1409         bool link_up = false;
1410
1411         DEBUGFUNC("ixgbe_reset_hw_X550em");
1412
1413         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1414         status = hw->mac.ops.stop_adapter(hw);
1415         if (status != IXGBE_SUCCESS)
1416                 return status;
1417
1418         /* flush pending Tx transactions */
1419         ixgbe_clear_tx_pending(hw);
1420
1421         /* PHY ops must be identified and initialized prior to reset */
1422
1423         /* Identify PHY and related function pointers */
1424         status = hw->phy.ops.init(hw);
1425
1426         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1427                 return status;
1428
1429         /* start the external PHY */
1430         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1431                 status = ixgbe_init_ext_t_x550em(hw);
1432                 if (status)
1433                         return status;
1434         }
1435
1436         /* Setup SFP module if there is one present. */
1437         if (hw->phy.sfp_setup_needed) {
1438                 status = hw->mac.ops.setup_sfp(hw);
1439                 hw->phy.sfp_setup_needed = false;
1440         }
1441
1442         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1443                 return status;
1444
1445         /* Reset PHY */
1446         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1447                 hw->phy.ops.reset(hw);
1448
1449 mac_reset_top:
1450         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1451          * If link reset is used when link is up, it might reset the PHY when
1452          * mng is using it.  If link is down or the flag to force full link
1453          * reset is set, then perform link reset.
1454          */
1455         ctrl = IXGBE_CTRL_LNK_RST;
1456         if (!hw->force_full_reset) {
1457                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1458                 if (link_up)
1459                         ctrl = IXGBE_CTRL_RST;
1460         }
1461
1462         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1463         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1464         IXGBE_WRITE_FLUSH(hw);
1465
1466         /* Poll for reset bit to self-clear meaning reset is complete */
1467         for (i = 0; i < 10; i++) {
1468                 usec_delay(1);
1469                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1470                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1471                         break;
1472         }
1473
1474         if (ctrl & IXGBE_CTRL_RST_MASK) {
1475                 status = IXGBE_ERR_RESET_FAILED;
1476                 DEBUGOUT("Reset polling failed to complete.\n");
1477         }
1478
1479         msec_delay(50);
1480
1481         /* Double resets are required for recovery from certain error
1482          * conditions.  Between resets, it is necessary to stall to
1483          * allow time for any pending HW events to complete.
1484          */
1485         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1486                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1487                 goto mac_reset_top;
1488         }
1489
1490         /* Store the permanent mac address */
1491         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1492
1493         /* Store MAC address from RAR0, clear receive address registers, and
1494          * clear the multicast table.  Also reset num_rar_entries to 128,
1495          * since we modify this value when programming the SAN MAC address.
1496          */
1497         hw->mac.num_rar_entries = 128;
1498         hw->mac.ops.init_rx_addrs(hw);
1499
1500
1501         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1502                 ixgbe_setup_mux_ctl(hw);
1503
1504         return status;
1505 }
1506
1507 /**
1508  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1509  * @hw: pointer to hardware structure
1510  */
1511 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1512 {
1513         u32 status;
1514         u16 reg;
1515
1516         status = hw->phy.ops.read_reg(hw,
1517                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1518                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1519                                       &reg);
1520
1521         if (status != IXGBE_SUCCESS)
1522                 return status;
1523
1524         /* If PHY FW reset completed bit is set then this is the first
1525          * SW instance after a power on so the PHY FW must be un-stalled.
1526          */
1527         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1528                 status = hw->phy.ops.read_reg(hw,
1529                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1530                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1531                                         &reg);
1532
1533                 if (status != IXGBE_SUCCESS)
1534                         return status;
1535
1536                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1537
1538                 status = hw->phy.ops.write_reg(hw,
1539                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1540                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1541                                         reg);
1542
1543                 if (status != IXGBE_SUCCESS)
1544                         return status;
1545         }
1546
1547         return status;
1548 }
1549
1550 /**
1551  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1552  *  @hw: pointer to hardware structure
1553  *
1554  *  Configures the integrated KR PHY.
1555  **/
1556 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1557 {
1558         s32 status;
1559         u32 reg_val;
1560
1561         status = ixgbe_read_iosf_sb_reg_x550(hw,
1562                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1563                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1564         if (status)
1565                 return status;
1566
1567         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1568         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1569                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1570         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1571                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1572
1573         /* Advertise 10G support. */
1574         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1575                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1576
1577         /* Advertise 1G support. */
1578         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1579                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1580
1581         /* Restart auto-negotiation. */
1582         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1583         status = ixgbe_write_iosf_sb_reg_x550(hw,
1584                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1585                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1586
1587         return status;
1588 }
1589
1590 /**
1591  *  ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1592  *  @hw: pointer to hardware structure
1593  *
1594  *  Configures the integrated KX4 PHY.
1595  **/
1596 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1597 {
1598         s32 status;
1599         u32 reg_val;
1600
1601         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1602                 IXGBE_SB_IOSF_TARGET_KX4_PCS, &reg_val);
1603         if (status)
1604                 return status;
1605
1606         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1607                         IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1608
1609         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1610
1611         /* Advertise 10G support. */
1612         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1613                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1614
1615         /* Advertise 1G support. */
1616         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1617                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1618
1619         /* Restart auto-negotiation. */
1620         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1621         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1622                 IXGBE_SB_IOSF_TARGET_KX4_PCS, reg_val);
1623
1624         return status;
1625 }
1626
1627 /**
1628  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1629  *  @hw: pointer to hardware structure
1630  *  @speed: the link speed to force
1631  *
1632  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1633  *  internal and external PHY at a specific speed, without autonegotiation.
1634  **/
1635 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1636 {
1637         s32 status;
1638         u32 reg_val;
1639
1640         /* Disable AN and force speed to 10G Serial. */
1641         status = ixgbe_read_iosf_sb_reg_x550(hw,
1642                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1643                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1644         if (status != IXGBE_SUCCESS)
1645                 return status;
1646
1647         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1648         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1649
1650         /* Select forced link speed for internal PHY. */
1651         switch (*speed) {
1652         case IXGBE_LINK_SPEED_10GB_FULL:
1653                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1654                 break;
1655         case IXGBE_LINK_SPEED_1GB_FULL:
1656                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1657                 break;
1658         default:
1659                 /* Other link speeds are not supported by internal KR PHY. */
1660                 return IXGBE_ERR_LINK_SETUP;
1661         }
1662
1663         status = ixgbe_write_iosf_sb_reg_x550(hw,
1664                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1665                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1666         if (status != IXGBE_SUCCESS)
1667                 return status;
1668
1669         /* Disable training protocol FSM. */
1670         status = ixgbe_read_iosf_sb_reg_x550(hw,
1671                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1672                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1673         if (status != IXGBE_SUCCESS)
1674                 return status;
1675         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1676         status = ixgbe_write_iosf_sb_reg_x550(hw,
1677                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1678                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1679         if (status != IXGBE_SUCCESS)
1680                 return status;
1681
1682         /* Disable Flex from training TXFFE. */
1683         status = ixgbe_read_iosf_sb_reg_x550(hw,
1684                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1685                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1686         if (status != IXGBE_SUCCESS)
1687                 return status;
1688         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1689         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1690         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1691         status = ixgbe_write_iosf_sb_reg_x550(hw,
1692                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1693                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1694         if (status != IXGBE_SUCCESS)
1695                 return status;
1696         status = ixgbe_read_iosf_sb_reg_x550(hw,
1697                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1698                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1699         if (status != IXGBE_SUCCESS)
1700                 return status;
1701         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1702         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1703         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1704         status = ixgbe_write_iosf_sb_reg_x550(hw,
1705                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1706                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1707         if (status != IXGBE_SUCCESS)
1708                 return status;
1709
1710         /* Enable override for coefficients. */
1711         status = ixgbe_read_iosf_sb_reg_x550(hw,
1712                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1713                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1714         if (status != IXGBE_SUCCESS)
1715                 return status;
1716         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1717         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1718         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1719         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1720         status = ixgbe_write_iosf_sb_reg_x550(hw,
1721                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1722                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1723         if (status != IXGBE_SUCCESS)
1724                 return status;
1725
1726         /* Toggle port SW reset by AN reset. */
1727         status = ixgbe_read_iosf_sb_reg_x550(hw,
1728                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1729                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1730         if (status != IXGBE_SUCCESS)
1731                 return status;
1732         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1733         status = ixgbe_write_iosf_sb_reg_x550(hw,
1734                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1735                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1736
1737         return status;
1738 }
1739
1740 /**
1741  *  ixgbe_setup_mac_link_sfp_x550em - Configure the CS4227 & KR PHY for SFP
1742  *  @hw: pointer to hardware structure
1743  *
1744  *  Configure the external CS4227 PHY and the integrated KR PHY for SFP support.
1745  **/
1746 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1747                                     ixgbe_link_speed speed,
1748                                     bool autoneg_wait_to_complete)
1749 {
1750         s32 ret_val;
1751         u16 reg_slice, reg_val;
1752         bool setup_linear = false;
1753         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1754
1755         /* Check if SFP module is supported and linear */
1756         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1757
1758         /* If no SFP module present, then return success. Return success since
1759          * there is no reason to configure CS4227 and SFP not present error is
1760          * not excepted in the setup MAC link flow.
1761          */
1762         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1763                 return IXGBE_SUCCESS;
1764
1765         if (ret_val != IXGBE_SUCCESS)
1766                 return ret_val;
1767
1768         /* Configure CS4227 for connection rate. */
1769         reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1770         reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1771         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1772                                            reg_val);
1773
1774         /* Configure CS4227 for connection type. */
1775         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1776         if (setup_linear)
1777                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1778         else
1779                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1780         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1781                                            reg_val);
1782
1783         reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1784         reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1785         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1786                                            reg_val);
1787
1788         /* Configure CS4227 for connection type. */
1789         reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1790         if (setup_linear)
1791                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1792         else
1793                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1794         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1795                                            reg_val);
1796
1797         /* Configure the internal PHY. */
1798         ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1799
1800         return ret_val;
1801 }
1802
1803 /**
1804  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1805  * @hw: point to hardware structure
1806  *
1807  * Configures the link between the integrated KR PHY and the external X557 PHY
1808  * The driver will call this function when it gets a link status change
1809  * interrupt from the X557 PHY. This function configures the link speed
1810  * between the PHYs to match the link speed of the BASE-T link.
1811  *
1812  * A return of a non-zero value indicates an error, and the base driver should
1813  * not report link up.
1814  */
1815 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1816 {
1817         u32 status;
1818         u16 autoneg_status, speed;
1819         ixgbe_link_speed force_speed;
1820
1821         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1822                 return IXGBE_ERR_CONFIG;
1823
1824         /* read this twice back to back to indicate current status */
1825         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1826                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1827                                       &autoneg_status);
1828         if (status != IXGBE_SUCCESS)
1829                 return status;
1830
1831         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1832                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1833                                       &autoneg_status);
1834         if (status != IXGBE_SUCCESS)
1835                 return status;
1836
1837         /* If link is not up, then there is no setup necessary so return  */
1838         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1839                 return IXGBE_SUCCESS;
1840
1841         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1842                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1843                                       &speed);
1844
1845         /* clear everything but the speed and duplex bits */
1846         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1847
1848         switch (speed) {
1849         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1850                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1851                 break;
1852         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1853                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1854                 break;
1855         default:
1856                 /* Internal PHY does not support anything else */
1857                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1858         }
1859
1860         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1861 }
1862
1863 /**
1864  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1865  *  @hw: pointer to hardware structure
1866  *
1867  *  Configures the integrated KR PHY to use internal loopback mode.
1868  **/
1869 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1870 {
1871         s32 status;
1872         u32 reg_val;
1873
1874         /* Disable AN and force speed to 10G Serial. */
1875         status = ixgbe_read_iosf_sb_reg_x550(hw,
1876                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1877                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1878         if (status != IXGBE_SUCCESS)
1879                 return status;
1880         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1881         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1882         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1883         status = ixgbe_write_iosf_sb_reg_x550(hw,
1884                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1885                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1886         if (status != IXGBE_SUCCESS)
1887                 return status;
1888
1889         /* Set near-end loopback clocks. */
1890         status = ixgbe_read_iosf_sb_reg_x550(hw,
1891                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1892                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1893         if (status != IXGBE_SUCCESS)
1894                 return status;
1895         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1896         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1897         status = ixgbe_write_iosf_sb_reg_x550(hw,
1898                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1899                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1900         if (status != IXGBE_SUCCESS)
1901                 return status;
1902
1903         /* Set loopback enable. */
1904         status = ixgbe_read_iosf_sb_reg_x550(hw,
1905                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1906                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1907         if (status != IXGBE_SUCCESS)
1908                 return status;
1909         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1910         status = ixgbe_write_iosf_sb_reg_x550(hw,
1911                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1912                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1913         if (status != IXGBE_SUCCESS)
1914                 return status;
1915
1916         /* Training bypass. */
1917         status = ixgbe_read_iosf_sb_reg_x550(hw,
1918                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1919                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1920         if (status != IXGBE_SUCCESS)
1921                 return status;
1922         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1923         status = ixgbe_write_iosf_sb_reg_x550(hw,
1924                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1925                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1926
1927         return status;
1928 }
1929
1930 /**
1931  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1932  *  assuming that the semaphore is already obtained.
1933  *  @hw: pointer to hardware structure
1934  *  @offset: offset of  word in the EEPROM to read
1935  *  @data: word read from the EEPROM
1936  *
1937  *  Reads a 16 bit word from the EEPROM using the hostif.
1938  **/
1939 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1940                                    u16 *data)
1941 {
1942         s32 status;
1943         struct ixgbe_hic_read_shadow_ram buffer;
1944
1945         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1946         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1947         buffer.hdr.req.buf_lenh = 0;
1948         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1949         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1950
1951         /* convert offset from words to bytes */
1952         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1953         /* one word */
1954         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1955
1956         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1957                                               sizeof(buffer),
1958                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1959
1960         if (status)
1961                 return status;
1962
1963         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1964                                           FW_NVM_DATA_OFFSET);
1965
1966         return 0;
1967 }
1968
1969 /**
1970  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1971  *  @hw: pointer to hardware structure
1972  *  @offset: offset of  word in the EEPROM to read
1973  *  @data: word read from the EEPROM
1974  *
1975  *  Reads a 16 bit word from the EEPROM using the hostif.
1976  **/
1977 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1978                               u16 *data)
1979 {
1980         s32 status = IXGBE_SUCCESS;
1981
1982         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1983
1984         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1985             IXGBE_SUCCESS) {
1986                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1987                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1988         } else {
1989                 status = IXGBE_ERR_SWFW_SYNC;
1990         }
1991
1992         return status;
1993 }
1994
1995 /**
1996  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1997  *  @hw: pointer to hardware structure
1998  *  @offset: offset of  word in the EEPROM to read
1999  *  @words: number of words
2000  *  @data: word(s) read from the EEPROM
2001  *
2002  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
2003  **/
2004 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2005                                      u16 offset, u16 words, u16 *data)
2006 {
2007         struct ixgbe_hic_read_shadow_ram buffer;
2008         u32 current_word = 0;
2009         u16 words_to_read;
2010         s32 status;
2011         u32 i;
2012
2013         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2014
2015         /* Take semaphore for the entire operation. */
2016         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2017         if (status) {
2018                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2019                 return status;
2020         }
2021         while (words) {
2022                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2023                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2024                 else
2025                         words_to_read = words;
2026
2027                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2028                 buffer.hdr.req.buf_lenh = 0;
2029                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2030                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2031
2032                 /* convert offset from words to bytes */
2033                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2034                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2035
2036                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2037                                                       sizeof(buffer),
2038                                                       IXGBE_HI_COMMAND_TIMEOUT,
2039                                                       false);
2040
2041                 if (status) {
2042                         DEBUGOUT("Host interface command failed\n");
2043                         goto out;
2044                 }
2045
2046                 for (i = 0; i < words_to_read; i++) {
2047                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2048                                   2 * i;
2049                         u32 value = IXGBE_READ_REG(hw, reg);
2050
2051                         data[current_word] = (u16)(value & 0xffff);
2052                         current_word++;
2053                         i++;
2054                         if (i < words_to_read) {
2055                                 value >>= 16;
2056                                 data[current_word] = (u16)(value & 0xffff);
2057                                 current_word++;
2058                         }
2059                 }
2060                 words -= words_to_read;
2061         }
2062
2063 out:
2064         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2065         return status;
2066 }
2067
2068 /**
2069  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2070  *  @hw: pointer to hardware structure
2071  *  @offset: offset of  word in the EEPROM to write
2072  *  @data: word write to the EEPROM
2073  *
2074  *  Write a 16 bit word to the EEPROM using the hostif.
2075  **/
2076 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2077                                     u16 data)
2078 {
2079         s32 status;
2080         struct ixgbe_hic_write_shadow_ram buffer;
2081
2082         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2083
2084         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2085         buffer.hdr.req.buf_lenh = 0;
2086         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2087         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2088
2089          /* one word */
2090         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2091         buffer.data = data;
2092         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2093
2094         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2095                                               sizeof(buffer),
2096                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2097
2098         return status;
2099 }
2100
2101 /**
2102  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2103  *  @hw: pointer to hardware structure
2104  *  @offset: offset of  word in the EEPROM to write
2105  *  @data: word write to the EEPROM
2106  *
2107  *  Write a 16 bit word to the EEPROM using the hostif.
2108  **/
2109 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2110                                u16 data)
2111 {
2112         s32 status = IXGBE_SUCCESS;
2113
2114         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2115
2116         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2117             IXGBE_SUCCESS) {
2118                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2119                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2120         } else {
2121                 DEBUGOUT("write ee hostif failed to get semaphore");
2122                 status = IXGBE_ERR_SWFW_SYNC;
2123         }
2124
2125         return status;
2126 }
2127
2128 /**
2129  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2130  *  @hw: pointer to hardware structure
2131  *  @offset: offset of  word in the EEPROM to write
2132  *  @words: number of words
2133  *  @data: word(s) write to the EEPROM
2134  *
2135  *  Write a 16 bit word(s) to the EEPROM using the hostif.
2136  **/
2137 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2138                                       u16 offset, u16 words, u16 *data)
2139 {
2140         s32 status = IXGBE_SUCCESS;
2141         u32 i = 0;
2142
2143         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2144
2145         /* Take semaphore for the entire operation. */
2146         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2147         if (status != IXGBE_SUCCESS) {
2148                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2149                 goto out;
2150         }
2151
2152         for (i = 0; i < words; i++) {
2153                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2154                                                          data[i]);
2155
2156                 if (status != IXGBE_SUCCESS) {
2157                         DEBUGOUT("Eeprom buffered write failed\n");
2158                         break;
2159                 }
2160         }
2161
2162         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2163 out:
2164
2165         return status;
2166 }
2167
2168 /**
2169  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2170  * @hw: pointer to hardware structure
2171  * @ptr: pointer offset in eeprom
2172  * @size: size of section pointed by ptr, if 0 first word will be used as size
2173  * @csum: address of checksum to update
2174  *
2175  * Returns error status for any failure
2176  */
2177 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2178                                    u16 size, u16 *csum, u16 *buffer,
2179                                    u32 buffer_size)
2180 {
2181         u16 buf[256];
2182         s32 status;
2183         u16 length, bufsz, i, start;
2184         u16 *local_buffer;
2185
2186         bufsz = sizeof(buf) / sizeof(buf[0]);
2187
2188         /* Read a chunk at the pointer location */
2189         if (!buffer) {
2190                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2191                 if (status) {
2192                         DEBUGOUT("Failed to read EEPROM image\n");
2193                         return status;
2194                 }
2195                 local_buffer = buf;
2196         } else {
2197                 if (buffer_size < ptr)
2198                         return  IXGBE_ERR_PARAM;
2199                 local_buffer = &buffer[ptr];
2200         }
2201
2202         if (size) {
2203                 start = 0;
2204                 length = size;
2205         } else {
2206                 start = 1;
2207                 length = local_buffer[0];
2208
2209                 /* Skip pointer section if length is invalid. */
2210                 if (length == 0xFFFF || length == 0 ||
2211                     (ptr + length) >= hw->eeprom.word_size)
2212                         return IXGBE_SUCCESS;
2213         }
2214
2215         if (buffer && ((u32)start + (u32)length > buffer_size))
2216                 return IXGBE_ERR_PARAM;
2217
2218         for (i = start; length; i++, length--) {
2219                 if (i == bufsz && !buffer) {
2220                         ptr += bufsz;
2221                         i = 0;
2222                         if (length < bufsz)
2223                                 bufsz = length;
2224
2225                         /* Read a chunk at the pointer location */
2226                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2227                                                                   bufsz, buf);
2228                         if (status) {
2229                                 DEBUGOUT("Failed to read EEPROM image\n");
2230                                 return status;
2231                         }
2232                 }
2233                 *csum += local_buffer[i];
2234         }
2235         return IXGBE_SUCCESS;
2236 }
2237
2238 /**
2239  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2240  *  @hw: pointer to hardware structure
2241  *  @buffer: pointer to buffer containing calculated checksum
2242  *  @buffer_size: size of buffer
2243  *
2244  *  Returns a negative error code on error, or the 16-bit checksum
2245  **/
2246 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2247 {
2248         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2249         u16 *local_buffer;
2250         s32 status;
2251         u16 checksum = 0;
2252         u16 pointer, i, size;
2253
2254         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2255
2256         hw->eeprom.ops.init_params(hw);
2257
2258         if (!buffer) {
2259                 /* Read pointer area */
2260                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2261                                                      IXGBE_EEPROM_LAST_WORD + 1,
2262                                                      eeprom_ptrs);
2263                 if (status) {
2264                         DEBUGOUT("Failed to read EEPROM image\n");
2265                         return status;
2266                 }
2267                 local_buffer = eeprom_ptrs;
2268         } else {
2269                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2270                         return IXGBE_ERR_PARAM;
2271                 local_buffer = buffer;
2272         }
2273
2274         /*
2275          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2276          * checksum word itself
2277          */
2278         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2279                 if (i != IXGBE_EEPROM_CHECKSUM)
2280                         checksum += local_buffer[i];
2281
2282         /*
2283          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2284          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2285          */
2286         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2287                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2288                         continue;
2289
2290                 pointer = local_buffer[i];
2291
2292                 /* Skip pointer section if the pointer is invalid. */
2293                 if (pointer == 0xFFFF || pointer == 0 ||
2294                     pointer >= hw->eeprom.word_size)
2295                         continue;
2296
2297                 switch (i) {
2298                 case IXGBE_PCIE_GENERAL_PTR:
2299                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2300                         break;
2301                 case IXGBE_PCIE_CONFIG0_PTR:
2302                 case IXGBE_PCIE_CONFIG1_PTR:
2303                         size = IXGBE_PCIE_CONFIG_SIZE;
2304                         break;
2305                 default:
2306                         size = 0;
2307                         break;
2308                 }
2309
2310                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2311                                                 buffer, buffer_size);
2312                 if (status)
2313                         return status;
2314         }
2315
2316         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2317
2318         return (s32)checksum;
2319 }
2320
2321 /**
2322  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2323  *  @hw: pointer to hardware structure
2324  *
2325  *  Returns a negative error code on error, or the 16-bit checksum
2326  **/
2327 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2328 {
2329         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2330 }
2331
2332 /**
2333  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2334  *  @hw: pointer to hardware structure
2335  *  @checksum_val: calculated checksum
2336  *
2337  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2338  *  caller does not need checksum_val, the value can be NULL.
2339  **/
2340 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2341 {
2342         s32 status;
2343         u16 checksum;
2344         u16 read_checksum = 0;
2345
2346         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2347
2348         /* Read the first word from the EEPROM. If this times out or fails, do
2349          * not continue or we could be in for a very long wait while every
2350          * EEPROM read fails
2351          */
2352         status = hw->eeprom.ops.read(hw, 0, &checksum);
2353         if (status) {
2354                 DEBUGOUT("EEPROM read failed\n");
2355                 return status;
2356         }
2357
2358         status = hw->eeprom.ops.calc_checksum(hw);
2359         if (status < 0)
2360                 return status;
2361
2362         checksum = (u16)(status & 0xffff);
2363
2364         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2365                                            &read_checksum);
2366         if (status)
2367                 return status;
2368
2369         /* Verify read checksum from EEPROM is the same as
2370          * calculated checksum
2371          */
2372         if (read_checksum != checksum) {
2373                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2374                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2375                              "Invalid EEPROM checksum");
2376         }
2377
2378         /* If the user cares, return the calculated checksum */
2379         if (checksum_val)
2380                 *checksum_val = checksum;
2381
2382         return status;
2383 }
2384
2385 /**
2386  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2387  * @hw: pointer to hardware structure
2388  *
2389  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2390  * checksum and updates the EEPROM and instructs the hardware to update
2391  * the flash.
2392  **/
2393 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2394 {
2395         s32 status;
2396         u16 checksum = 0;
2397
2398         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2399
2400         /* Read the first word from the EEPROM. If this times out or fails, do
2401          * not continue or we could be in for a very long wait while every
2402          * EEPROM read fails
2403          */
2404         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2405         if (status) {
2406                 DEBUGOUT("EEPROM read failed\n");
2407                 return status;
2408         }
2409
2410         status = ixgbe_calc_eeprom_checksum_X550(hw);
2411         if (status < 0)
2412                 return status;
2413
2414         checksum = (u16)(status & 0xffff);
2415
2416         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2417                                             checksum);
2418         if (status)
2419                 return status;
2420
2421         status = ixgbe_update_flash_X550(hw);
2422
2423         return status;
2424 }
2425
2426 /**
2427  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2428  *  @hw: pointer to hardware structure
2429  *
2430  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2431  **/
2432 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2433 {
2434         s32 status = IXGBE_SUCCESS;
2435         union ixgbe_hic_hdr2 buffer;
2436
2437         DEBUGFUNC("ixgbe_update_flash_X550");
2438
2439         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2440         buffer.req.buf_lenh = 0;
2441         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2442         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2443
2444         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2445                                               sizeof(buffer),
2446                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2447
2448         return status;
2449 }
2450
2451 /**
2452  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2453  *  @hw: pointer to hardware structure
2454  *
2455  *  Determines physical layer capabilities of the current configuration.
2456  **/
2457 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2458 {
2459         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2460         u16 ext_ability = 0;
2461
2462         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2463
2464         hw->phy.ops.identify(hw);
2465
2466         switch (hw->phy.type) {
2467         case ixgbe_phy_x550em_kr:
2468                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2469                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2470                 break;
2471         case ixgbe_phy_x550em_kx4:
2472                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2473                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2474                 break;
2475         case ixgbe_phy_x550em_ext_t:
2476                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2477                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2478                                      &ext_ability);
2479                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2480                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2481                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2482                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2483                 break;
2484         default:
2485                 break;
2486         }
2487
2488         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2489                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2490
2491         return physical_layer;
2492 }
2493
2494 /**
2495  * ixgbe_get_bus_info_x550em - Set PCI bus info
2496  * @hw: pointer to hardware structure
2497  *
2498  * Sets bus link width and speed to unknown because X550em is
2499  * not a PCI device.
2500  **/
2501 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2502 {
2503
2504         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2505
2506         hw->bus.width = ixgbe_bus_width_unknown;
2507         hw->bus.speed = ixgbe_bus_speed_unknown;
2508
2509         hw->mac.ops.set_lan_id(hw);
2510
2511         return IXGBE_SUCCESS;
2512 }
2513
2514 /**
2515  * ixgbe_disable_rx_x550 - Disable RX unit
2516  *
2517  * Enables the Rx DMA unit for x550
2518  **/
2519 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2520 {
2521         u32 rxctrl, pfdtxgswc;
2522         s32 status;
2523         struct ixgbe_hic_disable_rxen fw_cmd;
2524
2525         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2526
2527         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2528         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2529                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2530                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2531                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2532                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2533                         hw->mac.set_lben = true;
2534                 } else {
2535                         hw->mac.set_lben = false;
2536                 }
2537
2538                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2539                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2540                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2541                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2542
2543                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2544                                         sizeof(struct ixgbe_hic_disable_rxen),
2545                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2546
2547                 /* If we fail - disable RX using register write */
2548                 if (status) {
2549                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2550                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2551                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2552                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2553                         }
2554                 }
2555         }
2556 }
2557
2558 /**
2559  * ixgbe_enter_lplu_x550em - Transition to low power states
2560  *  @hw: pointer to hardware structure
2561  *
2562  * Configures Low Power Link Up on transition to low power states
2563  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2564  * X557 PHY immediately prior to entering LPLU.
2565  **/
2566 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2567 {
2568         u16 autoneg_status, an_10g_cntl_reg, autoneg_reg, speed;
2569         s32 status;
2570         ixgbe_link_speed lcd_speed;
2571         u32 save_autoneg;
2572
2573         /* If blocked by MNG FW, then don't restart AN */
2574         if (ixgbe_check_reset_blocked(hw))
2575                 return IXGBE_SUCCESS;
2576
2577         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2578                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2579                                       &autoneg_status);
2580
2581         if (status != IXGBE_SUCCESS)
2582                 return status;
2583
2584         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2585
2586         if (status != IXGBE_SUCCESS)
2587                 return status;
2588
2589         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2590          * disabled, then force link down by entering low power mode.
2591          */
2592         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS) ||
2593             !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2594             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2595                 return ixgbe_set_copper_phy_power(hw, FALSE);
2596
2597         /* Determine LCD */
2598         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2599
2600         if (status != IXGBE_SUCCESS)
2601                 return status;
2602
2603         /* If no valid LCD link speed, then force link down and exit. */
2604         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2605                 return ixgbe_set_copper_phy_power(hw, FALSE);
2606
2607         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2608                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2609                                       &speed);
2610
2611         if (status != IXGBE_SUCCESS)
2612                 return status;
2613
2614         /* clear everything but the speed bits */
2615         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2616
2617         /* If current speed is already LCD, then exit. */
2618         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2619              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2620             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2621              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2622                 return status;
2623
2624         /* Clear AN completed indication */
2625         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2626                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2627                                       &autoneg_status);
2628
2629         if (status != IXGBE_SUCCESS)
2630                 return status;
2631
2632         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2633                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2634                              &an_10g_cntl_reg);
2635
2636         if (status != IXGBE_SUCCESS)
2637                 return status;
2638
2639         status = hw->phy.ops.read_reg(hw,
2640                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2641                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2642                              &autoneg_reg);
2643
2644         if (status != IXGBE_SUCCESS)
2645                 return status;
2646
2647         save_autoneg = hw->phy.autoneg_advertised;
2648
2649         /* Setup link at least common link speed */
2650         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2651
2652         /* restore autoneg from before setting lplu speed */
2653         hw->phy.autoneg_advertised = save_autoneg;
2654
2655         return status;
2656 }
2657
2658 /**
2659  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2660  *  @hw: pointer to hardware structure
2661  *  @lcd_speed: pointer to lowest common link speed
2662  *
2663  * Determine lowest common link speed with link partner.
2664  **/
2665 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2666 {
2667         u16 an_lp_status;
2668         s32 status;
2669         u16 word = hw->eeprom.ctrl_word_3;
2670
2671         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2672
2673         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2674                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2675                                       &an_lp_status);
2676
2677         if (status != IXGBE_SUCCESS)
2678                 return status;
2679
2680         /* If link partner advertised 1G, return 1G */
2681         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2682                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2683                 return status;
2684         }
2685
2686         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2687         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2688             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2689                 return status;
2690
2691         /* Link partner not capable of lower speeds, return 10G */
2692         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2693         return status;
2694 }
2695
2696 /**
2697  *  ixgbe_setup_fc_X550em - Set up flow control
2698  *  @hw: pointer to hardware structure
2699  *
2700  *  Called at init time to set up flow control.
2701  **/
2702 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2703 {
2704         s32 ret_val = IXGBE_SUCCESS;
2705         u32 pause, asm_dir, reg_val;
2706
2707         DEBUGFUNC("ixgbe_setup_fc_X550em");
2708
2709         /* Validate the requested mode */
2710         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2711                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2712                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2713                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2714                 goto out;
2715         }
2716
2717         /* 10gig parts do not have a word in the EEPROM to determine the
2718          * default flow control setting, so we explicitly set it to full.
2719          */
2720         if (hw->fc.requested_mode == ixgbe_fc_default)
2721                 hw->fc.requested_mode = ixgbe_fc_full;
2722
2723         /* Determine PAUSE and ASM_DIR bits. */
2724         switch (hw->fc.requested_mode) {
2725         case ixgbe_fc_none:
2726                 pause = 0;
2727                 asm_dir = 0;
2728                 break;
2729         case ixgbe_fc_tx_pause:
2730                 pause = 0;
2731                 asm_dir = 1;
2732                 break;
2733         case ixgbe_fc_rx_pause:
2734                 /* Rx Flow control is enabled and Tx Flow control is
2735                  * disabled by software override. Since there really
2736                  * isn't a way to advertise that we are capable of RX
2737                  * Pause ONLY, we will advertise that we support both
2738                  * symmetric and asymmetric Rx PAUSE, as such we fall
2739                  * through to the fc_full statement.  Later, we will
2740                  * disable the adapter's ability to send PAUSE frames.
2741                  */
2742         case ixgbe_fc_full:
2743                 pause = 1;
2744                 asm_dir = 1;
2745                 break;
2746         default:
2747                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2748                         "Flow control param set incorrectly\n");
2749                 ret_val = IXGBE_ERR_CONFIG;
2750                 goto out;
2751         }
2752
2753         if (hw->phy.media_type == ixgbe_media_type_backplane) {
2754                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2755                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2756                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2757                 if (ret_val != IXGBE_SUCCESS)
2758                         goto out;
2759                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2760                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2761                 if (pause)
2762                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2763                 if (asm_dir)
2764                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2765                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2766                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2767                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2768
2769                 /* Not all devices fully support AN. */
2770                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR)
2771                         hw->fc.disable_fc_autoneg = true;
2772         }
2773
2774 out:
2775         return ret_val;
2776 }
2777
2778 /**
2779  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2780  * @hw: pointer to hardware structure
2781  * @state: set mux if 1, clear if 0
2782  */
2783 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2784 {
2785         u32 esdp;
2786
2787         if (!hw->bus.lan_id)
2788                 return;
2789         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2790         if (state)
2791                 esdp |= IXGBE_ESDP_SDP1;
2792         else
2793                 esdp &= ~IXGBE_ESDP_SDP1;
2794         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2795         IXGBE_WRITE_FLUSH(hw);
2796 }
2797
2798 /**
2799  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2800  *  @hw: pointer to hardware structure
2801  *  @mask: Mask to specify which semaphore to acquire
2802  *
2803  *  Acquires the SWFW semaphore and sets the I2C MUX
2804  **/
2805 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2806 {
2807         s32 status;
2808
2809         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2810
2811         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2812         if (status)
2813                 return status;
2814
2815         if (mask & IXGBE_GSSR_I2C_MASK)
2816                 ixgbe_set_mux(hw, 1);
2817
2818         return IXGBE_SUCCESS;
2819 }
2820
2821 /**
2822  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2823  *  @hw: pointer to hardware structure
2824  *  @mask: Mask to specify which semaphore to release
2825  *
2826  *  Releases the SWFW semaphore and sets the I2C MUX
2827  **/
2828 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2829 {
2830         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2831
2832         if (mask & IXGBE_GSSR_I2C_MASK)
2833                 ixgbe_set_mux(hw, 0);
2834
2835         ixgbe_release_swfw_sync_X540(hw, mask);
2836 }
2837
2838 /**
2839  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2840  * @hw: pointer to hardware structure
2841  *
2842  * Handle external Base T PHY interrupt. If high temperature
2843  * failure alarm then return error, else if link status change
2844  * then setup internal/external PHY link
2845  *
2846  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2847  * failure alarm, else return PHY access status.
2848  */
2849 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2850 {
2851         bool lsc;
2852         u32 status;
2853
2854         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2855
2856         if (status != IXGBE_SUCCESS)
2857                 return status;
2858
2859         if (lsc)
2860                 return ixgbe_setup_internal_phy_t_x550em(hw);
2861
2862         return IXGBE_SUCCESS;
2863 }
2864
2865 /**
2866  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
2867  * @hw: pointer to hardware structure
2868  * @speed: new link speed
2869  * @autoneg_wait_to_complete: true when waiting for completion is needed
2870  *
2871  * Setup internal/external PHY link speed based on link speed, then set
2872  * external PHY auto advertised link speed.
2873  *
2874  * Returns error status for any failure
2875  **/
2876 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
2877                                   ixgbe_link_speed speed,
2878                                   bool autoneg_wait_to_complete)
2879 {
2880         s32 status;
2881         ixgbe_link_speed force_speed;
2882
2883         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
2884
2885         /* Setup internal/external PHY link speed to iXFI (10G), unless
2886          * only 1G is auto advertised then setup KX link.
2887          */
2888         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2889                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2890         else
2891                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2892
2893         status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
2894
2895         if (status != IXGBE_SUCCESS)
2896                 return status;
2897
2898         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
2899 }
2900
2901 /**
2902  * ixgbe_check_link_t_X550em - Determine link and speed status
2903  * @hw: pointer to hardware structure
2904  * @speed: pointer to link speed
2905  * @link_up: true when link is up
2906  * @link_up_wait_to_complete: bool used to wait for link up or not
2907  *
2908  * Check that both the MAC and X557 external PHY have link.
2909  **/
2910 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
2911                               bool *link_up, bool link_up_wait_to_complete)
2912 {
2913         u32 status;
2914         u16 autoneg_status;
2915
2916         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2917                 return IXGBE_ERR_CONFIG;
2918
2919         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
2920                                               link_up_wait_to_complete);
2921
2922         /* If check link fails or MAC link is not up, then return */
2923         if (status != IXGBE_SUCCESS || !(*link_up))
2924                 return status;
2925
2926         /* MAC link is up, so check external PHY link.
2927          * Read this twice back to back to indicate current status.
2928          */
2929         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2930                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2931                                       &autoneg_status);
2932
2933         if (status != IXGBE_SUCCESS)
2934                 return status;
2935
2936         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2937                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2938                                       &autoneg_status);
2939
2940         if (status != IXGBE_SUCCESS)
2941                 return status;
2942
2943         /* If external PHY link is not up, then indicate link not up */
2944         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
2945                 *link_up = false;
2946
2947         return IXGBE_SUCCESS;
2948 }
2949
2950 /**
2951  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2952  *  @hw: pointer to hardware structure
2953  **/
2954 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2955 {
2956         s32 status;
2957
2958         status = ixgbe_reset_phy_generic(hw);
2959
2960         if (status != IXGBE_SUCCESS)
2961                 return status;
2962
2963         /* Configure Link Status Alarm and Temperature Threshold interrupts */
2964         return ixgbe_enable_lasi_ext_t_x550em(hw);
2965 }