drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41
  42 /**
  43  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  44  *  @hw: pointer to hardware structure
  45  *
  46  *  Initialize the function pointers and assign the MAC type for X550.
  47  *  Does not touch the hardware.
  48  **/
  49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  50 {
  51         struct ixgbe_mac_info *mac = &hw->mac;
  52         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  53         s32 ret_val;
  54
  55         DEBUGFUNC("ixgbe_init_ops_X550");
  56
  57         ret_val = ixgbe_init_ops_X540(hw);
  58         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  59         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  60         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  61         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  62         mac->ops.set_source_address_pruning =
  63                         ixgbe_set_source_address_pruning_X550;
  64         mac->ops.set_ethertype_anti_spoofing =
  65                         ixgbe_set_ethertype_anti_spoofing_X550;
  66
  67         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  68         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  69         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  70         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  71         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  72         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  73         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  74         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  75         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  76
  77         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  78         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  79         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  80         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  81         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  82         return ret_val;
  83 }
  84
  85 /**
  86  * ixgbe_read_cs4227 - Read CS4227 register
  87  * @hw: pointer to hardware structure
  88  * @reg: register number to write
  89  * @value: pointer to receive value read
  90  *
  91  * Returns status code
  92  **/
  93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  94 {
  95         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
  96 }
  97
  98 /**
  99  * ixgbe_write_cs4227 - Write CS4227 register
 100  * @hw: pointer to hardware structure
 101  * @reg: register number to write
 102  * @value: value to write to register
 103  *
 104  * Returns status code
 105  **/
 106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 107 {
 108         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 109 }
 110
 111 /**
 112  * ixgbe_get_cs4227_status - Return CS4227 status
 113  * @hw: pointer to hardware structure
 114  *
 115  * Returns error if CS4227 not successfully initialized
 116  **/
 117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
 118 {
 119         s32 status;
 120         u16 value = 0;
 121         u8 retry;
 122
 123         for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
 124                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
 125                                            &value);
 126                 if (status != IXGBE_SUCCESS)
 127                         return status;
 128                 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
 129                         break;
 130                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 131         }
 132         if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
 133                 return IXGBE_ERR_PHY;
 134
 135         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 136                                     IXGBE_CS4227_SCRATCH_VALUE);
 137         if (status != IXGBE_SUCCESS)
 138                 return status;
 139         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 140         if (status != IXGBE_SUCCESS)
 141                 return status;
 142         if (value != IXGBE_CS4227_SCRATCH_VALUE)
 143                 return IXGBE_ERR_PHY;
 144         return IXGBE_SUCCESS;
 145 }
 146
 147 /**
 148  * ixgbe_read_pe - Read register from port expander
 149  * @hw: pointer to hardware structure
 150  * @reg: register number to read
 151  * @value: pointer to receive read value
 152  *
 153  * Returns status code
 154  **/
 155 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 156 {
 157         s32 status;
 158
 159         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 160         if (status != IXGBE_SUCCESS)
 161                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 162                               "port expander access failed with %d\n", status);
 163         return status;
 164 }
 165
 166 /**
 167  * ixgbe_write_pe - Write register to port expander
 168  * @hw: pointer to hardware structure
 169  * @reg: register number to write
 170  * @value: value to write
 171  *
 172  * Returns status code
 173  **/
 174 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 175 {
 176         s32 status;
 177
 178         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 179         if (status != IXGBE_SUCCESS)
 180                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 181                               "port expander access failed with %d\n", status);
 182         return status;
 183 }
 184
 185 /**
 186  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 187  * @hw: pointer to hardware structure
 188  *
 189  * Returns error code
 190  **/
 191 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 192 {
 193         s32 status;
 194         u8 reg;
 195
 196         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199         reg |= IXGBE_PE_BIT1;
 200         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 201         if (status != IXGBE_SUCCESS)
 202                 return status;
 203
 204         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 205         if (status != IXGBE_SUCCESS)
 206                 return status;
 207         reg &= ~IXGBE_PE_BIT1;
 208         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 209         if (status != IXGBE_SUCCESS)
 210                 return status;
 211
 212         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 213         if (status != IXGBE_SUCCESS)
 214                 return status;
 215         reg &= ~IXGBE_PE_BIT1;
 216         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 217         if (status != IXGBE_SUCCESS)
 218                 return status;
 219
 220         usec_delay(IXGBE_CS4227_RESET_HOLD);
 221
 222         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 223         if (status != IXGBE_SUCCESS)
 224                 return status;
 225         reg |= IXGBE_PE_BIT1;
 226         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 227         if (status != IXGBE_SUCCESS)
 228                 return status;
 229
 230         msec_delay(IXGBE_CS4227_RESET_DELAY);
 231
 232         return IXGBE_SUCCESS;
 233 }
 234
 235 /**
 236  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 237  * @hw: pointer to hardware structure
 238  **/
 239 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 240 {
 241         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 242         s32 status;
 243         u8 retry;
 244
 245         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 246                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 247                 if (status != IXGBE_SUCCESS) {
 248                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 249                                       "semaphore failed with %d\n", status);
 250                         return;
 251                 }
 252                 status = ixgbe_get_cs4227_status(hw);
 253                 if (status == IXGBE_SUCCESS) {
 254                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 255                         msec_delay(hw->eeprom.semaphore_delay);
 256                         return;
 257                 }
 258                 ixgbe_reset_cs4227(hw);
 259                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 260                 msec_delay(hw->eeprom.semaphore_delay);
 261         }
 262         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 263                       "Unable to initialize CS4227, err=%d\n", status);
 264 }
 265
 266 /**
 267  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 268  * @hw: pointer to hardware structure
 269  *
 270  * Returns error code
 271  */
 272 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 273 {
 274         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 275
 276         switch (hw->device_id) {
 277         case IXGBE_DEV_ID_X550EM_X_SFP:
 278                 /* set up for CS4227 usage */
 279                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 280                 if (hw->bus.lan_id) {
 281
 282                         esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 283                         esdp |= IXGBE_ESDP_SDP1_DIR;
 284                 }
 285                 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 286                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 287
 288                 ixgbe_check_cs4227(hw);
 289
 290                 return ixgbe_identify_module_generic(hw);
 291                 break;
 292         case IXGBE_DEV_ID_X550EM_X_KX4:
 293                 hw->phy.type = ixgbe_phy_x550em_kx4;
 294                 break;
 295         case IXGBE_DEV_ID_X550EM_X_KR:
 296                 hw->phy.type = ixgbe_phy_x550em_kr;
 297                 break;
 298         case IXGBE_DEV_ID_X550EM_X_1G_T:
 299         case IXGBE_DEV_ID_X550EM_X_10G_T:
 300                 return ixgbe_identify_phy_generic(hw);
 301         default:
 302                 break;
 303         }
 304         return IXGBE_SUCCESS;
 305 }
 306
 307 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 308                                      u32 device_type, u16 *phy_data)
 309 {
 310         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 311         return IXGBE_NOT_IMPLEMENTED;
 312 }
 313
 314 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 315                                       u32 device_type, u16 phy_data)
 316 {
 317         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 318         return IXGBE_NOT_IMPLEMENTED;
 319 }
 320
 321 /**
 322 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 323 *  @hw: pointer to hardware structure
 324 *
 325 *  Initialize the function pointers and for MAC type X550EM.
 326 *  Does not touch the hardware.
 327 **/
 328 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 329 {
 330         struct ixgbe_mac_info *mac = &hw->mac;
 331         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 332         struct ixgbe_phy_info *phy = &hw->phy;
 333         s32 ret_val;
 334
 335         DEBUGFUNC("ixgbe_init_ops_X550EM");
 336
 337         /* Similar to X550 so start there. */
 338         ret_val = ixgbe_init_ops_X550(hw);
 339
 340         /* Since this function eventually calls
 341          * ixgbe_init_ops_540 by design, we are setting
 342          * the pointers to NULL explicitly here to overwrite
 343          * the values being set in the x540 function.
 344          */
 345         /* Thermal sensor not supported in x550EM */
 346         mac->ops.get_thermal_sensor_data = NULL;
 347         mac->ops.init_thermal_sensor_thresh = NULL;
 348         mac->thermal_sensor_enabled = false;
 349
 350         /* FCOE not supported in x550EM */
 351         mac->ops.get_san_mac_addr = NULL;
 352         mac->ops.set_san_mac_addr = NULL;
 353         mac->ops.get_wwn_prefix = NULL;
 354         mac->ops.get_fcoe_boot_status = NULL;
 355
 356         /* IPsec not supported in x550EM */
 357         mac->ops.disable_sec_rx_path = NULL;
 358         mac->ops.enable_sec_rx_path = NULL;
 359
 360         /* X550EM bus type is internal*/
 361         hw->bus.type = ixgbe_bus_type_internal;
 362         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 363
 364         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 365         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 366         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 367         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 368         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 369         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 370         mac->ops.get_supported_physical_layer =
 371                                     ixgbe_get_supported_physical_layer_X550em;
 372
 373         /* PHY */
 374         phy->ops.init = ixgbe_init_phy_ops_X550em;
 375         phy->ops.identify = ixgbe_identify_phy_x550em;
 376         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 377                 phy->ops.set_phy_power = NULL;
 378
 379
 380         /* EEPROM */
 381         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 382         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 383         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 384         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 385         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 386         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 387         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 388         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 389
 390         return ret_val;
 391 }
 392
 393 /**
 394  *  ixgbe_dmac_config_X550
 395  *  @hw: pointer to hardware structure
 396  *
 397  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 398  *  When disabling dmac, dmac enable dmac bit is cleared.
 399  **/
 400 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 401 {
 402         u32 reg, high_pri_tc;
 403
 404         DEBUGFUNC("ixgbe_dmac_config_X550");
 405
 406         /* Disable DMA coalescing before configuring */
 407         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 408         reg &= ~IXGBE_DMACR_DMAC_EN;
 409         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 410
 411         /* Disable DMA Coalescing if the watchdog timer is 0 */
 412         if (!hw->mac.dmac_config.watchdog_timer)
 413                 goto out;
 414
 415         ixgbe_dmac_config_tcs_X550(hw);
 416
 417         /* Configure DMA Coalescing Control Register */
 418         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 419
 420         /* Set the watchdog timer in units of 40.96 usec */
 421         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 422         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 423
 424         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 425         /* If fcoe is enabled, set high priority traffic class */
 426         if (hw->mac.dmac_config.fcoe_en) {
 427                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 428                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 429                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 430         }
 431         reg |= IXGBE_DMACR_EN_MNG_IND;
 432
 433         /* Enable DMA coalescing after configuration */
 434         reg |= IXGBE_DMACR_DMAC_EN;
 435         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 436
 437 out:
 438         return IXGBE_SUCCESS;
 439 }
 440
 441 /**
 442  *  ixgbe_dmac_config_tcs_X550
 443  *  @hw: pointer to hardware structure
 444  *
 445  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 446  *  be cleared before configuring.
 447  **/
 448 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 449 {
 450         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 451
 452         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 453
 454         /* Configure DMA coalescing enabled */
 455         switch (hw->mac.dmac_config.link_speed) {
 456         case IXGBE_LINK_SPEED_100_FULL:
 457                 pb_headroom = IXGBE_DMACRXT_100M;
 458                 break;
 459         case IXGBE_LINK_SPEED_1GB_FULL:
 460                 pb_headroom = IXGBE_DMACRXT_1G;
 461                 break;
 462         default:
 463                 pb_headroom = IXGBE_DMACRXT_10G;
 464                 break;
 465         }
 466
 467         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 468                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 469
 470         /* Set the per Rx packet buffer receive threshold */
 471         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 472                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 473                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 474
 475                 if (tc < hw->mac.dmac_config.num_tcs) {
 476                         /* Get Rx PB size */
 477                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 478                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 479                                 IXGBE_RXPBSIZE_SHIFT;
 480
 481                         /* Calculate receive buffer threshold in kilobytes */
 482                         if (rx_pb_size > pb_headroom)
 483                                 rx_pb_size = rx_pb_size - pb_headroom;
 484                         else
 485                                 rx_pb_size = 0;
 486
 487                         /* Minimum of MFS shall be set for DMCTH */
 488                         reg |= (rx_pb_size > maxframe_size_kb) ?
 489                                 rx_pb_size : maxframe_size_kb;
 490                 }
 491                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 492         }
 493         return IXGBE_SUCCESS;
 494 }
 495
 496 /**
 497  *  ixgbe_dmac_update_tcs_X550
 498  *  @hw: pointer to hardware structure
 499  *
 500  *  Disables dmac, updates per TC settings, and then enables dmac.
 501  **/
 502 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 503 {
 504         u32 reg;
 505
 506         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 507
 508         /* Disable DMA coalescing before configuring */
 509         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 510         reg &= ~IXGBE_DMACR_DMAC_EN;
 511         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 512
 513         ixgbe_dmac_config_tcs_X550(hw);
 514
 515         /* Enable DMA coalescing after configuration */
 516         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 517         reg |= IXGBE_DMACR_DMAC_EN;
 518         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 519
 520         return IXGBE_SUCCESS;
 521 }
 522
 523 /**
 524  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 525  *  @hw: pointer to hardware structure
 526  *
 527  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 528  *  ixgbe_hw struct in order to set up EEPROM access.
 529  **/
 530 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 531 {
 532         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 533         u32 eec;
 534         u16 eeprom_size;
 535
 536         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 537
 538         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 539                 eeprom->semaphore_delay = 10;
 540                 eeprom->type = ixgbe_flash;
 541
 542                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 543                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 544                                     IXGBE_EEC_SIZE_SHIFT);
 545                 eeprom->word_size = 1 << (eeprom_size +
 546                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 547
 548                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 549                           eeprom->type, eeprom->word_size);
 550         }
 551
 552         return IXGBE_SUCCESS;
 553 }
 554
 555 /**
 556  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 557  *  @hw: pointer to the HW structure
 558  *  @enable_eee: boolean flag to enable EEE
 559  *
 560  *  Enable/disable EEE based on enable_eee flag.
 561  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 562  *  are modified.
 563  *
 564  **/
 565 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 566 {
 567         u32 eeer;
 568         u16 autoneg_eee_reg;
 569         u32 link_reg;
 570         s32 status;
 571
 572         DEBUGFUNC("ixgbe_setup_eee_X550");
 573
 574         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 575         /* Enable or disable EEE per flag */
 576         if (enable_eee) {
 577                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 578
 579                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 580                         /* Advertise EEE capability */
 581                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 582                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 583
 584                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 585                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 586                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 587
 588                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 589                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 590                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 591                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 592                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 593                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 594                         if (status != IXGBE_SUCCESS)
 595                                 return status;
 596
 597                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 598                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 599
 600                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 601                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 602                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 603                         if (status != IXGBE_SUCCESS)
 604                                 return status;
 605                 }
 606         } else {
 607                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 608
 609                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 610                         /* Disable advertised EEE capability */
 611                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 612                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 613
 614                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 615                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 616                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 617
 618                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 619                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 620                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 621                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 622                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 623                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 624                         if (status != IXGBE_SUCCESS)
 625                                 return status;
 626
 627                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 628                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 629
 630                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 631                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 632                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 633                         if (status != IXGBE_SUCCESS)
 634                                 return status;
 635                 }
 636         }
 637         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 638
 639         return IXGBE_SUCCESS;
 640 }
 641
 642 /**
 643  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 644  * @hw: pointer to hardware structure
 645  * @enable: enable or disable source address pruning
 646  * @pool: Rx pool to set source address pruning for
 647  **/
 648 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 649                                            unsigned int pool)
 650 {
 651         u64 pfflp;
 652
 653         /* max rx pool is 63 */
 654         if (pool > 63)
 655                 return;
 656
 657         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 658         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 659
 660         if (enable)
 661                 pfflp |= (1ULL << pool);
 662         else
 663                 pfflp &= ~(1ULL << pool);
 664
 665         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 666         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 667 }
 668
 669 /**
 670  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 671  *  @hw: pointer to hardware structure
 672  *  @enable: enable or disable switch for Ethertype anti-spoofing
 673  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 674  *
 675  **/
 676 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 677                 bool enable, int vf)
 678 {
 679         int vf_target_reg = vf >> 3;
 680         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 681         u32 pfvfspoof;
 682
 683         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 684
 685         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 686         if (enable)
 687                 pfvfspoof |= (1 << vf_target_shift);
 688         else
 689                 pfvfspoof &= ~(1 << vf_target_shift);
 690
 691         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 692 }
 693
 694 /**
 695  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 696  *  device
 697  *  @hw: pointer to hardware structure
 698  *  @reg_addr: 32 bit PHY register to write
 699  *  @device_type: 3 bit device type
 700  *  @data: Data to write to the register
 701  **/
 702 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 703                             u32 device_type, u32 data)
 704 {
 705         u32 i, command, error;
 706
 707         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 708                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 709
 710         /* Write IOSF control register */
 711         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 712
 713         /* Write IOSF data register */
 714         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 715         /*
 716          * Check every 10 usec to see if the address cycle completed.
 717          * The SB IOSF BUSY bit will clear when the operation is
 718          * complete
 719          */
 720         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 721                 usec_delay(10);
 722
 723                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 724                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 725                         break;
 726         }
 727
 728         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 729                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 730                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 731                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 732                               "Failed to write, error %x\n", error);
 733                 return IXGBE_ERR_PHY;
 734         }
 735
 736         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 737                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
 738                 return IXGBE_ERR_PHY;
 739         }
 740
 741         return IXGBE_SUCCESS;
 742 }
 743
 744 /**
 745  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 746  *  device
 747  *  @hw: pointer to hardware structure
 748  *  @reg_addr: 32 bit PHY register to write
 749  *  @device_type: 3 bit device type
 750  *  @phy_data: Pointer to read data from the register
 751  **/
 752 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 753                            u32 device_type, u32 *data)
 754 {
 755         u32 i, command, error;
 756
 757         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 758                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 759
 760         /* Write IOSF control register */
 761         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 762
 763         /*
 764          * Check every 10 usec to see if the address cycle completed.
 765          * The SB IOSF BUSY bit will clear when the operation is
 766          * complete
 767          */
 768         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 769                 usec_delay(10);
 770
 771                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 772                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 773                         break;
 774         }
 775
 776         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 777                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 778                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 779                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 780                                 "Failed to read, error %x\n", error);
 781                 return IXGBE_ERR_PHY;
 782         }
 783
 784         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 785                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
 786                 return IXGBE_ERR_PHY;
 787         }
 788
 789         *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 790
 791         return IXGBE_SUCCESS;
 792 }
 793
 794 /**
 795  *  ixgbe_disable_mdd_X550
 796  *  @hw: pointer to hardware structure
 797  *
 798  *  Disable malicious driver detection
 799  **/
 800 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 801 {
 802         u32 reg;
 803
 804         DEBUGFUNC("ixgbe_disable_mdd_X550");
 805
 806         /* Disable MDD for TX DMA and interrupt */
 807         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 808         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 809         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 810
 811         /* Disable MDD for RX and interrupt */
 812         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 813         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 814         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 815 }
 816
 817 /**
 818  *  ixgbe_enable_mdd_X550
 819  *  @hw: pointer to hardware structure
 820  *
 821  *  Enable malicious driver detection
 822  **/
 823 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 824 {
 825         u32 reg;
 826
 827         DEBUGFUNC("ixgbe_enable_mdd_X550");
 828
 829         /* Enable MDD for TX DMA and interrupt */
 830         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 831         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 832         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 833
 834         /* Enable MDD for RX and interrupt */
 835         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 836         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 837         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 838 }
 839
 840 /**
 841  *  ixgbe_restore_mdd_vf_X550
 842  *  @hw: pointer to hardware structure
 843  *  @vf: vf index
 844  *
 845  *  Restore VF that was disabled during malicious driver detection event
 846  **/
 847 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 848 {
 849         u32 idx, reg, num_qs, start_q, bitmask;
 850
 851         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 852
 853         /* Map VF to queues */
 854         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 855         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 856         case IXGBE_MRQC_VMDQRT8TCEN:
 857                 num_qs = 8;  /* 16 VFs / pools */
 858                 bitmask = 0x000000FF;
 859                 break;
 860         case IXGBE_MRQC_VMDQRSS32EN:
 861         case IXGBE_MRQC_VMDQRT4TCEN:
 862                 num_qs = 4;  /* 32 VFs / pools */
 863                 bitmask = 0x0000000F;
 864                 break;
 865         default:            /* 64 VFs / pools */
 866                 num_qs = 2;
 867                 bitmask = 0x00000003;
 868                 break;
 869         }
 870         start_q = vf * num_qs;
 871
 872         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 873         idx = start_q / 32;
 874         reg = 0;
 875         reg |= (bitmask << (start_q % 32));
 876         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 877         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 878 }
 879
 880 /**
 881  *  ixgbe_mdd_event_X550
 882  *  @hw: pointer to hardware structure
 883  *  @vf_bitmap: vf bitmap of malicious vfs
 884  *
 885  *  Handle malicious driver detection event.
 886  **/
 887 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 888 {
 889         u32 wqbr;
 890         u32 i, j, reg, q, shift, vf, idx;
 891
 892         DEBUGFUNC("ixgbe_mdd_event_X550");
 893
 894         /* figure out pool size for mapping to vf's */
 895         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 896         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 897         case IXGBE_MRQC_VMDQRT8TCEN:
 898                 shift = 3;  /* 16 VFs / pools */
 899                 break;
 900         case IXGBE_MRQC_VMDQRSS32EN:
 901         case IXGBE_MRQC_VMDQRT4TCEN:
 902                 shift = 2;  /* 32 VFs / pools */
 903                 break;
 904         default:
 905                 shift = 1;  /* 64 VFs / pools */
 906                 break;
 907         }
 908
 909         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
 910         for (i = 0; i < 4; i++) {
 911                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
 912                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
 913
 914                 if (!wqbr)
 915                         continue;
 916
 917                 /* Get malicious queue */
 918                 for (j = 0; j < 32 && wqbr; j++) {
 919
 920                         if (!(wqbr & (1 << j)))
 921                                 continue;
 922
 923                         /* Get queue from bitmask */
 924                         q = j + (i * 32);
 925
 926                         /* Map queue to vf */
 927                         vf = (q >> shift);
 928
 929                         /* Set vf bit in vf_bitmap */
 930                         idx = vf / 32;
 931                         vf_bitmap[idx] |= (1 << (vf % 32));
 932                         wqbr &= ~(1 << j);
 933                 }
 934         }
 935 }
 936
 937 /**
 938  *  ixgbe_get_media_type_X550em - Get media type
 939  *  @hw: pointer to hardware structure
 940  *
 941  *  Returns the media type (fiber, copper, backplane)
 942  */
 943 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
 944 {
 945         enum ixgbe_media_type media_type;
 946
 947         DEBUGFUNC("ixgbe_get_media_type_X550em");
 948
 949         /* Detect if there is a copper PHY attached. */
 950         switch (hw->device_id) {
 951         case IXGBE_DEV_ID_X550EM_X_KR:
 952         case IXGBE_DEV_ID_X550EM_X_KX4:
 953                 media_type = ixgbe_media_type_backplane;
 954                 break;
 955         case IXGBE_DEV_ID_X550EM_X_SFP:
 956                 media_type = ixgbe_media_type_fiber;
 957                 break;
 958         case IXGBE_DEV_ID_X550EM_X_1G_T:
 959         case IXGBE_DEV_ID_X550EM_X_10G_T:
 960                 media_type = ixgbe_media_type_copper;
 961                 break;
 962         default:
 963                 media_type = ixgbe_media_type_unknown;
 964                 break;
 965         }
 966         return media_type;
 967 }
 968
 969 /**
 970  *  ixgbe_setup_sfp_modules_X550em - Setup SFP module
 971  *  @hw: pointer to hardware structure
 972  */
 973 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
 974 {
 975         bool setup_linear;
 976         u16 reg_slice, edc_mode;
 977         s32 ret_val;
 978
 979         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
 980
 981         switch (hw->phy.sfp_type) {
 982         case ixgbe_sfp_type_unknown:
 983                 return IXGBE_SUCCESS;
 984         case ixgbe_sfp_type_not_present:
 985                 return IXGBE_ERR_SFP_NOT_PRESENT;
 986         case ixgbe_sfp_type_da_cu_core0:
 987         case ixgbe_sfp_type_da_cu_core1:
 988                 setup_linear = true;
 989                 break;
 990         case ixgbe_sfp_type_srlr_core0:
 991         case ixgbe_sfp_type_srlr_core1:
 992         case ixgbe_sfp_type_da_act_lmt_core0:
 993         case ixgbe_sfp_type_da_act_lmt_core1:
 994         case ixgbe_sfp_type_1g_sx_core0:
 995         case ixgbe_sfp_type_1g_sx_core1:
 996         case ixgbe_sfp_type_1g_lx_core0:
 997         case ixgbe_sfp_type_1g_lx_core1:
 998                 setup_linear = false;
 999                 break;
1000         default:
1001                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1002         }
1003
1004         ixgbe_init_mac_link_ops_X550em(hw);
1005         hw->phy.ops.reset = NULL;
1006
1007         /* The CS4227 slice address is the base address + the port-pair reg
1008          * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
1009          */
1010         reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12);
1011
1012         if (setup_linear)
1013                 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1014         else
1015                 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1016
1017         /* Configure CS4227 for connection type. */
1018         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1019                                            edc_mode);
1020
1021         if (ret_val != IXGBE_SUCCESS)
1022                 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
1023                                                    edc_mode);
1024
1025         return ret_val;
1026 }
1027
1028 /**
1029  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1030  *  @hw: pointer to hardware structure
1031  */
1032 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1033 {
1034         struct ixgbe_mac_info *mac = &hw->mac;
1035
1036         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1037
1038         /* CS4227 does not support autoneg, so disable the laser control
1039          * functions for SFP+ fiber
1040          */
1041          if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
1042                 mac->ops.disable_tx_laser = NULL;
1043                 mac->ops.enable_tx_laser = NULL;
1044                 mac->ops.flap_tx_laser = NULL;
1045          }
1046 }
1047
1048 /**
1049  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1050  *  @hw: pointer to hardware structure
1051  *  @speed: pointer to link speed
1052  *  @autoneg: true when autoneg or autotry is enabled
1053  */
1054 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1055                                        ixgbe_link_speed *speed,
1056                                        bool *autoneg)
1057 {
1058         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1059
1060         /* SFP */
1061         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1062
1063                 /* CS4227 SFP must not enable auto-negotiation */
1064                 *autoneg = false;
1065
1066                 /* Check if 1G SFP module. */
1067                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1068                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1069                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1070                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1071                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1072                         return IXGBE_SUCCESS;
1073                 }
1074
1075                 /* Link capabilities are based on SFP */
1076                 if (hw->phy.multispeed_fiber)
1077                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1078                                  IXGBE_LINK_SPEED_1GB_FULL;
1079                 else
1080                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1081         } else {
1082                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1083                          IXGBE_LINK_SPEED_1GB_FULL;
1084                 *autoneg = true;
1085         }
1086
1087         return IXGBE_SUCCESS;
1088 }
1089
1090 /**
1091  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1092  *  @hw: pointer to hardware structure
1093  *
1094  *  Initialize any function pointers that were not able to be
1095  *  set during init_shared_code because the PHY/SFP type was
1096  *  not known.  Perform the SFP init if necessary.
1097  */
1098 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1099 {
1100         struct ixgbe_phy_info *phy = &hw->phy;
1101         s32 ret_val;
1102         u32 esdp;
1103
1104         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1105
1106         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
1107                 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
1108                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1109
1110                 if (hw->bus.lan_id) {
1111                         esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
1112                         esdp |= IXGBE_ESDP_SDP1_DIR;
1113                 }
1114                 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
1115                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
1116         }
1117
1118         /* Identify the PHY or SFP module */
1119         ret_val = phy->ops.identify(hw);
1120         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1121                 return ret_val;
1122
1123         /* Setup function pointers based on detected SFP module and speeds */
1124         ixgbe_init_mac_link_ops_X550em(hw);
1125         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1126                 phy->ops.reset = NULL;
1127
1128         /* Set functions pointers based on phy type */
1129         switch (hw->phy.type) {
1130         case ixgbe_phy_x550em_kx4:
1131                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1132                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1133                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1134                 break;
1135         case ixgbe_phy_x550em_kr:
1136                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1137                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1138                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1139                 break;
1140         case ixgbe_phy_x550em_ext_t:
1141                 phy->ops.setup_internal_link = ixgbe_setup_internal_phy_x550em;
1142                 break;
1143         default:
1144                 break;
1145         }
1146         return ret_val;
1147 }
1148
1149 /**
1150  *  ixgbe_reset_hw_X550em - Perform hardware reset
1151  *  @hw: pointer to hardware structure
1152  *
1153  *  Resets the hardware by resetting the transmit and receive units, masks
1154  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1155  *  reset.
1156  */
1157 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1158 {
1159         struct ixgbe_hic_hdr fw_cmd;
1160         ixgbe_link_speed link_speed;
1161         s32 status;
1162         u32 ctrl = 0;
1163         u32 i;
1164         bool link_up = false;
1165
1166         DEBUGFUNC("ixgbe_reset_hw_X550em");
1167
1168         fw_cmd.cmd = FW_PHY_MGMT_REQ_CMD;
1169         fw_cmd.buf_len = 0;
1170         fw_cmd.cmd_or_resp.cmd_resv = 0;
1171         fw_cmd.checksum = FW_DEFAULT_CHECKSUM;
1172         status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
1173                                               sizeof(fw_cmd),
1174                                               IXGBE_HI_PHY_MGMT_REQ_TIMEOUT,
1175                                               true);
1176         if (status)
1177                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1178                               "PHY mgmt command failed with %d\n", status);
1179         else if (fw_cmd.cmd_or_resp.ret_status != FW_CEM_RESP_STATUS_SUCCESS)
1180                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1181                               "PHY mgmt command returned %d\n",
1182                               fw_cmd.cmd_or_resp.ret_status);
1183
1184         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1185         status = hw->mac.ops.stop_adapter(hw);
1186         if (status != IXGBE_SUCCESS)
1187                 return status;
1188
1189         /* flush pending Tx transactions */
1190         ixgbe_clear_tx_pending(hw);
1191
1192         /* PHY ops must be identified and initialized prior to reset */
1193
1194         /* Identify PHY and related function pointers */
1195         status = hw->phy.ops.init(hw);
1196
1197         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1198                 return status;
1199
1200         /* start the external PHY */
1201         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1202                 status = ixgbe_init_ext_t_x550em(hw);
1203                 if (status)
1204                         return status;
1205         }
1206
1207         /* Setup SFP module if there is one present. */
1208         if (hw->phy.sfp_setup_needed) {
1209                 status = hw->mac.ops.setup_sfp(hw);
1210                 hw->phy.sfp_setup_needed = false;
1211         }
1212
1213         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1214                 return status;
1215
1216         /* Reset PHY */
1217         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1218                 hw->phy.ops.reset(hw);
1219
1220 mac_reset_top:
1221         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1222          * If link reset is used when link is up, it might reset the PHY when
1223          * mng is using it.  If link is down or the flag to force full link
1224          * reset is set, then perform link reset.
1225          */
1226         ctrl = IXGBE_CTRL_LNK_RST;
1227         if (!hw->force_full_reset) {
1228                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1229                 if (link_up)
1230                         ctrl = IXGBE_CTRL_RST;
1231         }
1232
1233         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1234         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1235         IXGBE_WRITE_FLUSH(hw);
1236
1237         /* Poll for reset bit to self-clear meaning reset is complete */
1238         for (i = 0; i < 10; i++) {
1239                 usec_delay(1);
1240                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1241                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1242                         break;
1243         }
1244
1245         if (ctrl & IXGBE_CTRL_RST_MASK) {
1246                 status = IXGBE_ERR_RESET_FAILED;
1247                 DEBUGOUT("Reset polling failed to complete.\n");
1248         }
1249
1250         msec_delay(50);
1251
1252         /* Double resets are required for recovery from certain error
1253          * conditions.  Between resets, it is necessary to stall to
1254          * allow time for any pending HW events to complete.
1255          */
1256         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1257                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1258                 goto mac_reset_top;
1259         }
1260
1261         /* Store the permanent mac address */
1262         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1263
1264         /* Store MAC address from RAR0, clear receive address registers, and
1265          * clear the multicast table.  Also reset num_rar_entries to 128,
1266          * since we modify this value when programming the SAN MAC address.
1267          */
1268         hw->mac.num_rar_entries = 128;
1269         hw->mac.ops.init_rx_addrs(hw);
1270
1271
1272         return status;
1273 }
1274
1275 /**
1276  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1277  * @hw: pointer to hardware structure
1278  */
1279 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1280 {
1281         u32 status;
1282         u16 reg;
1283         u32 retries = 1;
1284
1285         /* TODO: The number of attempts and delay between attempts is undefined */
1286         do {
1287                 /* decrement retries counter and exit if we hit 0 */
1288                 if (retries < 1) {
1289                         ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
1290                                       "External PHY not yet finished resetting.");
1291                         return IXGBE_ERR_PHY;
1292                 }
1293                 retries--;
1294
1295                 usec_delay(0);
1296
1297                 status = hw->phy.ops.read_reg(hw,
1298                                               IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1299                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1300                                               &reg);
1301
1302                 if (status != IXGBE_SUCCESS)
1303                         return status;
1304
1305                 /* Verify PHY FW reset has completed */
1306         } while ((reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) != 1);
1307
1308         /* Set port to low power mode */
1309         status = hw->phy.ops.read_reg(hw,
1310                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
1311                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1312                                       &reg);
1313
1314         if (status != IXGBE_SUCCESS)
1315                 return status;
1316
1317         reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
1318
1319         status = hw->phy.ops.write_reg(hw,
1320                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
1321                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1322                                        reg);
1323
1324         if (status != IXGBE_SUCCESS)
1325                 return status;
1326
1327         /* Enable the transmitter */
1328         status = hw->phy.ops.read_reg(hw,
1329                                       IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
1330                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1331                                       &reg);
1332
1333         if (status != IXGBE_SUCCESS)
1334                 return status;
1335
1336         reg &= ~IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE;
1337
1338         status = hw->phy.ops.write_reg(hw,
1339                                        IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
1340                                        IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1341                                        reg);
1342
1343         if (status != IXGBE_SUCCESS)
1344                 return status;
1345
1346         /* Un-stall the PHY FW */
1347         status = hw->phy.ops.read_reg(hw,
1348                                       IXGBE_MDIO_GLOBAL_RES_PR_10,
1349                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1350                                       &reg);
1351
1352         if (status != IXGBE_SUCCESS)
1353                 return status;
1354
1355         reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1356
1357         status = hw->phy.ops.write_reg(hw,
1358                                        IXGBE_MDIO_GLOBAL_RES_PR_10,
1359                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1360                                        reg);
1361
1362         return status;
1363 }
1364
1365 /**
1366  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1367  *  @hw: pointer to hardware structure
1368  *
1369  *  Configures the integrated KR PHY.
1370  **/
1371 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1372 {
1373         s32 status;
1374         u32 reg_val;
1375
1376         status = ixgbe_read_iosf_sb_reg_x550(hw,
1377                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1378                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1379         if (status)
1380                 return status;
1381
1382         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1383         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ;
1384         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1385         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1386                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1387
1388         /* Advertise 10G support. */
1389         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1390                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1391
1392         /* Advertise 1G support. */
1393         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1394                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1395
1396         /* Restart auto-negotiation. */
1397         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1398         status = ixgbe_write_iosf_sb_reg_x550(hw,
1399                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1400                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1401
1402         return status;
1403 }
1404
1405 /**
1406  *  ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1407  *  @hw: pointer to hardware structure
1408  *
1409  *  Configures the integrated KX4 PHY.
1410  **/
1411 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1412 {
1413         s32 status;
1414         u32 reg_val;
1415
1416         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1417                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, &reg_val);
1418         if (status)
1419                 return status;
1420
1421         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1422                         IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1423
1424         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1425
1426         /* Advertise 10G support. */
1427         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1428                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1429
1430         /* Advertise 1G support. */
1431         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1432                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1433
1434         /* Restart auto-negotiation. */
1435         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1436         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1437                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, reg_val);
1438
1439         return status;
1440 }
1441
1442 /**
1443  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1444  *  @hw: pointer to hardware structure
1445  *  @speed: the link speed to force
1446  *
1447  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1448  *  internal and external PHY at a specific speed, without autonegotiation.
1449  **/
1450 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1451 {
1452         s32 status;
1453         u32 reg_val;
1454
1455         /* Disable AN and force speed to 10G Serial. */
1456         status = ixgbe_read_iosf_sb_reg_x550(hw,
1457                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1458                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1459         if (status != IXGBE_SUCCESS)
1460                 return status;
1461
1462         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1463         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1464
1465         /* Select forced link speed for internal PHY. */
1466         switch (*speed) {
1467         case IXGBE_LINK_SPEED_10GB_FULL:
1468                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1469                 break;
1470         case IXGBE_LINK_SPEED_1GB_FULL:
1471                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1472                 break;
1473         default:
1474                 /* Other link speeds are not supported by internal KR PHY. */
1475                 return IXGBE_ERR_LINK_SETUP;
1476         }
1477
1478         status = ixgbe_write_iosf_sb_reg_x550(hw,
1479                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1480                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1481         if (status != IXGBE_SUCCESS)
1482                 return status;
1483
1484         /* Disable training protocol FSM. */
1485         status = ixgbe_read_iosf_sb_reg_x550(hw,
1486                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1487                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1488         if (status != IXGBE_SUCCESS)
1489                 return status;
1490         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1491         status = ixgbe_write_iosf_sb_reg_x550(hw,
1492                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1493                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1494         if (status != IXGBE_SUCCESS)
1495                 return status;
1496
1497         /* Disable Flex from training TXFFE. */
1498         status = ixgbe_read_iosf_sb_reg_x550(hw,
1499                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1500                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1501         if (status != IXGBE_SUCCESS)
1502                 return status;
1503         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1504         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1505         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1506         status = ixgbe_write_iosf_sb_reg_x550(hw,
1507                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1508                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1509         if (status != IXGBE_SUCCESS)
1510                 return status;
1511         status = ixgbe_read_iosf_sb_reg_x550(hw,
1512                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1513                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1514         if (status != IXGBE_SUCCESS)
1515                 return status;
1516         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1517         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1518         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1519         status = ixgbe_write_iosf_sb_reg_x550(hw,
1520                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1521                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1522         if (status != IXGBE_SUCCESS)
1523                 return status;
1524
1525         /* Enable override for coefficients. */
1526         status = ixgbe_read_iosf_sb_reg_x550(hw,
1527                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1528                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1529         if (status != IXGBE_SUCCESS)
1530                 return status;
1531         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1532         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1533         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1534         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1535         status = ixgbe_write_iosf_sb_reg_x550(hw,
1536                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1537                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1538         if (status != IXGBE_SUCCESS)
1539                 return status;
1540
1541         /* Toggle port SW reset by AN reset. */
1542         status = ixgbe_read_iosf_sb_reg_x550(hw,
1543                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1544                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1545         if (status != IXGBE_SUCCESS)
1546                 return status;
1547         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1548         status = ixgbe_write_iosf_sb_reg_x550(hw,
1549                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1550                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1551
1552         return status;
1553 }
1554
1555 /**
1556  * ixgbe_setup_internal_phy_x550em - Configure integrated KR PHY
1557  * @hw: point to hardware structure
1558  *
1559  * Configures the integrated KR PHY to talk to the external PHY. The base
1560  * driver will call this function when it gets notification via interrupt from
1561  * the external PHY. This function forces the internal PHY into iXFI mode at
1562  * the correct speed.
1563  *
1564  * A return of a non-zero value indicates an error, and the base driver should
1565  * not report link up.
1566  */
1567 s32 ixgbe_setup_internal_phy_x550em(struct ixgbe_hw *hw)
1568 {
1569         u32 status;
1570         u16 lasi, autoneg_status, speed;
1571         ixgbe_link_speed force_speed;
1572
1573         /* Verify that the external link status has changed */
1574         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_XENPAK_LASI_STATUS,
1575                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1576                                       &lasi);
1577         if (status != IXGBE_SUCCESS)
1578                 return status;
1579
1580         /* If there was no change in link status, we can just exit */
1581         if (!(lasi & IXGBE_XENPAK_LASI_LINK_STATUS_ALARM))
1582                 return IXGBE_SUCCESS;
1583
1584         /* we read this twice back to back to indicate current status */
1585         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1586                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1587                                       &autoneg_status);
1588         if (status != IXGBE_SUCCESS)
1589                 return status;
1590
1591         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1592                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1593                                       &autoneg_status);
1594         if (status != IXGBE_SUCCESS)
1595                 return status;
1596
1597         /* If link is not up return an error indicating treat link as down */
1598         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1599                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1600
1601         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1602                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1603                                       &speed);
1604
1605         /* clear everything but the speed and duplex bits */
1606         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1607
1608         switch (speed) {
1609         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1610                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1611                 break;
1612         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1613                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1614                 break;
1615         default:
1616                 /* Internal PHY does not support anything else */
1617                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1618         }
1619
1620         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1621 }
1622
1623 /**
1624  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1625  *  @hw: pointer to hardware structure
1626  *
1627  *  Configures the integrated KR PHY to use internal loopback mode.
1628  **/
1629 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1630 {
1631         s32 status;
1632         u32 reg_val;
1633
1634         /* Disable AN and force speed to 10G Serial. */
1635         status = ixgbe_read_iosf_sb_reg_x550(hw,
1636                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1637                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1638         if (status != IXGBE_SUCCESS)
1639                 return status;
1640         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1641         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1642         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1643         status = ixgbe_write_iosf_sb_reg_x550(hw,
1644                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1645                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1646         if (status != IXGBE_SUCCESS)
1647                 return status;
1648
1649         /* Set near-end loopback clocks. */
1650         status = ixgbe_read_iosf_sb_reg_x550(hw,
1651                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1652                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1653         if (status != IXGBE_SUCCESS)
1654                 return status;
1655         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1656         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1657         status = ixgbe_write_iosf_sb_reg_x550(hw,
1658                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1659                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1660         if (status != IXGBE_SUCCESS)
1661                 return status;
1662
1663         /* Set loopback enable. */
1664         status = ixgbe_read_iosf_sb_reg_x550(hw,
1665                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1666                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1667         if (status != IXGBE_SUCCESS)
1668                 return status;
1669         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1670         status = ixgbe_write_iosf_sb_reg_x550(hw,
1671                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1672                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1673         if (status != IXGBE_SUCCESS)
1674                 return status;
1675
1676         /* Training bypass. */
1677         status = ixgbe_read_iosf_sb_reg_x550(hw,
1678                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1679                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1680         if (status != IXGBE_SUCCESS)
1681                 return status;
1682         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1683         status = ixgbe_write_iosf_sb_reg_x550(hw,
1684                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1685                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1686
1687         return status;
1688 }
1689
1690 /**
1691  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1692  *  assuming that the semaphore is already obtained.
1693  *  @hw: pointer to hardware structure
1694  *  @offset: offset of  word in the EEPROM to read
1695  *  @data: word read from the EEPROM
1696  *
1697  *  Reads a 16 bit word from the EEPROM using the hostif.
1698  **/
1699 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1700                                    u16 *data)
1701 {
1702         s32 status;
1703         struct ixgbe_hic_read_shadow_ram buffer;
1704
1705         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1706         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1707         buffer.hdr.req.buf_lenh = 0;
1708         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1709         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1710
1711         /* convert offset from words to bytes */
1712         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1713         /* one word */
1714         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1715
1716         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1717                                               sizeof(buffer),
1718                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1719
1720         if (status)
1721                 return status;
1722
1723         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1724                                           FW_NVM_DATA_OFFSET);
1725
1726         return 0;
1727 }
1728
1729 /**
1730  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1731  *  @hw: pointer to hardware structure
1732  *  @offset: offset of  word in the EEPROM to read
1733  *  @data: word read from the EEPROM
1734  *
1735  *  Reads a 16 bit word from the EEPROM using the hostif.
1736  **/
1737 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1738                               u16 *data)
1739 {
1740         s32 status = IXGBE_SUCCESS;
1741
1742         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1743
1744         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1745             IXGBE_SUCCESS) {
1746                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1747                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1748         } else {
1749                 status = IXGBE_ERR_SWFW_SYNC;
1750         }
1751
1752         return status;
1753 }
1754
1755 /**
1756  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1757  *  @hw: pointer to hardware structure
1758  *  @offset: offset of  word in the EEPROM to read
1759  *  @words: number of words
1760  *  @data: word(s) read from the EEPROM
1761  *
1762  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
1763  **/
1764 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1765                                      u16 offset, u16 words, u16 *data)
1766 {
1767         struct ixgbe_hic_read_shadow_ram buffer;
1768         u32 current_word = 0;
1769         u16 words_to_read;
1770         s32 status;
1771         u32 i;
1772
1773         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1774
1775         /* Take semaphore for the entire operation. */
1776         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1777         if (status) {
1778                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1779                 return status;
1780         }
1781         while (words) {
1782                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1783                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1784                 else
1785                         words_to_read = words;
1786
1787                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1788                 buffer.hdr.req.buf_lenh = 0;
1789                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1790                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1791
1792                 /* convert offset from words to bytes */
1793                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1794                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1795
1796                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1797                                                       sizeof(buffer),
1798                                                       IXGBE_HI_COMMAND_TIMEOUT,
1799                                                       false);
1800
1801                 if (status) {
1802                         DEBUGOUT("Host interface command failed\n");
1803                         goto out;
1804                 }
1805
1806                 for (i = 0; i < words_to_read; i++) {
1807                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1808                                   2 * i;
1809                         u32 value = IXGBE_READ_REG(hw, reg);
1810
1811                         data[current_word] = (u16)(value & 0xffff);
1812                         current_word++;
1813                         i++;
1814                         if (i < words_to_read) {
1815                                 value >>= 16;
1816                                 data[current_word] = (u16)(value & 0xffff);
1817                                 current_word++;
1818                         }
1819                 }
1820                 words -= words_to_read;
1821         }
1822
1823 out:
1824         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1825         return status;
1826 }
1827
1828 /**
1829  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1830  *  @hw: pointer to hardware structure
1831  *  @offset: offset of  word in the EEPROM to write
1832  *  @data: word write to the EEPROM
1833  *
1834  *  Write a 16 bit word to the EEPROM using the hostif.
1835  **/
1836 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1837                                     u16 data)
1838 {
1839         s32 status;
1840         struct ixgbe_hic_write_shadow_ram buffer;
1841
1842         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1843
1844         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1845         buffer.hdr.req.buf_lenh = 0;
1846         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1847         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1848
1849          /* one word */
1850         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1851         buffer.data = data;
1852         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1853
1854         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1855                                               sizeof(buffer),
1856                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1857
1858         return status;
1859 }
1860
1861 /**
1862  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1863  *  @hw: pointer to hardware structure
1864  *  @offset: offset of  word in the EEPROM to write
1865  *  @data: word write to the EEPROM
1866  *
1867  *  Write a 16 bit word to the EEPROM using the hostif.
1868  **/
1869 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1870                                u16 data)
1871 {
1872         s32 status = IXGBE_SUCCESS;
1873
1874         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
1875
1876         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1877             IXGBE_SUCCESS) {
1878                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1879                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1880         } else {
1881                 DEBUGOUT("write ee hostif failed to get semaphore");
1882                 status = IXGBE_ERR_SWFW_SYNC;
1883         }
1884
1885         return status;
1886 }
1887
1888 /**
1889  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1890  *  @hw: pointer to hardware structure
1891  *  @offset: offset of  word in the EEPROM to write
1892  *  @words: number of words
1893  *  @data: word(s) write to the EEPROM
1894  *
1895  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1896  **/
1897 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1898                                       u16 offset, u16 words, u16 *data)
1899 {
1900         s32 status = IXGBE_SUCCESS;
1901         u32 i = 0;
1902
1903         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
1904
1905         /* Take semaphore for the entire operation. */
1906         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1907         if (status != IXGBE_SUCCESS) {
1908                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
1909                 goto out;
1910         }
1911
1912         for (i = 0; i < words; i++) {
1913                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1914                                                          data[i]);
1915
1916                 if (status != IXGBE_SUCCESS) {
1917                         DEBUGOUT("Eeprom buffered write failed\n");
1918                         break;
1919                 }
1920         }
1921
1922         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1923 out:
1924
1925         return status;
1926 }
1927
1928 /**
1929  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
1930  * @hw: pointer to hardware structure
1931  * @ptr: pointer offset in eeprom
1932  * @size: size of section pointed by ptr, if 0 first word will be used as size
1933  * @csum: address of checksum to update
1934  *
1935  * Returns error status for any failure
1936  */
1937 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
1938                                    u16 size, u16 *csum, u16 *buffer,
1939                                    u32 buffer_size)
1940 {
1941         u16 buf[256];
1942         s32 status;
1943         u16 length, bufsz, i, start;
1944         u16 *local_buffer;
1945
1946         bufsz = sizeof(buf) / sizeof(buf[0]);
1947
1948         /* Read a chunk at the pointer location */
1949         if (!buffer) {
1950                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
1951                 if (status) {
1952                         DEBUGOUT("Failed to read EEPROM image\n");
1953                         return status;
1954                 }
1955                 local_buffer = buf;
1956         } else {
1957                 if (buffer_size < ptr)
1958                         return  IXGBE_ERR_PARAM;
1959                 local_buffer = &buffer[ptr];
1960         }
1961
1962         if (size) {
1963                 start = 0;
1964                 length = size;
1965         } else {
1966                 start = 1;
1967                 length = local_buffer[0];
1968
1969                 /* Skip pointer section if length is invalid. */
1970                 if (length == 0xFFFF || length == 0 ||
1971                     (ptr + length) >= hw->eeprom.word_size)
1972                         return IXGBE_SUCCESS;
1973         }
1974
1975         if (buffer && ((u32)start + (u32)length > buffer_size))
1976                 return IXGBE_ERR_PARAM;
1977
1978         for (i = start; length; i++, length--) {
1979                 if (i == bufsz && !buffer) {
1980                         ptr += bufsz;
1981                         i = 0;
1982                         if (length < bufsz)
1983                                 bufsz = length;
1984
1985                         /* Read a chunk at the pointer location */
1986                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
1987                                                                   bufsz, buf);
1988                         if (status) {
1989                                 DEBUGOUT("Failed to read EEPROM image\n");
1990                                 return status;
1991                         }
1992                 }
1993                 *csum += local_buffer[i];
1994         }
1995         return IXGBE_SUCCESS;
1996 }
1997
1998 /**
1999  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2000  *  @hw: pointer to hardware structure
2001  *  @buffer: pointer to buffer containing calculated checksum
2002  *  @buffer_size: size of buffer
2003  *
2004  *  Returns a negative error code on error, or the 16-bit checksum
2005  **/
2006 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2007 {
2008         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2009         u16 *local_buffer;
2010         s32 status;
2011         u16 checksum = 0;
2012         u16 pointer, i, size;
2013
2014         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2015
2016         hw->eeprom.ops.init_params(hw);
2017
2018         if (!buffer) {
2019                 /* Read pointer area */
2020                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2021                                                      IXGBE_EEPROM_LAST_WORD + 1,
2022                                                      eeprom_ptrs);
2023                 if (status) {
2024                         DEBUGOUT("Failed to read EEPROM image\n");
2025                         return status;
2026                 }
2027                 local_buffer = eeprom_ptrs;
2028         } else {
2029                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2030                         return IXGBE_ERR_PARAM;
2031                 local_buffer = buffer;
2032         }
2033
2034         /*
2035          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2036          * checksum word itself
2037          */
2038         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2039                 if (i != IXGBE_EEPROM_CHECKSUM)
2040                         checksum += local_buffer[i];
2041
2042         /*
2043          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2044          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2045          */
2046         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2047                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2048                         continue;
2049
2050                 pointer = local_buffer[i];
2051
2052                 /* Skip pointer section if the pointer is invalid. */
2053                 if (pointer == 0xFFFF || pointer == 0 ||
2054                     pointer >= hw->eeprom.word_size)
2055                         continue;
2056
2057                 switch (i) {
2058                 case IXGBE_PCIE_GENERAL_PTR:
2059                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2060                         break;
2061                 case IXGBE_PCIE_CONFIG0_PTR:
2062                 case IXGBE_PCIE_CONFIG1_PTR:
2063                         size = IXGBE_PCIE_CONFIG_SIZE;
2064                         break;
2065                 default:
2066                         size = 0;
2067                         break;
2068                 }
2069
2070                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2071                                                 buffer, buffer_size);
2072                 if (status)
2073                         return status;
2074         }
2075
2076         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2077
2078         return (s32)checksum;
2079 }
2080
2081 /**
2082  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2083  *  @hw: pointer to hardware structure
2084  *
2085  *  Returns a negative error code on error, or the 16-bit checksum
2086  **/
2087 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2088 {
2089         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2090 }
2091
2092 /**
2093  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2094  *  @hw: pointer to hardware structure
2095  *  @checksum_val: calculated checksum
2096  *
2097  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2098  *  caller does not need checksum_val, the value can be NULL.
2099  **/
2100 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2101 {
2102         s32 status;
2103         u16 checksum;
2104         u16 read_checksum = 0;
2105
2106         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2107
2108         /* Read the first word from the EEPROM. If this times out or fails, do
2109          * not continue or we could be in for a very long wait while every
2110          * EEPROM read fails
2111          */
2112         status = hw->eeprom.ops.read(hw, 0, &checksum);
2113         if (status) {
2114                 DEBUGOUT("EEPROM read failed\n");
2115                 return status;
2116         }
2117
2118         status = hw->eeprom.ops.calc_checksum(hw);
2119         if (status < 0)
2120                 return status;
2121
2122         checksum = (u16)(status & 0xffff);
2123
2124         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2125                                            &read_checksum);
2126         if (status)
2127                 return status;
2128
2129         /* Verify read checksum from EEPROM is the same as
2130          * calculated checksum
2131          */
2132         if (read_checksum != checksum) {
2133                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2134                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2135                              "Invalid EEPROM checksum");
2136         }
2137
2138         /* If the user cares, return the calculated checksum */
2139         if (checksum_val)
2140                 *checksum_val = checksum;
2141
2142         return status;
2143 }
2144
2145 /**
2146  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2147  * @hw: pointer to hardware structure
2148  *
2149  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2150  * checksum and updates the EEPROM and instructs the hardware to update
2151  * the flash.
2152  **/
2153 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2154 {
2155         s32 status;
2156         u16 checksum = 0;
2157
2158         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2159
2160         /* Read the first word from the EEPROM. If this times out or fails, do
2161          * not continue or we could be in for a very long wait while every
2162          * EEPROM read fails
2163          */
2164         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2165         if (status) {
2166                 DEBUGOUT("EEPROM read failed\n");
2167                 return status;
2168         }
2169
2170         status = ixgbe_calc_eeprom_checksum_X550(hw);
2171         if (status < 0)
2172                 return status;
2173
2174         checksum = (u16)(status & 0xffff);
2175
2176         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2177                                             checksum);
2178         if (status)
2179                 return status;
2180
2181         status = ixgbe_update_flash_X550(hw);
2182
2183         return status;
2184 }
2185
2186 /**
2187  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2188  *  @hw: pointer to hardware structure
2189  *
2190  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2191  **/
2192 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2193 {
2194         s32 status = IXGBE_SUCCESS;
2195         union ixgbe_hic_hdr2 buffer;
2196
2197         DEBUGFUNC("ixgbe_update_flash_X550");
2198
2199         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2200         buffer.req.buf_lenh = 0;
2201         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2202         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2203
2204         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2205                                               sizeof(buffer),
2206                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2207
2208         return status;
2209 }
2210
2211 /**
2212  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2213  *  @hw: pointer to hardware structure
2214  *
2215  *  Determines physical layer capabilities of the current configuration.
2216  **/
2217 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2218 {
2219         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2220         u16 ext_ability = 0;
2221
2222         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2223
2224         hw->phy.ops.identify(hw);
2225
2226         switch (hw->phy.type) {
2227         case ixgbe_phy_x550em_kr:
2228                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2229                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2230                 break;
2231         case ixgbe_phy_x550em_kx4:
2232                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2233                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2234                 break;
2235         case ixgbe_phy_x550em_ext_t:
2236                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2237                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2238                                      &ext_ability);
2239                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2240                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2241                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2242                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2243                 break;
2244         default:
2245                 break;
2246         }
2247
2248         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2249                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2250
2251         return physical_layer;
2252 }
2253
2254 /**
2255  * ixgbe_get_bus_info_x550em - Set PCI bus info
2256  * @hw: pointer to hardware structure
2257  *
2258  * Sets bus link width and speed to unknown because X550em is
2259  * not a PCI device.
2260  **/
2261 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2262 {
2263
2264         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2265
2266         hw->bus.width = ixgbe_bus_width_unknown;
2267         hw->bus.speed = ixgbe_bus_speed_unknown;
2268
2269         return IXGBE_SUCCESS;
2270 }
2271
2272 /**
2273  * ixgbe_disable_rx_x550 - Disable RX unit
2274  *
2275  * Enables the Rx DMA unit for x550
2276  **/
2277 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2278 {
2279         u32 rxctrl, pfdtxgswc;
2280         s32 status;
2281         struct ixgbe_hic_disable_rxen fw_cmd;
2282
2283         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2284
2285         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2286         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2287                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2288                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2289                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2290                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2291                         hw->mac.set_lben = true;
2292                 } else {
2293                         hw->mac.set_lben = false;
2294                 }
2295
2296                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2297                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2298                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2299                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2300
2301                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2302                                         sizeof(struct ixgbe_hic_disable_rxen),
2303                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2304
2305                 /* If we fail - disable RX using register write */
2306                 if (status) {
2307                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2308                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2309                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2310                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2311                         }
2312                 }
2313         }
2314 }