drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41
  42 /**
  43  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  44  *  @hw: pointer to hardware structure
  45  *
  46  *  Initialize the function pointers and assign the MAC type for X550.
  47  *  Does not touch the hardware.
  48  **/
  49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  50 {
  51         struct ixgbe_mac_info *mac = &hw->mac;
  52         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  53         s32 ret_val;
  54
  55         DEBUGFUNC("ixgbe_init_ops_X550");
  56
  57         ret_val = ixgbe_init_ops_X540(hw);
  58         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  59         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  60         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  61         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  62         mac->ops.set_source_address_pruning =
  63                         ixgbe_set_source_address_pruning_X550;
  64         mac->ops.set_ethertype_anti_spoofing =
  65                         ixgbe_set_ethertype_anti_spoofing_X550;
  66
  67         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  68         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  69         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  70         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  71         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  72         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  73         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  74         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  75         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  76
  77         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  78         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  79         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  80         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  81         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  82         return ret_val;
  83 }
  84
  85 /**
  86  * ixgbe_read_cs4227 - Read CS4227 register
  87  * @hw: pointer to hardware structure
  88  * @reg: register number to write
  89  * @value: pointer to receive value read
  90  *
  91  * Returns status code
  92  **/
  93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  94 {
  95         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
  96 }
  97
  98 /**
  99  * ixgbe_write_cs4227 - Write CS4227 register
 100  * @hw: pointer to hardware structure
 101  * @reg: register number to write
 102  * @value: value to write to register
 103  *
 104  * Returns status code
 105  **/
 106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 107 {
 108         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 109 }
 110
 111 /**
 112  * ixgbe_get_cs4227_status - Return CS4227 status
 113  * @hw: pointer to hardware structure
 114  *
 115  * Returns error if CS4227 not successfully initialized
 116  **/
 117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
 118 {
 119         s32 status;
 120         u16 value = 0;
 121         u8 retry;
 122
 123         for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
 124                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
 125                                            &value);
 126                 if (status != IXGBE_SUCCESS)
 127                         return status;
 128                 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
 129                         break;
 130                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 131         }
 132         if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
 133                 return IXGBE_ERR_PHY;
 134
 135         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 136                                     IXGBE_CS4227_SCRATCH_VALUE);
 137         if (status != IXGBE_SUCCESS)
 138                 return status;
 139         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 140         if (status != IXGBE_SUCCESS)
 141                 return status;
 142         if (value != IXGBE_CS4227_SCRATCH_VALUE)
 143                 return IXGBE_ERR_PHY;
 144         return IXGBE_SUCCESS;
 145 }
 146
 147 /**
 148  * ixgbe_read_pe - Read register from port expander
 149  * @hw: pointer to hardware structure
 150  * @reg: register number to read
 151  * @value: pointer to receive read value
 152  *
 153  * Returns status code
 154  **/
 155 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 156 {
 157         s32 status;
 158
 159         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 160         if (status != IXGBE_SUCCESS)
 161                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 162                               "port expander access failed with %d\n", status);
 163         return status;
 164 }
 165
 166 /**
 167  * ixgbe_write_pe - Write register to port expander
 168  * @hw: pointer to hardware structure
 169  * @reg: register number to write
 170  * @value: value to write
 171  *
 172  * Returns status code
 173  **/
 174 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 175 {
 176         s32 status;
 177
 178         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 179         if (status != IXGBE_SUCCESS)
 180                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 181                               "port expander access failed with %d\n", status);
 182         return status;
 183 }
 184
 185 /**
 186  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 187  * @hw: pointer to hardware structure
 188  *
 189  * Returns error code
 190  **/
 191 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 192 {
 193         s32 status;
 194         u8 reg;
 195
 196         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199         reg |= IXGBE_PE_BIT1;
 200         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 201         if (status != IXGBE_SUCCESS)
 202                 return status;
 203
 204         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 205         if (status != IXGBE_SUCCESS)
 206                 return status;
 207         reg &= ~IXGBE_PE_BIT1;
 208         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 209         if (status != IXGBE_SUCCESS)
 210                 return status;
 211
 212         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 213         if (status != IXGBE_SUCCESS)
 214                 return status;
 215         reg &= ~IXGBE_PE_BIT1;
 216         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 217         if (status != IXGBE_SUCCESS)
 218                 return status;
 219
 220         usec_delay(IXGBE_CS4227_RESET_HOLD);
 221
 222         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 223         if (status != IXGBE_SUCCESS)
 224                 return status;
 225         reg |= IXGBE_PE_BIT1;
 226         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 227         if (status != IXGBE_SUCCESS)
 228                 return status;
 229
 230         msec_delay(IXGBE_CS4227_RESET_DELAY);
 231
 232         return IXGBE_SUCCESS;
 233 }
 234
 235 /**
 236  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 237  * @hw: pointer to hardware structure
 238  **/
 239 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 240 {
 241         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 242         s32 status;
 243         u8 retry;
 244
 245         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 246                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 247                 if (status != IXGBE_SUCCESS) {
 248                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 249                                       "semaphore failed with %d\n", status);
 250                         return;
 251                 }
 252                 status = ixgbe_get_cs4227_status(hw);
 253                 if (status == IXGBE_SUCCESS) {
 254                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 255                         msec_delay(hw->eeprom.semaphore_delay);
 256                         return;
 257                 }
 258                 ixgbe_reset_cs4227(hw);
 259                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 260                 msec_delay(hw->eeprom.semaphore_delay);
 261         }
 262         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 263                       "Unable to initialize CS4227, err=%d\n", status);
 264 }
 265
 266 /**
 267  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 268  * @hw: pointer to hardware structure
 269  **/
 270 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 271 {
 272         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 273
 274         if (hw->bus.lan_id) {
 275                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 276                 esdp |= IXGBE_ESDP_SDP1_DIR;
 277         }
 278         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 279         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 280         IXGBE_WRITE_FLUSH(hw);
 281 }
 282
 283 /**
 284  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 285  * @hw: pointer to hardware structure
 286  *
 287  * Returns error code
 288  */
 289 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 290 {
 291         switch (hw->device_id) {
 292         case IXGBE_DEV_ID_X550EM_X_SFP:
 293                 /* set up for CS4227 usage */
 294                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 295                 ixgbe_setup_mux_ctl(hw);
 296                 ixgbe_check_cs4227(hw);
 297
 298                 return ixgbe_identify_module_generic(hw);
 299                 break;
 300         case IXGBE_DEV_ID_X550EM_X_KX4:
 301                 hw->phy.type = ixgbe_phy_x550em_kx4;
 302                 break;
 303         case IXGBE_DEV_ID_X550EM_X_KR:
 304                 hw->phy.type = ixgbe_phy_x550em_kr;
 305                 break;
 306         case IXGBE_DEV_ID_X550EM_X_1G_T:
 307         case IXGBE_DEV_ID_X550EM_X_10G_T:
 308                 return ixgbe_identify_phy_generic(hw);
 309         default:
 310                 break;
 311         }
 312         return IXGBE_SUCCESS;
 313 }
 314
 315 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 316                                      u32 device_type, u16 *phy_data)
 317 {
 318         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 319         return IXGBE_NOT_IMPLEMENTED;
 320 }
 321
 322 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 323                                       u32 device_type, u16 phy_data)
 324 {
 325         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 326         return IXGBE_NOT_IMPLEMENTED;
 327 }
 328
 329 /**
 330 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 331 *  @hw: pointer to hardware structure
 332 *
 333 *  Initialize the function pointers and for MAC type X550EM.
 334 *  Does not touch the hardware.
 335 **/
 336 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 337 {
 338         struct ixgbe_mac_info *mac = &hw->mac;
 339         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 340         struct ixgbe_phy_info *phy = &hw->phy;
 341         s32 ret_val;
 342
 343         DEBUGFUNC("ixgbe_init_ops_X550EM");
 344
 345         /* Similar to X550 so start there. */
 346         ret_val = ixgbe_init_ops_X550(hw);
 347
 348         /* Since this function eventually calls
 349          * ixgbe_init_ops_540 by design, we are setting
 350          * the pointers to NULL explicitly here to overwrite
 351          * the values being set in the x540 function.
 352          */
 353         /* Thermal sensor not supported in x550EM */
 354         mac->ops.get_thermal_sensor_data = NULL;
 355         mac->ops.init_thermal_sensor_thresh = NULL;
 356         mac->thermal_sensor_enabled = false;
 357
 358         /* FCOE not supported in x550EM */
 359         mac->ops.get_san_mac_addr = NULL;
 360         mac->ops.set_san_mac_addr = NULL;
 361         mac->ops.get_wwn_prefix = NULL;
 362         mac->ops.get_fcoe_boot_status = NULL;
 363
 364         /* IPsec not supported in x550EM */
 365         mac->ops.disable_sec_rx_path = NULL;
 366         mac->ops.enable_sec_rx_path = NULL;
 367
 368         /* AUTOC register is not present in x550EM. */
 369         mac->ops.prot_autoc_read = NULL;
 370         mac->ops.prot_autoc_write = NULL;
 371
 372         /* X550EM bus type is internal*/
 373         hw->bus.type = ixgbe_bus_type_internal;
 374         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 375
 376         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 377         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 378         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 379         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 380         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 381         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 382         mac->ops.get_supported_physical_layer =
 383                                     ixgbe_get_supported_physical_layer_X550em;
 384
 385                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 386         /* PHY */
 387         phy->ops.init = ixgbe_init_phy_ops_X550em;
 388         phy->ops.identify = ixgbe_identify_phy_x550em;
 389         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 390                 phy->ops.set_phy_power = NULL;
 391
 392
 393         /* EEPROM */
 394         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 395         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 396         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 397         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 398         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 399         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 400         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 401         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 402
 403         return ret_val;
 404 }
 405
 406 /**
 407  *  ixgbe_dmac_config_X550
 408  *  @hw: pointer to hardware structure
 409  *
 410  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 411  *  When disabling dmac, dmac enable dmac bit is cleared.
 412  **/
 413 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 414 {
 415         u32 reg, high_pri_tc;
 416
 417         DEBUGFUNC("ixgbe_dmac_config_X550");
 418
 419         /* Disable DMA coalescing before configuring */
 420         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 421         reg &= ~IXGBE_DMACR_DMAC_EN;
 422         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 423
 424         /* Disable DMA Coalescing if the watchdog timer is 0 */
 425         if (!hw->mac.dmac_config.watchdog_timer)
 426                 goto out;
 427
 428         ixgbe_dmac_config_tcs_X550(hw);
 429
 430         /* Configure DMA Coalescing Control Register */
 431         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 432
 433         /* Set the watchdog timer in units of 40.96 usec */
 434         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 435         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 436
 437         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 438         /* If fcoe is enabled, set high priority traffic class */
 439         if (hw->mac.dmac_config.fcoe_en) {
 440                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 441                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 442                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 443         }
 444         reg |= IXGBE_DMACR_EN_MNG_IND;
 445
 446         /* Enable DMA coalescing after configuration */
 447         reg |= IXGBE_DMACR_DMAC_EN;
 448         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 449
 450 out:
 451         return IXGBE_SUCCESS;
 452 }
 453
 454 /**
 455  *  ixgbe_dmac_config_tcs_X550
 456  *  @hw: pointer to hardware structure
 457  *
 458  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 459  *  be cleared before configuring.
 460  **/
 461 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 462 {
 463         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 464
 465         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 466
 467         /* Configure DMA coalescing enabled */
 468         switch (hw->mac.dmac_config.link_speed) {
 469         case IXGBE_LINK_SPEED_100_FULL:
 470                 pb_headroom = IXGBE_DMACRXT_100M;
 471                 break;
 472         case IXGBE_LINK_SPEED_1GB_FULL:
 473                 pb_headroom = IXGBE_DMACRXT_1G;
 474                 break;
 475         default:
 476                 pb_headroom = IXGBE_DMACRXT_10G;
 477                 break;
 478         }
 479
 480         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 481                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 482
 483         /* Set the per Rx packet buffer receive threshold */
 484         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 485                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 486                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 487
 488                 if (tc < hw->mac.dmac_config.num_tcs) {
 489                         /* Get Rx PB size */
 490                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 491                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 492                                 IXGBE_RXPBSIZE_SHIFT;
 493
 494                         /* Calculate receive buffer threshold in kilobytes */
 495                         if (rx_pb_size > pb_headroom)
 496                                 rx_pb_size = rx_pb_size - pb_headroom;
 497                         else
 498                                 rx_pb_size = 0;
 499
 500                         /* Minimum of MFS shall be set for DMCTH */
 501                         reg |= (rx_pb_size > maxframe_size_kb) ?
 502                                 rx_pb_size : maxframe_size_kb;
 503                 }
 504                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 505         }
 506         return IXGBE_SUCCESS;
 507 }
 508
 509 /**
 510  *  ixgbe_dmac_update_tcs_X550
 511  *  @hw: pointer to hardware structure
 512  *
 513  *  Disables dmac, updates per TC settings, and then enables dmac.
 514  **/
 515 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 516 {
 517         u32 reg;
 518
 519         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 520
 521         /* Disable DMA coalescing before configuring */
 522         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 523         reg &= ~IXGBE_DMACR_DMAC_EN;
 524         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 525
 526         ixgbe_dmac_config_tcs_X550(hw);
 527
 528         /* Enable DMA coalescing after configuration */
 529         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 530         reg |= IXGBE_DMACR_DMAC_EN;
 531         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 532
 533         return IXGBE_SUCCESS;
 534 }
 535
 536 /**
 537  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 538  *  @hw: pointer to hardware structure
 539  *
 540  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 541  *  ixgbe_hw struct in order to set up EEPROM access.
 542  **/
 543 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 544 {
 545         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 546         u32 eec;
 547         u16 eeprom_size;
 548
 549         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 550
 551         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 552                 eeprom->semaphore_delay = 10;
 553                 eeprom->type = ixgbe_flash;
 554
 555                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 556                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 557                                     IXGBE_EEC_SIZE_SHIFT);
 558                 eeprom->word_size = 1 << (eeprom_size +
 559                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 560
 561                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 562                           eeprom->type, eeprom->word_size);
 563         }
 564
 565         return IXGBE_SUCCESS;
 566 }
 567
 568 /**
 569  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 570  *  @hw: pointer to the HW structure
 571  *  @enable_eee: boolean flag to enable EEE
 572  *
 573  *  Enable/disable EEE based on enable_eee flag.
 574  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 575  *  are modified.
 576  *
 577  **/
 578 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 579 {
 580         u32 eeer;
 581         u16 autoneg_eee_reg;
 582         u32 link_reg;
 583         s32 status;
 584
 585         DEBUGFUNC("ixgbe_setup_eee_X550");
 586
 587         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 588         /* Enable or disable EEE per flag */
 589         if (enable_eee) {
 590                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 591
 592                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 593                         /* Advertise EEE capability */
 594                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 595                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 596
 597                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 598                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 599                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 600
 601                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 602                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 603                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 604                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 605                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 606                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 607                         if (status != IXGBE_SUCCESS)
 608                                 return status;
 609
 610                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 611                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 612
 613                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 614                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 615                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 616                         if (status != IXGBE_SUCCESS)
 617                                 return status;
 618                 }
 619         } else {
 620                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 621
 622                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 623                         /* Disable advertised EEE capability */
 624                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 625                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 626
 627                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 628                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 629                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 630
 631                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 632                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 633                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 634                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 635                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 636                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 637                         if (status != IXGBE_SUCCESS)
 638                                 return status;
 639
 640                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 641                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 642
 643                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 644                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 645                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 646                         if (status != IXGBE_SUCCESS)
 647                                 return status;
 648                 }
 649         }
 650         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 651
 652         return IXGBE_SUCCESS;
 653 }
 654
 655 /**
 656  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 657  * @hw: pointer to hardware structure
 658  * @enable: enable or disable source address pruning
 659  * @pool: Rx pool to set source address pruning for
 660  **/
 661 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 662                                            unsigned int pool)
 663 {
 664         u64 pfflp;
 665
 666         /* max rx pool is 63 */
 667         if (pool > 63)
 668                 return;
 669
 670         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 671         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 672
 673         if (enable)
 674                 pfflp |= (1ULL << pool);
 675         else
 676                 pfflp &= ~(1ULL << pool);
 677
 678         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 679         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 680 }
 681
 682 /**
 683  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 684  *  @hw: pointer to hardware structure
 685  *  @enable: enable or disable switch for Ethertype anti-spoofing
 686  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 687  *
 688  **/
 689 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 690                 bool enable, int vf)
 691 {
 692         int vf_target_reg = vf >> 3;
 693         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 694         u32 pfvfspoof;
 695
 696         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 697
 698         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 699         if (enable)
 700                 pfvfspoof |= (1 << vf_target_shift);
 701         else
 702                 pfvfspoof &= ~(1 << vf_target_shift);
 703
 704         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 705 }
 706
 707 /**
 708  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 709  *  device
 710  *  @hw: pointer to hardware structure
 711  *  @reg_addr: 32 bit PHY register to write
 712  *  @device_type: 3 bit device type
 713  *  @data: Data to write to the register
 714  **/
 715 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 716                             u32 device_type, u32 data)
 717 {
 718         u32 i, command, error;
 719
 720         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 721                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 722
 723         /* Write IOSF control register */
 724         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 725
 726         /* Write IOSF data register */
 727         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 728         /*
 729          * Check every 10 usec to see if the address cycle completed.
 730          * The SB IOSF BUSY bit will clear when the operation is
 731          * complete
 732          */
 733         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 734                 usec_delay(10);
 735
 736                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 737                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 738                         break;
 739         }
 740
 741         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 742                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 743                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 744                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 745                               "Failed to write, error %x\n", error);
 746                 return IXGBE_ERR_PHY;
 747         }
 748
 749         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 750                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
 751                 return IXGBE_ERR_PHY;
 752         }
 753
 754         return IXGBE_SUCCESS;
 755 }
 756
 757 /**
 758  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 759  *  device
 760  *  @hw: pointer to hardware structure
 761  *  @reg_addr: 32 bit PHY register to write
 762  *  @device_type: 3 bit device type
 763  *  @phy_data: Pointer to read data from the register
 764  **/
 765 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 766                            u32 device_type, u32 *data)
 767 {
 768         u32 i, command, error;
 769
 770         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 771                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 772
 773         /* Write IOSF control register */
 774         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 775
 776         /*
 777          * Check every 10 usec to see if the address cycle completed.
 778          * The SB IOSF BUSY bit will clear when the operation is
 779          * complete
 780          */
 781         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 782                 usec_delay(10);
 783
 784                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 785                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 786                         break;
 787         }
 788
 789         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 790                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 791                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 792                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 793                                 "Failed to read, error %x\n", error);
 794                 return IXGBE_ERR_PHY;
 795         }
 796
 797         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 798                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
 799                 return IXGBE_ERR_PHY;
 800         }
 801
 802         *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 803
 804         return IXGBE_SUCCESS;
 805 }
 806
 807 /**
 808  *  ixgbe_disable_mdd_X550
 809  *  @hw: pointer to hardware structure
 810  *
 811  *  Disable malicious driver detection
 812  **/
 813 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 814 {
 815         u32 reg;
 816
 817         DEBUGFUNC("ixgbe_disable_mdd_X550");
 818
 819         /* Disable MDD for TX DMA and interrupt */
 820         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 821         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 822         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 823
 824         /* Disable MDD for RX and interrupt */
 825         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 826         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 827         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 828 }
 829
 830 /**
 831  *  ixgbe_enable_mdd_X550
 832  *  @hw: pointer to hardware structure
 833  *
 834  *  Enable malicious driver detection
 835  **/
 836 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 837 {
 838         u32 reg;
 839
 840         DEBUGFUNC("ixgbe_enable_mdd_X550");
 841
 842         /* Enable MDD for TX DMA and interrupt */
 843         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 844         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 845         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 846
 847         /* Enable MDD for RX and interrupt */
 848         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 849         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 850         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 851 }
 852
 853 /**
 854  *  ixgbe_restore_mdd_vf_X550
 855  *  @hw: pointer to hardware structure
 856  *  @vf: vf index
 857  *
 858  *  Restore VF that was disabled during malicious driver detection event
 859  **/
 860 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 861 {
 862         u32 idx, reg, num_qs, start_q, bitmask;
 863
 864         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 865
 866         /* Map VF to queues */
 867         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 868         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 869         case IXGBE_MRQC_VMDQRT8TCEN:
 870                 num_qs = 8;  /* 16 VFs / pools */
 871                 bitmask = 0x000000FF;
 872                 break;
 873         case IXGBE_MRQC_VMDQRSS32EN:
 874         case IXGBE_MRQC_VMDQRT4TCEN:
 875                 num_qs = 4;  /* 32 VFs / pools */
 876                 bitmask = 0x0000000F;
 877                 break;
 878         default:            /* 64 VFs / pools */
 879                 num_qs = 2;
 880                 bitmask = 0x00000003;
 881                 break;
 882         }
 883         start_q = vf * num_qs;
 884
 885         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 886         idx = start_q / 32;
 887         reg = 0;
 888         reg |= (bitmask << (start_q % 32));
 889         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 890         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 891 }
 892
 893 /**
 894  *  ixgbe_mdd_event_X550
 895  *  @hw: pointer to hardware structure
 896  *  @vf_bitmap: vf bitmap of malicious vfs
 897  *
 898  *  Handle malicious driver detection event.
 899  **/
 900 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 901 {
 902         u32 wqbr;
 903         u32 i, j, reg, q, shift, vf, idx;
 904
 905         DEBUGFUNC("ixgbe_mdd_event_X550");
 906
 907         /* figure out pool size for mapping to vf's */
 908         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 909         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 910         case IXGBE_MRQC_VMDQRT8TCEN:
 911                 shift = 3;  /* 16 VFs / pools */
 912                 break;
 913         case IXGBE_MRQC_VMDQRSS32EN:
 914         case IXGBE_MRQC_VMDQRT4TCEN:
 915                 shift = 2;  /* 32 VFs / pools */
 916                 break;
 917         default:
 918                 shift = 1;  /* 64 VFs / pools */
 919                 break;
 920         }
 921
 922         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
 923         for (i = 0; i < 4; i++) {
 924                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
 925                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
 926
 927                 if (!wqbr)
 928                         continue;
 929
 930                 /* Get malicious queue */
 931                 for (j = 0; j < 32 && wqbr; j++) {
 932
 933                         if (!(wqbr & (1 << j)))
 934                                 continue;
 935
 936                         /* Get queue from bitmask */
 937                         q = j + (i * 32);
 938
 939                         /* Map queue to vf */
 940                         vf = (q >> shift);
 941
 942                         /* Set vf bit in vf_bitmap */
 943                         idx = vf / 32;
 944                         vf_bitmap[idx] |= (1 << (vf % 32));
 945                         wqbr &= ~(1 << j);
 946                 }
 947         }
 948 }
 949
 950 /**
 951  *  ixgbe_get_media_type_X550em - Get media type
 952  *  @hw: pointer to hardware structure
 953  *
 954  *  Returns the media type (fiber, copper, backplane)
 955  */
 956 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
 957 {
 958         enum ixgbe_media_type media_type;
 959
 960         DEBUGFUNC("ixgbe_get_media_type_X550em");
 961
 962         /* Detect if there is a copper PHY attached. */
 963         switch (hw->device_id) {
 964         case IXGBE_DEV_ID_X550EM_X_KR:
 965         case IXGBE_DEV_ID_X550EM_X_KX4:
 966                 media_type = ixgbe_media_type_backplane;
 967                 break;
 968         case IXGBE_DEV_ID_X550EM_X_SFP:
 969                 media_type = ixgbe_media_type_fiber;
 970                 break;
 971         case IXGBE_DEV_ID_X550EM_X_1G_T:
 972         case IXGBE_DEV_ID_X550EM_X_10G_T:
 973                 media_type = ixgbe_media_type_copper;
 974                 break;
 975         default:
 976                 media_type = ixgbe_media_type_unknown;
 977                 break;
 978         }
 979         return media_type;
 980 }
 981
 982 /**
 983  *  ixgbe_setup_sfp_modules_X550em - Setup SFP module
 984  *  @hw: pointer to hardware structure
 985  */
 986 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
 987 {
 988         bool setup_linear;
 989         u16 reg_slice, edc_mode;
 990         s32 ret_val;
 991
 992         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
 993
 994         switch (hw->phy.sfp_type) {
 995         case ixgbe_sfp_type_unknown:
 996                 return IXGBE_SUCCESS;
 997         case ixgbe_sfp_type_not_present:
 998                 return IXGBE_ERR_SFP_NOT_PRESENT;
 999         case ixgbe_sfp_type_da_cu_core0:
1000         case ixgbe_sfp_type_da_cu_core1:
1001                 setup_linear = true;
1002                 break;
1003         case ixgbe_sfp_type_srlr_core0:
1004         case ixgbe_sfp_type_srlr_core1:
1005         case ixgbe_sfp_type_da_act_lmt_core0:
1006         case ixgbe_sfp_type_da_act_lmt_core1:
1007         case ixgbe_sfp_type_1g_sx_core0:
1008         case ixgbe_sfp_type_1g_sx_core1:
1009         case ixgbe_sfp_type_1g_lx_core0:
1010         case ixgbe_sfp_type_1g_lx_core1:
1011                 setup_linear = false;
1012                 break;
1013         default:
1014                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1015         }
1016
1017         ixgbe_init_mac_link_ops_X550em(hw);
1018         hw->phy.ops.reset = NULL;
1019
1020         /* The CS4227 slice address is the base address + the port-pair reg
1021          * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
1022          */
1023         reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12);
1024
1025         if (setup_linear)
1026                 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1027         else
1028                 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1029
1030         /* Configure CS4227 for connection type. */
1031         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1032                                            edc_mode);
1033
1034         if (ret_val != IXGBE_SUCCESS)
1035                 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
1036                                                    edc_mode);
1037
1038         return ret_val;
1039 }
1040
1041 /**
1042  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1043  *  @hw: pointer to hardware structure
1044  */
1045 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1046 {
1047         struct ixgbe_mac_info *mac = &hw->mac;
1048
1049         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1050
1051         /* CS4227 does not support autoneg, so disable the laser control
1052          * functions for SFP+ fiber
1053          */
1054          if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1055                 mac->ops.disable_tx_laser = NULL;
1056                 mac->ops.enable_tx_laser = NULL;
1057                 mac->ops.flap_tx_laser = NULL;
1058                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1059                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1060                 mac->ops.set_rate_select_speed =
1061                                         ixgbe_set_soft_rate_select_speed;
1062          }
1063 }
1064
1065 /**
1066  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1067  *  @hw: pointer to hardware structure
1068  *  @speed: pointer to link speed
1069  *  @autoneg: true when autoneg or autotry is enabled
1070  */
1071 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1072                                        ixgbe_link_speed *speed,
1073                                        bool *autoneg)
1074 {
1075         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1076
1077         /* SFP */
1078         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1079
1080                 /* CS4227 SFP must not enable auto-negotiation */
1081                 *autoneg = false;
1082
1083                 /* Check if 1G SFP module. */
1084                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1085                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1086                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1087                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1088                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1089                         return IXGBE_SUCCESS;
1090                 }
1091
1092                 /* Link capabilities are based on SFP */
1093                 if (hw->phy.multispeed_fiber)
1094                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1095                                  IXGBE_LINK_SPEED_1GB_FULL;
1096                 else
1097                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1098         } else {
1099                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1100                          IXGBE_LINK_SPEED_1GB_FULL;
1101                 *autoneg = true;
1102         }
1103
1104         return IXGBE_SUCCESS;
1105 }
1106
1107 /**
1108  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1109  *  @hw: pointer to hardware structure
1110  *
1111  *  Initialize any function pointers that were not able to be
1112  *  set during init_shared_code because the PHY/SFP type was
1113  *  not known.  Perform the SFP init if necessary.
1114  */
1115 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1116 {
1117         struct ixgbe_phy_info *phy = &hw->phy;
1118         s32 ret_val;
1119
1120         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1121
1122         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1123                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1124                 ixgbe_setup_mux_ctl(hw);
1125         }
1126
1127         /* Identify the PHY or SFP module */
1128         ret_val = phy->ops.identify(hw);
1129         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1130                 return ret_val;
1131
1132         /* Setup function pointers based on detected SFP module and speeds */
1133         ixgbe_init_mac_link_ops_X550em(hw);
1134         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1135                 phy->ops.reset = NULL;
1136
1137         /* Set functions pointers based on phy type */
1138         switch (hw->phy.type) {
1139         case ixgbe_phy_x550em_kx4:
1140                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1141                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1142                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1143                 break;
1144         case ixgbe_phy_x550em_kr:
1145                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1146                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1147                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1148                 break;
1149         case ixgbe_phy_x550em_ext_t:
1150                 phy->ops.setup_internal_link = ixgbe_setup_internal_phy_x550em;
1151                 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1152                 break;
1153         default:
1154                 break;
1155         }
1156         return ret_val;
1157 }
1158
1159 /**
1160  *  ixgbe_reset_hw_X550em - Perform hardware reset
1161  *  @hw: pointer to hardware structure
1162  *
1163  *  Resets the hardware by resetting the transmit and receive units, masks
1164  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1165  *  reset.
1166  */
1167 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1168 {
1169         struct ixgbe_hic_hdr fw_cmd;
1170         ixgbe_link_speed link_speed;
1171         s32 status;
1172         u32 ctrl = 0;
1173         u32 i;
1174         bool link_up = false;
1175
1176         DEBUGFUNC("ixgbe_reset_hw_X550em");
1177
1178         fw_cmd.cmd = FW_PHY_MGMT_REQ_CMD;
1179         fw_cmd.buf_len = 0;
1180         fw_cmd.cmd_or_resp.cmd_resv = 0;
1181         fw_cmd.checksum = FW_DEFAULT_CHECKSUM;
1182         status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
1183                                               sizeof(fw_cmd),
1184                                               IXGBE_HI_PHY_MGMT_REQ_TIMEOUT,
1185                                               true);
1186         if (status)
1187                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1188                               "PHY mgmt command failed with %d\n", status);
1189         else if (fw_cmd.cmd_or_resp.ret_status != FW_CEM_RESP_STATUS_SUCCESS)
1190                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1191                               "PHY mgmt command returned %d\n",
1192                               fw_cmd.cmd_or_resp.ret_status);
1193
1194         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1195         status = hw->mac.ops.stop_adapter(hw);
1196         if (status != IXGBE_SUCCESS)
1197                 return status;
1198
1199         /* flush pending Tx transactions */
1200         ixgbe_clear_tx_pending(hw);
1201
1202         /* PHY ops must be identified and initialized prior to reset */
1203
1204         /* Identify PHY and related function pointers */
1205         status = hw->phy.ops.init(hw);
1206
1207         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1208                 return status;
1209
1210         /* start the external PHY */
1211         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1212                 status = ixgbe_init_ext_t_x550em(hw);
1213                 if (status)
1214                         return status;
1215         }
1216
1217         /* Setup SFP module if there is one present. */
1218         if (hw->phy.sfp_setup_needed) {
1219                 status = hw->mac.ops.setup_sfp(hw);
1220                 hw->phy.sfp_setup_needed = false;
1221         }
1222
1223         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1224                 return status;
1225
1226         /* Reset PHY */
1227         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1228                 hw->phy.ops.reset(hw);
1229
1230 mac_reset_top:
1231         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1232          * If link reset is used when link is up, it might reset the PHY when
1233          * mng is using it.  If link is down or the flag to force full link
1234          * reset is set, then perform link reset.
1235          */
1236         ctrl = IXGBE_CTRL_LNK_RST;
1237         if (!hw->force_full_reset) {
1238                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1239                 if (link_up)
1240                         ctrl = IXGBE_CTRL_RST;
1241         }
1242
1243         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1244         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1245         IXGBE_WRITE_FLUSH(hw);
1246
1247         /* Poll for reset bit to self-clear meaning reset is complete */
1248         for (i = 0; i < 10; i++) {
1249                 usec_delay(1);
1250                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1251                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1252                         break;
1253         }
1254
1255         if (ctrl & IXGBE_CTRL_RST_MASK) {
1256                 status = IXGBE_ERR_RESET_FAILED;
1257                 DEBUGOUT("Reset polling failed to complete.\n");
1258         }
1259
1260         msec_delay(50);
1261
1262         /* Double resets are required for recovery from certain error
1263          * conditions.  Between resets, it is necessary to stall to
1264          * allow time for any pending HW events to complete.
1265          */
1266         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1267                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1268                 goto mac_reset_top;
1269         }
1270
1271         /* Store the permanent mac address */
1272         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1273
1274         /* Store MAC address from RAR0, clear receive address registers, and
1275          * clear the multicast table.  Also reset num_rar_entries to 128,
1276          * since we modify this value when programming the SAN MAC address.
1277          */
1278         hw->mac.num_rar_entries = 128;
1279         hw->mac.ops.init_rx_addrs(hw);
1280
1281
1282         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1283                 ixgbe_setup_mux_ctl(hw);
1284
1285         return status;
1286 }
1287
1288 /**
1289  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1290  * @hw: pointer to hardware structure
1291  */
1292 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1293 {
1294         u32 status;
1295         u16 reg;
1296
1297         status = hw->phy.ops.read_reg(hw,
1298                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1299                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1300                                       &reg);
1301
1302         if (status != IXGBE_SUCCESS)
1303                 return status;
1304
1305         /* If PHY FW reset completed bit is set then this is the first
1306          * SW instance after a power on so the PHY FW must be un-stalled.
1307          */
1308         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1309                 status = hw->phy.ops.read_reg(hw,
1310                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1311                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1312                                         &reg);
1313
1314                 if (status != IXGBE_SUCCESS)
1315                         return status;
1316
1317                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1318
1319                 status = hw->phy.ops.write_reg(hw,
1320                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1321                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1322                                         reg);
1323
1324                 if (status != IXGBE_SUCCESS)
1325                         return status;
1326         }
1327
1328         return status;
1329 }
1330
1331 /**
1332  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1333  *  @hw: pointer to hardware structure
1334  *
1335  *  Configures the integrated KR PHY.
1336  **/
1337 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1338 {
1339         s32 status;
1340         u32 reg_val;
1341
1342         status = ixgbe_read_iosf_sb_reg_x550(hw,
1343                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1344                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1345         if (status)
1346                 return status;
1347
1348         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1349         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1350                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1351         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1352                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1353
1354         /* Advertise 10G support. */
1355         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1356                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1357
1358         /* Advertise 1G support. */
1359         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1360                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1361
1362         /* Restart auto-negotiation. */
1363         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1364         status = ixgbe_write_iosf_sb_reg_x550(hw,
1365                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1366                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1367
1368         return status;
1369 }
1370
1371 /**
1372  *  ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1373  *  @hw: pointer to hardware structure
1374  *
1375  *  Configures the integrated KX4 PHY.
1376  **/
1377 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1378 {
1379         s32 status;
1380         u32 reg_val;
1381
1382         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1383                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, &reg_val);
1384         if (status)
1385                 return status;
1386
1387         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1388                         IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1389
1390         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1391
1392         /* Advertise 10G support. */
1393         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1394                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1395
1396         /* Advertise 1G support. */
1397         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1398                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1399
1400         /* Restart auto-negotiation. */
1401         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1402         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1403                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, reg_val);
1404
1405         return status;
1406 }
1407
1408 /**
1409  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1410  *  @hw: pointer to hardware structure
1411  *  @speed: the link speed to force
1412  *
1413  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1414  *  internal and external PHY at a specific speed, without autonegotiation.
1415  **/
1416 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1417 {
1418         s32 status;
1419         u32 reg_val;
1420
1421         /* Disable AN and force speed to 10G Serial. */
1422         status = ixgbe_read_iosf_sb_reg_x550(hw,
1423                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1424                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1425         if (status != IXGBE_SUCCESS)
1426                 return status;
1427
1428         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1429         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1430
1431         /* Select forced link speed for internal PHY. */
1432         switch (*speed) {
1433         case IXGBE_LINK_SPEED_10GB_FULL:
1434                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1435                 break;
1436         case IXGBE_LINK_SPEED_1GB_FULL:
1437                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1438                 break;
1439         default:
1440                 /* Other link speeds are not supported by internal KR PHY. */
1441                 return IXGBE_ERR_LINK_SETUP;
1442         }
1443
1444         status = ixgbe_write_iosf_sb_reg_x550(hw,
1445                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1446                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1447         if (status != IXGBE_SUCCESS)
1448                 return status;
1449
1450         /* Disable training protocol FSM. */
1451         status = ixgbe_read_iosf_sb_reg_x550(hw,
1452                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1453                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1454         if (status != IXGBE_SUCCESS)
1455                 return status;
1456         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1457         status = ixgbe_write_iosf_sb_reg_x550(hw,
1458                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1459                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1460         if (status != IXGBE_SUCCESS)
1461                 return status;
1462
1463         /* Disable Flex from training TXFFE. */
1464         status = ixgbe_read_iosf_sb_reg_x550(hw,
1465                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1466                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1467         if (status != IXGBE_SUCCESS)
1468                 return status;
1469         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1470         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1471         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1472         status = ixgbe_write_iosf_sb_reg_x550(hw,
1473                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1474                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1475         if (status != IXGBE_SUCCESS)
1476                 return status;
1477         status = ixgbe_read_iosf_sb_reg_x550(hw,
1478                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1479                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1480         if (status != IXGBE_SUCCESS)
1481                 return status;
1482         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1483         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1484         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1485         status = ixgbe_write_iosf_sb_reg_x550(hw,
1486                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1487                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1488         if (status != IXGBE_SUCCESS)
1489                 return status;
1490
1491         /* Enable override for coefficients. */
1492         status = ixgbe_read_iosf_sb_reg_x550(hw,
1493                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1494                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1495         if (status != IXGBE_SUCCESS)
1496                 return status;
1497         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1498         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1499         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1500         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1501         status = ixgbe_write_iosf_sb_reg_x550(hw,
1502                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1503                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1504         if (status != IXGBE_SUCCESS)
1505                 return status;
1506
1507         /* Toggle port SW reset by AN reset. */
1508         status = ixgbe_read_iosf_sb_reg_x550(hw,
1509                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1510                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1511         if (status != IXGBE_SUCCESS)
1512                 return status;
1513         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1514         status = ixgbe_write_iosf_sb_reg_x550(hw,
1515                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1516                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1517
1518         return status;
1519 }
1520
1521 /**
1522  *  ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1523  *  @hw: pointer to hardware structure
1524  *
1525  *  Configures the integrated KR PHY for SFP support.
1526  **/
1527 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1528                                     ixgbe_link_speed speed,
1529                                     bool autoneg_wait_to_complete)
1530 {
1531         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1532
1533         return ixgbe_setup_ixfi_x550em(hw, &speed);
1534 }
1535
1536 /**
1537  * ixgbe_setup_internal_phy_x550em - Configure integrated KR PHY
1538  * @hw: point to hardware structure
1539  *
1540  * Configures the integrated KR PHY to talk to the external PHY. The base
1541  * driver will call this function when it gets notification via interrupt from
1542  * the external PHY. This function forces the internal PHY into iXFI mode at
1543  * the correct speed.
1544  *
1545  * A return of a non-zero value indicates an error, and the base driver should
1546  * not report link up.
1547  */
1548 s32 ixgbe_setup_internal_phy_x550em(struct ixgbe_hw *hw)
1549 {
1550         u32 status;
1551         u16 lasi, autoneg_status, speed;
1552         ixgbe_link_speed force_speed;
1553
1554         /* Verify that the external link status has changed */
1555         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_XENPAK_LASI_STATUS,
1556                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1557                                       &lasi);
1558         if (status != IXGBE_SUCCESS)
1559                 return status;
1560
1561         /* If there was no change in link status, we can just exit */
1562         if (!(lasi & IXGBE_XENPAK_LASI_LINK_STATUS_ALARM))
1563                 return IXGBE_SUCCESS;
1564
1565         /* we read this twice back to back to indicate current status */
1566         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1567                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1568                                       &autoneg_status);
1569         if (status != IXGBE_SUCCESS)
1570                 return status;
1571
1572         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1573                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1574                                       &autoneg_status);
1575         if (status != IXGBE_SUCCESS)
1576                 return status;
1577
1578         /* If link is not up return an error indicating treat link as down */
1579         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1580                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1581
1582         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1583                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1584                                       &speed);
1585
1586         /* clear everything but the speed and duplex bits */
1587         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1588
1589         switch (speed) {
1590         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1591                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1592                 break;
1593         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1594                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1595                 break;
1596         default:
1597                 /* Internal PHY does not support anything else */
1598                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1599         }
1600
1601         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1602 }
1603
1604 /**
1605  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1606  *  @hw: pointer to hardware structure
1607  *
1608  *  Configures the integrated KR PHY to use internal loopback mode.
1609  **/
1610 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1611 {
1612         s32 status;
1613         u32 reg_val;
1614
1615         /* Disable AN and force speed to 10G Serial. */
1616         status = ixgbe_read_iosf_sb_reg_x550(hw,
1617                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1618                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1619         if (status != IXGBE_SUCCESS)
1620                 return status;
1621         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1622         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1623         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1624         status = ixgbe_write_iosf_sb_reg_x550(hw,
1625                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1626                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1627         if (status != IXGBE_SUCCESS)
1628                 return status;
1629
1630         /* Set near-end loopback clocks. */
1631         status = ixgbe_read_iosf_sb_reg_x550(hw,
1632                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1633                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1634         if (status != IXGBE_SUCCESS)
1635                 return status;
1636         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1637         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1638         status = ixgbe_write_iosf_sb_reg_x550(hw,
1639                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1640                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1641         if (status != IXGBE_SUCCESS)
1642                 return status;
1643
1644         /* Set loopback enable. */
1645         status = ixgbe_read_iosf_sb_reg_x550(hw,
1646                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1647                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1648         if (status != IXGBE_SUCCESS)
1649                 return status;
1650         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1651         status = ixgbe_write_iosf_sb_reg_x550(hw,
1652                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1653                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1654         if (status != IXGBE_SUCCESS)
1655                 return status;
1656
1657         /* Training bypass. */
1658         status = ixgbe_read_iosf_sb_reg_x550(hw,
1659                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1660                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1661         if (status != IXGBE_SUCCESS)
1662                 return status;
1663         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1664         status = ixgbe_write_iosf_sb_reg_x550(hw,
1665                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1666                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1667
1668         return status;
1669 }
1670
1671 /**
1672  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1673  *  assuming that the semaphore is already obtained.
1674  *  @hw: pointer to hardware structure
1675  *  @offset: offset of  word in the EEPROM to read
1676  *  @data: word read from the EEPROM
1677  *
1678  *  Reads a 16 bit word from the EEPROM using the hostif.
1679  **/
1680 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1681                                    u16 *data)
1682 {
1683         s32 status;
1684         struct ixgbe_hic_read_shadow_ram buffer;
1685
1686         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1687         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1688         buffer.hdr.req.buf_lenh = 0;
1689         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1690         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1691
1692         /* convert offset from words to bytes */
1693         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1694         /* one word */
1695         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1696
1697         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1698                                               sizeof(buffer),
1699                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1700
1701         if (status)
1702                 return status;
1703
1704         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1705                                           FW_NVM_DATA_OFFSET);
1706
1707         return 0;
1708 }
1709
1710 /**
1711  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1712  *  @hw: pointer to hardware structure
1713  *  @offset: offset of  word in the EEPROM to read
1714  *  @data: word read from the EEPROM
1715  *
1716  *  Reads a 16 bit word from the EEPROM using the hostif.
1717  **/
1718 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1719                               u16 *data)
1720 {
1721         s32 status = IXGBE_SUCCESS;
1722
1723         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1724
1725         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1726             IXGBE_SUCCESS) {
1727                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1728                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1729         } else {
1730                 status = IXGBE_ERR_SWFW_SYNC;
1731         }
1732
1733         return status;
1734 }
1735
1736 /**
1737  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1738  *  @hw: pointer to hardware structure
1739  *  @offset: offset of  word in the EEPROM to read
1740  *  @words: number of words
1741  *  @data: word(s) read from the EEPROM
1742  *
1743  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
1744  **/
1745 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1746                                      u16 offset, u16 words, u16 *data)
1747 {
1748         struct ixgbe_hic_read_shadow_ram buffer;
1749         u32 current_word = 0;
1750         u16 words_to_read;
1751         s32 status;
1752         u32 i;
1753
1754         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1755
1756         /* Take semaphore for the entire operation. */
1757         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1758         if (status) {
1759                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1760                 return status;
1761         }
1762         while (words) {
1763                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1764                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1765                 else
1766                         words_to_read = words;
1767
1768                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1769                 buffer.hdr.req.buf_lenh = 0;
1770                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1771                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1772
1773                 /* convert offset from words to bytes */
1774                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1775                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1776
1777                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1778                                                       sizeof(buffer),
1779                                                       IXGBE_HI_COMMAND_TIMEOUT,
1780                                                       false);
1781
1782                 if (status) {
1783                         DEBUGOUT("Host interface command failed\n");
1784                         goto out;
1785                 }
1786
1787                 for (i = 0; i < words_to_read; i++) {
1788                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1789                                   2 * i;
1790                         u32 value = IXGBE_READ_REG(hw, reg);
1791
1792                         data[current_word] = (u16)(value & 0xffff);
1793                         current_word++;
1794                         i++;
1795                         if (i < words_to_read) {
1796                                 value >>= 16;
1797                                 data[current_word] = (u16)(value & 0xffff);
1798                                 current_word++;
1799                         }
1800                 }
1801                 words -= words_to_read;
1802         }
1803
1804 out:
1805         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1806         return status;
1807 }
1808
1809 /**
1810  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1811  *  @hw: pointer to hardware structure
1812  *  @offset: offset of  word in the EEPROM to write
1813  *  @data: word write to the EEPROM
1814  *
1815  *  Write a 16 bit word to the EEPROM using the hostif.
1816  **/
1817 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1818                                     u16 data)
1819 {
1820         s32 status;
1821         struct ixgbe_hic_write_shadow_ram buffer;
1822
1823         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1824
1825         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1826         buffer.hdr.req.buf_lenh = 0;
1827         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1828         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1829
1830          /* one word */
1831         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1832         buffer.data = data;
1833         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1834
1835         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1836                                               sizeof(buffer),
1837                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1838
1839         return status;
1840 }
1841
1842 /**
1843  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1844  *  @hw: pointer to hardware structure
1845  *  @offset: offset of  word in the EEPROM to write
1846  *  @data: word write to the EEPROM
1847  *
1848  *  Write a 16 bit word to the EEPROM using the hostif.
1849  **/
1850 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1851                                u16 data)
1852 {
1853         s32 status = IXGBE_SUCCESS;
1854
1855         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
1856
1857         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1858             IXGBE_SUCCESS) {
1859                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1860                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1861         } else {
1862                 DEBUGOUT("write ee hostif failed to get semaphore");
1863                 status = IXGBE_ERR_SWFW_SYNC;
1864         }
1865
1866         return status;
1867 }
1868
1869 /**
1870  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1871  *  @hw: pointer to hardware structure
1872  *  @offset: offset of  word in the EEPROM to write
1873  *  @words: number of words
1874  *  @data: word(s) write to the EEPROM
1875  *
1876  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1877  **/
1878 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1879                                       u16 offset, u16 words, u16 *data)
1880 {
1881         s32 status = IXGBE_SUCCESS;
1882         u32 i = 0;
1883
1884         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
1885
1886         /* Take semaphore for the entire operation. */
1887         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1888         if (status != IXGBE_SUCCESS) {
1889                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
1890                 goto out;
1891         }
1892
1893         for (i = 0; i < words; i++) {
1894                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1895                                                          data[i]);
1896
1897                 if (status != IXGBE_SUCCESS) {
1898                         DEBUGOUT("Eeprom buffered write failed\n");
1899                         break;
1900                 }
1901         }
1902
1903         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1904 out:
1905
1906         return status;
1907 }
1908
1909 /**
1910  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
1911  * @hw: pointer to hardware structure
1912  * @ptr: pointer offset in eeprom
1913  * @size: size of section pointed by ptr, if 0 first word will be used as size
1914  * @csum: address of checksum to update
1915  *
1916  * Returns error status for any failure
1917  */
1918 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
1919                                    u16 size, u16 *csum, u16 *buffer,
1920                                    u32 buffer_size)
1921 {
1922         u16 buf[256];
1923         s32 status;
1924         u16 length, bufsz, i, start;
1925         u16 *local_buffer;
1926
1927         bufsz = sizeof(buf) / sizeof(buf[0]);
1928
1929         /* Read a chunk at the pointer location */
1930         if (!buffer) {
1931                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
1932                 if (status) {
1933                         DEBUGOUT("Failed to read EEPROM image\n");
1934                         return status;
1935                 }
1936                 local_buffer = buf;
1937         } else {
1938                 if (buffer_size < ptr)
1939                         return  IXGBE_ERR_PARAM;
1940                 local_buffer = &buffer[ptr];
1941         }
1942
1943         if (size) {
1944                 start = 0;
1945                 length = size;
1946         } else {
1947                 start = 1;
1948                 length = local_buffer[0];
1949
1950                 /* Skip pointer section if length is invalid. */
1951                 if (length == 0xFFFF || length == 0 ||
1952                     (ptr + length) >= hw->eeprom.word_size)
1953                         return IXGBE_SUCCESS;
1954         }
1955
1956         if (buffer && ((u32)start + (u32)length > buffer_size))
1957                 return IXGBE_ERR_PARAM;
1958
1959         for (i = start; length; i++, length--) {
1960                 if (i == bufsz && !buffer) {
1961                         ptr += bufsz;
1962                         i = 0;
1963                         if (length < bufsz)
1964                                 bufsz = length;
1965
1966                         /* Read a chunk at the pointer location */
1967                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
1968                                                                   bufsz, buf);
1969                         if (status) {
1970                                 DEBUGOUT("Failed to read EEPROM image\n");
1971                                 return status;
1972                         }
1973                 }
1974                 *csum += local_buffer[i];
1975         }
1976         return IXGBE_SUCCESS;
1977 }
1978
1979 /**
1980  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
1981  *  @hw: pointer to hardware structure
1982  *  @buffer: pointer to buffer containing calculated checksum
1983  *  @buffer_size: size of buffer
1984  *
1985  *  Returns a negative error code on error, or the 16-bit checksum
1986  **/
1987 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
1988 {
1989         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
1990         u16 *local_buffer;
1991         s32 status;
1992         u16 checksum = 0;
1993         u16 pointer, i, size;
1994
1995         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
1996
1997         hw->eeprom.ops.init_params(hw);
1998
1999         if (!buffer) {
2000                 /* Read pointer area */
2001                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2002                                                      IXGBE_EEPROM_LAST_WORD + 1,
2003                                                      eeprom_ptrs);
2004                 if (status) {
2005                         DEBUGOUT("Failed to read EEPROM image\n");
2006                         return status;
2007                 }
2008                 local_buffer = eeprom_ptrs;
2009         } else {
2010                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2011                         return IXGBE_ERR_PARAM;
2012                 local_buffer = buffer;
2013         }
2014
2015         /*
2016          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2017          * checksum word itself
2018          */
2019         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2020                 if (i != IXGBE_EEPROM_CHECKSUM)
2021                         checksum += local_buffer[i];
2022
2023         /*
2024          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2025          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2026          */
2027         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2028                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2029                         continue;
2030
2031                 pointer = local_buffer[i];
2032
2033                 /* Skip pointer section if the pointer is invalid. */
2034                 if (pointer == 0xFFFF || pointer == 0 ||
2035                     pointer >= hw->eeprom.word_size)
2036                         continue;
2037
2038                 switch (i) {
2039                 case IXGBE_PCIE_GENERAL_PTR:
2040                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2041                         break;
2042                 case IXGBE_PCIE_CONFIG0_PTR:
2043                 case IXGBE_PCIE_CONFIG1_PTR:
2044                         size = IXGBE_PCIE_CONFIG_SIZE;
2045                         break;
2046                 default:
2047                         size = 0;
2048                         break;
2049                 }
2050
2051                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2052                                                 buffer, buffer_size);
2053                 if (status)
2054                         return status;
2055         }
2056
2057         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2058
2059         return (s32)checksum;
2060 }
2061
2062 /**
2063  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2064  *  @hw: pointer to hardware structure
2065  *
2066  *  Returns a negative error code on error, or the 16-bit checksum
2067  **/
2068 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2069 {
2070         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2071 }
2072
2073 /**
2074  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2075  *  @hw: pointer to hardware structure
2076  *  @checksum_val: calculated checksum
2077  *
2078  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2079  *  caller does not need checksum_val, the value can be NULL.
2080  **/
2081 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2082 {
2083         s32 status;
2084         u16 checksum;
2085         u16 read_checksum = 0;
2086
2087         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2088
2089         /* Read the first word from the EEPROM. If this times out or fails, do
2090          * not continue or we could be in for a very long wait while every
2091          * EEPROM read fails
2092          */
2093         status = hw->eeprom.ops.read(hw, 0, &checksum);
2094         if (status) {
2095                 DEBUGOUT("EEPROM read failed\n");
2096                 return status;
2097         }
2098
2099         status = hw->eeprom.ops.calc_checksum(hw);
2100         if (status < 0)
2101                 return status;
2102
2103         checksum = (u16)(status & 0xffff);
2104
2105         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2106                                            &read_checksum);
2107         if (status)
2108                 return status;
2109
2110         /* Verify read checksum from EEPROM is the same as
2111          * calculated checksum
2112          */
2113         if (read_checksum != checksum) {
2114                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2115                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2116                              "Invalid EEPROM checksum");
2117         }
2118
2119         /* If the user cares, return the calculated checksum */
2120         if (checksum_val)
2121                 *checksum_val = checksum;
2122
2123         return status;
2124 }
2125
2126 /**
2127  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2128  * @hw: pointer to hardware structure
2129  *
2130  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2131  * checksum and updates the EEPROM and instructs the hardware to update
2132  * the flash.
2133  **/
2134 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2135 {
2136         s32 status;
2137         u16 checksum = 0;
2138
2139         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2140
2141         /* Read the first word from the EEPROM. If this times out or fails, do
2142          * not continue or we could be in for a very long wait while every
2143          * EEPROM read fails
2144          */
2145         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2146         if (status) {
2147                 DEBUGOUT("EEPROM read failed\n");
2148                 return status;
2149         }
2150
2151         status = ixgbe_calc_eeprom_checksum_X550(hw);
2152         if (status < 0)
2153                 return status;
2154
2155         checksum = (u16)(status & 0xffff);
2156
2157         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2158                                             checksum);
2159         if (status)
2160                 return status;
2161
2162         status = ixgbe_update_flash_X550(hw);
2163
2164         return status;
2165 }
2166
2167 /**
2168  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2169  *  @hw: pointer to hardware structure
2170  *
2171  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2172  **/
2173 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2174 {
2175         s32 status = IXGBE_SUCCESS;
2176         union ixgbe_hic_hdr2 buffer;
2177
2178         DEBUGFUNC("ixgbe_update_flash_X550");
2179
2180         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2181         buffer.req.buf_lenh = 0;
2182         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2183         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2184
2185         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2186                                               sizeof(buffer),
2187                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2188
2189         return status;
2190 }
2191
2192 /**
2193  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2194  *  @hw: pointer to hardware structure
2195  *
2196  *  Determines physical layer capabilities of the current configuration.
2197  **/
2198 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2199 {
2200         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2201         u16 ext_ability = 0;
2202
2203         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2204
2205         hw->phy.ops.identify(hw);
2206
2207         switch (hw->phy.type) {
2208         case ixgbe_phy_x550em_kr:
2209                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2210                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2211                 break;
2212         case ixgbe_phy_x550em_kx4:
2213                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2214                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2215                 break;
2216         case ixgbe_phy_x550em_ext_t:
2217                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2218                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2219                                      &ext_ability);
2220                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2221                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2222                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2223                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2224                 break;
2225         default:
2226                 break;
2227         }
2228
2229         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2230                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2231
2232         return physical_layer;
2233 }
2234
2235 /**
2236  * ixgbe_get_bus_info_x550em - Set PCI bus info
2237  * @hw: pointer to hardware structure
2238  *
2239  * Sets bus link width and speed to unknown because X550em is
2240  * not a PCI device.
2241  **/
2242 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2243 {
2244
2245         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2246
2247         hw->bus.width = ixgbe_bus_width_unknown;
2248         hw->bus.speed = ixgbe_bus_speed_unknown;
2249
2250         return IXGBE_SUCCESS;
2251 }
2252
2253 /**
2254  * ixgbe_disable_rx_x550 - Disable RX unit
2255  *
2256  * Enables the Rx DMA unit for x550
2257  **/
2258 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2259 {
2260         u32 rxctrl, pfdtxgswc;
2261         s32 status;
2262         struct ixgbe_hic_disable_rxen fw_cmd;
2263
2264         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2265
2266         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2267         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2268                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2269                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2270                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2271                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2272                         hw->mac.set_lben = true;
2273                 } else {
2274                         hw->mac.set_lben = false;
2275                 }
2276
2277                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2278                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2279                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2280                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2281
2282                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2283                                         sizeof(struct ixgbe_hic_disable_rxen),
2284                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2285
2286                 /* If we fail - disable RX using register write */
2287                 if (status) {
2288                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2289                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2290                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2291                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2292                         }
2293                 }
2294         }
2295 }
2296
2297 /**
2298  * ixgbe_enter_lplu_x550em - Transition to low power states
2299  *  @hw: pointer to hardware structure
2300  *
2301  * Configures Low Power Link Up on transition to low power states
2302  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2303  * X557 PHY immediately prior to entering LPLU.
2304  **/
2305 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2306 {
2307         u16 autoneg_status, an_10g_cntl_reg, autoneg_reg, speed;
2308         s32 status;
2309         ixgbe_link_speed lcd_speed;
2310
2311         /* If blocked by MNG FW, then don't restart AN */
2312         if (ixgbe_check_reset_blocked(hw))
2313                 return IXGBE_SUCCESS;
2314
2315         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2316                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2317                                       &autoneg_status);
2318
2319         if (status != IXGBE_SUCCESS)
2320                 return status;
2321
2322         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2323
2324         if (status != IXGBE_SUCCESS)
2325                 return status;
2326
2327         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2328          * disabled, then force link down by entering low power mode.
2329          */
2330         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS) ||
2331             !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2332             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2333                 return ixgbe_set_copper_phy_power(hw, FALSE);
2334
2335         /* Determine LCD */
2336         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2337
2338         if (status != IXGBE_SUCCESS)
2339                 return status;
2340
2341         /* If no valid LCD link speed, then force link down and exit. */
2342         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2343                 return ixgbe_set_copper_phy_power(hw, FALSE);
2344
2345         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2346                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2347                                       &speed);
2348
2349         if (status != IXGBE_SUCCESS)
2350                 return status;
2351
2352         /* clear everything but the speed bits */
2353         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2354
2355         /* If current speed is already LCD, then exit. */
2356         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2357              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2358             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2359              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2360                 return status;
2361
2362         /* Clear AN completed indication */
2363         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2364                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2365                                       &autoneg_status);
2366
2367         if (status != IXGBE_SUCCESS)
2368                 return status;
2369
2370         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2371                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2372                              &an_10g_cntl_reg);
2373
2374         if (status != IXGBE_SUCCESS)
2375                 return status;
2376
2377         status = hw->phy.ops.read_reg(hw,
2378                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2379                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2380                              &autoneg_reg);
2381
2382         if (status != IXGBE_SUCCESS)
2383                 return status;
2384
2385         /* Set AN advertizement to only include LCD  */
2386         if (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL) {
2387                 an_10g_cntl_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
2388                 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
2389         }
2390
2391         if (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL) {
2392                 an_10g_cntl_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
2393                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
2394         }
2395
2396         status = hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2397                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2398                               an_10g_cntl_reg);
2399
2400         if (status != IXGBE_SUCCESS)
2401                 return status;
2402
2403         status = hw->phy.ops.write_reg(hw,
2404                               IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2405                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2406                               autoneg_reg);
2407
2408         if (status != IXGBE_SUCCESS)
2409                 return status;
2410
2411         /* Restart PHY auto-negotiation. */
2412         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
2413                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
2414
2415         if (status != IXGBE_SUCCESS)
2416                 return status;
2417
2418         autoneg_reg |= IXGBE_MII_RESTART;
2419
2420         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
2421                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
2422
2423         if (status != IXGBE_SUCCESS)
2424                 return status;
2425
2426         status = ixgbe_setup_ixfi_x550em(hw, &lcd_speed);
2427
2428         return status;
2429 }
2430
2431 /**
2432  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2433  *  @hw: pointer to hardware structure
2434  *  @lcd_speed: pointer to lowest common link speed
2435  *
2436  * Determine lowest common link speed with link partner.
2437  **/
2438 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2439 {
2440         u16 an_lp_status;
2441         s32 status;
2442         u16 word = hw->eeprom.ctrl_word_3;
2443
2444         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2445
2446         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2447                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2448                                       &an_lp_status);
2449
2450         if (status != IXGBE_SUCCESS)
2451                 return status;
2452
2453         /* If link partner advertised 1G, return 1G */
2454         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2455                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2456                 return status;
2457         }
2458
2459         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2460         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2461             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2462                 return status;
2463
2464         /* Link partner not capable of lower speeds, return 10G */
2465         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2466         return status;
2467 }
2468
2469 /**
2470  *  ixgbe_setup_fc_X550em - Set up flow control
2471  *  @hw: pointer to hardware structure
2472  *
2473  *  Called at init time to set up flow control.
2474  **/
2475 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2476 {
2477         s32 ret_val = IXGBE_SUCCESS;
2478         u32 pause, asm_dir, reg_val;
2479
2480         DEBUGFUNC("ixgbe_setup_fc_X550em");
2481
2482         /* Validate the requested mode */
2483         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2484                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2485                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2486                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2487                 goto out;
2488         }
2489
2490         /* 10gig parts do not have a word in the EEPROM to determine the
2491          * default flow control setting, so we explicitly set it to full.
2492          */
2493         if (hw->fc.requested_mode == ixgbe_fc_default)
2494                 hw->fc.requested_mode = ixgbe_fc_full;
2495
2496         /* Determine PAUSE and ASM_DIR bits. */
2497         switch (hw->fc.requested_mode) {
2498         case ixgbe_fc_none:
2499                 pause = 0;
2500                 asm_dir = 0;
2501                 break;
2502         case ixgbe_fc_tx_pause:
2503                 pause = 0;
2504                 asm_dir = 1;
2505                 break;
2506         case ixgbe_fc_rx_pause:
2507                 /* Rx Flow control is enabled and Tx Flow control is
2508                  * disabled by software override. Since there really
2509                  * isn't a way to advertise that we are capable of RX
2510                  * Pause ONLY, we will advertise that we support both
2511                  * symmetric and asymmetric Rx PAUSE, as such we fall
2512                  * through to the fc_full statement.  Later, we will
2513                  * disable the adapter's ability to send PAUSE frames.
2514                  */
2515         case ixgbe_fc_full:
2516                 pause = 1;
2517                 asm_dir = 1;
2518                 break;
2519         default:
2520                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2521                         "Flow control param set incorrectly\n");
2522                 ret_val = IXGBE_ERR_CONFIG;
2523                 goto out;
2524         }
2525
2526         if (hw->phy.media_type == ixgbe_media_type_backplane) {
2527                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2528                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2529                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2530                 if (ret_val != IXGBE_SUCCESS)
2531                         goto out;
2532                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2533                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2534                 if (pause)
2535                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2536                 if (asm_dir)
2537                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2538                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2539                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2540                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2541
2542                 /* Not all devices fully support AN. */
2543                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR)
2544                         hw->fc.disable_fc_autoneg = true;
2545         }
2546
2547 out:
2548         return ret_val;
2549 }