drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44
  45 /**
  46  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  47  *  @hw: pointer to hardware structure
  48  *
  49  *  Initialize the function pointers and assign the MAC type for X550.
  50  *  Does not touch the hardware.
  51  **/
  52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  53 {
  54         struct ixgbe_mac_info *mac = &hw->mac;
  55         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  56         s32 ret_val;
  57
  58         DEBUGFUNC("ixgbe_init_ops_X550");
  59
  60         ret_val = ixgbe_init_ops_X540(hw);
  61         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  62         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  63         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  64         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  65         mac->ops.set_source_address_pruning =
  66                         ixgbe_set_source_address_pruning_X550;
  67         mac->ops.set_ethertype_anti_spoofing =
  68                         ixgbe_set_ethertype_anti_spoofing_X550;
  69
  70         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  71         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  72         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  73         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  74         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  75         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  76         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  77         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  78         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  79
  80         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  81         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  82         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  83         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  84         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  85         switch (hw->device_id) {
  86         case IXGBE_DEV_ID_X550EM_X_10G_T:
  87         case IXGBE_DEV_ID_X550EM_A_10G_T:
  88                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  89                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  90                 break;
  91         default:
  92                 break;
  93         }
  94         return ret_val;
  95 }
  96
  97 /**
  98  * ixgbe_read_cs4227 - Read CS4227 register
  99  * @hw: pointer to hardware structure
 100  * @reg: register number to write
 101  * @value: pointer to receive value read
 102  *
 103  * Returns status code
 104  **/
 105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 106 {
 107         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 108 }
 109
 110 /**
 111  * ixgbe_write_cs4227 - Write CS4227 register
 112  * @hw: pointer to hardware structure
 113  * @reg: register number to write
 114  * @value: value to write to register
 115  *
 116  * Returns status code
 117  **/
 118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 119 {
 120         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 121 }
 122
 123 /**
 124  * ixgbe_read_pe - Read register from port expander
 125  * @hw: pointer to hardware structure
 126  * @reg: register number to read
 127  * @value: pointer to receive read value
 128  *
 129  * Returns status code
 130  **/
 131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 132 {
 133         s32 status;
 134
 135         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 136         if (status != IXGBE_SUCCESS)
 137                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 138                               "port expander access failed with %d\n", status);
 139         return status;
 140 }
 141
 142 /**
 143  * ixgbe_write_pe - Write register to port expander
 144  * @hw: pointer to hardware structure
 145  * @reg: register number to write
 146  * @value: value to write
 147  *
 148  * Returns status code
 149  **/
 150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 151 {
 152         s32 status;
 153
 154         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 155         if (status != IXGBE_SUCCESS)
 156                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 157                               "port expander access failed with %d\n", status);
 158         return status;
 159 }
 160
 161 /**
 162  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 163  * @hw: pointer to hardware structure
 164  *
 165  * This function assumes that the caller has acquired the proper semaphore.
 166  * Returns error code
 167  **/
 168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 169 {
 170         s32 status;
 171         u32 retry;
 172         u16 value;
 173         u8 reg;
 174
 175         /* Trigger hard reset. */
 176         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 177         if (status != IXGBE_SUCCESS)
 178                 return status;
 179         reg |= IXGBE_PE_BIT1;
 180         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 181         if (status != IXGBE_SUCCESS)
 182                 return status;
 183
 184         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 185         if (status != IXGBE_SUCCESS)
 186                 return status;
 187         reg &= ~IXGBE_PE_BIT1;
 188         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 189         if (status != IXGBE_SUCCESS)
 190                 return status;
 191
 192         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 193         if (status != IXGBE_SUCCESS)
 194                 return status;
 195         reg &= ~IXGBE_PE_BIT1;
 196         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199
 200         usec_delay(IXGBE_CS4227_RESET_HOLD);
 201
 202         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 203         if (status != IXGBE_SUCCESS)
 204                 return status;
 205         reg |= IXGBE_PE_BIT1;
 206         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 207         if (status != IXGBE_SUCCESS)
 208                 return status;
 209
 210         /* Wait for the reset to complete. */
 211         msec_delay(IXGBE_CS4227_RESET_DELAY);
 212         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 213                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 214                                            &value);
 215                 if (status == IXGBE_SUCCESS &&
 216                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 217                         break;
 218                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 219         }
 220         if (retry == IXGBE_CS4227_RETRIES) {
 221                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 222                         "CS4227 reset did not complete.");
 223                 return IXGBE_ERR_PHY;
 224         }
 225
 226         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 227         if (status != IXGBE_SUCCESS ||
 228             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 229                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 230                         "CS4227 EEPROM did not load successfully.");
 231                 return IXGBE_ERR_PHY;
 232         }
 233
 234         return IXGBE_SUCCESS;
 235 }
 236
 237 /**
 238  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 239  * @hw: pointer to hardware structure
 240  **/
 241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 242 {
 243         s32 status = IXGBE_SUCCESS;
 244         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 245         u16 value = 0;
 246         u8 retry;
 247
 248         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 249                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 250                 if (status != IXGBE_SUCCESS) {
 251                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 252                                 "semaphore failed with %d", status);
 253                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 254                         continue;
 255                 }
 256
 257                 /* Get status of reset flow. */
 258                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 259
 260                 if (status == IXGBE_SUCCESS &&
 261                     value == IXGBE_CS4227_RESET_COMPLETE)
 262                         goto out;
 263
 264                 if (status != IXGBE_SUCCESS ||
 265                     value != IXGBE_CS4227_RESET_PENDING)
 266                         break;
 267
 268                 /* Reset is pending. Wait and check again. */
 269                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 270                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 271         }
 272
 273         /* If still pending, assume other instance failed. */
 274         if (retry == IXGBE_CS4227_RETRIES) {
 275                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 276                 if (status != IXGBE_SUCCESS) {
 277                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 278                                       "semaphore failed with %d", status);
 279                         return;
 280                 }
 281         }
 282
 283         /* Reset the CS4227. */
 284         status = ixgbe_reset_cs4227(hw);
 285         if (status != IXGBE_SUCCESS) {
 286                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 287                         "CS4227 reset failed: %d", status);
 288                 goto out;
 289         }
 290
 291         /* Reset takes so long, temporarily release semaphore in case the
 292          * other driver instance is waiting for the reset indication.
 293          */
 294         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 295                            IXGBE_CS4227_RESET_PENDING);
 296         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 297         msec_delay(10);
 298         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 299         if (status != IXGBE_SUCCESS) {
 300                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 301                         "semaphore failed with %d", status);
 302                 return;
 303         }
 304
 305         /* Record completion for next time. */
 306         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 307                 IXGBE_CS4227_RESET_COMPLETE);
 308
 309 out:
 310         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 311         msec_delay(hw->eeprom.semaphore_delay);
 312 }
 313
 314 /**
 315  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 316  * @hw: pointer to hardware structure
 317  **/
 318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 319 {
 320         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 321
 322         if (hw->bus.lan_id) {
 323                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 324                 esdp |= IXGBE_ESDP_SDP1_DIR;
 325         }
 326         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 327         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 328         IXGBE_WRITE_FLUSH(hw);
 329 }
 330
 331 /**
 332  * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
 333  * @hw: pointer to hardware structure
 334  * @reg_addr: 32 bit address of PHY register to read
 335  * @dev_type: always unused
 336  * @phy_data: Pointer to read data from PHY register
 337  */
 338 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 339                                      u32 dev_type, u16 *phy_data)
 340 {
 341         u32 i, data, command;
 342         UNREFERENCED_1PARAMETER(dev_type);
 343
 344         /* Setup and write the read command */
 345         command = (reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 346                 (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 347                 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 348                 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ |
 349                 IXGBE_MSCA_MDI_COMMAND;
 350
 351         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 352
 353         /* Check every 10 usec to see if the access completed.
 354          * The MDI Command bit will clear when the operation is
 355          * complete
 356          */
 357         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 358                 usec_delay(10);
 359
 360                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 361                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 362                         break;
 363         }
 364
 365         if (command & IXGBE_MSCA_MDI_COMMAND) {
 366                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 367                               "PHY read command did not complete.\n");
 368                 return IXGBE_ERR_PHY;
 369         }
 370
 371         /* Read operation is complete.  Get the data from MSRWD */
 372         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 373         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 374         *phy_data = (u16)data;
 375
 376         return IXGBE_SUCCESS;
 377 }
 378
 379 /**
 380  * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
 381  * @hw: pointer to hardware structure
 382  * @reg_addr: 32 bit PHY register to write
 383  * @dev_type: always unused
 384  * @phy_data: Data to write to the PHY register
 385  */
 386 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 387                                       u32 dev_type, u16 phy_data)
 388 {
 389         u32 i, command;
 390         UNREFERENCED_1PARAMETER(dev_type);
 391
 392         /* Put the data in the MDI single read and write data register*/
 393         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 394
 395         /* Setup and write the write command */
 396         command = (reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 397                 (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 398                 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 399                 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
 400                 IXGBE_MSCA_MDI_COMMAND;
 401
 402         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 403
 404         /* Check every 10 usec to see if the access completed.
 405          * The MDI Command bit will clear when the operation is
 406          * complete
 407          */
 408         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 409                 usec_delay(10);
 410
 411                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 412                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 413                         break;
 414         }
 415
 416         if (command & IXGBE_MSCA_MDI_COMMAND) {
 417                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 418                               "PHY write cmd didn't complete\n");
 419                 return IXGBE_ERR_PHY;
 420         }
 421
 422         return IXGBE_SUCCESS;
 423 }
 424
 425 /**
 426  * ixgbe_identify_phy_1g - Get 1g PHY type based on device id
 427  * @hw: pointer to hardware structure
 428  *
 429  * Returns error code
 430  */
 431 STATIC s32 ixgbe_identify_phy_1g(struct ixgbe_hw *hw)
 432 {
 433         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 434         u16 phy_id_high;
 435         u16 phy_id_low;
 436         s32 rc;
 437
 438         rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 439         if (rc)
 440                 return rc;
 441
 442         rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_MDIO_PHY_ID_HIGH, 0,
 443                                        &phy_id_high);
 444         if (rc)
 445                 goto rel_out;
 446
 447         rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_MDIO_PHY_ID_LOW, 0,
 448                                        &phy_id_low);
 449         if (rc)
 450                 goto rel_out;
 451
 452         hw->phy.id = (u32)phy_id_high << 16;
 453         hw->phy.id |= phy_id_low & IXGBE_PHY_REVISION_MASK;
 454         hw->phy.revision = (u32)phy_id_low & ~IXGBE_PHY_REVISION_MASK;
 455
 456 rel_out:
 457         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 458
 459         return rc;
 460 }
 461
 462 /**
 463  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 464  * @hw: pointer to hardware structure
 465  *
 466  * Returns error code
 467  */
 468 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 469 {
 470         switch (hw->device_id) {
 471         case IXGBE_DEV_ID_X550EM_A_SFP:
 472                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
 473                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
 474                 if (hw->bus.lan_id)
 475                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 476                 else
 477                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 478                 return ixgbe_identify_module_generic(hw);
 479         case IXGBE_DEV_ID_X550EM_X_SFP:
 480                 /* set up for CS4227 usage */
 481                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 482                 ixgbe_setup_mux_ctl(hw);
 483                 ixgbe_check_cs4227(hw);
 484                 /* Fallthrough */
 485
 486         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 487                 return ixgbe_identify_module_generic(hw);
 488                 break;
 489         case IXGBE_DEV_ID_X550EM_X_KX4:
 490                 hw->phy.type = ixgbe_phy_x550em_kx4;
 491                 break;
 492         case IXGBE_DEV_ID_X550EM_X_KR:
 493         case IXGBE_DEV_ID_X550EM_A_KR:
 494         case IXGBE_DEV_ID_X550EM_A_KR_L:
 495                 hw->phy.type = ixgbe_phy_x550em_kr;
 496                 break;
 497         case IXGBE_DEV_ID_X550EM_A_10G_T:
 498                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
 499                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
 500        /* Fallthrough to ixgbe_identify_phy_generic */
 501         case IXGBE_DEV_ID_X550EM_X_1G_T:
 502         case IXGBE_DEV_ID_X550EM_X_10G_T:
 503                 return ixgbe_identify_phy_generic(hw);
 504         case IXGBE_DEV_ID_X550EM_A_1G_T:
 505         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 506                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
 507                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
 508                 if (hw->bus.lan_id)
 509                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 510                 else
 511                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 512                 return ixgbe_identify_phy_1g(hw);
 513         default:
 514                 break;
 515         }
 516         return IXGBE_SUCCESS;
 517 }
 518
 519 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 520                                      u32 device_type, u16 *phy_data)
 521 {
 522         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 523         return IXGBE_NOT_IMPLEMENTED;
 524 }
 525
 526 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 527                                       u32 device_type, u16 phy_data)
 528 {
 529         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 530         return IXGBE_NOT_IMPLEMENTED;
 531 }
 532
 533 /**
 534  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 535  * @hw: pointer to the hardware structure
 536  * @addr: I2C bus address to read from
 537  * @reg: I2C device register to read from
 538  * @val: pointer to location to receive read value
 539  *
 540  * Returns an error code on error.
 541  **/
 542 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 543                                            u16 reg, u16 *val)
 544 {
 545         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 546 }
 547
 548 /**
 549  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 550  * @hw: pointer to the hardware structure
 551  * @addr: I2C bus address to read from
 552  * @reg: I2C device register to read from
 553  * @val: pointer to location to receive read value
 554  *
 555  * Returns an error code on error.
 556  **/
 557 STATIC s32
 558 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 559                                          u16 reg, u16 *val)
 560 {
 561         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 562 }
 563
 564 /**
 565  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 566  * @hw: pointer to the hardware structure
 567  * @addr: I2C bus address to write to
 568  * @reg: I2C device register to write to
 569  * @val: value to write
 570  *
 571  * Returns an error code on error.
 572  **/
 573 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 574                                             u8 addr, u16 reg, u16 val)
 575 {
 576         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 577 }
 578
 579 /**
 580  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 581  * @hw: pointer to the hardware structure
 582  * @addr: I2C bus address to write to
 583  * @reg: I2C device register to write to
 584  * @val: value to write
 585  *
 586  * Returns an error code on error.
 587  **/
 588 STATIC s32
 589 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 590                                           u8 addr, u16 reg, u16 val)
 591 {
 592         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 593 }
 594
 595 /**
 596 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 597 *  @hw: pointer to hardware structure
 598 *
 599 *  Initialize the function pointers and for MAC type X550EM.
 600 *  Does not touch the hardware.
 601 **/
 602 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 603 {
 604         struct ixgbe_mac_info *mac = &hw->mac;
 605         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 606         struct ixgbe_phy_info *phy = &hw->phy;
 607         struct ixgbe_link_info *link = &hw->link;
 608         s32 ret_val;
 609
 610         DEBUGFUNC("ixgbe_init_ops_X550EM");
 611
 612         /* Similar to X550 so start there. */
 613         ret_val = ixgbe_init_ops_X550(hw);
 614
 615         /* Since this function eventually calls
 616          * ixgbe_init_ops_540 by design, we are setting
 617          * the pointers to NULL explicitly here to overwrite
 618          * the values being set in the x540 function.
 619          */
 620         /* Thermal sensor not supported in x550EM */
 621         mac->ops.get_thermal_sensor_data = NULL;
 622         mac->ops.init_thermal_sensor_thresh = NULL;
 623         mac->thermal_sensor_enabled = false;
 624
 625         /* FCOE not supported in x550EM */
 626         mac->ops.get_san_mac_addr = NULL;
 627         mac->ops.set_san_mac_addr = NULL;
 628         mac->ops.get_wwn_prefix = NULL;
 629         mac->ops.get_fcoe_boot_status = NULL;
 630
 631         /* IPsec not supported in x550EM */
 632         mac->ops.disable_sec_rx_path = NULL;
 633         mac->ops.enable_sec_rx_path = NULL;
 634
 635         /* AUTOC register is not present in x550EM. */
 636         mac->ops.prot_autoc_read = NULL;
 637         mac->ops.prot_autoc_write = NULL;
 638
 639         /* X550EM bus type is internal*/
 640         hw->bus.type = ixgbe_bus_type_internal;
 641         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 642
 643         if (hw->mac.type == ixgbe_mac_X550EM_x) {
 644                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 645                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 646                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 647                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 648                 link->ops.read_link = ixgbe_read_i2c_combined_generic;
 649                 link->ops.read_link_unlocked =
 650                                 ixgbe_read_i2c_combined_generic_unlocked;
 651                 link->ops.write_link = ixgbe_write_i2c_combined_generic;
 652                 link->ops.write_link_unlocked =
 653                                 ixgbe_write_i2c_combined_generic_unlocked;
 654                 link->addr = IXGBE_CS4227;
 655         }
 656         if (hw->mac.type == ixgbe_mac_X550EM_a) {
 657                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 658                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 659                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 660                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 661         }
 662
 663         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 664         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 665         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 666         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 667         mac->ops.get_supported_physical_layer =
 668                                     ixgbe_get_supported_physical_layer_X550em;
 669
 670         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 671                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 672         else if (hw->mac.type == ixgbe_mac_X550EM_a) {
 673                 mac->ops.setup_fc = ixgbe_setup_fc_x550a;
 674                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_x550a;
 675         }
 676         else
 677                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 678
 679         switch (hw->device_id) {
 680         case IXGBE_DEV_ID_X550EM_X_KR:
 681         case IXGBE_DEV_ID_X550EM_A_KR:
 682         case IXGBE_DEV_ID_X550EM_A_KR_L:
 683                 break;
 684         default:
 685                 mac->ops.setup_eee = NULL;
 686         }
 687
 688         /* PHY */
 689         phy->ops.init = ixgbe_init_phy_ops_X550em;
 690         phy->ops.identify = ixgbe_identify_phy_x550em;
 691         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 692                 phy->ops.set_phy_power = NULL;
 693
 694
 695         /* EEPROM */
 696         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 697         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 698         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 699         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 700         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 701         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 702         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 703         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 704
 705         return ret_val;
 706 }
 707
 708 /**
 709  *  ixgbe_dmac_config_X550
 710  *  @hw: pointer to hardware structure
 711  *
 712  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 713  *  When disabling dmac, dmac enable dmac bit is cleared.
 714  **/
 715 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 716 {
 717         u32 reg, high_pri_tc;
 718
 719         DEBUGFUNC("ixgbe_dmac_config_X550");
 720
 721         /* Disable DMA coalescing before configuring */
 722         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 723         reg &= ~IXGBE_DMACR_DMAC_EN;
 724         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 725
 726         /* Disable DMA Coalescing if the watchdog timer is 0 */
 727         if (!hw->mac.dmac_config.watchdog_timer)
 728                 goto out;
 729
 730         ixgbe_dmac_config_tcs_X550(hw);
 731
 732         /* Configure DMA Coalescing Control Register */
 733         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 734
 735         /* Set the watchdog timer in units of 40.96 usec */
 736         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 737         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 738
 739         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 740         /* If fcoe is enabled, set high priority traffic class */
 741         if (hw->mac.dmac_config.fcoe_en) {
 742                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 743                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 744                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 745         }
 746         reg |= IXGBE_DMACR_EN_MNG_IND;
 747
 748         /* Enable DMA coalescing after configuration */
 749         reg |= IXGBE_DMACR_DMAC_EN;
 750         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 751
 752 out:
 753         return IXGBE_SUCCESS;
 754 }
 755
 756 /**
 757  *  ixgbe_dmac_config_tcs_X550
 758  *  @hw: pointer to hardware structure
 759  *
 760  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 761  *  be cleared before configuring.
 762  **/
 763 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 764 {
 765         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 766
 767         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 768
 769         /* Configure DMA coalescing enabled */
 770         switch (hw->mac.dmac_config.link_speed) {
 771         case IXGBE_LINK_SPEED_100_FULL:
 772                 pb_headroom = IXGBE_DMACRXT_100M;
 773                 break;
 774         case IXGBE_LINK_SPEED_1GB_FULL:
 775                 pb_headroom = IXGBE_DMACRXT_1G;
 776                 break;
 777         default:
 778                 pb_headroom = IXGBE_DMACRXT_10G;
 779                 break;
 780         }
 781
 782         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 783                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 784
 785         /* Set the per Rx packet buffer receive threshold */
 786         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 787                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 788                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 789
 790                 if (tc < hw->mac.dmac_config.num_tcs) {
 791                         /* Get Rx PB size */
 792                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 793                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 794                                 IXGBE_RXPBSIZE_SHIFT;
 795
 796                         /* Calculate receive buffer threshold in kilobytes */
 797                         if (rx_pb_size > pb_headroom)
 798                                 rx_pb_size = rx_pb_size - pb_headroom;
 799                         else
 800                                 rx_pb_size = 0;
 801
 802                         /* Minimum of MFS shall be set for DMCTH */
 803                         reg |= (rx_pb_size > maxframe_size_kb) ?
 804                                 rx_pb_size : maxframe_size_kb;
 805                 }
 806                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 807         }
 808         return IXGBE_SUCCESS;
 809 }
 810
 811 /**
 812  *  ixgbe_dmac_update_tcs_X550
 813  *  @hw: pointer to hardware structure
 814  *
 815  *  Disables dmac, updates per TC settings, and then enables dmac.
 816  **/
 817 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 818 {
 819         u32 reg;
 820
 821         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 822
 823         /* Disable DMA coalescing before configuring */
 824         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 825         reg &= ~IXGBE_DMACR_DMAC_EN;
 826         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 827
 828         ixgbe_dmac_config_tcs_X550(hw);
 829
 830         /* Enable DMA coalescing after configuration */
 831         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 832         reg |= IXGBE_DMACR_DMAC_EN;
 833         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 834
 835         return IXGBE_SUCCESS;
 836 }
 837
 838 /**
 839  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 840  *  @hw: pointer to hardware structure
 841  *
 842  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 843  *  ixgbe_hw struct in order to set up EEPROM access.
 844  **/
 845 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 846 {
 847         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 848         u32 eec;
 849         u16 eeprom_size;
 850
 851         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 852
 853         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 854                 eeprom->semaphore_delay = 10;
 855                 eeprom->type = ixgbe_flash;
 856
 857                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 858                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 859                                     IXGBE_EEC_SIZE_SHIFT);
 860                 eeprom->word_size = 1 << (eeprom_size +
 861                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 862
 863                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 864                           eeprom->type, eeprom->word_size);
 865         }
 866
 867         return IXGBE_SUCCESS;
 868 }
 869
 870 /**
 871  * ixgbe_enable_eee_x550 - Enable EEE support
 872  * @hw: pointer to hardware structure
 873  */
 874 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
 875 {
 876         u16 autoneg_eee_reg;
 877         u32 link_reg;
 878         s32 status;
 879
 880         if (hw->mac.type == ixgbe_mac_X550) {
 881                 /* Advertise EEE capability */
 882                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 883                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 884                                      &autoneg_eee_reg);
 885
 886                 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 887                                     IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 888                                     IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 889
 890                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 891                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 892                                       autoneg_eee_reg);
 893                 return IXGBE_SUCCESS;
 894         }
 895
 896         switch (hw->device_id) {
 897         case IXGBE_DEV_ID_X550EM_X_KR:
 898         case IXGBE_DEV_ID_X550EM_A_KR:
 899         case IXGBE_DEV_ID_X550EM_A_KR_L:
 900                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 901                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 902                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 903                 if (status != IXGBE_SUCCESS)
 904                         return status;
 905
 906                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 907                         IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 908
 909                 /* Don't advertise FEC capability when EEE enabled. */
 910                 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 911
 912                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 913                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 914                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 915                 if (status != IXGBE_SUCCESS)
 916                         return status;
 917                 break;
 918         default:
 919                 break;
 920         }
 921
 922         return IXGBE_SUCCESS;
 923 }
 924
 925 /**
 926  * ixgbe_disable_eee_x550 - Disable EEE support
 927  * @hw: pointer to hardware structure
 928  */
 929 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
 930 {
 931         u16 autoneg_eee_reg;
 932         u32 link_reg;
 933         s32 status;
 934
 935         if (hw->mac.type == ixgbe_mac_X550) {
 936                 /* Disable advertised EEE capability */
 937                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 938                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 939                                      &autoneg_eee_reg);
 940
 941                 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 942                                      IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 943                                      IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 944
 945                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 946                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 947                                       autoneg_eee_reg);
 948                 return IXGBE_SUCCESS;
 949         }
 950
 951         switch (hw->device_id) {
 952         case IXGBE_DEV_ID_X550EM_X_KR:
 953         case IXGBE_DEV_ID_X550EM_A_KR:
 954         case IXGBE_DEV_ID_X550EM_A_KR_L:
 955                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 956                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 957                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 958                 if (status != IXGBE_SUCCESS)
 959                         return status;
 960
 961                 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 962                               IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 963
 964                 /* Advertise FEC capability when EEE is disabled. */
 965                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 966
 967                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 968                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 969                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 970                 if (status != IXGBE_SUCCESS)
 971                         return status;
 972                 break;
 973         default:
 974                 break;
 975         }
 976
 977         return IXGBE_SUCCESS;
 978 }
 979
 980 /**
 981  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 982  *  @hw: pointer to the HW structure
 983  *  @enable_eee: boolean flag to enable EEE
 984  *
 985  *  Enable/disable EEE based on enable_eee flag.
 986  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 987  *  are modified.
 988  *
 989  **/
 990 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 991 {
 992         s32 status;
 993         u32 eeer;
 994
 995         DEBUGFUNC("ixgbe_setup_eee_X550");
 996
 997         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 998         /* Enable or disable EEE per flag */
 999         if (enable_eee) {
1000                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1001
1002                 /* Not supported on first revision of X550EM_x. */
1003                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1004                     !(IXGBE_FUSES0_REV_MASK &
1005                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1006                         return IXGBE_SUCCESS;
1007                 status = ixgbe_enable_eee_x550(hw);
1008                 if (status)
1009                         return status;
1010         } else {
1011                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1012
1013                 status = ixgbe_disable_eee_x550(hw);
1014                 if (status)
1015                         return status;
1016         }
1017         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1018
1019         return IXGBE_SUCCESS;
1020 }
1021
1022 /**
1023  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1024  * @hw: pointer to hardware structure
1025  * @enable: enable or disable source address pruning
1026  * @pool: Rx pool to set source address pruning for
1027  **/
1028 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1029                                            unsigned int pool)
1030 {
1031         u64 pfflp;
1032
1033         /* max rx pool is 63 */
1034         if (pool > 63)
1035                 return;
1036
1037         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1038         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1039
1040         if (enable)
1041                 pfflp |= (1ULL << pool);
1042         else
1043                 pfflp &= ~(1ULL << pool);
1044
1045         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1046         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1047 }
1048
1049 /**
1050  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1051  *  @hw: pointer to hardware structure
1052  *  @enable: enable or disable switch for Ethertype anti-spoofing
1053  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1054  *
1055  **/
1056 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1057                 bool enable, int vf)
1058 {
1059         int vf_target_reg = vf >> 3;
1060         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1061         u32 pfvfspoof;
1062
1063         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1064
1065         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1066         if (enable)
1067                 pfvfspoof |= (1 << vf_target_shift);
1068         else
1069                 pfvfspoof &= ~(1 << vf_target_shift);
1070
1071         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1072 }
1073
1074 /**
1075  * ixgbe_iosf_wait - Wait for IOSF command completion
1076  * @hw: pointer to hardware structure
1077  * @ctrl: pointer to location to receive final IOSF control value
1078  *
1079  * Returns failing status on timeout
1080  *
1081  * Note: ctrl can be NULL if the IOSF control register value is not needed
1082  **/
1083 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1084 {
1085         u32 i, command = 0;
1086
1087         /* Check every 10 usec to see if the address cycle completed.
1088          * The SB IOSF BUSY bit will clear when the operation is
1089          * complete
1090          */
1091         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1092                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1093                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1094                         break;
1095                 usec_delay(10);
1096         }
1097         if (ctrl)
1098                 *ctrl = command;
1099         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1100                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1101                 return IXGBE_ERR_PHY;
1102         }
1103
1104         return IXGBE_SUCCESS;
1105 }
1106
1107 /**
1108  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1109  *  device
1110  *  @hw: pointer to hardware structure
1111  *  @reg_addr: 32 bit PHY register to write
1112  *  @device_type: 3 bit device type
1113  *  @data: Data to write to the register
1114  **/
1115 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1116                             u32 device_type, u32 data)
1117 {
1118         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1119         u32 command, error;
1120         s32 ret;
1121
1122         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1123         if (ret != IXGBE_SUCCESS)
1124                 return ret;
1125
1126         ret = ixgbe_iosf_wait(hw, NULL);
1127         if (ret != IXGBE_SUCCESS)
1128                 goto out;
1129
1130         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1131                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1132
1133         /* Write IOSF control register */
1134         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1135
1136         /* Write IOSF data register */
1137         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1138
1139         ret = ixgbe_iosf_wait(hw, &command);
1140
1141         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1142                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1143                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1144                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1145                               "Failed to write, error %x\n", error);
1146                 ret = IXGBE_ERR_PHY;
1147         }
1148
1149 out:
1150         ixgbe_release_swfw_semaphore(hw, gssr);
1151         return ret;
1152 }
1153
1154 /**
1155  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1156  *  device
1157  *  @hw: pointer to hardware structure
1158  *  @reg_addr: 32 bit PHY register to write
1159  *  @device_type: 3 bit device type
1160  *  @phy_data: Pointer to read data from the register
1161  **/
1162 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1163                            u32 device_type, u32 *data)
1164 {
1165         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1166         u32 command, error;
1167         s32 ret;
1168
1169         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1170         if (ret != IXGBE_SUCCESS)
1171                 return ret;
1172
1173         ret = ixgbe_iosf_wait(hw, NULL);
1174         if (ret != IXGBE_SUCCESS)
1175                 goto out;
1176
1177         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1178                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1179
1180         /* Write IOSF control register */
1181         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1182
1183         ret = ixgbe_iosf_wait(hw, &command);
1184
1185         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1186                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1187                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1188                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1189                                 "Failed to read, error %x\n", error);
1190                 ret = IXGBE_ERR_PHY;
1191         }
1192
1193         if (ret == IXGBE_SUCCESS)
1194                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1195
1196 out:
1197         ixgbe_release_swfw_semaphore(hw, gssr);
1198         return ret;
1199 }
1200
1201 /**
1202  * ixgbe_get_phy_token - Get the token for shared phy access
1203  * @hw: Pointer to hardware structure
1204  */
1205
1206 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1207 {
1208         struct ixgbe_hic_phy_token_req token_cmd;
1209         s32 status;
1210
1211         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1212         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1213         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1214         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1215         token_cmd.port_number = hw->bus.lan_id;
1216         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1217         token_cmd.pad = 0;
1218         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1219                                               sizeof(token_cmd),
1220                                               IXGBE_HI_COMMAND_TIMEOUT,
1221                                               true);
1222         if (status)
1223                 return status;
1224         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1225                 return IXGBE_SUCCESS;
1226         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1227                 return IXGBE_ERR_FW_RESP_INVALID;
1228
1229         return IXGBE_ERR_TOKEN_RETRY;
1230 }
1231
1232 /**
1233  * ixgbe_put_phy_token - Put the token for shared phy access
1234  * @hw: Pointer to hardware structure
1235  */
1236
1237 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1238 {
1239         struct ixgbe_hic_phy_token_req token_cmd;
1240         s32 status;
1241
1242         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1243         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1244         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1245         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1246         token_cmd.port_number = hw->bus.lan_id;
1247         token_cmd.command_type = FW_PHY_TOKEN_REL;
1248         token_cmd.pad = 0;
1249         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1250                                               sizeof(token_cmd),
1251                                               IXGBE_HI_COMMAND_TIMEOUT,
1252                                               true);
1253         if (status)
1254                 return status;
1255         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1256                 return IXGBE_SUCCESS;
1257
1258         DEBUGOUT("Put PHY Token host interface command failed");
1259         return IXGBE_ERR_FW_RESP_INVALID;
1260 }
1261
1262 /**
1263  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1264  *  of the IOSF device
1265  *  @hw: pointer to hardware structure
1266  *  @reg_addr: 32 bit PHY register to write
1267  *  @device_type: 3 bit device type
1268  *  @data: Data to write to the register
1269  **/
1270 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1271                                   u32 device_type, u32 data)
1272 {
1273         struct ixgbe_hic_internal_phy_req write_cmd;
1274         s32 status;
1275         UNREFERENCED_1PARAMETER(device_type);
1276
1277         memset(&write_cmd, 0, sizeof(write_cmd));
1278         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1279         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1280         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1281         write_cmd.port_number = hw->bus.lan_id;
1282         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1283         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1284         write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1285
1286         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1287                                               sizeof(write_cmd),
1288                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1289
1290         return status;
1291 }
1292
1293 /**
1294  *  ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
1295  *  of the IOSF device.
1296  *  @hw: pointer to hardware structure
1297  *  @reg_addr: 32 bit PHY register to write
1298  *  @device_type: 3 bit device type
1299  *  @data: Pointer to read data from the register
1300  **/
1301 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1302                                  u32 device_type, u32 *data)
1303 {
1304         union {
1305                 struct ixgbe_hic_internal_phy_req cmd;
1306                 struct ixgbe_hic_internal_phy_resp rsp;
1307         } hic;
1308         s32 status;
1309         UNREFERENCED_1PARAMETER(device_type);
1310
1311         memset(&hic, 0, sizeof(hic));
1312         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1313         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1314         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1315         hic.cmd.port_number = hw->bus.lan_id;
1316         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1317         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1318
1319         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1320                                               sizeof(hic.cmd),
1321                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1322
1323         /* Extract the register value from the response. */
1324         *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1325
1326         return status;
1327 }
1328
1329 /**
1330  *  ixgbe_disable_mdd_X550
1331  *  @hw: pointer to hardware structure
1332  *
1333  *  Disable malicious driver detection
1334  **/
1335 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1336 {
1337         u32 reg;
1338
1339         DEBUGFUNC("ixgbe_disable_mdd_X550");
1340
1341         /* Disable MDD for TX DMA and interrupt */
1342         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1343         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1344         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1345
1346         /* Disable MDD for RX and interrupt */
1347         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1348         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1349         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1350 }
1351
1352 /**
1353  *  ixgbe_enable_mdd_X550
1354  *  @hw: pointer to hardware structure
1355  *
1356  *  Enable malicious driver detection
1357  **/
1358 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1359 {
1360         u32 reg;
1361
1362         DEBUGFUNC("ixgbe_enable_mdd_X550");
1363
1364         /* Enable MDD for TX DMA and interrupt */
1365         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1366         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1367         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1368
1369         /* Enable MDD for RX and interrupt */
1370         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1371         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1372         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1373 }
1374
1375 /**
1376  *  ixgbe_restore_mdd_vf_X550
1377  *  @hw: pointer to hardware structure
1378  *  @vf: vf index
1379  *
1380  *  Restore VF that was disabled during malicious driver detection event
1381  **/
1382 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1383 {
1384         u32 idx, reg, num_qs, start_q, bitmask;
1385
1386         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1387
1388         /* Map VF to queues */
1389         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1390         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1391         case IXGBE_MRQC_VMDQRT8TCEN:
1392                 num_qs = 8;  /* 16 VFs / pools */
1393                 bitmask = 0x000000FF;
1394                 break;
1395         case IXGBE_MRQC_VMDQRSS32EN:
1396         case IXGBE_MRQC_VMDQRT4TCEN:
1397                 num_qs = 4;  /* 32 VFs / pools */
1398                 bitmask = 0x0000000F;
1399                 break;
1400         default:            /* 64 VFs / pools */
1401                 num_qs = 2;
1402                 bitmask = 0x00000003;
1403                 break;
1404         }
1405         start_q = vf * num_qs;
1406
1407         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1408         idx = start_q / 32;
1409         reg = 0;
1410         reg |= (bitmask << (start_q % 32));
1411         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1412         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1413 }
1414
1415 /**
1416  *  ixgbe_mdd_event_X550
1417  *  @hw: pointer to hardware structure
1418  *  @vf_bitmap: vf bitmap of malicious vfs
1419  *
1420  *  Handle malicious driver detection event.
1421  **/
1422 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1423 {
1424         u32 wqbr;
1425         u32 i, j, reg, q, shift, vf, idx;
1426
1427         DEBUGFUNC("ixgbe_mdd_event_X550");
1428
1429         /* figure out pool size for mapping to vf's */
1430         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1431         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1432         case IXGBE_MRQC_VMDQRT8TCEN:
1433                 shift = 3;  /* 16 VFs / pools */
1434                 break;
1435         case IXGBE_MRQC_VMDQRSS32EN:
1436         case IXGBE_MRQC_VMDQRT4TCEN:
1437                 shift = 2;  /* 32 VFs / pools */
1438                 break;
1439         default:
1440                 shift = 1;  /* 64 VFs / pools */
1441                 break;
1442         }
1443
1444         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1445         for (i = 0; i < 4; i++) {
1446                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1447                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1448
1449                 if (!wqbr)
1450                         continue;
1451
1452                 /* Get malicious queue */
1453                 for (j = 0; j < 32 && wqbr; j++) {
1454
1455                         if (!(wqbr & (1 << j)))
1456                                 continue;
1457
1458                         /* Get queue from bitmask */
1459                         q = j + (i * 32);
1460
1461                         /* Map queue to vf */
1462                         vf = (q >> shift);
1463
1464                         /* Set vf bit in vf_bitmap */
1465                         idx = vf / 32;
1466                         vf_bitmap[idx] |= (1 << (vf % 32));
1467                         wqbr &= ~(1 << j);
1468                 }
1469         }
1470 }
1471
1472 /**
1473  *  ixgbe_get_media_type_X550em - Get media type
1474  *  @hw: pointer to hardware structure
1475  *
1476  *  Returns the media type (fiber, copper, backplane)
1477  */
1478 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1479 {
1480         enum ixgbe_media_type media_type;
1481
1482         DEBUGFUNC("ixgbe_get_media_type_X550em");
1483
1484         /* Detect if there is a copper PHY attached. */
1485         switch (hw->device_id) {
1486         case IXGBE_DEV_ID_X550EM_X_KR:
1487         case IXGBE_DEV_ID_X550EM_X_KX4:
1488         case IXGBE_DEV_ID_X550EM_A_KR:
1489         case IXGBE_DEV_ID_X550EM_A_KR_L:
1490                 media_type = ixgbe_media_type_backplane;
1491                 break;
1492         case IXGBE_DEV_ID_X550EM_X_SFP:
1493         case IXGBE_DEV_ID_X550EM_A_SFP:
1494         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1495         case IXGBE_DEV_ID_X550EM_A_QSFP:
1496         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1497                 media_type = ixgbe_media_type_fiber;
1498                 break;
1499         case IXGBE_DEV_ID_X550EM_X_1G_T:
1500         case IXGBE_DEV_ID_X550EM_X_10G_T:
1501         case IXGBE_DEV_ID_X550EM_A_10G_T:
1502                 media_type = ixgbe_media_type_copper;
1503                 break;
1504         case IXGBE_DEV_ID_X550EM_A_SGMII:
1505         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1506                 media_type = ixgbe_media_type_backplane;
1507                 hw->phy.type = ixgbe_phy_sgmii;
1508                 break;
1509         case IXGBE_DEV_ID_X550EM_A_1G_T:
1510         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1511                 media_type = ixgbe_media_type_copper;
1512                 hw->phy.type = ixgbe_phy_m88;
1513                 break;
1514         default:
1515                 media_type = ixgbe_media_type_unknown;
1516                 break;
1517         }
1518         return media_type;
1519 }
1520
1521 /**
1522  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1523  *  @hw: pointer to hardware structure
1524  *  @linear: true if SFP module is linear
1525  */
1526 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1527 {
1528         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1529
1530         switch (hw->phy.sfp_type) {
1531         case ixgbe_sfp_type_not_present:
1532                 return IXGBE_ERR_SFP_NOT_PRESENT;
1533         case ixgbe_sfp_type_da_cu_core0:
1534         case ixgbe_sfp_type_da_cu_core1:
1535                 *linear = true;
1536                 break;
1537         case ixgbe_sfp_type_srlr_core0:
1538         case ixgbe_sfp_type_srlr_core1:
1539         case ixgbe_sfp_type_da_act_lmt_core0:
1540         case ixgbe_sfp_type_da_act_lmt_core1:
1541         case ixgbe_sfp_type_1g_sx_core0:
1542         case ixgbe_sfp_type_1g_sx_core1:
1543         case ixgbe_sfp_type_1g_lx_core0:
1544         case ixgbe_sfp_type_1g_lx_core1:
1545                 *linear = false;
1546                 break;
1547         case ixgbe_sfp_type_unknown:
1548         case ixgbe_sfp_type_1g_cu_core0:
1549         case ixgbe_sfp_type_1g_cu_core1:
1550         default:
1551                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1552         }
1553
1554         return IXGBE_SUCCESS;
1555 }
1556
1557 /**
1558  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1559  *  @hw: pointer to hardware structure
1560  *
1561  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1562  **/
1563 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1564 {
1565         s32 status;
1566         bool linear;
1567
1568         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1569
1570         status = ixgbe_identify_module_generic(hw);
1571
1572         if (status != IXGBE_SUCCESS)
1573                 return status;
1574
1575         /* Check if SFP module is supported */
1576         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1577
1578         return status;
1579 }
1580
1581 /**
1582  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1583  *  @hw: pointer to hardware structure
1584  */
1585 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1586 {
1587         s32 status;
1588         bool linear;
1589
1590         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1591
1592         /* Check if SFP module is supported */
1593         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1594
1595         if (status != IXGBE_SUCCESS)
1596                 return status;
1597
1598         ixgbe_init_mac_link_ops_X550em(hw);
1599         hw->phy.ops.reset = NULL;
1600
1601         return IXGBE_SUCCESS;
1602 }
1603
1604 /**
1605  * ixgbe_setup_sgmii - Set up link for sgmii
1606  * @hw: pointer to hardware structure
1607  */
1608 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1609                              bool autoneg_wait_to_complete)
1610 {
1611         struct ixgbe_mac_info *mac = &hw->mac;
1612         u32 lval, sval;
1613         s32 rc;
1614         UNREFERENCED_2PARAMETER(speed, autoneg_wait_to_complete);
1615
1616         rc = mac->ops.read_iosf_sb_reg(hw,
1617                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1618                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1619         if (rc)
1620                 return rc;
1621
1622         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1623         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1624         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1625         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1626         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1627         rc = mac->ops.write_iosf_sb_reg(hw,
1628                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1629                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1630         if (rc)
1631                 return rc;
1632
1633         rc = mac->ops.read_iosf_sb_reg(hw,
1634                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1635                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1636         if (rc)
1637                 return rc;
1638
1639         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1640         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1641         rc = mac->ops.write_iosf_sb_reg(hw,
1642                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1643                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1644         if (rc)
1645                 return rc;
1646
1647         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1648         rc = mac->ops.write_iosf_sb_reg(hw,
1649                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1650                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1651
1652         return rc;
1653 }
1654
1655 /**
1656  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1657  *  @hw: pointer to hardware structure
1658  */
1659 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1660 {
1661         struct ixgbe_mac_info *mac = &hw->mac;
1662
1663         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1664
1665         switch (hw->mac.ops.get_media_type(hw)) {
1666         case ixgbe_media_type_fiber:
1667                 /* CS4227 does not support autoneg, so disable the laser control
1668                  * functions for SFP+ fiber
1669                  */
1670                 mac->ops.disable_tx_laser = NULL;
1671                 mac->ops.enable_tx_laser = NULL;
1672                 mac->ops.flap_tx_laser = NULL;
1673                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1674                 mac->ops.set_rate_select_speed =
1675                                         ixgbe_set_soft_rate_select_speed;
1676                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1677                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1678                         mac->ops.setup_mac_link =
1679                                 ixgbe_setup_mac_link_sfp_x550a;
1680                 else
1681                         mac->ops.setup_mac_link =
1682                                 ixgbe_setup_mac_link_sfp_x550em;
1683                 break;
1684         case ixgbe_media_type_copper:
1685                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1686                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1687                 break;
1688         case ixgbe_media_type_backplane:
1689                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1690                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1691                         mac->ops.setup_link = ixgbe_setup_sgmii;
1692                 break;
1693         default:
1694                 break;
1695         }
1696 }
1697
1698 /**
1699  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1700  *  @hw: pointer to hardware structure
1701  *  @speed: pointer to link speed
1702  *  @autoneg: true when autoneg or autotry is enabled
1703  */
1704 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1705                                        ixgbe_link_speed *speed,
1706                                        bool *autoneg)
1707 {
1708         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1709
1710         /* SFP */
1711         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1712
1713                 /* CS4227 SFP must not enable auto-negotiation */
1714                 *autoneg = false;
1715
1716                 /* Check if 1G SFP module. */
1717                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1718                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1719                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1720                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1721                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1722                         return IXGBE_SUCCESS;
1723                 }
1724
1725                 /* Link capabilities are based on SFP */
1726                 if (hw->phy.multispeed_fiber)
1727                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1728                                  IXGBE_LINK_SPEED_1GB_FULL;
1729                 else
1730                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1731         } else {
1732                 switch (hw->phy.type) {
1733                 case ixgbe_phy_m88:
1734                         *speed = IXGBE_LINK_SPEED_100_FULL |
1735                                  IXGBE_LINK_SPEED_1GB_FULL;
1736                         break;
1737                 case ixgbe_phy_sgmii:
1738                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1739                         break;
1740                 default:
1741                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1742                                  IXGBE_LINK_SPEED_1GB_FULL;
1743                         break;
1744                 }
1745                 *autoneg = true;
1746         }
1747
1748         return IXGBE_SUCCESS;
1749 }
1750
1751 /**
1752  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1753  * @hw: pointer to hardware structure
1754  * @lsc: pointer to boolean flag which indicates whether external Base T
1755  *       PHY interrupt is lsc
1756  *
1757  * Determime if external Base T PHY interrupt cause is high temperature
1758  * failure alarm or link status change.
1759  *
1760  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1761  * failure alarm, else return PHY access status.
1762  */
1763 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1764 {
1765         u32 status;
1766         u16 reg;
1767
1768         *lsc = false;
1769
1770         /* Vendor alarm triggered */
1771         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1772                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1773                                       &reg);
1774
1775         if (status != IXGBE_SUCCESS ||
1776             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1777                 return status;
1778
1779         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1780         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1781                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1782                                       &reg);
1783
1784         if (status != IXGBE_SUCCESS ||
1785             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1786             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1787                 return status;
1788
1789         /* Global alarm triggered */
1790         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1791                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1792                                       &reg);
1793
1794         if (status != IXGBE_SUCCESS)
1795                 return status;
1796
1797         /* If high temperature failure, then return over temp error and exit */
1798         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1799                 /* power down the PHY in case the PHY FW didn't already */
1800                 ixgbe_set_copper_phy_power(hw, false);
1801                 return IXGBE_ERR_OVERTEMP;
1802         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1803                 /*  device fault alarm triggered */
1804                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1805                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1806                                           &reg);
1807
1808                 if (status != IXGBE_SUCCESS)
1809                         return status;
1810
1811                 /* if device fault was due to high temp alarm handle and exit */
1812                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1813                         /* power down the PHY in case the PHY FW didn't */
1814                         ixgbe_set_copper_phy_power(hw, false);
1815                         return IXGBE_ERR_OVERTEMP;
1816                 }
1817         }
1818
1819         /* Vendor alarm 2 triggered */
1820         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1821                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1822
1823         if (status != IXGBE_SUCCESS ||
1824             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1825                 return status;
1826
1827         /* link connect/disconnect event occurred */
1828         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1829                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1830
1831         if (status != IXGBE_SUCCESS)
1832                 return status;
1833
1834         /* Indicate LSC */
1835         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1836                 *lsc = true;
1837
1838         return IXGBE_SUCCESS;
1839 }
1840
1841 /**
1842  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1843  * @hw: pointer to hardware structure
1844  *
1845  * Enable link status change and temperature failure alarm for the external
1846  * Base T PHY
1847  *
1848  * Returns PHY access status
1849  */
1850 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1851 {
1852         u32 status;
1853         u16 reg;
1854         bool lsc;
1855
1856         /* Clear interrupt flags */
1857         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1858
1859         /* Enable link status change alarm */
1860         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1861                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1862
1863         if (status != IXGBE_SUCCESS)
1864                 return status;
1865
1866         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1867
1868         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1869                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1870
1871         if (status != IXGBE_SUCCESS)
1872                 return status;
1873
1874         /* Enable high temperature failure and global fault alarms */
1875         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1876                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1877                                       &reg);
1878
1879         if (status != IXGBE_SUCCESS)
1880                 return status;
1881
1882         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1883                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1884
1885         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1886                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1887                                        reg);
1888
1889         if (status != IXGBE_SUCCESS)
1890                 return status;
1891
1892         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1893         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1894                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1895                                       &reg);
1896
1897         if (status != IXGBE_SUCCESS)
1898                 return status;
1899
1900         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1901                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1902
1903         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1904                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1905                                        reg);
1906
1907         if (status != IXGBE_SUCCESS)
1908                 return status;
1909
1910         /* Enable chip-wide vendor alarm */
1911         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1912                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1913                                       &reg);
1914
1915         if (status != IXGBE_SUCCESS)
1916                 return status;
1917
1918         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1919
1920         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1921                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1922                                        reg);
1923
1924         return status;
1925 }
1926
1927 /**
1928  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1929  *  @hw: pointer to hardware structure
1930  *  @speed: link speed
1931  *
1932  *  Configures the integrated KR PHY.
1933  **/
1934 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1935                                        ixgbe_link_speed speed)
1936 {
1937         s32 status;
1938         u32 reg_val;
1939
1940         status = hw->mac.ops.read_iosf_sb_reg(hw,
1941                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1942                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1943         if (status)
1944                 return status;
1945
1946         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1947         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1948                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1949
1950         /* Advertise 10G support. */
1951         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1952                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1953
1954         /* Advertise 1G support. */
1955         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1956                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1957
1958         /* Restart auto-negotiation. */
1959         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1960         status = hw->mac.ops.write_iosf_sb_reg(hw,
1961                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1962                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1963
1964         return status;
1965 }
1966
1967 /**
1968  * ixgbe_set_master_slave_mode - Set up PHY for master/slave mode
1969  * @hw: pointer to hardware structure
1970  *
1971  * Must be called while holding the PHY semaphore and token
1972  */
1973 STATIC s32 ixgbe_set_master_slave_mode(struct ixgbe_hw *hw)
1974 {
1975         u16 phy_data;
1976         s32 rc;
1977
1978         /* Resolve master/slave mode */
1979         rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_M88E1500_1000T_CTRL, 0,
1980                                        &phy_data);
1981         if (rc)
1982                 return rc;
1983
1984         /* load defaults for future use */
1985         if (phy_data & IXGBE_M88E1500_1000T_CTRL_MS_ENABLE) {
1986                 if (phy_data & IXGBE_M88E1500_1000T_CTRL_MS_VALUE)
1987                         hw->phy.original_ms_type = ixgbe_ms_force_master;
1988                 else
1989                         hw->phy.original_ms_type = ixgbe_ms_force_slave;
1990         } else {
1991                 hw->phy.original_ms_type = ixgbe_ms_auto;
1992         }
1993
1994         switch (hw->phy.ms_type) {
1995         case ixgbe_ms_force_master:
1996                 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
1997                 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_VALUE;
1998                 break;
1999         case ixgbe_ms_force_slave:
2000                 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
2001                 phy_data &= ~IXGBE_M88E1500_1000T_CTRL_MS_VALUE;
2002                 break;
2003         case ixgbe_ms_auto:
2004                 phy_data &= ~IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
2005                 break;
2006         default:
2007                 break;
2008         }
2009
2010         return ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_1000T_CTRL, 0,
2011                                           phy_data);
2012 }
2013
2014 /**
2015  * ixgbe_reset_phy_m88_nolock - Reset m88 PHY without locking
2016  * @hw: pointer to hardware structure
2017  *
2018  * Must be called while holding the PHY semaphore and token
2019  */
2020 STATIC s32 ixgbe_reset_phy_m88_nolock(struct ixgbe_hw *hw)
2021 {
2022         s32 rc;
2023
2024         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2025         if (rc)
2026                 return rc;
2027
2028         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_FIBER_CTRL, 0,
2029                                         IXGBE_M88E1500_FIBER_CTRL_RESET |
2030                                         IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2031                                         IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB);
2032         if (rc)
2033                 goto res_out;
2034
2035         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2036         if (rc)
2037                 goto res_out;
2038
2039         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_GEN_CTRL, 0,
2040                                         IXGBE_M88E1500_GEN_CTRL_RESET |
2041                                         IXGBE_M88E1500_GEN_CTRL_SGMII_COPPER);
2042         if (rc)
2043                 goto res_out;
2044
2045         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2046         if (rc)
2047                 goto res_out;
2048
2049         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2050                                         IXGBE_M88E1500_COPPER_CTRL_RESET |
2051                                         IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2052                                         IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2053                                         IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2054                                         IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB);
2055
2056 res_out:
2057         ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2058         return rc;
2059 }
2060
2061 /**
2062  * ixgbe_reset_phy_m88 - Reset m88 PHY
2063  * @hw: pointer to hardware structure
2064  */
2065 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2066 {
2067         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2068         s32 rc;
2069
2070         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2071                 return IXGBE_SUCCESS;
2072
2073         rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2074         if (rc)
2075                 return rc;
2076
2077         rc = ixgbe_reset_phy_m88_nolock(hw);
2078
2079         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2080         return rc;
2081 }
2082
2083 /**
2084  * ixgbe_setup_m88 - setup m88 PHY
2085  * @hw: pointer to hardware structure
2086  */
2087 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2088 {
2089         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2090         struct ixgbe_phy_info *phy = &hw->phy;
2091         u16 phy_data;
2092         s32 rc;
2093
2094         if (phy->reset_disable || ixgbe_check_reset_blocked(hw))
2095                 return IXGBE_SUCCESS;
2096
2097         rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2098         if (rc)
2099                 return rc;
2100
2101         rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_M88E1500_PHY_SPEC_CTRL, 0,
2102                                        &phy_data);
2103         if (rc)
2104                 goto rel_out;
2105
2106         /* Enable downshift and setting it to X6 */
2107         phy_data &= ~IXGBE_M88E1500_PSCR_DOWNSHIFT_ENABLE;
2108         phy_data |= IXGBE_M88E1500_PSCR_DOWNSHIFT_6X;
2109         phy_data |= IXGBE_M88E1500_PSCR_DOWNSHIFT_ENABLE;
2110         rc = ixgbe_write_phy_reg_mdi_22(hw,
2111                                         IXGBE_M88E1500_PHY_SPEC_CTRL, 0,
2112                                         phy_data);
2113         if (rc)
2114                 goto rel_out;
2115
2116         ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2117
2118         /* Commit the changes */
2119         rc = ixgbe_reset_phy_m88_nolock(hw);
2120         if (rc) {
2121                 DEBUGOUT("Error committing the PHY changes\n");
2122                 goto rel_out;
2123         }
2124
2125         rc = ixgbe_set_master_slave_mode(hw);
2126
2127         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2128         return rc;
2129
2130 rel_out:
2131         ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2132         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2133         return rc;
2134 }
2135
2136 /**
2137  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2138  *  @hw: pointer to hardware structure
2139  *
2140  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2141  *  values.
2142  **/
2143 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2144 {
2145         /* Save NW management interface connected on board. This is used
2146          * to determine internal PHY mode.
2147          */
2148         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2149
2150         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2151          * PHY address. This register field was has only been used for X552.
2152          */
2153         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2154             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2155                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2156                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2157                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2158         }
2159
2160         return IXGBE_SUCCESS;
2161 }
2162
2163 /**
2164  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2165  *  @hw: pointer to hardware structure
2166  *
2167  *  Initialize any function pointers that were not able to be
2168  *  set during init_shared_code because the PHY/SFP type was
2169  *  not known.  Perform the SFP init if necessary.
2170  */
2171 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2172 {
2173         struct ixgbe_phy_info *phy = &hw->phy;
2174         s32 ret_val;
2175
2176         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2177
2178         hw->mac.ops.set_lan_id(hw);
2179
2180         ixgbe_read_mng_if_sel_x550em(hw);
2181
2182         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2183                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2184                 ixgbe_setup_mux_ctl(hw);
2185                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2186         }
2187
2188         /* Identify the PHY or SFP module */
2189         ret_val = phy->ops.identify(hw);
2190         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2191                 return ret_val;
2192
2193         /* Setup function pointers based on detected hardware */
2194         ixgbe_init_mac_link_ops_X550em(hw);
2195         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2196                 phy->ops.reset = NULL;
2197
2198         /* Set functions pointers based on phy type */
2199         switch (hw->phy.type) {
2200         case ixgbe_phy_x550em_kx4:
2201                 phy->ops.setup_link = NULL;
2202                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2203                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2204                 break;
2205         case ixgbe_phy_x550em_kr:
2206                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2207                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2208                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2209                 break;
2210         case ixgbe_phy_x550em_ext_t:
2211                 /* If internal link mode is XFI, then setup iXFI internal link,
2212                  * else setup KR now.
2213                  */
2214                 phy->ops.setup_internal_link =
2215                                               ixgbe_setup_internal_phy_t_x550em;
2216
2217                 /* setup SW LPLU only for first revision of X550EM_x */
2218                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2219                     !(IXGBE_FUSES0_REV_MASK &
2220                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2221                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2222
2223                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2224                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2225                 break;
2226         case ixgbe_phy_sgmii:
2227                 phy->ops.setup_link = NULL;
2228                 break;
2229         case ixgbe_phy_m88:
2230                 phy->ops.setup_link = ixgbe_setup_m88;
2231                 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2232                 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2233                 phy->ops.reset = ixgbe_reset_phy_m88;
2234                 break;
2235         default:
2236                 break;
2237         }
2238         return ret_val;
2239 }
2240
2241 /**
2242  * ixgbe_set_mdio_speed - Set MDIO clock speed
2243  *  @hw: pointer to hardware structure
2244  */
2245 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2246 {
2247         u32 hlreg0;
2248
2249         switch (hw->device_id) {
2250         case IXGBE_DEV_ID_X550EM_X_10G_T:
2251         case IXGBE_DEV_ID_X550EM_A_SGMII:
2252         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2253         case IXGBE_DEV_ID_X550EM_A_1G_T:
2254         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2255         case IXGBE_DEV_ID_X550EM_A_10G_T:
2256         case IXGBE_DEV_ID_X550EM_A_SFP:
2257         case IXGBE_DEV_ID_X550EM_A_QSFP:
2258                 /* Config MDIO clock speed before the first MDIO PHY access */
2259                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2260                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2261                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2262                 break;
2263         default:
2264                 break;
2265         }
2266 }
2267
2268 /**
2269  *  ixgbe_reset_hw_X550em - Perform hardware reset
2270  *  @hw: pointer to hardware structure
2271  *
2272  *  Resets the hardware by resetting the transmit and receive units, masks
2273  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2274  *  reset.
2275  */
2276 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2277 {
2278         ixgbe_link_speed link_speed;
2279         s32 status;
2280         u32 ctrl = 0;
2281         u32 i;
2282         bool link_up = false;
2283
2284         DEBUGFUNC("ixgbe_reset_hw_X550em");
2285
2286         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2287         status = hw->mac.ops.stop_adapter(hw);
2288         if (status != IXGBE_SUCCESS)
2289                 return status;
2290
2291         /* flush pending Tx transactions */
2292         ixgbe_clear_tx_pending(hw);
2293
2294         ixgbe_set_mdio_speed(hw);
2295
2296         /* PHY ops must be identified and initialized prior to reset */
2297         status = hw->phy.ops.init(hw);
2298
2299         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2300                 return status;
2301
2302         /* start the external PHY */
2303         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2304                 status = ixgbe_init_ext_t_x550em(hw);
2305                 if (status)
2306                         return status;
2307         }
2308
2309         /* Setup SFP module if there is one present. */
2310         if (hw->phy.sfp_setup_needed) {
2311                 status = hw->mac.ops.setup_sfp(hw);
2312                 hw->phy.sfp_setup_needed = false;
2313         }
2314
2315         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2316                 return status;
2317
2318         /* Reset PHY */
2319         if (!hw->phy.reset_disable && hw->phy.ops.reset)
2320                 hw->phy.ops.reset(hw);
2321
2322 mac_reset_top:
2323         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2324          * If link reset is used when link is up, it might reset the PHY when
2325          * mng is using it.  If link is down or the flag to force full link
2326          * reset is set, then perform link reset.
2327          */
2328         ctrl = IXGBE_CTRL_LNK_RST;
2329         if (!hw->force_full_reset) {
2330                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2331                 if (link_up)
2332                         ctrl = IXGBE_CTRL_RST;
2333         }
2334
2335         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2336         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2337         IXGBE_WRITE_FLUSH(hw);
2338
2339         /* Poll for reset bit to self-clear meaning reset is complete */
2340         for (i = 0; i < 10; i++) {
2341                 usec_delay(1);
2342                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2343                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2344                         break;
2345         }
2346
2347         if (ctrl & IXGBE_CTRL_RST_MASK) {
2348                 status = IXGBE_ERR_RESET_FAILED;
2349                 DEBUGOUT("Reset polling failed to complete.\n");
2350         }
2351
2352         msec_delay(50);
2353
2354         /* Double resets are required for recovery from certain error
2355          * conditions.  Between resets, it is necessary to stall to
2356          * allow time for any pending HW events to complete.
2357          */
2358         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2359                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2360                 goto mac_reset_top;
2361         }
2362
2363         /* Store the permanent mac address */
2364         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2365
2366         /* Store MAC address from RAR0, clear receive address registers, and
2367          * clear the multicast table.  Also reset num_rar_entries to 128,
2368          * since we modify this value when programming the SAN MAC address.
2369          */
2370         hw->mac.num_rar_entries = 128;
2371         hw->mac.ops.init_rx_addrs(hw);
2372
2373         ixgbe_set_mdio_speed(hw);
2374
2375         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2376                 ixgbe_setup_mux_ctl(hw);
2377
2378         return status;
2379 }
2380
2381 /**
2382  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2383  * @hw: pointer to hardware structure
2384  */
2385 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2386 {
2387         u32 status;
2388         u16 reg;
2389
2390         status = hw->phy.ops.read_reg(hw,
2391                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2392                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2393                                       &reg);
2394
2395         if (status != IXGBE_SUCCESS)
2396                 return status;
2397
2398         /* If PHY FW reset completed bit is set then this is the first
2399          * SW instance after a power on so the PHY FW must be un-stalled.
2400          */
2401         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2402                 status = hw->phy.ops.read_reg(hw,
2403                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2404                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2405                                         &reg);
2406
2407                 if (status != IXGBE_SUCCESS)
2408                         return status;
2409
2410                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2411
2412                 status = hw->phy.ops.write_reg(hw,
2413                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2414                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2415                                         reg);
2416
2417                 if (status != IXGBE_SUCCESS)
2418                         return status;
2419         }
2420
2421         return status;
2422 }
2423
2424 /**
2425  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2426  *  @hw: pointer to hardware structure
2427  *
2428  *  Configures the integrated KR PHY for X550EM_x.
2429  **/
2430 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2431 {
2432         if (hw->mac.type != ixgbe_mac_X550EM_x)
2433                 return IXGBE_SUCCESS;
2434
2435         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2436 }
2437
2438 /**
2439  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2440  *  @hw: pointer to hardware structure
2441  *
2442  *  Configure the external PHY and the integrated KR PHY for SFP support.
2443  **/
2444 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2445                                     ixgbe_link_speed speed,
2446                                     bool autoneg_wait_to_complete)
2447 {
2448         s32 ret_val;
2449         u16 reg_slice, reg_val;
2450         bool setup_linear = false;
2451         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2452
2453         /* Check if SFP module is supported and linear */
2454         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2455
2456         /* If no SFP module present, then return success. Return success since
2457          * there is no reason to configure CS4227 and SFP not present error is
2458          * not excepted in the setup MAC link flow.
2459          */
2460         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2461                 return IXGBE_SUCCESS;
2462
2463         if (ret_val != IXGBE_SUCCESS)
2464                 return ret_val;
2465
2466         /* Configure internal PHY for KR/KX. */
2467         ixgbe_setup_kr_speed_x550em(hw, speed);
2468
2469         /* Configure CS4227 LINE side to proper mode. */
2470         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2471                     (hw->bus.lan_id << 12);
2472         if (setup_linear)
2473                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2474         else
2475                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2476         ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2477                                           reg_val);
2478         return ret_val;
2479 }
2480
2481 /**
2482  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2483  *  @hw: pointer to hardware structure
2484  *
2485  *  Configure the the integrated PHY for SFP support.
2486  **/
2487 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2488                                    ixgbe_link_speed speed,
2489                                    bool autoneg_wait_to_complete)
2490 {
2491         s32 ret_val;
2492         u16 reg_phy_ext;
2493         bool setup_linear = false;
2494         u32 reg_slice, reg_phy_int, slice_offset;
2495
2496         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2497
2498         /* Check if SFP module is supported and linear */
2499         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2500
2501         /* If no SFP module present, then return success. Return success since
2502          * SFP not present error is not excepted in the setup MAC link flow.
2503          */
2504         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2505                 return IXGBE_SUCCESS;
2506
2507         if (ret_val != IXGBE_SUCCESS)
2508                 return ret_val;
2509
2510         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2511                 /* Configure internal PHY for native SFI */
2512                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2513                                IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2514                                IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2515
2516                 if (ret_val != IXGBE_SUCCESS)
2517                         return ret_val;
2518
2519                 if (setup_linear) {
2520                         reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2521                         reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2522                 } else {
2523                         reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2524                         reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2525                 }
2526
2527                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2528                                 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2529                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2530
2531                 if (ret_val != IXGBE_SUCCESS)
2532                         return ret_val;
2533
2534                 /* Setup XFI/SFI internal link. */
2535                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2536         } else {
2537                 /* Configure internal PHY for KR/KX. */
2538                 ixgbe_setup_kr_speed_x550em(hw, speed);
2539
2540                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2541                         /* Find Address */
2542                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2543                         return IXGBE_ERR_PHY_ADDR_INVALID;
2544                 }
2545
2546                 /* Get external PHY device id */
2547                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2548                                        IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2549
2550                 if (ret_val != IXGBE_SUCCESS)
2551                         return ret_val;
2552
2553                 /* When configuring quad port CS4223, the MAC instance is part
2554                  * of the slice offset.
2555                  */
2556                 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2557                         slice_offset = (hw->bus.lan_id +
2558                                         (hw->bus.instance_id << 1)) << 12;
2559                 else
2560                         slice_offset = hw->bus.lan_id << 12;
2561
2562                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2563                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2564                 if (setup_linear)
2565                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2566                 else
2567                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2568                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2569                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2570         }
2571         return ret_val;
2572 }
2573
2574 /**
2575  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2576  *  @hw: pointer to hardware structure
2577  *
2578  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2579  **/
2580 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2581 {
2582         s32 status;
2583         u32 reg_val;
2584
2585         /* Disable training protocol FSM. */
2586         status = ixgbe_read_iosf_sb_reg_x550(hw,
2587                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2588                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2589         if (status != IXGBE_SUCCESS)
2590                 return status;
2591         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2592         status = ixgbe_write_iosf_sb_reg_x550(hw,
2593                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2594                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2595         if (status != IXGBE_SUCCESS)
2596                 return status;
2597
2598         /* Disable Flex from training TXFFE. */
2599         status = ixgbe_read_iosf_sb_reg_x550(hw,
2600                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2601                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2602         if (status != IXGBE_SUCCESS)
2603                 return status;
2604         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2605         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2606         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2607         status = ixgbe_write_iosf_sb_reg_x550(hw,
2608                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2609                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2610         if (status != IXGBE_SUCCESS)
2611                 return status;
2612         status = ixgbe_read_iosf_sb_reg_x550(hw,
2613                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2614                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2615         if (status != IXGBE_SUCCESS)
2616                 return status;
2617         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2618         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2619         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2620         status = ixgbe_write_iosf_sb_reg_x550(hw,
2621                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2622                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2623         if (status != IXGBE_SUCCESS)
2624                 return status;
2625
2626         /* Enable override for coefficients. */
2627         status = ixgbe_read_iosf_sb_reg_x550(hw,
2628                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2629                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2630         if (status != IXGBE_SUCCESS)
2631                 return status;
2632         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2633         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2634         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2635         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2636         status = ixgbe_write_iosf_sb_reg_x550(hw,
2637                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2638                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2639         return status;
2640 }
2641
2642 /**
2643  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2644  *  @hw: pointer to hardware structure
2645  *  @speed: the link speed to force
2646  *
2647  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2648  *  internal and external PHY at a specific speed, without autonegotiation.
2649  **/
2650 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2651 {
2652         s32 status;
2653         u32 reg_val;
2654
2655         /* Disable AN and force speed to 10G Serial. */
2656         status = ixgbe_read_iosf_sb_reg_x550(hw,
2657                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2658                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2659         if (status != IXGBE_SUCCESS)
2660                 return status;
2661
2662         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2663         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2664
2665         /* Select forced link speed for internal PHY. */
2666         switch (*speed) {
2667         case IXGBE_LINK_SPEED_10GB_FULL:
2668                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2669                 break;
2670         case IXGBE_LINK_SPEED_1GB_FULL:
2671                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2672                 break;
2673         default:
2674                 /* Other link speeds are not supported by internal KR PHY. */
2675                 return IXGBE_ERR_LINK_SETUP;
2676         }
2677
2678         status = ixgbe_write_iosf_sb_reg_x550(hw,
2679                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2680                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2681         if (status != IXGBE_SUCCESS)
2682                 return status;
2683
2684         /* Additional configuration needed for x550em_x */
2685         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2686                 status = ixgbe_setup_ixfi_x550em_x(hw);
2687                 if (status != IXGBE_SUCCESS)
2688                         return status;
2689         }
2690
2691         /* Toggle port SW reset by AN reset. */
2692         status = ixgbe_read_iosf_sb_reg_x550(hw,
2693                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2694                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2695         if (status != IXGBE_SUCCESS)
2696                 return status;
2697         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2698         status = ixgbe_write_iosf_sb_reg_x550(hw,
2699                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2700                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2701
2702         return status;
2703 }
2704
2705 /**
2706  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2707  * @hw: address of hardware structure
2708  * @link_up: address of boolean to indicate link status
2709  *
2710  * Returns error code if unable to get link status.
2711  */
2712 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2713 {
2714         u32 ret;
2715         u16 autoneg_status;
2716
2717         *link_up = false;
2718
2719         /* read this twice back to back to indicate current status */
2720         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2721                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2722                                    &autoneg_status);
2723         if (ret != IXGBE_SUCCESS)
2724                 return ret;
2725
2726         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2727                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2728                                    &autoneg_status);
2729         if (ret != IXGBE_SUCCESS)
2730                 return ret;
2731
2732         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2733
2734         return IXGBE_SUCCESS;
2735 }
2736
2737 /**
2738  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2739  * @hw: point to hardware structure
2740  *
2741  * Configures the link between the integrated KR PHY and the external X557 PHY
2742  * The driver will call this function when it gets a link status change
2743  * interrupt from the X557 PHY. This function configures the link speed
2744  * between the PHYs to match the link speed of the BASE-T link.
2745  *
2746  * A return of a non-zero value indicates an error, and the base driver should
2747  * not report link up.
2748  */
2749 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2750 {
2751         ixgbe_link_speed force_speed;
2752         bool link_up;
2753         u32 status;
2754         u16 speed;
2755
2756         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2757                 return IXGBE_ERR_CONFIG;
2758
2759         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2760                 /* If link is down, there is no setup necessary so return  */
2761                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2762                 if (status != IXGBE_SUCCESS)
2763                         return status;
2764
2765                 if (!link_up)
2766                         return IXGBE_SUCCESS;
2767
2768                 status = hw->phy.ops.read_reg(hw,
2769                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2770                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2771                                               &speed);
2772                 if (status != IXGBE_SUCCESS)
2773                         return status;
2774
2775                 /* If link is still down - no setup is required so return */
2776                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2777                 if (status != IXGBE_SUCCESS)
2778                         return status;
2779                 if (!link_up)
2780                         return IXGBE_SUCCESS;
2781
2782                 /* clear everything but the speed and duplex bits */
2783                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2784
2785                 switch (speed) {
2786                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2787                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2788                         break;
2789                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2790                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2791                         break;
2792                 default:
2793                         /* Internal PHY does not support anything else */
2794                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
2795                 }
2796
2797                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2798         } else {
2799                 speed = IXGBE_LINK_SPEED_10GB_FULL |
2800                         IXGBE_LINK_SPEED_1GB_FULL;
2801                 return ixgbe_setup_kr_speed_x550em(hw, speed);
2802         }
2803 }
2804
2805 /**
2806  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2807  *  @hw: pointer to hardware structure
2808  *
2809  *  Configures the integrated KR PHY to use internal loopback mode.
2810  **/
2811 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2812 {
2813         s32 status;
2814         u32 reg_val;
2815
2816         /* Disable AN and force speed to 10G Serial. */
2817         status = hw->mac.ops.read_iosf_sb_reg(hw,
2818                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2819                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2820         if (status != IXGBE_SUCCESS)
2821                 return status;
2822         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2823         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2824         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2825         status = hw->mac.ops.write_iosf_sb_reg(hw,
2826                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2827                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2828         if (status != IXGBE_SUCCESS)
2829                 return status;
2830
2831         /* Set near-end loopback clocks. */
2832         status = hw->mac.ops.read_iosf_sb_reg(hw,
2833                       IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2834                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2835         if (status != IXGBE_SUCCESS)
2836                 return status;
2837         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2838         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2839         status = hw->mac.ops.write_iosf_sb_reg(hw,
2840                        IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2841                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2842         if (status != IXGBE_SUCCESS)
2843                 return status;
2844
2845         /* Set loopback enable. */
2846         status = hw->mac.ops.read_iosf_sb_reg(hw,
2847                       IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2848                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2849         if (status != IXGBE_SUCCESS)
2850                 return status;
2851         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2852         status = hw->mac.ops.write_iosf_sb_reg(hw,
2853                        IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2854                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2855         if (status != IXGBE_SUCCESS)
2856                 return status;
2857
2858         /* Training bypass. */
2859         status = hw->mac.ops.read_iosf_sb_reg(hw,
2860                       IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2861                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2862         if (status != IXGBE_SUCCESS)
2863                 return status;
2864         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2865         status = hw->mac.ops.write_iosf_sb_reg(hw,
2866                        IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2867                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2868
2869         return status;
2870 }
2871
2872 /**
2873  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2874  *  assuming that the semaphore is already obtained.
2875  *  @hw: pointer to hardware structure
2876  *  @offset: offset of  word in the EEPROM to read
2877  *  @data: word read from the EEPROM
2878  *
2879  *  Reads a 16 bit word from the EEPROM using the hostif.
2880  **/
2881 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2882                                    u16 *data)
2883 {
2884         s32 status;
2885         struct ixgbe_hic_read_shadow_ram buffer;
2886
2887         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2888         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2889         buffer.hdr.req.buf_lenh = 0;
2890         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2891         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2892
2893         /* convert offset from words to bytes */
2894         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2895         /* one word */
2896         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2897
2898         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2899                                               sizeof(buffer),
2900                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2901
2902         if (status)
2903                 return status;
2904
2905         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2906                                           FW_NVM_DATA_OFFSET);
2907
2908         return 0;
2909 }
2910
2911 /**
2912  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2913  *  @hw: pointer to hardware structure
2914  *  @offset: offset of  word in the EEPROM to read
2915  *  @data: word read from the EEPROM
2916  *
2917  *  Reads a 16 bit word from the EEPROM using the hostif.
2918  **/
2919 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2920                               u16 *data)
2921 {
2922         s32 status = IXGBE_SUCCESS;
2923
2924         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2925
2926         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2927             IXGBE_SUCCESS) {
2928                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2929                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2930         } else {
2931                 status = IXGBE_ERR_SWFW_SYNC;
2932         }
2933
2934         return status;
2935 }
2936
2937 /**
2938  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2939  *  @hw: pointer to hardware structure
2940  *  @offset: offset of  word in the EEPROM to read
2941  *  @words: number of words
2942  *  @data: word(s) read from the EEPROM
2943  *
2944  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
2945  **/
2946 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2947                                      u16 offset, u16 words, u16 *data)
2948 {
2949         struct ixgbe_hic_read_shadow_ram buffer;
2950         u32 current_word = 0;
2951         u16 words_to_read;
2952         s32 status;
2953         u32 i;
2954
2955         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2956
2957         /* Take semaphore for the entire operation. */
2958         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2959         if (status) {
2960                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2961                 return status;
2962         }
2963         while (words) {
2964                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2965                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2966                 else
2967                         words_to_read = words;
2968
2969                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2970                 buffer.hdr.req.buf_lenh = 0;
2971                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2972                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2973
2974                 /* convert offset from words to bytes */
2975                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2976                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2977
2978                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2979                                                       sizeof(buffer),
2980                                                       IXGBE_HI_COMMAND_TIMEOUT,
2981                                                       false);
2982
2983                 if (status) {
2984                         DEBUGOUT("Host interface command failed\n");
2985                         goto out;
2986                 }
2987
2988                 for (i = 0; i < words_to_read; i++) {
2989                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2990                                   2 * i;
2991                         u32 value = IXGBE_READ_REG(hw, reg);
2992
2993                         data[current_word] = (u16)(value & 0xffff);
2994                         current_word++;
2995                         i++;
2996                         if (i < words_to_read) {
2997                                 value >>= 16;
2998                                 data[current_word] = (u16)(value & 0xffff);
2999                                 current_word++;
3000                         }
3001                 }
3002                 words -= words_to_read;
3003         }
3004
3005 out:
3006         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3007         return status;
3008 }
3009
3010 /**
3011  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3012  *  @hw: pointer to hardware structure
3013  *  @offset: offset of  word in the EEPROM to write
3014  *  @data: word write to the EEPROM
3015  *
3016  *  Write a 16 bit word to the EEPROM using the hostif.
3017  **/
3018 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3019                                     u16 data)
3020 {
3021         s32 status;
3022         struct ixgbe_hic_write_shadow_ram buffer;
3023
3024         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3025
3026         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3027         buffer.hdr.req.buf_lenh = 0;
3028         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3029         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3030
3031          /* one word */
3032         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3033         buffer.data = data;
3034         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3035
3036         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3037                                               sizeof(buffer),
3038                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3039
3040         return status;
3041 }
3042
3043 /**
3044  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3045  *  @hw: pointer to hardware structure
3046  *  @offset: offset of  word in the EEPROM to write
3047  *  @data: word write to the EEPROM
3048  *
3049  *  Write a 16 bit word to the EEPROM using the hostif.
3050  **/
3051 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3052                                u16 data)
3053 {
3054         s32 status = IXGBE_SUCCESS;
3055
3056         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3057
3058         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3059             IXGBE_SUCCESS) {
3060                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3061                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3062         } else {
3063                 DEBUGOUT("write ee hostif failed to get semaphore");
3064                 status = IXGBE_ERR_SWFW_SYNC;
3065         }
3066
3067         return status;
3068 }
3069
3070 /**
3071  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3072  *  @hw: pointer to hardware structure
3073  *  @offset: offset of  word in the EEPROM to write
3074  *  @words: number of words
3075  *  @data: word(s) write to the EEPROM
3076  *
3077  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3078  **/
3079 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3080                                       u16 offset, u16 words, u16 *data)
3081 {
3082         s32 status = IXGBE_SUCCESS;
3083         u32 i = 0;
3084
3085         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3086
3087         /* Take semaphore for the entire operation. */
3088         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3089         if (status != IXGBE_SUCCESS) {
3090                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3091                 goto out;
3092         }
3093
3094         for (i = 0; i < words; i++) {
3095                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3096                                                          data[i]);
3097
3098                 if (status != IXGBE_SUCCESS) {
3099                         DEBUGOUT("Eeprom buffered write failed\n");
3100                         break;
3101                 }
3102         }
3103
3104         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3105 out:
3106
3107         return status;
3108 }
3109
3110 /**
3111  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3112  * @hw: pointer to hardware structure
3113  * @ptr: pointer offset in eeprom
3114  * @size: size of section pointed by ptr, if 0 first word will be used as size
3115  * @csum: address of checksum to update
3116  *
3117  * Returns error status for any failure
3118  */
3119 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3120                                    u16 size, u16 *csum, u16 *buffer,
3121                                    u32 buffer_size)
3122 {
3123         u16 buf[256];
3124         s32 status;
3125         u16 length, bufsz, i, start;
3126         u16 *local_buffer;
3127
3128         bufsz = sizeof(buf) / sizeof(buf[0]);
3129
3130         /* Read a chunk at the pointer location */
3131         if (!buffer) {
3132                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3133                 if (status) {
3134                         DEBUGOUT("Failed to read EEPROM image\n");
3135                         return status;
3136                 }
3137                 local_buffer = buf;
3138         } else {
3139                 if (buffer_size < ptr)
3140                         return  IXGBE_ERR_PARAM;
3141                 local_buffer = &buffer[ptr];
3142         }
3143
3144         if (size) {
3145                 start = 0;
3146                 length = size;
3147         } else {
3148                 start = 1;
3149                 length = local_buffer[0];
3150
3151                 /* Skip pointer section if length is invalid. */
3152                 if (length == 0xFFFF || length == 0 ||
3153                     (ptr + length) >= hw->eeprom.word_size)
3154                         return IXGBE_SUCCESS;
3155         }
3156
3157         if (buffer && ((u32)start + (u32)length > buffer_size))
3158                 return IXGBE_ERR_PARAM;
3159
3160         for (i = start; length; i++, length--) {
3161                 if (i == bufsz && !buffer) {
3162                         ptr += bufsz;
3163                         i = 0;
3164                         if (length < bufsz)
3165                                 bufsz = length;
3166
3167                         /* Read a chunk at the pointer location */
3168                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3169                                                                   bufsz, buf);
3170                         if (status) {
3171                                 DEBUGOUT("Failed to read EEPROM image\n");
3172                                 return status;
3173                         }
3174                 }
3175                 *csum += local_buffer[i];
3176         }
3177         return IXGBE_SUCCESS;
3178 }
3179
3180 /**
3181  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3182  *  @hw: pointer to hardware structure
3183  *  @buffer: pointer to buffer containing calculated checksum
3184  *  @buffer_size: size of buffer
3185  *
3186  *  Returns a negative error code on error, or the 16-bit checksum
3187  **/
3188 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3189 {
3190         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3191         u16 *local_buffer;
3192         s32 status;
3193         u16 checksum = 0;
3194         u16 pointer, i, size;
3195
3196         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3197
3198         hw->eeprom.ops.init_params(hw);
3199
3200         if (!buffer) {
3201                 /* Read pointer area */
3202                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3203                                                      IXGBE_EEPROM_LAST_WORD + 1,
3204                                                      eeprom_ptrs);
3205                 if (status) {
3206                         DEBUGOUT("Failed to read EEPROM image\n");
3207                         return status;
3208                 }
3209                 local_buffer = eeprom_ptrs;
3210         } else {
3211                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3212                         return IXGBE_ERR_PARAM;
3213                 local_buffer = buffer;
3214         }
3215
3216         /*
3217          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3218          * checksum word itself
3219          */
3220         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3221                 if (i != IXGBE_EEPROM_CHECKSUM)
3222                         checksum += local_buffer[i];
3223
3224         /*
3225          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3226          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3227          */
3228         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3229                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3230                         continue;
3231
3232                 pointer = local_buffer[i];
3233
3234                 /* Skip pointer section if the pointer is invalid. */
3235                 if (pointer == 0xFFFF || pointer == 0 ||
3236                     pointer >= hw->eeprom.word_size)
3237                         continue;
3238
3239                 switch (i) {
3240                 case IXGBE_PCIE_GENERAL_PTR:
3241                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3242                         break;
3243                 case IXGBE_PCIE_CONFIG0_PTR:
3244                 case IXGBE_PCIE_CONFIG1_PTR:
3245                         size = IXGBE_PCIE_CONFIG_SIZE;
3246                         break;
3247                 default:
3248                         size = 0;
3249                         break;
3250                 }
3251
3252                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3253                                                 buffer, buffer_size);
3254                 if (status)
3255                         return status;
3256         }
3257
3258         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3259
3260         return (s32)checksum;
3261 }
3262
3263 /**
3264  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3265  *  @hw: pointer to hardware structure
3266  *
3267  *  Returns a negative error code on error, or the 16-bit checksum
3268  **/
3269 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3270 {
3271         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3272 }
3273
3274 /**
3275  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3276  *  @hw: pointer to hardware structure
3277  *  @checksum_val: calculated checksum
3278  *
3279  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3280  *  caller does not need checksum_val, the value can be NULL.
3281  **/
3282 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3283 {
3284         s32 status;
3285         u16 checksum;
3286         u16 read_checksum = 0;
3287
3288         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3289
3290         /* Read the first word from the EEPROM. If this times out or fails, do
3291          * not continue or we could be in for a very long wait while every
3292          * EEPROM read fails
3293          */
3294         status = hw->eeprom.ops.read(hw, 0, &checksum);
3295         if (status) {
3296                 DEBUGOUT("EEPROM read failed\n");
3297                 return status;
3298         }
3299
3300         status = hw->eeprom.ops.calc_checksum(hw);
3301         if (status < 0)
3302                 return status;
3303
3304         checksum = (u16)(status & 0xffff);
3305
3306         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3307                                            &read_checksum);
3308         if (status)
3309                 return status;
3310
3311         /* Verify read checksum from EEPROM is the same as
3312          * calculated checksum
3313          */
3314         if (read_checksum != checksum) {
3315                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3316                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3317                              "Invalid EEPROM checksum");
3318         }
3319
3320         /* If the user cares, return the calculated checksum */
3321         if (checksum_val)
3322                 *checksum_val = checksum;
3323
3324         return status;
3325 }
3326
3327 /**
3328  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3329  * @hw: pointer to hardware structure
3330  *
3331  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3332  * checksum and updates the EEPROM and instructs the hardware to update
3333  * the flash.
3334  **/
3335 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3336 {
3337         s32 status;
3338         u16 checksum = 0;
3339
3340         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3341
3342         /* Read the first word from the EEPROM. If this times out or fails, do
3343          * not continue or we could be in for a very long wait while every
3344          * EEPROM read fails
3345          */
3346         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3347         if (status) {
3348                 DEBUGOUT("EEPROM read failed\n");
3349                 return status;
3350         }
3351
3352         status = ixgbe_calc_eeprom_checksum_X550(hw);
3353         if (status < 0)
3354                 return status;
3355
3356         checksum = (u16)(status & 0xffff);
3357
3358         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3359                                             checksum);
3360         if (status)
3361                 return status;
3362
3363         status = ixgbe_update_flash_X550(hw);
3364
3365         return status;
3366 }
3367
3368 /**
3369  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3370  *  @hw: pointer to hardware structure
3371  *
3372  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3373  **/
3374 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3375 {
3376         s32 status = IXGBE_SUCCESS;
3377         union ixgbe_hic_hdr2 buffer;
3378
3379         DEBUGFUNC("ixgbe_update_flash_X550");
3380
3381         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3382         buffer.req.buf_lenh = 0;
3383         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3384         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3385
3386         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3387                                               sizeof(buffer),
3388                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3389
3390         return status;
3391 }
3392
3393 /**
3394  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3395  *  @hw: pointer to hardware structure
3396  *
3397  *  Determines physical layer capabilities of the current configuration.
3398  **/
3399 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3400 {
3401         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3402         u16 ext_ability = 0;
3403
3404         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3405
3406         hw->phy.ops.identify(hw);
3407
3408         switch (hw->phy.type) {
3409         case ixgbe_phy_x550em_kr:
3410                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3411                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3412                 break;
3413         case ixgbe_phy_x550em_kx4:
3414                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3415                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3416                 break;
3417         case ixgbe_phy_x550em_ext_t:
3418                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3419                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3420                                      &ext_ability);
3421                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3422                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3423                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3424                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3425                 break;
3426         default:
3427                 break;
3428         }
3429
3430         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3431                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3432
3433         return physical_layer;
3434 }
3435
3436 /**
3437  * ixgbe_get_bus_info_x550em - Set PCI bus info
3438  * @hw: pointer to hardware structure
3439  *
3440  * Sets bus link width and speed to unknown because X550em is
3441  * not a PCI device.
3442  **/
3443 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3444 {
3445
3446         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3447
3448         hw->bus.width = ixgbe_bus_width_unknown;
3449         hw->bus.speed = ixgbe_bus_speed_unknown;
3450
3451         hw->mac.ops.set_lan_id(hw);
3452
3453         return IXGBE_SUCCESS;
3454 }
3455
3456 /**
3457  * ixgbe_disable_rx_x550 - Disable RX unit
3458  *
3459  * Enables the Rx DMA unit for x550
3460  **/
3461 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3462 {
3463         u32 rxctrl, pfdtxgswc;
3464         s32 status;
3465         struct ixgbe_hic_disable_rxen fw_cmd;
3466
3467         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3468
3469         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3470         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3471                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3472                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3473                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3474                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3475                         hw->mac.set_lben = true;
3476                 } else {
3477                         hw->mac.set_lben = false;
3478                 }
3479
3480                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3481                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3482                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3483                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3484
3485                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3486                                         sizeof(struct ixgbe_hic_disable_rxen),
3487                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3488
3489                 /* If we fail - disable RX using register write */
3490                 if (status) {
3491                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3492                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3493                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3494                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3495                         }
3496                 }
3497         }
3498 }
3499
3500 /**
3501  * ixgbe_enter_lplu_x550em - Transition to low power states
3502  *  @hw: pointer to hardware structure
3503  *
3504  * Configures Low Power Link Up on transition to low power states
3505  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3506  * X557 PHY immediately prior to entering LPLU.
3507  **/
3508 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3509 {
3510         u16 an_10g_cntl_reg, autoneg_reg, speed;
3511         s32 status;
3512         ixgbe_link_speed lcd_speed;
3513         u32 save_autoneg;
3514         bool link_up;
3515
3516         /* SW LPLU not required on later HW revisions. */
3517         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3518             (IXGBE_FUSES0_REV_MASK &
3519              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3520                 return IXGBE_SUCCESS;
3521
3522         /* If blocked by MNG FW, then don't restart AN */
3523         if (ixgbe_check_reset_blocked(hw))
3524                 return IXGBE_SUCCESS;
3525
3526         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3527         if (status != IXGBE_SUCCESS)
3528                 return status;
3529
3530         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3531
3532         if (status != IXGBE_SUCCESS)
3533                 return status;
3534
3535         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3536          * disabled, then force link down by entering low power mode.
3537          */
3538         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3539             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3540                 return ixgbe_set_copper_phy_power(hw, FALSE);
3541
3542         /* Determine LCD */
3543         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3544
3545         if (status != IXGBE_SUCCESS)
3546                 return status;
3547
3548         /* If no valid LCD link speed, then force link down and exit. */
3549         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3550                 return ixgbe_set_copper_phy_power(hw, FALSE);
3551
3552         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3553                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3554                                       &speed);
3555
3556         if (status != IXGBE_SUCCESS)
3557                 return status;
3558
3559         /* If no link now, speed is invalid so take link down */
3560         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3561         if (status != IXGBE_SUCCESS)
3562                 return ixgbe_set_copper_phy_power(hw, false);
3563
3564         /* clear everything but the speed bits */
3565         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3566
3567         /* If current speed is already LCD, then exit. */
3568         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3569              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3570             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3571              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3572                 return status;
3573
3574         /* Clear AN completed indication */
3575         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3576                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3577                                       &autoneg_reg);
3578
3579         if (status != IXGBE_SUCCESS)
3580                 return status;
3581
3582         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3583                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3584                              &an_10g_cntl_reg);
3585
3586         if (status != IXGBE_SUCCESS)
3587                 return status;
3588
3589         status = hw->phy.ops.read_reg(hw,
3590                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3591                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3592                              &autoneg_reg);
3593
3594         if (status != IXGBE_SUCCESS)
3595                 return status;
3596
3597         save_autoneg = hw->phy.autoneg_advertised;
3598
3599         /* Setup link at least common link speed */
3600         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3601
3602         /* restore autoneg from before setting lplu speed */
3603         hw->phy.autoneg_advertised = save_autoneg;
3604
3605         return status;
3606 }
3607
3608 /**
3609  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3610  *  @hw: pointer to hardware structure
3611  *  @lcd_speed: pointer to lowest common link speed
3612  *
3613  * Determine lowest common link speed with link partner.
3614  **/
3615 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3616 {
3617         u16 an_lp_status;
3618         s32 status;
3619         u16 word = hw->eeprom.ctrl_word_3;
3620
3621         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3622
3623         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3624                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3625                                       &an_lp_status);
3626
3627         if (status != IXGBE_SUCCESS)
3628                 return status;
3629
3630         /* If link partner advertised 1G, return 1G */
3631         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3632                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3633                 return status;
3634         }
3635
3636         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3637         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3638             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3639                 return status;
3640
3641         /* Link partner not capable of lower speeds, return 10G */
3642         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3643         return status;
3644 }
3645
3646 /**
3647  *  ixgbe_setup_fc_X550em - Set up flow control
3648  *  @hw: pointer to hardware structure
3649  *
3650  *  Called at init time to set up flow control.
3651  **/
3652 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3653 {
3654         s32 ret_val = IXGBE_SUCCESS;
3655         u32 pause, asm_dir, reg_val;
3656
3657         DEBUGFUNC("ixgbe_setup_fc_X550em");
3658
3659         /* Validate the requested mode */
3660         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3661                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3662                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3663                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3664                 goto out;
3665         }
3666
3667         /* 10gig parts do not have a word in the EEPROM to determine the
3668          * default flow control setting, so we explicitly set it to full.
3669          */
3670         if (hw->fc.requested_mode == ixgbe_fc_default)
3671                 hw->fc.requested_mode = ixgbe_fc_full;
3672
3673         /* Determine PAUSE and ASM_DIR bits. */
3674         switch (hw->fc.requested_mode) {
3675         case ixgbe_fc_none:
3676                 pause = 0;
3677                 asm_dir = 0;
3678                 break;
3679         case ixgbe_fc_tx_pause:
3680                 pause = 0;
3681                 asm_dir = 1;
3682                 break;
3683         case ixgbe_fc_rx_pause:
3684                 /* Rx Flow control is enabled and Tx Flow control is
3685                  * disabled by software override. Since there really
3686                  * isn't a way to advertise that we are capable of RX
3687                  * Pause ONLY, we will advertise that we support both
3688                  * symmetric and asymmetric Rx PAUSE, as such we fall
3689                  * through to the fc_full statement.  Later, we will
3690                  * disable the adapter's ability to send PAUSE frames.
3691                  */
3692         case ixgbe_fc_full:
3693                 pause = 1;
3694                 asm_dir = 1;
3695                 break;
3696         default:
3697                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3698                         "Flow control param set incorrectly\n");
3699                 ret_val = IXGBE_ERR_CONFIG;
3700                 goto out;
3701         }
3702
3703         switch (hw->device_id) {
3704         case IXGBE_DEV_ID_X550EM_X_KR:
3705         case IXGBE_DEV_ID_X550EM_A_KR:
3706         case IXGBE_DEV_ID_X550EM_A_KR_L:
3707                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3708                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3709                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3710                 if (ret_val != IXGBE_SUCCESS)
3711                         goto out;
3712                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3713                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3714                 if (pause)
3715                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3716                 if (asm_dir)
3717                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3718                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3719                                        IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3720                                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3721
3722                 /* This device does not fully support AN. */
3723                 hw->fc.disable_fc_autoneg = true;
3724                 break;
3725         default:
3726                 break;
3727         }
3728
3729 out:
3730         return ret_val;
3731 }
3732
3733 /**
3734  *  ixgbe_fc_autoneg_x550a - Enable flow control IEEE clause 37
3735  *  @hw: pointer to hardware structure
3736  *
3737  *  Enable flow control according to IEEE clause 37.
3738  **/
3739 void ixgbe_fc_autoneg_x550a(struct ixgbe_hw *hw)
3740 {
3741         u32 link_s1, lp_an_page_low, an_cntl_1;
3742         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3743         ixgbe_link_speed speed;
3744         bool link_up;
3745
3746         /* AN should have completed when the cable was plugged in.
3747          * Look for reasons to bail out.  Bail out if:
3748          * - FC autoneg is disabled, or if
3749          * - link is not up.
3750          */
3751         if (hw->fc.disable_fc_autoneg) {
3752                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3753                               "Flow control autoneg is disabled");
3754                 goto out;
3755         }
3756
3757         hw->mac.ops.check_link(hw, &speed, &link_up, false);
3758         if (!link_up) {
3759                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3760                 goto out;
3761         }
3762
3763         /* Check at auto-negotiation has completed */
3764         status = hw->mac.ops.read_iosf_sb_reg(hw,
3765                                       IXGBE_KRM_LINK_S1(hw->bus.lan_id),
3766                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
3767
3768         if (status != IXGBE_SUCCESS ||
3769             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
3770                 DEBUGOUT("Auto-Negotiation did not complete\n");
3771                 goto out;
3772         }
3773
3774         /* Read the 10g AN autoc and LP ability registers and resolve
3775          * local flow control settings accordingly
3776          */
3777         status = hw->mac.ops.read_iosf_sb_reg(hw,
3778                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3779                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
3780
3781         if (status != IXGBE_SUCCESS) {
3782                 DEBUGOUT("Auto-Negotiation did not complete\n");
3783                 goto out;
3784         }
3785
3786         status = hw->mac.ops.read_iosf_sb_reg(hw,
3787                               IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
3788                               IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
3789
3790         if (status != IXGBE_SUCCESS) {
3791                 DEBUGOUT("Auto-Negotiation did not complete\n");
3792                 goto out;
3793         }
3794
3795         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
3796                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
3797                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
3798                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
3799                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
3800
3801 out:
3802         if (status == IXGBE_SUCCESS) {
3803                 hw->fc.fc_was_autonegged = true;
3804         } else {
3805                 hw->fc.fc_was_autonegged = false;
3806                 hw->fc.current_mode = hw->fc.requested_mode;
3807         }
3808 }
3809
3810 /**
3811  *  ixgbe_setup_fc_x550em - Set up flow control
3812  *  @hw: pointer to hardware structure
3813  *
3814  *  Called at init time to set up flow control.
3815  **/
3816 s32 ixgbe_setup_fc_x550a(struct ixgbe_hw *hw)
3817 {
3818         s32 status = IXGBE_SUCCESS;
3819         u32 an_cntl, link_ctrl = 0;
3820
3821         DEBUGFUNC("ixgbe_setup_fc_x550em");
3822
3823         /* Validate the requested mode */
3824         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3825                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3826                       "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3827                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
3828         }
3829
3830         if (hw->fc.requested_mode == ixgbe_fc_default)
3831                 hw->fc.requested_mode = ixgbe_fc_full;
3832
3833         /* Set up the 1G and 10G flow control advertisement registers so the
3834          * HW will be able to do FC autoneg once the cable is plugged in.  If
3835          * we link at 10G, the 1G advertisement is harmless and vice versa.
3836          */
3837         status = hw->mac.ops.read_iosf_sb_reg(hw,
3838                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3839                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
3840
3841         if (status != IXGBE_SUCCESS) {
3842                 DEBUGOUT("Auto-Negotiation did not complete\n");
3843                 return status;
3844         }
3845
3846         /* The possible values of fc.requested_mode are:
3847          * 0: Flow control is completely disabled
3848          * 1: Rx flow control is enabled (we can receive pause frames,
3849          *    but not send pause frames).
3850          * 2: Tx flow control is enabled (we can send pause frames but
3851          *    we do not support receiving pause frames).
3852          * 3: Both Rx and Tx flow control (symmetric) are enabled.
3853          * other: Invalid.
3854          */
3855         switch (hw->fc.requested_mode) {
3856         case ixgbe_fc_none:
3857                 /* Flow control completely disabled by software override. */
3858                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3859                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3860                 break;
3861         case ixgbe_fc_tx_pause:
3862                 /* Tx Flow control is enabled, and Rx Flow control is
3863                  * disabled by software override.
3864                  */
3865                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3866                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3867                 break;
3868         case ixgbe_fc_rx_pause:
3869                 /* Rx Flow control is enabled and Tx Flow control is
3870                  * disabled by software override. Since there really
3871                  * isn't a way to advertise that we are capable of RX
3872                  * Pause ONLY, we will advertise that we support both
3873                  * symmetric and asymmetric Rx PAUSE, as such we fall
3874                  * through to the fc_full statement.  Later, we will
3875                  * disable the adapter's ability to send PAUSE frames.
3876                  */
3877         case ixgbe_fc_full:
3878                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3879                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3880                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3881                 break;
3882         default:
3883                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3884                               "Flow control param set incorrectly\n");
3885                 return IXGBE_ERR_CONFIG;
3886         }
3887
3888         status = hw->mac.ops.write_iosf_sb_reg(hw,
3889                                        IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3890                                        IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
3891
3892         /* Restart auto-negotiation. */
3893         status = hw->mac.ops.read_iosf_sb_reg(hw,
3894                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3895                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
3896
3897         if (status != IXGBE_SUCCESS) {
3898                 DEBUGOUT("Auto-Negotiation did not complete\n");
3899                 return status;
3900         }
3901
3902         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
3903         status = hw->mac.ops.write_iosf_sb_reg(hw,
3904                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3905                                        IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
3906
3907         return status;
3908 }
3909
3910 /**
3911  * ixgbe_set_mux - Set mux for port 1 access with CS4227
3912  * @hw: pointer to hardware structure
3913  * @state: set mux if 1, clear if 0
3914  */
3915 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3916 {
3917         u32 esdp;
3918
3919         if (!hw->bus.lan_id)
3920                 return;
3921         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3922         if (state)
3923                 esdp |= IXGBE_ESDP_SDP1;
3924         else
3925                 esdp &= ~IXGBE_ESDP_SDP1;
3926         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3927         IXGBE_WRITE_FLUSH(hw);
3928 }
3929
3930 /**
3931  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3932  *  @hw: pointer to hardware structure
3933  *  @mask: Mask to specify which semaphore to acquire
3934  *
3935  *  Acquires the SWFW semaphore and sets the I2C MUX
3936  **/
3937 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3938 {
3939         s32 status;
3940
3941         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
3942
3943         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3944         if (status)
3945                 return status;
3946
3947         if (mask & IXGBE_GSSR_I2C_MASK)
3948                 ixgbe_set_mux(hw, 1);
3949
3950         return IXGBE_SUCCESS;
3951 }
3952
3953 /**
3954  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3955  *  @hw: pointer to hardware structure
3956  *  @mask: Mask to specify which semaphore to release
3957  *
3958  *  Releases the SWFW semaphore and sets the I2C MUX
3959  **/
3960 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3961 {
3962         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3963
3964         if (mask & IXGBE_GSSR_I2C_MASK)
3965                 ixgbe_set_mux(hw, 0);
3966
3967         ixgbe_release_swfw_sync_X540(hw, mask);
3968 }
3969
3970 /**
3971  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
3972  *  @hw: pointer to hardware structure
3973  *  @mask: Mask to specify which semaphore to acquire
3974  *
3975  *  Acquires the SWFW semaphore and get the shared phy token as needed
3976  */
3977 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3978 {
3979         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3980         int retries = FW_PHY_TOKEN_RETRIES;
3981         s32 status = IXGBE_SUCCESS;
3982
3983         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
3984
3985         while (--retries) {
3986                 status = IXGBE_SUCCESS;
3987                 if (hmask)
3988                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3989                 if (status)
3990                         return status;
3991                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3992                         return IXGBE_SUCCESS;
3993
3994                 status = ixgbe_get_phy_token(hw);
3995                 if (status == IXGBE_SUCCESS)
3996                         return IXGBE_SUCCESS;
3997
3998                 if (hmask)
3999                         ixgbe_release_swfw_sync_X540(hw, hmask);
4000                 if (status != IXGBE_ERR_TOKEN_RETRY)
4001                         return status;
4002                 msec_delay(FW_PHY_TOKEN_DELAY);
4003         }
4004
4005         return status;
4006 }
4007
4008 /**
4009  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4010  *  @hw: pointer to hardware structure
4011  *  @mask: Mask to specify which semaphore to release
4012  *
4013  *  Releases the SWFW semaphore and puts the shared phy token as needed
4014  */
4015 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4016 {
4017         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4018
4019         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4020
4021         if (mask & IXGBE_GSSR_TOKEN_SM)
4022                 ixgbe_put_phy_token(hw);
4023
4024         if (hmask)
4025                 ixgbe_release_swfw_sync_X540(hw, hmask);
4026 }
4027
4028 /**
4029  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4030  *  @hw: pointer to hardware structure
4031  *  @reg_addr: 32 bit address of PHY register to read
4032  *  @phy_data: Pointer to read data from PHY register
4033  *
4034  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4035  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4036  *  instances.
4037  **/
4038 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4039                              u32 device_type, u16 *phy_data)
4040 {
4041         s32 status;
4042         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4043
4044         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4045
4046         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4047                 return IXGBE_ERR_SWFW_SYNC;
4048
4049         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4050
4051         hw->mac.ops.release_swfw_sync(hw, mask);
4052
4053         return status;
4054 }
4055
4056 /**
4057  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4058  *  @hw: pointer to hardware structure
4059  *  @reg_addr: 32 bit PHY register to write
4060  *  @device_type: 5 bit device type
4061  *  @phy_data: Data to write to the PHY register
4062  *
4063  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4064  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4065  **/
4066 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4067                               u32 device_type, u16 phy_data)
4068 {
4069         s32 status;
4070         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4071
4072         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4073
4074         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4075                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
4076                                                  phy_data);
4077                 hw->mac.ops.release_swfw_sync(hw, mask);
4078         } else {
4079                 status = IXGBE_ERR_SWFW_SYNC;
4080         }
4081
4082         return status;
4083 }
4084
4085 /**
4086  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4087  * @hw: pointer to hardware structure
4088  *
4089  * Handle external Base T PHY interrupt. If high temperature
4090  * failure alarm then return error, else if link status change
4091  * then setup internal/external PHY link
4092  *
4093  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4094  * failure alarm, else return PHY access status.
4095  */
4096 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4097 {
4098         bool lsc;
4099         u32 status;
4100
4101         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4102
4103         if (status != IXGBE_SUCCESS)
4104                 return status;
4105
4106         if (lsc)
4107                 return ixgbe_setup_internal_phy(hw);
4108
4109         return IXGBE_SUCCESS;
4110 }
4111
4112 /**
4113  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4114  * @hw: pointer to hardware structure
4115  * @speed: new link speed
4116  * @autoneg_wait_to_complete: true when waiting for completion is needed
4117  *
4118  * Setup internal/external PHY link speed based on link speed, then set
4119  * external PHY auto advertised link speed.
4120  *
4121  * Returns error status for any failure
4122  **/
4123 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4124                                   ixgbe_link_speed speed,
4125                                   bool autoneg_wait_to_complete)
4126 {
4127         s32 status;
4128         ixgbe_link_speed force_speed;
4129
4130         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4131
4132         /* Setup internal/external PHY link speed to iXFI (10G), unless
4133          * only 1G is auto advertised then setup KX link.
4134          */
4135         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4136                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4137         else
4138                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4139
4140         /* If internal link mode is XFI, then setup XFI internal link. */
4141         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4142                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4143
4144                 if (status != IXGBE_SUCCESS)
4145                         return status;
4146         }
4147
4148         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4149 }
4150
4151 /**
4152  * ixgbe_check_link_t_X550em - Determine link and speed status
4153  * @hw: pointer to hardware structure
4154  * @speed: pointer to link speed
4155  * @link_up: true when link is up
4156  * @link_up_wait_to_complete: bool used to wait for link up or not
4157  *
4158  * Check that both the MAC and X557 external PHY have link.
4159  **/
4160 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4161                               bool *link_up, bool link_up_wait_to_complete)
4162 {
4163         u32 status;
4164         u16 autoneg_status;
4165
4166         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4167                 return IXGBE_ERR_CONFIG;
4168
4169         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4170                                               link_up_wait_to_complete);
4171
4172         /* If check link fails or MAC link is not up, then return */
4173         if (status != IXGBE_SUCCESS || !(*link_up))
4174                 return status;
4175
4176         /* MAC link is up, so check external PHY link.
4177          * Read this twice back to back to indicate current status.
4178          */
4179         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4180                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4181                                       &autoneg_status);
4182
4183         if (status != IXGBE_SUCCESS)
4184                 return status;
4185
4186         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4187                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4188                                       &autoneg_status);
4189
4190         if (status != IXGBE_SUCCESS)
4191                 return status;
4192
4193         /* If external PHY link is not up, then indicate link not up */
4194         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4195                 *link_up = false;
4196
4197         return IXGBE_SUCCESS;
4198 }
4199
4200 /**
4201  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4202  *  @hw: pointer to hardware structure
4203  **/
4204 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4205 {
4206         s32 status;
4207
4208         status = ixgbe_reset_phy_generic(hw);
4209
4210         if (status != IXGBE_SUCCESS)
4211                 return status;
4212
4213         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4214         return ixgbe_enable_lasi_ext_t_x550em(hw);
4215 }
4216
4217 /**
4218  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4219  *  @hw: pointer to hardware structure
4220  *  @led_idx: led number to turn on
4221  **/
4222 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4223 {
4224         u16 phy_data;
4225
4226         DEBUGFUNC("ixgbe_led_on_t_X550em");
4227
4228         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4229                 return IXGBE_ERR_PARAM;
4230
4231         /* To turn on the LED, set mode to ON. */
4232         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4233                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4234         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4235         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4236                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4237
4238         return IXGBE_SUCCESS;
4239 }
4240
4241 /**
4242  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4243  *  @hw: pointer to hardware structure
4244  *  @led_idx: led number to turn off
4245  **/
4246 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4247 {
4248         u16 phy_data;
4249
4250         DEBUGFUNC("ixgbe_led_off_t_X550em");
4251
4252         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4253                 return IXGBE_ERR_PARAM;
4254
4255         /* To turn on the LED, set mode to ON. */
4256         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4257                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4258         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4259         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4260                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4261
4262         return IXGBE_SUCCESS;
4263 }
4264