drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41
  42 /**
  43  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  44  *  @hw: pointer to hardware structure
  45  *
  46  *  Initialize the function pointers and assign the MAC type for X550.
  47  *  Does not touch the hardware.
  48  **/
  49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  50 {
  51         struct ixgbe_mac_info *mac = &hw->mac;
  52         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  53         s32 ret_val;
  54
  55         DEBUGFUNC("ixgbe_init_ops_X550");
  56
  57         ret_val = ixgbe_init_ops_X540(hw);
  58         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  59         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  60         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  61         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  62         mac->ops.set_source_address_pruning =
  63                         ixgbe_set_source_address_pruning_X550;
  64         mac->ops.set_ethertype_anti_spoofing =
  65                         ixgbe_set_ethertype_anti_spoofing_X550;
  66
  67         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  68         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  69         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  70         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  71         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  72         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  73         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  74         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  75         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  76
  77         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  78         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  79         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  80         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  81         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  82         return ret_val;
  83 }
  84
  85 /**
  86  * ixgbe_read_cs4227 - Read CS4227 register
  87  * @hw: pointer to hardware structure
  88  * @reg: register number to write
  89  * @value: pointer to receive value read
  90  *
  91  * Returns status code
  92  **/
  93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  94 {
  95         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
  96 }
  97
  98 /**
  99  * ixgbe_write_cs4227 - Write CS4227 register
 100  * @hw: pointer to hardware structure
 101  * @reg: register number to write
 102  * @value: value to write to register
 103  *
 104  * Returns status code
 105  **/
 106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 107 {
 108         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 109 }
 110
 111 /**
 112  * ixgbe_get_cs4227_status - Return CS4227 status
 113  * @hw: pointer to hardware structure
 114  *
 115  * Returns error if CS4227 not successfully initialized
 116  **/
 117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
 118 {
 119         s32 status;
 120         u16 value = 0;
 121         u8 retry;
 122
 123         for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
 124                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
 125                                            &value);
 126                 if (status != IXGBE_SUCCESS)
 127                         return status;
 128                 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
 129                         break;
 130                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 131         }
 132         if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
 133                 return IXGBE_ERR_PHY;
 134
 135         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 136                                     IXGBE_CS4227_SCRATCH_VALUE);
 137         if (status != IXGBE_SUCCESS)
 138                 return status;
 139         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 140         if (status != IXGBE_SUCCESS)
 141                 return status;
 142         if (value != IXGBE_CS4227_SCRATCH_VALUE)
 143                 return IXGBE_ERR_PHY;
 144         return IXGBE_SUCCESS;
 145 }
 146
 147 /**
 148  * ixgbe_read_pe - Read register from port expander
 149  * @hw: pointer to hardware structure
 150  * @reg: register number to read
 151  * @value: pointer to receive read value
 152  *
 153  * Returns status code
 154  **/
 155 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 156 {
 157         s32 status;
 158
 159         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 160         if (status != IXGBE_SUCCESS)
 161                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 162                               "port expander access failed with %d\n", status);
 163         return status;
 164 }
 165
 166 /**
 167  * ixgbe_write_pe - Write register to port expander
 168  * @hw: pointer to hardware structure
 169  * @reg: register number to write
 170  * @value: value to write
 171  *
 172  * Returns status code
 173  **/
 174 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 175 {
 176         s32 status;
 177
 178         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 179         if (status != IXGBE_SUCCESS)
 180                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 181                               "port expander access failed with %d\n", status);
 182         return status;
 183 }
 184
 185 /**
 186  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 187  * @hw: pointer to hardware structure
 188  *
 189  * Returns error code
 190  **/
 191 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 192 {
 193         s32 status;
 194         u8 reg;
 195
 196         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199         reg |= IXGBE_PE_BIT1;
 200         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 201         if (status != IXGBE_SUCCESS)
 202                 return status;
 203
 204         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 205         if (status != IXGBE_SUCCESS)
 206                 return status;
 207         reg &= ~IXGBE_PE_BIT1;
 208         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 209         if (status != IXGBE_SUCCESS)
 210                 return status;
 211
 212         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 213         if (status != IXGBE_SUCCESS)
 214                 return status;
 215         reg &= ~IXGBE_PE_BIT1;
 216         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 217         if (status != IXGBE_SUCCESS)
 218                 return status;
 219
 220         usec_delay(IXGBE_CS4227_RESET_HOLD);
 221
 222         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 223         if (status != IXGBE_SUCCESS)
 224                 return status;
 225         reg |= IXGBE_PE_BIT1;
 226         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 227         if (status != IXGBE_SUCCESS)
 228                 return status;
 229
 230         msec_delay(IXGBE_CS4227_RESET_DELAY);
 231
 232         return IXGBE_SUCCESS;
 233 }
 234
 235 /**
 236  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 237  * @hw: pointer to hardware structure
 238  **/
 239 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 240 {
 241         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 242         s32 status;
 243         u8 retry;
 244
 245         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 246                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 247                 if (status != IXGBE_SUCCESS) {
 248                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 249                                       "semaphore failed with %d\n", status);
 250                         return;
 251                 }
 252                 status = ixgbe_get_cs4227_status(hw);
 253                 if (status == IXGBE_SUCCESS) {
 254                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 255                         msec_delay(hw->eeprom.semaphore_delay);
 256                         return;
 257                 }
 258                 ixgbe_reset_cs4227(hw);
 259                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 260                 msec_delay(hw->eeprom.semaphore_delay);
 261         }
 262         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 263                       "Unable to initialize CS4227, err=%d\n", status);
 264 }
 265
 266 /**
 267  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 268  * @hw: pointer to hardware structure
 269  **/
 270 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 271 {
 272         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 273
 274         if (hw->bus.lan_id) {
 275                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 276                 esdp |= IXGBE_ESDP_SDP1_DIR;
 277         }
 278         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 279         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 280         IXGBE_WRITE_FLUSH(hw);
 281 }
 282
 283 /**
 284  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 285  * @hw: pointer to hardware structure
 286  *
 287  * Returns error code
 288  */
 289 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 290 {
 291         switch (hw->device_id) {
 292         case IXGBE_DEV_ID_X550EM_X_SFP:
 293                 /* set up for CS4227 usage */
 294                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 295                 ixgbe_setup_mux_ctl(hw);
 296                 ixgbe_check_cs4227(hw);
 297
 298                 return ixgbe_identify_module_generic(hw);
 299                 break;
 300         case IXGBE_DEV_ID_X550EM_X_KX4:
 301                 hw->phy.type = ixgbe_phy_x550em_kx4;
 302                 break;
 303         case IXGBE_DEV_ID_X550EM_X_KR:
 304                 hw->phy.type = ixgbe_phy_x550em_kr;
 305                 break;
 306         case IXGBE_DEV_ID_X550EM_X_1G_T:
 307         case IXGBE_DEV_ID_X550EM_X_10G_T:
 308                 return ixgbe_identify_phy_generic(hw);
 309         default:
 310                 break;
 311         }
 312         return IXGBE_SUCCESS;
 313 }
 314
 315 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 316                                      u32 device_type, u16 *phy_data)
 317 {
 318         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 319         return IXGBE_NOT_IMPLEMENTED;
 320 }
 321
 322 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 323                                       u32 device_type, u16 phy_data)
 324 {
 325         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 326         return IXGBE_NOT_IMPLEMENTED;
 327 }
 328
 329 /**
 330 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 331 *  @hw: pointer to hardware structure
 332 *
 333 *  Initialize the function pointers and for MAC type X550EM.
 334 *  Does not touch the hardware.
 335 **/
 336 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 337 {
 338         struct ixgbe_mac_info *mac = &hw->mac;
 339         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 340         struct ixgbe_phy_info *phy = &hw->phy;
 341         s32 ret_val;
 342
 343         DEBUGFUNC("ixgbe_init_ops_X550EM");
 344
 345         /* Similar to X550 so start there. */
 346         ret_val = ixgbe_init_ops_X550(hw);
 347
 348         /* Since this function eventually calls
 349          * ixgbe_init_ops_540 by design, we are setting
 350          * the pointers to NULL explicitly here to overwrite
 351          * the values being set in the x540 function.
 352          */
 353         /* Thermal sensor not supported in x550EM */
 354         mac->ops.get_thermal_sensor_data = NULL;
 355         mac->ops.init_thermal_sensor_thresh = NULL;
 356         mac->thermal_sensor_enabled = false;
 357
 358         /* FCOE not supported in x550EM */
 359         mac->ops.get_san_mac_addr = NULL;
 360         mac->ops.set_san_mac_addr = NULL;
 361         mac->ops.get_wwn_prefix = NULL;
 362         mac->ops.get_fcoe_boot_status = NULL;
 363
 364         /* IPsec not supported in x550EM */
 365         mac->ops.disable_sec_rx_path = NULL;
 366         mac->ops.enable_sec_rx_path = NULL;
 367
 368         /* AUTOC register is not present in x550EM. */
 369         mac->ops.prot_autoc_read = NULL;
 370         mac->ops.prot_autoc_write = NULL;
 371
 372         /* X550EM bus type is internal*/
 373         hw->bus.type = ixgbe_bus_type_internal;
 374         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 375
 376         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 377         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 378         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 379         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 380         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 381         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 382         mac->ops.get_supported_physical_layer =
 383                                     ixgbe_get_supported_physical_layer_X550em;
 384
 385         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 386                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 387         else
 388                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 389
 390         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 391         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 392
 393         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
 394                 mac->ops.setup_eee = NULL;
 395
 396         /* PHY */
 397         phy->ops.init = ixgbe_init_phy_ops_X550em;
 398         phy->ops.identify = ixgbe_identify_phy_x550em;
 399         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 400                 phy->ops.set_phy_power = NULL;
 401
 402
 403         /* EEPROM */
 404         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 405         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 406         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 407         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 408         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 409         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 410         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 411         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 412
 413         return ret_val;
 414 }
 415
 416 /**
 417  *  ixgbe_dmac_config_X550
 418  *  @hw: pointer to hardware structure
 419  *
 420  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 421  *  When disabling dmac, dmac enable dmac bit is cleared.
 422  **/
 423 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 424 {
 425         u32 reg, high_pri_tc;
 426
 427         DEBUGFUNC("ixgbe_dmac_config_X550");
 428
 429         /* Disable DMA coalescing before configuring */
 430         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 431         reg &= ~IXGBE_DMACR_DMAC_EN;
 432         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 433
 434         /* Disable DMA Coalescing if the watchdog timer is 0 */
 435         if (!hw->mac.dmac_config.watchdog_timer)
 436                 goto out;
 437
 438         ixgbe_dmac_config_tcs_X550(hw);
 439
 440         /* Configure DMA Coalescing Control Register */
 441         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 442
 443         /* Set the watchdog timer in units of 40.96 usec */
 444         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 445         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 446
 447         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 448         /* If fcoe is enabled, set high priority traffic class */
 449         if (hw->mac.dmac_config.fcoe_en) {
 450                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 451                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 452                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 453         }
 454         reg |= IXGBE_DMACR_EN_MNG_IND;
 455
 456         /* Enable DMA coalescing after configuration */
 457         reg |= IXGBE_DMACR_DMAC_EN;
 458         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 459
 460 out:
 461         return IXGBE_SUCCESS;
 462 }
 463
 464 /**
 465  *  ixgbe_dmac_config_tcs_X550
 466  *  @hw: pointer to hardware structure
 467  *
 468  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 469  *  be cleared before configuring.
 470  **/
 471 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 472 {
 473         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 474
 475         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 476
 477         /* Configure DMA coalescing enabled */
 478         switch (hw->mac.dmac_config.link_speed) {
 479         case IXGBE_LINK_SPEED_100_FULL:
 480                 pb_headroom = IXGBE_DMACRXT_100M;
 481                 break;
 482         case IXGBE_LINK_SPEED_1GB_FULL:
 483                 pb_headroom = IXGBE_DMACRXT_1G;
 484                 break;
 485         default:
 486                 pb_headroom = IXGBE_DMACRXT_10G;
 487                 break;
 488         }
 489
 490         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 491                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 492
 493         /* Set the per Rx packet buffer receive threshold */
 494         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 495                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 496                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 497
 498                 if (tc < hw->mac.dmac_config.num_tcs) {
 499                         /* Get Rx PB size */
 500                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 501                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 502                                 IXGBE_RXPBSIZE_SHIFT;
 503
 504                         /* Calculate receive buffer threshold in kilobytes */
 505                         if (rx_pb_size > pb_headroom)
 506                                 rx_pb_size = rx_pb_size - pb_headroom;
 507                         else
 508                                 rx_pb_size = 0;
 509
 510                         /* Minimum of MFS shall be set for DMCTH */
 511                         reg |= (rx_pb_size > maxframe_size_kb) ?
 512                                 rx_pb_size : maxframe_size_kb;
 513                 }
 514                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 515         }
 516         return IXGBE_SUCCESS;
 517 }
 518
 519 /**
 520  *  ixgbe_dmac_update_tcs_X550
 521  *  @hw: pointer to hardware structure
 522  *
 523  *  Disables dmac, updates per TC settings, and then enables dmac.
 524  **/
 525 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 526 {
 527         u32 reg;
 528
 529         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 530
 531         /* Disable DMA coalescing before configuring */
 532         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 533         reg &= ~IXGBE_DMACR_DMAC_EN;
 534         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 535
 536         ixgbe_dmac_config_tcs_X550(hw);
 537
 538         /* Enable DMA coalescing after configuration */
 539         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 540         reg |= IXGBE_DMACR_DMAC_EN;
 541         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 542
 543         return IXGBE_SUCCESS;
 544 }
 545
 546 /**
 547  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 548  *  @hw: pointer to hardware structure
 549  *
 550  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 551  *  ixgbe_hw struct in order to set up EEPROM access.
 552  **/
 553 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 554 {
 555         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 556         u32 eec;
 557         u16 eeprom_size;
 558
 559         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 560
 561         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 562                 eeprom->semaphore_delay = 10;
 563                 eeprom->type = ixgbe_flash;
 564
 565                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 566                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 567                                     IXGBE_EEC_SIZE_SHIFT);
 568                 eeprom->word_size = 1 << (eeprom_size +
 569                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 570
 571                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 572                           eeprom->type, eeprom->word_size);
 573         }
 574
 575         return IXGBE_SUCCESS;
 576 }
 577
 578 /**
 579  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 580  *  @hw: pointer to the HW structure
 581  *  @enable_eee: boolean flag to enable EEE
 582  *
 583  *  Enable/disable EEE based on enable_eee flag.
 584  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 585  *  are modified.
 586  *
 587  **/
 588 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 589 {
 590         u32 eeer;
 591         u16 autoneg_eee_reg;
 592         u32 link_reg;
 593         s32 status;
 594
 595         DEBUGFUNC("ixgbe_setup_eee_X550");
 596
 597         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 598         /* Enable or disable EEE per flag */
 599         if (enable_eee) {
 600                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 601
 602                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 603                         /* Advertise EEE capability */
 604                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 605                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 606
 607                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 608                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 609                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 610
 611                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 612                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 613                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 614                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 615                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 616                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 617                         if (status != IXGBE_SUCCESS)
 618                                 return status;
 619
 620                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 621                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 622
 623                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 624                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 625                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 626                         if (status != IXGBE_SUCCESS)
 627                                 return status;
 628                 }
 629         } else {
 630                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 631
 632                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 633                         /* Disable advertised EEE capability */
 634                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 635                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 636
 637                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 638                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 639                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 640
 641                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 642                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 643                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 644                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 645                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 646                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 647                         if (status != IXGBE_SUCCESS)
 648                                 return status;
 649
 650                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 651                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 652
 653                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 654                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 655                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 656                         if (status != IXGBE_SUCCESS)
 657                                 return status;
 658                 }
 659         }
 660         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 661
 662         return IXGBE_SUCCESS;
 663 }
 664
 665 /**
 666  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 667  * @hw: pointer to hardware structure
 668  * @enable: enable or disable source address pruning
 669  * @pool: Rx pool to set source address pruning for
 670  **/
 671 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 672                                            unsigned int pool)
 673 {
 674         u64 pfflp;
 675
 676         /* max rx pool is 63 */
 677         if (pool > 63)
 678                 return;
 679
 680         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 681         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 682
 683         if (enable)
 684                 pfflp |= (1ULL << pool);
 685         else
 686                 pfflp &= ~(1ULL << pool);
 687
 688         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 689         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 690 }
 691
 692 /**
 693  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 694  *  @hw: pointer to hardware structure
 695  *  @enable: enable or disable switch for Ethertype anti-spoofing
 696  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 697  *
 698  **/
 699 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 700                 bool enable, int vf)
 701 {
 702         int vf_target_reg = vf >> 3;
 703         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 704         u32 pfvfspoof;
 705
 706         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 707
 708         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 709         if (enable)
 710                 pfvfspoof |= (1 << vf_target_shift);
 711         else
 712                 pfvfspoof &= ~(1 << vf_target_shift);
 713
 714         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 715 }
 716
 717 /**
 718  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 719  *  device
 720  *  @hw: pointer to hardware structure
 721  *  @reg_addr: 32 bit PHY register to write
 722  *  @device_type: 3 bit device type
 723  *  @data: Data to write to the register
 724  **/
 725 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 726                             u32 device_type, u32 data)
 727 {
 728         u32 i, command, error;
 729
 730         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 731                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 732
 733         /* Write IOSF control register */
 734         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 735
 736         /* Write IOSF data register */
 737         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 738         /*
 739          * Check every 10 usec to see if the address cycle completed.
 740          * The SB IOSF BUSY bit will clear when the operation is
 741          * complete
 742          */
 743         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 744                 usec_delay(10);
 745
 746                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 747                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 748                         break;
 749         }
 750
 751         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 752                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 753                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 754                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 755                               "Failed to write, error %x\n", error);
 756                 return IXGBE_ERR_PHY;
 757         }
 758
 759         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 760                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
 761                 return IXGBE_ERR_PHY;
 762         }
 763
 764         return IXGBE_SUCCESS;
 765 }
 766
 767 /**
 768  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 769  *  device
 770  *  @hw: pointer to hardware structure
 771  *  @reg_addr: 32 bit PHY register to write
 772  *  @device_type: 3 bit device type
 773  *  @phy_data: Pointer to read data from the register
 774  **/
 775 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 776                            u32 device_type, u32 *data)
 777 {
 778         u32 i, command, error;
 779
 780         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 781                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 782
 783         /* Write IOSF control register */
 784         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 785
 786         /*
 787          * Check every 10 usec to see if the address cycle completed.
 788          * The SB IOSF BUSY bit will clear when the operation is
 789          * complete
 790          */
 791         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 792                 usec_delay(10);
 793
 794                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 795                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 796                         break;
 797         }
 798
 799         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 800                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 801                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 802                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 803                                 "Failed to read, error %x\n", error);
 804                 return IXGBE_ERR_PHY;
 805         }
 806
 807         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 808                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
 809                 return IXGBE_ERR_PHY;
 810         }
 811
 812         *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 813
 814         return IXGBE_SUCCESS;
 815 }
 816
 817 /**
 818  *  ixgbe_disable_mdd_X550
 819  *  @hw: pointer to hardware structure
 820  *
 821  *  Disable malicious driver detection
 822  **/
 823 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 824 {
 825         u32 reg;
 826
 827         DEBUGFUNC("ixgbe_disable_mdd_X550");
 828
 829         /* Disable MDD for TX DMA and interrupt */
 830         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 831         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 832         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 833
 834         /* Disable MDD for RX and interrupt */
 835         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 836         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 837         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 838 }
 839
 840 /**
 841  *  ixgbe_enable_mdd_X550
 842  *  @hw: pointer to hardware structure
 843  *
 844  *  Enable malicious driver detection
 845  **/
 846 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 847 {
 848         u32 reg;
 849
 850         DEBUGFUNC("ixgbe_enable_mdd_X550");
 851
 852         /* Enable MDD for TX DMA and interrupt */
 853         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 854         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 855         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 856
 857         /* Enable MDD for RX and interrupt */
 858         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 859         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 860         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 861 }
 862
 863 /**
 864  *  ixgbe_restore_mdd_vf_X550
 865  *  @hw: pointer to hardware structure
 866  *  @vf: vf index
 867  *
 868  *  Restore VF that was disabled during malicious driver detection event
 869  **/
 870 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 871 {
 872         u32 idx, reg, num_qs, start_q, bitmask;
 873
 874         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 875
 876         /* Map VF to queues */
 877         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 878         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 879         case IXGBE_MRQC_VMDQRT8TCEN:
 880                 num_qs = 8;  /* 16 VFs / pools */
 881                 bitmask = 0x000000FF;
 882                 break;
 883         case IXGBE_MRQC_VMDQRSS32EN:
 884         case IXGBE_MRQC_VMDQRT4TCEN:
 885                 num_qs = 4;  /* 32 VFs / pools */
 886                 bitmask = 0x0000000F;
 887                 break;
 888         default:            /* 64 VFs / pools */
 889                 num_qs = 2;
 890                 bitmask = 0x00000003;
 891                 break;
 892         }
 893         start_q = vf * num_qs;
 894
 895         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 896         idx = start_q / 32;
 897         reg = 0;
 898         reg |= (bitmask << (start_q % 32));
 899         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 900         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 901 }
 902
 903 /**
 904  *  ixgbe_mdd_event_X550
 905  *  @hw: pointer to hardware structure
 906  *  @vf_bitmap: vf bitmap of malicious vfs
 907  *
 908  *  Handle malicious driver detection event.
 909  **/
 910 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 911 {
 912         u32 wqbr;
 913         u32 i, j, reg, q, shift, vf, idx;
 914
 915         DEBUGFUNC("ixgbe_mdd_event_X550");
 916
 917         /* figure out pool size for mapping to vf's */
 918         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 919         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 920         case IXGBE_MRQC_VMDQRT8TCEN:
 921                 shift = 3;  /* 16 VFs / pools */
 922                 break;
 923         case IXGBE_MRQC_VMDQRSS32EN:
 924         case IXGBE_MRQC_VMDQRT4TCEN:
 925                 shift = 2;  /* 32 VFs / pools */
 926                 break;
 927         default:
 928                 shift = 1;  /* 64 VFs / pools */
 929                 break;
 930         }
 931
 932         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
 933         for (i = 0; i < 4; i++) {
 934                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
 935                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
 936
 937                 if (!wqbr)
 938                         continue;
 939
 940                 /* Get malicious queue */
 941                 for (j = 0; j < 32 && wqbr; j++) {
 942
 943                         if (!(wqbr & (1 << j)))
 944                                 continue;
 945
 946                         /* Get queue from bitmask */
 947                         q = j + (i * 32);
 948
 949                         /* Map queue to vf */
 950                         vf = (q >> shift);
 951
 952                         /* Set vf bit in vf_bitmap */
 953                         idx = vf / 32;
 954                         vf_bitmap[idx] |= (1 << (vf % 32));
 955                         wqbr &= ~(1 << j);
 956                 }
 957         }
 958 }
 959
 960 /**
 961  *  ixgbe_get_media_type_X550em - Get media type
 962  *  @hw: pointer to hardware structure
 963  *
 964  *  Returns the media type (fiber, copper, backplane)
 965  */
 966 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
 967 {
 968         enum ixgbe_media_type media_type;
 969
 970         DEBUGFUNC("ixgbe_get_media_type_X550em");
 971
 972         /* Detect if there is a copper PHY attached. */
 973         switch (hw->device_id) {
 974         case IXGBE_DEV_ID_X550EM_X_KR:
 975         case IXGBE_DEV_ID_X550EM_X_KX4:
 976                 media_type = ixgbe_media_type_backplane;
 977                 break;
 978         case IXGBE_DEV_ID_X550EM_X_SFP:
 979                 media_type = ixgbe_media_type_fiber;
 980                 break;
 981         case IXGBE_DEV_ID_X550EM_X_1G_T:
 982         case IXGBE_DEV_ID_X550EM_X_10G_T:
 983                 media_type = ixgbe_media_type_copper;
 984                 break;
 985         default:
 986                 media_type = ixgbe_media_type_unknown;
 987                 break;
 988         }
 989         return media_type;
 990 }
 991
 992 /**
 993  *  ixgbe_setup_sfp_modules_X550em - Setup SFP module
 994  *  @hw: pointer to hardware structure
 995  */
 996 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
 997 {
 998         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
 999
1000         ixgbe_init_mac_link_ops_X550em(hw);
1001         hw->phy.ops.reset = NULL;
1002
1003         return IXGBE_SUCCESS;
1004 }
1005
1006 /**
1007  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1008  *  @hw: pointer to hardware structure
1009  */
1010 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1011 {
1012         struct ixgbe_mac_info *mac = &hw->mac;
1013
1014         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1015
1016          switch (hw->mac.ops.get_media_type(hw)) {
1017          case ixgbe_media_type_fiber:
1018                 /* CS4227 does not support autoneg, so disable the laser control
1019                  * functions for SFP+ fiber
1020                  */
1021                 mac->ops.disable_tx_laser = NULL;
1022                 mac->ops.enable_tx_laser = NULL;
1023                 mac->ops.flap_tx_laser = NULL;
1024                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1025                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1026                 mac->ops.set_rate_select_speed =
1027                                         ixgbe_set_soft_rate_select_speed;
1028                 break;
1029         case ixgbe_media_type_copper:
1030                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1031                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1032                 break;
1033         default:
1034                 break;
1035          }
1036 }
1037
1038 /**
1039  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1040  *  @hw: pointer to hardware structure
1041  *  @speed: pointer to link speed
1042  *  @autoneg: true when autoneg or autotry is enabled
1043  */
1044 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1045                                        ixgbe_link_speed *speed,
1046                                        bool *autoneg)
1047 {
1048         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1049
1050         /* SFP */
1051         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1052
1053                 /* CS4227 SFP must not enable auto-negotiation */
1054                 *autoneg = false;
1055
1056                 /* Check if 1G SFP module. */
1057                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1058                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1059                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1060                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1061                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1062                         return IXGBE_SUCCESS;
1063                 }
1064
1065                 /* Link capabilities are based on SFP */
1066                 if (hw->phy.multispeed_fiber)
1067                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1068                                  IXGBE_LINK_SPEED_1GB_FULL;
1069                 else
1070                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1071         } else {
1072                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1073                          IXGBE_LINK_SPEED_1GB_FULL;
1074                 *autoneg = true;
1075         }
1076
1077         return IXGBE_SUCCESS;
1078 }
1079
1080 /**
1081  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1082  * @hw: pointer to hardware structure
1083  * @lsc: pointer to boolean flag which indicates whether external Base T
1084  *       PHY interrupt is lsc
1085  *
1086  * Determime if external Base T PHY interrupt cause is high temperature
1087  * failure alarm or link status change.
1088  *
1089  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1090  * failure alarm, else return PHY access status.
1091  */
1092 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1093 {
1094         u32 status;
1095         u16 reg;
1096
1097         *lsc = false;
1098
1099         /* Vendor alarm triggered */
1100         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1101                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1102                                       &reg);
1103
1104         if (status != IXGBE_SUCCESS ||
1105             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1106                 return status;
1107
1108         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1109         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1110                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1111                                       &reg);
1112
1113         if (status != IXGBE_SUCCESS ||
1114             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1115             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1116                 return status;
1117
1118         /* High temperature failure alarm triggered */
1119         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1120                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1121                                       &reg);
1122
1123         if (status != IXGBE_SUCCESS)
1124                 return status;
1125
1126         /* If high temperature failure, then return over temp error and exit */
1127         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL)
1128                 return IXGBE_ERR_OVERTEMP;
1129
1130         /* Vendor alarm 2 triggered */
1131         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1132                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1133
1134         if (status != IXGBE_SUCCESS ||
1135             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1136                 return status;
1137
1138         /* link connect/disconnect event occurred */
1139         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1140                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1141
1142         if (status != IXGBE_SUCCESS)
1143                 return status;
1144
1145         /* Indicate LSC */
1146         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1147                 *lsc = true;
1148
1149         return IXGBE_SUCCESS;
1150 }
1151
1152 /**
1153  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1154  * @hw: pointer to hardware structure
1155  *
1156  * Enable link status change and temperature failure alarm for the external
1157  * Base T PHY
1158  *
1159  * Returns PHY access status
1160  */
1161 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1162 {
1163         u32 status;
1164         u16 reg;
1165         bool lsc;
1166
1167         /* Clear interrupt flags */
1168         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1169
1170         /* Enable link status change alarm */
1171         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1172                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1173
1174         if (status != IXGBE_SUCCESS)
1175                 return status;
1176
1177         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1178
1179         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1180                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1181
1182         if (status != IXGBE_SUCCESS)
1183                 return status;
1184
1185         /* Enables high temperature failure alarm */
1186         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1187                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1188                                       &reg);
1189
1190         if (status != IXGBE_SUCCESS)
1191                 return status;
1192
1193         reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1194
1195         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1196                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1197                                        reg);
1198
1199         if (status != IXGBE_SUCCESS)
1200                 return status;
1201
1202         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1203         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1204                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1205                                       &reg);
1206
1207         if (status != IXGBE_SUCCESS)
1208                 return status;
1209
1210         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1211                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1212
1213         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1214                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1215                                        reg);
1216
1217         if (status != IXGBE_SUCCESS)
1218                 return status;
1219
1220         /* Enable chip-wide vendor alarm */
1221         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1222                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1223                                       &reg);
1224
1225         if (status != IXGBE_SUCCESS)
1226                 return status;
1227
1228         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1229
1230         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1231                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1232                                        reg);
1233
1234         return status;
1235 }
1236
1237 /**
1238  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1239  *  @hw: pointer to hardware structure
1240  *
1241  *  Initialize any function pointers that were not able to be
1242  *  set during init_shared_code because the PHY/SFP type was
1243  *  not known.  Perform the SFP init if necessary.
1244  */
1245 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1246 {
1247         struct ixgbe_phy_info *phy = &hw->phy;
1248         s32 ret_val;
1249
1250         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1251
1252         hw->mac.ops.set_lan_id(hw);
1253
1254         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1255                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1256                 ixgbe_setup_mux_ctl(hw);
1257         }
1258
1259         /* Identify the PHY or SFP module */
1260         ret_val = phy->ops.identify(hw);
1261         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1262                 return ret_val;
1263
1264         /* Setup function pointers based on detected hardware */
1265         ixgbe_init_mac_link_ops_X550em(hw);
1266         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1267                 phy->ops.reset = NULL;
1268
1269         /* Set functions pointers based on phy type */
1270         switch (hw->phy.type) {
1271         case ixgbe_phy_x550em_kx4:
1272                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1273                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1274                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1275                 break;
1276         case ixgbe_phy_x550em_kr:
1277                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1278                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1279                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1280                 break;
1281         case ixgbe_phy_x550em_ext_t:
1282                 phy->ops.setup_internal_link =
1283                                          ixgbe_setup_internal_phy_t_x550em;
1284                 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1285                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1286                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1287                 break;
1288         default:
1289                 break;
1290         }
1291         return ret_val;
1292 }
1293
1294 /**
1295  *  ixgbe_reset_hw_X550em - Perform hardware reset
1296  *  @hw: pointer to hardware structure
1297  *
1298  *  Resets the hardware by resetting the transmit and receive units, masks
1299  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1300  *  reset.
1301  */
1302 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1303 {
1304         ixgbe_link_speed link_speed;
1305         s32 status;
1306         u32 ctrl = 0;
1307         u32 i;
1308         bool link_up = false;
1309
1310         DEBUGFUNC("ixgbe_reset_hw_X550em");
1311
1312         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1313         status = hw->mac.ops.stop_adapter(hw);
1314         if (status != IXGBE_SUCCESS)
1315                 return status;
1316
1317         /* flush pending Tx transactions */
1318         ixgbe_clear_tx_pending(hw);
1319
1320         /* PHY ops must be identified and initialized prior to reset */
1321
1322         /* Identify PHY and related function pointers */
1323         status = hw->phy.ops.init(hw);
1324
1325         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1326                 return status;
1327
1328         /* start the external PHY */
1329         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1330                 status = ixgbe_init_ext_t_x550em(hw);
1331                 if (status)
1332                         return status;
1333         }
1334
1335         /* Setup SFP module if there is one present. */
1336         if (hw->phy.sfp_setup_needed) {
1337                 status = hw->mac.ops.setup_sfp(hw);
1338                 hw->phy.sfp_setup_needed = false;
1339         }
1340
1341         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1342                 return status;
1343
1344         /* Reset PHY */
1345         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1346                 hw->phy.ops.reset(hw);
1347
1348 mac_reset_top:
1349         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1350          * If link reset is used when link is up, it might reset the PHY when
1351          * mng is using it.  If link is down or the flag to force full link
1352          * reset is set, then perform link reset.
1353          */
1354         ctrl = IXGBE_CTRL_LNK_RST;
1355         if (!hw->force_full_reset) {
1356                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1357                 if (link_up)
1358                         ctrl = IXGBE_CTRL_RST;
1359         }
1360
1361         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1362         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1363         IXGBE_WRITE_FLUSH(hw);
1364
1365         /* Poll for reset bit to self-clear meaning reset is complete */
1366         for (i = 0; i < 10; i++) {
1367                 usec_delay(1);
1368                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1369                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1370                         break;
1371         }
1372
1373         if (ctrl & IXGBE_CTRL_RST_MASK) {
1374                 status = IXGBE_ERR_RESET_FAILED;
1375                 DEBUGOUT("Reset polling failed to complete.\n");
1376         }
1377
1378         msec_delay(50);
1379
1380         /* Double resets are required for recovery from certain error
1381          * conditions.  Between resets, it is necessary to stall to
1382          * allow time for any pending HW events to complete.
1383          */
1384         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1385                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1386                 goto mac_reset_top;
1387         }
1388
1389         /* Store the permanent mac address */
1390         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1391
1392         /* Store MAC address from RAR0, clear receive address registers, and
1393          * clear the multicast table.  Also reset num_rar_entries to 128,
1394          * since we modify this value when programming the SAN MAC address.
1395          */
1396         hw->mac.num_rar_entries = 128;
1397         hw->mac.ops.init_rx_addrs(hw);
1398
1399
1400         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1401                 ixgbe_setup_mux_ctl(hw);
1402
1403         return status;
1404 }
1405
1406 /**
1407  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1408  * @hw: pointer to hardware structure
1409  */
1410 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1411 {
1412         u32 status;
1413         u16 reg;
1414
1415         status = hw->phy.ops.read_reg(hw,
1416                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1417                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1418                                       &reg);
1419
1420         if (status != IXGBE_SUCCESS)
1421                 return status;
1422
1423         /* If PHY FW reset completed bit is set then this is the first
1424          * SW instance after a power on so the PHY FW must be un-stalled.
1425          */
1426         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1427                 status = hw->phy.ops.read_reg(hw,
1428                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1429                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1430                                         &reg);
1431
1432                 if (status != IXGBE_SUCCESS)
1433                         return status;
1434
1435                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1436
1437                 status = hw->phy.ops.write_reg(hw,
1438                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1439                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1440                                         reg);
1441
1442                 if (status != IXGBE_SUCCESS)
1443                         return status;
1444         }
1445
1446         return status;
1447 }
1448
1449 /**
1450  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1451  *  @hw: pointer to hardware structure
1452  *
1453  *  Configures the integrated KR PHY.
1454  **/
1455 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1456 {
1457         s32 status;
1458         u32 reg_val;
1459
1460         status = ixgbe_read_iosf_sb_reg_x550(hw,
1461                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1462                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1463         if (status)
1464                 return status;
1465
1466         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1467         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1468                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1469         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1470                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1471
1472         /* Advertise 10G support. */
1473         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1474                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1475
1476         /* Advertise 1G support. */
1477         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1478                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1479
1480         /* Restart auto-negotiation. */
1481         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1482         status = ixgbe_write_iosf_sb_reg_x550(hw,
1483                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1484                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1485
1486         return status;
1487 }
1488
1489 /**
1490  *  ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1491  *  @hw: pointer to hardware structure
1492  *
1493  *  Configures the integrated KX4 PHY.
1494  **/
1495 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1496 {
1497         s32 status;
1498         u32 reg_val;
1499
1500         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1501                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, &reg_val);
1502         if (status)
1503                 return status;
1504
1505         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1506                         IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1507
1508         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1509
1510         /* Advertise 10G support. */
1511         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1512                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1513
1514         /* Advertise 1G support. */
1515         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1516                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1517
1518         /* Restart auto-negotiation. */
1519         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1520         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1521                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, reg_val);
1522
1523         return status;
1524 }
1525
1526 /**
1527  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1528  *  @hw: pointer to hardware structure
1529  *  @speed: the link speed to force
1530  *
1531  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1532  *  internal and external PHY at a specific speed, without autonegotiation.
1533  **/
1534 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1535 {
1536         s32 status;
1537         u32 reg_val;
1538
1539         /* Disable AN and force speed to 10G Serial. */
1540         status = ixgbe_read_iosf_sb_reg_x550(hw,
1541                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1542                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1543         if (status != IXGBE_SUCCESS)
1544                 return status;
1545
1546         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1547         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1548
1549         /* Select forced link speed for internal PHY. */
1550         switch (*speed) {
1551         case IXGBE_LINK_SPEED_10GB_FULL:
1552                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1553                 break;
1554         case IXGBE_LINK_SPEED_1GB_FULL:
1555                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1556                 break;
1557         default:
1558                 /* Other link speeds are not supported by internal KR PHY. */
1559                 return IXGBE_ERR_LINK_SETUP;
1560         }
1561
1562         status = ixgbe_write_iosf_sb_reg_x550(hw,
1563                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1564                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1565         if (status != IXGBE_SUCCESS)
1566                 return status;
1567
1568         /* Disable training protocol FSM. */
1569         status = ixgbe_read_iosf_sb_reg_x550(hw,
1570                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1571                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1572         if (status != IXGBE_SUCCESS)
1573                 return status;
1574         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1575         status = ixgbe_write_iosf_sb_reg_x550(hw,
1576                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1577                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1578         if (status != IXGBE_SUCCESS)
1579                 return status;
1580
1581         /* Disable Flex from training TXFFE. */
1582         status = ixgbe_read_iosf_sb_reg_x550(hw,
1583                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1584                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1585         if (status != IXGBE_SUCCESS)
1586                 return status;
1587         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1588         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1589         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1590         status = ixgbe_write_iosf_sb_reg_x550(hw,
1591                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1592                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1593         if (status != IXGBE_SUCCESS)
1594                 return status;
1595         status = ixgbe_read_iosf_sb_reg_x550(hw,
1596                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1597                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1598         if (status != IXGBE_SUCCESS)
1599                 return status;
1600         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1601         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1602         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1603         status = ixgbe_write_iosf_sb_reg_x550(hw,
1604                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1605                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1606         if (status != IXGBE_SUCCESS)
1607                 return status;
1608
1609         /* Enable override for coefficients. */
1610         status = ixgbe_read_iosf_sb_reg_x550(hw,
1611                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1612                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1613         if (status != IXGBE_SUCCESS)
1614                 return status;
1615         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1616         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1617         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1618         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1619         status = ixgbe_write_iosf_sb_reg_x550(hw,
1620                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1621                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1622         if (status != IXGBE_SUCCESS)
1623                 return status;
1624
1625         /* Toggle port SW reset by AN reset. */
1626         status = ixgbe_read_iosf_sb_reg_x550(hw,
1627                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1628                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1629         if (status != IXGBE_SUCCESS)
1630                 return status;
1631         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1632         status = ixgbe_write_iosf_sb_reg_x550(hw,
1633                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1634                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1635
1636         return status;
1637 }
1638
1639 /**
1640  *  ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1641  *  @hw: pointer to hardware structure
1642  *
1643  *  Configures the integrated KR PHY for SFP support.
1644  **/
1645 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1646                                     ixgbe_link_speed speed,
1647                                     bool autoneg_wait_to_complete)
1648 {
1649         s32 ret_val;
1650         u16 reg_slice, reg_val;
1651         bool setup_linear;
1652         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1653
1654         /* Configure the external PHY. */
1655         switch (hw->phy.sfp_type) {
1656         case ixgbe_sfp_type_da_cu_core0:
1657         case ixgbe_sfp_type_da_cu_core1:
1658                 setup_linear = true;
1659                 break;
1660         case ixgbe_sfp_type_srlr_core0:
1661         case ixgbe_sfp_type_srlr_core1:
1662         case ixgbe_sfp_type_da_act_lmt_core0:
1663         case ixgbe_sfp_type_da_act_lmt_core1:
1664         case ixgbe_sfp_type_1g_sx_core0:
1665         case ixgbe_sfp_type_1g_sx_core1:
1666 #ifdef SUPPORT_1000BASE_LX
1667         case ixgbe_sfp_type_1g_lx_core0:
1668         case ixgbe_sfp_type_1g_lx_core1:
1669 #endif /* SUPPORT_1000BASE_LX */
1670                 setup_linear = false;
1671                 break;
1672         default:
1673                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1674         }
1675
1676         /* Configure CS4227 for connection rate. */
1677         reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1678         reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1679         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1680                                            reg_val);
1681
1682         /* Configure CS4227 for connection type. */
1683         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1684         if (setup_linear)
1685                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1686         else
1687                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1688         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1689                                            reg_val);
1690
1691         reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1692         reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1693         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1694                                            reg_val);
1695
1696         /* Configure CS4227 for connection type. */
1697         reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1698         if (setup_linear)
1699                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1700         else
1701                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1702         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1703                                            reg_val);
1704
1705         /* Configure the internal PHY. */
1706         ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1707
1708         return ret_val;
1709 }
1710
1711 /**
1712  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1713  * @hw: point to hardware structure
1714  *
1715  * Configures the link between the integrated KR PHY and the external X557 PHY
1716  * The driver will call this function when it gets a link status change
1717  * interrupt from the X557 PHY. This function configures the link speed
1718  * between the PHYs to match the link speed of the BASE-T link.
1719  *
1720  * A return of a non-zero value indicates an error, and the base driver should
1721  * not report link up.
1722  */
1723 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1724 {
1725         u32 status;
1726         u16 autoneg_status, speed;
1727         ixgbe_link_speed force_speed;
1728
1729         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1730                 return IXGBE_ERR_CONFIG;
1731
1732         /* read this twice back to back to indicate current status */
1733         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1734                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1735                                       &autoneg_status);
1736         if (status != IXGBE_SUCCESS)
1737                 return status;
1738
1739         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1740                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1741                                       &autoneg_status);
1742         if (status != IXGBE_SUCCESS)
1743                 return status;
1744
1745         /* If link is not up, then there is no setup necessary so return  */
1746         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1747                 return IXGBE_SUCCESS;
1748
1749         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1750                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1751                                       &speed);
1752
1753         /* clear everything but the speed and duplex bits */
1754         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1755
1756         switch (speed) {
1757         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1758                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1759                 break;
1760         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1761                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1762                 break;
1763         default:
1764                 /* Internal PHY does not support anything else */
1765                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1766         }
1767
1768         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1769 }
1770
1771 /**
1772  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1773  *  @hw: pointer to hardware structure
1774  *
1775  *  Configures the integrated KR PHY to use internal loopback mode.
1776  **/
1777 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1778 {
1779         s32 status;
1780         u32 reg_val;
1781
1782         /* Disable AN and force speed to 10G Serial. */
1783         status = ixgbe_read_iosf_sb_reg_x550(hw,
1784                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1785                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1786         if (status != IXGBE_SUCCESS)
1787                 return status;
1788         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1789         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1790         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1791         status = ixgbe_write_iosf_sb_reg_x550(hw,
1792                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1793                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1794         if (status != IXGBE_SUCCESS)
1795                 return status;
1796
1797         /* Set near-end loopback clocks. */
1798         status = ixgbe_read_iosf_sb_reg_x550(hw,
1799                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1800                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1801         if (status != IXGBE_SUCCESS)
1802                 return status;
1803         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1804         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1805         status = ixgbe_write_iosf_sb_reg_x550(hw,
1806                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1807                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1808         if (status != IXGBE_SUCCESS)
1809                 return status;
1810
1811         /* Set loopback enable. */
1812         status = ixgbe_read_iosf_sb_reg_x550(hw,
1813                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1814                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1815         if (status != IXGBE_SUCCESS)
1816                 return status;
1817         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1818         status = ixgbe_write_iosf_sb_reg_x550(hw,
1819                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1820                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1821         if (status != IXGBE_SUCCESS)
1822                 return status;
1823
1824         /* Training bypass. */
1825         status = ixgbe_read_iosf_sb_reg_x550(hw,
1826                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1827                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1828         if (status != IXGBE_SUCCESS)
1829                 return status;
1830         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1831         status = ixgbe_write_iosf_sb_reg_x550(hw,
1832                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1833                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1834
1835         return status;
1836 }
1837
1838 /**
1839  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1840  *  assuming that the semaphore is already obtained.
1841  *  @hw: pointer to hardware structure
1842  *  @offset: offset of  word in the EEPROM to read
1843  *  @data: word read from the EEPROM
1844  *
1845  *  Reads a 16 bit word from the EEPROM using the hostif.
1846  **/
1847 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1848                                    u16 *data)
1849 {
1850         s32 status;
1851         struct ixgbe_hic_read_shadow_ram buffer;
1852
1853         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1854         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1855         buffer.hdr.req.buf_lenh = 0;
1856         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1857         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1858
1859         /* convert offset from words to bytes */
1860         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1861         /* one word */
1862         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1863
1864         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1865                                               sizeof(buffer),
1866                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1867
1868         if (status)
1869                 return status;
1870
1871         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1872                                           FW_NVM_DATA_OFFSET);
1873
1874         return 0;
1875 }
1876
1877 /**
1878  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1879  *  @hw: pointer to hardware structure
1880  *  @offset: offset of  word in the EEPROM to read
1881  *  @data: word read from the EEPROM
1882  *
1883  *  Reads a 16 bit word from the EEPROM using the hostif.
1884  **/
1885 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1886                               u16 *data)
1887 {
1888         s32 status = IXGBE_SUCCESS;
1889
1890         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1891
1892         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1893             IXGBE_SUCCESS) {
1894                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1895                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1896         } else {
1897                 status = IXGBE_ERR_SWFW_SYNC;
1898         }
1899
1900         return status;
1901 }
1902
1903 /**
1904  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1905  *  @hw: pointer to hardware structure
1906  *  @offset: offset of  word in the EEPROM to read
1907  *  @words: number of words
1908  *  @data: word(s) read from the EEPROM
1909  *
1910  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
1911  **/
1912 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1913                                      u16 offset, u16 words, u16 *data)
1914 {
1915         struct ixgbe_hic_read_shadow_ram buffer;
1916         u32 current_word = 0;
1917         u16 words_to_read;
1918         s32 status;
1919         u32 i;
1920
1921         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1922
1923         /* Take semaphore for the entire operation. */
1924         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1925         if (status) {
1926                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1927                 return status;
1928         }
1929         while (words) {
1930                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1931                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1932                 else
1933                         words_to_read = words;
1934
1935                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1936                 buffer.hdr.req.buf_lenh = 0;
1937                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1938                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1939
1940                 /* convert offset from words to bytes */
1941                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1942                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1943
1944                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1945                                                       sizeof(buffer),
1946                                                       IXGBE_HI_COMMAND_TIMEOUT,
1947                                                       false);
1948
1949                 if (status) {
1950                         DEBUGOUT("Host interface command failed\n");
1951                         goto out;
1952                 }
1953
1954                 for (i = 0; i < words_to_read; i++) {
1955                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1956                                   2 * i;
1957                         u32 value = IXGBE_READ_REG(hw, reg);
1958
1959                         data[current_word] = (u16)(value & 0xffff);
1960                         current_word++;
1961                         i++;
1962                         if (i < words_to_read) {
1963                                 value >>= 16;
1964                                 data[current_word] = (u16)(value & 0xffff);
1965                                 current_word++;
1966                         }
1967                 }
1968                 words -= words_to_read;
1969         }
1970
1971 out:
1972         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1973         return status;
1974 }
1975
1976 /**
1977  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1978  *  @hw: pointer to hardware structure
1979  *  @offset: offset of  word in the EEPROM to write
1980  *  @data: word write to the EEPROM
1981  *
1982  *  Write a 16 bit word to the EEPROM using the hostif.
1983  **/
1984 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1985                                     u16 data)
1986 {
1987         s32 status;
1988         struct ixgbe_hic_write_shadow_ram buffer;
1989
1990         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1991
1992         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1993         buffer.hdr.req.buf_lenh = 0;
1994         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1995         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1996
1997          /* one word */
1998         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1999         buffer.data = data;
2000         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2001
2002         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2003                                               sizeof(buffer),
2004                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2005
2006         return status;
2007 }
2008
2009 /**
2010  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2011  *  @hw: pointer to hardware structure
2012  *  @offset: offset of  word in the EEPROM to write
2013  *  @data: word write to the EEPROM
2014  *
2015  *  Write a 16 bit word to the EEPROM using the hostif.
2016  **/
2017 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2018                                u16 data)
2019 {
2020         s32 status = IXGBE_SUCCESS;
2021
2022         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2023
2024         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2025             IXGBE_SUCCESS) {
2026                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2027                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2028         } else {
2029                 DEBUGOUT("write ee hostif failed to get semaphore");
2030                 status = IXGBE_ERR_SWFW_SYNC;
2031         }
2032
2033         return status;
2034 }
2035
2036 /**
2037  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2038  *  @hw: pointer to hardware structure
2039  *  @offset: offset of  word in the EEPROM to write
2040  *  @words: number of words
2041  *  @data: word(s) write to the EEPROM
2042  *
2043  *  Write a 16 bit word(s) to the EEPROM using the hostif.
2044  **/
2045 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2046                                       u16 offset, u16 words, u16 *data)
2047 {
2048         s32 status = IXGBE_SUCCESS;
2049         u32 i = 0;
2050
2051         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2052
2053         /* Take semaphore for the entire operation. */
2054         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2055         if (status != IXGBE_SUCCESS) {
2056                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2057                 goto out;
2058         }
2059
2060         for (i = 0; i < words; i++) {
2061                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2062                                                          data[i]);
2063
2064                 if (status != IXGBE_SUCCESS) {
2065                         DEBUGOUT("Eeprom buffered write failed\n");
2066                         break;
2067                 }
2068         }
2069
2070         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2071 out:
2072
2073         return status;
2074 }
2075
2076 /**
2077  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2078  * @hw: pointer to hardware structure
2079  * @ptr: pointer offset in eeprom
2080  * @size: size of section pointed by ptr, if 0 first word will be used as size
2081  * @csum: address of checksum to update
2082  *
2083  * Returns error status for any failure
2084  */
2085 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2086                                    u16 size, u16 *csum, u16 *buffer,
2087                                    u32 buffer_size)
2088 {
2089         u16 buf[256];
2090         s32 status;
2091         u16 length, bufsz, i, start;
2092         u16 *local_buffer;
2093
2094         bufsz = sizeof(buf) / sizeof(buf[0]);
2095
2096         /* Read a chunk at the pointer location */
2097         if (!buffer) {
2098                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2099                 if (status) {
2100                         DEBUGOUT("Failed to read EEPROM image\n");
2101                         return status;
2102                 }
2103                 local_buffer = buf;
2104         } else {
2105                 if (buffer_size < ptr)
2106                         return  IXGBE_ERR_PARAM;
2107                 local_buffer = &buffer[ptr];
2108         }
2109
2110         if (size) {
2111                 start = 0;
2112                 length = size;
2113         } else {
2114                 start = 1;
2115                 length = local_buffer[0];
2116
2117                 /* Skip pointer section if length is invalid. */
2118                 if (length == 0xFFFF || length == 0 ||
2119                     (ptr + length) >= hw->eeprom.word_size)
2120                         return IXGBE_SUCCESS;
2121         }
2122
2123         if (buffer && ((u32)start + (u32)length > buffer_size))
2124                 return IXGBE_ERR_PARAM;
2125
2126         for (i = start; length; i++, length--) {
2127                 if (i == bufsz && !buffer) {
2128                         ptr += bufsz;
2129                         i = 0;
2130                         if (length < bufsz)
2131                                 bufsz = length;
2132
2133                         /* Read a chunk at the pointer location */
2134                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2135                                                                   bufsz, buf);
2136                         if (status) {
2137                                 DEBUGOUT("Failed to read EEPROM image\n");
2138                                 return status;
2139                         }
2140                 }
2141                 *csum += local_buffer[i];
2142         }
2143         return IXGBE_SUCCESS;
2144 }
2145
2146 /**
2147  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2148  *  @hw: pointer to hardware structure
2149  *  @buffer: pointer to buffer containing calculated checksum
2150  *  @buffer_size: size of buffer
2151  *
2152  *  Returns a negative error code on error, or the 16-bit checksum
2153  **/
2154 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2155 {
2156         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2157         u16 *local_buffer;
2158         s32 status;
2159         u16 checksum = 0;
2160         u16 pointer, i, size;
2161
2162         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2163
2164         hw->eeprom.ops.init_params(hw);
2165
2166         if (!buffer) {
2167                 /* Read pointer area */
2168                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2169                                                      IXGBE_EEPROM_LAST_WORD + 1,
2170                                                      eeprom_ptrs);
2171                 if (status) {
2172                         DEBUGOUT("Failed to read EEPROM image\n");
2173                         return status;
2174                 }
2175                 local_buffer = eeprom_ptrs;
2176         } else {
2177                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2178                         return IXGBE_ERR_PARAM;
2179                 local_buffer = buffer;
2180         }
2181
2182         /*
2183          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2184          * checksum word itself
2185          */
2186         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2187                 if (i != IXGBE_EEPROM_CHECKSUM)
2188                         checksum += local_buffer[i];
2189
2190         /*
2191          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2192          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2193          */
2194         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2195                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2196                         continue;
2197
2198                 pointer = local_buffer[i];
2199
2200                 /* Skip pointer section if the pointer is invalid. */
2201                 if (pointer == 0xFFFF || pointer == 0 ||
2202                     pointer >= hw->eeprom.word_size)
2203                         continue;
2204
2205                 switch (i) {
2206                 case IXGBE_PCIE_GENERAL_PTR:
2207                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2208                         break;
2209                 case IXGBE_PCIE_CONFIG0_PTR:
2210                 case IXGBE_PCIE_CONFIG1_PTR:
2211                         size = IXGBE_PCIE_CONFIG_SIZE;
2212                         break;
2213                 default:
2214                         size = 0;
2215                         break;
2216                 }
2217
2218                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2219                                                 buffer, buffer_size);
2220                 if (status)
2221                         return status;
2222         }
2223
2224         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2225
2226         return (s32)checksum;
2227 }
2228
2229 /**
2230  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2231  *  @hw: pointer to hardware structure
2232  *
2233  *  Returns a negative error code on error, or the 16-bit checksum
2234  **/
2235 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2236 {
2237         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2238 }
2239
2240 /**
2241  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2242  *  @hw: pointer to hardware structure
2243  *  @checksum_val: calculated checksum
2244  *
2245  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2246  *  caller does not need checksum_val, the value can be NULL.
2247  **/
2248 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2249 {
2250         s32 status;
2251         u16 checksum;
2252         u16 read_checksum = 0;
2253
2254         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2255
2256         /* Read the first word from the EEPROM. If this times out or fails, do
2257          * not continue or we could be in for a very long wait while every
2258          * EEPROM read fails
2259          */
2260         status = hw->eeprom.ops.read(hw, 0, &checksum);
2261         if (status) {
2262                 DEBUGOUT("EEPROM read failed\n");
2263                 return status;
2264         }
2265
2266         status = hw->eeprom.ops.calc_checksum(hw);
2267         if (status < 0)
2268                 return status;
2269
2270         checksum = (u16)(status & 0xffff);
2271
2272         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2273                                            &read_checksum);
2274         if (status)
2275                 return status;
2276
2277         /* Verify read checksum from EEPROM is the same as
2278          * calculated checksum
2279          */
2280         if (read_checksum != checksum) {
2281                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2282                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2283                              "Invalid EEPROM checksum");
2284         }
2285
2286         /* If the user cares, return the calculated checksum */
2287         if (checksum_val)
2288                 *checksum_val = checksum;
2289
2290         return status;
2291 }
2292
2293 /**
2294  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2295  * @hw: pointer to hardware structure
2296  *
2297  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2298  * checksum and updates the EEPROM and instructs the hardware to update
2299  * the flash.
2300  **/
2301 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2302 {
2303         s32 status;
2304         u16 checksum = 0;
2305
2306         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2307
2308         /* Read the first word from the EEPROM. If this times out or fails, do
2309          * not continue or we could be in for a very long wait while every
2310          * EEPROM read fails
2311          */
2312         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2313         if (status) {
2314                 DEBUGOUT("EEPROM read failed\n");
2315                 return status;
2316         }
2317
2318         status = ixgbe_calc_eeprom_checksum_X550(hw);
2319         if (status < 0)
2320                 return status;
2321
2322         checksum = (u16)(status & 0xffff);
2323
2324         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2325                                             checksum);
2326         if (status)
2327                 return status;
2328
2329         status = ixgbe_update_flash_X550(hw);
2330
2331         return status;
2332 }
2333
2334 /**
2335  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2336  *  @hw: pointer to hardware structure
2337  *
2338  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2339  **/
2340 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2341 {
2342         s32 status = IXGBE_SUCCESS;
2343         union ixgbe_hic_hdr2 buffer;
2344
2345         DEBUGFUNC("ixgbe_update_flash_X550");
2346
2347         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2348         buffer.req.buf_lenh = 0;
2349         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2350         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2351
2352         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2353                                               sizeof(buffer),
2354                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2355
2356         return status;
2357 }
2358
2359 /**
2360  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2361  *  @hw: pointer to hardware structure
2362  *
2363  *  Determines physical layer capabilities of the current configuration.
2364  **/
2365 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2366 {
2367         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2368         u16 ext_ability = 0;
2369
2370         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2371
2372         hw->phy.ops.identify(hw);
2373
2374         switch (hw->phy.type) {
2375         case ixgbe_phy_x550em_kr:
2376                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2377                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2378                 break;
2379         case ixgbe_phy_x550em_kx4:
2380                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2381                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2382                 break;
2383         case ixgbe_phy_x550em_ext_t:
2384                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2385                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2386                                      &ext_ability);
2387                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2388                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2389                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2390                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2391                 break;
2392         default:
2393                 break;
2394         }
2395
2396         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2397                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2398
2399         return physical_layer;
2400 }
2401
2402 /**
2403  * ixgbe_get_bus_info_x550em - Set PCI bus info
2404  * @hw: pointer to hardware structure
2405  *
2406  * Sets bus link width and speed to unknown because X550em is
2407  * not a PCI device.
2408  **/
2409 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2410 {
2411
2412         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2413
2414         hw->bus.width = ixgbe_bus_width_unknown;
2415         hw->bus.speed = ixgbe_bus_speed_unknown;
2416
2417         hw->mac.ops.set_lan_id(hw);
2418
2419         return IXGBE_SUCCESS;
2420 }
2421
2422 /**
2423  * ixgbe_disable_rx_x550 - Disable RX unit
2424  *
2425  * Enables the Rx DMA unit for x550
2426  **/
2427 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2428 {
2429         u32 rxctrl, pfdtxgswc;
2430         s32 status;
2431         struct ixgbe_hic_disable_rxen fw_cmd;
2432
2433         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2434
2435         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2436         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2437                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2438                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2439                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2440                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2441                         hw->mac.set_lben = true;
2442                 } else {
2443                         hw->mac.set_lben = false;
2444                 }
2445
2446                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2447                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2448                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2449                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2450
2451                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2452                                         sizeof(struct ixgbe_hic_disable_rxen),
2453                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2454
2455                 /* If we fail - disable RX using register write */
2456                 if (status) {
2457                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2458                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2459                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2460                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2461                         }
2462                 }
2463         }
2464 }
2465
2466 /**
2467  * ixgbe_enter_lplu_x550em - Transition to low power states
2468  *  @hw: pointer to hardware structure
2469  *
2470  * Configures Low Power Link Up on transition to low power states
2471  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2472  * X557 PHY immediately prior to entering LPLU.
2473  **/
2474 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2475 {
2476         u16 autoneg_status, an_10g_cntl_reg, autoneg_reg, speed;
2477         s32 status;
2478         ixgbe_link_speed lcd_speed;
2479         u32 save_autoneg;
2480
2481         /* If blocked by MNG FW, then don't restart AN */
2482         if (ixgbe_check_reset_blocked(hw))
2483                 return IXGBE_SUCCESS;
2484
2485         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2486                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2487                                       &autoneg_status);
2488
2489         if (status != IXGBE_SUCCESS)
2490                 return status;
2491
2492         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2493
2494         if (status != IXGBE_SUCCESS)
2495                 return status;
2496
2497         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2498          * disabled, then force link down by entering low power mode.
2499          */
2500         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS) ||
2501             !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2502             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2503                 return ixgbe_set_copper_phy_power(hw, FALSE);
2504
2505         /* Determine LCD */
2506         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2507
2508         if (status != IXGBE_SUCCESS)
2509                 return status;
2510
2511         /* If no valid LCD link speed, then force link down and exit. */
2512         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2513                 return ixgbe_set_copper_phy_power(hw, FALSE);
2514
2515         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2516                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2517                                       &speed);
2518
2519         if (status != IXGBE_SUCCESS)
2520                 return status;
2521
2522         /* clear everything but the speed bits */
2523         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2524
2525         /* If current speed is already LCD, then exit. */
2526         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2527              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2528             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2529              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2530                 return status;
2531
2532         /* Clear AN completed indication */
2533         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2534                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2535                                       &autoneg_status);
2536
2537         if (status != IXGBE_SUCCESS)
2538                 return status;
2539
2540         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2541                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2542                              &an_10g_cntl_reg);
2543
2544         if (status != IXGBE_SUCCESS)
2545                 return status;
2546
2547         status = hw->phy.ops.read_reg(hw,
2548                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2549                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2550                              &autoneg_reg);
2551
2552         if (status != IXGBE_SUCCESS)
2553                 return status;
2554
2555         save_autoneg = hw->phy.autoneg_advertised;
2556
2557         /* Setup link at least common link speed */
2558         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2559
2560         /* restore autoneg from before setting lplu speed */
2561         hw->phy.autoneg_advertised = save_autoneg;
2562
2563         return status;
2564 }
2565
2566 /**
2567  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2568  *  @hw: pointer to hardware structure
2569  *  @lcd_speed: pointer to lowest common link speed
2570  *
2571  * Determine lowest common link speed with link partner.
2572  **/
2573 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2574 {
2575         u16 an_lp_status;
2576         s32 status;
2577         u16 word = hw->eeprom.ctrl_word_3;
2578
2579         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2580
2581         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2582                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2583                                       &an_lp_status);
2584
2585         if (status != IXGBE_SUCCESS)
2586                 return status;
2587
2588         /* If link partner advertised 1G, return 1G */
2589         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2590                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2591                 return status;
2592         }
2593
2594         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2595         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2596             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2597                 return status;
2598
2599         /* Link partner not capable of lower speeds, return 10G */
2600         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2601         return status;
2602 }
2603
2604 /**
2605  *  ixgbe_setup_fc_X550em - Set up flow control
2606  *  @hw: pointer to hardware structure
2607  *
2608  *  Called at init time to set up flow control.
2609  **/
2610 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2611 {
2612         s32 ret_val = IXGBE_SUCCESS;
2613         u32 pause, asm_dir, reg_val;
2614
2615         DEBUGFUNC("ixgbe_setup_fc_X550em");
2616
2617         /* Validate the requested mode */
2618         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2619                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2620                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2621                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2622                 goto out;
2623         }
2624
2625         /* 10gig parts do not have a word in the EEPROM to determine the
2626          * default flow control setting, so we explicitly set it to full.
2627          */
2628         if (hw->fc.requested_mode == ixgbe_fc_default)
2629                 hw->fc.requested_mode = ixgbe_fc_full;
2630
2631         /* Determine PAUSE and ASM_DIR bits. */
2632         switch (hw->fc.requested_mode) {
2633         case ixgbe_fc_none:
2634                 pause = 0;
2635                 asm_dir = 0;
2636                 break;
2637         case ixgbe_fc_tx_pause:
2638                 pause = 0;
2639                 asm_dir = 1;
2640                 break;
2641         case ixgbe_fc_rx_pause:
2642                 /* Rx Flow control is enabled and Tx Flow control is
2643                  * disabled by software override. Since there really
2644                  * isn't a way to advertise that we are capable of RX
2645                  * Pause ONLY, we will advertise that we support both
2646                  * symmetric and asymmetric Rx PAUSE, as such we fall
2647                  * through to the fc_full statement.  Later, we will
2648                  * disable the adapter's ability to send PAUSE frames.
2649                  */
2650         case ixgbe_fc_full:
2651                 pause = 1;
2652                 asm_dir = 1;
2653                 break;
2654         default:
2655                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2656                         "Flow control param set incorrectly\n");
2657                 ret_val = IXGBE_ERR_CONFIG;
2658                 goto out;
2659         }
2660
2661         if (hw->phy.media_type == ixgbe_media_type_backplane) {
2662                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2663                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2664                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2665                 if (ret_val != IXGBE_SUCCESS)
2666                         goto out;
2667                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2668                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2669                 if (pause)
2670                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2671                 if (asm_dir)
2672                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2673                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2674                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2675                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2676
2677                 /* Not all devices fully support AN. */
2678                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR)
2679                         hw->fc.disable_fc_autoneg = true;
2680         }
2681
2682 out:
2683         return ret_val;
2684 }
2685
2686 /**
2687  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2688  * @hw: pointer to hardware structure
2689  * @state: set mux if 1, clear if 0
2690  */
2691 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2692 {
2693         u32 esdp;
2694
2695         if (!hw->bus.lan_id)
2696                 return;
2697         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2698         if (state)
2699                 esdp |= IXGBE_ESDP_SDP1;
2700         else
2701                 esdp &= ~IXGBE_ESDP_SDP1;
2702         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2703         IXGBE_WRITE_FLUSH(hw);
2704 }
2705
2706 /**
2707  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2708  *  @hw: pointer to hardware structure
2709  *  @mask: Mask to specify which semaphore to acquire
2710  *
2711  *  Acquires the SWFW semaphore and sets the I2C MUX
2712  **/
2713 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2714 {
2715         s32 status;
2716
2717         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2718
2719         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2720         if (status)
2721                 return status;
2722
2723         if (mask & IXGBE_GSSR_I2C_MASK)
2724                 ixgbe_set_mux(hw, 1);
2725
2726         return IXGBE_SUCCESS;
2727 }
2728
2729 /**
2730  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2731  *  @hw: pointer to hardware structure
2732  *  @mask: Mask to specify which semaphore to release
2733  *
2734  *  Releases the SWFW semaphore and sets the I2C MUX
2735  **/
2736 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2737 {
2738         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2739
2740         if (mask & IXGBE_GSSR_I2C_MASK)
2741                 ixgbe_set_mux(hw, 0);
2742
2743         ixgbe_release_swfw_sync_X540(hw, mask);
2744 }
2745
2746 /**
2747  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2748  * @hw: pointer to hardware structure
2749  *
2750  * Handle external Base T PHY interrupt. If high temperature
2751  * failure alarm then return error, else if link status change
2752  * then setup internal/external PHY link
2753  *
2754  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2755  * failure alarm, else return PHY access status.
2756  */
2757 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2758 {
2759         bool lsc;
2760         u32 status;
2761
2762         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2763
2764         if (status != IXGBE_SUCCESS)
2765                 return status;
2766
2767         if (lsc)
2768                 return ixgbe_setup_internal_phy_t_x550em(hw);
2769
2770         return IXGBE_SUCCESS;
2771 }
2772
2773 /**
2774  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
2775  * @hw: pointer to hardware structure
2776  * @speed: new link speed
2777  * @autoneg_wait_to_complete: true when waiting for completion is needed
2778  *
2779  * Setup internal/external PHY link speed based on link speed, then set
2780  * external PHY auto advertised link speed.
2781  *
2782  * Returns error status for any failure
2783  **/
2784 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
2785                                   ixgbe_link_speed speed,
2786                                   bool autoneg_wait_to_complete)
2787 {
2788         s32 status;
2789         ixgbe_link_speed force_speed;
2790
2791         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
2792
2793         /* Setup internal/external PHY link speed to iXFI (10G), unless
2794          * only 1G is auto advertised then setup KX link.
2795          */
2796         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2797                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2798         else
2799                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2800
2801         status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
2802
2803         if (status != IXGBE_SUCCESS)
2804                 return status;
2805
2806         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
2807 }
2808
2809 /**
2810  * ixgbe_check_link_t_X550em - Determine link and speed status
2811  * @hw: pointer to hardware structure
2812  * @speed: pointer to link speed
2813  * @link_up: true when link is up
2814  * @link_up_wait_to_complete: bool used to wait for link up or not
2815  *
2816  * Check that both the MAC and X557 external PHY have link.
2817  **/
2818 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
2819                               bool *link_up, bool link_up_wait_to_complete)
2820 {
2821         u32 status;
2822         u16 autoneg_status;
2823
2824         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2825                 return IXGBE_ERR_CONFIG;
2826
2827         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
2828                                               link_up_wait_to_complete);
2829
2830         /* If check link fails or MAC link is not up, then return */
2831         if (status != IXGBE_SUCCESS || !(*link_up))
2832                 return status;
2833
2834         /* MAC link is up, so check external PHY link.
2835          * Read this twice back to back to indicate current status.
2836          */
2837         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2838                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2839                                       &autoneg_status);
2840
2841         if (status != IXGBE_SUCCESS)
2842                 return status;
2843
2844         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2845                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2846                                       &autoneg_status);
2847
2848         if (status != IXGBE_SUCCESS)
2849                 return status;
2850
2851         /* If external PHY link is not up, then indicate link not up */
2852         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
2853                 *link_up = false;
2854
2855         return IXGBE_SUCCESS;
2856 }
2857
2858 /**
2859  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2860  *  @hw: pointer to hardware structure
2861  **/
2862 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2863 {
2864         s32 status;
2865
2866         status = ixgbe_reset_phy_generic(hw);
2867
2868         if (status != IXGBE_SUCCESS)
2869                 return status;
2870
2871         /* Configure Link Status Alarm and Temperature Threshold interrupts */
2872         return ixgbe_enable_lasi_ext_t_x550em(hw);
2873 }