drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41
  42 /**
  43  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  44  *  @hw: pointer to hardware structure
  45  *
  46  *  Initialize the function pointers and assign the MAC type for X550.
  47  *  Does not touch the hardware.
  48  **/
  49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  50 {
  51         struct ixgbe_mac_info *mac = &hw->mac;
  52         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  53         s32 ret_val;
  54
  55         DEBUGFUNC("ixgbe_init_ops_X550");
  56
  57         ret_val = ixgbe_init_ops_X540(hw);
  58         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  59         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  60         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  61         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  62         mac->ops.set_source_address_pruning =
  63                         ixgbe_set_source_address_pruning_X550;
  64         mac->ops.set_ethertype_anti_spoofing =
  65                         ixgbe_set_ethertype_anti_spoofing_X550;
  66
  67         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  68         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  69         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  70         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  71         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  72         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  73         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  74         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  75         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  76
  77         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  78         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  79         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  80         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  81         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  82         return ret_val;
  83 }
  84
  85 /**
  86  * ixgbe_read_cs4227 - Read CS4227 register
  87  * @hw: pointer to hardware structure
  88  * @reg: register number to write
  89  * @value: pointer to receive value read
  90  *
  91  * Returns status code
  92  **/
  93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  94 {
  95         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
  96 }
  97
  98 /**
  99  * ixgbe_write_cs4227 - Write CS4227 register
 100  * @hw: pointer to hardware structure
 101  * @reg: register number to write
 102  * @value: value to write to register
 103  *
 104  * Returns status code
 105  **/
 106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 107 {
 108         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 109 }
 110
 111 /**
 112  * ixgbe_get_cs4227_status - Return CS4227 status
 113  * @hw: pointer to hardware structure
 114  *
 115  * Returns error if CS4227 not successfully initialized
 116  **/
 117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
 118 {
 119         s32 status;
 120         u16 value = 0;
 121         u8 retry;
 122
 123         for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
 124                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
 125                                            &value);
 126                 if (status != IXGBE_SUCCESS)
 127                         return status;
 128                 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
 129                         break;
 130                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 131         }
 132         if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
 133                 return IXGBE_ERR_PHY;
 134
 135         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 136                                     IXGBE_CS4227_SCRATCH_VALUE);
 137         if (status != IXGBE_SUCCESS)
 138                 return status;
 139         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 140         if (status != IXGBE_SUCCESS)
 141                 return status;
 142         if (value != IXGBE_CS4227_SCRATCH_VALUE)
 143                 return IXGBE_ERR_PHY;
 144         return IXGBE_SUCCESS;
 145 }
 146
 147 /**
 148  * ixgbe_read_pe - Read register from port expander
 149  * @hw: pointer to hardware structure
 150  * @reg: register number to read
 151  * @value: pointer to receive read value
 152  *
 153  * Returns status code
 154  **/
 155 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 156 {
 157         s32 status;
 158
 159         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 160         if (status != IXGBE_SUCCESS)
 161                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 162                               "port expander access failed with %d\n", status);
 163         return status;
 164 }
 165
 166 /**
 167  * ixgbe_write_pe - Write register to port expander
 168  * @hw: pointer to hardware structure
 169  * @reg: register number to write
 170  * @value: value to write
 171  *
 172  * Returns status code
 173  **/
 174 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 175 {
 176         s32 status;
 177
 178         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 179         if (status != IXGBE_SUCCESS)
 180                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 181                               "port expander access failed with %d\n", status);
 182         return status;
 183 }
 184
 185 /**
 186  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 187  * @hw: pointer to hardware structure
 188  *
 189  * Returns error code
 190  **/
 191 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 192 {
 193         s32 status;
 194         u8 reg;
 195
 196         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199         reg |= IXGBE_PE_BIT1;
 200         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 201         if (status != IXGBE_SUCCESS)
 202                 return status;
 203
 204         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 205         if (status != IXGBE_SUCCESS)
 206                 return status;
 207         reg &= ~IXGBE_PE_BIT1;
 208         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 209         if (status != IXGBE_SUCCESS)
 210                 return status;
 211
 212         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 213         if (status != IXGBE_SUCCESS)
 214                 return status;
 215         reg &= ~IXGBE_PE_BIT1;
 216         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 217         if (status != IXGBE_SUCCESS)
 218                 return status;
 219
 220         usec_delay(IXGBE_CS4227_RESET_HOLD);
 221
 222         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 223         if (status != IXGBE_SUCCESS)
 224                 return status;
 225         reg |= IXGBE_PE_BIT1;
 226         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 227         if (status != IXGBE_SUCCESS)
 228                 return status;
 229
 230         msec_delay(IXGBE_CS4227_RESET_DELAY);
 231
 232         return IXGBE_SUCCESS;
 233 }
 234
 235 /**
 236  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 237  * @hw: pointer to hardware structure
 238  **/
 239 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 240 {
 241         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 242         s32 status;
 243         u8 retry;
 244
 245         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 246                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 247                 if (status != IXGBE_SUCCESS) {
 248                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 249                                       "semaphore failed with %d\n", status);
 250                         return;
 251                 }
 252                 status = ixgbe_get_cs4227_status(hw);
 253                 if (status == IXGBE_SUCCESS) {
 254                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 255                         msec_delay(hw->eeprom.semaphore_delay);
 256                         return;
 257                 }
 258                 ixgbe_reset_cs4227(hw);
 259                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 260                 msec_delay(hw->eeprom.semaphore_delay);
 261         }
 262         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 263                       "Unable to initialize CS4227, err=%d\n", status);
 264 }
 265
 266 /**
 267  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 268  * @hw: pointer to hardware structure
 269  **/
 270 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 271 {
 272         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 273
 274         if (hw->bus.lan_id) {
 275                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 276                 esdp |= IXGBE_ESDP_SDP1_DIR;
 277         }
 278         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 279         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 280         IXGBE_WRITE_FLUSH(hw);
 281 }
 282
 283 /**
 284  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 285  * @hw: pointer to hardware structure
 286  *
 287  * Returns error code
 288  */
 289 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 290 {
 291         switch (hw->device_id) {
 292         case IXGBE_DEV_ID_X550EM_X_SFP:
 293                 /* set up for CS4227 usage */
 294                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 295                 ixgbe_setup_mux_ctl(hw);
 296                 ixgbe_check_cs4227(hw);
 297
 298                 return ixgbe_identify_module_generic(hw);
 299                 break;
 300         case IXGBE_DEV_ID_X550EM_X_KX4:
 301                 hw->phy.type = ixgbe_phy_x550em_kx4;
 302                 break;
 303         case IXGBE_DEV_ID_X550EM_X_KR:
 304                 hw->phy.type = ixgbe_phy_x550em_kr;
 305                 break;
 306         case IXGBE_DEV_ID_X550EM_X_1G_T:
 307         case IXGBE_DEV_ID_X550EM_X_10G_T:
 308                 return ixgbe_identify_phy_generic(hw);
 309         default:
 310                 break;
 311         }
 312         return IXGBE_SUCCESS;
 313 }
 314
 315 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 316                                      u32 device_type, u16 *phy_data)
 317 {
 318         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 319         return IXGBE_NOT_IMPLEMENTED;
 320 }
 321
 322 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 323                                       u32 device_type, u16 phy_data)
 324 {
 325         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 326         return IXGBE_NOT_IMPLEMENTED;
 327 }
 328
 329 /**
 330 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 331 *  @hw: pointer to hardware structure
 332 *
 333 *  Initialize the function pointers and for MAC type X550EM.
 334 *  Does not touch the hardware.
 335 **/
 336 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 337 {
 338         struct ixgbe_mac_info *mac = &hw->mac;
 339         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 340         struct ixgbe_phy_info *phy = &hw->phy;
 341         s32 ret_val;
 342
 343         DEBUGFUNC("ixgbe_init_ops_X550EM");
 344
 345         /* Similar to X550 so start there. */
 346         ret_val = ixgbe_init_ops_X550(hw);
 347
 348         /* Since this function eventually calls
 349          * ixgbe_init_ops_540 by design, we are setting
 350          * the pointers to NULL explicitly here to overwrite
 351          * the values being set in the x540 function.
 352          */
 353         /* Thermal sensor not supported in x550EM */
 354         mac->ops.get_thermal_sensor_data = NULL;
 355         mac->ops.init_thermal_sensor_thresh = NULL;
 356         mac->thermal_sensor_enabled = false;
 357
 358         /* FCOE not supported in x550EM */
 359         mac->ops.get_san_mac_addr = NULL;
 360         mac->ops.set_san_mac_addr = NULL;
 361         mac->ops.get_wwn_prefix = NULL;
 362         mac->ops.get_fcoe_boot_status = NULL;
 363
 364         /* IPsec not supported in x550EM */
 365         mac->ops.disable_sec_rx_path = NULL;
 366         mac->ops.enable_sec_rx_path = NULL;
 367
 368         /* AUTOC register is not present in x550EM. */
 369         mac->ops.prot_autoc_read = NULL;
 370         mac->ops.prot_autoc_write = NULL;
 371
 372         /* X550EM bus type is internal*/
 373         hw->bus.type = ixgbe_bus_type_internal;
 374         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 375
 376         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 377         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 378         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 379         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 380         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 381         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 382         mac->ops.get_supported_physical_layer =
 383                                     ixgbe_get_supported_physical_layer_X550em;
 384
 385         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 386                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 387         else
 388                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 389
 390         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 391         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 392
 393         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
 394                 mac->ops.setup_eee = NULL;
 395
 396         /* PHY */
 397         phy->ops.init = ixgbe_init_phy_ops_X550em;
 398         phy->ops.identify = ixgbe_identify_phy_x550em;
 399         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 400                 phy->ops.set_phy_power = NULL;
 401
 402
 403         /* EEPROM */
 404         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 405         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 406         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 407         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 408         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 409         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 410         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 411         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 412
 413         return ret_val;
 414 }
 415
 416 /**
 417  *  ixgbe_dmac_config_X550
 418  *  @hw: pointer to hardware structure
 419  *
 420  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 421  *  When disabling dmac, dmac enable dmac bit is cleared.
 422  **/
 423 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 424 {
 425         u32 reg, high_pri_tc;
 426
 427         DEBUGFUNC("ixgbe_dmac_config_X550");
 428
 429         /* Disable DMA coalescing before configuring */
 430         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 431         reg &= ~IXGBE_DMACR_DMAC_EN;
 432         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 433
 434         /* Disable DMA Coalescing if the watchdog timer is 0 */
 435         if (!hw->mac.dmac_config.watchdog_timer)
 436                 goto out;
 437
 438         ixgbe_dmac_config_tcs_X550(hw);
 439
 440         /* Configure DMA Coalescing Control Register */
 441         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 442
 443         /* Set the watchdog timer in units of 40.96 usec */
 444         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 445         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 446
 447         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 448         /* If fcoe is enabled, set high priority traffic class */
 449         if (hw->mac.dmac_config.fcoe_en) {
 450                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 451                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 452                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 453         }
 454         reg |= IXGBE_DMACR_EN_MNG_IND;
 455
 456         /* Enable DMA coalescing after configuration */
 457         reg |= IXGBE_DMACR_DMAC_EN;
 458         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 459
 460 out:
 461         return IXGBE_SUCCESS;
 462 }
 463
 464 /**
 465  *  ixgbe_dmac_config_tcs_X550
 466  *  @hw: pointer to hardware structure
 467  *
 468  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 469  *  be cleared before configuring.
 470  **/
 471 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 472 {
 473         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 474
 475         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 476
 477         /* Configure DMA coalescing enabled */
 478         switch (hw->mac.dmac_config.link_speed) {
 479         case IXGBE_LINK_SPEED_100_FULL:
 480                 pb_headroom = IXGBE_DMACRXT_100M;
 481                 break;
 482         case IXGBE_LINK_SPEED_1GB_FULL:
 483                 pb_headroom = IXGBE_DMACRXT_1G;
 484                 break;
 485         default:
 486                 pb_headroom = IXGBE_DMACRXT_10G;
 487                 break;
 488         }
 489
 490         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 491                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 492
 493         /* Set the per Rx packet buffer receive threshold */
 494         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 495                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 496                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 497
 498                 if (tc < hw->mac.dmac_config.num_tcs) {
 499                         /* Get Rx PB size */
 500                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 501                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 502                                 IXGBE_RXPBSIZE_SHIFT;
 503
 504                         /* Calculate receive buffer threshold in kilobytes */
 505                         if (rx_pb_size > pb_headroom)
 506                                 rx_pb_size = rx_pb_size - pb_headroom;
 507                         else
 508                                 rx_pb_size = 0;
 509
 510                         /* Minimum of MFS shall be set for DMCTH */
 511                         reg |= (rx_pb_size > maxframe_size_kb) ?
 512                                 rx_pb_size : maxframe_size_kb;
 513                 }
 514                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 515         }
 516         return IXGBE_SUCCESS;
 517 }
 518
 519 /**
 520  *  ixgbe_dmac_update_tcs_X550
 521  *  @hw: pointer to hardware structure
 522  *
 523  *  Disables dmac, updates per TC settings, and then enables dmac.
 524  **/
 525 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 526 {
 527         u32 reg;
 528
 529         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 530
 531         /* Disable DMA coalescing before configuring */
 532         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 533         reg &= ~IXGBE_DMACR_DMAC_EN;
 534         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 535
 536         ixgbe_dmac_config_tcs_X550(hw);
 537
 538         /* Enable DMA coalescing after configuration */
 539         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 540         reg |= IXGBE_DMACR_DMAC_EN;
 541         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 542
 543         return IXGBE_SUCCESS;
 544 }
 545
 546 /**
 547  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 548  *  @hw: pointer to hardware structure
 549  *
 550  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 551  *  ixgbe_hw struct in order to set up EEPROM access.
 552  **/
 553 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 554 {
 555         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 556         u32 eec;
 557         u16 eeprom_size;
 558
 559         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 560
 561         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 562                 eeprom->semaphore_delay = 10;
 563                 eeprom->type = ixgbe_flash;
 564
 565                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 566                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 567                                     IXGBE_EEC_SIZE_SHIFT);
 568                 eeprom->word_size = 1 << (eeprom_size +
 569                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 570
 571                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 572                           eeprom->type, eeprom->word_size);
 573         }
 574
 575         return IXGBE_SUCCESS;
 576 }
 577
 578 /**
 579  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 580  *  @hw: pointer to the HW structure
 581  *  @enable_eee: boolean flag to enable EEE
 582  *
 583  *  Enable/disable EEE based on enable_eee flag.
 584  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 585  *  are modified.
 586  *
 587  **/
 588 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 589 {
 590         u32 eeer;
 591         u16 autoneg_eee_reg;
 592         u32 link_reg;
 593         s32 status;
 594
 595         DEBUGFUNC("ixgbe_setup_eee_X550");
 596
 597         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 598         /* Enable or disable EEE per flag */
 599         if (enable_eee) {
 600                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 601
 602                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 603                         /* Advertise EEE capability */
 604                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 605                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 606
 607                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 608                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 609                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 610
 611                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 612                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 613                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 614                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 615                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 616                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 617                         if (status != IXGBE_SUCCESS)
 618                                 return status;
 619
 620                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 621                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 622
 623                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 624                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 625                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 626                         if (status != IXGBE_SUCCESS)
 627                                 return status;
 628                 }
 629         } else {
 630                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 631
 632                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 633                         /* Disable advertised EEE capability */
 634                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 635                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 636
 637                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 638                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 639                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 640
 641                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 642                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 643                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 644                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 645                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 646                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 647                         if (status != IXGBE_SUCCESS)
 648                                 return status;
 649
 650                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 651                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 652
 653                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 654                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 655                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 656                         if (status != IXGBE_SUCCESS)
 657                                 return status;
 658                 }
 659         }
 660         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 661
 662         return IXGBE_SUCCESS;
 663 }
 664
 665 /**
 666  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 667  * @hw: pointer to hardware structure
 668  * @enable: enable or disable source address pruning
 669  * @pool: Rx pool to set source address pruning for
 670  **/
 671 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 672                                            unsigned int pool)
 673 {
 674         u64 pfflp;
 675
 676         /* max rx pool is 63 */
 677         if (pool > 63)
 678                 return;
 679
 680         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 681         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 682
 683         if (enable)
 684                 pfflp |= (1ULL << pool);
 685         else
 686                 pfflp &= ~(1ULL << pool);
 687
 688         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 689         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 690 }
 691
 692 /**
 693  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 694  *  @hw: pointer to hardware structure
 695  *  @enable: enable or disable switch for Ethertype anti-spoofing
 696  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 697  *
 698  **/
 699 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 700                 bool enable, int vf)
 701 {
 702         int vf_target_reg = vf >> 3;
 703         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 704         u32 pfvfspoof;
 705
 706         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 707
 708         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 709         if (enable)
 710                 pfvfspoof |= (1 << vf_target_shift);
 711         else
 712                 pfvfspoof &= ~(1 << vf_target_shift);
 713
 714         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 715 }
 716
 717 /**
 718  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 719  *  device
 720  *  @hw: pointer to hardware structure
 721  *  @reg_addr: 32 bit PHY register to write
 722  *  @device_type: 3 bit device type
 723  *  @data: Data to write to the register
 724  **/
 725 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 726                             u32 device_type, u32 data)
 727 {
 728         u32 i, command, error;
 729
 730         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 731                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 732
 733         /* Write IOSF control register */
 734         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 735
 736         /* Write IOSF data register */
 737         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 738         /*
 739          * Check every 10 usec to see if the address cycle completed.
 740          * The SB IOSF BUSY bit will clear when the operation is
 741          * complete
 742          */
 743         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 744                 usec_delay(10);
 745
 746                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 747                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 748                         break;
 749         }
 750
 751         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 752                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 753                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 754                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 755                               "Failed to write, error %x\n", error);
 756                 return IXGBE_ERR_PHY;
 757         }
 758
 759         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 760                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
 761                 return IXGBE_ERR_PHY;
 762         }
 763
 764         return IXGBE_SUCCESS;
 765 }
 766
 767 /**
 768  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 769  *  device
 770  *  @hw: pointer to hardware structure
 771  *  @reg_addr: 32 bit PHY register to write
 772  *  @device_type: 3 bit device type
 773  *  @phy_data: Pointer to read data from the register
 774  **/
 775 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 776                            u32 device_type, u32 *data)
 777 {
 778         u32 i, command, error;
 779
 780         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 781                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 782
 783         /* Write IOSF control register */
 784         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 785
 786         /*
 787          * Check every 10 usec to see if the address cycle completed.
 788          * The SB IOSF BUSY bit will clear when the operation is
 789          * complete
 790          */
 791         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 792                 usec_delay(10);
 793
 794                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 795                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 796                         break;
 797         }
 798
 799         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 800                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 801                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 802                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 803                                 "Failed to read, error %x\n", error);
 804                 return IXGBE_ERR_PHY;
 805         }
 806
 807         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 808                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
 809                 return IXGBE_ERR_PHY;
 810         }
 811
 812         *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 813
 814         return IXGBE_SUCCESS;
 815 }
 816
 817 /**
 818  *  ixgbe_disable_mdd_X550
 819  *  @hw: pointer to hardware structure
 820  *
 821  *  Disable malicious driver detection
 822  **/
 823 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 824 {
 825         u32 reg;
 826
 827         DEBUGFUNC("ixgbe_disable_mdd_X550");
 828
 829         /* Disable MDD for TX DMA and interrupt */
 830         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 831         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 832         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 833
 834         /* Disable MDD for RX and interrupt */
 835         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 836         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 837         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 838 }
 839
 840 /**
 841  *  ixgbe_enable_mdd_X550
 842  *  @hw: pointer to hardware structure
 843  *
 844  *  Enable malicious driver detection
 845  **/
 846 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 847 {
 848         u32 reg;
 849
 850         DEBUGFUNC("ixgbe_enable_mdd_X550");
 851
 852         /* Enable MDD for TX DMA and interrupt */
 853         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 854         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 855         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 856
 857         /* Enable MDD for RX and interrupt */
 858         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 859         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 860         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 861 }
 862
 863 /**
 864  *  ixgbe_restore_mdd_vf_X550
 865  *  @hw: pointer to hardware structure
 866  *  @vf: vf index
 867  *
 868  *  Restore VF that was disabled during malicious driver detection event
 869  **/
 870 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 871 {
 872         u32 idx, reg, num_qs, start_q, bitmask;
 873
 874         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 875
 876         /* Map VF to queues */
 877         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 878         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 879         case IXGBE_MRQC_VMDQRT8TCEN:
 880                 num_qs = 8;  /* 16 VFs / pools */
 881                 bitmask = 0x000000FF;
 882                 break;
 883         case IXGBE_MRQC_VMDQRSS32EN:
 884         case IXGBE_MRQC_VMDQRT4TCEN:
 885                 num_qs = 4;  /* 32 VFs / pools */
 886                 bitmask = 0x0000000F;
 887                 break;
 888         default:            /* 64 VFs / pools */
 889                 num_qs = 2;
 890                 bitmask = 0x00000003;
 891                 break;
 892         }
 893         start_q = vf * num_qs;
 894
 895         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 896         idx = start_q / 32;
 897         reg = 0;
 898         reg |= (bitmask << (start_q % 32));
 899         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 900         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 901 }
 902
 903 /**
 904  *  ixgbe_mdd_event_X550
 905  *  @hw: pointer to hardware structure
 906  *  @vf_bitmap: vf bitmap of malicious vfs
 907  *
 908  *  Handle malicious driver detection event.
 909  **/
 910 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 911 {
 912         u32 wqbr;
 913         u32 i, j, reg, q, shift, vf, idx;
 914
 915         DEBUGFUNC("ixgbe_mdd_event_X550");
 916
 917         /* figure out pool size for mapping to vf's */
 918         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 919         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 920         case IXGBE_MRQC_VMDQRT8TCEN:
 921                 shift = 3;  /* 16 VFs / pools */
 922                 break;
 923         case IXGBE_MRQC_VMDQRSS32EN:
 924         case IXGBE_MRQC_VMDQRT4TCEN:
 925                 shift = 2;  /* 32 VFs / pools */
 926                 break;
 927         default:
 928                 shift = 1;  /* 64 VFs / pools */
 929                 break;
 930         }
 931
 932         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
 933         for (i = 0; i < 4; i++) {
 934                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
 935                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
 936
 937                 if (!wqbr)
 938                         continue;
 939
 940                 /* Get malicious queue */
 941                 for (j = 0; j < 32 && wqbr; j++) {
 942
 943                         if (!(wqbr & (1 << j)))
 944                                 continue;
 945
 946                         /* Get queue from bitmask */
 947                         q = j + (i * 32);
 948
 949                         /* Map queue to vf */
 950                         vf = (q >> shift);
 951
 952                         /* Set vf bit in vf_bitmap */
 953                         idx = vf / 32;
 954                         vf_bitmap[idx] |= (1 << (vf % 32));
 955                         wqbr &= ~(1 << j);
 956                 }
 957         }
 958 }
 959
 960 /**
 961  *  ixgbe_get_media_type_X550em - Get media type
 962  *  @hw: pointer to hardware structure
 963  *
 964  *  Returns the media type (fiber, copper, backplane)
 965  */
 966 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
 967 {
 968         enum ixgbe_media_type media_type;
 969
 970         DEBUGFUNC("ixgbe_get_media_type_X550em");
 971
 972         /* Detect if there is a copper PHY attached. */
 973         switch (hw->device_id) {
 974         case IXGBE_DEV_ID_X550EM_X_KR:
 975         case IXGBE_DEV_ID_X550EM_X_KX4:
 976                 media_type = ixgbe_media_type_backplane;
 977                 break;
 978         case IXGBE_DEV_ID_X550EM_X_SFP:
 979                 media_type = ixgbe_media_type_fiber;
 980                 break;
 981         case IXGBE_DEV_ID_X550EM_X_1G_T:
 982         case IXGBE_DEV_ID_X550EM_X_10G_T:
 983                 media_type = ixgbe_media_type_copper;
 984                 break;
 985         default:
 986                 media_type = ixgbe_media_type_unknown;
 987                 break;
 988         }
 989         return media_type;
 990 }
 991
 992 /**
 993  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
 994  *  @hw: pointer to hardware structure
 995  *  @linear: true if SFP module is linear
 996  */
 997 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
 998 {
 999         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1000
1001         switch (hw->phy.sfp_type) {
1002         case ixgbe_sfp_type_not_present:
1003                 return IXGBE_ERR_SFP_NOT_PRESENT;
1004         case ixgbe_sfp_type_da_cu_core0:
1005         case ixgbe_sfp_type_da_cu_core1:
1006                 *linear = true;
1007                 break;
1008         case ixgbe_sfp_type_srlr_core0:
1009         case ixgbe_sfp_type_srlr_core1:
1010         case ixgbe_sfp_type_da_act_lmt_core0:
1011         case ixgbe_sfp_type_da_act_lmt_core1:
1012         case ixgbe_sfp_type_1g_sx_core0:
1013         case ixgbe_sfp_type_1g_sx_core1:
1014         case ixgbe_sfp_type_1g_lx_core0:
1015         case ixgbe_sfp_type_1g_lx_core1:
1016                 *linear = false;
1017                 break;
1018         case ixgbe_sfp_type_unknown:
1019         case ixgbe_sfp_type_1g_cu_core0:
1020         case ixgbe_sfp_type_1g_cu_core1:
1021         default:
1022                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1023         }
1024
1025         return IXGBE_SUCCESS;
1026 }
1027
1028 /**
1029  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1030  *  @hw: pointer to hardware structure
1031  *
1032  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1033  **/
1034 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1035 {
1036         s32 status;
1037         bool linear;
1038
1039         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1040
1041         status = ixgbe_identify_module_generic(hw);
1042
1043         if (status != IXGBE_SUCCESS)
1044                 return status;
1045
1046         /* Check if SFP module is supported */
1047         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1048
1049         return status;
1050 }
1051
1052 /**
1053  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1054  *  @hw: pointer to hardware structure
1055  */
1056 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1057 {
1058         s32 status;
1059         bool linear;
1060
1061         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1062
1063         /* Check if SFP module is supported */
1064         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1065
1066         if (status != IXGBE_SUCCESS)
1067                 return status;
1068
1069         ixgbe_init_mac_link_ops_X550em(hw);
1070         hw->phy.ops.reset = NULL;
1071
1072         return IXGBE_SUCCESS;
1073 }
1074
1075 /**
1076  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1077  *  @hw: pointer to hardware structure
1078  */
1079 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1080 {
1081         struct ixgbe_mac_info *mac = &hw->mac;
1082
1083         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1084
1085          switch (hw->mac.ops.get_media_type(hw)) {
1086          case ixgbe_media_type_fiber:
1087                 /* CS4227 does not support autoneg, so disable the laser control
1088                  * functions for SFP+ fiber
1089                  */
1090                 mac->ops.disable_tx_laser = NULL;
1091                 mac->ops.enable_tx_laser = NULL;
1092                 mac->ops.flap_tx_laser = NULL;
1093                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1094                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1095                 mac->ops.set_rate_select_speed =
1096                                         ixgbe_set_soft_rate_select_speed;
1097                 break;
1098         case ixgbe_media_type_copper:
1099                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1100                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1101                 break;
1102         default:
1103                 break;
1104          }
1105 }
1106
1107 /**
1108  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1109  *  @hw: pointer to hardware structure
1110  *  @speed: pointer to link speed
1111  *  @autoneg: true when autoneg or autotry is enabled
1112  */
1113 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1114                                        ixgbe_link_speed *speed,
1115                                        bool *autoneg)
1116 {
1117         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1118
1119         /* SFP */
1120         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1121
1122                 /* CS4227 SFP must not enable auto-negotiation */
1123                 *autoneg = false;
1124
1125                 /* Check if 1G SFP module. */
1126                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1127                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1128                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1129                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1130                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1131                         return IXGBE_SUCCESS;
1132                 }
1133
1134                 /* Link capabilities are based on SFP */
1135                 if (hw->phy.multispeed_fiber)
1136                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1137                                  IXGBE_LINK_SPEED_1GB_FULL;
1138                 else
1139                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1140         } else {
1141                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1142                          IXGBE_LINK_SPEED_1GB_FULL;
1143                 *autoneg = true;
1144         }
1145
1146         return IXGBE_SUCCESS;
1147 }
1148
1149 /**
1150  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1151  * @hw: pointer to hardware structure
1152  * @lsc: pointer to boolean flag which indicates whether external Base T
1153  *       PHY interrupt is lsc
1154  *
1155  * Determime if external Base T PHY interrupt cause is high temperature
1156  * failure alarm or link status change.
1157  *
1158  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1159  * failure alarm, else return PHY access status.
1160  */
1161 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1162 {
1163         u32 status;
1164         u16 reg;
1165
1166         *lsc = false;
1167
1168         /* Vendor alarm triggered */
1169         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1170                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1171                                       &reg);
1172
1173         if (status != IXGBE_SUCCESS ||
1174             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1175                 return status;
1176
1177         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1178         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1179                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1180                                       &reg);
1181
1182         if (status != IXGBE_SUCCESS ||
1183             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1184             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1185                 return status;
1186
1187         /* High temperature failure alarm triggered */
1188         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1189                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1190                                       &reg);
1191
1192         if (status != IXGBE_SUCCESS)
1193                 return status;
1194
1195         /* If high temperature failure, then return over temp error and exit */
1196         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1197                 /* power down the PHY in case the PHY FW didn't already */
1198                 ixgbe_set_copper_phy_power(hw, false);
1199                 return IXGBE_ERR_OVERTEMP;
1200         }
1201
1202         /* Vendor alarm 2 triggered */
1203         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1204                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1205
1206         if (status != IXGBE_SUCCESS ||
1207             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1208                 return status;
1209
1210         /* link connect/disconnect event occurred */
1211         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1212                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1213
1214         if (status != IXGBE_SUCCESS)
1215                 return status;
1216
1217         /* Indicate LSC */
1218         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1219                 *lsc = true;
1220
1221         return IXGBE_SUCCESS;
1222 }
1223
1224 /**
1225  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1226  * @hw: pointer to hardware structure
1227  *
1228  * Enable link status change and temperature failure alarm for the external
1229  * Base T PHY
1230  *
1231  * Returns PHY access status
1232  */
1233 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1234 {
1235         u32 status;
1236         u16 reg;
1237         bool lsc;
1238
1239         /* Clear interrupt flags */
1240         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1241
1242         /* Enable link status change alarm */
1243         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1244                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1245
1246         if (status != IXGBE_SUCCESS)
1247                 return status;
1248
1249         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1250
1251         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1252                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1253
1254         if (status != IXGBE_SUCCESS)
1255                 return status;
1256
1257         /* Enables high temperature failure alarm */
1258         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1259                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1260                                       &reg);
1261
1262         if (status != IXGBE_SUCCESS)
1263                 return status;
1264
1265         reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1266
1267         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1268                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1269                                        reg);
1270
1271         if (status != IXGBE_SUCCESS)
1272                 return status;
1273
1274         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1275         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1276                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1277                                       &reg);
1278
1279         if (status != IXGBE_SUCCESS)
1280                 return status;
1281
1282         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1283                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1284
1285         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1286                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1287                                        reg);
1288
1289         if (status != IXGBE_SUCCESS)
1290                 return status;
1291
1292         /* Enable chip-wide vendor alarm */
1293         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1294                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1295                                       &reg);
1296
1297         if (status != IXGBE_SUCCESS)
1298                 return status;
1299
1300         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1301
1302         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1303                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1304                                        reg);
1305
1306         return status;
1307 }
1308
1309 /**
1310  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1311  *  @hw: pointer to hardware structure
1312  *
1313  *  Initialize any function pointers that were not able to be
1314  *  set during init_shared_code because the PHY/SFP type was
1315  *  not known.  Perform the SFP init if necessary.
1316  */
1317 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1318 {
1319         struct ixgbe_phy_info *phy = &hw->phy;
1320         s32 ret_val;
1321
1322         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1323
1324         hw->mac.ops.set_lan_id(hw);
1325
1326         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1327                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1328                 ixgbe_setup_mux_ctl(hw);
1329
1330                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1331         }
1332
1333         /* Identify the PHY or SFP module */
1334         ret_val = phy->ops.identify(hw);
1335         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1336                 return ret_val;
1337
1338         /* Setup function pointers based on detected hardware */
1339         ixgbe_init_mac_link_ops_X550em(hw);
1340         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1341                 phy->ops.reset = NULL;
1342
1343         /* Set functions pointers based on phy type */
1344         switch (hw->phy.type) {
1345         case ixgbe_phy_x550em_kx4:
1346                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1347                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1348                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1349                 break;
1350         case ixgbe_phy_x550em_kr:
1351                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1352                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1353                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1354                 break;
1355         case ixgbe_phy_x550em_ext_t:
1356                 phy->ops.setup_internal_link =
1357                                          ixgbe_setup_internal_phy_t_x550em;
1358                 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1359                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1360                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1361                 break;
1362         default:
1363                 break;
1364         }
1365         return ret_val;
1366 }
1367
1368 /**
1369  *  ixgbe_reset_hw_X550em - Perform hardware reset
1370  *  @hw: pointer to hardware structure
1371  *
1372  *  Resets the hardware by resetting the transmit and receive units, masks
1373  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1374  *  reset.
1375  */
1376 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1377 {
1378         ixgbe_link_speed link_speed;
1379         s32 status;
1380         u32 ctrl = 0;
1381         u32 i;
1382         bool link_up = false;
1383
1384         DEBUGFUNC("ixgbe_reset_hw_X550em");
1385
1386         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1387         status = hw->mac.ops.stop_adapter(hw);
1388         if (status != IXGBE_SUCCESS)
1389                 return status;
1390
1391         /* flush pending Tx transactions */
1392         ixgbe_clear_tx_pending(hw);
1393
1394         /* PHY ops must be identified and initialized prior to reset */
1395
1396         /* Identify PHY and related function pointers */
1397         status = hw->phy.ops.init(hw);
1398
1399         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1400                 return status;
1401
1402         /* start the external PHY */
1403         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1404                 status = ixgbe_init_ext_t_x550em(hw);
1405                 if (status)
1406                         return status;
1407         }
1408
1409         /* Setup SFP module if there is one present. */
1410         if (hw->phy.sfp_setup_needed) {
1411                 status = hw->mac.ops.setup_sfp(hw);
1412                 hw->phy.sfp_setup_needed = false;
1413         }
1414
1415         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1416                 return status;
1417
1418         /* Reset PHY */
1419         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1420                 hw->phy.ops.reset(hw);
1421
1422 mac_reset_top:
1423         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1424          * If link reset is used when link is up, it might reset the PHY when
1425          * mng is using it.  If link is down or the flag to force full link
1426          * reset is set, then perform link reset.
1427          */
1428         ctrl = IXGBE_CTRL_LNK_RST;
1429         if (!hw->force_full_reset) {
1430                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1431                 if (link_up)
1432                         ctrl = IXGBE_CTRL_RST;
1433         }
1434
1435         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1436         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1437         IXGBE_WRITE_FLUSH(hw);
1438
1439         /* Poll for reset bit to self-clear meaning reset is complete */
1440         for (i = 0; i < 10; i++) {
1441                 usec_delay(1);
1442                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1443                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1444                         break;
1445         }
1446
1447         if (ctrl & IXGBE_CTRL_RST_MASK) {
1448                 status = IXGBE_ERR_RESET_FAILED;
1449                 DEBUGOUT("Reset polling failed to complete.\n");
1450         }
1451
1452         msec_delay(50);
1453
1454         /* Double resets are required for recovery from certain error
1455          * conditions.  Between resets, it is necessary to stall to
1456          * allow time for any pending HW events to complete.
1457          */
1458         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1459                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1460                 goto mac_reset_top;
1461         }
1462
1463         /* Store the permanent mac address */
1464         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1465
1466         /* Store MAC address from RAR0, clear receive address registers, and
1467          * clear the multicast table.  Also reset num_rar_entries to 128,
1468          * since we modify this value when programming the SAN MAC address.
1469          */
1470         hw->mac.num_rar_entries = 128;
1471         hw->mac.ops.init_rx_addrs(hw);
1472
1473
1474         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1475                 ixgbe_setup_mux_ctl(hw);
1476
1477         return status;
1478 }
1479
1480 /**
1481  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1482  * @hw: pointer to hardware structure
1483  */
1484 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1485 {
1486         u32 status;
1487         u16 reg;
1488
1489         status = hw->phy.ops.read_reg(hw,
1490                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1491                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1492                                       &reg);
1493
1494         if (status != IXGBE_SUCCESS)
1495                 return status;
1496
1497         /* If PHY FW reset completed bit is set then this is the first
1498          * SW instance after a power on so the PHY FW must be un-stalled.
1499          */
1500         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1501                 status = hw->phy.ops.read_reg(hw,
1502                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1503                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1504                                         &reg);
1505
1506                 if (status != IXGBE_SUCCESS)
1507                         return status;
1508
1509                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1510
1511                 status = hw->phy.ops.write_reg(hw,
1512                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1513                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1514                                         reg);
1515
1516                 if (status != IXGBE_SUCCESS)
1517                         return status;
1518         }
1519
1520         return status;
1521 }
1522
1523 /**
1524  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1525  *  @hw: pointer to hardware structure
1526  *
1527  *  Configures the integrated KR PHY.
1528  **/
1529 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1530 {
1531         s32 status;
1532         u32 reg_val;
1533
1534         status = ixgbe_read_iosf_sb_reg_x550(hw,
1535                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1536                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1537         if (status)
1538                 return status;
1539
1540         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1541         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1542                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1543         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1544                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1545
1546         /* Advertise 10G support. */
1547         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1548                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1549
1550         /* Advertise 1G support. */
1551         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1552                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1553
1554         /* Restart auto-negotiation. */
1555         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1556         status = ixgbe_write_iosf_sb_reg_x550(hw,
1557                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1558                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1559
1560         return status;
1561 }
1562
1563 /**
1564  *  ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1565  *  @hw: pointer to hardware structure
1566  *
1567  *  Configures the integrated KX4 PHY.
1568  **/
1569 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1570 {
1571         s32 status;
1572         u32 reg_val;
1573
1574         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1575                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, &reg_val);
1576         if (status)
1577                 return status;
1578
1579         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1580                         IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1581
1582         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1583
1584         /* Advertise 10G support. */
1585         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1586                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1587
1588         /* Advertise 1G support. */
1589         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1590                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1591
1592         /* Restart auto-negotiation. */
1593         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1594         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1595                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, reg_val);
1596
1597         return status;
1598 }
1599
1600 /**
1601  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1602  *  @hw: pointer to hardware structure
1603  *  @speed: the link speed to force
1604  *
1605  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1606  *  internal and external PHY at a specific speed, without autonegotiation.
1607  **/
1608 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1609 {
1610         s32 status;
1611         u32 reg_val;
1612
1613         /* Disable AN and force speed to 10G Serial. */
1614         status = ixgbe_read_iosf_sb_reg_x550(hw,
1615                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1616                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1617         if (status != IXGBE_SUCCESS)
1618                 return status;
1619
1620         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1621         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1622
1623         /* Select forced link speed for internal PHY. */
1624         switch (*speed) {
1625         case IXGBE_LINK_SPEED_10GB_FULL:
1626                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1627                 break;
1628         case IXGBE_LINK_SPEED_1GB_FULL:
1629                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1630                 break;
1631         default:
1632                 /* Other link speeds are not supported by internal KR PHY. */
1633                 return IXGBE_ERR_LINK_SETUP;
1634         }
1635
1636         status = ixgbe_write_iosf_sb_reg_x550(hw,
1637                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1638                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1639         if (status != IXGBE_SUCCESS)
1640                 return status;
1641
1642         /* Disable training protocol FSM. */
1643         status = ixgbe_read_iosf_sb_reg_x550(hw,
1644                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1645                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1646         if (status != IXGBE_SUCCESS)
1647                 return status;
1648         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1649         status = ixgbe_write_iosf_sb_reg_x550(hw,
1650                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1651                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1652         if (status != IXGBE_SUCCESS)
1653                 return status;
1654
1655         /* Disable Flex from training TXFFE. */
1656         status = ixgbe_read_iosf_sb_reg_x550(hw,
1657                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1658                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1659         if (status != IXGBE_SUCCESS)
1660                 return status;
1661         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1662         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1663         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1664         status = ixgbe_write_iosf_sb_reg_x550(hw,
1665                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1666                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1667         if (status != IXGBE_SUCCESS)
1668                 return status;
1669         status = ixgbe_read_iosf_sb_reg_x550(hw,
1670                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1671                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1672         if (status != IXGBE_SUCCESS)
1673                 return status;
1674         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1675         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1676         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1677         status = ixgbe_write_iosf_sb_reg_x550(hw,
1678                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1679                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1680         if (status != IXGBE_SUCCESS)
1681                 return status;
1682
1683         /* Enable override for coefficients. */
1684         status = ixgbe_read_iosf_sb_reg_x550(hw,
1685                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1686                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1687         if (status != IXGBE_SUCCESS)
1688                 return status;
1689         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1690         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1691         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1692         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1693         status = ixgbe_write_iosf_sb_reg_x550(hw,
1694                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1695                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1696         if (status != IXGBE_SUCCESS)
1697                 return status;
1698
1699         /* Toggle port SW reset by AN reset. */
1700         status = ixgbe_read_iosf_sb_reg_x550(hw,
1701                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1702                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1703         if (status != IXGBE_SUCCESS)
1704                 return status;
1705         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1706         status = ixgbe_write_iosf_sb_reg_x550(hw,
1707                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1708                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1709
1710         return status;
1711 }
1712
1713 /**
1714  *  ixgbe_setup_mac_link_sfp_x550em - Configure the CS4227 & KR PHY for SFP
1715  *  @hw: pointer to hardware structure
1716  *
1717  *  Configure the external CS4227 PHY and the integrated KR PHY for SFP support.
1718  **/
1719 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1720                                     ixgbe_link_speed speed,
1721                                     bool autoneg_wait_to_complete)
1722 {
1723         s32 ret_val;
1724         u16 reg_slice, reg_val;
1725         bool setup_linear = false;
1726         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1727
1728         /* Check if SFP module is supported and linear */
1729         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1730
1731         /* If no SFP module present, then return success. Return success since
1732          * there is no reason to configure CS4227 and SFP not present error is
1733          * not excepted in the setup MAC link flow.
1734          */
1735         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1736                 return IXGBE_SUCCESS;
1737
1738         if (ret_val != IXGBE_SUCCESS)
1739                 return ret_val;
1740
1741         /* Configure CS4227 for connection rate. */
1742         reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1743         reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1744         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1745                                            reg_val);
1746
1747         /* Configure CS4227 for connection type. */
1748         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1749         if (setup_linear)
1750                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1751         else
1752                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1753         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1754                                            reg_val);
1755
1756         reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1757         reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1758         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1759                                            reg_val);
1760
1761         /* Configure CS4227 for connection type. */
1762         reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1763         if (setup_linear)
1764                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1765         else
1766                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1767         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1768                                            reg_val);
1769
1770         /* Configure the internal PHY. */
1771         ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1772
1773         return ret_val;
1774 }
1775
1776 /**
1777  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1778  * @hw: point to hardware structure
1779  *
1780  * Configures the link between the integrated KR PHY and the external X557 PHY
1781  * The driver will call this function when it gets a link status change
1782  * interrupt from the X557 PHY. This function configures the link speed
1783  * between the PHYs to match the link speed of the BASE-T link.
1784  *
1785  * A return of a non-zero value indicates an error, and the base driver should
1786  * not report link up.
1787  */
1788 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1789 {
1790         u32 status;
1791         u16 autoneg_status, speed;
1792         ixgbe_link_speed force_speed;
1793
1794         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1795                 return IXGBE_ERR_CONFIG;
1796
1797         /* read this twice back to back to indicate current status */
1798         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1799                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1800                                       &autoneg_status);
1801         if (status != IXGBE_SUCCESS)
1802                 return status;
1803
1804         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1805                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1806                                       &autoneg_status);
1807         if (status != IXGBE_SUCCESS)
1808                 return status;
1809
1810         /* If link is not up, then there is no setup necessary so return  */
1811         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1812                 return IXGBE_SUCCESS;
1813
1814         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1815                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1816                                       &speed);
1817
1818         /* clear everything but the speed and duplex bits */
1819         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1820
1821         switch (speed) {
1822         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1823                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1824                 break;
1825         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1826                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1827                 break;
1828         default:
1829                 /* Internal PHY does not support anything else */
1830                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1831         }
1832
1833         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1834 }
1835
1836 /**
1837  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1838  *  @hw: pointer to hardware structure
1839  *
1840  *  Configures the integrated KR PHY to use internal loopback mode.
1841  **/
1842 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1843 {
1844         s32 status;
1845         u32 reg_val;
1846
1847         /* Disable AN and force speed to 10G Serial. */
1848         status = ixgbe_read_iosf_sb_reg_x550(hw,
1849                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1850                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1851         if (status != IXGBE_SUCCESS)
1852                 return status;
1853         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1854         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1855         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1856         status = ixgbe_write_iosf_sb_reg_x550(hw,
1857                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1858                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1859         if (status != IXGBE_SUCCESS)
1860                 return status;
1861
1862         /* Set near-end loopback clocks. */
1863         status = ixgbe_read_iosf_sb_reg_x550(hw,
1864                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1865                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1866         if (status != IXGBE_SUCCESS)
1867                 return status;
1868         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1869         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1870         status = ixgbe_write_iosf_sb_reg_x550(hw,
1871                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1872                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1873         if (status != IXGBE_SUCCESS)
1874                 return status;
1875
1876         /* Set loopback enable. */
1877         status = ixgbe_read_iosf_sb_reg_x550(hw,
1878                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1879                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1880         if (status != IXGBE_SUCCESS)
1881                 return status;
1882         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1883         status = ixgbe_write_iosf_sb_reg_x550(hw,
1884                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1885                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1886         if (status != IXGBE_SUCCESS)
1887                 return status;
1888
1889         /* Training bypass. */
1890         status = ixgbe_read_iosf_sb_reg_x550(hw,
1891                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1892                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1893         if (status != IXGBE_SUCCESS)
1894                 return status;
1895         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1896         status = ixgbe_write_iosf_sb_reg_x550(hw,
1897                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1898                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1899
1900         return status;
1901 }
1902
1903 /**
1904  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1905  *  assuming that the semaphore is already obtained.
1906  *  @hw: pointer to hardware structure
1907  *  @offset: offset of  word in the EEPROM to read
1908  *  @data: word read from the EEPROM
1909  *
1910  *  Reads a 16 bit word from the EEPROM using the hostif.
1911  **/
1912 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1913                                    u16 *data)
1914 {
1915         s32 status;
1916         struct ixgbe_hic_read_shadow_ram buffer;
1917
1918         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1919         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1920         buffer.hdr.req.buf_lenh = 0;
1921         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1922         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1923
1924         /* convert offset from words to bytes */
1925         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1926         /* one word */
1927         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1928
1929         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1930                                               sizeof(buffer),
1931                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1932
1933         if (status)
1934                 return status;
1935
1936         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1937                                           FW_NVM_DATA_OFFSET);
1938
1939         return 0;
1940 }
1941
1942 /**
1943  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1944  *  @hw: pointer to hardware structure
1945  *  @offset: offset of  word in the EEPROM to read
1946  *  @data: word read from the EEPROM
1947  *
1948  *  Reads a 16 bit word from the EEPROM using the hostif.
1949  **/
1950 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1951                               u16 *data)
1952 {
1953         s32 status = IXGBE_SUCCESS;
1954
1955         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1956
1957         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1958             IXGBE_SUCCESS) {
1959                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1960                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1961         } else {
1962                 status = IXGBE_ERR_SWFW_SYNC;
1963         }
1964
1965         return status;
1966 }
1967
1968 /**
1969  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1970  *  @hw: pointer to hardware structure
1971  *  @offset: offset of  word in the EEPROM to read
1972  *  @words: number of words
1973  *  @data: word(s) read from the EEPROM
1974  *
1975  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
1976  **/
1977 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1978                                      u16 offset, u16 words, u16 *data)
1979 {
1980         struct ixgbe_hic_read_shadow_ram buffer;
1981         u32 current_word = 0;
1982         u16 words_to_read;
1983         s32 status;
1984         u32 i;
1985
1986         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1987
1988         /* Take semaphore for the entire operation. */
1989         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1990         if (status) {
1991                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1992                 return status;
1993         }
1994         while (words) {
1995                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1996                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1997                 else
1998                         words_to_read = words;
1999
2000                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2001                 buffer.hdr.req.buf_lenh = 0;
2002                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2003                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2004
2005                 /* convert offset from words to bytes */
2006                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2007                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2008
2009                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2010                                                       sizeof(buffer),
2011                                                       IXGBE_HI_COMMAND_TIMEOUT,
2012                                                       false);
2013
2014                 if (status) {
2015                         DEBUGOUT("Host interface command failed\n");
2016                         goto out;
2017                 }
2018
2019                 for (i = 0; i < words_to_read; i++) {
2020                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2021                                   2 * i;
2022                         u32 value = IXGBE_READ_REG(hw, reg);
2023
2024                         data[current_word] = (u16)(value & 0xffff);
2025                         current_word++;
2026                         i++;
2027                         if (i < words_to_read) {
2028                                 value >>= 16;
2029                                 data[current_word] = (u16)(value & 0xffff);
2030                                 current_word++;
2031                         }
2032                 }
2033                 words -= words_to_read;
2034         }
2035
2036 out:
2037         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2038         return status;
2039 }
2040
2041 /**
2042  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2043  *  @hw: pointer to hardware structure
2044  *  @offset: offset of  word in the EEPROM to write
2045  *  @data: word write to the EEPROM
2046  *
2047  *  Write a 16 bit word to the EEPROM using the hostif.
2048  **/
2049 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2050                                     u16 data)
2051 {
2052         s32 status;
2053         struct ixgbe_hic_write_shadow_ram buffer;
2054
2055         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2056
2057         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2058         buffer.hdr.req.buf_lenh = 0;
2059         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2060         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2061
2062          /* one word */
2063         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2064         buffer.data = data;
2065         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2066
2067         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2068                                               sizeof(buffer),
2069                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2070
2071         return status;
2072 }
2073
2074 /**
2075  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2076  *  @hw: pointer to hardware structure
2077  *  @offset: offset of  word in the EEPROM to write
2078  *  @data: word write to the EEPROM
2079  *
2080  *  Write a 16 bit word to the EEPROM using the hostif.
2081  **/
2082 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2083                                u16 data)
2084 {
2085         s32 status = IXGBE_SUCCESS;
2086
2087         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2088
2089         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2090             IXGBE_SUCCESS) {
2091                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2092                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2093         } else {
2094                 DEBUGOUT("write ee hostif failed to get semaphore");
2095                 status = IXGBE_ERR_SWFW_SYNC;
2096         }
2097
2098         return status;
2099 }
2100
2101 /**
2102  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2103  *  @hw: pointer to hardware structure
2104  *  @offset: offset of  word in the EEPROM to write
2105  *  @words: number of words
2106  *  @data: word(s) write to the EEPROM
2107  *
2108  *  Write a 16 bit word(s) to the EEPROM using the hostif.
2109  **/
2110 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2111                                       u16 offset, u16 words, u16 *data)
2112 {
2113         s32 status = IXGBE_SUCCESS;
2114         u32 i = 0;
2115
2116         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2117
2118         /* Take semaphore for the entire operation. */
2119         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2120         if (status != IXGBE_SUCCESS) {
2121                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2122                 goto out;
2123         }
2124
2125         for (i = 0; i < words; i++) {
2126                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2127                                                          data[i]);
2128
2129                 if (status != IXGBE_SUCCESS) {
2130                         DEBUGOUT("Eeprom buffered write failed\n");
2131                         break;
2132                 }
2133         }
2134
2135         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2136 out:
2137
2138         return status;
2139 }
2140
2141 /**
2142  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2143  * @hw: pointer to hardware structure
2144  * @ptr: pointer offset in eeprom
2145  * @size: size of section pointed by ptr, if 0 first word will be used as size
2146  * @csum: address of checksum to update
2147  *
2148  * Returns error status for any failure
2149  */
2150 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2151                                    u16 size, u16 *csum, u16 *buffer,
2152                                    u32 buffer_size)
2153 {
2154         u16 buf[256];
2155         s32 status;
2156         u16 length, bufsz, i, start;
2157         u16 *local_buffer;
2158
2159         bufsz = sizeof(buf) / sizeof(buf[0]);
2160
2161         /* Read a chunk at the pointer location */
2162         if (!buffer) {
2163                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2164                 if (status) {
2165                         DEBUGOUT("Failed to read EEPROM image\n");
2166                         return status;
2167                 }
2168                 local_buffer = buf;
2169         } else {
2170                 if (buffer_size < ptr)
2171                         return  IXGBE_ERR_PARAM;
2172                 local_buffer = &buffer[ptr];
2173         }
2174
2175         if (size) {
2176                 start = 0;
2177                 length = size;
2178         } else {
2179                 start = 1;
2180                 length = local_buffer[0];
2181
2182                 /* Skip pointer section if length is invalid. */
2183                 if (length == 0xFFFF || length == 0 ||
2184                     (ptr + length) >= hw->eeprom.word_size)
2185                         return IXGBE_SUCCESS;
2186         }
2187
2188         if (buffer && ((u32)start + (u32)length > buffer_size))
2189                 return IXGBE_ERR_PARAM;
2190
2191         for (i = start; length; i++, length--) {
2192                 if (i == bufsz && !buffer) {
2193                         ptr += bufsz;
2194                         i = 0;
2195                         if (length < bufsz)
2196                                 bufsz = length;
2197
2198                         /* Read a chunk at the pointer location */
2199                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2200                                                                   bufsz, buf);
2201                         if (status) {
2202                                 DEBUGOUT("Failed to read EEPROM image\n");
2203                                 return status;
2204                         }
2205                 }
2206                 *csum += local_buffer[i];
2207         }
2208         return IXGBE_SUCCESS;
2209 }
2210
2211 /**
2212  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2213  *  @hw: pointer to hardware structure
2214  *  @buffer: pointer to buffer containing calculated checksum
2215  *  @buffer_size: size of buffer
2216  *
2217  *  Returns a negative error code on error, or the 16-bit checksum
2218  **/
2219 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2220 {
2221         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2222         u16 *local_buffer;
2223         s32 status;
2224         u16 checksum = 0;
2225         u16 pointer, i, size;
2226
2227         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2228
2229         hw->eeprom.ops.init_params(hw);
2230
2231         if (!buffer) {
2232                 /* Read pointer area */
2233                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2234                                                      IXGBE_EEPROM_LAST_WORD + 1,
2235                                                      eeprom_ptrs);
2236                 if (status) {
2237                         DEBUGOUT("Failed to read EEPROM image\n");
2238                         return status;
2239                 }
2240                 local_buffer = eeprom_ptrs;
2241         } else {
2242                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2243                         return IXGBE_ERR_PARAM;
2244                 local_buffer = buffer;
2245         }
2246
2247         /*
2248          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2249          * checksum word itself
2250          */
2251         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2252                 if (i != IXGBE_EEPROM_CHECKSUM)
2253                         checksum += local_buffer[i];
2254
2255         /*
2256          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2257          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2258          */
2259         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2260                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2261                         continue;
2262
2263                 pointer = local_buffer[i];
2264
2265                 /* Skip pointer section if the pointer is invalid. */
2266                 if (pointer == 0xFFFF || pointer == 0 ||
2267                     pointer >= hw->eeprom.word_size)
2268                         continue;
2269
2270                 switch (i) {
2271                 case IXGBE_PCIE_GENERAL_PTR:
2272                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2273                         break;
2274                 case IXGBE_PCIE_CONFIG0_PTR:
2275                 case IXGBE_PCIE_CONFIG1_PTR:
2276                         size = IXGBE_PCIE_CONFIG_SIZE;
2277                         break;
2278                 default:
2279                         size = 0;
2280                         break;
2281                 }
2282
2283                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2284                                                 buffer, buffer_size);
2285                 if (status)
2286                         return status;
2287         }
2288
2289         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2290
2291         return (s32)checksum;
2292 }
2293
2294 /**
2295  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2296  *  @hw: pointer to hardware structure
2297  *
2298  *  Returns a negative error code on error, or the 16-bit checksum
2299  **/
2300 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2301 {
2302         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2303 }
2304
2305 /**
2306  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2307  *  @hw: pointer to hardware structure
2308  *  @checksum_val: calculated checksum
2309  *
2310  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2311  *  caller does not need checksum_val, the value can be NULL.
2312  **/
2313 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2314 {
2315         s32 status;
2316         u16 checksum;
2317         u16 read_checksum = 0;
2318
2319         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2320
2321         /* Read the first word from the EEPROM. If this times out or fails, do
2322          * not continue or we could be in for a very long wait while every
2323          * EEPROM read fails
2324          */
2325         status = hw->eeprom.ops.read(hw, 0, &checksum);
2326         if (status) {
2327                 DEBUGOUT("EEPROM read failed\n");
2328                 return status;
2329         }
2330
2331         status = hw->eeprom.ops.calc_checksum(hw);
2332         if (status < 0)
2333                 return status;
2334
2335         checksum = (u16)(status & 0xffff);
2336
2337         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2338                                            &read_checksum);
2339         if (status)
2340                 return status;
2341
2342         /* Verify read checksum from EEPROM is the same as
2343          * calculated checksum
2344          */
2345         if (read_checksum != checksum) {
2346                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2347                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2348                              "Invalid EEPROM checksum");
2349         }
2350
2351         /* If the user cares, return the calculated checksum */
2352         if (checksum_val)
2353                 *checksum_val = checksum;
2354
2355         return status;
2356 }
2357
2358 /**
2359  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2360  * @hw: pointer to hardware structure
2361  *
2362  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2363  * checksum and updates the EEPROM and instructs the hardware to update
2364  * the flash.
2365  **/
2366 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2367 {
2368         s32 status;
2369         u16 checksum = 0;
2370
2371         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2372
2373         /* Read the first word from the EEPROM. If this times out or fails, do
2374          * not continue or we could be in for a very long wait while every
2375          * EEPROM read fails
2376          */
2377         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2378         if (status) {
2379                 DEBUGOUT("EEPROM read failed\n");
2380                 return status;
2381         }
2382
2383         status = ixgbe_calc_eeprom_checksum_X550(hw);
2384         if (status < 0)
2385                 return status;
2386
2387         checksum = (u16)(status & 0xffff);
2388
2389         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2390                                             checksum);
2391         if (status)
2392                 return status;
2393
2394         status = ixgbe_update_flash_X550(hw);
2395
2396         return status;
2397 }
2398
2399 /**
2400  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2401  *  @hw: pointer to hardware structure
2402  *
2403  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2404  **/
2405 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2406 {
2407         s32 status = IXGBE_SUCCESS;
2408         union ixgbe_hic_hdr2 buffer;
2409
2410         DEBUGFUNC("ixgbe_update_flash_X550");
2411
2412         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2413         buffer.req.buf_lenh = 0;
2414         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2415         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2416
2417         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2418                                               sizeof(buffer),
2419                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2420
2421         return status;
2422 }
2423
2424 /**
2425  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2426  *  @hw: pointer to hardware structure
2427  *
2428  *  Determines physical layer capabilities of the current configuration.
2429  **/
2430 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2431 {
2432         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2433         u16 ext_ability = 0;
2434
2435         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2436
2437         hw->phy.ops.identify(hw);
2438
2439         switch (hw->phy.type) {
2440         case ixgbe_phy_x550em_kr:
2441                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2442                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2443                 break;
2444         case ixgbe_phy_x550em_kx4:
2445                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2446                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2447                 break;
2448         case ixgbe_phy_x550em_ext_t:
2449                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2450                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2451                                      &ext_ability);
2452                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2453                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2454                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2455                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2456                 break;
2457         default:
2458                 break;
2459         }
2460
2461         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2462                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2463
2464         return physical_layer;
2465 }
2466
2467 /**
2468  * ixgbe_get_bus_info_x550em - Set PCI bus info
2469  * @hw: pointer to hardware structure
2470  *
2471  * Sets bus link width and speed to unknown because X550em is
2472  * not a PCI device.
2473  **/
2474 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2475 {
2476
2477         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2478
2479         hw->bus.width = ixgbe_bus_width_unknown;
2480         hw->bus.speed = ixgbe_bus_speed_unknown;
2481
2482         hw->mac.ops.set_lan_id(hw);
2483
2484         return IXGBE_SUCCESS;
2485 }
2486
2487 /**
2488  * ixgbe_disable_rx_x550 - Disable RX unit
2489  *
2490  * Enables the Rx DMA unit for x550
2491  **/
2492 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2493 {
2494         u32 rxctrl, pfdtxgswc;
2495         s32 status;
2496         struct ixgbe_hic_disable_rxen fw_cmd;
2497
2498         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2499
2500         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2501         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2502                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2503                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2504                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2505                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2506                         hw->mac.set_lben = true;
2507                 } else {
2508                         hw->mac.set_lben = false;
2509                 }
2510
2511                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2512                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2513                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2514                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2515
2516                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2517                                         sizeof(struct ixgbe_hic_disable_rxen),
2518                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2519
2520                 /* If we fail - disable RX using register write */
2521                 if (status) {
2522                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2523                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2524                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2525                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2526                         }
2527                 }
2528         }
2529 }
2530
2531 /**
2532  * ixgbe_enter_lplu_x550em - Transition to low power states
2533  *  @hw: pointer to hardware structure
2534  *
2535  * Configures Low Power Link Up on transition to low power states
2536  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2537  * X557 PHY immediately prior to entering LPLU.
2538  **/
2539 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2540 {
2541         u16 autoneg_status, an_10g_cntl_reg, autoneg_reg, speed;
2542         s32 status;
2543         ixgbe_link_speed lcd_speed;
2544         u32 save_autoneg;
2545
2546         /* If blocked by MNG FW, then don't restart AN */
2547         if (ixgbe_check_reset_blocked(hw))
2548                 return IXGBE_SUCCESS;
2549
2550         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2551                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2552                                       &autoneg_status);
2553
2554         if (status != IXGBE_SUCCESS)
2555                 return status;
2556
2557         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2558
2559         if (status != IXGBE_SUCCESS)
2560                 return status;
2561
2562         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2563          * disabled, then force link down by entering low power mode.
2564          */
2565         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS) ||
2566             !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2567             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2568                 return ixgbe_set_copper_phy_power(hw, FALSE);
2569
2570         /* Determine LCD */
2571         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2572
2573         if (status != IXGBE_SUCCESS)
2574                 return status;
2575
2576         /* If no valid LCD link speed, then force link down and exit. */
2577         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2578                 return ixgbe_set_copper_phy_power(hw, FALSE);
2579
2580         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2581                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2582                                       &speed);
2583
2584         if (status != IXGBE_SUCCESS)
2585                 return status;
2586
2587         /* clear everything but the speed bits */
2588         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2589
2590         /* If current speed is already LCD, then exit. */
2591         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2592              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2593             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2594              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2595                 return status;
2596
2597         /* Clear AN completed indication */
2598         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2599                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2600                                       &autoneg_status);
2601
2602         if (status != IXGBE_SUCCESS)
2603                 return status;
2604
2605         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2606                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2607                              &an_10g_cntl_reg);
2608
2609         if (status != IXGBE_SUCCESS)
2610                 return status;
2611
2612         status = hw->phy.ops.read_reg(hw,
2613                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2614                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2615                              &autoneg_reg);
2616
2617         if (status != IXGBE_SUCCESS)
2618                 return status;
2619
2620         save_autoneg = hw->phy.autoneg_advertised;
2621
2622         /* Setup link at least common link speed */
2623         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2624
2625         /* restore autoneg from before setting lplu speed */
2626         hw->phy.autoneg_advertised = save_autoneg;
2627
2628         return status;
2629 }
2630
2631 /**
2632  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2633  *  @hw: pointer to hardware structure
2634  *  @lcd_speed: pointer to lowest common link speed
2635  *
2636  * Determine lowest common link speed with link partner.
2637  **/
2638 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2639 {
2640         u16 an_lp_status;
2641         s32 status;
2642         u16 word = hw->eeprom.ctrl_word_3;
2643
2644         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2645
2646         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2647                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2648                                       &an_lp_status);
2649
2650         if (status != IXGBE_SUCCESS)
2651                 return status;
2652
2653         /* If link partner advertised 1G, return 1G */
2654         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2655                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2656                 return status;
2657         }
2658
2659         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2660         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2661             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2662                 return status;
2663
2664         /* Link partner not capable of lower speeds, return 10G */
2665         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2666         return status;
2667 }
2668
2669 /**
2670  *  ixgbe_setup_fc_X550em - Set up flow control
2671  *  @hw: pointer to hardware structure
2672  *
2673  *  Called at init time to set up flow control.
2674  **/
2675 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2676 {
2677         s32 ret_val = IXGBE_SUCCESS;
2678         u32 pause, asm_dir, reg_val;
2679
2680         DEBUGFUNC("ixgbe_setup_fc_X550em");
2681
2682         /* Validate the requested mode */
2683         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2684                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2685                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2686                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2687                 goto out;
2688         }
2689
2690         /* 10gig parts do not have a word in the EEPROM to determine the
2691          * default flow control setting, so we explicitly set it to full.
2692          */
2693         if (hw->fc.requested_mode == ixgbe_fc_default)
2694                 hw->fc.requested_mode = ixgbe_fc_full;
2695
2696         /* Determine PAUSE and ASM_DIR bits. */
2697         switch (hw->fc.requested_mode) {
2698         case ixgbe_fc_none:
2699                 pause = 0;
2700                 asm_dir = 0;
2701                 break;
2702         case ixgbe_fc_tx_pause:
2703                 pause = 0;
2704                 asm_dir = 1;
2705                 break;
2706         case ixgbe_fc_rx_pause:
2707                 /* Rx Flow control is enabled and Tx Flow control is
2708                  * disabled by software override. Since there really
2709                  * isn't a way to advertise that we are capable of RX
2710                  * Pause ONLY, we will advertise that we support both
2711                  * symmetric and asymmetric Rx PAUSE, as such we fall
2712                  * through to the fc_full statement.  Later, we will
2713                  * disable the adapter's ability to send PAUSE frames.
2714                  */
2715         case ixgbe_fc_full:
2716                 pause = 1;
2717                 asm_dir = 1;
2718                 break;
2719         default:
2720                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2721                         "Flow control param set incorrectly\n");
2722                 ret_val = IXGBE_ERR_CONFIG;
2723                 goto out;
2724         }
2725
2726         if (hw->phy.media_type == ixgbe_media_type_backplane) {
2727                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2728                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2729                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2730                 if (ret_val != IXGBE_SUCCESS)
2731                         goto out;
2732                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2733                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2734                 if (pause)
2735                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2736                 if (asm_dir)
2737                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2738                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2739                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2740                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2741
2742                 /* Not all devices fully support AN. */
2743                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR)
2744                         hw->fc.disable_fc_autoneg = true;
2745         }
2746
2747 out:
2748         return ret_val;
2749 }
2750
2751 /**
2752  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2753  * @hw: pointer to hardware structure
2754  * @state: set mux if 1, clear if 0
2755  */
2756 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2757 {
2758         u32 esdp;
2759
2760         if (!hw->bus.lan_id)
2761                 return;
2762         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2763         if (state)
2764                 esdp |= IXGBE_ESDP_SDP1;
2765         else
2766                 esdp &= ~IXGBE_ESDP_SDP1;
2767         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2768         IXGBE_WRITE_FLUSH(hw);
2769 }
2770
2771 /**
2772  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2773  *  @hw: pointer to hardware structure
2774  *  @mask: Mask to specify which semaphore to acquire
2775  *
2776  *  Acquires the SWFW semaphore and sets the I2C MUX
2777  **/
2778 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2779 {
2780         s32 status;
2781
2782         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2783
2784         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2785         if (status)
2786                 return status;
2787
2788         if (mask & IXGBE_GSSR_I2C_MASK)
2789                 ixgbe_set_mux(hw, 1);
2790
2791         return IXGBE_SUCCESS;
2792 }
2793
2794 /**
2795  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2796  *  @hw: pointer to hardware structure
2797  *  @mask: Mask to specify which semaphore to release
2798  *
2799  *  Releases the SWFW semaphore and sets the I2C MUX
2800  **/
2801 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2802 {
2803         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2804
2805         if (mask & IXGBE_GSSR_I2C_MASK)
2806                 ixgbe_set_mux(hw, 0);
2807
2808         ixgbe_release_swfw_sync_X540(hw, mask);
2809 }
2810
2811 /**
2812  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2813  * @hw: pointer to hardware structure
2814  *
2815  * Handle external Base T PHY interrupt. If high temperature
2816  * failure alarm then return error, else if link status change
2817  * then setup internal/external PHY link
2818  *
2819  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2820  * failure alarm, else return PHY access status.
2821  */
2822 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2823 {
2824         bool lsc;
2825         u32 status;
2826
2827         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2828
2829         if (status != IXGBE_SUCCESS)
2830                 return status;
2831
2832         if (lsc)
2833                 return ixgbe_setup_internal_phy_t_x550em(hw);
2834
2835         return IXGBE_SUCCESS;
2836 }
2837
2838 /**
2839  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
2840  * @hw: pointer to hardware structure
2841  * @speed: new link speed
2842  * @autoneg_wait_to_complete: true when waiting for completion is needed
2843  *
2844  * Setup internal/external PHY link speed based on link speed, then set
2845  * external PHY auto advertised link speed.
2846  *
2847  * Returns error status for any failure
2848  **/
2849 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
2850                                   ixgbe_link_speed speed,
2851                                   bool autoneg_wait_to_complete)
2852 {
2853         s32 status;
2854         ixgbe_link_speed force_speed;
2855
2856         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
2857
2858         /* Setup internal/external PHY link speed to iXFI (10G), unless
2859          * only 1G is auto advertised then setup KX link.
2860          */
2861         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2862                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2863         else
2864                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2865
2866         status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
2867
2868         if (status != IXGBE_SUCCESS)
2869                 return status;
2870
2871         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
2872 }
2873
2874 /**
2875  * ixgbe_check_link_t_X550em - Determine link and speed status
2876  * @hw: pointer to hardware structure
2877  * @speed: pointer to link speed
2878  * @link_up: true when link is up
2879  * @link_up_wait_to_complete: bool used to wait for link up or not
2880  *
2881  * Check that both the MAC and X557 external PHY have link.
2882  **/
2883 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
2884                               bool *link_up, bool link_up_wait_to_complete)
2885 {
2886         u32 status;
2887         u16 autoneg_status;
2888
2889         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2890                 return IXGBE_ERR_CONFIG;
2891
2892         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
2893                                               link_up_wait_to_complete);
2894
2895         /* If check link fails or MAC link is not up, then return */
2896         if (status != IXGBE_SUCCESS || !(*link_up))
2897                 return status;
2898
2899         /* MAC link is up, so check external PHY link.
2900          * Read this twice back to back to indicate current status.
2901          */
2902         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2903                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2904                                       &autoneg_status);
2905
2906         if (status != IXGBE_SUCCESS)
2907                 return status;
2908
2909         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2910                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2911                                       &autoneg_status);
2912
2913         if (status != IXGBE_SUCCESS)
2914                 return status;
2915
2916         /* If external PHY link is not up, then indicate link not up */
2917         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
2918                 *link_up = false;
2919
2920         return IXGBE_SUCCESS;
2921 }
2922
2923 /**
2924  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2925  *  @hw: pointer to hardware structure
2926  **/
2927 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2928 {
2929         s32 status;
2930
2931         status = ixgbe_reset_phy_generic(hw);
2932
2933         if (status != IXGBE_SUCCESS)
2934                 return status;
2935
2936         /* Configure Link Status Alarm and Temperature Threshold interrupts */
2937         return ixgbe_enable_lasi_ext_t_x550em(hw);
2938 }