1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
46 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
47 * @hw: pointer to hardware structure
49 * Initialize the function pointers and assign the MAC type for X550.
50 * Does not touch the hardware.
52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
54 struct ixgbe_mac_info *mac = &hw->mac;
55 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
58 DEBUGFUNC("ixgbe_init_ops_X550");
60 ret_val = ixgbe_init_ops_X540(hw);
61 mac->ops.dmac_config = ixgbe_dmac_config_X550;
62 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
63 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
64 mac->ops.setup_eee = ixgbe_setup_eee_X550;
65 mac->ops.set_source_address_pruning =
66 ixgbe_set_source_address_pruning_X550;
67 mac->ops.set_ethertype_anti_spoofing =
68 ixgbe_set_ethertype_anti_spoofing_X550;
70 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
71 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
72 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
73 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
74 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
75 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
76 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
77 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
78 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
80 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
81 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
82 mac->ops.mdd_event = ixgbe_mdd_event_X550;
83 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
84 mac->ops.disable_rx = ixgbe_disable_rx_x550;
85 switch (hw->device_id) {
86 case IXGBE_DEV_ID_X550EM_X_10G_T:
87 case IXGBE_DEV_ID_X550EM_A_10G_T:
88 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
89 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
98 * ixgbe_read_cs4227 - Read CS4227 register
99 * @hw: pointer to hardware structure
100 * @reg: register number to write
101 * @value: pointer to receive value read
103 * Returns status code
105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
107 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
111 * ixgbe_write_cs4227 - Write CS4227 register
112 * @hw: pointer to hardware structure
113 * @reg: register number to write
114 * @value: value to write to register
116 * Returns status code
118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
120 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
124 * ixgbe_read_pe - Read register from port expander
125 * @hw: pointer to hardware structure
126 * @reg: register number to read
127 * @value: pointer to receive read value
129 * Returns status code
131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
135 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
136 if (status != IXGBE_SUCCESS)
137 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
138 "port expander access failed with %d\n", status);
143 * ixgbe_write_pe - Write register to port expander
144 * @hw: pointer to hardware structure
145 * @reg: register number to write
146 * @value: value to write
148 * Returns status code
150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
154 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
155 if (status != IXGBE_SUCCESS)
156 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
157 "port expander access failed with %d\n", status);
162 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
163 * @hw: pointer to hardware structure
165 * This function assumes that the caller has acquired the proper semaphore.
168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
175 /* Trigger hard reset. */
176 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
177 if (status != IXGBE_SUCCESS)
179 reg |= IXGBE_PE_BIT1;
180 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
181 if (status != IXGBE_SUCCESS)
184 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
185 if (status != IXGBE_SUCCESS)
187 reg &= ~IXGBE_PE_BIT1;
188 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
189 if (status != IXGBE_SUCCESS)
192 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
193 if (status != IXGBE_SUCCESS)
195 reg &= ~IXGBE_PE_BIT1;
196 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
197 if (status != IXGBE_SUCCESS)
200 usec_delay(IXGBE_CS4227_RESET_HOLD);
202 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
203 if (status != IXGBE_SUCCESS)
205 reg |= IXGBE_PE_BIT1;
206 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
207 if (status != IXGBE_SUCCESS)
210 /* Wait for the reset to complete. */
211 msec_delay(IXGBE_CS4227_RESET_DELAY);
212 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
213 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
215 if (status == IXGBE_SUCCESS &&
216 value == IXGBE_CS4227_EEPROM_LOAD_OK)
218 msec_delay(IXGBE_CS4227_CHECK_DELAY);
220 if (retry == IXGBE_CS4227_RETRIES) {
221 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
222 "CS4227 reset did not complete.");
223 return IXGBE_ERR_PHY;
226 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
227 if (status != IXGBE_SUCCESS ||
228 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
229 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
230 "CS4227 EEPROM did not load successfully.");
231 return IXGBE_ERR_PHY;
234 return IXGBE_SUCCESS;
238 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
239 * @hw: pointer to hardware structure
241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
243 s32 status = IXGBE_SUCCESS;
244 u32 swfw_mask = hw->phy.phy_semaphore_mask;
248 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
249 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
250 if (status != IXGBE_SUCCESS) {
251 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
252 "semaphore failed with %d", status);
253 msec_delay(IXGBE_CS4227_CHECK_DELAY);
257 /* Get status of reset flow. */
258 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
260 if (status == IXGBE_SUCCESS &&
261 value == IXGBE_CS4227_RESET_COMPLETE)
264 if (status != IXGBE_SUCCESS ||
265 value != IXGBE_CS4227_RESET_PENDING)
268 /* Reset is pending. Wait and check again. */
269 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
270 msec_delay(IXGBE_CS4227_CHECK_DELAY);
273 /* If still pending, assume other instance failed. */
274 if (retry == IXGBE_CS4227_RETRIES) {
275 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
276 if (status != IXGBE_SUCCESS) {
277 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
278 "semaphore failed with %d", status);
283 /* Reset the CS4227. */
284 status = ixgbe_reset_cs4227(hw);
285 if (status != IXGBE_SUCCESS) {
286 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
287 "CS4227 reset failed: %d", status);
291 /* Reset takes so long, temporarily release semaphore in case the
292 * other driver instance is waiting for the reset indication.
294 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
295 IXGBE_CS4227_RESET_PENDING);
296 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
298 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
299 if (status != IXGBE_SUCCESS) {
300 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
301 "semaphore failed with %d", status);
305 /* Record completion for next time. */
306 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
307 IXGBE_CS4227_RESET_COMPLETE);
310 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
311 msec_delay(hw->eeprom.semaphore_delay);
315 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
316 * @hw: pointer to hardware structure
318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
320 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
322 if (hw->bus.lan_id) {
323 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
324 esdp |= IXGBE_ESDP_SDP1_DIR;
326 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
327 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
328 IXGBE_WRITE_FLUSH(hw);
332 * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
333 * @hw: pointer to hardware structure
334 * @reg_addr: 32 bit address of PHY register to read
335 * @dev_type: always unused
336 * @phy_data: Pointer to read data from PHY register
338 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
339 u32 dev_type, u16 *phy_data)
341 u32 i, data, command;
342 UNREFERENCED_1PARAMETER(dev_type);
344 /* Setup and write the read command */
345 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
346 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
347 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
348 IXGBE_MSCA_MDI_COMMAND;
350 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
352 /* Check every 10 usec to see if the access completed.
353 * The MDI Command bit will clear when the operation is
356 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
359 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
360 if (!(command & IXGBE_MSCA_MDI_COMMAND))
364 if (command & IXGBE_MSCA_MDI_COMMAND) {
365 ERROR_REPORT1(IXGBE_ERROR_POLLING,
366 "PHY read command did not complete.\n");
367 return IXGBE_ERR_PHY;
370 /* Read operation is complete. Get the data from MSRWD */
371 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
372 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
373 *phy_data = (u16)data;
375 return IXGBE_SUCCESS;
379 * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
380 * @hw: pointer to hardware structure
381 * @reg_addr: 32 bit PHY register to write
382 * @dev_type: always unused
383 * @phy_data: Data to write to the PHY register
385 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
386 u32 dev_type, u16 phy_data)
389 UNREFERENCED_1PARAMETER(dev_type);
391 /* Put the data in the MDI single read and write data register*/
392 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
394 /* Setup and write the write command */
395 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
396 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
397 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
398 IXGBE_MSCA_MDI_COMMAND;
400 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
402 /* Check every 10 usec to see if the access completed.
403 * The MDI Command bit will clear when the operation is
406 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
409 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
410 if (!(command & IXGBE_MSCA_MDI_COMMAND))
414 if (command & IXGBE_MSCA_MDI_COMMAND) {
415 ERROR_REPORT1(IXGBE_ERROR_POLLING,
416 "PHY write cmd didn't complete\n");
417 return IXGBE_ERR_PHY;
420 return IXGBE_SUCCESS;
424 * ixgbe_identify_phy_x550em - Get PHY type based on device id
425 * @hw: pointer to hardware structure
429 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
431 switch (hw->device_id) {
432 case IXGBE_DEV_ID_X550EM_A_SFP:
433 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
434 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
436 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
438 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
439 return ixgbe_identify_module_generic(hw);
440 case IXGBE_DEV_ID_X550EM_X_SFP:
441 /* set up for CS4227 usage */
442 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
443 ixgbe_setup_mux_ctl(hw);
444 ixgbe_check_cs4227(hw);
447 case IXGBE_DEV_ID_X550EM_A_SFP_N:
448 return ixgbe_identify_module_generic(hw);
450 case IXGBE_DEV_ID_X550EM_X_KX4:
451 hw->phy.type = ixgbe_phy_x550em_kx4;
453 case IXGBE_DEV_ID_X550EM_X_KR:
454 case IXGBE_DEV_ID_X550EM_A_KR:
455 case IXGBE_DEV_ID_X550EM_A_KR_L:
456 hw->phy.type = ixgbe_phy_x550em_kr;
458 case IXGBE_DEV_ID_X550EM_A_10G_T:
459 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
460 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
461 /* Fallthrough to ixgbe_identify_phy_generic */
462 case IXGBE_DEV_ID_X550EM_A_1G_T:
463 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
464 case IXGBE_DEV_ID_X550EM_X_1G_T:
465 case IXGBE_DEV_ID_X550EM_X_10G_T:
466 return ixgbe_identify_phy_generic(hw);
470 return IXGBE_SUCCESS;
473 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
474 u32 device_type, u16 *phy_data)
476 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
477 return IXGBE_NOT_IMPLEMENTED;
480 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
481 u32 device_type, u16 phy_data)
483 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
484 return IXGBE_NOT_IMPLEMENTED;
488 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
489 * @hw: pointer to the hardware structure
490 * @addr: I2C bus address to read from
491 * @reg: I2C device register to read from
492 * @val: pointer to location to receive read value
494 * Returns an error code on error.
496 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
499 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
503 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
504 * @hw: pointer to the hardware structure
505 * @addr: I2C bus address to read from
506 * @reg: I2C device register to read from
507 * @val: pointer to location to receive read value
509 * Returns an error code on error.
512 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
515 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
519 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
520 * @hw: pointer to the hardware structure
521 * @addr: I2C bus address to write to
522 * @reg: I2C device register to write to
523 * @val: value to write
525 * Returns an error code on error.
527 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
528 u8 addr, u16 reg, u16 val)
530 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
534 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
535 * @hw: pointer to the hardware structure
536 * @addr: I2C bus address to write to
537 * @reg: I2C device register to write to
538 * @val: value to write
540 * Returns an error code on error.
543 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
544 u8 addr, u16 reg, u16 val)
546 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
550 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
551 * @hw: pointer to hardware structure
553 * Initialize the function pointers and for MAC type X550EM.
554 * Does not touch the hardware.
556 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
558 struct ixgbe_mac_info *mac = &hw->mac;
559 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
560 struct ixgbe_phy_info *phy = &hw->phy;
563 DEBUGFUNC("ixgbe_init_ops_X550EM");
565 /* Similar to X550 so start there. */
566 ret_val = ixgbe_init_ops_X550(hw);
568 /* Since this function eventually calls
569 * ixgbe_init_ops_540 by design, we are setting
570 * the pointers to NULL explicitly here to overwrite
571 * the values being set in the x540 function.
573 /* Thermal sensor not supported in x550EM */
574 mac->ops.get_thermal_sensor_data = NULL;
575 mac->ops.init_thermal_sensor_thresh = NULL;
576 mac->thermal_sensor_enabled = false;
578 /* FCOE not supported in x550EM */
579 mac->ops.get_san_mac_addr = NULL;
580 mac->ops.set_san_mac_addr = NULL;
581 mac->ops.get_wwn_prefix = NULL;
582 mac->ops.get_fcoe_boot_status = NULL;
584 /* IPsec not supported in x550EM */
585 mac->ops.disable_sec_rx_path = NULL;
586 mac->ops.enable_sec_rx_path = NULL;
588 /* AUTOC register is not present in x550EM. */
589 mac->ops.prot_autoc_read = NULL;
590 mac->ops.prot_autoc_write = NULL;
592 /* X550EM bus type is internal*/
593 hw->bus.type = ixgbe_bus_type_internal;
594 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
597 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
598 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
599 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
600 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
601 mac->ops.get_supported_physical_layer =
602 ixgbe_get_supported_physical_layer_X550em;
604 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
605 mac->ops.setup_fc = ixgbe_setup_fc_generic;
607 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
609 switch (hw->device_id) {
610 case IXGBE_DEV_ID_X550EM_X_KR:
611 case IXGBE_DEV_ID_X550EM_A_KR:
612 case IXGBE_DEV_ID_X550EM_A_KR_L:
615 mac->ops.setup_eee = NULL;
619 phy->ops.init = ixgbe_init_phy_ops_X550em;
620 phy->ops.identify = ixgbe_identify_phy_x550em;
621 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
622 phy->ops.set_phy_power = NULL;
626 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
627 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
628 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
629 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
630 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
631 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
632 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
633 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
639 * ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
640 * @hw: pointer to hardware structure
642 * Initialize the function pointers and for MAC type X550EM_a.
643 * Does not touch the hardware.
645 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
647 struct ixgbe_mac_info *mac = &hw->mac;
650 DEBUGFUNC("ixgbe_init_ops_X550EM_a");
652 /* Start with generic X550EM init */
653 ret_val = ixgbe_init_ops_X550EM(hw);
655 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
656 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
657 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
658 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
660 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
661 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
663 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
664 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
666 switch (mac->ops.get_media_type(hw)) {
667 case ixgbe_media_type_fiber:
668 mac->ops.setup_fc = ixgbe_setup_fc_fiber_x550em_a;
669 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
671 case ixgbe_media_type_backplane:
672 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
673 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
679 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T) ||
680 (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)) {
681 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
682 mac->ops.setup_fc = ixgbe_setup_fc_sgmii_x550em_a;
689 * ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
690 * @hw: pointer to hardware structure
692 * Initialize the function pointers and for MAC type X550EM_x.
693 * Does not touch the hardware.
695 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
697 struct ixgbe_mac_info *mac = &hw->mac;
698 struct ixgbe_link_info *link = &hw->link;
701 DEBUGFUNC("ixgbe_init_ops_X550EM_x");
703 /* Start with generic X550EM init */
704 ret_val = ixgbe_init_ops_X550EM(hw);
706 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
707 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
708 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
709 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
710 link->ops.read_link = ixgbe_read_i2c_combined_generic;
711 link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
712 link->ops.write_link = ixgbe_write_i2c_combined_generic;
713 link->ops.write_link_unlocked =
714 ixgbe_write_i2c_combined_generic_unlocked;
715 link->addr = IXGBE_CS4227;
721 * ixgbe_dmac_config_X550
722 * @hw: pointer to hardware structure
724 * Configure DMA coalescing. If enabling dmac, dmac is activated.
725 * When disabling dmac, dmac enable dmac bit is cleared.
727 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
729 u32 reg, high_pri_tc;
731 DEBUGFUNC("ixgbe_dmac_config_X550");
733 /* Disable DMA coalescing before configuring */
734 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
735 reg &= ~IXGBE_DMACR_DMAC_EN;
736 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
738 /* Disable DMA Coalescing if the watchdog timer is 0 */
739 if (!hw->mac.dmac_config.watchdog_timer)
742 ixgbe_dmac_config_tcs_X550(hw);
744 /* Configure DMA Coalescing Control Register */
745 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
747 /* Set the watchdog timer in units of 40.96 usec */
748 reg &= ~IXGBE_DMACR_DMACWT_MASK;
749 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
751 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
752 /* If fcoe is enabled, set high priority traffic class */
753 if (hw->mac.dmac_config.fcoe_en) {
754 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
755 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
756 IXGBE_DMACR_HIGH_PRI_TC_MASK);
758 reg |= IXGBE_DMACR_EN_MNG_IND;
760 /* Enable DMA coalescing after configuration */
761 reg |= IXGBE_DMACR_DMAC_EN;
762 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
765 return IXGBE_SUCCESS;
769 * ixgbe_dmac_config_tcs_X550
770 * @hw: pointer to hardware structure
772 * Configure DMA coalescing threshold per TC. The dmac enable bit must
773 * be cleared before configuring.
775 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
777 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
779 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
781 /* Configure DMA coalescing enabled */
782 switch (hw->mac.dmac_config.link_speed) {
783 case IXGBE_LINK_SPEED_10_FULL:
784 case IXGBE_LINK_SPEED_100_FULL:
785 pb_headroom = IXGBE_DMACRXT_100M;
787 case IXGBE_LINK_SPEED_1GB_FULL:
788 pb_headroom = IXGBE_DMACRXT_1G;
791 pb_headroom = IXGBE_DMACRXT_10G;
795 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
796 IXGBE_MHADD_MFS_SHIFT) / 1024);
798 /* Set the per Rx packet buffer receive threshold */
799 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
800 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
801 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
803 if (tc < hw->mac.dmac_config.num_tcs) {
805 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
806 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
807 IXGBE_RXPBSIZE_SHIFT;
809 /* Calculate receive buffer threshold in kilobytes */
810 if (rx_pb_size > pb_headroom)
811 rx_pb_size = rx_pb_size - pb_headroom;
815 /* Minimum of MFS shall be set for DMCTH */
816 reg |= (rx_pb_size > maxframe_size_kb) ?
817 rx_pb_size : maxframe_size_kb;
819 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
821 return IXGBE_SUCCESS;
825 * ixgbe_dmac_update_tcs_X550
826 * @hw: pointer to hardware structure
828 * Disables dmac, updates per TC settings, and then enables dmac.
830 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
834 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
836 /* Disable DMA coalescing before configuring */
837 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
838 reg &= ~IXGBE_DMACR_DMAC_EN;
839 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
841 ixgbe_dmac_config_tcs_X550(hw);
843 /* Enable DMA coalescing after configuration */
844 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
845 reg |= IXGBE_DMACR_DMAC_EN;
846 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
848 return IXGBE_SUCCESS;
852 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
853 * @hw: pointer to hardware structure
855 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
856 * ixgbe_hw struct in order to set up EEPROM access.
858 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
860 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
864 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
866 if (eeprom->type == ixgbe_eeprom_uninitialized) {
867 eeprom->semaphore_delay = 10;
868 eeprom->type = ixgbe_flash;
870 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
871 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
872 IXGBE_EEC_SIZE_SHIFT);
873 eeprom->word_size = 1 << (eeprom_size +
874 IXGBE_EEPROM_WORD_SIZE_SHIFT);
876 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
877 eeprom->type, eeprom->word_size);
880 return IXGBE_SUCCESS;
884 * ixgbe_enable_eee_x550 - Enable EEE support
885 * @hw: pointer to hardware structure
887 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
893 if (hw->mac.type == ixgbe_mac_X550) {
894 /* Advertise EEE capability */
895 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
896 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
899 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
900 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
901 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
903 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
904 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
906 return IXGBE_SUCCESS;
909 switch (hw->device_id) {
910 case IXGBE_DEV_ID_X550EM_X_KR:
911 case IXGBE_DEV_ID_X550EM_A_KR:
912 case IXGBE_DEV_ID_X550EM_A_KR_L:
913 status = hw->mac.ops.read_iosf_sb_reg(hw,
914 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
915 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
916 if (status != IXGBE_SUCCESS)
919 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
920 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
922 /* Don't advertise FEC capability when EEE enabled. */
923 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
925 status = hw->mac.ops.write_iosf_sb_reg(hw,
926 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
927 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
928 if (status != IXGBE_SUCCESS)
935 return IXGBE_SUCCESS;
939 * ixgbe_disable_eee_x550 - Disable EEE support
940 * @hw: pointer to hardware structure
942 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
948 if (hw->mac.type == ixgbe_mac_X550) {
949 /* Disable advertised EEE capability */
950 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
951 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
954 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
955 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
956 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
958 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
959 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
961 return IXGBE_SUCCESS;
964 switch (hw->device_id) {
965 case IXGBE_DEV_ID_X550EM_X_KR:
966 case IXGBE_DEV_ID_X550EM_A_KR:
967 case IXGBE_DEV_ID_X550EM_A_KR_L:
968 status = hw->mac.ops.read_iosf_sb_reg(hw,
969 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
970 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
971 if (status != IXGBE_SUCCESS)
974 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
975 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
977 /* Advertise FEC capability when EEE is disabled. */
978 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
980 status = hw->mac.ops.write_iosf_sb_reg(hw,
981 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
982 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
983 if (status != IXGBE_SUCCESS)
990 return IXGBE_SUCCESS;
994 * ixgbe_setup_eee_X550 - Enable/disable EEE support
995 * @hw: pointer to the HW structure
996 * @enable_eee: boolean flag to enable EEE
998 * Enable/disable EEE based on enable_eee flag.
999 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
1003 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
1008 DEBUGFUNC("ixgbe_setup_eee_X550");
1010 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
1011 /* Enable or disable EEE per flag */
1013 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1015 /* Not supported on first revision of X550EM_x. */
1016 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1017 !(IXGBE_FUSES0_REV_MASK &
1018 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1019 return IXGBE_SUCCESS;
1020 status = ixgbe_enable_eee_x550(hw);
1024 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1026 status = ixgbe_disable_eee_x550(hw);
1030 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1032 return IXGBE_SUCCESS;
1036 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1037 * @hw: pointer to hardware structure
1038 * @enable: enable or disable source address pruning
1039 * @pool: Rx pool to set source address pruning for
1041 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1046 /* max rx pool is 63 */
1050 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1051 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1054 pfflp |= (1ULL << pool);
1056 pfflp &= ~(1ULL << pool);
1058 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1059 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1063 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1064 * @hw: pointer to hardware structure
1065 * @enable: enable or disable switch for Ethertype anti-spoofing
1066 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1069 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1070 bool enable, int vf)
1072 int vf_target_reg = vf >> 3;
1073 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1076 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1078 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1080 pfvfspoof |= (1 << vf_target_shift);
1082 pfvfspoof &= ~(1 << vf_target_shift);
1084 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1088 * ixgbe_iosf_wait - Wait for IOSF command completion
1089 * @hw: pointer to hardware structure
1090 * @ctrl: pointer to location to receive final IOSF control value
1092 * Returns failing status on timeout
1094 * Note: ctrl can be NULL if the IOSF control register value is not needed
1096 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1100 /* Check every 10 usec to see if the address cycle completed.
1101 * The SB IOSF BUSY bit will clear when the operation is
1104 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1105 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1106 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1112 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1113 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1114 return IXGBE_ERR_PHY;
1117 return IXGBE_SUCCESS;
1121 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1122 * of the IOSF device
1123 * @hw: pointer to hardware structure
1124 * @reg_addr: 32 bit PHY register to write
1125 * @device_type: 3 bit device type
1126 * @data: Data to write to the register
1128 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1129 u32 device_type, u32 data)
1131 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1135 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1136 if (ret != IXGBE_SUCCESS)
1139 ret = ixgbe_iosf_wait(hw, NULL);
1140 if (ret != IXGBE_SUCCESS)
1143 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1144 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1146 /* Write IOSF control register */
1147 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1149 /* Write IOSF data register */
1150 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1152 ret = ixgbe_iosf_wait(hw, &command);
1154 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1155 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1156 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1157 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1158 "Failed to write, error %x\n", error);
1159 ret = IXGBE_ERR_PHY;
1163 ixgbe_release_swfw_semaphore(hw, gssr);
1168 * ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1169 * @hw: pointer to hardware structure
1170 * @reg_addr: 32 bit PHY register to write
1171 * @device_type: 3 bit device type
1172 * @data: Pointer to read data from the register
1174 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1175 u32 device_type, u32 *data)
1177 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1181 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1182 if (ret != IXGBE_SUCCESS)
1185 ret = ixgbe_iosf_wait(hw, NULL);
1186 if (ret != IXGBE_SUCCESS)
1189 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1190 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1192 /* Write IOSF control register */
1193 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1195 ret = ixgbe_iosf_wait(hw, &command);
1197 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1198 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1199 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1200 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1201 "Failed to read, error %x\n", error);
1202 ret = IXGBE_ERR_PHY;
1205 if (ret == IXGBE_SUCCESS)
1206 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1209 ixgbe_release_swfw_semaphore(hw, gssr);
1214 * ixgbe_get_phy_token - Get the token for shared phy access
1215 * @hw: Pointer to hardware structure
1218 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1220 struct ixgbe_hic_phy_token_req token_cmd;
1223 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1224 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1225 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1226 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1227 token_cmd.port_number = hw->bus.lan_id;
1228 token_cmd.command_type = FW_PHY_TOKEN_REQ;
1230 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1232 IXGBE_HI_COMMAND_TIMEOUT,
1236 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1237 return IXGBE_SUCCESS;
1238 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1239 return IXGBE_ERR_FW_RESP_INVALID;
1241 return IXGBE_ERR_TOKEN_RETRY;
1245 * ixgbe_put_phy_token - Put the token for shared phy access
1246 * @hw: Pointer to hardware structure
1249 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1251 struct ixgbe_hic_phy_token_req token_cmd;
1254 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1255 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1256 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1257 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1258 token_cmd.port_number = hw->bus.lan_id;
1259 token_cmd.command_type = FW_PHY_TOKEN_REL;
1261 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1263 IXGBE_HI_COMMAND_TIMEOUT,
1267 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1268 return IXGBE_SUCCESS;
1270 DEBUGOUT("Put PHY Token host interface command failed");
1271 return IXGBE_ERR_FW_RESP_INVALID;
1275 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1276 * of the IOSF device
1277 * @hw: pointer to hardware structure
1278 * @reg_addr: 32 bit PHY register to write
1279 * @device_type: 3 bit device type
1280 * @data: Data to write to the register
1282 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1283 u32 device_type, u32 data)
1285 struct ixgbe_hic_internal_phy_req write_cmd;
1287 UNREFERENCED_1PARAMETER(device_type);
1289 memset(&write_cmd, 0, sizeof(write_cmd));
1290 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1291 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1292 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1293 write_cmd.port_number = hw->bus.lan_id;
1294 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1295 write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1296 write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1298 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1300 IXGBE_HI_COMMAND_TIMEOUT, false);
1306 * ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1307 * @hw: pointer to hardware structure
1308 * @reg_addr: 32 bit PHY register to write
1309 * @device_type: 3 bit device type
1310 * @data: Pointer to read data from the register
1312 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1313 u32 device_type, u32 *data)
1316 struct ixgbe_hic_internal_phy_req cmd;
1317 struct ixgbe_hic_internal_phy_resp rsp;
1320 UNREFERENCED_1PARAMETER(device_type);
1322 memset(&hic, 0, sizeof(hic));
1323 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1324 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1325 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1326 hic.cmd.port_number = hw->bus.lan_id;
1327 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1328 hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1330 status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1332 IXGBE_HI_COMMAND_TIMEOUT, true);
1334 /* Extract the register value from the response. */
1335 *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1341 * ixgbe_disable_mdd_X550
1342 * @hw: pointer to hardware structure
1344 * Disable malicious driver detection
1346 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1350 DEBUGFUNC("ixgbe_disable_mdd_X550");
1352 /* Disable MDD for TX DMA and interrupt */
1353 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1354 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1355 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1357 /* Disable MDD for RX and interrupt */
1358 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1359 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1360 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1364 * ixgbe_enable_mdd_X550
1365 * @hw: pointer to hardware structure
1367 * Enable malicious driver detection
1369 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1373 DEBUGFUNC("ixgbe_enable_mdd_X550");
1375 /* Enable MDD for TX DMA and interrupt */
1376 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1377 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1378 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1380 /* Enable MDD for RX and interrupt */
1381 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1382 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1383 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1387 * ixgbe_restore_mdd_vf_X550
1388 * @hw: pointer to hardware structure
1391 * Restore VF that was disabled during malicious driver detection event
1393 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1395 u32 idx, reg, num_qs, start_q, bitmask;
1397 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1399 /* Map VF to queues */
1400 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1401 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1402 case IXGBE_MRQC_VMDQRT8TCEN:
1403 num_qs = 8; /* 16 VFs / pools */
1404 bitmask = 0x000000FF;
1406 case IXGBE_MRQC_VMDQRSS32EN:
1407 case IXGBE_MRQC_VMDQRT4TCEN:
1408 num_qs = 4; /* 32 VFs / pools */
1409 bitmask = 0x0000000F;
1411 default: /* 64 VFs / pools */
1413 bitmask = 0x00000003;
1416 start_q = vf * num_qs;
1418 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1421 reg |= (bitmask << (start_q % 32));
1422 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1423 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1427 * ixgbe_mdd_event_X550
1428 * @hw: pointer to hardware structure
1429 * @vf_bitmap: vf bitmap of malicious vfs
1431 * Handle malicious driver detection event.
1433 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1436 u32 i, j, reg, q, shift, vf, idx;
1438 DEBUGFUNC("ixgbe_mdd_event_X550");
1440 /* figure out pool size for mapping to vf's */
1441 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1442 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1443 case IXGBE_MRQC_VMDQRT8TCEN:
1444 shift = 3; /* 16 VFs / pools */
1446 case IXGBE_MRQC_VMDQRSS32EN:
1447 case IXGBE_MRQC_VMDQRT4TCEN:
1448 shift = 2; /* 32 VFs / pools */
1451 shift = 1; /* 64 VFs / pools */
1455 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1456 for (i = 0; i < 4; i++) {
1457 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1458 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1463 /* Get malicious queue */
1464 for (j = 0; j < 32 && wqbr; j++) {
1466 if (!(wqbr & (1 << j)))
1469 /* Get queue from bitmask */
1472 /* Map queue to vf */
1475 /* Set vf bit in vf_bitmap */
1477 vf_bitmap[idx] |= (1 << (vf % 32));
1484 * ixgbe_get_media_type_X550em - Get media type
1485 * @hw: pointer to hardware structure
1487 * Returns the media type (fiber, copper, backplane)
1489 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1491 enum ixgbe_media_type media_type;
1493 DEBUGFUNC("ixgbe_get_media_type_X550em");
1495 /* Detect if there is a copper PHY attached. */
1496 switch (hw->device_id) {
1497 case IXGBE_DEV_ID_X550EM_X_KR:
1498 case IXGBE_DEV_ID_X550EM_X_KX4:
1499 case IXGBE_DEV_ID_X550EM_A_KR:
1500 case IXGBE_DEV_ID_X550EM_A_KR_L:
1501 media_type = ixgbe_media_type_backplane;
1503 case IXGBE_DEV_ID_X550EM_X_SFP:
1504 case IXGBE_DEV_ID_X550EM_A_SFP:
1505 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1506 case IXGBE_DEV_ID_X550EM_A_QSFP:
1507 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1508 media_type = ixgbe_media_type_fiber;
1510 case IXGBE_DEV_ID_X550EM_X_1G_T:
1511 case IXGBE_DEV_ID_X550EM_X_10G_T:
1512 case IXGBE_DEV_ID_X550EM_A_10G_T:
1513 media_type = ixgbe_media_type_copper;
1515 case IXGBE_DEV_ID_X550EM_A_SGMII:
1516 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1517 media_type = ixgbe_media_type_backplane;
1518 hw->phy.type = ixgbe_phy_sgmii;
1520 case IXGBE_DEV_ID_X550EM_A_1G_T:
1521 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1522 media_type = ixgbe_media_type_copper;
1525 media_type = ixgbe_media_type_unknown;
1532 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1533 * @hw: pointer to hardware structure
1534 * @linear: true if SFP module is linear
1536 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1538 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1540 switch (hw->phy.sfp_type) {
1541 case ixgbe_sfp_type_not_present:
1542 return IXGBE_ERR_SFP_NOT_PRESENT;
1543 case ixgbe_sfp_type_da_cu_core0:
1544 case ixgbe_sfp_type_da_cu_core1:
1547 case ixgbe_sfp_type_srlr_core0:
1548 case ixgbe_sfp_type_srlr_core1:
1549 case ixgbe_sfp_type_da_act_lmt_core0:
1550 case ixgbe_sfp_type_da_act_lmt_core1:
1551 case ixgbe_sfp_type_1g_sx_core0:
1552 case ixgbe_sfp_type_1g_sx_core1:
1553 case ixgbe_sfp_type_1g_lx_core0:
1554 case ixgbe_sfp_type_1g_lx_core1:
1557 case ixgbe_sfp_type_unknown:
1558 case ixgbe_sfp_type_1g_cu_core0:
1559 case ixgbe_sfp_type_1g_cu_core1:
1561 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1564 return IXGBE_SUCCESS;
1568 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1569 * @hw: pointer to hardware structure
1571 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1573 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1578 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1580 status = ixgbe_identify_module_generic(hw);
1582 if (status != IXGBE_SUCCESS)
1585 /* Check if SFP module is supported */
1586 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1592 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1593 * @hw: pointer to hardware structure
1595 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1600 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1602 /* Check if SFP module is supported */
1603 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1605 if (status != IXGBE_SUCCESS)
1608 ixgbe_init_mac_link_ops_X550em(hw);
1609 hw->phy.ops.reset = NULL;
1611 return IXGBE_SUCCESS;
1615 * ixgbe_setup_sgmii - Set up link for sgmii
1616 * @hw: pointer to hardware structure
1618 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1621 struct ixgbe_mac_info *mac = &hw->mac;
1625 rc = mac->ops.read_iosf_sb_reg(hw,
1626 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1627 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1631 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1632 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1633 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1634 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1635 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1636 rc = mac->ops.write_iosf_sb_reg(hw,
1637 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1638 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1642 rc = mac->ops.read_iosf_sb_reg(hw,
1643 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1644 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1648 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1649 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1650 rc = mac->ops.write_iosf_sb_reg(hw,
1651 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1652 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1656 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1657 rc = mac->ops.write_iosf_sb_reg(hw,
1658 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1659 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1663 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1667 * ixgbe_setup_sgmii_m88 - Set up link for sgmii with Marvell PHYs
1668 * @hw: pointer to hardware structure
1670 STATIC s32 ixgbe_setup_sgmii_m88(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1673 struct ixgbe_mac_info *mac = &hw->mac;
1677 rc = mac->ops.read_iosf_sb_reg(hw,
1678 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1679 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1683 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1684 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1685 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1686 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1687 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1688 rc = mac->ops.write_iosf_sb_reg(hw,
1689 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1690 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1694 rc = mac->ops.read_iosf_sb_reg(hw,
1695 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1696 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1700 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1701 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1702 rc = mac->ops.write_iosf_sb_reg(hw,
1703 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1704 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1708 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1709 rc = mac->ops.write_iosf_sb_reg(hw,
1710 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1711 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1715 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1719 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1720 * @hw: pointer to hardware structure
1722 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1724 struct ixgbe_mac_info *mac = &hw->mac;
1726 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1728 switch (hw->mac.ops.get_media_type(hw)) {
1729 case ixgbe_media_type_fiber:
1730 /* CS4227 does not support autoneg, so disable the laser control
1731 * functions for SFP+ fiber
1733 mac->ops.disable_tx_laser = NULL;
1734 mac->ops.enable_tx_laser = NULL;
1735 mac->ops.flap_tx_laser = NULL;
1736 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1737 mac->ops.set_rate_select_speed =
1738 ixgbe_set_soft_rate_select_speed;
1739 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1740 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1741 mac->ops.setup_mac_link =
1742 ixgbe_setup_mac_link_sfp_x550a;
1744 mac->ops.setup_mac_link =
1745 ixgbe_setup_mac_link_sfp_x550em;
1747 case ixgbe_media_type_copper:
1748 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1749 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1750 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1751 mac->ops.setup_link = ixgbe_setup_sgmii_m88;
1753 mac->ops.setup_link =
1754 ixgbe_setup_mac_link_t_X550em;
1757 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1758 mac->ops.check_link = ixgbe_check_link_t_X550em;
1761 case ixgbe_media_type_backplane:
1762 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1763 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1764 mac->ops.setup_link = ixgbe_setup_sgmii;
1772 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1773 * @hw: pointer to hardware structure
1774 * @speed: pointer to link speed
1775 * @autoneg: true when autoneg or autotry is enabled
1777 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1778 ixgbe_link_speed *speed,
1781 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1784 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1786 /* CS4227 SFP must not enable auto-negotiation */
1789 /* Check if 1G SFP module. */
1790 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1791 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1792 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1793 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1794 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1795 return IXGBE_SUCCESS;
1798 /* Link capabilities are based on SFP */
1799 if (hw->phy.multispeed_fiber)
1800 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1801 IXGBE_LINK_SPEED_1GB_FULL;
1803 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1805 switch (hw->phy.type) {
1807 *speed = IXGBE_LINK_SPEED_1GB_FULL |
1808 IXGBE_LINK_SPEED_100_FULL |
1809 IXGBE_LINK_SPEED_10_FULL;
1811 case ixgbe_phy_sgmii:
1812 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1815 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1816 IXGBE_LINK_SPEED_1GB_FULL;
1822 return IXGBE_SUCCESS;
1826 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1827 * @hw: pointer to hardware structure
1828 * @lsc: pointer to boolean flag which indicates whether external Base T
1829 * PHY interrupt is lsc
1831 * Determime if external Base T PHY interrupt cause is high temperature
1832 * failure alarm or link status change.
1834 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1835 * failure alarm, else return PHY access status.
1837 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1844 /* Vendor alarm triggered */
1845 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1846 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1849 if (status != IXGBE_SUCCESS ||
1850 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1853 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1854 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1855 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1858 if (status != IXGBE_SUCCESS ||
1859 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1860 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1863 /* Global alarm triggered */
1864 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1865 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1868 if (status != IXGBE_SUCCESS)
1871 /* If high temperature failure, then return over temp error and exit */
1872 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1873 /* power down the PHY in case the PHY FW didn't already */
1874 ixgbe_set_copper_phy_power(hw, false);
1875 return IXGBE_ERR_OVERTEMP;
1876 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1877 /* device fault alarm triggered */
1878 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1879 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1882 if (status != IXGBE_SUCCESS)
1885 /* if device fault was due to high temp alarm handle and exit */
1886 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1887 /* power down the PHY in case the PHY FW didn't */
1888 ixgbe_set_copper_phy_power(hw, false);
1889 return IXGBE_ERR_OVERTEMP;
1893 /* Vendor alarm 2 triggered */
1894 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1895 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1897 if (status != IXGBE_SUCCESS ||
1898 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1901 /* link connect/disconnect event occurred */
1902 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1903 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1905 if (status != IXGBE_SUCCESS)
1909 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1912 return IXGBE_SUCCESS;
1916 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1917 * @hw: pointer to hardware structure
1919 * Enable link status change and temperature failure alarm for the external
1922 * Returns PHY access status
1924 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1930 /* Clear interrupt flags */
1931 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1933 /* Enable link status change alarm */
1934 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1935 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1937 if (status != IXGBE_SUCCESS)
1940 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1942 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1943 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1945 if (status != IXGBE_SUCCESS)
1948 /* Enable high temperature failure and global fault alarms */
1949 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1950 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1953 if (status != IXGBE_SUCCESS)
1956 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1957 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1959 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1960 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1963 if (status != IXGBE_SUCCESS)
1966 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1967 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1968 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1971 if (status != IXGBE_SUCCESS)
1974 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1975 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1977 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1978 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1981 if (status != IXGBE_SUCCESS)
1984 /* Enable chip-wide vendor alarm */
1985 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1986 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1989 if (status != IXGBE_SUCCESS)
1992 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1994 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1995 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2002 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2003 * @hw: pointer to hardware structure
2004 * @speed: link speed
2006 * Configures the integrated KR PHY.
2008 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2009 ixgbe_link_speed speed)
2014 status = hw->mac.ops.read_iosf_sb_reg(hw,
2015 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2016 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2020 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2021 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2022 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2024 /* Advertise 10G support. */
2025 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2026 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2028 /* Advertise 1G support. */
2029 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2030 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2032 /* Restart auto-negotiation. */
2033 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2034 status = hw->mac.ops.write_iosf_sb_reg(hw,
2035 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2036 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2042 * ixgbe_setup_m88 - setup m88 PHY
2043 * @hw: pointer to hardware structure
2045 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2047 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2051 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2052 return IXGBE_SUCCESS;
2054 rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2058 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2061 if (reg & IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN) {
2062 reg &= ~IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN;
2063 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2067 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, ®);
2070 if (reg & IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN) {
2071 reg &= ~IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN;
2072 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0,
2076 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 2);
2080 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2084 if (reg & IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN) {
2085 reg &= ~IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN;
2086 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2088 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2092 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2096 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2097 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2101 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2107 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2111 if (!(reg & IXGBE_M88E1500_COPPER_CTRL_AN_EN)) {
2112 reg |= IXGBE_M88E1500_COPPER_CTRL_AN_EN;
2113 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2117 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, ®);
2120 reg &= ~IXGBE_M88E1500_1000T_CTRL_HALF_DUPLEX;
2121 reg &= ~IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2122 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
2123 reg |= IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2124 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, reg);
2126 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, ®);
2129 reg &= ~IXGBE_M88E1500_COPPER_AN_T4;
2130 reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_FD;
2131 reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_HD;
2132 reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_FD;
2133 reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_HD;
2135 /* Flow control auto negotiation configuration was moved from here to
2136 * the function ixgbe_setup_fc_sgmii_x550em_a()
2139 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
2140 reg |= IXGBE_M88E1500_COPPER_AN_100TX_FD;
2141 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
2142 reg |= IXGBE_M88E1500_COPPER_AN_10TX_FD;
2143 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, reg);
2145 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2148 reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
2149 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2152 hw->mac.ops.release_swfw_sync(hw, mask);
2156 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2157 hw->mac.ops.release_swfw_sync(hw, mask);
2162 * ixgbe_reset_phy_m88e1500 - Reset m88e1500 PHY
2163 * @hw: pointer to hardware structure
2165 * The PHY token must be held when calling this function.
2167 static s32 ixgbe_reset_phy_m88e1500(struct ixgbe_hw *hw)
2172 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2176 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2180 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2181 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2189 * ixgbe_reset_phy_m88e1543 - Reset m88e1543 PHY
2190 * @hw: pointer to hardware structure
2192 * The PHY token must be held when calling this function.
2194 static s32 ixgbe_reset_phy_m88e1543(struct ixgbe_hw *hw)
2196 return hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2200 * ixgbe_reset_phy_m88 - Reset m88 PHY
2201 * @hw: pointer to hardware structure
2203 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2205 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2209 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2210 return IXGBE_SUCCESS;
2212 rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2216 switch (hw->phy.id) {
2217 case IXGBE_M88E1500_E_PHY_ID:
2218 rc = ixgbe_reset_phy_m88e1500(hw);
2220 case IXGBE_M88E1543_E_PHY_ID:
2221 rc = ixgbe_reset_phy_m88e1543(hw);
2228 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2232 reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2233 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2234 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2235 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2239 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2243 reg = IXGBE_M88E1500_GEN_CTRL_RESET |
2244 IXGBE_M88E1500_GEN_CTRL_MODE_SGMII_COPPER;
2245 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_GEN_CTRL, 0, reg);
2249 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2253 reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2254 IXGBE_M88E1500_FIBER_CTRL_AN_EN |
2255 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2256 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2257 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2261 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2265 reg = (IXGBE_M88E1500_MAC_CTRL_1_DWN_4X <<
2266 IXGBE_M88E1500_MAC_CTRL_1_DWN_SHIFT) |
2267 (IXGBE_M88E1500_MAC_CTRL_1_ED_TM <<
2268 IXGBE_M88E1500_MAC_CTRL_1_ED_SHIFT) |
2269 (IXGBE_M88E1500_MAC_CTRL_1_MDIX_AUTO <<
2270 IXGBE_M88E1500_MAC_CTRL_1_MDIX_SHIFT);
2271 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, reg);
2275 reg = IXGBE_M88E1500_COPPER_CTRL_RESET |
2276 IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2277 IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2278 IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2279 IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB;
2280 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2284 hw->mac.ops.release_swfw_sync(hw, mask);
2286 return ixgbe_setup_m88(hw);
2289 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2290 hw->mac.ops.release_swfw_sync(hw, mask);
2295 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2296 * @hw: pointer to hardware structure
2298 * Read NW_MNG_IF_SEL register and save field values, and check for valid field
2301 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2303 /* Save NW management interface connected on board. This is used
2304 * to determine internal PHY mode.
2306 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2308 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2309 * PHY address. This register field was has only been used for X552.
2311 if (hw->mac.type == ixgbe_mac_X550EM_a &&
2312 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2313 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2314 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2315 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2318 return IXGBE_SUCCESS;
2322 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2323 * @hw: pointer to hardware structure
2325 * Initialize any function pointers that were not able to be
2326 * set during init_shared_code because the PHY/SFP type was
2327 * not known. Perform the SFP init if necessary.
2329 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2331 struct ixgbe_phy_info *phy = &hw->phy;
2334 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2336 hw->mac.ops.set_lan_id(hw);
2338 ixgbe_read_mng_if_sel_x550em(hw);
2340 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2341 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2342 ixgbe_setup_mux_ctl(hw);
2343 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2346 switch (hw->device_id) {
2347 case IXGBE_DEV_ID_X550EM_A_1G_T:
2348 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2349 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2350 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2356 /* Identify the PHY or SFP module */
2357 ret_val = phy->ops.identify(hw);
2358 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2361 /* Setup function pointers based on detected hardware */
2362 ixgbe_init_mac_link_ops_X550em(hw);
2363 if (phy->sfp_type != ixgbe_sfp_type_unknown)
2364 phy->ops.reset = NULL;
2366 /* Set functions pointers based on phy type */
2367 switch (hw->phy.type) {
2368 case ixgbe_phy_x550em_kx4:
2369 phy->ops.setup_link = NULL;
2370 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2371 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2373 case ixgbe_phy_x550em_kr:
2374 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2375 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2376 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2378 case ixgbe_phy_x550em_ext_t:
2379 /* If internal link mode is XFI, then setup iXFI internal link,
2380 * else setup KR now.
2382 phy->ops.setup_internal_link =
2383 ixgbe_setup_internal_phy_t_x550em;
2385 /* setup SW LPLU only for first revision of X550EM_x */
2386 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2387 !(IXGBE_FUSES0_REV_MASK &
2388 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2389 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2391 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2392 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2394 case ixgbe_phy_sgmii:
2395 phy->ops.setup_link = NULL;
2398 phy->ops.setup_link = ixgbe_setup_m88;
2399 phy->ops.reset = ixgbe_reset_phy_m88;
2408 * ixgbe_set_mdio_speed - Set MDIO clock speed
2409 * @hw: pointer to hardware structure
2411 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2415 switch (hw->device_id) {
2416 case IXGBE_DEV_ID_X550EM_X_10G_T:
2417 case IXGBE_DEV_ID_X550EM_A_SGMII:
2418 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2419 case IXGBE_DEV_ID_X550EM_A_1G_T:
2420 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2421 case IXGBE_DEV_ID_X550EM_A_10G_T:
2422 case IXGBE_DEV_ID_X550EM_A_SFP:
2423 case IXGBE_DEV_ID_X550EM_A_QSFP:
2424 /* Config MDIO clock speed before the first MDIO PHY access */
2425 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2426 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2427 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2435 * ixgbe_reset_hw_X550em - Perform hardware reset
2436 * @hw: pointer to hardware structure
2438 * Resets the hardware by resetting the transmit and receive units, masks
2439 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2442 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2444 ixgbe_link_speed link_speed;
2448 bool link_up = false;
2450 DEBUGFUNC("ixgbe_reset_hw_X550em");
2452 /* Call adapter stop to disable Tx/Rx and clear interrupts */
2453 status = hw->mac.ops.stop_adapter(hw);
2454 if (status != IXGBE_SUCCESS)
2457 /* flush pending Tx transactions */
2458 ixgbe_clear_tx_pending(hw);
2460 ixgbe_set_mdio_speed(hw);
2462 /* PHY ops must be identified and initialized prior to reset */
2463 status = hw->phy.ops.init(hw);
2465 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2468 /* start the external PHY */
2469 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2470 status = ixgbe_init_ext_t_x550em(hw);
2475 /* Setup SFP module if there is one present. */
2476 if (hw->phy.sfp_setup_needed) {
2477 status = hw->mac.ops.setup_sfp(hw);
2478 hw->phy.sfp_setup_needed = false;
2481 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2485 if (!hw->phy.reset_disable && hw->phy.ops.reset)
2486 hw->phy.ops.reset(hw);
2489 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
2490 * If link reset is used when link is up, it might reset the PHY when
2491 * mng is using it. If link is down or the flag to force full link
2492 * reset is set, then perform link reset.
2494 ctrl = IXGBE_CTRL_LNK_RST;
2495 if (!hw->force_full_reset) {
2496 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2498 ctrl = IXGBE_CTRL_RST;
2501 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2502 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2503 IXGBE_WRITE_FLUSH(hw);
2505 /* Poll for reset bit to self-clear meaning reset is complete */
2506 for (i = 0; i < 10; i++) {
2508 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2509 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2513 if (ctrl & IXGBE_CTRL_RST_MASK) {
2514 status = IXGBE_ERR_RESET_FAILED;
2515 DEBUGOUT("Reset polling failed to complete.\n");
2520 /* Double resets are required for recovery from certain error
2521 * conditions. Between resets, it is necessary to stall to
2522 * allow time for any pending HW events to complete.
2524 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2525 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2529 /* Store the permanent mac address */
2530 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2532 /* Store MAC address from RAR0, clear receive address registers, and
2533 * clear the multicast table. Also reset num_rar_entries to 128,
2534 * since we modify this value when programming the SAN MAC address.
2536 hw->mac.num_rar_entries = 128;
2537 hw->mac.ops.init_rx_addrs(hw);
2539 ixgbe_set_mdio_speed(hw);
2541 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2542 ixgbe_setup_mux_ctl(hw);
2548 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2549 * @hw: pointer to hardware structure
2551 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2556 status = hw->phy.ops.read_reg(hw,
2557 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2558 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2561 if (status != IXGBE_SUCCESS)
2564 /* If PHY FW reset completed bit is set then this is the first
2565 * SW instance after a power on so the PHY FW must be un-stalled.
2567 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2568 status = hw->phy.ops.read_reg(hw,
2569 IXGBE_MDIO_GLOBAL_RES_PR_10,
2570 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2573 if (status != IXGBE_SUCCESS)
2576 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2578 status = hw->phy.ops.write_reg(hw,
2579 IXGBE_MDIO_GLOBAL_RES_PR_10,
2580 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2583 if (status != IXGBE_SUCCESS)
2591 * ixgbe_setup_kr_x550em - Configure the KR PHY.
2592 * @hw: pointer to hardware structure
2594 * Configures the integrated KR PHY for X550EM_x.
2596 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2598 if (hw->mac.type != ixgbe_mac_X550EM_x)
2599 return IXGBE_SUCCESS;
2601 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2605 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2606 * @hw: pointer to hardware structure
2608 * Configure the external PHY and the integrated KR PHY for SFP support.
2610 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2611 ixgbe_link_speed speed,
2612 bool autoneg_wait_to_complete)
2615 u16 reg_slice, reg_val;
2616 bool setup_linear = false;
2617 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2619 /* Check if SFP module is supported and linear */
2620 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2622 /* If no SFP module present, then return success. Return success since
2623 * there is no reason to configure CS4227 and SFP not present error is
2624 * not excepted in the setup MAC link flow.
2626 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2627 return IXGBE_SUCCESS;
2629 if (ret_val != IXGBE_SUCCESS)
2632 /* Configure internal PHY for KR/KX. */
2633 ixgbe_setup_kr_speed_x550em(hw, speed);
2635 /* Configure CS4227 LINE side to proper mode. */
2636 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2637 (hw->bus.lan_id << 12);
2639 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2641 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2642 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2648 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2649 * @hw: pointer to hardware structure
2651 * Configure the the integrated PHY for SFP support.
2653 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2654 ixgbe_link_speed speed,
2655 bool autoneg_wait_to_complete)
2659 bool setup_linear = false;
2660 u32 reg_slice, reg_phy_int, slice_offset;
2662 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2664 /* Check if SFP module is supported and linear */
2665 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2667 /* If no SFP module present, then return success. Return success since
2668 * SFP not present error is not excepted in the setup MAC link flow.
2670 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2671 return IXGBE_SUCCESS;
2673 if (ret_val != IXGBE_SUCCESS)
2676 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2677 /* Configure internal PHY for native SFI */
2678 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2679 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2680 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
2682 if (ret_val != IXGBE_SUCCESS)
2686 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2687 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2689 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2690 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2693 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2694 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2695 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2697 if (ret_val != IXGBE_SUCCESS)
2700 /* Setup XFI/SFI internal link. */
2701 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2703 /* Configure internal PHY for KR/KX. */
2704 ixgbe_setup_kr_speed_x550em(hw, speed);
2706 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2708 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2709 return IXGBE_ERR_PHY_ADDR_INVALID;
2712 /* Get external PHY device id */
2713 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2714 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2716 if (ret_val != IXGBE_SUCCESS)
2719 /* When configuring quad port CS4223, the MAC instance is part
2720 * of the slice offset.
2722 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2723 slice_offset = (hw->bus.lan_id +
2724 (hw->bus.instance_id << 1)) << 12;
2726 slice_offset = hw->bus.lan_id << 12;
2728 /* Configure CS4227/CS4223 LINE side to proper mode. */
2729 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2731 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2733 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2734 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2735 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2741 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2742 * @hw: pointer to hardware structure
2744 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2746 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2748 struct ixgbe_mac_info *mac = &hw->mac;
2752 /* Disable training protocol FSM. */
2753 status = mac->ops.read_iosf_sb_reg(hw,
2754 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2755 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2756 if (status != IXGBE_SUCCESS)
2758 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2759 status = mac->ops.write_iosf_sb_reg(hw,
2760 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2761 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2762 if (status != IXGBE_SUCCESS)
2765 /* Disable Flex from training TXFFE. */
2766 status = mac->ops.read_iosf_sb_reg(hw,
2767 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2768 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2769 if (status != IXGBE_SUCCESS)
2771 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2772 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2773 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2774 status = mac->ops.write_iosf_sb_reg(hw,
2775 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2776 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2777 if (status != IXGBE_SUCCESS)
2779 status = mac->ops.read_iosf_sb_reg(hw,
2780 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2781 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2782 if (status != IXGBE_SUCCESS)
2784 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2785 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2786 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2787 status = mac->ops.write_iosf_sb_reg(hw,
2788 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2789 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2790 if (status != IXGBE_SUCCESS)
2793 /* Enable override for coefficients. */
2794 status = mac->ops.read_iosf_sb_reg(hw,
2795 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2796 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2797 if (status != IXGBE_SUCCESS)
2799 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2800 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2801 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2802 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2803 status = mac->ops.write_iosf_sb_reg(hw,
2804 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2805 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2810 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2811 * @hw: pointer to hardware structure
2812 * @speed: the link speed to force
2814 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
2815 * internal and external PHY at a specific speed, without autonegotiation.
2817 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2819 struct ixgbe_mac_info *mac = &hw->mac;
2823 /* Disable AN and force speed to 10G Serial. */
2824 status = mac->ops.read_iosf_sb_reg(hw,
2825 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2826 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2827 if (status != IXGBE_SUCCESS)
2830 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2831 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2833 /* Select forced link speed for internal PHY. */
2835 case IXGBE_LINK_SPEED_10GB_FULL:
2836 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2838 case IXGBE_LINK_SPEED_1GB_FULL:
2839 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2842 /* Other link speeds are not supported by internal KR PHY. */
2843 return IXGBE_ERR_LINK_SETUP;
2846 status = mac->ops.write_iosf_sb_reg(hw,
2847 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2848 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2849 if (status != IXGBE_SUCCESS)
2852 /* Additional configuration needed for x550em_x */
2853 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2854 status = ixgbe_setup_ixfi_x550em_x(hw);
2855 if (status != IXGBE_SUCCESS)
2859 /* Toggle port SW reset by AN reset. */
2860 status = mac->ops.read_iosf_sb_reg(hw,
2861 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2862 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2863 if (status != IXGBE_SUCCESS)
2865 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2866 status = mac->ops.write_iosf_sb_reg(hw,
2867 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2868 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2874 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2875 * @hw: address of hardware structure
2876 * @link_up: address of boolean to indicate link status
2878 * Returns error code if unable to get link status.
2880 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2887 /* read this twice back to back to indicate current status */
2888 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2889 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2891 if (ret != IXGBE_SUCCESS)
2894 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2895 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2897 if (ret != IXGBE_SUCCESS)
2900 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2902 return IXGBE_SUCCESS;
2906 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2907 * @hw: point to hardware structure
2909 * Configures the link between the integrated KR PHY and the external X557 PHY
2910 * The driver will call this function when it gets a link status change
2911 * interrupt from the X557 PHY. This function configures the link speed
2912 * between the PHYs to match the link speed of the BASE-T link.
2914 * A return of a non-zero value indicates an error, and the base driver should
2915 * not report link up.
2917 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2919 ixgbe_link_speed force_speed;
2924 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2925 return IXGBE_ERR_CONFIG;
2927 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2928 /* If link is down, there is no setup necessary so return */
2929 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2930 if (status != IXGBE_SUCCESS)
2934 return IXGBE_SUCCESS;
2936 status = hw->phy.ops.read_reg(hw,
2937 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2938 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2940 if (status != IXGBE_SUCCESS)
2943 /* If link is still down - no setup is required so return */
2944 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2945 if (status != IXGBE_SUCCESS)
2948 return IXGBE_SUCCESS;
2950 /* clear everything but the speed and duplex bits */
2951 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2954 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2955 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2957 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2958 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2961 /* Internal PHY does not support anything else */
2962 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2965 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2967 speed = IXGBE_LINK_SPEED_10GB_FULL |
2968 IXGBE_LINK_SPEED_1GB_FULL;
2969 return ixgbe_setup_kr_speed_x550em(hw, speed);
2974 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2975 * @hw: pointer to hardware structure
2977 * Configures the integrated KR PHY to use internal loopback mode.
2979 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2984 /* Disable AN and force speed to 10G Serial. */
2985 status = hw->mac.ops.read_iosf_sb_reg(hw,
2986 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2987 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2988 if (status != IXGBE_SUCCESS)
2990 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2991 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2992 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2993 status = hw->mac.ops.write_iosf_sb_reg(hw,
2994 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2995 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2996 if (status != IXGBE_SUCCESS)
2999 /* Set near-end loopback clocks. */
3000 status = hw->mac.ops.read_iosf_sb_reg(hw,
3001 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3002 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3003 if (status != IXGBE_SUCCESS)
3005 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3006 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3007 status = hw->mac.ops.write_iosf_sb_reg(hw,
3008 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3009 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3010 if (status != IXGBE_SUCCESS)
3013 /* Set loopback enable. */
3014 status = hw->mac.ops.read_iosf_sb_reg(hw,
3015 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3016 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3017 if (status != IXGBE_SUCCESS)
3019 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3020 status = hw->mac.ops.write_iosf_sb_reg(hw,
3021 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3022 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3023 if (status != IXGBE_SUCCESS)
3026 /* Training bypass. */
3027 status = hw->mac.ops.read_iosf_sb_reg(hw,
3028 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3029 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3030 if (status != IXGBE_SUCCESS)
3032 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3033 status = hw->mac.ops.write_iosf_sb_reg(hw,
3034 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3035 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3041 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3042 * assuming that the semaphore is already obtained.
3043 * @hw: pointer to hardware structure
3044 * @offset: offset of word in the EEPROM to read
3045 * @data: word read from the EEPROM
3047 * Reads a 16 bit word from the EEPROM using the hostif.
3049 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3053 struct ixgbe_hic_read_shadow_ram buffer;
3055 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
3056 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3057 buffer.hdr.req.buf_lenh = 0;
3058 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3059 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3061 /* convert offset from words to bytes */
3062 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3064 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3066 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3068 IXGBE_HI_COMMAND_TIMEOUT, false);
3073 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3074 FW_NVM_DATA_OFFSET);
3080 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3081 * @hw: pointer to hardware structure
3082 * @offset: offset of word in the EEPROM to read
3083 * @data: word read from the EEPROM
3085 * Reads a 16 bit word from the EEPROM using the hostif.
3087 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3090 s32 status = IXGBE_SUCCESS;
3092 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3094 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3096 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
3097 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3099 status = IXGBE_ERR_SWFW_SYNC;
3106 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3107 * @hw: pointer to hardware structure
3108 * @offset: offset of word in the EEPROM to read
3109 * @words: number of words
3110 * @data: word(s) read from the EEPROM
3112 * Reads a 16 bit word(s) from the EEPROM using the hostif.
3114 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3115 u16 offset, u16 words, u16 *data)
3117 struct ixgbe_hic_read_shadow_ram buffer;
3118 u32 current_word = 0;
3123 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3125 /* Take semaphore for the entire operation. */
3126 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3128 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3132 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3133 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3135 words_to_read = words;
3137 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3138 buffer.hdr.req.buf_lenh = 0;
3139 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3140 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3142 /* convert offset from words to bytes */
3143 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3144 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3146 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3148 IXGBE_HI_COMMAND_TIMEOUT,
3152 DEBUGOUT("Host interface command failed\n");
3156 for (i = 0; i < words_to_read; i++) {
3157 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3159 u32 value = IXGBE_READ_REG(hw, reg);
3161 data[current_word] = (u16)(value & 0xffff);
3164 if (i < words_to_read) {
3166 data[current_word] = (u16)(value & 0xffff);
3170 words -= words_to_read;
3174 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3179 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3180 * @hw: pointer to hardware structure
3181 * @offset: offset of word in the EEPROM to write
3182 * @data: word write to the EEPROM
3184 * Write a 16 bit word to the EEPROM using the hostif.
3186 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3190 struct ixgbe_hic_write_shadow_ram buffer;
3192 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3194 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3195 buffer.hdr.req.buf_lenh = 0;
3196 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3197 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3200 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3202 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3204 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3206 IXGBE_HI_COMMAND_TIMEOUT, false);
3212 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3213 * @hw: pointer to hardware structure
3214 * @offset: offset of word in the EEPROM to write
3215 * @data: word write to the EEPROM
3217 * Write a 16 bit word to the EEPROM using the hostif.
3219 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3222 s32 status = IXGBE_SUCCESS;
3224 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3226 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3228 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3229 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3231 DEBUGOUT("write ee hostif failed to get semaphore");
3232 status = IXGBE_ERR_SWFW_SYNC;
3239 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3240 * @hw: pointer to hardware structure
3241 * @offset: offset of word in the EEPROM to write
3242 * @words: number of words
3243 * @data: word(s) write to the EEPROM
3245 * Write a 16 bit word(s) to the EEPROM using the hostif.
3247 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3248 u16 offset, u16 words, u16 *data)
3250 s32 status = IXGBE_SUCCESS;
3253 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3255 /* Take semaphore for the entire operation. */
3256 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3257 if (status != IXGBE_SUCCESS) {
3258 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3262 for (i = 0; i < words; i++) {
3263 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3266 if (status != IXGBE_SUCCESS) {
3267 DEBUGOUT("Eeprom buffered write failed\n");
3272 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3279 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3280 * @hw: pointer to hardware structure
3281 * @ptr: pointer offset in eeprom
3282 * @size: size of section pointed by ptr, if 0 first word will be used as size
3283 * @csum: address of checksum to update
3285 * Returns error status for any failure
3287 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3288 u16 size, u16 *csum, u16 *buffer,
3293 u16 length, bufsz, i, start;
3296 bufsz = sizeof(buf) / sizeof(buf[0]);
3298 /* Read a chunk at the pointer location */
3300 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3302 DEBUGOUT("Failed to read EEPROM image\n");
3307 if (buffer_size < ptr)
3308 return IXGBE_ERR_PARAM;
3309 local_buffer = &buffer[ptr];
3317 length = local_buffer[0];
3319 /* Skip pointer section if length is invalid. */
3320 if (length == 0xFFFF || length == 0 ||
3321 (ptr + length) >= hw->eeprom.word_size)
3322 return IXGBE_SUCCESS;
3325 if (buffer && ((u32)start + (u32)length > buffer_size))
3326 return IXGBE_ERR_PARAM;
3328 for (i = start; length; i++, length--) {
3329 if (i == bufsz && !buffer) {
3335 /* Read a chunk at the pointer location */
3336 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3339 DEBUGOUT("Failed to read EEPROM image\n");
3343 *csum += local_buffer[i];
3345 return IXGBE_SUCCESS;
3349 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3350 * @hw: pointer to hardware structure
3351 * @buffer: pointer to buffer containing calculated checksum
3352 * @buffer_size: size of buffer
3354 * Returns a negative error code on error, or the 16-bit checksum
3356 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3358 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3362 u16 pointer, i, size;
3364 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3366 hw->eeprom.ops.init_params(hw);
3369 /* Read pointer area */
3370 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3371 IXGBE_EEPROM_LAST_WORD + 1,
3374 DEBUGOUT("Failed to read EEPROM image\n");
3377 local_buffer = eeprom_ptrs;
3379 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3380 return IXGBE_ERR_PARAM;
3381 local_buffer = buffer;
3385 * For X550 hardware include 0x0-0x41 in the checksum, skip the
3386 * checksum word itself
3388 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3389 if (i != IXGBE_EEPROM_CHECKSUM)
3390 checksum += local_buffer[i];
3393 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
3394 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3396 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3397 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3400 pointer = local_buffer[i];
3402 /* Skip pointer section if the pointer is invalid. */
3403 if (pointer == 0xFFFF || pointer == 0 ||
3404 pointer >= hw->eeprom.word_size)
3408 case IXGBE_PCIE_GENERAL_PTR:
3409 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3411 case IXGBE_PCIE_CONFIG0_PTR:
3412 case IXGBE_PCIE_CONFIG1_PTR:
3413 size = IXGBE_PCIE_CONFIG_SIZE;
3420 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3421 buffer, buffer_size);
3426 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3428 return (s32)checksum;
3432 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3433 * @hw: pointer to hardware structure
3435 * Returns a negative error code on error, or the 16-bit checksum
3437 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3439 return ixgbe_calc_checksum_X550(hw, NULL, 0);
3443 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3444 * @hw: pointer to hardware structure
3445 * @checksum_val: calculated checksum
3447 * Performs checksum calculation and validates the EEPROM checksum. If the
3448 * caller does not need checksum_val, the value can be NULL.
3450 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3454 u16 read_checksum = 0;
3456 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3458 /* Read the first word from the EEPROM. If this times out or fails, do
3459 * not continue or we could be in for a very long wait while every
3462 status = hw->eeprom.ops.read(hw, 0, &checksum);
3464 DEBUGOUT("EEPROM read failed\n");
3468 status = hw->eeprom.ops.calc_checksum(hw);
3472 checksum = (u16)(status & 0xffff);
3474 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3479 /* Verify read checksum from EEPROM is the same as
3480 * calculated checksum
3482 if (read_checksum != checksum) {
3483 status = IXGBE_ERR_EEPROM_CHECKSUM;
3484 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3485 "Invalid EEPROM checksum");
3488 /* If the user cares, return the calculated checksum */
3490 *checksum_val = checksum;
3496 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3497 * @hw: pointer to hardware structure
3499 * After writing EEPROM to shadow RAM using EEWR register, software calculates
3500 * checksum and updates the EEPROM and instructs the hardware to update
3503 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3508 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3510 /* Read the first word from the EEPROM. If this times out or fails, do
3511 * not continue or we could be in for a very long wait while every
3514 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3516 DEBUGOUT("EEPROM read failed\n");
3520 status = ixgbe_calc_eeprom_checksum_X550(hw);
3524 checksum = (u16)(status & 0xffff);
3526 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3531 status = ixgbe_update_flash_X550(hw);
3537 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3538 * @hw: pointer to hardware structure
3540 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3542 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3544 s32 status = IXGBE_SUCCESS;
3545 union ixgbe_hic_hdr2 buffer;
3547 DEBUGFUNC("ixgbe_update_flash_X550");
3549 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3550 buffer.req.buf_lenh = 0;
3551 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3552 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3554 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3556 IXGBE_HI_COMMAND_TIMEOUT, false);
3562 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3563 * @hw: pointer to hardware structure
3565 * Determines physical layer capabilities of the current configuration.
3567 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3569 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3570 u16 ext_ability = 0;
3572 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3574 hw->phy.ops.identify(hw);
3576 switch (hw->phy.type) {
3577 case ixgbe_phy_x550em_kr:
3578 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3579 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3581 case ixgbe_phy_x550em_kx4:
3582 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3583 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3585 case ixgbe_phy_x550em_ext_t:
3586 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3587 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3589 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3590 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3591 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3592 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3598 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3599 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3601 return physical_layer;
3605 * ixgbe_get_bus_info_x550em - Set PCI bus info
3606 * @hw: pointer to hardware structure
3608 * Sets bus link width and speed to unknown because X550em is
3611 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3614 DEBUGFUNC("ixgbe_get_bus_info_x550em");
3616 hw->bus.width = ixgbe_bus_width_unknown;
3617 hw->bus.speed = ixgbe_bus_speed_unknown;
3619 hw->mac.ops.set_lan_id(hw);
3621 return IXGBE_SUCCESS;
3625 * ixgbe_disable_rx_x550 - Disable RX unit
3627 * Enables the Rx DMA unit for x550
3629 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3631 u32 rxctrl, pfdtxgswc;
3633 struct ixgbe_hic_disable_rxen fw_cmd;
3635 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3637 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3638 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3639 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3640 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3641 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3642 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3643 hw->mac.set_lben = true;
3645 hw->mac.set_lben = false;
3648 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3649 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3650 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3651 fw_cmd.port_number = (u8)hw->bus.lan_id;
3653 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3654 sizeof(struct ixgbe_hic_disable_rxen),
3655 IXGBE_HI_COMMAND_TIMEOUT, true);
3657 /* If we fail - disable RX using register write */
3659 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3660 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3661 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3662 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3669 * ixgbe_enter_lplu_x550em - Transition to low power states
3670 * @hw: pointer to hardware structure
3672 * Configures Low Power Link Up on transition to low power states
3673 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3674 * X557 PHY immediately prior to entering LPLU.
3676 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3678 u16 an_10g_cntl_reg, autoneg_reg, speed;
3680 ixgbe_link_speed lcd_speed;
3684 /* SW LPLU not required on later HW revisions. */
3685 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3686 (IXGBE_FUSES0_REV_MASK &
3687 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3688 return IXGBE_SUCCESS;
3690 /* If blocked by MNG FW, then don't restart AN */
3691 if (ixgbe_check_reset_blocked(hw))
3692 return IXGBE_SUCCESS;
3694 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3695 if (status != IXGBE_SUCCESS)
3698 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3700 if (status != IXGBE_SUCCESS)
3703 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3704 * disabled, then force link down by entering low power mode.
3706 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3707 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3708 return ixgbe_set_copper_phy_power(hw, FALSE);
3711 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3713 if (status != IXGBE_SUCCESS)
3716 /* If no valid LCD link speed, then force link down and exit. */
3717 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3718 return ixgbe_set_copper_phy_power(hw, FALSE);
3720 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3721 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3724 if (status != IXGBE_SUCCESS)
3727 /* If no link now, speed is invalid so take link down */
3728 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3729 if (status != IXGBE_SUCCESS)
3730 return ixgbe_set_copper_phy_power(hw, false);
3732 /* clear everything but the speed bits */
3733 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3735 /* If current speed is already LCD, then exit. */
3736 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3737 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3738 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3739 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3742 /* Clear AN completed indication */
3743 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3744 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3747 if (status != IXGBE_SUCCESS)
3750 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3751 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3754 if (status != IXGBE_SUCCESS)
3757 status = hw->phy.ops.read_reg(hw,
3758 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3759 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3762 if (status != IXGBE_SUCCESS)
3765 save_autoneg = hw->phy.autoneg_advertised;
3767 /* Setup link at least common link speed */
3768 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3770 /* restore autoneg from before setting lplu speed */
3771 hw->phy.autoneg_advertised = save_autoneg;
3777 * ixgbe_get_lcd_x550em - Determine lowest common denominator
3778 * @hw: pointer to hardware structure
3779 * @lcd_speed: pointer to lowest common link speed
3781 * Determine lowest common link speed with link partner.
3783 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3787 u16 word = hw->eeprom.ctrl_word_3;
3789 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3791 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3792 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3795 if (status != IXGBE_SUCCESS)
3798 /* If link partner advertised 1G, return 1G */
3799 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3800 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3804 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3805 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3806 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3809 /* Link partner not capable of lower speeds, return 10G */
3810 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3815 * ixgbe_setup_fc_X550em - Set up flow control
3816 * @hw: pointer to hardware structure
3818 * Called at init time to set up flow control.
3820 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3822 s32 ret_val = IXGBE_SUCCESS;
3823 u32 pause, asm_dir, reg_val;
3825 DEBUGFUNC("ixgbe_setup_fc_X550em");
3827 /* Validate the requested mode */
3828 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3829 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3830 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3831 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3835 /* 10gig parts do not have a word in the EEPROM to determine the
3836 * default flow control setting, so we explicitly set it to full.
3838 if (hw->fc.requested_mode == ixgbe_fc_default)
3839 hw->fc.requested_mode = ixgbe_fc_full;
3841 /* Determine PAUSE and ASM_DIR bits. */
3842 switch (hw->fc.requested_mode) {
3847 case ixgbe_fc_tx_pause:
3851 case ixgbe_fc_rx_pause:
3852 /* Rx Flow control is enabled and Tx Flow control is
3853 * disabled by software override. Since there really
3854 * isn't a way to advertise that we are capable of RX
3855 * Pause ONLY, we will advertise that we support both
3856 * symmetric and asymmetric Rx PAUSE, as such we fall
3857 * through to the fc_full statement. Later, we will
3858 * disable the adapter's ability to send PAUSE frames.
3865 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3866 "Flow control param set incorrectly\n");
3867 ret_val = IXGBE_ERR_CONFIG;
3871 switch (hw->device_id) {
3872 case IXGBE_DEV_ID_X550EM_X_KR:
3873 case IXGBE_DEV_ID_X550EM_A_KR:
3874 case IXGBE_DEV_ID_X550EM_A_KR_L:
3875 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3876 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3877 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3878 if (ret_val != IXGBE_SUCCESS)
3880 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3881 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3883 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3885 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3886 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3887 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3888 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3890 /* This device does not fully support AN. */
3891 hw->fc.disable_fc_autoneg = true;
3902 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
3903 * @hw: pointer to hardware structure
3905 * Enable flow control according to IEEE clause 37.
3907 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
3909 u32 link_s1, lp_an_page_low, an_cntl_1;
3910 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3911 ixgbe_link_speed speed;
3914 /* AN should have completed when the cable was plugged in.
3915 * Look for reasons to bail out. Bail out if:
3916 * - FC autoneg is disabled, or if
3919 if (hw->fc.disable_fc_autoneg) {
3920 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3921 "Flow control autoneg is disabled");
3925 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3927 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3931 /* Check at auto-negotiation has completed */
3932 status = hw->mac.ops.read_iosf_sb_reg(hw,
3933 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
3934 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
3936 if (status != IXGBE_SUCCESS ||
3937 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
3938 DEBUGOUT("Auto-Negotiation did not complete\n");
3939 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3943 /* Read the 10g AN autoc and LP ability registers and resolve
3944 * local flow control settings accordingly
3946 status = hw->mac.ops.read_iosf_sb_reg(hw,
3947 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3948 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
3950 if (status != IXGBE_SUCCESS) {
3951 DEBUGOUT("Auto-Negotiation did not complete\n");
3955 status = hw->mac.ops.read_iosf_sb_reg(hw,
3956 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
3957 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
3959 if (status != IXGBE_SUCCESS) {
3960 DEBUGOUT("Auto-Negotiation did not complete\n");
3964 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
3965 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
3966 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
3967 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
3968 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
3971 if (status == IXGBE_SUCCESS) {
3972 hw->fc.fc_was_autonegged = true;
3974 hw->fc.fc_was_autonegged = false;
3975 hw->fc.current_mode = hw->fc.requested_mode;
3980 * ixgbe_fc_autoneg_fiber_x550em_a - Enable flow control IEEE clause 37
3981 * @hw: pointer to hardware structure
3983 * Enable flow control according to IEEE clause 37.
3985 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
3987 u32 link_s1, pcs_an_lp, pcs_an;
3988 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3989 ixgbe_link_speed speed;
3992 /* AN should have completed when the cable was plugged in.
3993 * Look for reasons to bail out. Bail out if:
3994 * - FC autoneg is disabled, or if
3997 if (hw->fc.disable_fc_autoneg) {
3998 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3999 "Flow control autoneg is disabled");
4003 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4005 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4009 /* Check if auto-negotiation has completed */
4010 status = hw->mac.ops.read_iosf_sb_reg(hw,
4011 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4012 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4014 if (status != IXGBE_SUCCESS ||
4015 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4016 DEBUGOUT("Auto-Negotiation did not complete\n");
4017 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4021 /* Determine advertised flow control */
4022 status = hw->mac.ops.read_iosf_sb_reg(hw,
4023 IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4024 IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an);
4026 if (status != IXGBE_SUCCESS) {
4027 DEBUGOUT("Auto-Negotiation did not complete\n");
4031 /* Determine link parter flow control */
4032 status = hw->mac.ops.read_iosf_sb_reg(hw,
4033 IXGBE_KRM_PCS_KX_AN_LP(hw->bus.lan_id),
4034 IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an_lp);
4036 if (status != IXGBE_SUCCESS) {
4037 DEBUGOUT("Auto-Negotiation did not complete\n");
4041 status = ixgbe_negotiate_fc(hw, pcs_an, pcs_an_lp,
4042 IXGBE_KRM_PCS_KX_AN_SYM_PAUSE,
4043 IXGBE_KRM_PCS_KX_AN_ASM_PAUSE,
4044 IXGBE_KRM_PCS_KX_AN_LP_SYM_PAUSE,
4045 IXGBE_KRM_PCS_KX_AN_LP_ASM_PAUSE);
4048 if (status == IXGBE_SUCCESS) {
4049 hw->fc.fc_was_autonegged = true;
4051 hw->fc.fc_was_autonegged = false;
4052 hw->fc.current_mode = hw->fc.requested_mode;
4057 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4058 * @hw: pointer to hardware structure
4060 * Enable flow control according to IEEE clause 37.
4062 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4064 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4065 u16 reg, pcs_an_lp, pcs_an;
4066 ixgbe_link_speed speed;
4069 /* AN should have completed when the cable was plugged in.
4070 * Look for reasons to bail out. Bail out if:
4071 * - FC autoneg is disabled, or if
4074 if (hw->fc.disable_fc_autoneg) {
4075 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4076 "Flow control autoneg is disabled");
4080 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4082 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4086 /* Check if auto-negotiation has completed */
4087 status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_STATUS,
4088 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4089 if (status != IXGBE_SUCCESS ||
4090 (reg & IXGBE_M88E1500_COPPER_STATUS_AN_DONE) == 0) {
4091 DEBUGOUT("Auto-Negotiation did not complete\n");
4092 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4096 /* Get the advertized flow control */
4097 status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4098 IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an);
4099 if (status != IXGBE_SUCCESS)
4102 /* Get link partner's flow control */
4103 status = hw->phy.ops.read_reg(hw,
4104 IXGBE_M88E1500_COPPER_AN_LP_ABILITY,
4105 IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an_lp);
4106 if (status != IXGBE_SUCCESS)
4109 /* Negotiate the flow control */
4110 status = ixgbe_negotiate_fc(hw, (u32)pcs_an, (u32)pcs_an_lp,
4111 IXGBE_M88E1500_COPPER_AN_PAUSE,
4112 IXGBE_M88E1500_COPPER_AN_AS_PAUSE,
4113 IXGBE_M88E1500_COPPER_AN_LP_PAUSE,
4114 IXGBE_M88E1500_COPPER_AN_LP_AS_PAUSE);
4117 if (status == IXGBE_SUCCESS) {
4118 hw->fc.fc_was_autonegged = true;
4120 hw->fc.fc_was_autonegged = false;
4121 hw->fc.current_mode = hw->fc.requested_mode;
4126 * ixgbe_setup_fc_sgmii_x550em_a - Set up flow control
4127 * @hw: pointer to hardware structure
4129 * Called at init time to set up flow control.
4131 s32 ixgbe_setup_fc_sgmii_x550em_a(struct ixgbe_hw *hw)
4136 /* Validate the requested mode */
4137 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4138 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4139 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4140 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4143 if (hw->fc.requested_mode == ixgbe_fc_default)
4144 hw->fc.requested_mode = ixgbe_fc_full;
4146 /* Read contents of the Auto-Negotiation register, page 0 reg 4 */
4147 rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4148 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4152 /* Disable all the settings related to Flow control Auto-negotiation */
4153 reg &= ~IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4154 reg &= ~IXGBE_M88E1500_COPPER_AN_PAUSE;
4156 /* Configure the Asymmetric and symmetric pause according to the user
4159 switch (hw->fc.requested_mode) {
4161 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4162 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4164 case ixgbe_fc_rx_pause:
4165 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4166 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4168 case ixgbe_fc_tx_pause:
4169 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4175 /* Write back to the Auto-Negotiation register with newly configured
4178 hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_AN,
4179 IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4181 /* In this section of the code we restart Auto-negotiation */
4183 /* Read the CONTROL register, Page 0 reg 0 */
4184 rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4185 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4189 /* Set the bit to restart Auto-Neg. The bit to enable Auto-neg is ON
4192 reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
4194 /* write the new values to the register to restart Auto-Negotiation */
4195 hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4196 IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4203 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4204 * @hw: pointer to hardware structure
4206 * Called at init time to set up flow control.
4208 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4210 s32 status = IXGBE_SUCCESS;
4211 u32 an_cntl, link_ctrl = 0;
4213 DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4215 /* Validate the requested mode */
4216 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4217 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4218 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4219 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4222 if (hw->fc.requested_mode == ixgbe_fc_default)
4223 hw->fc.requested_mode = ixgbe_fc_full;
4225 /* Set up the 1G and 10G flow control advertisement registers so the
4226 * HW will be able to do FC autoneg once the cable is plugged in. If
4227 * we link at 10G, the 1G advertisement is harmless and vice versa.
4229 status = hw->mac.ops.read_iosf_sb_reg(hw,
4230 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4231 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4233 if (status != IXGBE_SUCCESS) {
4234 DEBUGOUT("Auto-Negotiation did not complete\n");
4238 /* The possible values of fc.requested_mode are:
4239 * 0: Flow control is completely disabled
4240 * 1: Rx flow control is enabled (we can receive pause frames,
4241 * but not send pause frames).
4242 * 2: Tx flow control is enabled (we can send pause frames but
4243 * we do not support receiving pause frames).
4244 * 3: Both Rx and Tx flow control (symmetric) are enabled.
4247 switch (hw->fc.requested_mode) {
4249 /* Flow control completely disabled by software override. */
4250 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4251 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4253 case ixgbe_fc_tx_pause:
4254 /* Tx Flow control is enabled, and Rx Flow control is
4255 * disabled by software override.
4257 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4258 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4260 case ixgbe_fc_rx_pause:
4261 /* Rx Flow control is enabled and Tx Flow control is
4262 * disabled by software override. Since there really
4263 * isn't a way to advertise that we are capable of RX
4264 * Pause ONLY, we will advertise that we support both
4265 * symmetric and asymmetric Rx PAUSE, as such we fall
4266 * through to the fc_full statement. Later, we will
4267 * disable the adapter's ability to send PAUSE frames.
4270 /* Flow control (both Rx and Tx) is enabled by SW override. */
4271 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4272 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4275 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4276 "Flow control param set incorrectly\n");
4277 return IXGBE_ERR_CONFIG;
4280 status = hw->mac.ops.write_iosf_sb_reg(hw,
4281 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4282 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4284 /* Restart auto-negotiation. */
4285 status = hw->mac.ops.read_iosf_sb_reg(hw,
4286 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4287 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
4289 if (status != IXGBE_SUCCESS) {
4290 DEBUGOUT("Auto-Negotiation did not complete\n");
4294 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
4295 status = hw->mac.ops.write_iosf_sb_reg(hw,
4296 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4297 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
4303 * ixgbe_setup_fc_fiber_x550em_a - Set up flow control
4304 * @hw: pointer to hardware structure
4306 * Called at init time to set up flow control.
4308 s32 ixgbe_setup_fc_fiber_x550em_a(struct ixgbe_hw *hw)
4310 struct ixgbe_mac_info *mac = &hw->mac;
4311 s32 rc = IXGBE_SUCCESS;
4312 u32 an_cntl4, lctrl, pcs_an;
4314 DEBUGFUNC("ixgbe_setup_fc_fiber_x550em_a");
4316 /* Validate the requested mode */
4317 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4318 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4319 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4320 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4323 /* Enable clause 37 auto-negotiation in KRM_LINK_CTRL_1 */
4324 if (hw->fc.requested_mode == ixgbe_fc_default)
4325 hw->fc.requested_mode = ixgbe_fc_full;
4327 rc = mac->ops.read_iosf_sb_reg(hw,
4328 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4329 IXGBE_SB_IOSF_TARGET_KR_PHY, &lctrl);
4333 lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
4334 lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
4336 rc = mac->ops.write_iosf_sb_reg(hw,
4337 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4338 IXGBE_SB_IOSF_TARGET_KR_PHY, lctrl);
4342 /* Enable clause 37 over 73 in KRM_AN_CNTL_4 */
4343 rc = mac->ops.read_iosf_sb_reg(hw,
4344 IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
4345 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl4);
4349 an_cntl4 |= IXGBE_KRM_AN_CNTL_4_ECSR_AN37_OVER_73;
4351 rc = mac->ops.write_iosf_sb_reg(hw,
4352 IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
4353 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl4);
4357 rc = hw->mac.ops.read_iosf_sb_reg(hw,
4358 IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4359 IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an);
4364 /* The possible values of fc.requested_mode are:
4365 * 0: Flow control is completely disabled
4366 * 1: Rx flow control is enabled (we can receive pause frames,
4367 * but not send pause frames).
4368 * 2: Tx flow control is enabled (we can send pause frames but
4369 * we do not support receiving pause frames).
4370 * 3: Both Rx and Tx flow control (symmetric) are enabled.
4373 switch (hw->fc.requested_mode) {
4375 /* Flow control completely disabled by software override. */
4376 pcs_an &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4377 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4379 case ixgbe_fc_tx_pause:
4380 /* Tx Flow control is enabled, and Rx Flow control is
4381 * disabled by software override.
4383 pcs_an |= IXGBE_KRM_PCS_KX_AN_ASM_PAUSE;
4384 pcs_an &= ~IXGBE_KRM_PCS_KX_AN_SYM_PAUSE;
4386 case ixgbe_fc_rx_pause:
4387 /* Rx Flow control is enabled and Tx Flow control is
4388 * disabled by software override. Since there really
4389 * isn't a way to advertise that we are capable of RX
4390 * Pause ONLY, we will advertise that we support both
4391 * symmetric and asymmetric Rx PAUSE, as such we fall
4392 * through to the fc_full statement. Later, we will
4393 * disable the adapter's ability to send PAUSE frames.
4396 /* Flow control (both Rx and Tx) is enabled by SW override. */
4397 pcs_an |= IXGBE_KRM_PCS_KX_AN_SYM_PAUSE |
4398 IXGBE_KRM_PCS_KX_AN_ASM_PAUSE;
4401 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4402 "Flow control param set incorrectly\n");
4403 return IXGBE_ERR_CONFIG;
4406 rc = hw->mac.ops.write_iosf_sb_reg(hw,
4407 IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4408 IXGBE_SB_IOSF_TARGET_KR_PHY, pcs_an);
4410 /* Restart auto-negotiation. */
4411 rc = hw->mac.ops.read_iosf_sb_reg(hw,
4412 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4413 IXGBE_SB_IOSF_TARGET_KR_PHY, &lctrl);
4416 DEBUGOUT("Auto-Negotiation did not complete\n");
4420 lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
4421 rc = hw->mac.ops.write_iosf_sb_reg(hw,
4422 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4423 IXGBE_SB_IOSF_TARGET_KR_PHY, lctrl);
4429 * ixgbe_set_mux - Set mux for port 1 access with CS4227
4430 * @hw: pointer to hardware structure
4431 * @state: set mux if 1, clear if 0
4433 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4437 if (!hw->bus.lan_id)
4439 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4441 esdp |= IXGBE_ESDP_SDP1;
4443 esdp &= ~IXGBE_ESDP_SDP1;
4444 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4445 IXGBE_WRITE_FLUSH(hw);
4449 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4450 * @hw: pointer to hardware structure
4451 * @mask: Mask to specify which semaphore to acquire
4453 * Acquires the SWFW semaphore and sets the I2C MUX
4455 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4459 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4461 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4465 if (mask & IXGBE_GSSR_I2C_MASK)
4466 ixgbe_set_mux(hw, 1);
4468 return IXGBE_SUCCESS;
4472 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4473 * @hw: pointer to hardware structure
4474 * @mask: Mask to specify which semaphore to release
4476 * Releases the SWFW semaphore and sets the I2C MUX
4478 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4480 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4482 if (mask & IXGBE_GSSR_I2C_MASK)
4483 ixgbe_set_mux(hw, 0);
4485 ixgbe_release_swfw_sync_X540(hw, mask);
4489 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4490 * @hw: pointer to hardware structure
4491 * @mask: Mask to specify which semaphore to acquire
4493 * Acquires the SWFW semaphore and get the shared phy token as needed
4495 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4497 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4498 int retries = FW_PHY_TOKEN_RETRIES;
4499 s32 status = IXGBE_SUCCESS;
4501 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4504 status = IXGBE_SUCCESS;
4506 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4509 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4510 return IXGBE_SUCCESS;
4512 status = ixgbe_get_phy_token(hw);
4513 if (status == IXGBE_SUCCESS)
4514 return IXGBE_SUCCESS;
4517 ixgbe_release_swfw_sync_X540(hw, hmask);
4518 if (status != IXGBE_ERR_TOKEN_RETRY)
4520 msec_delay(FW_PHY_TOKEN_DELAY);
4527 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4528 * @hw: pointer to hardware structure
4529 * @mask: Mask to specify which semaphore to release
4531 * Releases the SWFW semaphore and puts the shared phy token as needed
4533 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4535 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4537 DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4539 if (mask & IXGBE_GSSR_TOKEN_SM)
4540 ixgbe_put_phy_token(hw);
4543 ixgbe_release_swfw_sync_X540(hw, hmask);
4547 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
4548 * @hw: pointer to hardware structure
4549 * @reg_addr: 32 bit address of PHY register to read
4550 * @phy_data: Pointer to read data from PHY register
4552 * Reads a value from a specified PHY register using the SWFW lock and PHY
4553 * Token. The PHY Token is needed since the MDIO is shared between to MAC
4556 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4557 u32 device_type, u16 *phy_data)
4560 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4562 DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4564 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4565 return IXGBE_ERR_SWFW_SYNC;
4567 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4569 hw->mac.ops.release_swfw_sync(hw, mask);
4575 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
4576 * @hw: pointer to hardware structure
4577 * @reg_addr: 32 bit PHY register to write
4578 * @device_type: 5 bit device type
4579 * @phy_data: Data to write to the PHY register
4581 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
4582 * The PHY Token is needed since the MDIO is shared between to MAC instances.
4584 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4585 u32 device_type, u16 phy_data)
4588 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4590 DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4592 if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4593 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4595 hw->mac.ops.release_swfw_sync(hw, mask);
4597 status = IXGBE_ERR_SWFW_SYNC;
4604 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4605 * @hw: pointer to hardware structure
4607 * Handle external Base T PHY interrupt. If high temperature
4608 * failure alarm then return error, else if link status change
4609 * then setup internal/external PHY link
4611 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4612 * failure alarm, else return PHY access status.
4614 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4619 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4621 if (status != IXGBE_SUCCESS)
4625 return ixgbe_setup_internal_phy(hw);
4627 return IXGBE_SUCCESS;
4631 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4632 * @hw: pointer to hardware structure
4633 * @speed: new link speed
4634 * @autoneg_wait_to_complete: true when waiting for completion is needed
4636 * Setup internal/external PHY link speed based on link speed, then set
4637 * external PHY auto advertised link speed.
4639 * Returns error status for any failure
4641 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4642 ixgbe_link_speed speed,
4643 bool autoneg_wait_to_complete)
4646 ixgbe_link_speed force_speed;
4648 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4650 /* Setup internal/external PHY link speed to iXFI (10G), unless
4651 * only 1G is auto advertised then setup KX link.
4653 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4654 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4656 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4658 /* If internal link mode is XFI, then setup XFI internal link. */
4659 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4660 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4662 if (status != IXGBE_SUCCESS)
4666 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4670 * ixgbe_check_link_t_X550em - Determine link and speed status
4671 * @hw: pointer to hardware structure
4672 * @speed: pointer to link speed
4673 * @link_up: true when link is up
4674 * @link_up_wait_to_complete: bool used to wait for link up or not
4676 * Check that both the MAC and X557 external PHY have link.
4678 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4679 bool *link_up, bool link_up_wait_to_complete)
4684 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4685 return IXGBE_ERR_CONFIG;
4687 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4688 link_up_wait_to_complete);
4690 /* If check link fails or MAC link is not up, then return */
4691 if (status != IXGBE_SUCCESS || !(*link_up))
4694 /* MAC link is up, so check external PHY link.
4695 * Read this twice back to back to indicate current status.
4697 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4698 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4701 if (status != IXGBE_SUCCESS)
4704 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4705 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4708 if (status != IXGBE_SUCCESS)
4711 /* If external PHY link is not up, then indicate link not up */
4712 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4715 return IXGBE_SUCCESS;
4719 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4720 * @hw: pointer to hardware structure
4722 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4726 status = ixgbe_reset_phy_generic(hw);
4728 if (status != IXGBE_SUCCESS)
4731 /* Configure Link Status Alarm and Temperature Threshold interrupts */
4732 return ixgbe_enable_lasi_ext_t_x550em(hw);
4736 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4737 * @hw: pointer to hardware structure
4738 * @led_idx: led number to turn on
4740 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4744 DEBUGFUNC("ixgbe_led_on_t_X550em");
4746 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4747 return IXGBE_ERR_PARAM;
4749 /* To turn on the LED, set mode to ON. */
4750 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4751 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4752 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4753 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4754 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4756 return IXGBE_SUCCESS;
4760 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4761 * @hw: pointer to hardware structure
4762 * @led_idx: led number to turn off
4764 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4768 DEBUGFUNC("ixgbe_led_off_t_X550em");
4770 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4771 return IXGBE_ERR_PARAM;
4773 /* To turn on the LED, set mode to ON. */
4774 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4775 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4776 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4777 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4778 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4780 return IXGBE_SUCCESS;