1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
47 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
48 * @hw: pointer to hardware structure
50 * Initialize the function pointers and assign the MAC type for X550.
51 * Does not touch the hardware.
53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
55 struct ixgbe_mac_info *mac = &hw->mac;
56 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
59 DEBUGFUNC("ixgbe_init_ops_X550");
61 ret_val = ixgbe_init_ops_X540(hw);
62 mac->ops.dmac_config = ixgbe_dmac_config_X550;
63 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
64 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
65 mac->ops.setup_eee = ixgbe_setup_eee_X550;
66 mac->ops.set_source_address_pruning =
67 ixgbe_set_source_address_pruning_X550;
68 mac->ops.set_ethertype_anti_spoofing =
69 ixgbe_set_ethertype_anti_spoofing_X550;
71 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
72 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
73 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
74 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
75 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
76 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
77 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
78 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
79 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
81 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
82 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
83 mac->ops.mdd_event = ixgbe_mdd_event_X550;
84 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
85 mac->ops.disable_rx = ixgbe_disable_rx_x550;
86 /* Manageability interface */
87 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
88 switch (hw->device_id) {
89 case IXGBE_DEV_ID_X550EM_X_10G_T:
90 case IXGBE_DEV_ID_X550EM_A_10G_T:
91 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
92 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
101 * ixgbe_read_cs4227 - Read CS4227 register
102 * @hw: pointer to hardware structure
103 * @reg: register number to write
104 * @value: pointer to receive value read
106 * Returns status code
108 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
110 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
114 * ixgbe_write_cs4227 - Write CS4227 register
115 * @hw: pointer to hardware structure
116 * @reg: register number to write
117 * @value: value to write to register
119 * Returns status code
121 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
123 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
127 * ixgbe_read_pe - Read register from port expander
128 * @hw: pointer to hardware structure
129 * @reg: register number to read
130 * @value: pointer to receive read value
132 * Returns status code
134 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
138 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
139 if (status != IXGBE_SUCCESS)
140 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
141 "port expander access failed with %d\n", status);
146 * ixgbe_write_pe - Write register to port expander
147 * @hw: pointer to hardware structure
148 * @reg: register number to write
149 * @value: value to write
151 * Returns status code
153 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
157 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
158 if (status != IXGBE_SUCCESS)
159 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
160 "port expander access failed with %d\n", status);
165 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
166 * @hw: pointer to hardware structure
168 * This function assumes that the caller has acquired the proper semaphore.
171 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
178 /* Trigger hard reset. */
179 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
180 if (status != IXGBE_SUCCESS)
182 reg |= IXGBE_PE_BIT1;
183 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
184 if (status != IXGBE_SUCCESS)
187 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
188 if (status != IXGBE_SUCCESS)
190 reg &= ~IXGBE_PE_BIT1;
191 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
192 if (status != IXGBE_SUCCESS)
195 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
196 if (status != IXGBE_SUCCESS)
198 reg &= ~IXGBE_PE_BIT1;
199 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
200 if (status != IXGBE_SUCCESS)
203 usec_delay(IXGBE_CS4227_RESET_HOLD);
205 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
206 if (status != IXGBE_SUCCESS)
208 reg |= IXGBE_PE_BIT1;
209 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
210 if (status != IXGBE_SUCCESS)
213 /* Wait for the reset to complete. */
214 msec_delay(IXGBE_CS4227_RESET_DELAY);
215 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
216 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
218 if (status == IXGBE_SUCCESS &&
219 value == IXGBE_CS4227_EEPROM_LOAD_OK)
221 msec_delay(IXGBE_CS4227_CHECK_DELAY);
223 if (retry == IXGBE_CS4227_RETRIES) {
224 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
225 "CS4227 reset did not complete.");
226 return IXGBE_ERR_PHY;
229 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
230 if (status != IXGBE_SUCCESS ||
231 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
232 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
233 "CS4227 EEPROM did not load successfully.");
234 return IXGBE_ERR_PHY;
237 return IXGBE_SUCCESS;
241 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
242 * @hw: pointer to hardware structure
244 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
246 s32 status = IXGBE_SUCCESS;
247 u32 swfw_mask = hw->phy.phy_semaphore_mask;
251 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
252 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
253 if (status != IXGBE_SUCCESS) {
254 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
255 "semaphore failed with %d", status);
256 msec_delay(IXGBE_CS4227_CHECK_DELAY);
260 /* Get status of reset flow. */
261 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
263 if (status == IXGBE_SUCCESS &&
264 value == IXGBE_CS4227_RESET_COMPLETE)
267 if (status != IXGBE_SUCCESS ||
268 value != IXGBE_CS4227_RESET_PENDING)
271 /* Reset is pending. Wait and check again. */
272 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
273 msec_delay(IXGBE_CS4227_CHECK_DELAY);
276 /* If still pending, assume other instance failed. */
277 if (retry == IXGBE_CS4227_RETRIES) {
278 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
279 if (status != IXGBE_SUCCESS) {
280 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
281 "semaphore failed with %d", status);
286 /* Reset the CS4227. */
287 status = ixgbe_reset_cs4227(hw);
288 if (status != IXGBE_SUCCESS) {
289 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
290 "CS4227 reset failed: %d", status);
294 /* Reset takes so long, temporarily release semaphore in case the
295 * other driver instance is waiting for the reset indication.
297 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
298 IXGBE_CS4227_RESET_PENDING);
299 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
301 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
302 if (status != IXGBE_SUCCESS) {
303 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
304 "semaphore failed with %d", status);
308 /* Record completion for next time. */
309 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
310 IXGBE_CS4227_RESET_COMPLETE);
313 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
314 msec_delay(hw->eeprom.semaphore_delay);
318 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
319 * @hw: pointer to hardware structure
321 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
323 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
325 if (hw->bus.lan_id) {
326 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
327 esdp |= IXGBE_ESDP_SDP1_DIR;
329 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
330 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
331 IXGBE_WRITE_FLUSH(hw);
335 * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
336 * @hw: pointer to hardware structure
337 * @reg_addr: 32 bit address of PHY register to read
338 * @dev_type: always unused
339 * @phy_data: Pointer to read data from PHY register
341 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
342 u32 dev_type, u16 *phy_data)
344 u32 i, data, command;
345 UNREFERENCED_1PARAMETER(dev_type);
347 /* Setup and write the read command */
348 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
349 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
350 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
351 IXGBE_MSCA_MDI_COMMAND;
353 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
355 /* Check every 10 usec to see if the access completed.
356 * The MDI Command bit will clear when the operation is
359 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
362 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
363 if (!(command & IXGBE_MSCA_MDI_COMMAND))
367 if (command & IXGBE_MSCA_MDI_COMMAND) {
368 ERROR_REPORT1(IXGBE_ERROR_POLLING,
369 "PHY read command did not complete.\n");
370 return IXGBE_ERR_PHY;
373 /* Read operation is complete. Get the data from MSRWD */
374 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
375 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
376 *phy_data = (u16)data;
378 return IXGBE_SUCCESS;
382 * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
383 * @hw: pointer to hardware structure
384 * @reg_addr: 32 bit PHY register to write
385 * @dev_type: always unused
386 * @phy_data: Data to write to the PHY register
388 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
389 u32 dev_type, u16 phy_data)
392 UNREFERENCED_1PARAMETER(dev_type);
394 /* Put the data in the MDI single read and write data register*/
395 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
397 /* Setup and write the write command */
398 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
399 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
400 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
401 IXGBE_MSCA_MDI_COMMAND;
403 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
405 /* Check every 10 usec to see if the access completed.
406 * The MDI Command bit will clear when the operation is
409 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
412 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
413 if (!(command & IXGBE_MSCA_MDI_COMMAND))
417 if (command & IXGBE_MSCA_MDI_COMMAND) {
418 ERROR_REPORT1(IXGBE_ERROR_POLLING,
419 "PHY write cmd didn't complete\n");
420 return IXGBE_ERR_PHY;
423 return IXGBE_SUCCESS;
427 * ixgbe_identify_phy_x550em - Get PHY type based on device id
428 * @hw: pointer to hardware structure
432 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
434 hw->mac.ops.set_lan_id(hw);
436 ixgbe_read_mng_if_sel_x550em(hw);
438 switch (hw->device_id) {
439 case IXGBE_DEV_ID_X550EM_A_SFP:
440 return ixgbe_identify_module_generic(hw);
441 case IXGBE_DEV_ID_X550EM_X_SFP:
442 /* set up for CS4227 usage */
443 ixgbe_setup_mux_ctl(hw);
444 ixgbe_check_cs4227(hw);
447 case IXGBE_DEV_ID_X550EM_A_SFP_N:
448 return ixgbe_identify_module_generic(hw);
450 case IXGBE_DEV_ID_X550EM_X_KX4:
451 hw->phy.type = ixgbe_phy_x550em_kx4;
453 case IXGBE_DEV_ID_X550EM_X_KR:
454 case IXGBE_DEV_ID_X550EM_A_KR:
455 case IXGBE_DEV_ID_X550EM_A_KR_L:
456 hw->phy.type = ixgbe_phy_x550em_kr;
458 case IXGBE_DEV_ID_X550EM_A_10G_T:
459 case IXGBE_DEV_ID_X550EM_A_1G_T:
460 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
461 case IXGBE_DEV_ID_X550EM_X_1G_T:
462 case IXGBE_DEV_ID_X550EM_X_10G_T:
463 return ixgbe_identify_phy_generic(hw);
467 return IXGBE_SUCCESS;
470 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
471 u32 device_type, u16 *phy_data)
473 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
474 return IXGBE_NOT_IMPLEMENTED;
477 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
478 u32 device_type, u16 phy_data)
480 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
481 return IXGBE_NOT_IMPLEMENTED;
485 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
486 * @hw: pointer to the hardware structure
487 * @addr: I2C bus address to read from
488 * @reg: I2C device register to read from
489 * @val: pointer to location to receive read value
491 * Returns an error code on error.
493 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
496 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
500 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
501 * @hw: pointer to the hardware structure
502 * @addr: I2C bus address to read from
503 * @reg: I2C device register to read from
504 * @val: pointer to location to receive read value
506 * Returns an error code on error.
509 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
512 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
516 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
517 * @hw: pointer to the hardware structure
518 * @addr: I2C bus address to write to
519 * @reg: I2C device register to write to
520 * @val: value to write
522 * Returns an error code on error.
524 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
525 u8 addr, u16 reg, u16 val)
527 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
531 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
532 * @hw: pointer to the hardware structure
533 * @addr: I2C bus address to write to
534 * @reg: I2C device register to write to
535 * @val: value to write
537 * Returns an error code on error.
540 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
541 u8 addr, u16 reg, u16 val)
543 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
547 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
548 * @hw: pointer to hardware structure
550 * Initialize the function pointers and for MAC type X550EM.
551 * Does not touch the hardware.
553 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
555 struct ixgbe_mac_info *mac = &hw->mac;
556 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
557 struct ixgbe_phy_info *phy = &hw->phy;
560 DEBUGFUNC("ixgbe_init_ops_X550EM");
562 /* Similar to X550 so start there. */
563 ret_val = ixgbe_init_ops_X550(hw);
565 /* Since this function eventually calls
566 * ixgbe_init_ops_540 by design, we are setting
567 * the pointers to NULL explicitly here to overwrite
568 * the values being set in the x540 function.
570 /* Thermal sensor not supported in x550EM */
571 mac->ops.get_thermal_sensor_data = NULL;
572 mac->ops.init_thermal_sensor_thresh = NULL;
573 mac->thermal_sensor_enabled = false;
575 /* FCOE not supported in x550EM */
576 mac->ops.get_san_mac_addr = NULL;
577 mac->ops.set_san_mac_addr = NULL;
578 mac->ops.get_wwn_prefix = NULL;
579 mac->ops.get_fcoe_boot_status = NULL;
581 /* IPsec not supported in x550EM */
582 mac->ops.disable_sec_rx_path = NULL;
583 mac->ops.enable_sec_rx_path = NULL;
585 /* AUTOC register is not present in x550EM. */
586 mac->ops.prot_autoc_read = NULL;
587 mac->ops.prot_autoc_write = NULL;
589 /* X550EM bus type is internal*/
590 hw->bus.type = ixgbe_bus_type_internal;
591 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
594 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
595 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
596 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
597 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
598 mac->ops.get_supported_physical_layer =
599 ixgbe_get_supported_physical_layer_X550em;
601 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
602 mac->ops.setup_fc = ixgbe_setup_fc_generic;
604 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
606 switch (hw->device_id) {
607 case IXGBE_DEV_ID_X550EM_X_KR:
608 case IXGBE_DEV_ID_X550EM_A_KR:
609 case IXGBE_DEV_ID_X550EM_A_KR_L:
612 mac->ops.setup_eee = NULL;
616 phy->ops.init = ixgbe_init_phy_ops_X550em;
617 phy->ops.identify = ixgbe_identify_phy_x550em;
618 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
619 phy->ops.set_phy_power = NULL;
623 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
624 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
625 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
626 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
627 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
628 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
629 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
630 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
636 * ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
637 * @hw: pointer to hardware structure
639 * Initialize the function pointers and for MAC type X550EM_a.
640 * Does not touch the hardware.
642 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
644 struct ixgbe_mac_info *mac = &hw->mac;
647 DEBUGFUNC("ixgbe_init_ops_X550EM_a");
649 /* Start with generic X550EM init */
650 ret_val = ixgbe_init_ops_X550EM(hw);
652 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
653 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
654 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
655 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
657 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
658 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
660 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
661 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
663 switch (mac->ops.get_media_type(hw)) {
664 case ixgbe_media_type_fiber:
665 mac->ops.setup_fc = NULL;
666 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
668 case ixgbe_media_type_backplane:
669 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
670 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
676 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T) ||
677 (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)) {
678 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
679 mac->ops.setup_fc = ixgbe_setup_fc_sgmii_x550em_a;
686 * ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
687 * @hw: pointer to hardware structure
689 * Initialize the function pointers and for MAC type X550EM_x.
690 * Does not touch the hardware.
692 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
694 struct ixgbe_mac_info *mac = &hw->mac;
695 struct ixgbe_link_info *link = &hw->link;
698 DEBUGFUNC("ixgbe_init_ops_X550EM_x");
700 /* Start with generic X550EM init */
701 ret_val = ixgbe_init_ops_X550EM(hw);
703 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
704 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
705 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
706 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
707 link->ops.read_link = ixgbe_read_i2c_combined_generic;
708 link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
709 link->ops.write_link = ixgbe_write_i2c_combined_generic;
710 link->ops.write_link_unlocked =
711 ixgbe_write_i2c_combined_generic_unlocked;
712 link->addr = IXGBE_CS4227;
718 * ixgbe_dmac_config_X550
719 * @hw: pointer to hardware structure
721 * Configure DMA coalescing. If enabling dmac, dmac is activated.
722 * When disabling dmac, dmac enable dmac bit is cleared.
724 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
726 u32 reg, high_pri_tc;
728 DEBUGFUNC("ixgbe_dmac_config_X550");
730 /* Disable DMA coalescing before configuring */
731 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
732 reg &= ~IXGBE_DMACR_DMAC_EN;
733 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
735 /* Disable DMA Coalescing if the watchdog timer is 0 */
736 if (!hw->mac.dmac_config.watchdog_timer)
739 ixgbe_dmac_config_tcs_X550(hw);
741 /* Configure DMA Coalescing Control Register */
742 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
744 /* Set the watchdog timer in units of 40.96 usec */
745 reg &= ~IXGBE_DMACR_DMACWT_MASK;
746 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
748 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
749 /* If fcoe is enabled, set high priority traffic class */
750 if (hw->mac.dmac_config.fcoe_en) {
751 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
752 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
753 IXGBE_DMACR_HIGH_PRI_TC_MASK);
755 reg |= IXGBE_DMACR_EN_MNG_IND;
757 /* Enable DMA coalescing after configuration */
758 reg |= IXGBE_DMACR_DMAC_EN;
759 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
762 return IXGBE_SUCCESS;
766 * ixgbe_dmac_config_tcs_X550
767 * @hw: pointer to hardware structure
769 * Configure DMA coalescing threshold per TC. The dmac enable bit must
770 * be cleared before configuring.
772 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
774 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
776 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
778 /* Configure DMA coalescing enabled */
779 switch (hw->mac.dmac_config.link_speed) {
780 case IXGBE_LINK_SPEED_10_FULL:
781 case IXGBE_LINK_SPEED_100_FULL:
782 pb_headroom = IXGBE_DMACRXT_100M;
784 case IXGBE_LINK_SPEED_1GB_FULL:
785 pb_headroom = IXGBE_DMACRXT_1G;
788 pb_headroom = IXGBE_DMACRXT_10G;
792 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
793 IXGBE_MHADD_MFS_SHIFT) / 1024);
795 /* Set the per Rx packet buffer receive threshold */
796 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
797 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
798 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
800 if (tc < hw->mac.dmac_config.num_tcs) {
802 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
803 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
804 IXGBE_RXPBSIZE_SHIFT;
806 /* Calculate receive buffer threshold in kilobytes */
807 if (rx_pb_size > pb_headroom)
808 rx_pb_size = rx_pb_size - pb_headroom;
812 /* Minimum of MFS shall be set for DMCTH */
813 reg |= (rx_pb_size > maxframe_size_kb) ?
814 rx_pb_size : maxframe_size_kb;
816 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
818 return IXGBE_SUCCESS;
822 * ixgbe_dmac_update_tcs_X550
823 * @hw: pointer to hardware structure
825 * Disables dmac, updates per TC settings, and then enables dmac.
827 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
831 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
833 /* Disable DMA coalescing before configuring */
834 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
835 reg &= ~IXGBE_DMACR_DMAC_EN;
836 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
838 ixgbe_dmac_config_tcs_X550(hw);
840 /* Enable DMA coalescing after configuration */
841 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
842 reg |= IXGBE_DMACR_DMAC_EN;
843 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
845 return IXGBE_SUCCESS;
849 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
850 * @hw: pointer to hardware structure
852 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
853 * ixgbe_hw struct in order to set up EEPROM access.
855 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
857 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
861 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
863 if (eeprom->type == ixgbe_eeprom_uninitialized) {
864 eeprom->semaphore_delay = 10;
865 eeprom->type = ixgbe_flash;
867 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
868 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
869 IXGBE_EEC_SIZE_SHIFT);
870 eeprom->word_size = 1 << (eeprom_size +
871 IXGBE_EEPROM_WORD_SIZE_SHIFT);
873 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
874 eeprom->type, eeprom->word_size);
877 return IXGBE_SUCCESS;
881 * ixgbe_enable_eee_x550 - Enable EEE support
882 * @hw: pointer to hardware structure
884 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
890 if (hw->mac.type == ixgbe_mac_X550) {
891 /* Advertise EEE capability */
892 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
893 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
896 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
897 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
898 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
900 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
901 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
903 return IXGBE_SUCCESS;
906 switch (hw->device_id) {
907 case IXGBE_DEV_ID_X550EM_X_KR:
908 case IXGBE_DEV_ID_X550EM_A_KR:
909 case IXGBE_DEV_ID_X550EM_A_KR_L:
910 status = hw->mac.ops.read_iosf_sb_reg(hw,
911 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
912 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
913 if (status != IXGBE_SUCCESS)
916 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
917 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
919 /* Don't advertise FEC capability when EEE enabled. */
920 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
922 status = hw->mac.ops.write_iosf_sb_reg(hw,
923 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
924 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
925 if (status != IXGBE_SUCCESS)
932 return IXGBE_SUCCESS;
936 * ixgbe_disable_eee_x550 - Disable EEE support
937 * @hw: pointer to hardware structure
939 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
945 if (hw->mac.type == ixgbe_mac_X550) {
946 /* Disable advertised EEE capability */
947 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
948 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
951 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
952 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
953 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
955 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
956 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
958 return IXGBE_SUCCESS;
961 switch (hw->device_id) {
962 case IXGBE_DEV_ID_X550EM_X_KR:
963 case IXGBE_DEV_ID_X550EM_A_KR:
964 case IXGBE_DEV_ID_X550EM_A_KR_L:
965 status = hw->mac.ops.read_iosf_sb_reg(hw,
966 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
967 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
968 if (status != IXGBE_SUCCESS)
971 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
972 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
974 /* Advertise FEC capability when EEE is disabled. */
975 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
977 status = hw->mac.ops.write_iosf_sb_reg(hw,
978 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
979 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
980 if (status != IXGBE_SUCCESS)
987 return IXGBE_SUCCESS;
991 * ixgbe_setup_eee_X550 - Enable/disable EEE support
992 * @hw: pointer to the HW structure
993 * @enable_eee: boolean flag to enable EEE
995 * Enable/disable EEE based on enable_eee flag.
996 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
1000 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
1005 DEBUGFUNC("ixgbe_setup_eee_X550");
1007 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
1008 /* Enable or disable EEE per flag */
1010 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1012 /* Not supported on first revision of X550EM_x. */
1013 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1014 !(IXGBE_FUSES0_REV_MASK &
1015 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1016 return IXGBE_SUCCESS;
1018 status = ixgbe_enable_eee_x550(hw);
1022 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1024 status = ixgbe_disable_eee_x550(hw);
1028 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1030 return IXGBE_SUCCESS;
1034 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1035 * @hw: pointer to hardware structure
1036 * @enable: enable or disable source address pruning
1037 * @pool: Rx pool to set source address pruning for
1039 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1044 /* max rx pool is 63 */
1048 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1049 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1052 pfflp |= (1ULL << pool);
1054 pfflp &= ~(1ULL << pool);
1056 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1057 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1061 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1062 * @hw: pointer to hardware structure
1063 * @enable: enable or disable switch for Ethertype anti-spoofing
1064 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1067 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1068 bool enable, int vf)
1070 int vf_target_reg = vf >> 3;
1071 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1074 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1076 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1078 pfvfspoof |= (1 << vf_target_shift);
1080 pfvfspoof &= ~(1 << vf_target_shift);
1082 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1086 * ixgbe_iosf_wait - Wait for IOSF command completion
1087 * @hw: pointer to hardware structure
1088 * @ctrl: pointer to location to receive final IOSF control value
1090 * Returns failing status on timeout
1092 * Note: ctrl can be NULL if the IOSF control register value is not needed
1094 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1098 /* Check every 10 usec to see if the address cycle completed.
1099 * The SB IOSF BUSY bit will clear when the operation is
1102 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1103 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1104 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1110 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1111 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1112 return IXGBE_ERR_PHY;
1115 return IXGBE_SUCCESS;
1119 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1120 * of the IOSF device
1121 * @hw: pointer to hardware structure
1122 * @reg_addr: 32 bit PHY register to write
1123 * @device_type: 3 bit device type
1124 * @data: Data to write to the register
1126 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1127 u32 device_type, u32 data)
1129 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1133 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1134 if (ret != IXGBE_SUCCESS)
1137 ret = ixgbe_iosf_wait(hw, NULL);
1138 if (ret != IXGBE_SUCCESS)
1141 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1142 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1144 /* Write IOSF control register */
1145 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1147 /* Write IOSF data register */
1148 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1150 ret = ixgbe_iosf_wait(hw, &command);
1152 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1153 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1154 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1155 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1156 "Failed to write, error %x\n", error);
1157 ret = IXGBE_ERR_PHY;
1161 ixgbe_release_swfw_semaphore(hw, gssr);
1166 * ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1167 * @hw: pointer to hardware structure
1168 * @reg_addr: 32 bit PHY register to write
1169 * @device_type: 3 bit device type
1170 * @data: Pointer to read data from the register
1172 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1173 u32 device_type, u32 *data)
1175 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1179 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1180 if (ret != IXGBE_SUCCESS)
1183 ret = ixgbe_iosf_wait(hw, NULL);
1184 if (ret != IXGBE_SUCCESS)
1187 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1188 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1190 /* Write IOSF control register */
1191 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1193 ret = ixgbe_iosf_wait(hw, &command);
1195 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1196 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1197 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1198 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1199 "Failed to read, error %x\n", error);
1200 ret = IXGBE_ERR_PHY;
1203 if (ret == IXGBE_SUCCESS)
1204 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1207 ixgbe_release_swfw_semaphore(hw, gssr);
1212 * ixgbe_get_phy_token - Get the token for shared phy access
1213 * @hw: Pointer to hardware structure
1216 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1218 struct ixgbe_hic_phy_token_req token_cmd;
1221 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1222 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1223 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1224 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1225 token_cmd.port_number = hw->bus.lan_id;
1226 token_cmd.command_type = FW_PHY_TOKEN_REQ;
1228 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1230 IXGBE_HI_COMMAND_TIMEOUT,
1234 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1235 return IXGBE_SUCCESS;
1236 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1237 return IXGBE_ERR_FW_RESP_INVALID;
1239 return IXGBE_ERR_TOKEN_RETRY;
1243 * ixgbe_put_phy_token - Put the token for shared phy access
1244 * @hw: Pointer to hardware structure
1247 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1249 struct ixgbe_hic_phy_token_req token_cmd;
1252 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1253 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1254 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1255 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1256 token_cmd.port_number = hw->bus.lan_id;
1257 token_cmd.command_type = FW_PHY_TOKEN_REL;
1259 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1261 IXGBE_HI_COMMAND_TIMEOUT,
1265 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1266 return IXGBE_SUCCESS;
1268 DEBUGOUT("Put PHY Token host interface command failed");
1269 return IXGBE_ERR_FW_RESP_INVALID;
1273 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1274 * of the IOSF device
1275 * @hw: pointer to hardware structure
1276 * @reg_addr: 32 bit PHY register to write
1277 * @device_type: 3 bit device type
1278 * @data: Data to write to the register
1280 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1281 u32 device_type, u32 data)
1283 struct ixgbe_hic_internal_phy_req write_cmd;
1285 UNREFERENCED_1PARAMETER(device_type);
1287 memset(&write_cmd, 0, sizeof(write_cmd));
1288 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1289 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1290 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1291 write_cmd.port_number = hw->bus.lan_id;
1292 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1293 write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1294 write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1296 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1298 IXGBE_HI_COMMAND_TIMEOUT, false);
1304 * ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1305 * @hw: pointer to hardware structure
1306 * @reg_addr: 32 bit PHY register to write
1307 * @device_type: 3 bit device type
1308 * @data: Pointer to read data from the register
1310 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1311 u32 device_type, u32 *data)
1314 struct ixgbe_hic_internal_phy_req cmd;
1315 struct ixgbe_hic_internal_phy_resp rsp;
1318 UNREFERENCED_1PARAMETER(device_type);
1320 memset(&hic, 0, sizeof(hic));
1321 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1322 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1323 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1324 hic.cmd.port_number = hw->bus.lan_id;
1325 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1326 hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1328 status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1330 IXGBE_HI_COMMAND_TIMEOUT, true);
1332 /* Extract the register value from the response. */
1333 *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1339 * ixgbe_disable_mdd_X550
1340 * @hw: pointer to hardware structure
1342 * Disable malicious driver detection
1344 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1348 DEBUGFUNC("ixgbe_disable_mdd_X550");
1350 /* Disable MDD for TX DMA and interrupt */
1351 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1352 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1353 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1355 /* Disable MDD for RX and interrupt */
1356 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1357 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1358 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1362 * ixgbe_enable_mdd_X550
1363 * @hw: pointer to hardware structure
1365 * Enable malicious driver detection
1367 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1371 DEBUGFUNC("ixgbe_enable_mdd_X550");
1373 /* Enable MDD for TX DMA and interrupt */
1374 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1375 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1376 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1378 /* Enable MDD for RX and interrupt */
1379 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1380 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1381 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1385 * ixgbe_restore_mdd_vf_X550
1386 * @hw: pointer to hardware structure
1389 * Restore VF that was disabled during malicious driver detection event
1391 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1393 u32 idx, reg, num_qs, start_q, bitmask;
1395 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1397 /* Map VF to queues */
1398 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1399 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1400 case IXGBE_MRQC_VMDQRT8TCEN:
1401 num_qs = 8; /* 16 VFs / pools */
1402 bitmask = 0x000000FF;
1404 case IXGBE_MRQC_VMDQRSS32EN:
1405 case IXGBE_MRQC_VMDQRT4TCEN:
1406 num_qs = 4; /* 32 VFs / pools */
1407 bitmask = 0x0000000F;
1409 default: /* 64 VFs / pools */
1411 bitmask = 0x00000003;
1414 start_q = vf * num_qs;
1416 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1419 reg |= (bitmask << (start_q % 32));
1420 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1421 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1425 * ixgbe_mdd_event_X550
1426 * @hw: pointer to hardware structure
1427 * @vf_bitmap: vf bitmap of malicious vfs
1429 * Handle malicious driver detection event.
1431 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1434 u32 i, j, reg, q, shift, vf, idx;
1436 DEBUGFUNC("ixgbe_mdd_event_X550");
1438 /* figure out pool size for mapping to vf's */
1439 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1440 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1441 case IXGBE_MRQC_VMDQRT8TCEN:
1442 shift = 3; /* 16 VFs / pools */
1444 case IXGBE_MRQC_VMDQRSS32EN:
1445 case IXGBE_MRQC_VMDQRT4TCEN:
1446 shift = 2; /* 32 VFs / pools */
1449 shift = 1; /* 64 VFs / pools */
1453 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1454 for (i = 0; i < 4; i++) {
1455 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1456 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1461 /* Get malicious queue */
1462 for (j = 0; j < 32 && wqbr; j++) {
1464 if (!(wqbr & (1 << j)))
1467 /* Get queue from bitmask */
1470 /* Map queue to vf */
1473 /* Set vf bit in vf_bitmap */
1475 vf_bitmap[idx] |= (1 << (vf % 32));
1482 * ixgbe_get_media_type_X550em - Get media type
1483 * @hw: pointer to hardware structure
1485 * Returns the media type (fiber, copper, backplane)
1487 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1489 enum ixgbe_media_type media_type;
1491 DEBUGFUNC("ixgbe_get_media_type_X550em");
1493 /* Detect if there is a copper PHY attached. */
1494 switch (hw->device_id) {
1495 case IXGBE_DEV_ID_X550EM_X_KR:
1496 case IXGBE_DEV_ID_X550EM_X_KX4:
1497 case IXGBE_DEV_ID_X550EM_A_KR:
1498 case IXGBE_DEV_ID_X550EM_A_KR_L:
1499 media_type = ixgbe_media_type_backplane;
1501 case IXGBE_DEV_ID_X550EM_X_SFP:
1502 case IXGBE_DEV_ID_X550EM_A_SFP:
1503 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1504 case IXGBE_DEV_ID_X550EM_A_QSFP:
1505 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1506 media_type = ixgbe_media_type_fiber;
1508 case IXGBE_DEV_ID_X550EM_X_1G_T:
1509 case IXGBE_DEV_ID_X550EM_X_10G_T:
1510 case IXGBE_DEV_ID_X550EM_A_10G_T:
1511 media_type = ixgbe_media_type_copper;
1513 case IXGBE_DEV_ID_X550EM_A_SGMII:
1514 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1515 media_type = ixgbe_media_type_backplane;
1516 hw->phy.type = ixgbe_phy_sgmii;
1518 case IXGBE_DEV_ID_X550EM_A_1G_T:
1519 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1520 media_type = ixgbe_media_type_copper;
1523 media_type = ixgbe_media_type_unknown;
1530 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1531 * @hw: pointer to hardware structure
1532 * @linear: true if SFP module is linear
1534 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1536 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1538 switch (hw->phy.sfp_type) {
1539 case ixgbe_sfp_type_not_present:
1540 return IXGBE_ERR_SFP_NOT_PRESENT;
1541 case ixgbe_sfp_type_da_cu_core0:
1542 case ixgbe_sfp_type_da_cu_core1:
1545 case ixgbe_sfp_type_srlr_core0:
1546 case ixgbe_sfp_type_srlr_core1:
1547 case ixgbe_sfp_type_da_act_lmt_core0:
1548 case ixgbe_sfp_type_da_act_lmt_core1:
1549 case ixgbe_sfp_type_1g_sx_core0:
1550 case ixgbe_sfp_type_1g_sx_core1:
1551 case ixgbe_sfp_type_1g_lx_core0:
1552 case ixgbe_sfp_type_1g_lx_core1:
1555 case ixgbe_sfp_type_unknown:
1556 case ixgbe_sfp_type_1g_cu_core0:
1557 case ixgbe_sfp_type_1g_cu_core1:
1559 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1562 return IXGBE_SUCCESS;
1566 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1567 * @hw: pointer to hardware structure
1569 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1571 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1576 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1578 status = ixgbe_identify_module_generic(hw);
1580 if (status != IXGBE_SUCCESS)
1583 /* Check if SFP module is supported */
1584 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1590 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1591 * @hw: pointer to hardware structure
1593 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1598 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1600 /* Check if SFP module is supported */
1601 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1603 if (status != IXGBE_SUCCESS)
1606 ixgbe_init_mac_link_ops_X550em(hw);
1607 hw->phy.ops.reset = NULL;
1609 return IXGBE_SUCCESS;
1613 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1615 * @hw: pointer to hardware structure
1617 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1622 /* Restart auto-negotiation. */
1623 status = hw->mac.ops.read_iosf_sb_reg(hw,
1624 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1625 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1628 DEBUGOUT("Auto-negotiation did not complete\n");
1632 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1633 status = hw->mac.ops.write_iosf_sb_reg(hw,
1634 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1635 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1637 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1640 /* Indicate to FW that AN restart has been asserted */
1641 status = hw->mac.ops.read_iosf_sb_reg(hw,
1642 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1643 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1646 DEBUGOUT("Auto-negotiation did not complete\n");
1650 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1651 status = hw->mac.ops.write_iosf_sb_reg(hw,
1652 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1653 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1660 * ixgbe_setup_sgmii - Set up link for sgmii
1661 * @hw: pointer to hardware structure
1663 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1666 struct ixgbe_mac_info *mac = &hw->mac;
1667 u32 lval, sval, flx_val;
1670 rc = mac->ops.read_iosf_sb_reg(hw,
1671 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1672 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1676 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1677 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1678 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1679 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1680 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1681 rc = mac->ops.write_iosf_sb_reg(hw,
1682 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1683 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1687 rc = mac->ops.read_iosf_sb_reg(hw,
1688 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1689 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1693 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1694 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1695 rc = mac->ops.write_iosf_sb_reg(hw,
1696 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1697 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1701 rc = mac->ops.read_iosf_sb_reg(hw,
1702 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1703 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1707 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1708 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1709 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1710 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1711 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1713 rc = mac->ops.write_iosf_sb_reg(hw,
1714 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1715 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1719 rc = ixgbe_restart_an_internal_phy_x550em(hw);
1723 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1727 * ixgbe_setup_sgmii_m88 - Set up link for sgmii with Marvell PHYs
1728 * @hw: pointer to hardware structure
1730 STATIC s32 ixgbe_setup_sgmii_m88(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1733 struct ixgbe_mac_info *mac = &hw->mac;
1734 u32 lval, sval, flx_val;
1737 rc = mac->ops.read_iosf_sb_reg(hw,
1738 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1739 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1743 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1744 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1745 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1746 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1747 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1748 rc = mac->ops.write_iosf_sb_reg(hw,
1749 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1750 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1754 rc = mac->ops.read_iosf_sb_reg(hw,
1755 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1756 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1760 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1761 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1762 rc = mac->ops.write_iosf_sb_reg(hw,
1763 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1764 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1768 rc = mac->ops.write_iosf_sb_reg(hw,
1769 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1770 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1774 rc = mac->ops.read_iosf_sb_reg(hw,
1775 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1776 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1780 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1781 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1782 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1783 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1784 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1786 rc = mac->ops.write_iosf_sb_reg(hw,
1787 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1788 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1792 rc = ixgbe_restart_an_internal_phy_x550em(hw);
1794 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1798 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1799 * @hw: pointer to hardware structure
1801 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1803 struct ixgbe_mac_info *mac = &hw->mac;
1805 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1807 switch (hw->mac.ops.get_media_type(hw)) {
1808 case ixgbe_media_type_fiber:
1809 /* CS4227 does not support autoneg, so disable the laser control
1810 * functions for SFP+ fiber
1812 mac->ops.disable_tx_laser = NULL;
1813 mac->ops.enable_tx_laser = NULL;
1814 mac->ops.flap_tx_laser = NULL;
1815 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1816 mac->ops.set_rate_select_speed =
1817 ixgbe_set_soft_rate_select_speed;
1819 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1820 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1821 mac->ops.setup_mac_link =
1822 ixgbe_setup_mac_link_sfp_x550a;
1824 mac->ops.setup_mac_link =
1825 ixgbe_setup_mac_link_sfp_x550em;
1827 case ixgbe_media_type_copper:
1828 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1829 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1830 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1831 mac->ops.setup_link = ixgbe_setup_sgmii_m88;
1833 mac->ops.setup_link =
1834 ixgbe_setup_mac_link_t_X550em;
1837 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1838 mac->ops.check_link = ixgbe_check_link_t_X550em;
1841 case ixgbe_media_type_backplane:
1842 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1843 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1844 mac->ops.setup_link = ixgbe_setup_sgmii;
1852 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1853 * @hw: pointer to hardware structure
1854 * @speed: pointer to link speed
1855 * @autoneg: true when autoneg or autotry is enabled
1857 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1858 ixgbe_link_speed *speed,
1861 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1865 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1867 /* CS4227 SFP must not enable auto-negotiation */
1870 /* Check if 1G SFP module. */
1871 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1872 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1873 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1874 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1875 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1876 return IXGBE_SUCCESS;
1879 /* Link capabilities are based on SFP */
1880 if (hw->phy.multispeed_fiber)
1881 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1882 IXGBE_LINK_SPEED_1GB_FULL;
1884 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1886 switch (hw->phy.type) {
1888 *speed = IXGBE_LINK_SPEED_1GB_FULL |
1889 IXGBE_LINK_SPEED_100_FULL |
1890 IXGBE_LINK_SPEED_10_FULL;
1892 case ixgbe_phy_sgmii:
1893 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1895 case ixgbe_phy_x550em_kr:
1896 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1897 /* check different backplane modes */
1898 if (hw->phy.nw_mng_if_sel &
1899 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
1900 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
1902 } else if (hw->device_id ==
1903 IXGBE_DEV_ID_X550EM_A_KR_L) {
1904 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1910 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1911 IXGBE_LINK_SPEED_1GB_FULL;
1917 return IXGBE_SUCCESS;
1921 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1922 * @hw: pointer to hardware structure
1923 * @lsc: pointer to boolean flag which indicates whether external Base T
1924 * PHY interrupt is lsc
1926 * Determime if external Base T PHY interrupt cause is high temperature
1927 * failure alarm or link status change.
1929 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1930 * failure alarm, else return PHY access status.
1932 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1939 /* Vendor alarm triggered */
1940 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1941 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1944 if (status != IXGBE_SUCCESS ||
1945 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1948 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1949 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1950 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1953 if (status != IXGBE_SUCCESS ||
1954 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1955 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1958 /* Global alarm triggered */
1959 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1960 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1963 if (status != IXGBE_SUCCESS)
1966 /* If high temperature failure, then return over temp error and exit */
1967 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1968 /* power down the PHY in case the PHY FW didn't already */
1969 ixgbe_set_copper_phy_power(hw, false);
1970 return IXGBE_ERR_OVERTEMP;
1971 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1972 /* device fault alarm triggered */
1973 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1974 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1977 if (status != IXGBE_SUCCESS)
1980 /* if device fault was due to high temp alarm handle and exit */
1981 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1982 /* power down the PHY in case the PHY FW didn't */
1983 ixgbe_set_copper_phy_power(hw, false);
1984 return IXGBE_ERR_OVERTEMP;
1988 /* Vendor alarm 2 triggered */
1989 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1990 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1992 if (status != IXGBE_SUCCESS ||
1993 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1996 /* link connect/disconnect event occurred */
1997 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1998 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
2000 if (status != IXGBE_SUCCESS)
2004 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2007 return IXGBE_SUCCESS;
2011 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2012 * @hw: pointer to hardware structure
2014 * Enable link status change and temperature failure alarm for the external
2017 * Returns PHY access status
2019 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2025 /* Clear interrupt flags */
2026 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2028 /* Enable link status change alarm */
2030 /* Enable the LASI interrupts on X552 devices to receive notifications
2031 * of the link configurations of the external PHY and correspondingly
2032 * support the configuration of the internal iXFI link, since iXFI does
2033 * not support auto-negotiation. This is not required for X553 devices
2034 * having KR support, which performs auto-negotiations and which is used
2035 * as the internal link to the external PHY. Hence adding a check here
2036 * to avoid enabling LASI interrupts for X553 devices.
2038 if (hw->mac.type != ixgbe_mac_X550EM_a) {
2039 status = hw->phy.ops.read_reg(hw,
2040 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2041 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
2043 if (status != IXGBE_SUCCESS)
2046 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2048 status = hw->phy.ops.write_reg(hw,
2049 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2050 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2052 if (status != IXGBE_SUCCESS)
2056 /* Enable high temperature failure and global fault alarms */
2057 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2058 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2061 if (status != IXGBE_SUCCESS)
2064 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2065 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2067 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2068 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2071 if (status != IXGBE_SUCCESS)
2074 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2075 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2076 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2079 if (status != IXGBE_SUCCESS)
2082 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2083 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2085 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2086 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2089 if (status != IXGBE_SUCCESS)
2092 /* Enable chip-wide vendor alarm */
2093 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2094 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2097 if (status != IXGBE_SUCCESS)
2100 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2102 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2103 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2110 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2111 * @hw: pointer to hardware structure
2112 * @speed: link speed
2114 * Configures the integrated KR PHY.
2116 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2117 ixgbe_link_speed speed)
2122 status = hw->mac.ops.read_iosf_sb_reg(hw,
2123 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2124 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2128 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2129 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2130 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2132 /* Advertise 10G support. */
2133 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2134 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2136 /* Advertise 1G support. */
2137 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2138 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2140 status = hw->mac.ops.write_iosf_sb_reg(hw,
2141 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2142 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2144 if (hw->mac.type == ixgbe_mac_X550EM_a) {
2145 /* Set lane mode to KR auto negotiation */
2146 status = hw->mac.ops.read_iosf_sb_reg(hw,
2147 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2148 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2153 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2154 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2155 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2156 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2157 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2159 status = hw->mac.ops.write_iosf_sb_reg(hw,
2160 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2161 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2164 return ixgbe_restart_an_internal_phy_x550em(hw);
2168 * ixgbe_setup_m88 - setup m88 PHY
2169 * @hw: pointer to hardware structure
2171 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2173 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2177 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2178 return IXGBE_SUCCESS;
2180 rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2184 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2187 if (reg & IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN) {
2188 reg &= ~IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN;
2189 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2193 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, ®);
2196 if (reg & IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN) {
2197 reg &= ~IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN;
2198 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0,
2202 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 2);
2206 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2210 if (reg & IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN) {
2211 reg &= ~IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN;
2212 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2214 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2218 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2222 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2223 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2227 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2233 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2237 if (!(reg & IXGBE_M88E1500_COPPER_CTRL_AN_EN)) {
2238 reg |= IXGBE_M88E1500_COPPER_CTRL_AN_EN;
2239 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2243 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, ®);
2246 reg &= ~IXGBE_M88E1500_1000T_CTRL_HALF_DUPLEX;
2247 reg &= ~IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2248 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
2249 reg |= IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2250 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, reg);
2252 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, ®);
2255 reg &= ~IXGBE_M88E1500_COPPER_AN_T4;
2256 reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_FD;
2257 reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_HD;
2258 reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_FD;
2259 reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_HD;
2261 /* Flow control auto negotiation configuration was moved from here to
2262 * the function ixgbe_setup_fc_sgmii_x550em_a()
2265 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
2266 reg |= IXGBE_M88E1500_COPPER_AN_100TX_FD;
2267 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
2268 reg |= IXGBE_M88E1500_COPPER_AN_10TX_FD;
2269 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, reg);
2271 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2274 reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
2275 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2278 hw->mac.ops.release_swfw_sync(hw, mask);
2282 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2283 hw->mac.ops.release_swfw_sync(hw, mask);
2288 * ixgbe_reset_phy_m88e1500 - Reset m88e1500 PHY
2289 * @hw: pointer to hardware structure
2291 * The PHY token must be held when calling this function.
2293 static s32 ixgbe_reset_phy_m88e1500(struct ixgbe_hw *hw)
2298 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2302 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2306 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2307 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2315 * ixgbe_reset_phy_m88e1543 - Reset m88e1543 PHY
2316 * @hw: pointer to hardware structure
2318 * The PHY token must be held when calling this function.
2320 static s32 ixgbe_reset_phy_m88e1543(struct ixgbe_hw *hw)
2322 return hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2326 * ixgbe_reset_phy_m88 - Reset m88 PHY
2327 * @hw: pointer to hardware structure
2329 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2331 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2335 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2336 return IXGBE_SUCCESS;
2338 rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2342 switch (hw->phy.id) {
2343 case IXGBE_M88E1500_E_PHY_ID:
2344 rc = ixgbe_reset_phy_m88e1500(hw);
2346 case IXGBE_M88E1543_E_PHY_ID:
2347 rc = ixgbe_reset_phy_m88e1543(hw);
2354 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2358 reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2359 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2360 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2361 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2365 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2369 reg = IXGBE_M88E1500_GEN_CTRL_RESET |
2370 IXGBE_M88E1500_GEN_CTRL_MODE_SGMII_COPPER;
2371 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_GEN_CTRL, 0, reg);
2375 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2379 reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2380 IXGBE_M88E1500_FIBER_CTRL_AN_EN |
2381 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2382 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2383 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2387 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2391 reg = (IXGBE_M88E1500_MAC_CTRL_1_DWN_4X <<
2392 IXGBE_M88E1500_MAC_CTRL_1_DWN_SHIFT) |
2393 (IXGBE_M88E1500_MAC_CTRL_1_ED_TM <<
2394 IXGBE_M88E1500_MAC_CTRL_1_ED_SHIFT) |
2395 (IXGBE_M88E1500_MAC_CTRL_1_MDIX_AUTO <<
2396 IXGBE_M88E1500_MAC_CTRL_1_MDIX_SHIFT);
2397 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, reg);
2401 reg = IXGBE_M88E1500_COPPER_CTRL_RESET |
2402 IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2403 IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2404 IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2405 IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB;
2406 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2410 hw->mac.ops.release_swfw_sync(hw, mask);
2412 /* In case of first reset set advertised speeds to default value */
2413 if (!hw->phy.autoneg_advertised)
2414 hw->phy.autoneg_advertised = IXGBE_LINK_SPEED_1GB_FULL |
2415 IXGBE_LINK_SPEED_100_FULL |
2416 IXGBE_LINK_SPEED_10_FULL;
2418 return ixgbe_setup_m88(hw);
2421 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2422 hw->mac.ops.release_swfw_sync(hw, mask);
2427 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2428 * @hw: pointer to hardware structure
2430 * Read NW_MNG_IF_SEL register and save field values, and check for valid field
2433 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2435 /* Save NW management interface connected on board. This is used
2436 * to determine internal PHY mode.
2438 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2440 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2441 * PHY address. This register field was has only been used for X552.
2443 if (hw->mac.type == ixgbe_mac_X550EM_a &&
2444 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2445 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2446 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2447 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2450 return IXGBE_SUCCESS;
2454 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2455 * @hw: pointer to hardware structure
2457 * Initialize any function pointers that were not able to be
2458 * set during init_shared_code because the PHY/SFP type was
2459 * not known. Perform the SFP init if necessary.
2461 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2463 struct ixgbe_phy_info *phy = &hw->phy;
2466 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2468 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2469 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2470 ixgbe_setup_mux_ctl(hw);
2471 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2474 switch (hw->device_id) {
2475 case IXGBE_DEV_ID_X550EM_A_1G_T:
2476 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2477 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2478 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2479 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2480 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2482 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2484 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2487 case IXGBE_DEV_ID_X550EM_A_10G_T:
2488 case IXGBE_DEV_ID_X550EM_A_SFP:
2489 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2490 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2492 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2494 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2496 case IXGBE_DEV_ID_X550EM_X_SFP:
2497 /* set up for CS4227 usage */
2498 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2504 /* Identify the PHY or SFP module */
2505 ret_val = phy->ops.identify(hw);
2506 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2509 /* Setup function pointers based on detected hardware */
2510 ixgbe_init_mac_link_ops_X550em(hw);
2511 if (phy->sfp_type != ixgbe_sfp_type_unknown)
2512 phy->ops.reset = NULL;
2514 /* Set functions pointers based on phy type */
2515 switch (hw->phy.type) {
2516 case ixgbe_phy_x550em_kx4:
2517 phy->ops.setup_link = NULL;
2518 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2519 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2521 case ixgbe_phy_x550em_kr:
2522 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2523 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2524 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2526 case ixgbe_phy_x550em_ext_t:
2527 /* If internal link mode is XFI, then setup iXFI internal link,
2528 * else setup KR now.
2530 phy->ops.setup_internal_link =
2531 ixgbe_setup_internal_phy_t_x550em;
2533 /* setup SW LPLU only for first revision of X550EM_x */
2534 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2535 !(IXGBE_FUSES0_REV_MASK &
2536 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2537 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2539 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2540 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2542 case ixgbe_phy_sgmii:
2543 phy->ops.setup_link = NULL;
2546 phy->ops.setup_link = ixgbe_setup_m88;
2547 phy->ops.reset = ixgbe_reset_phy_m88;
2556 * ixgbe_set_mdio_speed - Set MDIO clock speed
2557 * @hw: pointer to hardware structure
2559 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2563 switch (hw->device_id) {
2564 case IXGBE_DEV_ID_X550EM_X_10G_T:
2565 case IXGBE_DEV_ID_X550EM_A_SGMII:
2566 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2567 case IXGBE_DEV_ID_X550EM_A_10G_T:
2568 case IXGBE_DEV_ID_X550EM_A_SFP:
2569 case IXGBE_DEV_ID_X550EM_A_QSFP:
2570 /* Config MDIO clock speed before the first MDIO PHY access */
2571 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2572 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2573 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2575 case IXGBE_DEV_ID_X550EM_A_1G_T:
2576 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2577 /* Select fast MDIO clock speed for these devices */
2578 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2579 hlreg0 |= IXGBE_HLREG0_MDCSPD;
2580 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2588 * ixgbe_reset_hw_X550em - Perform hardware reset
2589 * @hw: pointer to hardware structure
2591 * Resets the hardware by resetting the transmit and receive units, masks
2592 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2595 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2597 ixgbe_link_speed link_speed;
2601 bool link_up = false;
2603 DEBUGFUNC("ixgbe_reset_hw_X550em");
2605 /* Call adapter stop to disable Tx/Rx and clear interrupts */
2606 status = hw->mac.ops.stop_adapter(hw);
2607 if (status != IXGBE_SUCCESS)
2610 /* flush pending Tx transactions */
2611 ixgbe_clear_tx_pending(hw);
2613 ixgbe_set_mdio_speed(hw);
2615 /* PHY ops must be identified and initialized prior to reset */
2616 status = hw->phy.ops.init(hw);
2618 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2621 /* start the external PHY */
2622 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2623 status = ixgbe_init_ext_t_x550em(hw);
2628 /* Setup SFP module if there is one present. */
2629 if (hw->phy.sfp_setup_needed) {
2630 status = hw->mac.ops.setup_sfp(hw);
2631 hw->phy.sfp_setup_needed = false;
2634 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2638 if (!hw->phy.reset_disable && hw->phy.ops.reset)
2639 hw->phy.ops.reset(hw);
2642 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
2643 * If link reset is used when link is up, it might reset the PHY when
2644 * mng is using it. If link is down or the flag to force full link
2645 * reset is set, then perform link reset.
2647 ctrl = IXGBE_CTRL_LNK_RST;
2648 if (!hw->force_full_reset) {
2649 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2651 ctrl = IXGBE_CTRL_RST;
2654 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2655 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2656 IXGBE_WRITE_FLUSH(hw);
2658 /* Poll for reset bit to self-clear meaning reset is complete */
2659 for (i = 0; i < 10; i++) {
2661 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2662 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2666 if (ctrl & IXGBE_CTRL_RST_MASK) {
2667 status = IXGBE_ERR_RESET_FAILED;
2668 DEBUGOUT("Reset polling failed to complete.\n");
2673 /* Double resets are required for recovery from certain error
2674 * conditions. Between resets, it is necessary to stall to
2675 * allow time for any pending HW events to complete.
2677 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2678 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2682 /* Store the permanent mac address */
2683 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2685 /* Store MAC address from RAR0, clear receive address registers, and
2686 * clear the multicast table. Also reset num_rar_entries to 128,
2687 * since we modify this value when programming the SAN MAC address.
2689 hw->mac.num_rar_entries = 128;
2690 hw->mac.ops.init_rx_addrs(hw);
2692 ixgbe_set_mdio_speed(hw);
2694 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2695 ixgbe_setup_mux_ctl(hw);
2701 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2702 * @hw: pointer to hardware structure
2704 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2709 status = hw->phy.ops.read_reg(hw,
2710 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2711 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2714 if (status != IXGBE_SUCCESS)
2717 /* If PHY FW reset completed bit is set then this is the first
2718 * SW instance after a power on so the PHY FW must be un-stalled.
2720 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2721 status = hw->phy.ops.read_reg(hw,
2722 IXGBE_MDIO_GLOBAL_RES_PR_10,
2723 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2726 if (status != IXGBE_SUCCESS)
2729 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2731 status = hw->phy.ops.write_reg(hw,
2732 IXGBE_MDIO_GLOBAL_RES_PR_10,
2733 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2736 if (status != IXGBE_SUCCESS)
2744 * ixgbe_setup_kr_x550em - Configure the KR PHY.
2745 * @hw: pointer to hardware structure
2747 * Configures the integrated KR PHY for X550EM_x.
2749 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2751 if (hw->mac.type != ixgbe_mac_X550EM_x)
2752 return IXGBE_SUCCESS;
2754 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2758 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2759 * @hw: pointer to hardware structure
2761 * Configure the external PHY and the integrated KR PHY for SFP support.
2763 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2764 ixgbe_link_speed speed,
2765 bool autoneg_wait_to_complete)
2768 u16 reg_slice, reg_val;
2769 bool setup_linear = false;
2770 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2772 /* Check if SFP module is supported and linear */
2773 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2775 /* If no SFP module present, then return success. Return success since
2776 * there is no reason to configure CS4227 and SFP not present error is
2777 * not excepted in the setup MAC link flow.
2779 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2780 return IXGBE_SUCCESS;
2782 if (ret_val != IXGBE_SUCCESS)
2785 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2786 /* Configure CS4227 LINE side to 10G SR. */
2787 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2788 (hw->bus.lan_id << 12);
2789 reg_val = IXGBE_CS4227_SPEED_10G;
2790 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2793 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2794 (hw->bus.lan_id << 12);
2795 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2796 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2799 /* Configure CS4227 for HOST connection rate then type. */
2800 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2801 (hw->bus.lan_id << 12);
2802 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2803 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2804 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2807 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2808 (hw->bus.lan_id << 12);
2810 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2812 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2813 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2816 /* Setup XFI internal link. */
2817 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2819 /* Configure internal PHY for KR/KX. */
2820 ixgbe_setup_kr_speed_x550em(hw, speed);
2822 /* Configure CS4227 LINE side to proper mode. */
2823 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2824 (hw->bus.lan_id << 12);
2826 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2828 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2829 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2836 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2837 * @hw: pointer to hardware structure
2838 * @speed: the link speed to force
2840 * Configures the integrated PHY for native SFI mode. Used to connect the
2841 * internal PHY directly to an SFP cage, without autonegotiation.
2843 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2845 struct ixgbe_mac_info *mac = &hw->mac;
2849 /* Disable all AN and force speed to 10G Serial. */
2850 status = mac->ops.read_iosf_sb_reg(hw,
2851 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2852 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2853 if (status != IXGBE_SUCCESS)
2856 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2857 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2858 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2859 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2861 /* Select forced link speed for internal PHY. */
2863 case IXGBE_LINK_SPEED_10GB_FULL:
2864 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2866 case IXGBE_LINK_SPEED_1GB_FULL:
2867 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2870 /* Other link speeds are not supported by internal PHY. */
2871 return IXGBE_ERR_LINK_SETUP;
2874 status = mac->ops.write_iosf_sb_reg(hw,
2875 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2876 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2878 /* Toggle port SW reset by AN reset. */
2879 status = ixgbe_restart_an_internal_phy_x550em(hw);
2885 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2886 * @hw: pointer to hardware structure
2888 * Configure the the integrated PHY for SFP support.
2890 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2891 ixgbe_link_speed speed,
2892 bool autoneg_wait_to_complete)
2896 bool setup_linear = false;
2897 u32 reg_slice, reg_phy_int, slice_offset;
2899 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2901 /* Check if SFP module is supported and linear */
2902 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2904 /* If no SFP module present, then return success. Return success since
2905 * SFP not present error is not excepted in the setup MAC link flow.
2907 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2908 return IXGBE_SUCCESS;
2910 if (ret_val != IXGBE_SUCCESS)
2913 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2914 /* Configure internal PHY for native SFI based on module type */
2915 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2916 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2917 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
2919 if (ret_val != IXGBE_SUCCESS)
2922 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2924 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2926 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2927 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2928 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2930 if (ret_val != IXGBE_SUCCESS)
2933 /* Setup SFI internal link. */
2934 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2936 /* Configure internal PHY for KR/KX. */
2937 ixgbe_setup_kr_speed_x550em(hw, speed);
2939 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2941 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2942 return IXGBE_ERR_PHY_ADDR_INVALID;
2945 /* Get external PHY SKU id */
2946 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
2947 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2949 if (ret_val != IXGBE_SUCCESS)
2952 /* When configuring quad port CS4223, the MAC instance is part
2953 * of the slice offset.
2955 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
2956 slice_offset = (hw->bus.lan_id +
2957 (hw->bus.instance_id << 1)) << 12;
2959 slice_offset = hw->bus.lan_id << 12;
2961 /* Configure CS4227/CS4223 LINE side to proper mode. */
2962 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2964 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2966 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2967 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2968 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2974 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2975 * @hw: pointer to hardware structure
2977 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2979 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2981 struct ixgbe_mac_info *mac = &hw->mac;
2985 /* Disable training protocol FSM. */
2986 status = mac->ops.read_iosf_sb_reg(hw,
2987 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2988 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2989 if (status != IXGBE_SUCCESS)
2991 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2992 status = mac->ops.write_iosf_sb_reg(hw,
2993 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2994 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2995 if (status != IXGBE_SUCCESS)
2998 /* Disable Flex from training TXFFE. */
2999 status = mac->ops.read_iosf_sb_reg(hw,
3000 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
3001 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3002 if (status != IXGBE_SUCCESS)
3004 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
3005 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
3006 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
3007 status = mac->ops.write_iosf_sb_reg(hw,
3008 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
3009 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3010 if (status != IXGBE_SUCCESS)
3012 status = mac->ops.read_iosf_sb_reg(hw,
3013 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
3014 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3015 if (status != IXGBE_SUCCESS)
3017 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
3018 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
3019 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
3020 status = mac->ops.write_iosf_sb_reg(hw,
3021 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
3022 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3023 if (status != IXGBE_SUCCESS)
3026 /* Enable override for coefficients. */
3027 status = mac->ops.read_iosf_sb_reg(hw,
3028 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
3029 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3030 if (status != IXGBE_SUCCESS)
3032 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
3033 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
3034 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
3035 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
3036 status = mac->ops.write_iosf_sb_reg(hw,
3037 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
3038 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3043 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
3044 * @hw: pointer to hardware structure
3045 * @speed: the link speed to force
3047 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
3048 * internal and external PHY at a specific speed, without autonegotiation.
3050 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
3052 struct ixgbe_mac_info *mac = &hw->mac;
3056 /* iXFI is only supported with X552 */
3057 if (mac->type != ixgbe_mac_X550EM_x)
3058 return IXGBE_ERR_LINK_SETUP;
3060 /* Disable AN and force speed to 10G Serial. */
3061 status = mac->ops.read_iosf_sb_reg(hw,
3062 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3063 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3064 if (status != IXGBE_SUCCESS)
3067 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3068 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3070 /* Select forced link speed for internal PHY. */
3072 case IXGBE_LINK_SPEED_10GB_FULL:
3073 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3075 case IXGBE_LINK_SPEED_1GB_FULL:
3076 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
3079 /* Other link speeds are not supported by internal KR PHY. */
3080 return IXGBE_ERR_LINK_SETUP;
3083 status = mac->ops.write_iosf_sb_reg(hw,
3084 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3085 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3086 if (status != IXGBE_SUCCESS)
3089 /* Additional configuration needed for x550em_x */
3090 if (hw->mac.type == ixgbe_mac_X550EM_x) {
3091 status = ixgbe_setup_ixfi_x550em_x(hw);
3092 if (status != IXGBE_SUCCESS)
3096 /* Toggle port SW reset by AN reset. */
3097 status = ixgbe_restart_an_internal_phy_x550em(hw);
3103 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
3104 * @hw: address of hardware structure
3105 * @link_up: address of boolean to indicate link status
3107 * Returns error code if unable to get link status.
3109 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
3116 /* read this twice back to back to indicate current status */
3117 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3118 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3120 if (ret != IXGBE_SUCCESS)
3123 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3124 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3126 if (ret != IXGBE_SUCCESS)
3129 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
3131 return IXGBE_SUCCESS;
3135 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
3136 * @hw: point to hardware structure
3138 * Configures the link between the integrated KR PHY and the external X557 PHY
3139 * The driver will call this function when it gets a link status change
3140 * interrupt from the X557 PHY. This function configures the link speed
3141 * between the PHYs to match the link speed of the BASE-T link.
3143 * A return of a non-zero value indicates an error, and the base driver should
3144 * not report link up.
3146 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
3148 ixgbe_link_speed force_speed;
3153 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3154 return IXGBE_ERR_CONFIG;
3156 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3157 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3158 /* If link is down, there is no setup necessary so return */
3159 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3160 if (status != IXGBE_SUCCESS)
3164 return IXGBE_SUCCESS;
3166 status = hw->phy.ops.read_reg(hw,
3167 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3168 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3170 if (status != IXGBE_SUCCESS)
3173 /* If link is still down - no setup is required so return */
3174 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3175 if (status != IXGBE_SUCCESS)
3178 return IXGBE_SUCCESS;
3180 /* clear everything but the speed and duplex bits */
3181 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3184 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3185 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3187 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3188 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3191 /* Internal PHY does not support anything else */
3192 return IXGBE_ERR_INVALID_LINK_SETTINGS;
3195 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3197 speed = IXGBE_LINK_SPEED_10GB_FULL |
3198 IXGBE_LINK_SPEED_1GB_FULL;
3199 return ixgbe_setup_kr_speed_x550em(hw, speed);
3204 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3205 * @hw: pointer to hardware structure
3207 * Configures the integrated KR PHY to use internal loopback mode.
3209 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3214 /* Disable AN and force speed to 10G Serial. */
3215 status = hw->mac.ops.read_iosf_sb_reg(hw,
3216 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3217 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3218 if (status != IXGBE_SUCCESS)
3220 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3221 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3222 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3223 status = hw->mac.ops.write_iosf_sb_reg(hw,
3224 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3225 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3226 if (status != IXGBE_SUCCESS)
3229 /* Set near-end loopback clocks. */
3230 status = hw->mac.ops.read_iosf_sb_reg(hw,
3231 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3232 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3233 if (status != IXGBE_SUCCESS)
3235 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3236 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3237 status = hw->mac.ops.write_iosf_sb_reg(hw,
3238 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3239 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3240 if (status != IXGBE_SUCCESS)
3243 /* Set loopback enable. */
3244 status = hw->mac.ops.read_iosf_sb_reg(hw,
3245 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3246 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3247 if (status != IXGBE_SUCCESS)
3249 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3250 status = hw->mac.ops.write_iosf_sb_reg(hw,
3251 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3252 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3253 if (status != IXGBE_SUCCESS)
3256 /* Training bypass. */
3257 status = hw->mac.ops.read_iosf_sb_reg(hw,
3258 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3259 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3260 if (status != IXGBE_SUCCESS)
3262 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3263 status = hw->mac.ops.write_iosf_sb_reg(hw,
3264 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3265 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3271 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3272 * assuming that the semaphore is already obtained.
3273 * @hw: pointer to hardware structure
3274 * @offset: offset of word in the EEPROM to read
3275 * @data: word read from the EEPROM
3277 * Reads a 16 bit word from the EEPROM using the hostif.
3279 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3281 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3282 struct ixgbe_hic_read_shadow_ram buffer;
3285 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3286 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3287 buffer.hdr.req.buf_lenh = 0;
3288 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3289 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3291 /* convert offset from words to bytes */
3292 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3294 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3296 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3300 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3301 IXGBE_HI_COMMAND_TIMEOUT);
3303 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3304 FW_NVM_DATA_OFFSET);
3307 hw->mac.ops.release_swfw_sync(hw, mask);
3312 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3313 * @hw: pointer to hardware structure
3314 * @offset: offset of word in the EEPROM to read
3315 * @words: number of words
3316 * @data: word(s) read from the EEPROM
3318 * Reads a 16 bit word(s) from the EEPROM using the hostif.
3320 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3321 u16 offset, u16 words, u16 *data)
3323 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3324 struct ixgbe_hic_read_shadow_ram buffer;
3325 u32 current_word = 0;
3330 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3332 /* Take semaphore for the entire operation. */
3333 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3335 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3340 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3341 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3343 words_to_read = words;
3345 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3346 buffer.hdr.req.buf_lenh = 0;
3347 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3348 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3350 /* convert offset from words to bytes */
3351 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3352 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3354 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3355 IXGBE_HI_COMMAND_TIMEOUT);
3358 DEBUGOUT("Host interface command failed\n");
3362 for (i = 0; i < words_to_read; i++) {
3363 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3365 u32 value = IXGBE_READ_REG(hw, reg);
3367 data[current_word] = (u16)(value & 0xffff);
3370 if (i < words_to_read) {
3372 data[current_word] = (u16)(value & 0xffff);
3376 words -= words_to_read;
3380 hw->mac.ops.release_swfw_sync(hw, mask);
3385 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3386 * @hw: pointer to hardware structure
3387 * @offset: offset of word in the EEPROM to write
3388 * @data: word write to the EEPROM
3390 * Write a 16 bit word to the EEPROM using the hostif.
3392 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3396 struct ixgbe_hic_write_shadow_ram buffer;
3398 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3400 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3401 buffer.hdr.req.buf_lenh = 0;
3402 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3403 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3406 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3408 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3410 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3412 IXGBE_HI_COMMAND_TIMEOUT, false);
3418 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3419 * @hw: pointer to hardware structure
3420 * @offset: offset of word in the EEPROM to write
3421 * @data: word write to the EEPROM
3423 * Write a 16 bit word to the EEPROM using the hostif.
3425 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3428 s32 status = IXGBE_SUCCESS;
3430 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3432 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3434 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3435 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3437 DEBUGOUT("write ee hostif failed to get semaphore");
3438 status = IXGBE_ERR_SWFW_SYNC;
3445 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3446 * @hw: pointer to hardware structure
3447 * @offset: offset of word in the EEPROM to write
3448 * @words: number of words
3449 * @data: word(s) write to the EEPROM
3451 * Write a 16 bit word(s) to the EEPROM using the hostif.
3453 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3454 u16 offset, u16 words, u16 *data)
3456 s32 status = IXGBE_SUCCESS;
3459 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3461 /* Take semaphore for the entire operation. */
3462 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3463 if (status != IXGBE_SUCCESS) {
3464 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3468 for (i = 0; i < words; i++) {
3469 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3472 if (status != IXGBE_SUCCESS) {
3473 DEBUGOUT("Eeprom buffered write failed\n");
3478 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3485 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3486 * @hw: pointer to hardware structure
3487 * @ptr: pointer offset in eeprom
3488 * @size: size of section pointed by ptr, if 0 first word will be used as size
3489 * @csum: address of checksum to update
3491 * Returns error status for any failure
3493 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3494 u16 size, u16 *csum, u16 *buffer,
3499 u16 length, bufsz, i, start;
3502 bufsz = sizeof(buf) / sizeof(buf[0]);
3504 /* Read a chunk at the pointer location */
3506 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3508 DEBUGOUT("Failed to read EEPROM image\n");
3513 if (buffer_size < ptr)
3514 return IXGBE_ERR_PARAM;
3515 local_buffer = &buffer[ptr];
3523 length = local_buffer[0];
3525 /* Skip pointer section if length is invalid. */
3526 if (length == 0xFFFF || length == 0 ||
3527 (ptr + length) >= hw->eeprom.word_size)
3528 return IXGBE_SUCCESS;
3531 if (buffer && ((u32)start + (u32)length > buffer_size))
3532 return IXGBE_ERR_PARAM;
3534 for (i = start; length; i++, length--) {
3535 if (i == bufsz && !buffer) {
3541 /* Read a chunk at the pointer location */
3542 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3545 DEBUGOUT("Failed to read EEPROM image\n");
3549 *csum += local_buffer[i];
3551 return IXGBE_SUCCESS;
3555 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3556 * @hw: pointer to hardware structure
3557 * @buffer: pointer to buffer containing calculated checksum
3558 * @buffer_size: size of buffer
3560 * Returns a negative error code on error, or the 16-bit checksum
3562 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3564 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3568 u16 pointer, i, size;
3570 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3572 hw->eeprom.ops.init_params(hw);
3575 /* Read pointer area */
3576 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3577 IXGBE_EEPROM_LAST_WORD + 1,
3580 DEBUGOUT("Failed to read EEPROM image\n");
3583 local_buffer = eeprom_ptrs;
3585 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3586 return IXGBE_ERR_PARAM;
3587 local_buffer = buffer;
3591 * For X550 hardware include 0x0-0x41 in the checksum, skip the
3592 * checksum word itself
3594 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3595 if (i != IXGBE_EEPROM_CHECKSUM)
3596 checksum += local_buffer[i];
3599 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
3600 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3602 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3603 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3606 pointer = local_buffer[i];
3608 /* Skip pointer section if the pointer is invalid. */
3609 if (pointer == 0xFFFF || pointer == 0 ||
3610 pointer >= hw->eeprom.word_size)
3614 case IXGBE_PCIE_GENERAL_PTR:
3615 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3617 case IXGBE_PCIE_CONFIG0_PTR:
3618 case IXGBE_PCIE_CONFIG1_PTR:
3619 size = IXGBE_PCIE_CONFIG_SIZE;
3626 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3627 buffer, buffer_size);
3632 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3634 return (s32)checksum;
3638 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3639 * @hw: pointer to hardware structure
3641 * Returns a negative error code on error, or the 16-bit checksum
3643 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3645 return ixgbe_calc_checksum_X550(hw, NULL, 0);
3649 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3650 * @hw: pointer to hardware structure
3651 * @checksum_val: calculated checksum
3653 * Performs checksum calculation and validates the EEPROM checksum. If the
3654 * caller does not need checksum_val, the value can be NULL.
3656 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3660 u16 read_checksum = 0;
3662 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3664 /* Read the first word from the EEPROM. If this times out or fails, do
3665 * not continue or we could be in for a very long wait while every
3668 status = hw->eeprom.ops.read(hw, 0, &checksum);
3670 DEBUGOUT("EEPROM read failed\n");
3674 status = hw->eeprom.ops.calc_checksum(hw);
3678 checksum = (u16)(status & 0xffff);
3680 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3685 /* Verify read checksum from EEPROM is the same as
3686 * calculated checksum
3688 if (read_checksum != checksum) {
3689 status = IXGBE_ERR_EEPROM_CHECKSUM;
3690 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3691 "Invalid EEPROM checksum");
3694 /* If the user cares, return the calculated checksum */
3696 *checksum_val = checksum;
3702 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3703 * @hw: pointer to hardware structure
3705 * After writing EEPROM to shadow RAM using EEWR register, software calculates
3706 * checksum and updates the EEPROM and instructs the hardware to update
3709 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3714 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3716 /* Read the first word from the EEPROM. If this times out or fails, do
3717 * not continue or we could be in for a very long wait while every
3720 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3722 DEBUGOUT("EEPROM read failed\n");
3726 status = ixgbe_calc_eeprom_checksum_X550(hw);
3730 checksum = (u16)(status & 0xffff);
3732 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3737 status = ixgbe_update_flash_X550(hw);
3743 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3744 * @hw: pointer to hardware structure
3746 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3748 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3750 s32 status = IXGBE_SUCCESS;
3751 union ixgbe_hic_hdr2 buffer;
3753 DEBUGFUNC("ixgbe_update_flash_X550");
3755 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3756 buffer.req.buf_lenh = 0;
3757 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3758 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3760 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3762 IXGBE_HI_COMMAND_TIMEOUT, false);
3768 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3769 * @hw: pointer to hardware structure
3771 * Determines physical layer capabilities of the current configuration.
3773 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3775 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3776 u16 ext_ability = 0;
3778 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3780 hw->phy.ops.identify(hw);
3782 switch (hw->phy.type) {
3783 case ixgbe_phy_x550em_kr:
3784 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3785 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3787 case ixgbe_phy_x550em_kx4:
3788 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3789 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3791 case ixgbe_phy_x550em_ext_t:
3792 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3793 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3795 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3796 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3797 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3798 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3804 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3805 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3807 return physical_layer;
3811 * ixgbe_get_bus_info_x550em - Set PCI bus info
3812 * @hw: pointer to hardware structure
3814 * Sets bus link width and speed to unknown because X550em is
3817 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3820 DEBUGFUNC("ixgbe_get_bus_info_x550em");
3822 hw->bus.width = ixgbe_bus_width_unknown;
3823 hw->bus.speed = ixgbe_bus_speed_unknown;
3825 hw->mac.ops.set_lan_id(hw);
3827 return IXGBE_SUCCESS;
3831 * ixgbe_disable_rx_x550 - Disable RX unit
3833 * Enables the Rx DMA unit for x550
3835 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3837 u32 rxctrl, pfdtxgswc;
3839 struct ixgbe_hic_disable_rxen fw_cmd;
3841 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3843 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3844 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3845 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3846 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3847 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3848 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3849 hw->mac.set_lben = true;
3851 hw->mac.set_lben = false;
3854 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3855 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3856 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3857 fw_cmd.port_number = (u8)hw->bus.lan_id;
3859 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3860 sizeof(struct ixgbe_hic_disable_rxen),
3861 IXGBE_HI_COMMAND_TIMEOUT, true);
3863 /* If we fail - disable RX using register write */
3865 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3866 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3867 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3868 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3875 * ixgbe_enter_lplu_x550em - Transition to low power states
3876 * @hw: pointer to hardware structure
3878 * Configures Low Power Link Up on transition to low power states
3879 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3880 * X557 PHY immediately prior to entering LPLU.
3882 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3884 u16 an_10g_cntl_reg, autoneg_reg, speed;
3886 ixgbe_link_speed lcd_speed;
3890 /* SW LPLU not required on later HW revisions. */
3891 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3892 (IXGBE_FUSES0_REV_MASK &
3893 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3894 return IXGBE_SUCCESS;
3896 /* If blocked by MNG FW, then don't restart AN */
3897 if (ixgbe_check_reset_blocked(hw))
3898 return IXGBE_SUCCESS;
3900 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3901 if (status != IXGBE_SUCCESS)
3904 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3906 if (status != IXGBE_SUCCESS)
3909 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3910 * disabled, then force link down by entering low power mode.
3912 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3913 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3914 return ixgbe_set_copper_phy_power(hw, FALSE);
3917 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3919 if (status != IXGBE_SUCCESS)
3922 /* If no valid LCD link speed, then force link down and exit. */
3923 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3924 return ixgbe_set_copper_phy_power(hw, FALSE);
3926 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3927 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3930 if (status != IXGBE_SUCCESS)
3933 /* If no link now, speed is invalid so take link down */
3934 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3935 if (status != IXGBE_SUCCESS)
3936 return ixgbe_set_copper_phy_power(hw, false);
3938 /* clear everything but the speed bits */
3939 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3941 /* If current speed is already LCD, then exit. */
3942 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3943 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3944 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3945 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3948 /* Clear AN completed indication */
3949 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3950 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3953 if (status != IXGBE_SUCCESS)
3956 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3957 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3960 if (status != IXGBE_SUCCESS)
3963 status = hw->phy.ops.read_reg(hw,
3964 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3965 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3968 if (status != IXGBE_SUCCESS)
3971 save_autoneg = hw->phy.autoneg_advertised;
3973 /* Setup link at least common link speed */
3974 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3976 /* restore autoneg from before setting lplu speed */
3977 hw->phy.autoneg_advertised = save_autoneg;
3983 * ixgbe_get_lcd_x550em - Determine lowest common denominator
3984 * @hw: pointer to hardware structure
3985 * @lcd_speed: pointer to lowest common link speed
3987 * Determine lowest common link speed with link partner.
3989 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3993 u16 word = hw->eeprom.ctrl_word_3;
3995 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3997 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3998 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4001 if (status != IXGBE_SUCCESS)
4004 /* If link partner advertised 1G, return 1G */
4005 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
4006 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
4010 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
4011 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
4012 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
4015 /* Link partner not capable of lower speeds, return 10G */
4016 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
4021 * ixgbe_setup_fc_X550em - Set up flow control
4022 * @hw: pointer to hardware structure
4024 * Called at init time to set up flow control.
4026 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
4028 s32 ret_val = IXGBE_SUCCESS;
4029 u32 pause, asm_dir, reg_val;
4031 DEBUGFUNC("ixgbe_setup_fc_X550em");
4033 /* Validate the requested mode */
4034 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4035 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4036 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4037 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4041 /* 10gig parts do not have a word in the EEPROM to determine the
4042 * default flow control setting, so we explicitly set it to full.
4044 if (hw->fc.requested_mode == ixgbe_fc_default)
4045 hw->fc.requested_mode = ixgbe_fc_full;
4047 /* Determine PAUSE and ASM_DIR bits. */
4048 switch (hw->fc.requested_mode) {
4053 case ixgbe_fc_tx_pause:
4057 case ixgbe_fc_rx_pause:
4058 /* Rx Flow control is enabled and Tx Flow control is
4059 * disabled by software override. Since there really
4060 * isn't a way to advertise that we are capable of RX
4061 * Pause ONLY, we will advertise that we support both
4062 * symmetric and asymmetric Rx PAUSE, as such we fall
4063 * through to the fc_full statement. Later, we will
4064 * disable the adapter's ability to send PAUSE frames.
4071 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4072 "Flow control param set incorrectly\n");
4073 ret_val = IXGBE_ERR_CONFIG;
4077 switch (hw->device_id) {
4078 case IXGBE_DEV_ID_X550EM_X_KR:
4079 case IXGBE_DEV_ID_X550EM_A_KR:
4080 case IXGBE_DEV_ID_X550EM_A_KR_L:
4081 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
4082 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4083 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
4084 if (ret_val != IXGBE_SUCCESS)
4086 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4087 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4089 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4091 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4092 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
4093 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4094 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
4096 /* This device does not fully support AN. */
4097 hw->fc.disable_fc_autoneg = true;
4108 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
4109 * @hw: pointer to hardware structure
4111 * Enable flow control according to IEEE clause 37.
4113 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
4115 u32 link_s1, lp_an_page_low, an_cntl_1;
4116 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4117 ixgbe_link_speed speed;
4120 /* AN should have completed when the cable was plugged in.
4121 * Look for reasons to bail out. Bail out if:
4122 * - FC autoneg is disabled, or if
4125 if (hw->fc.disable_fc_autoneg) {
4126 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4127 "Flow control autoneg is disabled");
4131 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4133 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4137 /* Check at auto-negotiation has completed */
4138 status = hw->mac.ops.read_iosf_sb_reg(hw,
4139 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4140 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4142 if (status != IXGBE_SUCCESS ||
4143 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4144 DEBUGOUT("Auto-Negotiation did not complete\n");
4145 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4149 /* Read the 10g AN autoc and LP ability registers and resolve
4150 * local flow control settings accordingly
4152 status = hw->mac.ops.read_iosf_sb_reg(hw,
4153 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4154 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4156 if (status != IXGBE_SUCCESS) {
4157 DEBUGOUT("Auto-Negotiation did not complete\n");
4161 status = hw->mac.ops.read_iosf_sb_reg(hw,
4162 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4163 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4165 if (status != IXGBE_SUCCESS) {
4166 DEBUGOUT("Auto-Negotiation did not complete\n");
4170 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4171 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4172 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4173 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4174 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4177 if (status == IXGBE_SUCCESS) {
4178 hw->fc.fc_was_autonegged = true;
4180 hw->fc.fc_was_autonegged = false;
4181 hw->fc.current_mode = hw->fc.requested_mode;
4186 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4187 * @hw: pointer to hardware structure
4190 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4192 hw->fc.fc_was_autonegged = false;
4193 hw->fc.current_mode = hw->fc.requested_mode;
4197 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4198 * @hw: pointer to hardware structure
4200 * Enable flow control according to IEEE clause 37.
4202 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4204 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4205 u16 reg, pcs_an_lp, pcs_an;
4206 ixgbe_link_speed speed;
4209 /* AN should have completed when the cable was plugged in.
4210 * Look for reasons to bail out. Bail out if:
4211 * - FC autoneg is disabled, or if
4214 if (hw->fc.disable_fc_autoneg) {
4215 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4216 "Flow control autoneg is disabled");
4220 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4222 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4226 /* Check if auto-negotiation has completed */
4227 status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_STATUS,
4228 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4229 if (status != IXGBE_SUCCESS ||
4230 (reg & IXGBE_M88E1500_COPPER_STATUS_AN_DONE) == 0) {
4231 DEBUGOUT("Auto-Negotiation did not complete\n");
4232 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4236 /* Get the advertized flow control */
4237 status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4238 IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an);
4239 if (status != IXGBE_SUCCESS)
4242 /* Get link partner's flow control */
4243 status = hw->phy.ops.read_reg(hw,
4244 IXGBE_M88E1500_COPPER_AN_LP_ABILITY,
4245 IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an_lp);
4246 if (status != IXGBE_SUCCESS)
4249 /* Negotiate the flow control */
4250 status = ixgbe_negotiate_fc(hw, (u32)pcs_an, (u32)pcs_an_lp,
4251 IXGBE_M88E1500_COPPER_AN_PAUSE,
4252 IXGBE_M88E1500_COPPER_AN_AS_PAUSE,
4253 IXGBE_M88E1500_COPPER_AN_LP_PAUSE,
4254 IXGBE_M88E1500_COPPER_AN_LP_AS_PAUSE);
4257 if (status == IXGBE_SUCCESS) {
4258 hw->fc.fc_was_autonegged = true;
4260 hw->fc.fc_was_autonegged = false;
4261 hw->fc.current_mode = hw->fc.requested_mode;
4266 * ixgbe_setup_fc_sgmii_x550em_a - Set up flow control
4267 * @hw: pointer to hardware structure
4269 * Called at init time to set up flow control.
4271 s32 ixgbe_setup_fc_sgmii_x550em_a(struct ixgbe_hw *hw)
4276 /* Validate the requested mode */
4277 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4278 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4279 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4280 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4283 if (hw->fc.requested_mode == ixgbe_fc_default)
4284 hw->fc.requested_mode = ixgbe_fc_full;
4286 /* Read contents of the Auto-Negotiation register, page 0 reg 4 */
4287 rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4288 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4292 /* Disable all the settings related to Flow control Auto-negotiation */
4293 reg &= ~IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4294 reg &= ~IXGBE_M88E1500_COPPER_AN_PAUSE;
4296 /* Configure the Asymmetric and symmetric pause according to the user
4299 switch (hw->fc.requested_mode) {
4301 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4302 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4304 case ixgbe_fc_rx_pause:
4305 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4306 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4308 case ixgbe_fc_tx_pause:
4309 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4315 /* Write back to the Auto-Negotiation register with newly configured
4318 hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_AN,
4319 IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4321 /* In this section of the code we restart Auto-negotiation */
4323 /* Read the CONTROL register, Page 0 reg 0 */
4324 rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4325 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4329 /* Set the bit to restart Auto-Neg. The bit to enable Auto-neg is ON
4332 reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
4334 /* write the new values to the register to restart Auto-Negotiation */
4335 hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4336 IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4343 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4344 * @hw: pointer to hardware structure
4346 * Called at init time to set up flow control.
4348 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4350 s32 status = IXGBE_SUCCESS;
4353 DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4355 /* Validate the requested mode */
4356 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4357 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4358 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4359 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4362 if (hw->fc.requested_mode == ixgbe_fc_default)
4363 hw->fc.requested_mode = ixgbe_fc_full;
4365 /* Set up the 1G and 10G flow control advertisement registers so the
4366 * HW will be able to do FC autoneg once the cable is plugged in. If
4367 * we link at 10G, the 1G advertisement is harmless and vice versa.
4369 status = hw->mac.ops.read_iosf_sb_reg(hw,
4370 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4371 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4373 if (status != IXGBE_SUCCESS) {
4374 DEBUGOUT("Auto-Negotiation did not complete\n");
4378 /* The possible values of fc.requested_mode are:
4379 * 0: Flow control is completely disabled
4380 * 1: Rx flow control is enabled (we can receive pause frames,
4381 * but not send pause frames).
4382 * 2: Tx flow control is enabled (we can send pause frames but
4383 * we do not support receiving pause frames).
4384 * 3: Both Rx and Tx flow control (symmetric) are enabled.
4387 switch (hw->fc.requested_mode) {
4389 /* Flow control completely disabled by software override. */
4390 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4391 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4393 case ixgbe_fc_tx_pause:
4394 /* Tx Flow control is enabled, and Rx Flow control is
4395 * disabled by software override.
4397 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4398 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4400 case ixgbe_fc_rx_pause:
4401 /* Rx Flow control is enabled and Tx Flow control is
4402 * disabled by software override. Since there really
4403 * isn't a way to advertise that we are capable of RX
4404 * Pause ONLY, we will advertise that we support both
4405 * symmetric and asymmetric Rx PAUSE, as such we fall
4406 * through to the fc_full statement. Later, we will
4407 * disable the adapter's ability to send PAUSE frames.
4410 /* Flow control (both Rx and Tx) is enabled by SW override. */
4411 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4412 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4415 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4416 "Flow control param set incorrectly\n");
4417 return IXGBE_ERR_CONFIG;
4420 status = hw->mac.ops.write_iosf_sb_reg(hw,
4421 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4422 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4424 /* Restart auto-negotiation. */
4425 status = ixgbe_restart_an_internal_phy_x550em(hw);
4431 * ixgbe_set_mux - Set mux for port 1 access with CS4227
4432 * @hw: pointer to hardware structure
4433 * @state: set mux if 1, clear if 0
4435 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4439 if (!hw->bus.lan_id)
4441 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4443 esdp |= IXGBE_ESDP_SDP1;
4445 esdp &= ~IXGBE_ESDP_SDP1;
4446 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4447 IXGBE_WRITE_FLUSH(hw);
4451 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4452 * @hw: pointer to hardware structure
4453 * @mask: Mask to specify which semaphore to acquire
4455 * Acquires the SWFW semaphore and sets the I2C MUX
4457 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4461 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4463 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4467 if (mask & IXGBE_GSSR_I2C_MASK)
4468 ixgbe_set_mux(hw, 1);
4470 return IXGBE_SUCCESS;
4474 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4475 * @hw: pointer to hardware structure
4476 * @mask: Mask to specify which semaphore to release
4478 * Releases the SWFW semaphore and sets the I2C MUX
4480 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4482 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4484 if (mask & IXGBE_GSSR_I2C_MASK)
4485 ixgbe_set_mux(hw, 0);
4487 ixgbe_release_swfw_sync_X540(hw, mask);
4491 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4492 * @hw: pointer to hardware structure
4493 * @mask: Mask to specify which semaphore to acquire
4495 * Acquires the SWFW semaphore and get the shared phy token as needed
4497 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4499 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4500 int retries = FW_PHY_TOKEN_RETRIES;
4501 s32 status = IXGBE_SUCCESS;
4503 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4506 status = IXGBE_SUCCESS;
4508 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4511 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4512 return IXGBE_SUCCESS;
4514 status = ixgbe_get_phy_token(hw);
4515 if (status == IXGBE_SUCCESS)
4516 return IXGBE_SUCCESS;
4519 ixgbe_release_swfw_sync_X540(hw, hmask);
4520 if (status != IXGBE_ERR_TOKEN_RETRY)
4528 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4529 * @hw: pointer to hardware structure
4530 * @mask: Mask to specify which semaphore to release
4532 * Releases the SWFW semaphore and puts the shared phy token as needed
4534 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4536 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4538 DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4540 if (mask & IXGBE_GSSR_TOKEN_SM)
4541 ixgbe_put_phy_token(hw);
4544 ixgbe_release_swfw_sync_X540(hw, hmask);
4548 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
4549 * @hw: pointer to hardware structure
4550 * @reg_addr: 32 bit address of PHY register to read
4551 * @phy_data: Pointer to read data from PHY register
4553 * Reads a value from a specified PHY register using the SWFW lock and PHY
4554 * Token. The PHY Token is needed since the MDIO is shared between to MAC
4557 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4558 u32 device_type, u16 *phy_data)
4561 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4563 DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4565 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4566 return IXGBE_ERR_SWFW_SYNC;
4568 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4570 hw->mac.ops.release_swfw_sync(hw, mask);
4576 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
4577 * @hw: pointer to hardware structure
4578 * @reg_addr: 32 bit PHY register to write
4579 * @device_type: 5 bit device type
4580 * @phy_data: Data to write to the PHY register
4582 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
4583 * The PHY Token is needed since the MDIO is shared between to MAC instances.
4585 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4586 u32 device_type, u16 phy_data)
4589 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4591 DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4593 if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4594 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4596 hw->mac.ops.release_swfw_sync(hw, mask);
4598 status = IXGBE_ERR_SWFW_SYNC;
4605 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4606 * @hw: pointer to hardware structure
4608 * Handle external Base T PHY interrupt. If high temperature
4609 * failure alarm then return error, else if link status change
4610 * then setup internal/external PHY link
4612 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4613 * failure alarm, else return PHY access status.
4615 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4620 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4622 if (status != IXGBE_SUCCESS)
4626 return ixgbe_setup_internal_phy(hw);
4628 return IXGBE_SUCCESS;
4632 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4633 * @hw: pointer to hardware structure
4634 * @speed: new link speed
4635 * @autoneg_wait_to_complete: true when waiting for completion is needed
4637 * Setup internal/external PHY link speed based on link speed, then set
4638 * external PHY auto advertised link speed.
4640 * Returns error status for any failure
4642 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4643 ixgbe_link_speed speed,
4644 bool autoneg_wait_to_complete)
4647 ixgbe_link_speed force_speed;
4649 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4651 /* Setup internal/external PHY link speed to iXFI (10G), unless
4652 * only 1G is auto advertised then setup KX link.
4654 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4655 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4657 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4659 /* If X552 and internal link mode is XFI, then setup XFI internal link.
4661 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4662 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4663 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4665 if (status != IXGBE_SUCCESS)
4669 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4673 * ixgbe_check_link_t_X550em - Determine link and speed status
4674 * @hw: pointer to hardware structure
4675 * @speed: pointer to link speed
4676 * @link_up: true when link is up
4677 * @link_up_wait_to_complete: bool used to wait for link up or not
4679 * Check that both the MAC and X557 external PHY have link.
4681 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4682 bool *link_up, bool link_up_wait_to_complete)
4685 u16 i, autoneg_status = 0;
4687 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4688 return IXGBE_ERR_CONFIG;
4690 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4691 link_up_wait_to_complete);
4693 /* If check link fails or MAC link is not up, then return */
4694 if (status != IXGBE_SUCCESS || !(*link_up))
4697 /* MAC link is up, so check external PHY link.
4698 * X557 PHY. Link status is latching low, and can only be used to detect
4699 * link drop, and not the current status of the link without performing
4700 * back-to-back reads.
4702 for (i = 0; i < 2; i++) {
4703 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4704 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4707 if (status != IXGBE_SUCCESS)
4711 /* If external PHY link is not up, then indicate link not up */
4712 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4715 return IXGBE_SUCCESS;
4719 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4720 * @hw: pointer to hardware structure
4722 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4726 status = ixgbe_reset_phy_generic(hw);
4728 if (status != IXGBE_SUCCESS)
4731 /* Configure Link Status Alarm and Temperature Threshold interrupts */
4732 return ixgbe_enable_lasi_ext_t_x550em(hw);
4736 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4737 * @hw: pointer to hardware structure
4738 * @led_idx: led number to turn on
4740 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4744 DEBUGFUNC("ixgbe_led_on_t_X550em");
4746 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4747 return IXGBE_ERR_PARAM;
4749 /* To turn on the LED, set mode to ON. */
4750 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4751 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4752 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4753 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4754 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4756 return IXGBE_SUCCESS;
4760 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4761 * @hw: pointer to hardware structure
4762 * @led_idx: led number to turn off
4764 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4768 DEBUGFUNC("ixgbe_led_off_t_X550em");
4770 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4771 return IXGBE_ERR_PARAM;
4773 /* To turn on the LED, set mode to ON. */
4774 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4775 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4776 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4777 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4778 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4780 return IXGBE_SUCCESS;
4784 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
4785 * @hw: pointer to the HW structure
4786 * @maj: driver version major number
4787 * @min: driver version minor number
4788 * @build: driver version build number
4789 * @sub: driver version sub build number
4790 * @len: length of driver_ver string
4791 * @driver_ver: driver string
4793 * Sends driver version number to firmware through the manageability
4794 * block. On success return IXGBE_SUCCESS
4795 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4796 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4798 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
4799 u8 build, u8 sub, u16 len, const char *driver_ver)
4801 struct ixgbe_hic_drv_info2 fw_cmd;
4802 s32 ret_val = IXGBE_SUCCESS;
4805 DEBUGFUNC("ixgbe_set_fw_drv_ver_x550");
4807 if ((len == 0) || (driver_ver == NULL) ||
4808 (len > sizeof(fw_cmd.driver_string)))
4809 return IXGBE_ERR_INVALID_ARGUMENT;
4811 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4812 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
4813 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4814 fw_cmd.port_num = (u8)hw->bus.func;
4815 fw_cmd.ver_maj = maj;
4816 fw_cmd.ver_min = min;
4817 fw_cmd.ver_build = build;
4818 fw_cmd.ver_sub = sub;
4819 fw_cmd.hdr.checksum = 0;
4820 memcpy(fw_cmd.driver_string, driver_ver, len);
4821 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4822 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4824 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4825 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4827 IXGBE_HI_COMMAND_TIMEOUT,
4829 if (ret_val != IXGBE_SUCCESS)
4832 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4833 FW_CEM_RESP_STATUS_SUCCESS)
4834 ret_val = IXGBE_SUCCESS;
4836 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;