1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
47 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
48 * @hw: pointer to hardware structure
50 * Initialize the function pointers and assign the MAC type for X550.
51 * Does not touch the hardware.
53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
55 struct ixgbe_mac_info *mac = &hw->mac;
56 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
59 DEBUGFUNC("ixgbe_init_ops_X550");
61 ret_val = ixgbe_init_ops_X540(hw);
62 mac->ops.dmac_config = ixgbe_dmac_config_X550;
63 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
64 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
65 mac->ops.setup_eee = ixgbe_setup_eee_X550;
66 mac->ops.set_source_address_pruning =
67 ixgbe_set_source_address_pruning_X550;
68 mac->ops.set_ethertype_anti_spoofing =
69 ixgbe_set_ethertype_anti_spoofing_X550;
71 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
72 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
73 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
74 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
75 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
76 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
77 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
78 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
79 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
81 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
82 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
83 mac->ops.mdd_event = ixgbe_mdd_event_X550;
84 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
85 mac->ops.disable_rx = ixgbe_disable_rx_x550;
86 switch (hw->device_id) {
87 case IXGBE_DEV_ID_X550EM_X_10G_T:
88 case IXGBE_DEV_ID_X550EM_A_10G_T:
89 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
90 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
99 * ixgbe_read_cs4227 - Read CS4227 register
100 * @hw: pointer to hardware structure
101 * @reg: register number to write
102 * @value: pointer to receive value read
104 * Returns status code
106 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
108 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
112 * ixgbe_write_cs4227 - Write CS4227 register
113 * @hw: pointer to hardware structure
114 * @reg: register number to write
115 * @value: value to write to register
117 * Returns status code
119 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
121 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
125 * ixgbe_read_pe - Read register from port expander
126 * @hw: pointer to hardware structure
127 * @reg: register number to read
128 * @value: pointer to receive read value
130 * Returns status code
132 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
136 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
137 if (status != IXGBE_SUCCESS)
138 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
139 "port expander access failed with %d\n", status);
144 * ixgbe_write_pe - Write register to port expander
145 * @hw: pointer to hardware structure
146 * @reg: register number to write
147 * @value: value to write
149 * Returns status code
151 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
155 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
156 if (status != IXGBE_SUCCESS)
157 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
158 "port expander access failed with %d\n", status);
163 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
164 * @hw: pointer to hardware structure
166 * This function assumes that the caller has acquired the proper semaphore.
169 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
176 /* Trigger hard reset. */
177 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
178 if (status != IXGBE_SUCCESS)
180 reg |= IXGBE_PE_BIT1;
181 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
182 if (status != IXGBE_SUCCESS)
185 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
186 if (status != IXGBE_SUCCESS)
188 reg &= ~IXGBE_PE_BIT1;
189 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
190 if (status != IXGBE_SUCCESS)
193 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
194 if (status != IXGBE_SUCCESS)
196 reg &= ~IXGBE_PE_BIT1;
197 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
198 if (status != IXGBE_SUCCESS)
201 usec_delay(IXGBE_CS4227_RESET_HOLD);
203 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
204 if (status != IXGBE_SUCCESS)
206 reg |= IXGBE_PE_BIT1;
207 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
208 if (status != IXGBE_SUCCESS)
211 /* Wait for the reset to complete. */
212 msec_delay(IXGBE_CS4227_RESET_DELAY);
213 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
214 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
216 if (status == IXGBE_SUCCESS &&
217 value == IXGBE_CS4227_EEPROM_LOAD_OK)
219 msec_delay(IXGBE_CS4227_CHECK_DELAY);
221 if (retry == IXGBE_CS4227_RETRIES) {
222 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
223 "CS4227 reset did not complete.");
224 return IXGBE_ERR_PHY;
227 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
228 if (status != IXGBE_SUCCESS ||
229 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
230 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
231 "CS4227 EEPROM did not load successfully.");
232 return IXGBE_ERR_PHY;
235 return IXGBE_SUCCESS;
239 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
240 * @hw: pointer to hardware structure
242 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
244 s32 status = IXGBE_SUCCESS;
245 u32 swfw_mask = hw->phy.phy_semaphore_mask;
249 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
250 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
251 if (status != IXGBE_SUCCESS) {
252 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
253 "semaphore failed with %d", status);
254 msec_delay(IXGBE_CS4227_CHECK_DELAY);
258 /* Get status of reset flow. */
259 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
261 if (status == IXGBE_SUCCESS &&
262 value == IXGBE_CS4227_RESET_COMPLETE)
265 if (status != IXGBE_SUCCESS ||
266 value != IXGBE_CS4227_RESET_PENDING)
269 /* Reset is pending. Wait and check again. */
270 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
271 msec_delay(IXGBE_CS4227_CHECK_DELAY);
274 /* If still pending, assume other instance failed. */
275 if (retry == IXGBE_CS4227_RETRIES) {
276 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
277 if (status != IXGBE_SUCCESS) {
278 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
279 "semaphore failed with %d", status);
284 /* Reset the CS4227. */
285 status = ixgbe_reset_cs4227(hw);
286 if (status != IXGBE_SUCCESS) {
287 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
288 "CS4227 reset failed: %d", status);
292 /* Reset takes so long, temporarily release semaphore in case the
293 * other driver instance is waiting for the reset indication.
295 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
296 IXGBE_CS4227_RESET_PENDING);
297 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
299 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
300 if (status != IXGBE_SUCCESS) {
301 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
302 "semaphore failed with %d", status);
306 /* Record completion for next time. */
307 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
308 IXGBE_CS4227_RESET_COMPLETE);
311 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
312 msec_delay(hw->eeprom.semaphore_delay);
316 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
317 * @hw: pointer to hardware structure
319 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
321 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
323 if (hw->bus.lan_id) {
324 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
325 esdp |= IXGBE_ESDP_SDP1_DIR;
327 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
328 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
329 IXGBE_WRITE_FLUSH(hw);
333 * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
334 * @hw: pointer to hardware structure
335 * @reg_addr: 32 bit address of PHY register to read
336 * @dev_type: always unused
337 * @phy_data: Pointer to read data from PHY register
339 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
340 u32 dev_type, u16 *phy_data)
342 u32 i, data, command;
343 UNREFERENCED_1PARAMETER(dev_type);
345 /* Setup and write the read command */
346 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
347 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
348 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
349 IXGBE_MSCA_MDI_COMMAND;
351 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
353 /* Check every 10 usec to see if the access completed.
354 * The MDI Command bit will clear when the operation is
357 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
360 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
361 if (!(command & IXGBE_MSCA_MDI_COMMAND))
365 if (command & IXGBE_MSCA_MDI_COMMAND) {
366 ERROR_REPORT1(IXGBE_ERROR_POLLING,
367 "PHY read command did not complete.\n");
368 return IXGBE_ERR_PHY;
371 /* Read operation is complete. Get the data from MSRWD */
372 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
373 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
374 *phy_data = (u16)data;
376 return IXGBE_SUCCESS;
380 * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
381 * @hw: pointer to hardware structure
382 * @reg_addr: 32 bit PHY register to write
383 * @dev_type: always unused
384 * @phy_data: Data to write to the PHY register
386 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
387 u32 dev_type, u16 phy_data)
390 UNREFERENCED_1PARAMETER(dev_type);
392 /* Put the data in the MDI single read and write data register*/
393 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
395 /* Setup and write the write command */
396 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
397 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
398 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
399 IXGBE_MSCA_MDI_COMMAND;
401 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
403 /* Check every 10 usec to see if the access completed.
404 * The MDI Command bit will clear when the operation is
407 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
410 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
411 if (!(command & IXGBE_MSCA_MDI_COMMAND))
415 if (command & IXGBE_MSCA_MDI_COMMAND) {
416 ERROR_REPORT1(IXGBE_ERROR_POLLING,
417 "PHY write cmd didn't complete\n");
418 return IXGBE_ERR_PHY;
421 return IXGBE_SUCCESS;
425 * ixgbe_identify_phy_x550em - Get PHY type based on device id
426 * @hw: pointer to hardware structure
430 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
432 hw->mac.ops.set_lan_id(hw);
434 ixgbe_read_mng_if_sel_x550em(hw);
436 switch (hw->device_id) {
437 case IXGBE_DEV_ID_X550EM_A_SFP:
438 return ixgbe_identify_module_generic(hw);
439 case IXGBE_DEV_ID_X550EM_X_SFP:
440 /* set up for CS4227 usage */
441 ixgbe_setup_mux_ctl(hw);
442 ixgbe_check_cs4227(hw);
445 case IXGBE_DEV_ID_X550EM_A_SFP_N:
446 return ixgbe_identify_module_generic(hw);
448 case IXGBE_DEV_ID_X550EM_X_KX4:
449 hw->phy.type = ixgbe_phy_x550em_kx4;
451 case IXGBE_DEV_ID_X550EM_X_KR:
452 case IXGBE_DEV_ID_X550EM_A_KR:
453 case IXGBE_DEV_ID_X550EM_A_KR_L:
454 hw->phy.type = ixgbe_phy_x550em_kr;
456 case IXGBE_DEV_ID_X550EM_A_10G_T:
457 case IXGBE_DEV_ID_X550EM_A_1G_T:
458 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
459 case IXGBE_DEV_ID_X550EM_X_1G_T:
460 case IXGBE_DEV_ID_X550EM_X_10G_T:
461 return ixgbe_identify_phy_generic(hw);
465 return IXGBE_SUCCESS;
468 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
469 u32 device_type, u16 *phy_data)
471 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
472 return IXGBE_NOT_IMPLEMENTED;
475 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
476 u32 device_type, u16 phy_data)
478 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
479 return IXGBE_NOT_IMPLEMENTED;
483 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
484 * @hw: pointer to the hardware structure
485 * @addr: I2C bus address to read from
486 * @reg: I2C device register to read from
487 * @val: pointer to location to receive read value
489 * Returns an error code on error.
491 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
494 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
498 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
499 * @hw: pointer to the hardware structure
500 * @addr: I2C bus address to read from
501 * @reg: I2C device register to read from
502 * @val: pointer to location to receive read value
504 * Returns an error code on error.
507 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
510 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
514 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
515 * @hw: pointer to the hardware structure
516 * @addr: I2C bus address to write to
517 * @reg: I2C device register to write to
518 * @val: value to write
520 * Returns an error code on error.
522 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
523 u8 addr, u16 reg, u16 val)
525 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
529 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
530 * @hw: pointer to the hardware structure
531 * @addr: I2C bus address to write to
532 * @reg: I2C device register to write to
533 * @val: value to write
535 * Returns an error code on error.
538 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
539 u8 addr, u16 reg, u16 val)
541 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
545 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
546 * @hw: pointer to hardware structure
548 * Initialize the function pointers and for MAC type X550EM.
549 * Does not touch the hardware.
551 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
553 struct ixgbe_mac_info *mac = &hw->mac;
554 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
555 struct ixgbe_phy_info *phy = &hw->phy;
558 DEBUGFUNC("ixgbe_init_ops_X550EM");
560 /* Similar to X550 so start there. */
561 ret_val = ixgbe_init_ops_X550(hw);
563 /* Since this function eventually calls
564 * ixgbe_init_ops_540 by design, we are setting
565 * the pointers to NULL explicitly here to overwrite
566 * the values being set in the x540 function.
568 /* Thermal sensor not supported in x550EM */
569 mac->ops.get_thermal_sensor_data = NULL;
570 mac->ops.init_thermal_sensor_thresh = NULL;
571 mac->thermal_sensor_enabled = false;
573 /* FCOE not supported in x550EM */
574 mac->ops.get_san_mac_addr = NULL;
575 mac->ops.set_san_mac_addr = NULL;
576 mac->ops.get_wwn_prefix = NULL;
577 mac->ops.get_fcoe_boot_status = NULL;
579 /* IPsec not supported in x550EM */
580 mac->ops.disable_sec_rx_path = NULL;
581 mac->ops.enable_sec_rx_path = NULL;
583 /* AUTOC register is not present in x550EM. */
584 mac->ops.prot_autoc_read = NULL;
585 mac->ops.prot_autoc_write = NULL;
587 /* X550EM bus type is internal*/
588 hw->bus.type = ixgbe_bus_type_internal;
589 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
592 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
593 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
594 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
595 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
596 mac->ops.get_supported_physical_layer =
597 ixgbe_get_supported_physical_layer_X550em;
599 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
600 mac->ops.setup_fc = ixgbe_setup_fc_generic;
602 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
604 switch (hw->device_id) {
605 case IXGBE_DEV_ID_X550EM_X_KR:
606 case IXGBE_DEV_ID_X550EM_A_KR:
607 case IXGBE_DEV_ID_X550EM_A_KR_L:
610 mac->ops.setup_eee = NULL;
614 phy->ops.init = ixgbe_init_phy_ops_X550em;
615 phy->ops.identify = ixgbe_identify_phy_x550em;
616 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
617 phy->ops.set_phy_power = NULL;
621 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
622 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
623 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
624 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
625 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
626 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
627 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
628 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
634 * ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
635 * @hw: pointer to hardware structure
637 * Initialize the function pointers and for MAC type X550EM_a.
638 * Does not touch the hardware.
640 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
642 struct ixgbe_mac_info *mac = &hw->mac;
645 DEBUGFUNC("ixgbe_init_ops_X550EM_a");
647 /* Start with generic X550EM init */
648 ret_val = ixgbe_init_ops_X550EM(hw);
650 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
651 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
652 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
653 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
655 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
656 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
658 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
659 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
661 switch (mac->ops.get_media_type(hw)) {
662 case ixgbe_media_type_fiber:
663 mac->ops.setup_fc = ixgbe_setup_fc_fiber_x550em_a;
664 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
666 case ixgbe_media_type_backplane:
667 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
668 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
674 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T) ||
675 (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)) {
676 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
677 mac->ops.setup_fc = ixgbe_setup_fc_sgmii_x550em_a;
684 * ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
685 * @hw: pointer to hardware structure
687 * Initialize the function pointers and for MAC type X550EM_x.
688 * Does not touch the hardware.
690 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
692 struct ixgbe_mac_info *mac = &hw->mac;
693 struct ixgbe_link_info *link = &hw->link;
696 DEBUGFUNC("ixgbe_init_ops_X550EM_x");
698 /* Start with generic X550EM init */
699 ret_val = ixgbe_init_ops_X550EM(hw);
701 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
702 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
703 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
704 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
705 link->ops.read_link = ixgbe_read_i2c_combined_generic;
706 link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
707 link->ops.write_link = ixgbe_write_i2c_combined_generic;
708 link->ops.write_link_unlocked =
709 ixgbe_write_i2c_combined_generic_unlocked;
710 link->addr = IXGBE_CS4227;
716 * ixgbe_dmac_config_X550
717 * @hw: pointer to hardware structure
719 * Configure DMA coalescing. If enabling dmac, dmac is activated.
720 * When disabling dmac, dmac enable dmac bit is cleared.
722 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
724 u32 reg, high_pri_tc;
726 DEBUGFUNC("ixgbe_dmac_config_X550");
728 /* Disable DMA coalescing before configuring */
729 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
730 reg &= ~IXGBE_DMACR_DMAC_EN;
731 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
733 /* Disable DMA Coalescing if the watchdog timer is 0 */
734 if (!hw->mac.dmac_config.watchdog_timer)
737 ixgbe_dmac_config_tcs_X550(hw);
739 /* Configure DMA Coalescing Control Register */
740 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
742 /* Set the watchdog timer in units of 40.96 usec */
743 reg &= ~IXGBE_DMACR_DMACWT_MASK;
744 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
746 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
747 /* If fcoe is enabled, set high priority traffic class */
748 if (hw->mac.dmac_config.fcoe_en) {
749 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
750 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
751 IXGBE_DMACR_HIGH_PRI_TC_MASK);
753 reg |= IXGBE_DMACR_EN_MNG_IND;
755 /* Enable DMA coalescing after configuration */
756 reg |= IXGBE_DMACR_DMAC_EN;
757 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
760 return IXGBE_SUCCESS;
764 * ixgbe_dmac_config_tcs_X550
765 * @hw: pointer to hardware structure
767 * Configure DMA coalescing threshold per TC. The dmac enable bit must
768 * be cleared before configuring.
770 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
772 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
774 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
776 /* Configure DMA coalescing enabled */
777 switch (hw->mac.dmac_config.link_speed) {
778 case IXGBE_LINK_SPEED_10_FULL:
779 case IXGBE_LINK_SPEED_100_FULL:
780 pb_headroom = IXGBE_DMACRXT_100M;
782 case IXGBE_LINK_SPEED_1GB_FULL:
783 pb_headroom = IXGBE_DMACRXT_1G;
786 pb_headroom = IXGBE_DMACRXT_10G;
790 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
791 IXGBE_MHADD_MFS_SHIFT) / 1024);
793 /* Set the per Rx packet buffer receive threshold */
794 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
795 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
796 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
798 if (tc < hw->mac.dmac_config.num_tcs) {
800 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
801 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
802 IXGBE_RXPBSIZE_SHIFT;
804 /* Calculate receive buffer threshold in kilobytes */
805 if (rx_pb_size > pb_headroom)
806 rx_pb_size = rx_pb_size - pb_headroom;
810 /* Minimum of MFS shall be set for DMCTH */
811 reg |= (rx_pb_size > maxframe_size_kb) ?
812 rx_pb_size : maxframe_size_kb;
814 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
816 return IXGBE_SUCCESS;
820 * ixgbe_dmac_update_tcs_X550
821 * @hw: pointer to hardware structure
823 * Disables dmac, updates per TC settings, and then enables dmac.
825 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
829 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
831 /* Disable DMA coalescing before configuring */
832 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
833 reg &= ~IXGBE_DMACR_DMAC_EN;
834 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
836 ixgbe_dmac_config_tcs_X550(hw);
838 /* Enable DMA coalescing after configuration */
839 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
840 reg |= IXGBE_DMACR_DMAC_EN;
841 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
843 return IXGBE_SUCCESS;
847 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
848 * @hw: pointer to hardware structure
850 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
851 * ixgbe_hw struct in order to set up EEPROM access.
853 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
855 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
859 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
861 if (eeprom->type == ixgbe_eeprom_uninitialized) {
862 eeprom->semaphore_delay = 10;
863 eeprom->type = ixgbe_flash;
865 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
866 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
867 IXGBE_EEC_SIZE_SHIFT);
868 eeprom->word_size = 1 << (eeprom_size +
869 IXGBE_EEPROM_WORD_SIZE_SHIFT);
871 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
872 eeprom->type, eeprom->word_size);
875 return IXGBE_SUCCESS;
879 * ixgbe_enable_eee_x550 - Enable EEE support
880 * @hw: pointer to hardware structure
882 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
888 if (hw->mac.type == ixgbe_mac_X550) {
889 /* Advertise EEE capability */
890 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
891 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
894 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
895 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
896 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
898 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
899 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
901 return IXGBE_SUCCESS;
904 switch (hw->device_id) {
905 case IXGBE_DEV_ID_X550EM_X_KR:
906 case IXGBE_DEV_ID_X550EM_A_KR:
907 case IXGBE_DEV_ID_X550EM_A_KR_L:
908 status = hw->mac.ops.read_iosf_sb_reg(hw,
909 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
910 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
911 if (status != IXGBE_SUCCESS)
914 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
915 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
917 /* Don't advertise FEC capability when EEE enabled. */
918 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
920 status = hw->mac.ops.write_iosf_sb_reg(hw,
921 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
922 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
923 if (status != IXGBE_SUCCESS)
930 return IXGBE_SUCCESS;
934 * ixgbe_disable_eee_x550 - Disable EEE support
935 * @hw: pointer to hardware structure
937 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
943 if (hw->mac.type == ixgbe_mac_X550) {
944 /* Disable advertised EEE capability */
945 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
946 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
949 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
950 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
951 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
953 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
954 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
956 return IXGBE_SUCCESS;
959 switch (hw->device_id) {
960 case IXGBE_DEV_ID_X550EM_X_KR:
961 case IXGBE_DEV_ID_X550EM_A_KR:
962 case IXGBE_DEV_ID_X550EM_A_KR_L:
963 status = hw->mac.ops.read_iosf_sb_reg(hw,
964 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
965 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
966 if (status != IXGBE_SUCCESS)
969 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
970 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
972 /* Advertise FEC capability when EEE is disabled. */
973 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
975 status = hw->mac.ops.write_iosf_sb_reg(hw,
976 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
977 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
978 if (status != IXGBE_SUCCESS)
985 return IXGBE_SUCCESS;
989 * ixgbe_setup_eee_X550 - Enable/disable EEE support
990 * @hw: pointer to the HW structure
991 * @enable_eee: boolean flag to enable EEE
993 * Enable/disable EEE based on enable_eee flag.
994 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
998 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
1003 DEBUGFUNC("ixgbe_setup_eee_X550");
1005 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
1006 /* Enable or disable EEE per flag */
1008 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1010 /* Not supported on first revision of X550EM_x. */
1011 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1012 !(IXGBE_FUSES0_REV_MASK &
1013 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1014 return IXGBE_SUCCESS;
1015 status = ixgbe_enable_eee_x550(hw);
1019 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1021 status = ixgbe_disable_eee_x550(hw);
1025 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1027 return IXGBE_SUCCESS;
1031 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1032 * @hw: pointer to hardware structure
1033 * @enable: enable or disable source address pruning
1034 * @pool: Rx pool to set source address pruning for
1036 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1041 /* max rx pool is 63 */
1045 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1046 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1049 pfflp |= (1ULL << pool);
1051 pfflp &= ~(1ULL << pool);
1053 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1054 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1058 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1059 * @hw: pointer to hardware structure
1060 * @enable: enable or disable switch for Ethertype anti-spoofing
1061 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1064 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1065 bool enable, int vf)
1067 int vf_target_reg = vf >> 3;
1068 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1071 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1073 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1075 pfvfspoof |= (1 << vf_target_shift);
1077 pfvfspoof &= ~(1 << vf_target_shift);
1079 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1083 * ixgbe_iosf_wait - Wait for IOSF command completion
1084 * @hw: pointer to hardware structure
1085 * @ctrl: pointer to location to receive final IOSF control value
1087 * Returns failing status on timeout
1089 * Note: ctrl can be NULL if the IOSF control register value is not needed
1091 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1095 /* Check every 10 usec to see if the address cycle completed.
1096 * The SB IOSF BUSY bit will clear when the operation is
1099 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1100 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1101 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1107 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1108 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1109 return IXGBE_ERR_PHY;
1112 return IXGBE_SUCCESS;
1116 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1117 * of the IOSF device
1118 * @hw: pointer to hardware structure
1119 * @reg_addr: 32 bit PHY register to write
1120 * @device_type: 3 bit device type
1121 * @data: Data to write to the register
1123 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1124 u32 device_type, u32 data)
1126 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1130 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1131 if (ret != IXGBE_SUCCESS)
1134 ret = ixgbe_iosf_wait(hw, NULL);
1135 if (ret != IXGBE_SUCCESS)
1138 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1139 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1141 /* Write IOSF control register */
1142 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1144 /* Write IOSF data register */
1145 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1147 ret = ixgbe_iosf_wait(hw, &command);
1149 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1150 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1151 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1152 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1153 "Failed to write, error %x\n", error);
1154 ret = IXGBE_ERR_PHY;
1158 ixgbe_release_swfw_semaphore(hw, gssr);
1163 * ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1164 * @hw: pointer to hardware structure
1165 * @reg_addr: 32 bit PHY register to write
1166 * @device_type: 3 bit device type
1167 * @data: Pointer to read data from the register
1169 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1170 u32 device_type, u32 *data)
1172 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1176 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1177 if (ret != IXGBE_SUCCESS)
1180 ret = ixgbe_iosf_wait(hw, NULL);
1181 if (ret != IXGBE_SUCCESS)
1184 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1185 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1187 /* Write IOSF control register */
1188 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1190 ret = ixgbe_iosf_wait(hw, &command);
1192 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1193 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1194 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1195 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1196 "Failed to read, error %x\n", error);
1197 ret = IXGBE_ERR_PHY;
1200 if (ret == IXGBE_SUCCESS)
1201 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1204 ixgbe_release_swfw_semaphore(hw, gssr);
1209 * ixgbe_get_phy_token - Get the token for shared phy access
1210 * @hw: Pointer to hardware structure
1213 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1215 struct ixgbe_hic_phy_token_req token_cmd;
1218 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1219 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1220 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1221 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1222 token_cmd.port_number = hw->bus.lan_id;
1223 token_cmd.command_type = FW_PHY_TOKEN_REQ;
1225 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1227 IXGBE_HI_COMMAND_TIMEOUT,
1231 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1232 return IXGBE_SUCCESS;
1233 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1234 return IXGBE_ERR_FW_RESP_INVALID;
1236 return IXGBE_ERR_TOKEN_RETRY;
1240 * ixgbe_put_phy_token - Put the token for shared phy access
1241 * @hw: Pointer to hardware structure
1244 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1246 struct ixgbe_hic_phy_token_req token_cmd;
1249 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1250 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1251 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1252 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1253 token_cmd.port_number = hw->bus.lan_id;
1254 token_cmd.command_type = FW_PHY_TOKEN_REL;
1256 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1258 IXGBE_HI_COMMAND_TIMEOUT,
1262 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1263 return IXGBE_SUCCESS;
1265 DEBUGOUT("Put PHY Token host interface command failed");
1266 return IXGBE_ERR_FW_RESP_INVALID;
1270 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1271 * of the IOSF device
1272 * @hw: pointer to hardware structure
1273 * @reg_addr: 32 bit PHY register to write
1274 * @device_type: 3 bit device type
1275 * @data: Data to write to the register
1277 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1278 u32 device_type, u32 data)
1280 struct ixgbe_hic_internal_phy_req write_cmd;
1282 UNREFERENCED_1PARAMETER(device_type);
1284 memset(&write_cmd, 0, sizeof(write_cmd));
1285 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1286 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1287 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1288 write_cmd.port_number = hw->bus.lan_id;
1289 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1290 write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1291 write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1293 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1295 IXGBE_HI_COMMAND_TIMEOUT, false);
1301 * ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1302 * @hw: pointer to hardware structure
1303 * @reg_addr: 32 bit PHY register to write
1304 * @device_type: 3 bit device type
1305 * @data: Pointer to read data from the register
1307 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1308 u32 device_type, u32 *data)
1311 struct ixgbe_hic_internal_phy_req cmd;
1312 struct ixgbe_hic_internal_phy_resp rsp;
1315 UNREFERENCED_1PARAMETER(device_type);
1317 memset(&hic, 0, sizeof(hic));
1318 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1319 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1320 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1321 hic.cmd.port_number = hw->bus.lan_id;
1322 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1323 hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1325 status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1327 IXGBE_HI_COMMAND_TIMEOUT, true);
1329 /* Extract the register value from the response. */
1330 *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1336 * ixgbe_disable_mdd_X550
1337 * @hw: pointer to hardware structure
1339 * Disable malicious driver detection
1341 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1345 DEBUGFUNC("ixgbe_disable_mdd_X550");
1347 /* Disable MDD for TX DMA and interrupt */
1348 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1349 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1350 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1352 /* Disable MDD for RX and interrupt */
1353 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1354 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1355 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1359 * ixgbe_enable_mdd_X550
1360 * @hw: pointer to hardware structure
1362 * Enable malicious driver detection
1364 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1368 DEBUGFUNC("ixgbe_enable_mdd_X550");
1370 /* Enable MDD for TX DMA and interrupt */
1371 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1372 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1373 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1375 /* Enable MDD for RX and interrupt */
1376 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1377 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1378 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1382 * ixgbe_restore_mdd_vf_X550
1383 * @hw: pointer to hardware structure
1386 * Restore VF that was disabled during malicious driver detection event
1388 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1390 u32 idx, reg, num_qs, start_q, bitmask;
1392 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1394 /* Map VF to queues */
1395 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1396 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1397 case IXGBE_MRQC_VMDQRT8TCEN:
1398 num_qs = 8; /* 16 VFs / pools */
1399 bitmask = 0x000000FF;
1401 case IXGBE_MRQC_VMDQRSS32EN:
1402 case IXGBE_MRQC_VMDQRT4TCEN:
1403 num_qs = 4; /* 32 VFs / pools */
1404 bitmask = 0x0000000F;
1406 default: /* 64 VFs / pools */
1408 bitmask = 0x00000003;
1411 start_q = vf * num_qs;
1413 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1416 reg |= (bitmask << (start_q % 32));
1417 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1418 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1422 * ixgbe_mdd_event_X550
1423 * @hw: pointer to hardware structure
1424 * @vf_bitmap: vf bitmap of malicious vfs
1426 * Handle malicious driver detection event.
1428 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1431 u32 i, j, reg, q, shift, vf, idx;
1433 DEBUGFUNC("ixgbe_mdd_event_X550");
1435 /* figure out pool size for mapping to vf's */
1436 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1437 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1438 case IXGBE_MRQC_VMDQRT8TCEN:
1439 shift = 3; /* 16 VFs / pools */
1441 case IXGBE_MRQC_VMDQRSS32EN:
1442 case IXGBE_MRQC_VMDQRT4TCEN:
1443 shift = 2; /* 32 VFs / pools */
1446 shift = 1; /* 64 VFs / pools */
1450 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1451 for (i = 0; i < 4; i++) {
1452 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1453 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1458 /* Get malicious queue */
1459 for (j = 0; j < 32 && wqbr; j++) {
1461 if (!(wqbr & (1 << j)))
1464 /* Get queue from bitmask */
1467 /* Map queue to vf */
1470 /* Set vf bit in vf_bitmap */
1472 vf_bitmap[idx] |= (1 << (vf % 32));
1479 * ixgbe_get_media_type_X550em - Get media type
1480 * @hw: pointer to hardware structure
1482 * Returns the media type (fiber, copper, backplane)
1484 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1486 enum ixgbe_media_type media_type;
1488 DEBUGFUNC("ixgbe_get_media_type_X550em");
1490 /* Detect if there is a copper PHY attached. */
1491 switch (hw->device_id) {
1492 case IXGBE_DEV_ID_X550EM_X_KR:
1493 case IXGBE_DEV_ID_X550EM_X_KX4:
1494 case IXGBE_DEV_ID_X550EM_A_KR:
1495 case IXGBE_DEV_ID_X550EM_A_KR_L:
1496 media_type = ixgbe_media_type_backplane;
1498 case IXGBE_DEV_ID_X550EM_X_SFP:
1499 case IXGBE_DEV_ID_X550EM_A_SFP:
1500 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1501 case IXGBE_DEV_ID_X550EM_A_QSFP:
1502 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1503 media_type = ixgbe_media_type_fiber;
1505 case IXGBE_DEV_ID_X550EM_X_1G_T:
1506 case IXGBE_DEV_ID_X550EM_X_10G_T:
1507 case IXGBE_DEV_ID_X550EM_A_10G_T:
1508 media_type = ixgbe_media_type_copper;
1510 case IXGBE_DEV_ID_X550EM_A_SGMII:
1511 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1512 media_type = ixgbe_media_type_backplane;
1513 hw->phy.type = ixgbe_phy_sgmii;
1515 case IXGBE_DEV_ID_X550EM_A_1G_T:
1516 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1517 media_type = ixgbe_media_type_copper;
1520 media_type = ixgbe_media_type_unknown;
1527 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1528 * @hw: pointer to hardware structure
1529 * @linear: true if SFP module is linear
1531 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1533 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1535 switch (hw->phy.sfp_type) {
1536 case ixgbe_sfp_type_not_present:
1537 return IXGBE_ERR_SFP_NOT_PRESENT;
1538 case ixgbe_sfp_type_da_cu_core0:
1539 case ixgbe_sfp_type_da_cu_core1:
1542 case ixgbe_sfp_type_srlr_core0:
1543 case ixgbe_sfp_type_srlr_core1:
1544 case ixgbe_sfp_type_da_act_lmt_core0:
1545 case ixgbe_sfp_type_da_act_lmt_core1:
1546 case ixgbe_sfp_type_1g_sx_core0:
1547 case ixgbe_sfp_type_1g_sx_core1:
1548 case ixgbe_sfp_type_1g_lx_core0:
1549 case ixgbe_sfp_type_1g_lx_core1:
1552 case ixgbe_sfp_type_unknown:
1553 case ixgbe_sfp_type_1g_cu_core0:
1554 case ixgbe_sfp_type_1g_cu_core1:
1556 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1559 return IXGBE_SUCCESS;
1563 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1564 * @hw: pointer to hardware structure
1566 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1568 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1573 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1575 status = ixgbe_identify_module_generic(hw);
1577 if (status != IXGBE_SUCCESS)
1580 /* Check if SFP module is supported */
1581 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1587 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1588 * @hw: pointer to hardware structure
1590 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1595 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1597 /* Check if SFP module is supported */
1598 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1600 if (status != IXGBE_SUCCESS)
1603 ixgbe_init_mac_link_ops_X550em(hw);
1604 hw->phy.ops.reset = NULL;
1606 return IXGBE_SUCCESS;
1610 * ixgbe_setup_sgmii - Set up link for sgmii
1611 * @hw: pointer to hardware structure
1613 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1616 struct ixgbe_mac_info *mac = &hw->mac;
1620 rc = mac->ops.read_iosf_sb_reg(hw,
1621 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1622 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1626 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1627 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1628 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1629 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1630 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1631 rc = mac->ops.write_iosf_sb_reg(hw,
1632 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1633 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1637 rc = mac->ops.read_iosf_sb_reg(hw,
1638 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1639 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1643 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1644 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1645 rc = mac->ops.write_iosf_sb_reg(hw,
1646 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1647 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1651 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1652 rc = mac->ops.write_iosf_sb_reg(hw,
1653 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1654 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1658 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1662 * ixgbe_setup_sgmii_m88 - Set up link for sgmii with Marvell PHYs
1663 * @hw: pointer to hardware structure
1665 STATIC s32 ixgbe_setup_sgmii_m88(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1668 struct ixgbe_mac_info *mac = &hw->mac;
1672 rc = mac->ops.read_iosf_sb_reg(hw,
1673 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1674 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1678 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1679 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1680 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1681 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1682 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1683 rc = mac->ops.write_iosf_sb_reg(hw,
1684 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1685 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1689 rc = mac->ops.read_iosf_sb_reg(hw,
1690 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1691 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1695 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1696 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1697 rc = mac->ops.write_iosf_sb_reg(hw,
1698 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1699 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1703 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1704 rc = mac->ops.write_iosf_sb_reg(hw,
1705 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1706 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1710 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1714 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1715 * @hw: pointer to hardware structure
1717 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1719 struct ixgbe_mac_info *mac = &hw->mac;
1721 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1723 switch (hw->mac.ops.get_media_type(hw)) {
1724 case ixgbe_media_type_fiber:
1725 /* CS4227 does not support autoneg, so disable the laser control
1726 * functions for SFP+ fiber
1728 mac->ops.disable_tx_laser = NULL;
1729 mac->ops.enable_tx_laser = NULL;
1730 mac->ops.flap_tx_laser = NULL;
1731 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1732 mac->ops.set_rate_select_speed =
1733 ixgbe_set_soft_rate_select_speed;
1734 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1735 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1736 mac->ops.setup_mac_link =
1737 ixgbe_setup_mac_link_sfp_x550a;
1739 mac->ops.setup_mac_link =
1740 ixgbe_setup_mac_link_sfp_x550em;
1742 case ixgbe_media_type_copper:
1743 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1744 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1745 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1746 mac->ops.setup_link = ixgbe_setup_sgmii_m88;
1748 mac->ops.setup_link =
1749 ixgbe_setup_mac_link_t_X550em;
1752 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1753 mac->ops.check_link = ixgbe_check_link_t_X550em;
1756 case ixgbe_media_type_backplane:
1757 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1758 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1759 mac->ops.setup_link = ixgbe_setup_sgmii;
1767 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1768 * @hw: pointer to hardware structure
1769 * @speed: pointer to link speed
1770 * @autoneg: true when autoneg or autotry is enabled
1772 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1773 ixgbe_link_speed *speed,
1776 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1779 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1781 /* CS4227 SFP must not enable auto-negotiation */
1784 /* Check if 1G SFP module. */
1785 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1786 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1787 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1788 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1789 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1790 return IXGBE_SUCCESS;
1793 /* Link capabilities are based on SFP */
1794 if (hw->phy.multispeed_fiber)
1795 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1796 IXGBE_LINK_SPEED_1GB_FULL;
1798 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1800 switch (hw->phy.type) {
1802 *speed = IXGBE_LINK_SPEED_1GB_FULL |
1803 IXGBE_LINK_SPEED_100_FULL |
1804 IXGBE_LINK_SPEED_10_FULL;
1806 case ixgbe_phy_sgmii:
1807 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1810 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1811 IXGBE_LINK_SPEED_1GB_FULL;
1817 return IXGBE_SUCCESS;
1821 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1822 * @hw: pointer to hardware structure
1823 * @lsc: pointer to boolean flag which indicates whether external Base T
1824 * PHY interrupt is lsc
1826 * Determime if external Base T PHY interrupt cause is high temperature
1827 * failure alarm or link status change.
1829 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1830 * failure alarm, else return PHY access status.
1832 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1839 /* Vendor alarm triggered */
1840 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1841 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1844 if (status != IXGBE_SUCCESS ||
1845 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1848 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1849 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1850 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1853 if (status != IXGBE_SUCCESS ||
1854 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1855 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1858 /* Global alarm triggered */
1859 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1860 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1863 if (status != IXGBE_SUCCESS)
1866 /* If high temperature failure, then return over temp error and exit */
1867 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1868 /* power down the PHY in case the PHY FW didn't already */
1869 ixgbe_set_copper_phy_power(hw, false);
1870 return IXGBE_ERR_OVERTEMP;
1871 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1872 /* device fault alarm triggered */
1873 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1874 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1877 if (status != IXGBE_SUCCESS)
1880 /* if device fault was due to high temp alarm handle and exit */
1881 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1882 /* power down the PHY in case the PHY FW didn't */
1883 ixgbe_set_copper_phy_power(hw, false);
1884 return IXGBE_ERR_OVERTEMP;
1888 /* Vendor alarm 2 triggered */
1889 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1890 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1892 if (status != IXGBE_SUCCESS ||
1893 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1896 /* link connect/disconnect event occurred */
1897 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1898 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1900 if (status != IXGBE_SUCCESS)
1904 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1907 return IXGBE_SUCCESS;
1911 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1912 * @hw: pointer to hardware structure
1914 * Enable link status change and temperature failure alarm for the external
1917 * Returns PHY access status
1919 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1925 /* Clear interrupt flags */
1926 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1928 /* Enable link status change alarm */
1929 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1930 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1932 if (status != IXGBE_SUCCESS)
1935 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1937 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1938 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1940 if (status != IXGBE_SUCCESS)
1943 /* Enable high temperature failure and global fault alarms */
1944 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1945 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1948 if (status != IXGBE_SUCCESS)
1951 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1952 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1954 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1955 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1958 if (status != IXGBE_SUCCESS)
1961 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1962 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1963 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1966 if (status != IXGBE_SUCCESS)
1969 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1970 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1972 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1973 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1976 if (status != IXGBE_SUCCESS)
1979 /* Enable chip-wide vendor alarm */
1980 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1981 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1984 if (status != IXGBE_SUCCESS)
1987 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1989 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1990 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1997 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1998 * @hw: pointer to hardware structure
1999 * @speed: link speed
2001 * Configures the integrated KR PHY.
2003 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2004 ixgbe_link_speed speed)
2009 status = hw->mac.ops.read_iosf_sb_reg(hw,
2010 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2011 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2015 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2016 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2017 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2019 /* Advertise 10G support. */
2020 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2021 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2023 /* Advertise 1G support. */
2024 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2025 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2027 /* Restart auto-negotiation. */
2028 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2029 status = hw->mac.ops.write_iosf_sb_reg(hw,
2030 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2031 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2037 * ixgbe_setup_m88 - setup m88 PHY
2038 * @hw: pointer to hardware structure
2040 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2042 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2046 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2047 return IXGBE_SUCCESS;
2049 rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2053 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2056 if (reg & IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN) {
2057 reg &= ~IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN;
2058 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2062 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, ®);
2065 if (reg & IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN) {
2066 reg &= ~IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN;
2067 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0,
2071 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 2);
2075 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2079 if (reg & IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN) {
2080 reg &= ~IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN;
2081 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2083 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2087 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2091 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2092 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2096 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2102 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2106 if (!(reg & IXGBE_M88E1500_COPPER_CTRL_AN_EN)) {
2107 reg |= IXGBE_M88E1500_COPPER_CTRL_AN_EN;
2108 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2112 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, ®);
2115 reg &= ~IXGBE_M88E1500_1000T_CTRL_HALF_DUPLEX;
2116 reg &= ~IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2117 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
2118 reg |= IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2119 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, reg);
2121 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, ®);
2124 reg &= ~IXGBE_M88E1500_COPPER_AN_T4;
2125 reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_FD;
2126 reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_HD;
2127 reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_FD;
2128 reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_HD;
2130 /* Flow control auto negotiation configuration was moved from here to
2131 * the function ixgbe_setup_fc_sgmii_x550em_a()
2134 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
2135 reg |= IXGBE_M88E1500_COPPER_AN_100TX_FD;
2136 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
2137 reg |= IXGBE_M88E1500_COPPER_AN_10TX_FD;
2138 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, reg);
2140 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2143 reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
2144 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2147 hw->mac.ops.release_swfw_sync(hw, mask);
2151 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2152 hw->mac.ops.release_swfw_sync(hw, mask);
2157 * ixgbe_reset_phy_m88e1500 - Reset m88e1500 PHY
2158 * @hw: pointer to hardware structure
2160 * The PHY token must be held when calling this function.
2162 static s32 ixgbe_reset_phy_m88e1500(struct ixgbe_hw *hw)
2167 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2171 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2175 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2176 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2184 * ixgbe_reset_phy_m88e1543 - Reset m88e1543 PHY
2185 * @hw: pointer to hardware structure
2187 * The PHY token must be held when calling this function.
2189 static s32 ixgbe_reset_phy_m88e1543(struct ixgbe_hw *hw)
2191 return hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2195 * ixgbe_reset_phy_m88 - Reset m88 PHY
2196 * @hw: pointer to hardware structure
2198 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2200 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2204 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2205 return IXGBE_SUCCESS;
2207 rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2211 switch (hw->phy.id) {
2212 case IXGBE_M88E1500_E_PHY_ID:
2213 rc = ixgbe_reset_phy_m88e1500(hw);
2215 case IXGBE_M88E1543_E_PHY_ID:
2216 rc = ixgbe_reset_phy_m88e1543(hw);
2223 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2227 reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2228 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2229 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2230 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2234 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2238 reg = IXGBE_M88E1500_GEN_CTRL_RESET |
2239 IXGBE_M88E1500_GEN_CTRL_MODE_SGMII_COPPER;
2240 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_GEN_CTRL, 0, reg);
2244 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2248 reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2249 IXGBE_M88E1500_FIBER_CTRL_AN_EN |
2250 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2251 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2252 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2256 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2260 reg = (IXGBE_M88E1500_MAC_CTRL_1_DWN_4X <<
2261 IXGBE_M88E1500_MAC_CTRL_1_DWN_SHIFT) |
2262 (IXGBE_M88E1500_MAC_CTRL_1_ED_TM <<
2263 IXGBE_M88E1500_MAC_CTRL_1_ED_SHIFT) |
2264 (IXGBE_M88E1500_MAC_CTRL_1_MDIX_AUTO <<
2265 IXGBE_M88E1500_MAC_CTRL_1_MDIX_SHIFT);
2266 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, reg);
2270 reg = IXGBE_M88E1500_COPPER_CTRL_RESET |
2271 IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2272 IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2273 IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2274 IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB;
2275 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2279 hw->mac.ops.release_swfw_sync(hw, mask);
2281 /* In case of first reset set advertised speeds to default value */
2282 if (!hw->phy.autoneg_advertised)
2283 hw->phy.autoneg_advertised = IXGBE_LINK_SPEED_1GB_FULL |
2284 IXGBE_LINK_SPEED_100_FULL |
2285 IXGBE_LINK_SPEED_10_FULL;
2287 return ixgbe_setup_m88(hw);
2290 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2291 hw->mac.ops.release_swfw_sync(hw, mask);
2296 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2297 * @hw: pointer to hardware structure
2299 * Read NW_MNG_IF_SEL register and save field values, and check for valid field
2302 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2304 /* Save NW management interface connected on board. This is used
2305 * to determine internal PHY mode.
2307 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2309 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2310 * PHY address. This register field was has only been used for X552.
2312 if (hw->mac.type == ixgbe_mac_X550EM_a &&
2313 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2314 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2315 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2316 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2319 return IXGBE_SUCCESS;
2323 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2324 * @hw: pointer to hardware structure
2326 * Initialize any function pointers that were not able to be
2327 * set during init_shared_code because the PHY/SFP type was
2328 * not known. Perform the SFP init if necessary.
2330 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2332 struct ixgbe_phy_info *phy = &hw->phy;
2335 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2337 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2338 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2339 ixgbe_setup_mux_ctl(hw);
2340 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2343 switch (hw->device_id) {
2344 case IXGBE_DEV_ID_X550EM_A_1G_T:
2345 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2346 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2347 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2348 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2349 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2351 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2353 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2356 case IXGBE_DEV_ID_X550EM_A_10G_T:
2357 case IXGBE_DEV_ID_X550EM_A_SFP:
2358 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2359 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2361 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2363 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2365 case IXGBE_DEV_ID_X550EM_X_SFP:
2366 /* set up for CS4227 usage */
2367 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2373 /* Identify the PHY or SFP module */
2374 ret_val = phy->ops.identify(hw);
2375 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2378 /* Setup function pointers based on detected hardware */
2379 ixgbe_init_mac_link_ops_X550em(hw);
2380 if (phy->sfp_type != ixgbe_sfp_type_unknown)
2381 phy->ops.reset = NULL;
2383 /* Set functions pointers based on phy type */
2384 switch (hw->phy.type) {
2385 case ixgbe_phy_x550em_kx4:
2386 phy->ops.setup_link = NULL;
2387 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2388 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2390 case ixgbe_phy_x550em_kr:
2391 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2392 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2393 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2395 case ixgbe_phy_x550em_ext_t:
2396 /* If internal link mode is XFI, then setup iXFI internal link,
2397 * else setup KR now.
2399 phy->ops.setup_internal_link =
2400 ixgbe_setup_internal_phy_t_x550em;
2402 /* setup SW LPLU only for first revision of X550EM_x */
2403 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2404 !(IXGBE_FUSES0_REV_MASK &
2405 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2406 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2408 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2409 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2411 case ixgbe_phy_sgmii:
2412 phy->ops.setup_link = NULL;
2415 phy->ops.setup_link = ixgbe_setup_m88;
2416 phy->ops.reset = ixgbe_reset_phy_m88;
2425 * ixgbe_set_mdio_speed - Set MDIO clock speed
2426 * @hw: pointer to hardware structure
2428 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2432 switch (hw->device_id) {
2433 case IXGBE_DEV_ID_X550EM_X_10G_T:
2434 case IXGBE_DEV_ID_X550EM_A_SGMII:
2435 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2436 case IXGBE_DEV_ID_X550EM_A_1G_T:
2437 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2438 case IXGBE_DEV_ID_X550EM_A_10G_T:
2439 case IXGBE_DEV_ID_X550EM_A_SFP:
2440 case IXGBE_DEV_ID_X550EM_A_QSFP:
2441 /* Config MDIO clock speed before the first MDIO PHY access */
2442 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2443 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2444 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2452 * ixgbe_reset_hw_X550em - Perform hardware reset
2453 * @hw: pointer to hardware structure
2455 * Resets the hardware by resetting the transmit and receive units, masks
2456 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2459 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2461 ixgbe_link_speed link_speed;
2465 bool link_up = false;
2467 DEBUGFUNC("ixgbe_reset_hw_X550em");
2469 /* Call adapter stop to disable Tx/Rx and clear interrupts */
2470 status = hw->mac.ops.stop_adapter(hw);
2471 if (status != IXGBE_SUCCESS)
2474 /* flush pending Tx transactions */
2475 ixgbe_clear_tx_pending(hw);
2477 ixgbe_set_mdio_speed(hw);
2479 /* PHY ops must be identified and initialized prior to reset */
2480 status = hw->phy.ops.init(hw);
2482 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2485 /* start the external PHY */
2486 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2487 status = ixgbe_init_ext_t_x550em(hw);
2492 /* Setup SFP module if there is one present. */
2493 if (hw->phy.sfp_setup_needed) {
2494 status = hw->mac.ops.setup_sfp(hw);
2495 hw->phy.sfp_setup_needed = false;
2498 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2502 if (!hw->phy.reset_disable && hw->phy.ops.reset)
2503 hw->phy.ops.reset(hw);
2506 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
2507 * If link reset is used when link is up, it might reset the PHY when
2508 * mng is using it. If link is down or the flag to force full link
2509 * reset is set, then perform link reset.
2511 ctrl = IXGBE_CTRL_LNK_RST;
2512 if (!hw->force_full_reset) {
2513 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2515 ctrl = IXGBE_CTRL_RST;
2518 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2519 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2520 IXGBE_WRITE_FLUSH(hw);
2522 /* Poll for reset bit to self-clear meaning reset is complete */
2523 for (i = 0; i < 10; i++) {
2525 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2526 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2530 if (ctrl & IXGBE_CTRL_RST_MASK) {
2531 status = IXGBE_ERR_RESET_FAILED;
2532 DEBUGOUT("Reset polling failed to complete.\n");
2537 /* Double resets are required for recovery from certain error
2538 * conditions. Between resets, it is necessary to stall to
2539 * allow time for any pending HW events to complete.
2541 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2542 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2546 /* Store the permanent mac address */
2547 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2549 /* Store MAC address from RAR0, clear receive address registers, and
2550 * clear the multicast table. Also reset num_rar_entries to 128,
2551 * since we modify this value when programming the SAN MAC address.
2553 hw->mac.num_rar_entries = 128;
2554 hw->mac.ops.init_rx_addrs(hw);
2556 ixgbe_set_mdio_speed(hw);
2558 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2559 ixgbe_setup_mux_ctl(hw);
2565 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2566 * @hw: pointer to hardware structure
2568 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2573 status = hw->phy.ops.read_reg(hw,
2574 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2575 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2578 if (status != IXGBE_SUCCESS)
2581 /* If PHY FW reset completed bit is set then this is the first
2582 * SW instance after a power on so the PHY FW must be un-stalled.
2584 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2585 status = hw->phy.ops.read_reg(hw,
2586 IXGBE_MDIO_GLOBAL_RES_PR_10,
2587 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2590 if (status != IXGBE_SUCCESS)
2593 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2595 status = hw->phy.ops.write_reg(hw,
2596 IXGBE_MDIO_GLOBAL_RES_PR_10,
2597 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2600 if (status != IXGBE_SUCCESS)
2608 * ixgbe_setup_kr_x550em - Configure the KR PHY.
2609 * @hw: pointer to hardware structure
2611 * Configures the integrated KR PHY for X550EM_x.
2613 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2615 if (hw->mac.type != ixgbe_mac_X550EM_x)
2616 return IXGBE_SUCCESS;
2618 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2622 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2623 * @hw: pointer to hardware structure
2625 * Configure the external PHY and the integrated KR PHY for SFP support.
2627 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2628 ixgbe_link_speed speed,
2629 bool autoneg_wait_to_complete)
2632 u16 reg_slice, reg_val;
2633 bool setup_linear = false;
2634 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2636 /* Check if SFP module is supported and linear */
2637 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2639 /* If no SFP module present, then return success. Return success since
2640 * there is no reason to configure CS4227 and SFP not present error is
2641 * not excepted in the setup MAC link flow.
2643 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2644 return IXGBE_SUCCESS;
2646 if (ret_val != IXGBE_SUCCESS)
2649 /* Configure internal PHY for KR/KX. */
2650 ixgbe_setup_kr_speed_x550em(hw, speed);
2652 /* Configure CS4227 LINE side to proper mode. */
2653 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2654 (hw->bus.lan_id << 12);
2656 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2658 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2659 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2665 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2666 * @hw: pointer to hardware structure
2668 * Configure the the integrated PHY for SFP support.
2670 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2671 ixgbe_link_speed speed,
2672 bool autoneg_wait_to_complete)
2676 bool setup_linear = false;
2677 u32 reg_slice, reg_phy_int, slice_offset;
2679 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2681 /* Check if SFP module is supported and linear */
2682 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2684 /* If no SFP module present, then return success. Return success since
2685 * SFP not present error is not excepted in the setup MAC link flow.
2687 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2688 return IXGBE_SUCCESS;
2690 if (ret_val != IXGBE_SUCCESS)
2693 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2694 /* Configure internal PHY for native SFI */
2695 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2696 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2697 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
2699 if (ret_val != IXGBE_SUCCESS)
2703 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2704 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2706 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2707 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2710 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2711 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2712 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2714 if (ret_val != IXGBE_SUCCESS)
2717 /* Setup XFI/SFI internal link. */
2718 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2720 /* Configure internal PHY for KR/KX. */
2721 ixgbe_setup_kr_speed_x550em(hw, speed);
2723 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2725 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2726 return IXGBE_ERR_PHY_ADDR_INVALID;
2729 /* Get external PHY device id */
2730 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2731 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2733 if (ret_val != IXGBE_SUCCESS)
2736 /* When configuring quad port CS4223, the MAC instance is part
2737 * of the slice offset.
2739 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2740 slice_offset = (hw->bus.lan_id +
2741 (hw->bus.instance_id << 1)) << 12;
2743 slice_offset = hw->bus.lan_id << 12;
2745 /* Configure CS4227/CS4223 LINE side to proper mode. */
2746 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2748 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2750 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2751 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2752 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2758 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2759 * @hw: pointer to hardware structure
2761 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2763 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2765 struct ixgbe_mac_info *mac = &hw->mac;
2769 /* Disable training protocol FSM. */
2770 status = mac->ops.read_iosf_sb_reg(hw,
2771 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2772 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2773 if (status != IXGBE_SUCCESS)
2775 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2776 status = mac->ops.write_iosf_sb_reg(hw,
2777 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2778 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2779 if (status != IXGBE_SUCCESS)
2782 /* Disable Flex from training TXFFE. */
2783 status = mac->ops.read_iosf_sb_reg(hw,
2784 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2785 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2786 if (status != IXGBE_SUCCESS)
2788 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2789 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2790 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2791 status = mac->ops.write_iosf_sb_reg(hw,
2792 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2793 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2794 if (status != IXGBE_SUCCESS)
2796 status = mac->ops.read_iosf_sb_reg(hw,
2797 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2798 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2799 if (status != IXGBE_SUCCESS)
2801 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2802 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2803 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2804 status = mac->ops.write_iosf_sb_reg(hw,
2805 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2806 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2807 if (status != IXGBE_SUCCESS)
2810 /* Enable override for coefficients. */
2811 status = mac->ops.read_iosf_sb_reg(hw,
2812 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2813 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2814 if (status != IXGBE_SUCCESS)
2816 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2817 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2818 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2819 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2820 status = mac->ops.write_iosf_sb_reg(hw,
2821 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2822 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2827 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2828 * @hw: pointer to hardware structure
2829 * @speed: the link speed to force
2831 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
2832 * internal and external PHY at a specific speed, without autonegotiation.
2834 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2836 struct ixgbe_mac_info *mac = &hw->mac;
2840 /* Disable AN and force speed to 10G Serial. */
2841 status = mac->ops.read_iosf_sb_reg(hw,
2842 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2843 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2844 if (status != IXGBE_SUCCESS)
2847 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2848 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2850 /* Select forced link speed for internal PHY. */
2852 case IXGBE_LINK_SPEED_10GB_FULL:
2853 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2855 case IXGBE_LINK_SPEED_1GB_FULL:
2856 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2859 /* Other link speeds are not supported by internal KR PHY. */
2860 return IXGBE_ERR_LINK_SETUP;
2863 status = mac->ops.write_iosf_sb_reg(hw,
2864 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2865 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2866 if (status != IXGBE_SUCCESS)
2869 /* Additional configuration needed for x550em_x */
2870 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2871 status = ixgbe_setup_ixfi_x550em_x(hw);
2872 if (status != IXGBE_SUCCESS)
2876 /* Toggle port SW reset by AN reset. */
2877 status = mac->ops.read_iosf_sb_reg(hw,
2878 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2879 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2880 if (status != IXGBE_SUCCESS)
2882 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2883 status = mac->ops.write_iosf_sb_reg(hw,
2884 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2885 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2891 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2892 * @hw: address of hardware structure
2893 * @link_up: address of boolean to indicate link status
2895 * Returns error code if unable to get link status.
2897 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2904 /* read this twice back to back to indicate current status */
2905 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2906 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2908 if (ret != IXGBE_SUCCESS)
2911 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2912 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2914 if (ret != IXGBE_SUCCESS)
2917 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2919 return IXGBE_SUCCESS;
2923 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2924 * @hw: point to hardware structure
2926 * Configures the link between the integrated KR PHY and the external X557 PHY
2927 * The driver will call this function when it gets a link status change
2928 * interrupt from the X557 PHY. This function configures the link speed
2929 * between the PHYs to match the link speed of the BASE-T link.
2931 * A return of a non-zero value indicates an error, and the base driver should
2932 * not report link up.
2934 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2936 ixgbe_link_speed force_speed;
2941 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2942 return IXGBE_ERR_CONFIG;
2944 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2945 /* If link is down, there is no setup necessary so return */
2946 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2947 if (status != IXGBE_SUCCESS)
2951 return IXGBE_SUCCESS;
2953 status = hw->phy.ops.read_reg(hw,
2954 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2955 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2957 if (status != IXGBE_SUCCESS)
2960 /* If link is still down - no setup is required so return */
2961 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2962 if (status != IXGBE_SUCCESS)
2965 return IXGBE_SUCCESS;
2967 /* clear everything but the speed and duplex bits */
2968 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2971 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2972 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2974 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2975 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2978 /* Internal PHY does not support anything else */
2979 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2982 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2984 speed = IXGBE_LINK_SPEED_10GB_FULL |
2985 IXGBE_LINK_SPEED_1GB_FULL;
2986 return ixgbe_setup_kr_speed_x550em(hw, speed);
2991 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2992 * @hw: pointer to hardware structure
2994 * Configures the integrated KR PHY to use internal loopback mode.
2996 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3001 /* Disable AN and force speed to 10G Serial. */
3002 status = hw->mac.ops.read_iosf_sb_reg(hw,
3003 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3004 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3005 if (status != IXGBE_SUCCESS)
3007 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3008 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3009 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3010 status = hw->mac.ops.write_iosf_sb_reg(hw,
3011 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3012 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3013 if (status != IXGBE_SUCCESS)
3016 /* Set near-end loopback clocks. */
3017 status = hw->mac.ops.read_iosf_sb_reg(hw,
3018 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3019 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3020 if (status != IXGBE_SUCCESS)
3022 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3023 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3024 status = hw->mac.ops.write_iosf_sb_reg(hw,
3025 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3026 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3027 if (status != IXGBE_SUCCESS)
3030 /* Set loopback enable. */
3031 status = hw->mac.ops.read_iosf_sb_reg(hw,
3032 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3033 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3034 if (status != IXGBE_SUCCESS)
3036 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3037 status = hw->mac.ops.write_iosf_sb_reg(hw,
3038 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3039 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3040 if (status != IXGBE_SUCCESS)
3043 /* Training bypass. */
3044 status = hw->mac.ops.read_iosf_sb_reg(hw,
3045 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3046 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3047 if (status != IXGBE_SUCCESS)
3049 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3050 status = hw->mac.ops.write_iosf_sb_reg(hw,
3051 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3052 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3058 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3059 * assuming that the semaphore is already obtained.
3060 * @hw: pointer to hardware structure
3061 * @offset: offset of word in the EEPROM to read
3062 * @data: word read from the EEPROM
3064 * Reads a 16 bit word from the EEPROM using the hostif.
3066 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3070 struct ixgbe_hic_read_shadow_ram buffer;
3072 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
3073 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3074 buffer.hdr.req.buf_lenh = 0;
3075 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3076 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3078 /* convert offset from words to bytes */
3079 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3081 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3083 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3085 IXGBE_HI_COMMAND_TIMEOUT, false);
3090 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3091 FW_NVM_DATA_OFFSET);
3097 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3098 * @hw: pointer to hardware structure
3099 * @offset: offset of word in the EEPROM to read
3100 * @data: word read from the EEPROM
3102 * Reads a 16 bit word from the EEPROM using the hostif.
3104 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3107 s32 status = IXGBE_SUCCESS;
3109 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3111 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3113 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
3114 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3116 status = IXGBE_ERR_SWFW_SYNC;
3123 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3124 * @hw: pointer to hardware structure
3125 * @offset: offset of word in the EEPROM to read
3126 * @words: number of words
3127 * @data: word(s) read from the EEPROM
3129 * Reads a 16 bit word(s) from the EEPROM using the hostif.
3131 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3132 u16 offset, u16 words, u16 *data)
3134 struct ixgbe_hic_read_shadow_ram buffer;
3135 u32 current_word = 0;
3140 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3142 /* Take semaphore for the entire operation. */
3143 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3145 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3149 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3150 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3152 words_to_read = words;
3154 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3155 buffer.hdr.req.buf_lenh = 0;
3156 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3157 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3159 /* convert offset from words to bytes */
3160 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3161 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3163 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3165 IXGBE_HI_COMMAND_TIMEOUT,
3169 DEBUGOUT("Host interface command failed\n");
3173 for (i = 0; i < words_to_read; i++) {
3174 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3176 u32 value = IXGBE_READ_REG(hw, reg);
3178 data[current_word] = (u16)(value & 0xffff);
3181 if (i < words_to_read) {
3183 data[current_word] = (u16)(value & 0xffff);
3187 words -= words_to_read;
3191 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3196 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3197 * @hw: pointer to hardware structure
3198 * @offset: offset of word in the EEPROM to write
3199 * @data: word write to the EEPROM
3201 * Write a 16 bit word to the EEPROM using the hostif.
3203 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3207 struct ixgbe_hic_write_shadow_ram buffer;
3209 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3211 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3212 buffer.hdr.req.buf_lenh = 0;
3213 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3214 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3217 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3219 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3221 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3223 IXGBE_HI_COMMAND_TIMEOUT, false);
3229 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3230 * @hw: pointer to hardware structure
3231 * @offset: offset of word in the EEPROM to write
3232 * @data: word write to the EEPROM
3234 * Write a 16 bit word to the EEPROM using the hostif.
3236 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3239 s32 status = IXGBE_SUCCESS;
3241 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3243 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3245 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3246 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3248 DEBUGOUT("write ee hostif failed to get semaphore");
3249 status = IXGBE_ERR_SWFW_SYNC;
3256 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3257 * @hw: pointer to hardware structure
3258 * @offset: offset of word in the EEPROM to write
3259 * @words: number of words
3260 * @data: word(s) write to the EEPROM
3262 * Write a 16 bit word(s) to the EEPROM using the hostif.
3264 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3265 u16 offset, u16 words, u16 *data)
3267 s32 status = IXGBE_SUCCESS;
3270 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3272 /* Take semaphore for the entire operation. */
3273 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3274 if (status != IXGBE_SUCCESS) {
3275 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3279 for (i = 0; i < words; i++) {
3280 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3283 if (status != IXGBE_SUCCESS) {
3284 DEBUGOUT("Eeprom buffered write failed\n");
3289 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3296 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3297 * @hw: pointer to hardware structure
3298 * @ptr: pointer offset in eeprom
3299 * @size: size of section pointed by ptr, if 0 first word will be used as size
3300 * @csum: address of checksum to update
3302 * Returns error status for any failure
3304 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3305 u16 size, u16 *csum, u16 *buffer,
3310 u16 length, bufsz, i, start;
3313 bufsz = sizeof(buf) / sizeof(buf[0]);
3315 /* Read a chunk at the pointer location */
3317 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3319 DEBUGOUT("Failed to read EEPROM image\n");
3324 if (buffer_size < ptr)
3325 return IXGBE_ERR_PARAM;
3326 local_buffer = &buffer[ptr];
3334 length = local_buffer[0];
3336 /* Skip pointer section if length is invalid. */
3337 if (length == 0xFFFF || length == 0 ||
3338 (ptr + length) >= hw->eeprom.word_size)
3339 return IXGBE_SUCCESS;
3342 if (buffer && ((u32)start + (u32)length > buffer_size))
3343 return IXGBE_ERR_PARAM;
3345 for (i = start; length; i++, length--) {
3346 if (i == bufsz && !buffer) {
3352 /* Read a chunk at the pointer location */
3353 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3356 DEBUGOUT("Failed to read EEPROM image\n");
3360 *csum += local_buffer[i];
3362 return IXGBE_SUCCESS;
3366 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3367 * @hw: pointer to hardware structure
3368 * @buffer: pointer to buffer containing calculated checksum
3369 * @buffer_size: size of buffer
3371 * Returns a negative error code on error, or the 16-bit checksum
3373 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3375 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3379 u16 pointer, i, size;
3381 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3383 hw->eeprom.ops.init_params(hw);
3386 /* Read pointer area */
3387 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3388 IXGBE_EEPROM_LAST_WORD + 1,
3391 DEBUGOUT("Failed to read EEPROM image\n");
3394 local_buffer = eeprom_ptrs;
3396 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3397 return IXGBE_ERR_PARAM;
3398 local_buffer = buffer;
3402 * For X550 hardware include 0x0-0x41 in the checksum, skip the
3403 * checksum word itself
3405 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3406 if (i != IXGBE_EEPROM_CHECKSUM)
3407 checksum += local_buffer[i];
3410 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
3411 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3413 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3414 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3417 pointer = local_buffer[i];
3419 /* Skip pointer section if the pointer is invalid. */
3420 if (pointer == 0xFFFF || pointer == 0 ||
3421 pointer >= hw->eeprom.word_size)
3425 case IXGBE_PCIE_GENERAL_PTR:
3426 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3428 case IXGBE_PCIE_CONFIG0_PTR:
3429 case IXGBE_PCIE_CONFIG1_PTR:
3430 size = IXGBE_PCIE_CONFIG_SIZE;
3437 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3438 buffer, buffer_size);
3443 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3445 return (s32)checksum;
3449 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3450 * @hw: pointer to hardware structure
3452 * Returns a negative error code on error, or the 16-bit checksum
3454 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3456 return ixgbe_calc_checksum_X550(hw, NULL, 0);
3460 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3461 * @hw: pointer to hardware structure
3462 * @checksum_val: calculated checksum
3464 * Performs checksum calculation and validates the EEPROM checksum. If the
3465 * caller does not need checksum_val, the value can be NULL.
3467 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3471 u16 read_checksum = 0;
3473 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3475 /* Read the first word from the EEPROM. If this times out or fails, do
3476 * not continue or we could be in for a very long wait while every
3479 status = hw->eeprom.ops.read(hw, 0, &checksum);
3481 DEBUGOUT("EEPROM read failed\n");
3485 status = hw->eeprom.ops.calc_checksum(hw);
3489 checksum = (u16)(status & 0xffff);
3491 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3496 /* Verify read checksum from EEPROM is the same as
3497 * calculated checksum
3499 if (read_checksum != checksum) {
3500 status = IXGBE_ERR_EEPROM_CHECKSUM;
3501 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3502 "Invalid EEPROM checksum");
3505 /* If the user cares, return the calculated checksum */
3507 *checksum_val = checksum;
3513 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3514 * @hw: pointer to hardware structure
3516 * After writing EEPROM to shadow RAM using EEWR register, software calculates
3517 * checksum and updates the EEPROM and instructs the hardware to update
3520 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3525 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3527 /* Read the first word from the EEPROM. If this times out or fails, do
3528 * not continue or we could be in for a very long wait while every
3531 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3533 DEBUGOUT("EEPROM read failed\n");
3537 status = ixgbe_calc_eeprom_checksum_X550(hw);
3541 checksum = (u16)(status & 0xffff);
3543 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3548 status = ixgbe_update_flash_X550(hw);
3554 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3555 * @hw: pointer to hardware structure
3557 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3559 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3561 s32 status = IXGBE_SUCCESS;
3562 union ixgbe_hic_hdr2 buffer;
3564 DEBUGFUNC("ixgbe_update_flash_X550");
3566 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3567 buffer.req.buf_lenh = 0;
3568 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3569 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3571 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3573 IXGBE_HI_COMMAND_TIMEOUT, false);
3579 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3580 * @hw: pointer to hardware structure
3582 * Determines physical layer capabilities of the current configuration.
3584 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3586 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3587 u16 ext_ability = 0;
3589 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3591 hw->phy.ops.identify(hw);
3593 switch (hw->phy.type) {
3594 case ixgbe_phy_x550em_kr:
3595 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3596 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3598 case ixgbe_phy_x550em_kx4:
3599 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3600 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3602 case ixgbe_phy_x550em_ext_t:
3603 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3604 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3606 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3607 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3608 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3609 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3615 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3616 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3618 return physical_layer;
3622 * ixgbe_get_bus_info_x550em - Set PCI bus info
3623 * @hw: pointer to hardware structure
3625 * Sets bus link width and speed to unknown because X550em is
3628 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3631 DEBUGFUNC("ixgbe_get_bus_info_x550em");
3633 hw->bus.width = ixgbe_bus_width_unknown;
3634 hw->bus.speed = ixgbe_bus_speed_unknown;
3636 hw->mac.ops.set_lan_id(hw);
3638 return IXGBE_SUCCESS;
3642 * ixgbe_disable_rx_x550 - Disable RX unit
3644 * Enables the Rx DMA unit for x550
3646 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3648 u32 rxctrl, pfdtxgswc;
3650 struct ixgbe_hic_disable_rxen fw_cmd;
3652 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3654 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3655 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3656 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3657 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3658 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3659 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3660 hw->mac.set_lben = true;
3662 hw->mac.set_lben = false;
3665 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3666 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3667 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3668 fw_cmd.port_number = (u8)hw->bus.lan_id;
3670 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3671 sizeof(struct ixgbe_hic_disable_rxen),
3672 IXGBE_HI_COMMAND_TIMEOUT, true);
3674 /* If we fail - disable RX using register write */
3676 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3677 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3678 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3679 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3686 * ixgbe_enter_lplu_x550em - Transition to low power states
3687 * @hw: pointer to hardware structure
3689 * Configures Low Power Link Up on transition to low power states
3690 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3691 * X557 PHY immediately prior to entering LPLU.
3693 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3695 u16 an_10g_cntl_reg, autoneg_reg, speed;
3697 ixgbe_link_speed lcd_speed;
3701 /* SW LPLU not required on later HW revisions. */
3702 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3703 (IXGBE_FUSES0_REV_MASK &
3704 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3705 return IXGBE_SUCCESS;
3707 /* If blocked by MNG FW, then don't restart AN */
3708 if (ixgbe_check_reset_blocked(hw))
3709 return IXGBE_SUCCESS;
3711 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3712 if (status != IXGBE_SUCCESS)
3715 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3717 if (status != IXGBE_SUCCESS)
3720 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3721 * disabled, then force link down by entering low power mode.
3723 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3724 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3725 return ixgbe_set_copper_phy_power(hw, FALSE);
3728 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3730 if (status != IXGBE_SUCCESS)
3733 /* If no valid LCD link speed, then force link down and exit. */
3734 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3735 return ixgbe_set_copper_phy_power(hw, FALSE);
3737 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3738 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3741 if (status != IXGBE_SUCCESS)
3744 /* If no link now, speed is invalid so take link down */
3745 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3746 if (status != IXGBE_SUCCESS)
3747 return ixgbe_set_copper_phy_power(hw, false);
3749 /* clear everything but the speed bits */
3750 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3752 /* If current speed is already LCD, then exit. */
3753 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3754 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3755 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3756 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3759 /* Clear AN completed indication */
3760 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3761 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3764 if (status != IXGBE_SUCCESS)
3767 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3768 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3771 if (status != IXGBE_SUCCESS)
3774 status = hw->phy.ops.read_reg(hw,
3775 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3776 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3779 if (status != IXGBE_SUCCESS)
3782 save_autoneg = hw->phy.autoneg_advertised;
3784 /* Setup link at least common link speed */
3785 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3787 /* restore autoneg from before setting lplu speed */
3788 hw->phy.autoneg_advertised = save_autoneg;
3794 * ixgbe_get_lcd_x550em - Determine lowest common denominator
3795 * @hw: pointer to hardware structure
3796 * @lcd_speed: pointer to lowest common link speed
3798 * Determine lowest common link speed with link partner.
3800 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3804 u16 word = hw->eeprom.ctrl_word_3;
3806 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3808 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3809 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3812 if (status != IXGBE_SUCCESS)
3815 /* If link partner advertised 1G, return 1G */
3816 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3817 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3821 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3822 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3823 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3826 /* Link partner not capable of lower speeds, return 10G */
3827 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3832 * ixgbe_setup_fc_X550em - Set up flow control
3833 * @hw: pointer to hardware structure
3835 * Called at init time to set up flow control.
3837 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3839 s32 ret_val = IXGBE_SUCCESS;
3840 u32 pause, asm_dir, reg_val;
3842 DEBUGFUNC("ixgbe_setup_fc_X550em");
3844 /* Validate the requested mode */
3845 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3846 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3847 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3848 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3852 /* 10gig parts do not have a word in the EEPROM to determine the
3853 * default flow control setting, so we explicitly set it to full.
3855 if (hw->fc.requested_mode == ixgbe_fc_default)
3856 hw->fc.requested_mode = ixgbe_fc_full;
3858 /* Determine PAUSE and ASM_DIR bits. */
3859 switch (hw->fc.requested_mode) {
3864 case ixgbe_fc_tx_pause:
3868 case ixgbe_fc_rx_pause:
3869 /* Rx Flow control is enabled and Tx Flow control is
3870 * disabled by software override. Since there really
3871 * isn't a way to advertise that we are capable of RX
3872 * Pause ONLY, we will advertise that we support both
3873 * symmetric and asymmetric Rx PAUSE, as such we fall
3874 * through to the fc_full statement. Later, we will
3875 * disable the adapter's ability to send PAUSE frames.
3882 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3883 "Flow control param set incorrectly\n");
3884 ret_val = IXGBE_ERR_CONFIG;
3888 switch (hw->device_id) {
3889 case IXGBE_DEV_ID_X550EM_X_KR:
3890 case IXGBE_DEV_ID_X550EM_A_KR:
3891 case IXGBE_DEV_ID_X550EM_A_KR_L:
3892 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3893 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3894 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3895 if (ret_val != IXGBE_SUCCESS)
3897 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3898 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3900 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3902 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3903 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3904 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3905 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3907 /* This device does not fully support AN. */
3908 hw->fc.disable_fc_autoneg = true;
3919 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
3920 * @hw: pointer to hardware structure
3922 * Enable flow control according to IEEE clause 37.
3924 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
3926 u32 link_s1, lp_an_page_low, an_cntl_1;
3927 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3928 ixgbe_link_speed speed;
3931 /* AN should have completed when the cable was plugged in.
3932 * Look for reasons to bail out. Bail out if:
3933 * - FC autoneg is disabled, or if
3936 if (hw->fc.disable_fc_autoneg) {
3937 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3938 "Flow control autoneg is disabled");
3942 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3944 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3948 /* Check at auto-negotiation has completed */
3949 status = hw->mac.ops.read_iosf_sb_reg(hw,
3950 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
3951 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
3953 if (status != IXGBE_SUCCESS ||
3954 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
3955 DEBUGOUT("Auto-Negotiation did not complete\n");
3956 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3960 /* Read the 10g AN autoc and LP ability registers and resolve
3961 * local flow control settings accordingly
3963 status = hw->mac.ops.read_iosf_sb_reg(hw,
3964 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3965 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
3967 if (status != IXGBE_SUCCESS) {
3968 DEBUGOUT("Auto-Negotiation did not complete\n");
3972 status = hw->mac.ops.read_iosf_sb_reg(hw,
3973 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
3974 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
3976 if (status != IXGBE_SUCCESS) {
3977 DEBUGOUT("Auto-Negotiation did not complete\n");
3981 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
3982 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
3983 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
3984 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
3985 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
3988 if (status == IXGBE_SUCCESS) {
3989 hw->fc.fc_was_autonegged = true;
3991 hw->fc.fc_was_autonegged = false;
3992 hw->fc.current_mode = hw->fc.requested_mode;
3997 * ixgbe_fc_autoneg_fiber_x550em_a - Enable flow control IEEE clause 37
3998 * @hw: pointer to hardware structure
4000 * Enable flow control according to IEEE clause 37.
4002 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4004 u32 link_s1, pcs_an_lp, pcs_an;
4005 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4006 ixgbe_link_speed speed;
4009 /* AN should have completed when the cable was plugged in.
4010 * Look for reasons to bail out. Bail out if:
4011 * - FC autoneg is disabled, or if
4014 if (hw->fc.disable_fc_autoneg) {
4015 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4016 "Flow control autoneg is disabled");
4020 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4022 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4026 /* Check if auto-negotiation has completed */
4027 status = hw->mac.ops.read_iosf_sb_reg(hw,
4028 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4029 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4031 if (status != IXGBE_SUCCESS ||
4032 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4033 DEBUGOUT("Auto-Negotiation did not complete\n");
4034 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4038 /* Determine advertised flow control */
4039 status = hw->mac.ops.read_iosf_sb_reg(hw,
4040 IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4041 IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an);
4043 if (status != IXGBE_SUCCESS) {
4044 DEBUGOUT("Auto-Negotiation did not complete\n");
4048 /* Determine link parter flow control */
4049 status = hw->mac.ops.read_iosf_sb_reg(hw,
4050 IXGBE_KRM_PCS_KX_AN_LP(hw->bus.lan_id),
4051 IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an_lp);
4053 if (status != IXGBE_SUCCESS) {
4054 DEBUGOUT("Auto-Negotiation did not complete\n");
4058 status = ixgbe_negotiate_fc(hw, pcs_an, pcs_an_lp,
4059 IXGBE_KRM_PCS_KX_AN_SYM_PAUSE,
4060 IXGBE_KRM_PCS_KX_AN_ASM_PAUSE,
4061 IXGBE_KRM_PCS_KX_AN_LP_SYM_PAUSE,
4062 IXGBE_KRM_PCS_KX_AN_LP_ASM_PAUSE);
4065 if (status == IXGBE_SUCCESS) {
4066 hw->fc.fc_was_autonegged = true;
4068 hw->fc.fc_was_autonegged = false;
4069 hw->fc.current_mode = hw->fc.requested_mode;
4074 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4075 * @hw: pointer to hardware structure
4077 * Enable flow control according to IEEE clause 37.
4079 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4081 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4082 u16 reg, pcs_an_lp, pcs_an;
4083 ixgbe_link_speed speed;
4086 /* AN should have completed when the cable was plugged in.
4087 * Look for reasons to bail out. Bail out if:
4088 * - FC autoneg is disabled, or if
4091 if (hw->fc.disable_fc_autoneg) {
4092 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4093 "Flow control autoneg is disabled");
4097 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4099 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4103 /* Check if auto-negotiation has completed */
4104 status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_STATUS,
4105 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4106 if (status != IXGBE_SUCCESS ||
4107 (reg & IXGBE_M88E1500_COPPER_STATUS_AN_DONE) == 0) {
4108 DEBUGOUT("Auto-Negotiation did not complete\n");
4109 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4113 /* Get the advertized flow control */
4114 status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4115 IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an);
4116 if (status != IXGBE_SUCCESS)
4119 /* Get link partner's flow control */
4120 status = hw->phy.ops.read_reg(hw,
4121 IXGBE_M88E1500_COPPER_AN_LP_ABILITY,
4122 IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an_lp);
4123 if (status != IXGBE_SUCCESS)
4126 /* Negotiate the flow control */
4127 status = ixgbe_negotiate_fc(hw, (u32)pcs_an, (u32)pcs_an_lp,
4128 IXGBE_M88E1500_COPPER_AN_PAUSE,
4129 IXGBE_M88E1500_COPPER_AN_AS_PAUSE,
4130 IXGBE_M88E1500_COPPER_AN_LP_PAUSE,
4131 IXGBE_M88E1500_COPPER_AN_LP_AS_PAUSE);
4134 if (status == IXGBE_SUCCESS) {
4135 hw->fc.fc_was_autonegged = true;
4137 hw->fc.fc_was_autonegged = false;
4138 hw->fc.current_mode = hw->fc.requested_mode;
4143 * ixgbe_setup_fc_sgmii_x550em_a - Set up flow control
4144 * @hw: pointer to hardware structure
4146 * Called at init time to set up flow control.
4148 s32 ixgbe_setup_fc_sgmii_x550em_a(struct ixgbe_hw *hw)
4153 /* Validate the requested mode */
4154 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4155 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4156 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4157 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4160 if (hw->fc.requested_mode == ixgbe_fc_default)
4161 hw->fc.requested_mode = ixgbe_fc_full;
4163 /* Read contents of the Auto-Negotiation register, page 0 reg 4 */
4164 rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4165 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4169 /* Disable all the settings related to Flow control Auto-negotiation */
4170 reg &= ~IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4171 reg &= ~IXGBE_M88E1500_COPPER_AN_PAUSE;
4173 /* Configure the Asymmetric and symmetric pause according to the user
4176 switch (hw->fc.requested_mode) {
4178 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4179 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4181 case ixgbe_fc_rx_pause:
4182 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4183 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4185 case ixgbe_fc_tx_pause:
4186 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4192 /* Write back to the Auto-Negotiation register with newly configured
4195 hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_AN,
4196 IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4198 /* In this section of the code we restart Auto-negotiation */
4200 /* Read the CONTROL register, Page 0 reg 0 */
4201 rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4202 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4206 /* Set the bit to restart Auto-Neg. The bit to enable Auto-neg is ON
4209 reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
4211 /* write the new values to the register to restart Auto-Negotiation */
4212 hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4213 IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4220 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4221 * @hw: pointer to hardware structure
4223 * Called at init time to set up flow control.
4225 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4227 s32 status = IXGBE_SUCCESS;
4228 u32 an_cntl, link_ctrl = 0;
4230 DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4232 /* Validate the requested mode */
4233 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4234 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4235 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4236 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4239 if (hw->fc.requested_mode == ixgbe_fc_default)
4240 hw->fc.requested_mode = ixgbe_fc_full;
4242 /* Set up the 1G and 10G flow control advertisement registers so the
4243 * HW will be able to do FC autoneg once the cable is plugged in. If
4244 * we link at 10G, the 1G advertisement is harmless and vice versa.
4246 status = hw->mac.ops.read_iosf_sb_reg(hw,
4247 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4248 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4250 if (status != IXGBE_SUCCESS) {
4251 DEBUGOUT("Auto-Negotiation did not complete\n");
4255 /* The possible values of fc.requested_mode are:
4256 * 0: Flow control is completely disabled
4257 * 1: Rx flow control is enabled (we can receive pause frames,
4258 * but not send pause frames).
4259 * 2: Tx flow control is enabled (we can send pause frames but
4260 * we do not support receiving pause frames).
4261 * 3: Both Rx and Tx flow control (symmetric) are enabled.
4264 switch (hw->fc.requested_mode) {
4266 /* Flow control completely disabled by software override. */
4267 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4268 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4270 case ixgbe_fc_tx_pause:
4271 /* Tx Flow control is enabled, and Rx Flow control is
4272 * disabled by software override.
4274 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4275 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4277 case ixgbe_fc_rx_pause:
4278 /* Rx Flow control is enabled and Tx Flow control is
4279 * disabled by software override. Since there really
4280 * isn't a way to advertise that we are capable of RX
4281 * Pause ONLY, we will advertise that we support both
4282 * symmetric and asymmetric Rx PAUSE, as such we fall
4283 * through to the fc_full statement. Later, we will
4284 * disable the adapter's ability to send PAUSE frames.
4287 /* Flow control (both Rx and Tx) is enabled by SW override. */
4288 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4289 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4292 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4293 "Flow control param set incorrectly\n");
4294 return IXGBE_ERR_CONFIG;
4297 status = hw->mac.ops.write_iosf_sb_reg(hw,
4298 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4299 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4301 /* Restart auto-negotiation. */
4302 status = hw->mac.ops.read_iosf_sb_reg(hw,
4303 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4304 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
4306 if (status != IXGBE_SUCCESS) {
4307 DEBUGOUT("Auto-Negotiation did not complete\n");
4311 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
4312 status = hw->mac.ops.write_iosf_sb_reg(hw,
4313 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4314 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
4320 * ixgbe_setup_fc_fiber_x550em_a - Set up flow control
4321 * @hw: pointer to hardware structure
4323 * Called at init time to set up flow control.
4325 s32 ixgbe_setup_fc_fiber_x550em_a(struct ixgbe_hw *hw)
4327 struct ixgbe_mac_info *mac = &hw->mac;
4328 s32 rc = IXGBE_SUCCESS;
4329 u32 an_cntl4, lctrl, pcs_an;
4331 DEBUGFUNC("ixgbe_setup_fc_fiber_x550em_a");
4333 /* Validate the requested mode */
4334 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4335 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4336 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4337 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4340 /* Enable clause 37 auto-negotiation in KRM_LINK_CTRL_1 */
4341 if (hw->fc.requested_mode == ixgbe_fc_default)
4342 hw->fc.requested_mode = ixgbe_fc_full;
4344 rc = mac->ops.read_iosf_sb_reg(hw,
4345 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4346 IXGBE_SB_IOSF_TARGET_KR_PHY, &lctrl);
4350 lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
4351 lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
4353 rc = mac->ops.write_iosf_sb_reg(hw,
4354 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4355 IXGBE_SB_IOSF_TARGET_KR_PHY, lctrl);
4359 /* Enable clause 37 over 73 in KRM_AN_CNTL_4 */
4360 rc = mac->ops.read_iosf_sb_reg(hw,
4361 IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
4362 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl4);
4366 an_cntl4 |= IXGBE_KRM_AN_CNTL_4_ECSR_AN37_OVER_73;
4368 rc = mac->ops.write_iosf_sb_reg(hw,
4369 IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
4370 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl4);
4374 rc = hw->mac.ops.read_iosf_sb_reg(hw,
4375 IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4376 IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an);
4381 /* The possible values of fc.requested_mode are:
4382 * 0: Flow control is completely disabled
4383 * 1: Rx flow control is enabled (we can receive pause frames,
4384 * but not send pause frames).
4385 * 2: Tx flow control is enabled (we can send pause frames but
4386 * we do not support receiving pause frames).
4387 * 3: Both Rx and Tx flow control (symmetric) are enabled.
4390 switch (hw->fc.requested_mode) {
4392 /* Flow control completely disabled by software override. */
4393 pcs_an &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4394 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4396 case ixgbe_fc_tx_pause:
4397 /* Tx Flow control is enabled, and Rx Flow control is
4398 * disabled by software override.
4400 pcs_an |= IXGBE_KRM_PCS_KX_AN_ASM_PAUSE;
4401 pcs_an &= ~IXGBE_KRM_PCS_KX_AN_SYM_PAUSE;
4403 case ixgbe_fc_rx_pause:
4404 /* Rx Flow control is enabled and Tx Flow control is
4405 * disabled by software override. Since there really
4406 * isn't a way to advertise that we are capable of RX
4407 * Pause ONLY, we will advertise that we support both
4408 * symmetric and asymmetric Rx PAUSE, as such we fall
4409 * through to the fc_full statement. Later, we will
4410 * disable the adapter's ability to send PAUSE frames.
4413 /* Flow control (both Rx and Tx) is enabled by SW override. */
4414 pcs_an |= IXGBE_KRM_PCS_KX_AN_SYM_PAUSE |
4415 IXGBE_KRM_PCS_KX_AN_ASM_PAUSE;
4418 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4419 "Flow control param set incorrectly\n");
4420 return IXGBE_ERR_CONFIG;
4423 rc = hw->mac.ops.write_iosf_sb_reg(hw,
4424 IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4425 IXGBE_SB_IOSF_TARGET_KR_PHY, pcs_an);
4427 /* Restart auto-negotiation. */
4428 rc = hw->mac.ops.read_iosf_sb_reg(hw,
4429 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4430 IXGBE_SB_IOSF_TARGET_KR_PHY, &lctrl);
4433 DEBUGOUT("Auto-Negotiation did not complete\n");
4437 lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
4438 rc = hw->mac.ops.write_iosf_sb_reg(hw,
4439 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4440 IXGBE_SB_IOSF_TARGET_KR_PHY, lctrl);
4446 * ixgbe_set_mux - Set mux for port 1 access with CS4227
4447 * @hw: pointer to hardware structure
4448 * @state: set mux if 1, clear if 0
4450 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4454 if (!hw->bus.lan_id)
4456 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4458 esdp |= IXGBE_ESDP_SDP1;
4460 esdp &= ~IXGBE_ESDP_SDP1;
4461 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4462 IXGBE_WRITE_FLUSH(hw);
4466 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4467 * @hw: pointer to hardware structure
4468 * @mask: Mask to specify which semaphore to acquire
4470 * Acquires the SWFW semaphore and sets the I2C MUX
4472 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4476 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4478 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4482 if (mask & IXGBE_GSSR_I2C_MASK)
4483 ixgbe_set_mux(hw, 1);
4485 return IXGBE_SUCCESS;
4489 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4490 * @hw: pointer to hardware structure
4491 * @mask: Mask to specify which semaphore to release
4493 * Releases the SWFW semaphore and sets the I2C MUX
4495 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4497 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4499 if (mask & IXGBE_GSSR_I2C_MASK)
4500 ixgbe_set_mux(hw, 0);
4502 ixgbe_release_swfw_sync_X540(hw, mask);
4506 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4507 * @hw: pointer to hardware structure
4508 * @mask: Mask to specify which semaphore to acquire
4510 * Acquires the SWFW semaphore and get the shared phy token as needed
4512 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4514 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4515 int retries = FW_PHY_TOKEN_RETRIES;
4516 s32 status = IXGBE_SUCCESS;
4518 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4521 status = IXGBE_SUCCESS;
4523 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4526 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4527 return IXGBE_SUCCESS;
4529 status = ixgbe_get_phy_token(hw);
4530 if (status == IXGBE_SUCCESS)
4531 return IXGBE_SUCCESS;
4534 ixgbe_release_swfw_sync_X540(hw, hmask);
4535 if (status != IXGBE_ERR_TOKEN_RETRY)
4543 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4544 * @hw: pointer to hardware structure
4545 * @mask: Mask to specify which semaphore to release
4547 * Releases the SWFW semaphore and puts the shared phy token as needed
4549 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4551 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4553 DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4555 if (mask & IXGBE_GSSR_TOKEN_SM)
4556 ixgbe_put_phy_token(hw);
4559 ixgbe_release_swfw_sync_X540(hw, hmask);
4563 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
4564 * @hw: pointer to hardware structure
4565 * @reg_addr: 32 bit address of PHY register to read
4566 * @phy_data: Pointer to read data from PHY register
4568 * Reads a value from a specified PHY register using the SWFW lock and PHY
4569 * Token. The PHY Token is needed since the MDIO is shared between to MAC
4572 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4573 u32 device_type, u16 *phy_data)
4576 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4578 DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4580 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4581 return IXGBE_ERR_SWFW_SYNC;
4583 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4585 hw->mac.ops.release_swfw_sync(hw, mask);
4591 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
4592 * @hw: pointer to hardware structure
4593 * @reg_addr: 32 bit PHY register to write
4594 * @device_type: 5 bit device type
4595 * @phy_data: Data to write to the PHY register
4597 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
4598 * The PHY Token is needed since the MDIO is shared between to MAC instances.
4600 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4601 u32 device_type, u16 phy_data)
4604 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4606 DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4608 if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4609 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4611 hw->mac.ops.release_swfw_sync(hw, mask);
4613 status = IXGBE_ERR_SWFW_SYNC;
4620 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4621 * @hw: pointer to hardware structure
4623 * Handle external Base T PHY interrupt. If high temperature
4624 * failure alarm then return error, else if link status change
4625 * then setup internal/external PHY link
4627 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4628 * failure alarm, else return PHY access status.
4630 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4635 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4637 if (status != IXGBE_SUCCESS)
4641 return ixgbe_setup_internal_phy(hw);
4643 return IXGBE_SUCCESS;
4647 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4648 * @hw: pointer to hardware structure
4649 * @speed: new link speed
4650 * @autoneg_wait_to_complete: true when waiting for completion is needed
4652 * Setup internal/external PHY link speed based on link speed, then set
4653 * external PHY auto advertised link speed.
4655 * Returns error status for any failure
4657 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4658 ixgbe_link_speed speed,
4659 bool autoneg_wait_to_complete)
4662 ixgbe_link_speed force_speed;
4664 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4666 /* Setup internal/external PHY link speed to iXFI (10G), unless
4667 * only 1G is auto advertised then setup KX link.
4669 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4670 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4672 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4674 /* If internal link mode is XFI, then setup XFI internal link. */
4675 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4676 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4678 if (status != IXGBE_SUCCESS)
4682 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4686 * ixgbe_check_link_t_X550em - Determine link and speed status
4687 * @hw: pointer to hardware structure
4688 * @speed: pointer to link speed
4689 * @link_up: true when link is up
4690 * @link_up_wait_to_complete: bool used to wait for link up or not
4692 * Check that both the MAC and X557 external PHY have link.
4694 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4695 bool *link_up, bool link_up_wait_to_complete)
4700 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4701 return IXGBE_ERR_CONFIG;
4703 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4704 link_up_wait_to_complete);
4706 /* If check link fails or MAC link is not up, then return */
4707 if (status != IXGBE_SUCCESS || !(*link_up))
4710 /* MAC link is up, so check external PHY link.
4711 * Read this twice back to back to indicate current status.
4713 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4714 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4717 if (status != IXGBE_SUCCESS)
4720 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4721 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4724 if (status != IXGBE_SUCCESS)
4727 /* If external PHY link is not up, then indicate link not up */
4728 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4731 return IXGBE_SUCCESS;
4735 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4736 * @hw: pointer to hardware structure
4738 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4742 status = ixgbe_reset_phy_generic(hw);
4744 if (status != IXGBE_SUCCESS)
4747 /* Configure Link Status Alarm and Temperature Threshold interrupts */
4748 return ixgbe_enable_lasi_ext_t_x550em(hw);
4752 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4753 * @hw: pointer to hardware structure
4754 * @led_idx: led number to turn on
4756 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4760 DEBUGFUNC("ixgbe_led_on_t_X550em");
4762 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4763 return IXGBE_ERR_PARAM;
4765 /* To turn on the LED, set mode to ON. */
4766 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4767 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4768 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4769 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4770 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4772 return IXGBE_SUCCESS;
4776 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4777 * @hw: pointer to hardware structure
4778 * @led_idx: led number to turn off
4780 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4784 DEBUGFUNC("ixgbe_led_off_t_X550em");
4786 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4787 return IXGBE_ERR_PARAM;
4789 /* To turn on the LED, set mode to ON. */
4790 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4791 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4792 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4793 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4794 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4796 return IXGBE_SUCCESS;