drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
  45
  46 /**
  47  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  48  *  @hw: pointer to hardware structure
  49  *
  50  *  Initialize the function pointers and assign the MAC type for X550.
  51  *  Does not touch the hardware.
  52  **/
  53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  54 {
  55         struct ixgbe_mac_info *mac = &hw->mac;
  56         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  57         s32 ret_val;
  58
  59         DEBUGFUNC("ixgbe_init_ops_X550");
  60
  61         ret_val = ixgbe_init_ops_X540(hw);
  62         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  63         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  64         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  65         mac->ops.setup_eee = NULL;
  66         mac->ops.set_source_address_pruning =
  67                         ixgbe_set_source_address_pruning_X550;
  68         mac->ops.set_ethertype_anti_spoofing =
  69                         ixgbe_set_ethertype_anti_spoofing_X550;
  70
  71         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  72         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  73         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  74         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  75         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  76         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  77         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  78         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  79         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  80
  81         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  82         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  83         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  84         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  85         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  86         /* Manageability interface */
  87         mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
  88         switch (hw->device_id) {
  89         case IXGBE_DEV_ID_X550EM_X_10G_T:
  90         case IXGBE_DEV_ID_X550EM_A_10G_T:
  91                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  92                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  93                 break;
  94         default:
  95                 break;
  96         }
  97         return ret_val;
  98 }
  99
 100 /**
 101  * ixgbe_read_cs4227 - Read CS4227 register
 102  * @hw: pointer to hardware structure
 103  * @reg: register number to write
 104  * @value: pointer to receive value read
 105  *
 106  * Returns status code
 107  **/
 108 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 109 {
 110         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 111 }
 112
 113 /**
 114  * ixgbe_write_cs4227 - Write CS4227 register
 115  * @hw: pointer to hardware structure
 116  * @reg: register number to write
 117  * @value: value to write to register
 118  *
 119  * Returns status code
 120  **/
 121 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 122 {
 123         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 124 }
 125
 126 /**
 127  * ixgbe_read_pe - Read register from port expander
 128  * @hw: pointer to hardware structure
 129  * @reg: register number to read
 130  * @value: pointer to receive read value
 131  *
 132  * Returns status code
 133  **/
 134 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 135 {
 136         s32 status;
 137
 138         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 139         if (status != IXGBE_SUCCESS)
 140                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 141                               "port expander access failed with %d\n", status);
 142         return status;
 143 }
 144
 145 /**
 146  * ixgbe_write_pe - Write register to port expander
 147  * @hw: pointer to hardware structure
 148  * @reg: register number to write
 149  * @value: value to write
 150  *
 151  * Returns status code
 152  **/
 153 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 154 {
 155         s32 status;
 156
 157         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 158         if (status != IXGBE_SUCCESS)
 159                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 160                               "port expander access failed with %d\n", status);
 161         return status;
 162 }
 163
 164 /**
 165  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 166  * @hw: pointer to hardware structure
 167  *
 168  * This function assumes that the caller has acquired the proper semaphore.
 169  * Returns error code
 170  **/
 171 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 172 {
 173         s32 status;
 174         u32 retry;
 175         u16 value;
 176         u8 reg;
 177
 178         /* Trigger hard reset. */
 179         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 180         if (status != IXGBE_SUCCESS)
 181                 return status;
 182         reg |= IXGBE_PE_BIT1;
 183         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 184         if (status != IXGBE_SUCCESS)
 185                 return status;
 186
 187         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 188         if (status != IXGBE_SUCCESS)
 189                 return status;
 190         reg &= ~IXGBE_PE_BIT1;
 191         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 192         if (status != IXGBE_SUCCESS)
 193                 return status;
 194
 195         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 196         if (status != IXGBE_SUCCESS)
 197                 return status;
 198         reg &= ~IXGBE_PE_BIT1;
 199         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 200         if (status != IXGBE_SUCCESS)
 201                 return status;
 202
 203         usec_delay(IXGBE_CS4227_RESET_HOLD);
 204
 205         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 206         if (status != IXGBE_SUCCESS)
 207                 return status;
 208         reg |= IXGBE_PE_BIT1;
 209         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 210         if (status != IXGBE_SUCCESS)
 211                 return status;
 212
 213         /* Wait for the reset to complete. */
 214         msec_delay(IXGBE_CS4227_RESET_DELAY);
 215         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 216                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 217                                            &value);
 218                 if (status == IXGBE_SUCCESS &&
 219                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 220                         break;
 221                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 222         }
 223         if (retry == IXGBE_CS4227_RETRIES) {
 224                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 225                         "CS4227 reset did not complete.");
 226                 return IXGBE_ERR_PHY;
 227         }
 228
 229         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 230         if (status != IXGBE_SUCCESS ||
 231             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 232                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 233                         "CS4227 EEPROM did not load successfully.");
 234                 return IXGBE_ERR_PHY;
 235         }
 236
 237         return IXGBE_SUCCESS;
 238 }
 239
 240 /**
 241  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 242  * @hw: pointer to hardware structure
 243  **/
 244 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 245 {
 246         s32 status = IXGBE_SUCCESS;
 247         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 248         u16 value = 0;
 249         u8 retry;
 250
 251         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 252                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 253                 if (status != IXGBE_SUCCESS) {
 254                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 255                                 "semaphore failed with %d", status);
 256                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 257                         continue;
 258                 }
 259
 260                 /* Get status of reset flow. */
 261                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 262
 263                 if (status == IXGBE_SUCCESS &&
 264                     value == IXGBE_CS4227_RESET_COMPLETE)
 265                         goto out;
 266
 267                 if (status != IXGBE_SUCCESS ||
 268                     value != IXGBE_CS4227_RESET_PENDING)
 269                         break;
 270
 271                 /* Reset is pending. Wait and check again. */
 272                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 273                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 274         }
 275
 276         /* If still pending, assume other instance failed. */
 277         if (retry == IXGBE_CS4227_RETRIES) {
 278                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 279                 if (status != IXGBE_SUCCESS) {
 280                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 281                                       "semaphore failed with %d", status);
 282                         return;
 283                 }
 284         }
 285
 286         /* Reset the CS4227. */
 287         status = ixgbe_reset_cs4227(hw);
 288         if (status != IXGBE_SUCCESS) {
 289                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 290                         "CS4227 reset failed: %d", status);
 291                 goto out;
 292         }
 293
 294         /* Reset takes so long, temporarily release semaphore in case the
 295          * other driver instance is waiting for the reset indication.
 296          */
 297         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 298                            IXGBE_CS4227_RESET_PENDING);
 299         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 300         msec_delay(10);
 301         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 302         if (status != IXGBE_SUCCESS) {
 303                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 304                         "semaphore failed with %d", status);
 305                 return;
 306         }
 307
 308         /* Record completion for next time. */
 309         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 310                 IXGBE_CS4227_RESET_COMPLETE);
 311
 312 out:
 313         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 314         msec_delay(hw->eeprom.semaphore_delay);
 315 }
 316
 317 /**
 318  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 319  * @hw: pointer to hardware structure
 320  **/
 321 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 322 {
 323         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 324
 325         if (hw->bus.lan_id) {
 326                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 327                 esdp |= IXGBE_ESDP_SDP1_DIR;
 328         }
 329         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 330         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 331         IXGBE_WRITE_FLUSH(hw);
 332 }
 333
 334 /**
 335  * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
 336  * @hw: pointer to hardware structure
 337  * @reg_addr: 32 bit address of PHY register to read
 338  * @dev_type: always unused
 339  * @phy_data: Pointer to read data from PHY register
 340  */
 341 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 342                                      u32 dev_type, u16 *phy_data)
 343 {
 344         u32 i, data, command;
 345         UNREFERENCED_1PARAMETER(dev_type);
 346
 347         /* Setup and write the read command */
 348         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 349                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 350                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
 351                   IXGBE_MSCA_MDI_COMMAND;
 352
 353         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 354
 355         /* Check every 10 usec to see if the access completed.
 356          * The MDI Command bit will clear when the operation is
 357          * complete
 358          */
 359         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 360                 usec_delay(10);
 361
 362                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 363                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 364                         break;
 365         }
 366
 367         if (command & IXGBE_MSCA_MDI_COMMAND) {
 368                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 369                               "PHY read command did not complete.\n");
 370                 return IXGBE_ERR_PHY;
 371         }
 372
 373         /* Read operation is complete.  Get the data from MSRWD */
 374         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 375         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 376         *phy_data = (u16)data;
 377
 378         return IXGBE_SUCCESS;
 379 }
 380
 381 /**
 382  * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
 383  * @hw: pointer to hardware structure
 384  * @reg_addr: 32 bit PHY register to write
 385  * @dev_type: always unused
 386  * @phy_data: Data to write to the PHY register
 387  */
 388 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 389                                       u32 dev_type, u16 phy_data)
 390 {
 391         u32 i, command;
 392         UNREFERENCED_1PARAMETER(dev_type);
 393
 394         /* Put the data in the MDI single read and write data register*/
 395         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 396
 397         /* Setup and write the write command */
 398         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 399                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 400                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
 401                   IXGBE_MSCA_MDI_COMMAND;
 402
 403         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 404
 405         /* Check every 10 usec to see if the access completed.
 406          * The MDI Command bit will clear when the operation is
 407          * complete
 408          */
 409         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 410                 usec_delay(10);
 411
 412                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 413                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 414                         break;
 415         }
 416
 417         if (command & IXGBE_MSCA_MDI_COMMAND) {
 418                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 419                               "PHY write cmd didn't complete\n");
 420                 return IXGBE_ERR_PHY;
 421         }
 422
 423         return IXGBE_SUCCESS;
 424 }
 425
 426 /**
 427  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 428  * @hw: pointer to hardware structure
 429  *
 430  * Returns error code
 431  */
 432 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 433 {
 434         hw->mac.ops.set_lan_id(hw);
 435
 436         ixgbe_read_mng_if_sel_x550em(hw);
 437
 438         switch (hw->device_id) {
 439         case IXGBE_DEV_ID_X550EM_A_SFP:
 440                 return ixgbe_identify_module_generic(hw);
 441         case IXGBE_DEV_ID_X550EM_X_SFP:
 442                 /* set up for CS4227 usage */
 443                 ixgbe_setup_mux_ctl(hw);
 444                 ixgbe_check_cs4227(hw);
 445                 /* Fallthrough */
 446
 447         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 448                 return ixgbe_identify_module_generic(hw);
 449                 break;
 450         case IXGBE_DEV_ID_X550EM_X_KX4:
 451                 hw->phy.type = ixgbe_phy_x550em_kx4;
 452                 break;
 453         case IXGBE_DEV_ID_X550EM_X_KR:
 454         case IXGBE_DEV_ID_X550EM_A_KR:
 455         case IXGBE_DEV_ID_X550EM_A_KR_L:
 456                 hw->phy.type = ixgbe_phy_x550em_kr;
 457                 break;
 458         case IXGBE_DEV_ID_X550EM_A_10G_T:
 459         case IXGBE_DEV_ID_X550EM_X_1G_T:
 460         case IXGBE_DEV_ID_X550EM_X_10G_T:
 461                 return ixgbe_identify_phy_generic(hw);
 462         case IXGBE_DEV_ID_X550EM_A_1G_T:
 463         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 464                 hw->phy.type = ixgbe_phy_fw;
 465                 hw->phy.ops.read_reg = NULL;
 466                 hw->phy.ops.write_reg = NULL;
 467                 if (hw->bus.lan_id)
 468                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 469                 else
 470                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 471                 break;
 472         default:
 473                 break;
 474         }
 475         return IXGBE_SUCCESS;
 476 }
 477
 478 /**
 479  * ixgbe_fw_phy_activity - Perform an activity on a PHY
 480  * @hw: pointer to hardware structure
 481  * @activity: activity to perform
 482  * @data: Pointer to 4 32-bit words of data
 483  */
 484 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
 485                           u32 (*data)[FW_PHY_ACT_DATA_COUNT])
 486 {
 487         union {
 488                 struct ixgbe_hic_phy_activity_req cmd;
 489                 struct ixgbe_hic_phy_activity_resp rsp;
 490         } hic;
 491         u16 retries = FW_PHY_ACT_RETRIES;
 492         s32 rc;
 493         u16 i;
 494
 495         do {
 496                 memset(&hic, 0, sizeof(hic));
 497                 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
 498                 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
 499                 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 500                 hic.cmd.port_number = hw->bus.lan_id;
 501                 hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity);
 502                 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 503                         hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]);
 504
 505                 rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
 506                                                   sizeof(hic.cmd),
 507                                                   IXGBE_HI_COMMAND_TIMEOUT,
 508                                                   true);
 509                 if (rc != IXGBE_SUCCESS)
 510                         return rc;
 511                 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
 512                     FW_CEM_RESP_STATUS_SUCCESS) {
 513                         for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 514                                 (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]);
 515                         return IXGBE_SUCCESS;
 516                 }
 517                 usec_delay(20);
 518                 --retries;
 519         } while (retries > 0);
 520
 521         return IXGBE_ERR_HOST_INTERFACE_COMMAND;
 522 }
 523
 524 static const struct {
 525         u16 fw_speed;
 526         ixgbe_link_speed phy_speed;
 527 } ixgbe_fw_map[] = {
 528         { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
 529         { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
 530         { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
 531         { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
 532         { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
 533         { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
 534 };
 535
 536 /**
 537  * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
 538  * @hw: pointer to hardware structure
 539  *
 540  * Returns error code
 541  */
 542 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
 543 {
 544         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
 545         u16 phy_speeds;
 546         u16 phy_id_lo;
 547         s32 rc;
 548         u16 i;
 549
 550         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
 551         if (rc)
 552                 return rc;
 553
 554         hw->phy.speeds_supported = 0;
 555         phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
 556         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 557                 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
 558                         hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
 559         }
 560         if (!hw->phy.autoneg_advertised)
 561                 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
 562
 563         hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
 564         phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
 565         hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
 566         hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
 567         if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
 568                 return IXGBE_ERR_PHY_ADDR_INVALID;
 569         return IXGBE_SUCCESS;
 570 }
 571
 572 /**
 573  * ixgbe_identify_phy_fw - Get PHY type based on firmware command
 574  * @hw: pointer to hardware structure
 575  *
 576  * Returns error code
 577  */
 578 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
 579 {
 580         if (hw->bus.lan_id)
 581                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 582         else
 583                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 584
 585         hw->phy.type = ixgbe_phy_fw;
 586         hw->phy.ops.read_reg = NULL;
 587         hw->phy.ops.write_reg = NULL;
 588         return ixgbe_get_phy_id_fw(hw);
 589 }
 590
 591 /**
 592  * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
 593  * @hw: pointer to hardware structure
 594  *
 595  * Returns error code
 596  */
 597 s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
 598 {
 599         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 600
 601         setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
 602         return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
 603 }
 604
 605 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 606                                      u32 device_type, u16 *phy_data)
 607 {
 608         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 609         return IXGBE_NOT_IMPLEMENTED;
 610 }
 611
 612 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 613                                       u32 device_type, u16 phy_data)
 614 {
 615         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 616         return IXGBE_NOT_IMPLEMENTED;
 617 }
 618
 619 /**
 620  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 621  * @hw: pointer to the hardware structure
 622  * @addr: I2C bus address to read from
 623  * @reg: I2C device register to read from
 624  * @val: pointer to location to receive read value
 625  *
 626  * Returns an error code on error.
 627  **/
 628 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 629                                            u16 reg, u16 *val)
 630 {
 631         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 632 }
 633
 634 /**
 635  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 636  * @hw: pointer to the hardware structure
 637  * @addr: I2C bus address to read from
 638  * @reg: I2C device register to read from
 639  * @val: pointer to location to receive read value
 640  *
 641  * Returns an error code on error.
 642  **/
 643 STATIC s32
 644 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 645                                          u16 reg, u16 *val)
 646 {
 647         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 648 }
 649
 650 /**
 651  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 652  * @hw: pointer to the hardware structure
 653  * @addr: I2C bus address to write to
 654  * @reg: I2C device register to write to
 655  * @val: value to write
 656  *
 657  * Returns an error code on error.
 658  **/
 659 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 660                                             u8 addr, u16 reg, u16 val)
 661 {
 662         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 663 }
 664
 665 /**
 666  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 667  * @hw: pointer to the hardware structure
 668  * @addr: I2C bus address to write to
 669  * @reg: I2C device register to write to
 670  * @val: value to write
 671  *
 672  * Returns an error code on error.
 673  **/
 674 STATIC s32
 675 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 676                                           u8 addr, u16 reg, u16 val)
 677 {
 678         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 679 }
 680
 681 /**
 682 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 683 *  @hw: pointer to hardware structure
 684 *
 685 *  Initialize the function pointers and for MAC type X550EM.
 686 *  Does not touch the hardware.
 687 **/
 688 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 689 {
 690         struct ixgbe_mac_info *mac = &hw->mac;
 691         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 692         struct ixgbe_phy_info *phy = &hw->phy;
 693         s32 ret_val;
 694
 695         DEBUGFUNC("ixgbe_init_ops_X550EM");
 696
 697         /* Similar to X550 so start there. */
 698         ret_val = ixgbe_init_ops_X550(hw);
 699
 700         /* Since this function eventually calls
 701          * ixgbe_init_ops_540 by design, we are setting
 702          * the pointers to NULL explicitly here to overwrite
 703          * the values being set in the x540 function.
 704          */
 705         /* Thermal sensor not supported in x550EM */
 706         mac->ops.get_thermal_sensor_data = NULL;
 707         mac->ops.init_thermal_sensor_thresh = NULL;
 708         mac->thermal_sensor_enabled = false;
 709
 710         /* FCOE not supported in x550EM */
 711         mac->ops.get_san_mac_addr = NULL;
 712         mac->ops.set_san_mac_addr = NULL;
 713         mac->ops.get_wwn_prefix = NULL;
 714         mac->ops.get_fcoe_boot_status = NULL;
 715
 716         /* IPsec not supported in x550EM */
 717         mac->ops.disable_sec_rx_path = NULL;
 718         mac->ops.enable_sec_rx_path = NULL;
 719
 720         /* AUTOC register is not present in x550EM. */
 721         mac->ops.prot_autoc_read = NULL;
 722         mac->ops.prot_autoc_write = NULL;
 723
 724         /* X550EM bus type is internal*/
 725         hw->bus.type = ixgbe_bus_type_internal;
 726         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 727
 728
 729         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 730         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 731         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 732         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 733         mac->ops.get_supported_physical_layer =
 734                                     ixgbe_get_supported_physical_layer_X550em;
 735
 736         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 737                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 738         else
 739                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 740
 741         /* PHY */
 742         phy->ops.init = ixgbe_init_phy_ops_X550em;
 743         switch (hw->device_id) {
 744         case IXGBE_DEV_ID_X550EM_A_1G_T:
 745         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 746                 mac->ops.setup_fc = NULL;
 747                 phy->ops.identify = ixgbe_identify_phy_fw;
 748                 phy->ops.set_phy_power = NULL;
 749                 phy->ops.get_firmware_version = NULL;
 750                 break;
 751         default:
 752                 phy->ops.identify = ixgbe_identify_phy_x550em;
 753         }
 754
 755         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 756                 phy->ops.set_phy_power = NULL;
 757
 758
 759         /* EEPROM */
 760         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 761         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 762         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 763         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 764         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 765         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 766         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 767         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 768
 769         return ret_val;
 770 }
 771
 772 /**
 773  * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
 774  * @hw: pointer to hardware structure
 775  */
 776 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
 777 {
 778         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 779         s32 rc;
 780         u16 i;
 781
 782         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
 783                 return 0;
 784
 785         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 786                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
 787                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
 788                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
 789         }
 790
 791         switch (hw->fc.requested_mode) {
 792         case ixgbe_fc_full:
 793                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
 794                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 795                 break;
 796         case ixgbe_fc_rx_pause:
 797                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
 798                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 799                 break;
 800         case ixgbe_fc_tx_pause:
 801                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
 802                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 803                 break;
 804         default:
 805                 break;
 806         }
 807
 808         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 809                 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
 810                         setup[0] |= ixgbe_fw_map[i].fw_speed;
 811         }
 812         setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
 813
 814         if (hw->phy.eee_speeds_advertised)
 815                 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
 816
 817         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
 818         if (rc)
 819                 return rc;
 820         if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
 821                 return IXGBE_ERR_OVERTEMP;
 822         return IXGBE_SUCCESS;
 823 }
 824
 825 /**
 826  * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs
 827  * @hw: pointer to hardware structure
 828  *
 829  *  Called at init time to set up flow control.
 830  */
 831 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
 832 {
 833         if (hw->fc.requested_mode == ixgbe_fc_default)
 834                 hw->fc.requested_mode = ixgbe_fc_full;
 835
 836         return ixgbe_setup_fw_link(hw);
 837 }
 838
 839 /**
 840  * ixgbe_setup_eee_fw - Enable/disable EEE support
 841  * @hw: pointer to the HW structure
 842  * @enable_eee: boolean flag to enable EEE
 843  *
 844  * Enable/disable EEE based on enable_eee flag.
 845  * This function controls EEE for firmware-based PHY implementations.
 846  */
 847 static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee)
 848 {
 849         if (!!hw->phy.eee_speeds_advertised == enable_eee)
 850                 return IXGBE_SUCCESS;
 851         if (enable_eee)
 852                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 853         else
 854                 hw->phy.eee_speeds_advertised = 0;
 855         return hw->phy.ops.setup_link(hw);
 856 }
 857
 858 /**
 859 *  ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
 860 *  @hw: pointer to hardware structure
 861 *
 862 *  Initialize the function pointers and for MAC type X550EM_a.
 863 *  Does not touch the hardware.
 864 **/
 865 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
 866 {
 867         struct ixgbe_mac_info *mac = &hw->mac;
 868         s32 ret_val;
 869
 870         DEBUGFUNC("ixgbe_init_ops_X550EM_a");
 871
 872         /* Start with generic X550EM init */
 873         ret_val = ixgbe_init_ops_X550EM(hw);
 874
 875         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
 876             hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
 877                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 878                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 879         } else {
 880                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 881                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 882         }
 883         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 884         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 885
 886         switch (mac->ops.get_media_type(hw)) {
 887         case ixgbe_media_type_fiber:
 888                 mac->ops.setup_fc = NULL;
 889                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
 890                 break;
 891         case ixgbe_media_type_backplane:
 892                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
 893                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
 894                 break;
 895         default:
 896                 break;
 897         }
 898
 899         if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T) ||
 900                 (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)) {
 901                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
 902                 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
 903         }
 904
 905         switch (hw->device_id) {
 906         case IXGBE_DEV_ID_X550EM_A_KR:
 907         case IXGBE_DEV_ID_X550EM_A_KR_L:
 908                 mac->ops.setup_eee = ixgbe_setup_eee_fw;
 909                 break;
 910         default:
 911                 mac->ops.setup_eee = NULL;
 912         }
 913
 914         return ret_val;
 915 }
 916
 917 /**
 918 *  ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
 919 *  @hw: pointer to hardware structure
 920 *
 921 *  Initialize the function pointers and for MAC type X550EM_x.
 922 *  Does not touch the hardware.
 923 **/
 924 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
 925 {
 926         struct ixgbe_mac_info *mac = &hw->mac;
 927         struct ixgbe_link_info *link = &hw->link;
 928         s32 ret_val;
 929
 930         DEBUGFUNC("ixgbe_init_ops_X550EM_x");
 931
 932         /* Start with generic X550EM init */
 933         ret_val = ixgbe_init_ops_X550EM(hw);
 934
 935         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 936         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 937         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 938         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 939         link->ops.read_link = ixgbe_read_i2c_combined_generic;
 940         link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
 941         link->ops.write_link = ixgbe_write_i2c_combined_generic;
 942         link->ops.write_link_unlocked =
 943                                       ixgbe_write_i2c_combined_generic_unlocked;
 944         link->addr = IXGBE_CS4227;
 945
 946         return ret_val;
 947 }
 948
 949 /**
 950  *  ixgbe_dmac_config_X550
 951  *  @hw: pointer to hardware structure
 952  *
 953  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 954  *  When disabling dmac, dmac enable dmac bit is cleared.
 955  **/
 956 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 957 {
 958         u32 reg, high_pri_tc;
 959
 960         DEBUGFUNC("ixgbe_dmac_config_X550");
 961
 962         /* Disable DMA coalescing before configuring */
 963         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 964         reg &= ~IXGBE_DMACR_DMAC_EN;
 965         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 966
 967         /* Disable DMA Coalescing if the watchdog timer is 0 */
 968         if (!hw->mac.dmac_config.watchdog_timer)
 969                 goto out;
 970
 971         ixgbe_dmac_config_tcs_X550(hw);
 972
 973         /* Configure DMA Coalescing Control Register */
 974         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 975
 976         /* Set the watchdog timer in units of 40.96 usec */
 977         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 978         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 979
 980         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 981         /* If fcoe is enabled, set high priority traffic class */
 982         if (hw->mac.dmac_config.fcoe_en) {
 983                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 984                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 985                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 986         }
 987         reg |= IXGBE_DMACR_EN_MNG_IND;
 988
 989         /* Enable DMA coalescing after configuration */
 990         reg |= IXGBE_DMACR_DMAC_EN;
 991         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 992
 993 out:
 994         return IXGBE_SUCCESS;
 995 }
 996
 997 /**
 998  *  ixgbe_dmac_config_tcs_X550
 999  *  @hw: pointer to hardware structure
1000  *
1001  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
1002  *  be cleared before configuring.
1003  **/
1004 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
1005 {
1006         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
1007
1008         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
1009
1010         /* Configure DMA coalescing enabled */
1011         switch (hw->mac.dmac_config.link_speed) {
1012         case IXGBE_LINK_SPEED_10_FULL:
1013         case IXGBE_LINK_SPEED_100_FULL:
1014                 pb_headroom = IXGBE_DMACRXT_100M;
1015                 break;
1016         case IXGBE_LINK_SPEED_1GB_FULL:
1017                 pb_headroom = IXGBE_DMACRXT_1G;
1018                 break;
1019         default:
1020                 pb_headroom = IXGBE_DMACRXT_10G;
1021                 break;
1022         }
1023
1024         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
1025                              IXGBE_MHADD_MFS_SHIFT) / 1024);
1026
1027         /* Set the per Rx packet buffer receive threshold */
1028         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
1029                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
1030                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
1031
1032                 if (tc < hw->mac.dmac_config.num_tcs) {
1033                         /* Get Rx PB size */
1034                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
1035                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
1036                                 IXGBE_RXPBSIZE_SHIFT;
1037
1038                         /* Calculate receive buffer threshold in kilobytes */
1039                         if (rx_pb_size > pb_headroom)
1040                                 rx_pb_size = rx_pb_size - pb_headroom;
1041                         else
1042                                 rx_pb_size = 0;
1043
1044                         /* Minimum of MFS shall be set for DMCTH */
1045                         reg |= (rx_pb_size > maxframe_size_kb) ?
1046                                 rx_pb_size : maxframe_size_kb;
1047                 }
1048                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
1049         }
1050         return IXGBE_SUCCESS;
1051 }
1052
1053 /**
1054  *  ixgbe_dmac_update_tcs_X550
1055  *  @hw: pointer to hardware structure
1056  *
1057  *  Disables dmac, updates per TC settings, and then enables dmac.
1058  **/
1059 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
1060 {
1061         u32 reg;
1062
1063         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
1064
1065         /* Disable DMA coalescing before configuring */
1066         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1067         reg &= ~IXGBE_DMACR_DMAC_EN;
1068         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1069
1070         ixgbe_dmac_config_tcs_X550(hw);
1071
1072         /* Enable DMA coalescing after configuration */
1073         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1074         reg |= IXGBE_DMACR_DMAC_EN;
1075         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1076
1077         return IXGBE_SUCCESS;
1078 }
1079
1080 /**
1081  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
1082  *  @hw: pointer to hardware structure
1083  *
1084  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
1085  *  ixgbe_hw struct in order to set up EEPROM access.
1086  **/
1087 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
1088 {
1089         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1090         u32 eec;
1091         u16 eeprom_size;
1092
1093         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
1094
1095         if (eeprom->type == ixgbe_eeprom_uninitialized) {
1096                 eeprom->semaphore_delay = 10;
1097                 eeprom->type = ixgbe_flash;
1098
1099                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1100                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1101                                     IXGBE_EEC_SIZE_SHIFT);
1102                 eeprom->word_size = 1 << (eeprom_size +
1103                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
1104
1105                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
1106                           eeprom->type, eeprom->word_size);
1107         }
1108
1109         return IXGBE_SUCCESS;
1110 }
1111
1112 /**
1113  * ixgbe_enable_eee_x550 - Enable EEE support
1114  * @hw: pointer to hardware structure
1115  */
1116 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
1117 {
1118         u32 link_reg;
1119         s32 status;
1120
1121         switch (hw->device_id) {
1122         case IXGBE_DEV_ID_X550EM_A_KR:
1123         case IXGBE_DEV_ID_X550EM_A_KR_L:
1124                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1125                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1126                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
1127                 if (status != IXGBE_SUCCESS)
1128                         return status;
1129
1130                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
1131                             IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
1132
1133                 /* Don't advertise FEC capability when EEE enabled. */
1134                 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1135
1136                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1137                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1138                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
1139                 if (status != IXGBE_SUCCESS)
1140                         return status;
1141                 break;
1142         default:
1143                 break;
1144         }
1145
1146         return IXGBE_SUCCESS;
1147 }
1148
1149 /**
1150  * ixgbe_disable_eee_x550 - Disable EEE support
1151  * @hw: pointer to hardware structure
1152  */
1153 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
1154 {
1155         u32 link_reg;
1156         s32 status;
1157
1158         switch (hw->device_id) {
1159         case IXGBE_DEV_ID_X550EM_X_KR:
1160         case IXGBE_DEV_ID_X550EM_A_KR:
1161         case IXGBE_DEV_ID_X550EM_A_KR_L:
1162                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1163                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1164                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
1165                 if (status != IXGBE_SUCCESS)
1166                         return status;
1167
1168                 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
1169                               IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
1170
1171                 /* Advertise FEC capability when EEE is disabled. */
1172                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1173
1174                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1175                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1176                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
1177                 if (status != IXGBE_SUCCESS)
1178                         return status;
1179                 break;
1180         default:
1181                 break;
1182         }
1183
1184         return IXGBE_SUCCESS;
1185 }
1186
1187 /**
1188  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
1189  *  @hw: pointer to the HW structure
1190  *  @enable_eee: boolean flag to enable EEE
1191  *
1192  *  Enable/disable EEE based on enable_eee flag.
1193  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
1194  *  are modified.
1195  *
1196  **/
1197 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
1198 {
1199         s32 status;
1200         u32 eeer;
1201
1202         DEBUGFUNC("ixgbe_setup_eee_X550");
1203
1204         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
1205         /* Enable or disable EEE per flag */
1206         if (enable_eee) {
1207                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1208
1209                 status = ixgbe_enable_eee_x550(hw);
1210                 if (status)
1211                         return status;
1212         } else {
1213                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1214
1215                 status = ixgbe_disable_eee_x550(hw);
1216                 if (status)
1217                         return status;
1218         }
1219         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1220
1221         return IXGBE_SUCCESS;
1222 }
1223
1224 /**
1225  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1226  * @hw: pointer to hardware structure
1227  * @enable: enable or disable source address pruning
1228  * @pool: Rx pool to set source address pruning for
1229  **/
1230 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1231                                            unsigned int pool)
1232 {
1233         u64 pfflp;
1234
1235         /* max rx pool is 63 */
1236         if (pool > 63)
1237                 return;
1238
1239         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1240         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1241
1242         if (enable)
1243                 pfflp |= (1ULL << pool);
1244         else
1245                 pfflp &= ~(1ULL << pool);
1246
1247         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1248         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1249 }
1250
1251 /**
1252  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1253  *  @hw: pointer to hardware structure
1254  *  @enable: enable or disable switch for Ethertype anti-spoofing
1255  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1256  *
1257  **/
1258 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1259                 bool enable, int vf)
1260 {
1261         int vf_target_reg = vf >> 3;
1262         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1263         u32 pfvfspoof;
1264
1265         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1266
1267         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1268         if (enable)
1269                 pfvfspoof |= (1 << vf_target_shift);
1270         else
1271                 pfvfspoof &= ~(1 << vf_target_shift);
1272
1273         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1274 }
1275
1276 /**
1277  * ixgbe_iosf_wait - Wait for IOSF command completion
1278  * @hw: pointer to hardware structure
1279  * @ctrl: pointer to location to receive final IOSF control value
1280  *
1281  * Returns failing status on timeout
1282  *
1283  * Note: ctrl can be NULL if the IOSF control register value is not needed
1284  **/
1285 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1286 {
1287         u32 i, command = 0;
1288
1289         /* Check every 10 usec to see if the address cycle completed.
1290          * The SB IOSF BUSY bit will clear when the operation is
1291          * complete
1292          */
1293         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1294                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1295                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1296                         break;
1297                 usec_delay(10);
1298         }
1299         if (ctrl)
1300                 *ctrl = command;
1301         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1302                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1303                 return IXGBE_ERR_PHY;
1304         }
1305
1306         return IXGBE_SUCCESS;
1307 }
1308
1309 /**
1310  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1311  *  of the IOSF device
1312  *  @hw: pointer to hardware structure
1313  *  @reg_addr: 32 bit PHY register to write
1314  *  @device_type: 3 bit device type
1315  *  @data: Data to write to the register
1316  **/
1317 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1318                             u32 device_type, u32 data)
1319 {
1320         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1321         u32 command, error;
1322         s32 ret;
1323
1324         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1325         if (ret != IXGBE_SUCCESS)
1326                 return ret;
1327
1328         ret = ixgbe_iosf_wait(hw, NULL);
1329         if (ret != IXGBE_SUCCESS)
1330                 goto out;
1331
1332         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1333                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1334
1335         /* Write IOSF control register */
1336         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1337
1338         /* Write IOSF data register */
1339         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1340
1341         ret = ixgbe_iosf_wait(hw, &command);
1342
1343         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1344                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1345                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1346                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1347                               "Failed to write, error %x\n", error);
1348                 ret = IXGBE_ERR_PHY;
1349         }
1350
1351 out:
1352         ixgbe_release_swfw_semaphore(hw, gssr);
1353         return ret;
1354 }
1355
1356 /**
1357  *  ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1358  *  @hw: pointer to hardware structure
1359  *  @reg_addr: 32 bit PHY register to write
1360  *  @device_type: 3 bit device type
1361  *  @data: Pointer to read data from the register
1362  **/
1363 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1364                            u32 device_type, u32 *data)
1365 {
1366         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1367         u32 command, error;
1368         s32 ret;
1369
1370         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1371         if (ret != IXGBE_SUCCESS)
1372                 return ret;
1373
1374         ret = ixgbe_iosf_wait(hw, NULL);
1375         if (ret != IXGBE_SUCCESS)
1376                 goto out;
1377
1378         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1379                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1380
1381         /* Write IOSF control register */
1382         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1383
1384         ret = ixgbe_iosf_wait(hw, &command);
1385
1386         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1387                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1388                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1389                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1390                                 "Failed to read, error %x\n", error);
1391                 ret = IXGBE_ERR_PHY;
1392         }
1393
1394         if (ret == IXGBE_SUCCESS)
1395                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1396
1397 out:
1398         ixgbe_release_swfw_semaphore(hw, gssr);
1399         return ret;
1400 }
1401
1402 /**
1403  * ixgbe_get_phy_token - Get the token for shared phy access
1404  * @hw: Pointer to hardware structure
1405  */
1406
1407 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1408 {
1409         struct ixgbe_hic_phy_token_req token_cmd;
1410         s32 status;
1411
1412         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1413         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1414         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1415         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1416         token_cmd.port_number = hw->bus.lan_id;
1417         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1418         token_cmd.pad = 0;
1419         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1420                                               sizeof(token_cmd),
1421                                               IXGBE_HI_COMMAND_TIMEOUT,
1422                                               true);
1423         if (status)
1424                 return status;
1425         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1426                 return IXGBE_SUCCESS;
1427         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1428                 return IXGBE_ERR_FW_RESP_INVALID;
1429
1430         return IXGBE_ERR_TOKEN_RETRY;
1431 }
1432
1433 /**
1434  * ixgbe_put_phy_token - Put the token for shared phy access
1435  * @hw: Pointer to hardware structure
1436  */
1437
1438 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1439 {
1440         struct ixgbe_hic_phy_token_req token_cmd;
1441         s32 status;
1442
1443         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1444         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1445         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1446         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1447         token_cmd.port_number = hw->bus.lan_id;
1448         token_cmd.command_type = FW_PHY_TOKEN_REL;
1449         token_cmd.pad = 0;
1450         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1451                                               sizeof(token_cmd),
1452                                               IXGBE_HI_COMMAND_TIMEOUT,
1453                                               true);
1454         if (status)
1455                 return status;
1456         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1457                 return IXGBE_SUCCESS;
1458
1459         DEBUGOUT("Put PHY Token host interface command failed");
1460         return IXGBE_ERR_FW_RESP_INVALID;
1461 }
1462
1463 /**
1464  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1465  *  of the IOSF device
1466  *  @hw: pointer to hardware structure
1467  *  @reg_addr: 32 bit PHY register to write
1468  *  @device_type: 3 bit device type
1469  *  @data: Data to write to the register
1470  **/
1471 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1472                                   u32 device_type, u32 data)
1473 {
1474         struct ixgbe_hic_internal_phy_req write_cmd;
1475         s32 status;
1476         UNREFERENCED_1PARAMETER(device_type);
1477
1478         memset(&write_cmd, 0, sizeof(write_cmd));
1479         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1480         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1481         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1482         write_cmd.port_number = hw->bus.lan_id;
1483         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1484         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1485         write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1486
1487         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1488                                               sizeof(write_cmd),
1489                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1490
1491         return status;
1492 }
1493
1494 /**
1495  *  ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1496  *  @hw: pointer to hardware structure
1497  *  @reg_addr: 32 bit PHY register to write
1498  *  @device_type: 3 bit device type
1499  *  @data: Pointer to read data from the register
1500  **/
1501 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1502                                  u32 device_type, u32 *data)
1503 {
1504         union {
1505                 struct ixgbe_hic_internal_phy_req cmd;
1506                 struct ixgbe_hic_internal_phy_resp rsp;
1507         } hic;
1508         s32 status;
1509         UNREFERENCED_1PARAMETER(device_type);
1510
1511         memset(&hic, 0, sizeof(hic));
1512         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1513         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1514         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1515         hic.cmd.port_number = hw->bus.lan_id;
1516         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1517         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1518
1519         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1520                                               sizeof(hic.cmd),
1521                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1522
1523         /* Extract the register value from the response. */
1524         *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1525
1526         return status;
1527 }
1528
1529 /**
1530  *  ixgbe_disable_mdd_X550
1531  *  @hw: pointer to hardware structure
1532  *
1533  *  Disable malicious driver detection
1534  **/
1535 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1536 {
1537         u32 reg;
1538
1539         DEBUGFUNC("ixgbe_disable_mdd_X550");
1540
1541         /* Disable MDD for TX DMA and interrupt */
1542         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1543         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1544         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1545
1546         /* Disable MDD for RX and interrupt */
1547         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1548         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1549         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1550 }
1551
1552 /**
1553  *  ixgbe_enable_mdd_X550
1554  *  @hw: pointer to hardware structure
1555  *
1556  *  Enable malicious driver detection
1557  **/
1558 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1559 {
1560         u32 reg;
1561
1562         DEBUGFUNC("ixgbe_enable_mdd_X550");
1563
1564         /* Enable MDD for TX DMA and interrupt */
1565         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1566         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1567         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1568
1569         /* Enable MDD for RX and interrupt */
1570         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1571         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1572         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1573 }
1574
1575 /**
1576  *  ixgbe_restore_mdd_vf_X550
1577  *  @hw: pointer to hardware structure
1578  *  @vf: vf index
1579  *
1580  *  Restore VF that was disabled during malicious driver detection event
1581  **/
1582 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1583 {
1584         u32 idx, reg, num_qs, start_q, bitmask;
1585
1586         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1587
1588         /* Map VF to queues */
1589         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1590         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1591         case IXGBE_MRQC_VMDQRT8TCEN:
1592                 num_qs = 8;  /* 16 VFs / pools */
1593                 bitmask = 0x000000FF;
1594                 break;
1595         case IXGBE_MRQC_VMDQRSS32EN:
1596         case IXGBE_MRQC_VMDQRT4TCEN:
1597                 num_qs = 4;  /* 32 VFs / pools */
1598                 bitmask = 0x0000000F;
1599                 break;
1600         default:            /* 64 VFs / pools */
1601                 num_qs = 2;
1602                 bitmask = 0x00000003;
1603                 break;
1604         }
1605         start_q = vf * num_qs;
1606
1607         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1608         idx = start_q / 32;
1609         reg = 0;
1610         reg |= (bitmask << (start_q % 32));
1611         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1612         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1613 }
1614
1615 /**
1616  *  ixgbe_mdd_event_X550
1617  *  @hw: pointer to hardware structure
1618  *  @vf_bitmap: vf bitmap of malicious vfs
1619  *
1620  *  Handle malicious driver detection event.
1621  **/
1622 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1623 {
1624         u32 wqbr;
1625         u32 i, j, reg, q, shift, vf, idx;
1626
1627         DEBUGFUNC("ixgbe_mdd_event_X550");
1628
1629         /* figure out pool size for mapping to vf's */
1630         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1631         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1632         case IXGBE_MRQC_VMDQRT8TCEN:
1633                 shift = 3;  /* 16 VFs / pools */
1634                 break;
1635         case IXGBE_MRQC_VMDQRSS32EN:
1636         case IXGBE_MRQC_VMDQRT4TCEN:
1637                 shift = 2;  /* 32 VFs / pools */
1638                 break;
1639         default:
1640                 shift = 1;  /* 64 VFs / pools */
1641                 break;
1642         }
1643
1644         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1645         for (i = 0; i < 4; i++) {
1646                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1647                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1648
1649                 if (!wqbr)
1650                         continue;
1651
1652                 /* Get malicious queue */
1653                 for (j = 0; j < 32 && wqbr; j++) {
1654
1655                         if (!(wqbr & (1 << j)))
1656                                 continue;
1657
1658                         /* Get queue from bitmask */
1659                         q = j + (i * 32);
1660
1661                         /* Map queue to vf */
1662                         vf = (q >> shift);
1663
1664                         /* Set vf bit in vf_bitmap */
1665                         idx = vf / 32;
1666                         vf_bitmap[idx] |= (1 << (vf % 32));
1667                         wqbr &= ~(1 << j);
1668                 }
1669         }
1670 }
1671
1672 /**
1673  *  ixgbe_get_media_type_X550em - Get media type
1674  *  @hw: pointer to hardware structure
1675  *
1676  *  Returns the media type (fiber, copper, backplane)
1677  */
1678 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1679 {
1680         enum ixgbe_media_type media_type;
1681
1682         DEBUGFUNC("ixgbe_get_media_type_X550em");
1683
1684         /* Detect if there is a copper PHY attached. */
1685         switch (hw->device_id) {
1686         case IXGBE_DEV_ID_X550EM_X_KR:
1687         case IXGBE_DEV_ID_X550EM_X_KX4:
1688         case IXGBE_DEV_ID_X550EM_A_KR:
1689         case IXGBE_DEV_ID_X550EM_A_KR_L:
1690                 media_type = ixgbe_media_type_backplane;
1691                 break;
1692         case IXGBE_DEV_ID_X550EM_X_SFP:
1693         case IXGBE_DEV_ID_X550EM_A_SFP:
1694         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1695         case IXGBE_DEV_ID_X550EM_A_QSFP:
1696         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1697                 media_type = ixgbe_media_type_fiber;
1698                 break;
1699         case IXGBE_DEV_ID_X550EM_X_1G_T:
1700         case IXGBE_DEV_ID_X550EM_X_10G_T:
1701         case IXGBE_DEV_ID_X550EM_A_10G_T:
1702                 media_type = ixgbe_media_type_copper;
1703                 break;
1704         case IXGBE_DEV_ID_X550EM_A_SGMII:
1705         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1706                 media_type = ixgbe_media_type_backplane;
1707                 hw->phy.type = ixgbe_phy_sgmii;
1708                 break;
1709         case IXGBE_DEV_ID_X550EM_A_1G_T:
1710         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1711                 media_type = ixgbe_media_type_copper;
1712                 break;
1713         default:
1714                 media_type = ixgbe_media_type_unknown;
1715                 break;
1716         }
1717         return media_type;
1718 }
1719
1720 /**
1721  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1722  *  @hw: pointer to hardware structure
1723  *  @linear: true if SFP module is linear
1724  */
1725 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1726 {
1727         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1728
1729         switch (hw->phy.sfp_type) {
1730         case ixgbe_sfp_type_not_present:
1731                 return IXGBE_ERR_SFP_NOT_PRESENT;
1732         case ixgbe_sfp_type_da_cu_core0:
1733         case ixgbe_sfp_type_da_cu_core1:
1734                 *linear = true;
1735                 break;
1736         case ixgbe_sfp_type_srlr_core0:
1737         case ixgbe_sfp_type_srlr_core1:
1738         case ixgbe_sfp_type_da_act_lmt_core0:
1739         case ixgbe_sfp_type_da_act_lmt_core1:
1740         case ixgbe_sfp_type_1g_sx_core0:
1741         case ixgbe_sfp_type_1g_sx_core1:
1742         case ixgbe_sfp_type_1g_lx_core0:
1743         case ixgbe_sfp_type_1g_lx_core1:
1744                 *linear = false;
1745                 break;
1746         case ixgbe_sfp_type_unknown:
1747         case ixgbe_sfp_type_1g_cu_core0:
1748         case ixgbe_sfp_type_1g_cu_core1:
1749         default:
1750                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1751         }
1752
1753         return IXGBE_SUCCESS;
1754 }
1755
1756 /**
1757  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1758  *  @hw: pointer to hardware structure
1759  *
1760  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1761  **/
1762 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1763 {
1764         s32 status;
1765         bool linear;
1766
1767         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1768
1769         status = ixgbe_identify_module_generic(hw);
1770
1771         if (status != IXGBE_SUCCESS)
1772                 return status;
1773
1774         /* Check if SFP module is supported */
1775         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1776
1777         return status;
1778 }
1779
1780 /**
1781  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1782  *  @hw: pointer to hardware structure
1783  */
1784 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1785 {
1786         s32 status;
1787         bool linear;
1788
1789         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1790
1791         /* Check if SFP module is supported */
1792         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1793
1794         if (status != IXGBE_SUCCESS)
1795                 return status;
1796
1797         ixgbe_init_mac_link_ops_X550em(hw);
1798         hw->phy.ops.reset = NULL;
1799
1800         return IXGBE_SUCCESS;
1801 }
1802
1803 /**
1804 *  ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1805 *  internal PHY
1806 *  @hw: pointer to hardware structure
1807 **/
1808 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1809 {
1810         s32 status;
1811         u32 link_ctrl;
1812
1813         /* Restart auto-negotiation. */
1814         status = hw->mac.ops.read_iosf_sb_reg(hw,
1815                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1816                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1817
1818         if (status) {
1819                 DEBUGOUT("Auto-negotiation did not complete\n");
1820                 return status;
1821         }
1822
1823         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1824         status = hw->mac.ops.write_iosf_sb_reg(hw,
1825                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1826                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1827
1828         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1829                 u32 flx_mask_st20;
1830
1831                 /* Indicate to FW that AN restart has been asserted */
1832                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1833                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1834                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1835
1836                 if (status) {
1837                         DEBUGOUT("Auto-negotiation did not complete\n");
1838                         return status;
1839                 }
1840
1841                 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1842                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1843                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1844                                 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1845         }
1846
1847         return status;
1848 }
1849
1850 /**
1851  * ixgbe_setup_sgmii - Set up link for sgmii
1852  * @hw: pointer to hardware structure
1853  */
1854 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1855                              bool autoneg_wait)
1856 {
1857         struct ixgbe_mac_info *mac = &hw->mac;
1858         u32 lval, sval, flx_val;
1859         s32 rc;
1860
1861         rc = mac->ops.read_iosf_sb_reg(hw,
1862                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1863                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1864         if (rc)
1865                 return rc;
1866
1867         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1868         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1869         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1870         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1871         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1872         rc = mac->ops.write_iosf_sb_reg(hw,
1873                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1874                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1875         if (rc)
1876                 return rc;
1877
1878         rc = mac->ops.read_iosf_sb_reg(hw,
1879                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1880                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1881         if (rc)
1882                 return rc;
1883
1884         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1885         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1886         rc = mac->ops.write_iosf_sb_reg(hw,
1887                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1888                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1889         if (rc)
1890                 return rc;
1891
1892         rc = mac->ops.read_iosf_sb_reg(hw,
1893                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1894                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1895         if (rc)
1896                 return rc;
1897
1898         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1899         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1900         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1901         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1902         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1903
1904         rc = mac->ops.write_iosf_sb_reg(hw,
1905                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1906                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1907         if (rc)
1908                 return rc;
1909
1910         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1911         if (rc)
1912                 return rc;
1913
1914         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1915 }
1916
1917 /**
1918  * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs
1919  * @hw: pointer to hardware structure
1920  */
1921 STATIC s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1922                                 bool autoneg_wait)
1923 {
1924         struct ixgbe_mac_info *mac = &hw->mac;
1925         u32 lval, sval, flx_val;
1926         s32 rc;
1927
1928         rc = mac->ops.read_iosf_sb_reg(hw,
1929                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1930                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1931         if (rc)
1932                 return rc;
1933
1934         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1935         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1936         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1937         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1938         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1939         rc = mac->ops.write_iosf_sb_reg(hw,
1940                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1941                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1942         if (rc)
1943                 return rc;
1944
1945         rc = mac->ops.read_iosf_sb_reg(hw,
1946                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1947                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1948         if (rc)
1949                 return rc;
1950
1951         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1952         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1953         rc = mac->ops.write_iosf_sb_reg(hw,
1954                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1955                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1956         if (rc)
1957                 return rc;
1958
1959         rc = mac->ops.write_iosf_sb_reg(hw,
1960                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1961                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1962         if (rc)
1963                 return rc;
1964
1965         rc = mac->ops.read_iosf_sb_reg(hw,
1966                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1967                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1968         if (rc)
1969                 return rc;
1970
1971         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1972         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
1973         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1974         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1975         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1976
1977         rc = mac->ops.write_iosf_sb_reg(hw,
1978                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1979                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1980         if (rc)
1981                 return rc;
1982
1983         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1984
1985         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1986 }
1987
1988 /**
1989  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1990  *  @hw: pointer to hardware structure
1991  */
1992 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1993 {
1994         struct ixgbe_mac_info *mac = &hw->mac;
1995
1996         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1997
1998         switch (hw->mac.ops.get_media_type(hw)) {
1999         case ixgbe_media_type_fiber:
2000                 /* CS4227 does not support autoneg, so disable the laser control
2001                  * functions for SFP+ fiber
2002                  */
2003                 mac->ops.disable_tx_laser = NULL;
2004                 mac->ops.enable_tx_laser = NULL;
2005                 mac->ops.flap_tx_laser = NULL;
2006                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
2007                 mac->ops.set_rate_select_speed =
2008                                         ixgbe_set_soft_rate_select_speed;
2009
2010                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
2011                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
2012                         mac->ops.setup_mac_link =
2013                                                 ixgbe_setup_mac_link_sfp_x550a;
2014                 else
2015                         mac->ops.setup_mac_link =
2016                                                 ixgbe_setup_mac_link_sfp_x550em;
2017                 break;
2018         case ixgbe_media_type_copper:
2019                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
2020                         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2021                             hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
2022                                 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
2023                                 mac->ops.check_link =
2024                                                    ixgbe_check_mac_link_generic;
2025                         } else {
2026                                 mac->ops.setup_link =
2027                                                   ixgbe_setup_mac_link_t_X550em;
2028                         }
2029                 } else {
2030                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2031                         mac->ops.check_link = ixgbe_check_link_t_X550em;
2032                 }
2033                 break;
2034         case ixgbe_media_type_backplane:
2035                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
2036                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
2037                         mac->ops.setup_link = ixgbe_setup_sgmii;
2038                 break;
2039         default:
2040                 break;
2041         }
2042 }
2043
2044 /**
2045  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
2046  *  @hw: pointer to hardware structure
2047  *  @speed: pointer to link speed
2048  *  @autoneg: true when autoneg or autotry is enabled
2049  */
2050 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
2051                                        ixgbe_link_speed *speed,
2052                                        bool *autoneg)
2053 {
2054         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
2055
2056
2057         if (hw->phy.type == ixgbe_phy_fw) {
2058                 *autoneg = true;
2059                 *speed = hw->phy.speeds_supported;
2060                 return 0;
2061         }
2062
2063         /* SFP */
2064         if (hw->phy.media_type == ixgbe_media_type_fiber) {
2065
2066                 /* CS4227 SFP must not enable auto-negotiation */
2067                 *autoneg = false;
2068
2069                 /* Check if 1G SFP module. */
2070                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
2071                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
2072                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
2073                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
2074                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
2075                         return IXGBE_SUCCESS;
2076                 }
2077
2078                 /* Link capabilities are based on SFP */
2079                 if (hw->phy.multispeed_fiber)
2080                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
2081                                  IXGBE_LINK_SPEED_1GB_FULL;
2082                 else
2083                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
2084         } else {
2085                 switch (hw->phy.type) {
2086                 case ixgbe_phy_sgmii:
2087                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
2088                         break;
2089                 case ixgbe_phy_x550em_kr:
2090                         if (hw->mac.type == ixgbe_mac_X550EM_a) {
2091                                 /* check different backplane modes */
2092                                 if (hw->phy.nw_mng_if_sel &
2093                                            IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
2094                                         *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
2095                                         break;
2096                                 } else if (hw->device_id ==
2097                                                    IXGBE_DEV_ID_X550EM_A_KR_L) {
2098                                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
2099                                         break;
2100                                 }
2101                         }
2102                         /* fall through */
2103                 default:
2104                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
2105                                  IXGBE_LINK_SPEED_1GB_FULL;
2106                         break;
2107                 }
2108                 *autoneg = true;
2109         }
2110
2111         return IXGBE_SUCCESS;
2112 }
2113
2114 /**
2115  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
2116  * @hw: pointer to hardware structure
2117  * @lsc: pointer to boolean flag which indicates whether external Base T
2118  *       PHY interrupt is lsc
2119  *
2120  * Determime if external Base T PHY interrupt cause is high temperature
2121  * failure alarm or link status change.
2122  *
2123  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2124  * failure alarm, else return PHY access status.
2125  */
2126 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
2127 {
2128         u32 status;
2129         u16 reg;
2130
2131         *lsc = false;
2132
2133         /* Vendor alarm triggered */
2134         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2135                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2136                                       &reg);
2137
2138         if (status != IXGBE_SUCCESS ||
2139             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
2140                 return status;
2141
2142         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
2143         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
2144                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2145                                       &reg);
2146
2147         if (status != IXGBE_SUCCESS ||
2148             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2149             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
2150                 return status;
2151
2152         /* Global alarm triggered */
2153         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
2154                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2155                                       &reg);
2156
2157         if (status != IXGBE_SUCCESS)
2158                 return status;
2159
2160         /* If high temperature failure, then return over temp error and exit */
2161         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2162                 /* power down the PHY in case the PHY FW didn't already */
2163                 ixgbe_set_copper_phy_power(hw, false);
2164                 return IXGBE_ERR_OVERTEMP;
2165         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2166                 /*  device fault alarm triggered */
2167                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2168                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2169                                           &reg);
2170
2171                 if (status != IXGBE_SUCCESS)
2172                         return status;
2173
2174                 /* if device fault was due to high temp alarm handle and exit */
2175                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2176                         /* power down the PHY in case the PHY FW didn't */
2177                         ixgbe_set_copper_phy_power(hw, false);
2178                         return IXGBE_ERR_OVERTEMP;
2179                 }
2180         }
2181
2182         /* Vendor alarm 2 triggered */
2183         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2184                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2185
2186         if (status != IXGBE_SUCCESS ||
2187             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2188                 return status;
2189
2190         /* link connect/disconnect event occurred */
2191         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2192                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2193
2194         if (status != IXGBE_SUCCESS)
2195                 return status;
2196
2197         /* Indicate LSC */
2198         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2199                 *lsc = true;
2200
2201         return IXGBE_SUCCESS;
2202 }
2203
2204 /**
2205  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2206  * @hw: pointer to hardware structure
2207  *
2208  * Enable link status change and temperature failure alarm for the external
2209  * Base T PHY
2210  *
2211  * Returns PHY access status
2212  */
2213 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2214 {
2215         u32 status;
2216         u16 reg;
2217         bool lsc;
2218
2219         /* Clear interrupt flags */
2220         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2221
2222         /* Enable link status change alarm */
2223
2224         /* Enable the LASI interrupts on X552 devices to receive notifications
2225          * of the link configurations of the external PHY and correspondingly
2226          * support the configuration of the internal iXFI link, since iXFI does
2227          * not support auto-negotiation. This is not required for X553 devices
2228          * having KR support, which performs auto-negotiations and which is used
2229          * as the internal link to the external PHY. Hence adding a check here
2230          * to avoid enabling LASI interrupts for X553 devices.
2231          */
2232         if (hw->mac.type != ixgbe_mac_X550EM_a) {
2233                 status = hw->phy.ops.read_reg(hw,
2234                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2235                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2236
2237                 if (status != IXGBE_SUCCESS)
2238                         return status;
2239
2240                 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2241
2242                 status = hw->phy.ops.write_reg(hw,
2243                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2244                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2245
2246                 if (status != IXGBE_SUCCESS)
2247                         return status;
2248         }
2249
2250         /* Enable high temperature failure and global fault alarms */
2251         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2252                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2253                                       &reg);
2254
2255         if (status != IXGBE_SUCCESS)
2256                 return status;
2257
2258         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2259                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2260
2261         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2262                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2263                                        reg);
2264
2265         if (status != IXGBE_SUCCESS)
2266                 return status;
2267
2268         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2269         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2270                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2271                                       &reg);
2272
2273         if (status != IXGBE_SUCCESS)
2274                 return status;
2275
2276         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2277                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2278
2279         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2280                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2281                                        reg);
2282
2283         if (status != IXGBE_SUCCESS)
2284                 return status;
2285
2286         /* Enable chip-wide vendor alarm */
2287         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2288                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2289                                       &reg);
2290
2291         if (status != IXGBE_SUCCESS)
2292                 return status;
2293
2294         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2295
2296         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2297                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2298                                        reg);
2299
2300         return status;
2301 }
2302
2303 /**
2304  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2305  *  @hw: pointer to hardware structure
2306  *  @speed: link speed
2307  *
2308  *  Configures the integrated KR PHY.
2309  **/
2310 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2311                                        ixgbe_link_speed speed)
2312 {
2313         s32 status;
2314         u32 reg_val;
2315
2316         status = hw->mac.ops.read_iosf_sb_reg(hw,
2317                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2318                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2319         if (status)
2320                 return status;
2321
2322         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2323         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2324                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2325
2326         /* Advertise 10G support. */
2327         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2328                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2329
2330         /* Advertise 1G support. */
2331         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2332                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2333
2334         status = hw->mac.ops.write_iosf_sb_reg(hw,
2335                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2336                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2337
2338         if (hw->mac.type == ixgbe_mac_X550EM_a) {
2339                 /* Set lane mode  to KR auto negotiation */
2340                 status = hw->mac.ops.read_iosf_sb_reg(hw,
2341                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2342                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2343
2344                 if (status)
2345                         return status;
2346
2347                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2348                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2349                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2350                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2351                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2352
2353                 status = hw->mac.ops.write_iosf_sb_reg(hw,
2354                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2355                                     IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2356         }
2357
2358         return ixgbe_restart_an_internal_phy_x550em(hw);
2359 }
2360
2361 /**
2362  * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
2363  * @hw: pointer to hardware structure
2364  */
2365 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
2366 {
2367         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2368         s32 rc;
2369
2370         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2371                 return IXGBE_SUCCESS;
2372
2373         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
2374         if (rc)
2375                 return rc;
2376         memset(store, 0, sizeof(store));
2377
2378         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
2379         if (rc)
2380                 return rc;
2381
2382         return ixgbe_setup_fw_link(hw);
2383 }
2384
2385 /**
2386  * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
2387  * @hw: pointer to hardware structure
2388  */
2389 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
2390 {
2391         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2392         s32 rc;
2393
2394         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
2395         if (rc)
2396                 return rc;
2397
2398         if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
2399                 ixgbe_shutdown_fw_phy(hw);
2400                 return IXGBE_ERR_OVERTEMP;
2401         }
2402         return IXGBE_SUCCESS;
2403 }
2404
2405 /**
2406  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2407  *  @hw: pointer to hardware structure
2408  *
2409  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2410  *  values.
2411  **/
2412 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2413 {
2414         /* Save NW management interface connected on board. This is used
2415          * to determine internal PHY mode.
2416          */
2417         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2418
2419         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2420          * PHY address. This register field was has only been used for X552.
2421          */
2422         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2423             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2424                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2425                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2426                                IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2427         }
2428
2429         return IXGBE_SUCCESS;
2430 }
2431
2432 /**
2433  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2434  *  @hw: pointer to hardware structure
2435  *
2436  *  Initialize any function pointers that were not able to be
2437  *  set during init_shared_code because the PHY/SFP type was
2438  *  not known.  Perform the SFP init if necessary.
2439  */
2440 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2441 {
2442         struct ixgbe_phy_info *phy = &hw->phy;
2443         s32 ret_val;
2444
2445         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2446
2447         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2448                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2449                 ixgbe_setup_mux_ctl(hw);
2450                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2451         }
2452
2453         switch (hw->device_id) {
2454         case IXGBE_DEV_ID_X550EM_A_1G_T:
2455         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2456                 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2457                 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2458                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2459                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2460                 phy->ops.check_overtemp = ixgbe_check_overtemp_fw;
2461                 if (hw->bus.lan_id)
2462                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2463                 else
2464                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2465
2466                 break;
2467         case IXGBE_DEV_ID_X550EM_A_10G_T:
2468         case IXGBE_DEV_ID_X550EM_A_SFP:
2469                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2470                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2471                 if (hw->bus.lan_id)
2472                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2473                 else
2474                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2475                 break;
2476         case IXGBE_DEV_ID_X550EM_X_SFP:
2477                 /* set up for CS4227 usage */
2478                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2479                 break;
2480         default:
2481                 break;
2482         }
2483
2484         /* Identify the PHY or SFP module */
2485         ret_val = phy->ops.identify(hw);
2486         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2487                 return ret_val;
2488
2489         /* Setup function pointers based on detected hardware */
2490         ixgbe_init_mac_link_ops_X550em(hw);
2491         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2492                 phy->ops.reset = NULL;
2493
2494         /* Set functions pointers based on phy type */
2495         switch (hw->phy.type) {
2496         case ixgbe_phy_x550em_kx4:
2497                 phy->ops.setup_link = NULL;
2498                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2499                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2500                 break;
2501         case ixgbe_phy_x550em_kr:
2502                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2503                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2504                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2505                 break;
2506         case ixgbe_phy_x550em_ext_t:
2507                 /* If internal link mode is XFI, then setup iXFI internal link,
2508                  * else setup KR now.
2509                  */
2510                 phy->ops.setup_internal_link =
2511                                               ixgbe_setup_internal_phy_t_x550em;
2512
2513                 /* setup SW LPLU only for first revision of X550EM_x */
2514                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2515                     !(IXGBE_FUSES0_REV_MASK &
2516                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2517                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2518
2519                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2520                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2521                 break;
2522         case ixgbe_phy_sgmii:
2523                 phy->ops.setup_link = NULL;
2524                 break;
2525         case ixgbe_phy_fw:
2526                 phy->ops.setup_link = ixgbe_setup_fw_link;
2527                 phy->ops.reset = ixgbe_reset_phy_fw;
2528                 break;
2529         default:
2530                 break;
2531         }
2532         return ret_val;
2533 }
2534
2535 /**
2536  * ixgbe_set_mdio_speed - Set MDIO clock speed
2537  *  @hw: pointer to hardware structure
2538  */
2539 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2540 {
2541         u32 hlreg0;
2542
2543         switch (hw->device_id) {
2544         case IXGBE_DEV_ID_X550EM_X_10G_T:
2545         case IXGBE_DEV_ID_X550EM_A_SGMII:
2546         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2547         case IXGBE_DEV_ID_X550EM_A_10G_T:
2548         case IXGBE_DEV_ID_X550EM_A_SFP:
2549         case IXGBE_DEV_ID_X550EM_A_QSFP:
2550                 /* Config MDIO clock speed before the first MDIO PHY access */
2551                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2552                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2553                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2554                 break;
2555         case IXGBE_DEV_ID_X550EM_A_1G_T:
2556         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2557                 /* Select fast MDIO clock speed for these devices */
2558                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2559                 hlreg0 |= IXGBE_HLREG0_MDCSPD;
2560                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2561                 break;
2562         default:
2563                 break;
2564         }
2565 }
2566
2567 /**
2568  *  ixgbe_reset_hw_X550em - Perform hardware reset
2569  *  @hw: pointer to hardware structure
2570  *
2571  *  Resets the hardware by resetting the transmit and receive units, masks
2572  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2573  *  reset.
2574  */
2575 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2576 {
2577         ixgbe_link_speed link_speed;
2578         s32 status;
2579         u32 ctrl = 0;
2580         u32 i;
2581         bool link_up = false;
2582
2583         DEBUGFUNC("ixgbe_reset_hw_X550em");
2584
2585         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2586         status = hw->mac.ops.stop_adapter(hw);
2587         if (status != IXGBE_SUCCESS)
2588                 return status;
2589
2590         /* flush pending Tx transactions */
2591         ixgbe_clear_tx_pending(hw);
2592
2593         ixgbe_set_mdio_speed(hw);
2594
2595         /* PHY ops must be identified and initialized prior to reset */
2596         status = hw->phy.ops.init(hw);
2597
2598         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2599                 return status;
2600
2601         /* start the external PHY */
2602         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2603                 status = ixgbe_init_ext_t_x550em(hw);
2604                 if (status)
2605                         return status;
2606         }
2607
2608         /* Setup SFP module if there is one present. */
2609         if (hw->phy.sfp_setup_needed) {
2610                 status = hw->mac.ops.setup_sfp(hw);
2611                 hw->phy.sfp_setup_needed = false;
2612         }
2613
2614         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2615                 return status;
2616
2617         /* Reset PHY */
2618         if (!hw->phy.reset_disable && hw->phy.ops.reset) {
2619                 if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP)
2620                         return IXGBE_ERR_OVERTEMP;
2621         }
2622
2623 mac_reset_top:
2624         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2625          * If link reset is used when link is up, it might reset the PHY when
2626          * mng is using it.  If link is down or the flag to force full link
2627          * reset is set, then perform link reset.
2628          */
2629         ctrl = IXGBE_CTRL_LNK_RST;
2630         if (!hw->force_full_reset) {
2631                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2632                 if (link_up)
2633                         ctrl = IXGBE_CTRL_RST;
2634         }
2635
2636         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2637         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2638         IXGBE_WRITE_FLUSH(hw);
2639
2640         /* Poll for reset bit to self-clear meaning reset is complete */
2641         for (i = 0; i < 10; i++) {
2642                 usec_delay(1);
2643                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2644                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2645                         break;
2646         }
2647
2648         if (ctrl & IXGBE_CTRL_RST_MASK) {
2649                 status = IXGBE_ERR_RESET_FAILED;
2650                 DEBUGOUT("Reset polling failed to complete.\n");
2651         }
2652
2653         msec_delay(50);
2654
2655         /* Double resets are required for recovery from certain error
2656          * conditions.  Between resets, it is necessary to stall to
2657          * allow time for any pending HW events to complete.
2658          */
2659         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2660                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2661                 goto mac_reset_top;
2662         }
2663
2664         /* Store the permanent mac address */
2665         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2666
2667         /* Store MAC address from RAR0, clear receive address registers, and
2668          * clear the multicast table.  Also reset num_rar_entries to 128,
2669          * since we modify this value when programming the SAN MAC address.
2670          */
2671         hw->mac.num_rar_entries = 128;
2672         hw->mac.ops.init_rx_addrs(hw);
2673
2674         ixgbe_set_mdio_speed(hw);
2675
2676         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2677                 ixgbe_setup_mux_ctl(hw);
2678
2679         return status;
2680 }
2681
2682 /**
2683  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2684  * @hw: pointer to hardware structure
2685  */
2686 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2687 {
2688         u32 status;
2689         u16 reg;
2690
2691         status = hw->phy.ops.read_reg(hw,
2692                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2693                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2694                                       &reg);
2695
2696         if (status != IXGBE_SUCCESS)
2697                 return status;
2698
2699         /* If PHY FW reset completed bit is set then this is the first
2700          * SW instance after a power on so the PHY FW must be un-stalled.
2701          */
2702         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2703                 status = hw->phy.ops.read_reg(hw,
2704                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2705                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2706                                         &reg);
2707
2708                 if (status != IXGBE_SUCCESS)
2709                         return status;
2710
2711                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2712
2713                 status = hw->phy.ops.write_reg(hw,
2714                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2715                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2716                                         reg);
2717
2718                 if (status != IXGBE_SUCCESS)
2719                         return status;
2720         }
2721
2722         return status;
2723 }
2724
2725 /**
2726  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2727  *  @hw: pointer to hardware structure
2728  *
2729  *  Configures the integrated KR PHY for X550EM_x.
2730  **/
2731 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2732 {
2733         if (hw->mac.type != ixgbe_mac_X550EM_x)
2734                 return IXGBE_SUCCESS;
2735
2736         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2737 }
2738
2739 /**
2740  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2741  *  @hw: pointer to hardware structure
2742  *
2743  *  Configure the external PHY and the integrated KR PHY for SFP support.
2744  **/
2745 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2746                                     ixgbe_link_speed speed,
2747                                     bool autoneg_wait_to_complete)
2748 {
2749         s32 ret_val;
2750         u16 reg_slice, reg_val;
2751         bool setup_linear = false;
2752         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2753
2754         /* Check if SFP module is supported and linear */
2755         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2756
2757         /* If no SFP module present, then return success. Return success since
2758          * there is no reason to configure CS4227 and SFP not present error is
2759          * not excepted in the setup MAC link flow.
2760          */
2761         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2762                 return IXGBE_SUCCESS;
2763
2764         if (ret_val != IXGBE_SUCCESS)
2765                 return ret_val;
2766
2767         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2768                 /* Configure CS4227 LINE side to 10G SR. */
2769                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2770                             (hw->bus.lan_id << 12);
2771                 reg_val = IXGBE_CS4227_SPEED_10G;
2772                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2773                                                   reg_val);
2774
2775                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2776                             (hw->bus.lan_id << 12);
2777                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2778                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2779                                                   reg_val);
2780
2781                 /* Configure CS4227 for HOST connection rate then type. */
2782                 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2783                             (hw->bus.lan_id << 12);
2784                 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2785                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2786                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2787                                                   reg_val);
2788
2789                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2790                             (hw->bus.lan_id << 12);
2791                 if (setup_linear)
2792                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2793                 else
2794                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2795                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2796                                                   reg_val);
2797
2798                 /* Setup XFI internal link. */
2799                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2800         } else {
2801                 /* Configure internal PHY for KR/KX. */
2802                 ixgbe_setup_kr_speed_x550em(hw, speed);
2803
2804                 /* Configure CS4227 LINE side to proper mode. */
2805                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2806                             (hw->bus.lan_id << 12);
2807                 if (setup_linear)
2808                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2809                 else
2810                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2811                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2812                                                   reg_val);
2813         }
2814         return ret_val;
2815 }
2816
2817 /**
2818  *  ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2819  *  @hw: pointer to hardware structure
2820  *  @speed: the link speed to force
2821  *
2822  *  Configures the integrated PHY for native SFI mode. Used to connect the
2823  *  internal PHY directly to an SFP cage, without autonegotiation.
2824  **/
2825 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2826 {
2827         struct ixgbe_mac_info *mac = &hw->mac;
2828         s32 status;
2829         u32 reg_val;
2830
2831         /* Disable all AN and force speed to 10G Serial. */
2832         status = mac->ops.read_iosf_sb_reg(hw,
2833                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2834                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2835         if (status != IXGBE_SUCCESS)
2836                 return status;
2837
2838         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2839         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2840         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2841         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2842
2843         /* Select forced link speed for internal PHY. */
2844         switch (*speed) {
2845         case IXGBE_LINK_SPEED_10GB_FULL:
2846                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2847                 break;
2848         case IXGBE_LINK_SPEED_1GB_FULL:
2849                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2850                 break;
2851         default:
2852                 /* Other link speeds are not supported by internal PHY. */
2853                 return IXGBE_ERR_LINK_SETUP;
2854         }
2855
2856         status = mac->ops.write_iosf_sb_reg(hw,
2857                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2858                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2859
2860         /* Toggle port SW reset by AN reset. */
2861         status = ixgbe_restart_an_internal_phy_x550em(hw);
2862
2863         return status;
2864 }
2865
2866 /**
2867  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2868  *  @hw: pointer to hardware structure
2869  *
2870  *  Configure the the integrated PHY for SFP support.
2871  **/
2872 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2873                                     ixgbe_link_speed speed,
2874                                     bool autoneg_wait_to_complete)
2875 {
2876         s32 ret_val;
2877         u16 reg_phy_ext;
2878         bool setup_linear = false;
2879         u32 reg_slice, reg_phy_int, slice_offset;
2880
2881         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2882
2883         /* Check if SFP module is supported and linear */
2884         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2885
2886         /* If no SFP module present, then return success. Return success since
2887          * SFP not present error is not excepted in the setup MAC link flow.
2888          */
2889         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2890                 return IXGBE_SUCCESS;
2891
2892         if (ret_val != IXGBE_SUCCESS)
2893                 return ret_val;
2894
2895         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2896                 /* Configure internal PHY for native SFI based on module type */
2897                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2898                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2899                                    IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2900
2901                 if (ret_val != IXGBE_SUCCESS)
2902                         return ret_val;
2903
2904                 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2905                 if (!setup_linear)
2906                         reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2907
2908                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2909                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2910                                    IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2911
2912                 if (ret_val != IXGBE_SUCCESS)
2913                         return ret_val;
2914
2915                 /* Setup SFI internal link. */
2916                 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2917         } else {
2918                 /* Configure internal PHY for KR/KX. */
2919                 ixgbe_setup_kr_speed_x550em(hw, speed);
2920
2921                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2922                         /* Find Address */
2923                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2924                         return IXGBE_ERR_PHY_ADDR_INVALID;
2925                 }
2926
2927                 /* Get external PHY SKU id */
2928                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
2929                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2930
2931                 if (ret_val != IXGBE_SUCCESS)
2932                         return ret_val;
2933
2934                 /* When configuring quad port CS4223, the MAC instance is part
2935                  * of the slice offset.
2936                  */
2937                 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
2938                         slice_offset = (hw->bus.lan_id +
2939                                         (hw->bus.instance_id << 1)) << 12;
2940                 else
2941                         slice_offset = hw->bus.lan_id << 12;
2942
2943                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2944                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2945                 if (setup_linear)
2946                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2947                 else
2948                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2949                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2950                                          IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2951         }
2952         return ret_val;
2953 }
2954
2955 /**
2956  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2957  *  @hw: pointer to hardware structure
2958  *
2959  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2960  **/
2961 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2962 {
2963         struct ixgbe_mac_info *mac = &hw->mac;
2964         s32 status;
2965         u32 reg_val;
2966
2967         /* Disable training protocol FSM. */
2968         status = mac->ops.read_iosf_sb_reg(hw,
2969                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2970                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2971         if (status != IXGBE_SUCCESS)
2972                 return status;
2973         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2974         status = mac->ops.write_iosf_sb_reg(hw,
2975                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2976                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2977         if (status != IXGBE_SUCCESS)
2978                 return status;
2979
2980         /* Disable Flex from training TXFFE. */
2981         status = mac->ops.read_iosf_sb_reg(hw,
2982                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2983                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2984         if (status != IXGBE_SUCCESS)
2985                 return status;
2986         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2987         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2988         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2989         status = mac->ops.write_iosf_sb_reg(hw,
2990                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2991                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2992         if (status != IXGBE_SUCCESS)
2993                 return status;
2994         status = mac->ops.read_iosf_sb_reg(hw,
2995                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2996                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2997         if (status != IXGBE_SUCCESS)
2998                 return status;
2999         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
3000         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
3001         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
3002         status = mac->ops.write_iosf_sb_reg(hw,
3003                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
3004                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3005         if (status != IXGBE_SUCCESS)
3006                 return status;
3007
3008         /* Enable override for coefficients. */
3009         status = mac->ops.read_iosf_sb_reg(hw,
3010                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
3011                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3012         if (status != IXGBE_SUCCESS)
3013                 return status;
3014         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
3015         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
3016         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
3017         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
3018         status = mac->ops.write_iosf_sb_reg(hw,
3019                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
3020                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3021         return status;
3022 }
3023
3024 /**
3025  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
3026  *  @hw: pointer to hardware structure
3027  *  @speed: the link speed to force
3028  *
3029  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
3030  *  internal and external PHY at a specific speed, without autonegotiation.
3031  **/
3032 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
3033 {
3034         struct ixgbe_mac_info *mac = &hw->mac;
3035         s32 status;
3036         u32 reg_val;
3037
3038         /* iXFI is only supported with X552 */
3039         if (mac->type != ixgbe_mac_X550EM_x)
3040                 return IXGBE_ERR_LINK_SETUP;
3041
3042         /* Disable AN and force speed to 10G Serial. */
3043         status = mac->ops.read_iosf_sb_reg(hw,
3044                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3045                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3046         if (status != IXGBE_SUCCESS)
3047                 return status;
3048
3049         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3050         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3051
3052         /* Select forced link speed for internal PHY. */
3053         switch (*speed) {
3054         case IXGBE_LINK_SPEED_10GB_FULL:
3055                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3056                 break;
3057         case IXGBE_LINK_SPEED_1GB_FULL:
3058                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
3059                 break;
3060         default:
3061                 /* Other link speeds are not supported by internal KR PHY. */
3062                 return IXGBE_ERR_LINK_SETUP;
3063         }
3064
3065         status = mac->ops.write_iosf_sb_reg(hw,
3066                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3067                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3068         if (status != IXGBE_SUCCESS)
3069                 return status;
3070
3071         /* Additional configuration needed for x550em_x */
3072         if (hw->mac.type == ixgbe_mac_X550EM_x) {
3073                 status = ixgbe_setup_ixfi_x550em_x(hw);
3074                 if (status != IXGBE_SUCCESS)
3075                         return status;
3076         }
3077
3078         /* Toggle port SW reset by AN reset. */
3079         status = ixgbe_restart_an_internal_phy_x550em(hw);
3080
3081         return status;
3082 }
3083
3084 /**
3085  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
3086  * @hw: address of hardware structure
3087  * @link_up: address of boolean to indicate link status
3088  *
3089  * Returns error code if unable to get link status.
3090  */
3091 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
3092 {
3093         u32 ret;
3094         u16 autoneg_status;
3095
3096         *link_up = false;
3097
3098         /* read this twice back to back to indicate current status */
3099         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3100                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3101                                    &autoneg_status);
3102         if (ret != IXGBE_SUCCESS)
3103                 return ret;
3104
3105         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3106                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3107                                    &autoneg_status);
3108         if (ret != IXGBE_SUCCESS)
3109                 return ret;
3110
3111         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
3112
3113         return IXGBE_SUCCESS;
3114 }
3115
3116 /**
3117  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
3118  * @hw: point to hardware structure
3119  *
3120  * Configures the link between the integrated KR PHY and the external X557 PHY
3121  * The driver will call this function when it gets a link status change
3122  * interrupt from the X557 PHY. This function configures the link speed
3123  * between the PHYs to match the link speed of the BASE-T link.
3124  *
3125  * A return of a non-zero value indicates an error, and the base driver should
3126  * not report link up.
3127  */
3128 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
3129 {
3130         ixgbe_link_speed force_speed;
3131         bool link_up;
3132         u32 status;
3133         u16 speed;
3134
3135         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3136                 return IXGBE_ERR_CONFIG;
3137
3138         if (hw->mac.type == ixgbe_mac_X550EM_x &&
3139             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3140                 /* If link is down, there is no setup necessary so return  */
3141                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3142                 if (status != IXGBE_SUCCESS)
3143                         return status;
3144
3145                 if (!link_up)
3146                         return IXGBE_SUCCESS;
3147
3148                 status = hw->phy.ops.read_reg(hw,
3149                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3150                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3151                                               &speed);
3152                 if (status != IXGBE_SUCCESS)
3153                         return status;
3154
3155                 /* If link is still down - no setup is required so return */
3156                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3157                 if (status != IXGBE_SUCCESS)
3158                         return status;
3159                 if (!link_up)
3160                         return IXGBE_SUCCESS;
3161
3162                 /* clear everything but the speed and duplex bits */
3163                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3164
3165                 switch (speed) {
3166                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3167                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3168                         break;
3169                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3170                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3171                         break;
3172                 default:
3173                         /* Internal PHY does not support anything else */
3174                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
3175                 }
3176
3177                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3178         } else {
3179                 speed = IXGBE_LINK_SPEED_10GB_FULL |
3180                         IXGBE_LINK_SPEED_1GB_FULL;
3181                 return ixgbe_setup_kr_speed_x550em(hw, speed);
3182         }
3183 }
3184
3185 /**
3186  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3187  *  @hw: pointer to hardware structure
3188  *
3189  *  Configures the integrated KR PHY to use internal loopback mode.
3190  **/
3191 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3192 {
3193         s32 status;
3194         u32 reg_val;
3195
3196         /* Disable AN and force speed to 10G Serial. */
3197         status = hw->mac.ops.read_iosf_sb_reg(hw,
3198                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3199                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3200         if (status != IXGBE_SUCCESS)
3201                 return status;
3202         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3203         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3204         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3205         status = hw->mac.ops.write_iosf_sb_reg(hw,
3206                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3207                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3208         if (status != IXGBE_SUCCESS)
3209                 return status;
3210
3211         /* Set near-end loopback clocks. */
3212         status = hw->mac.ops.read_iosf_sb_reg(hw,
3213                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3214                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3215         if (status != IXGBE_SUCCESS)
3216                 return status;
3217         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3218         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3219         status = hw->mac.ops.write_iosf_sb_reg(hw,
3220                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3221                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3222         if (status != IXGBE_SUCCESS)
3223                 return status;
3224
3225         /* Set loopback enable. */
3226         status = hw->mac.ops.read_iosf_sb_reg(hw,
3227                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3228                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3229         if (status != IXGBE_SUCCESS)
3230                 return status;
3231         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3232         status = hw->mac.ops.write_iosf_sb_reg(hw,
3233                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3234                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3235         if (status != IXGBE_SUCCESS)
3236                 return status;
3237
3238         /* Training bypass. */
3239         status = hw->mac.ops.read_iosf_sb_reg(hw,
3240                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3241                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3242         if (status != IXGBE_SUCCESS)
3243                 return status;
3244         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3245         status = hw->mac.ops.write_iosf_sb_reg(hw,
3246                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3247                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3248
3249         return status;
3250 }
3251
3252 /**
3253  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3254  *  assuming that the semaphore is already obtained.
3255  *  @hw: pointer to hardware structure
3256  *  @offset: offset of  word in the EEPROM to read
3257  *  @data: word read from the EEPROM
3258  *
3259  *  Reads a 16 bit word from the EEPROM using the hostif.
3260  **/
3261 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3262 {
3263         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3264         struct ixgbe_hic_read_shadow_ram buffer;
3265         s32 status;
3266
3267         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3268         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3269         buffer.hdr.req.buf_lenh = 0;
3270         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3271         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3272
3273         /* convert offset from words to bytes */
3274         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3275         /* one word */
3276         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3277
3278         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3279         if (status)
3280                 return status;
3281
3282         status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3283                                     IXGBE_HI_COMMAND_TIMEOUT);
3284         if (!status) {
3285                 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3286                                                   FW_NVM_DATA_OFFSET);
3287         }
3288
3289         hw->mac.ops.release_swfw_sync(hw, mask);
3290         return status;
3291 }
3292
3293 /**
3294  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3295  *  @hw: pointer to hardware structure
3296  *  @offset: offset of  word in the EEPROM to read
3297  *  @words: number of words
3298  *  @data: word(s) read from the EEPROM
3299  *
3300  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
3301  **/
3302 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3303                                      u16 offset, u16 words, u16 *data)
3304 {
3305         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3306         struct ixgbe_hic_read_shadow_ram buffer;
3307         u32 current_word = 0;
3308         u16 words_to_read;
3309         s32 status;
3310         u32 i;
3311
3312         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3313
3314         /* Take semaphore for the entire operation. */
3315         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3316         if (status) {
3317                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3318                 return status;
3319         }
3320
3321         while (words) {
3322                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3323                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3324                 else
3325                         words_to_read = words;
3326
3327                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3328                 buffer.hdr.req.buf_lenh = 0;
3329                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3330                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3331
3332                 /* convert offset from words to bytes */
3333                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3334                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3335
3336                 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3337                                             IXGBE_HI_COMMAND_TIMEOUT);
3338
3339                 if (status) {
3340                         DEBUGOUT("Host interface command failed\n");
3341                         goto out;
3342                 }
3343
3344                 for (i = 0; i < words_to_read; i++) {
3345                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3346                                   2 * i;
3347                         u32 value = IXGBE_READ_REG(hw, reg);
3348
3349                         data[current_word] = (u16)(value & 0xffff);
3350                         current_word++;
3351                         i++;
3352                         if (i < words_to_read) {
3353                                 value >>= 16;
3354                                 data[current_word] = (u16)(value & 0xffff);
3355                                 current_word++;
3356                         }
3357                 }
3358                 words -= words_to_read;
3359         }
3360
3361 out:
3362         hw->mac.ops.release_swfw_sync(hw, mask);
3363         return status;
3364 }
3365
3366 /**
3367  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3368  *  @hw: pointer to hardware structure
3369  *  @offset: offset of  word in the EEPROM to write
3370  *  @data: word write to the EEPROM
3371  *
3372  *  Write a 16 bit word to the EEPROM using the hostif.
3373  **/
3374 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3375                                     u16 data)
3376 {
3377         s32 status;
3378         struct ixgbe_hic_write_shadow_ram buffer;
3379
3380         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3381
3382         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3383         buffer.hdr.req.buf_lenh = 0;
3384         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3385         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3386
3387          /* one word */
3388         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3389         buffer.data = data;
3390         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3391
3392         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3393                                               sizeof(buffer),
3394                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3395
3396         return status;
3397 }
3398
3399 /**
3400  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3401  *  @hw: pointer to hardware structure
3402  *  @offset: offset of  word in the EEPROM to write
3403  *  @data: word write to the EEPROM
3404  *
3405  *  Write a 16 bit word to the EEPROM using the hostif.
3406  **/
3407 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3408                                u16 data)
3409 {
3410         s32 status = IXGBE_SUCCESS;
3411
3412         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3413
3414         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3415             IXGBE_SUCCESS) {
3416                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3417                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3418         } else {
3419                 DEBUGOUT("write ee hostif failed to get semaphore");
3420                 status = IXGBE_ERR_SWFW_SYNC;
3421         }
3422
3423         return status;
3424 }
3425
3426 /**
3427  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3428  *  @hw: pointer to hardware structure
3429  *  @offset: offset of  word in the EEPROM to write
3430  *  @words: number of words
3431  *  @data: word(s) write to the EEPROM
3432  *
3433  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3434  **/
3435 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3436                                       u16 offset, u16 words, u16 *data)
3437 {
3438         s32 status = IXGBE_SUCCESS;
3439         u32 i = 0;
3440
3441         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3442
3443         /* Take semaphore for the entire operation. */
3444         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3445         if (status != IXGBE_SUCCESS) {
3446                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3447                 goto out;
3448         }
3449
3450         for (i = 0; i < words; i++) {
3451                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3452                                                          data[i]);
3453
3454                 if (status != IXGBE_SUCCESS) {
3455                         DEBUGOUT("Eeprom buffered write failed\n");
3456                         break;
3457                 }
3458         }
3459
3460         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3461 out:
3462
3463         return status;
3464 }
3465
3466 /**
3467  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3468  * @hw: pointer to hardware structure
3469  * @ptr: pointer offset in eeprom
3470  * @size: size of section pointed by ptr, if 0 first word will be used as size
3471  * @csum: address of checksum to update
3472  *
3473  * Returns error status for any failure
3474  */
3475 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3476                                    u16 size, u16 *csum, u16 *buffer,
3477                                    u32 buffer_size)
3478 {
3479         u16 buf[256];
3480         s32 status;
3481         u16 length, bufsz, i, start;
3482         u16 *local_buffer;
3483
3484         bufsz = sizeof(buf) / sizeof(buf[0]);
3485
3486         /* Read a chunk at the pointer location */
3487         if (!buffer) {
3488                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3489                 if (status) {
3490                         DEBUGOUT("Failed to read EEPROM image\n");
3491                         return status;
3492                 }
3493                 local_buffer = buf;
3494         } else {
3495                 if (buffer_size < ptr)
3496                         return  IXGBE_ERR_PARAM;
3497                 local_buffer = &buffer[ptr];
3498         }
3499
3500         if (size) {
3501                 start = 0;
3502                 length = size;
3503         } else {
3504                 start = 1;
3505                 length = local_buffer[0];
3506
3507                 /* Skip pointer section if length is invalid. */
3508                 if (length == 0xFFFF || length == 0 ||
3509                     (ptr + length) >= hw->eeprom.word_size)
3510                         return IXGBE_SUCCESS;
3511         }
3512
3513         if (buffer && ((u32)start + (u32)length > buffer_size))
3514                 return IXGBE_ERR_PARAM;
3515
3516         for (i = start; length; i++, length--) {
3517                 if (i == bufsz && !buffer) {
3518                         ptr += bufsz;
3519                         i = 0;
3520                         if (length < bufsz)
3521                                 bufsz = length;
3522
3523                         /* Read a chunk at the pointer location */
3524                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3525                                                                   bufsz, buf);
3526                         if (status) {
3527                                 DEBUGOUT("Failed to read EEPROM image\n");
3528                                 return status;
3529                         }
3530                 }
3531                 *csum += local_buffer[i];
3532         }
3533         return IXGBE_SUCCESS;
3534 }
3535
3536 /**
3537  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3538  *  @hw: pointer to hardware structure
3539  *  @buffer: pointer to buffer containing calculated checksum
3540  *  @buffer_size: size of buffer
3541  *
3542  *  Returns a negative error code on error, or the 16-bit checksum
3543  **/
3544 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3545 {
3546         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3547         u16 *local_buffer;
3548         s32 status;
3549         u16 checksum = 0;
3550         u16 pointer, i, size;
3551
3552         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3553
3554         hw->eeprom.ops.init_params(hw);
3555
3556         if (!buffer) {
3557                 /* Read pointer area */
3558                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3559                                                      IXGBE_EEPROM_LAST_WORD + 1,
3560                                                      eeprom_ptrs);
3561                 if (status) {
3562                         DEBUGOUT("Failed to read EEPROM image\n");
3563                         return status;
3564                 }
3565                 local_buffer = eeprom_ptrs;
3566         } else {
3567                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3568                         return IXGBE_ERR_PARAM;
3569                 local_buffer = buffer;
3570         }
3571
3572         /*
3573          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3574          * checksum word itself
3575          */
3576         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3577                 if (i != IXGBE_EEPROM_CHECKSUM)
3578                         checksum += local_buffer[i];
3579
3580         /*
3581          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3582          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3583          */
3584         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3585                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3586                         continue;
3587
3588                 pointer = local_buffer[i];
3589
3590                 /* Skip pointer section if the pointer is invalid. */
3591                 if (pointer == 0xFFFF || pointer == 0 ||
3592                     pointer >= hw->eeprom.word_size)
3593                         continue;
3594
3595                 switch (i) {
3596                 case IXGBE_PCIE_GENERAL_PTR:
3597                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3598                         break;
3599                 case IXGBE_PCIE_CONFIG0_PTR:
3600                 case IXGBE_PCIE_CONFIG1_PTR:
3601                         size = IXGBE_PCIE_CONFIG_SIZE;
3602                         break;
3603                 default:
3604                         size = 0;
3605                         break;
3606                 }
3607
3608                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3609                                                 buffer, buffer_size);
3610                 if (status)
3611                         return status;
3612         }
3613
3614         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3615
3616         return (s32)checksum;
3617 }
3618
3619 /**
3620  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3621  *  @hw: pointer to hardware structure
3622  *
3623  *  Returns a negative error code on error, or the 16-bit checksum
3624  **/
3625 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3626 {
3627         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3628 }
3629
3630 /**
3631  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3632  *  @hw: pointer to hardware structure
3633  *  @checksum_val: calculated checksum
3634  *
3635  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3636  *  caller does not need checksum_val, the value can be NULL.
3637  **/
3638 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3639 {
3640         s32 status;
3641         u16 checksum;
3642         u16 read_checksum = 0;
3643
3644         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3645
3646         /* Read the first word from the EEPROM. If this times out or fails, do
3647          * not continue or we could be in for a very long wait while every
3648          * EEPROM read fails
3649          */
3650         status = hw->eeprom.ops.read(hw, 0, &checksum);
3651         if (status) {
3652                 DEBUGOUT("EEPROM read failed\n");
3653                 return status;
3654         }
3655
3656         status = hw->eeprom.ops.calc_checksum(hw);
3657         if (status < 0)
3658                 return status;
3659
3660         checksum = (u16)(status & 0xffff);
3661
3662         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3663                                            &read_checksum);
3664         if (status)
3665                 return status;
3666
3667         /* Verify read checksum from EEPROM is the same as
3668          * calculated checksum
3669          */
3670         if (read_checksum != checksum) {
3671                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3672                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3673                              "Invalid EEPROM checksum");
3674         }
3675
3676         /* If the user cares, return the calculated checksum */
3677         if (checksum_val)
3678                 *checksum_val = checksum;
3679
3680         return status;
3681 }
3682
3683 /**
3684  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3685  * @hw: pointer to hardware structure
3686  *
3687  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3688  * checksum and updates the EEPROM and instructs the hardware to update
3689  * the flash.
3690  **/
3691 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3692 {
3693         s32 status;
3694         u16 checksum = 0;
3695
3696         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3697
3698         /* Read the first word from the EEPROM. If this times out or fails, do
3699          * not continue or we could be in for a very long wait while every
3700          * EEPROM read fails
3701          */
3702         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3703         if (status) {
3704                 DEBUGOUT("EEPROM read failed\n");
3705                 return status;
3706         }
3707
3708         status = ixgbe_calc_eeprom_checksum_X550(hw);
3709         if (status < 0)
3710                 return status;
3711
3712         checksum = (u16)(status & 0xffff);
3713
3714         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3715                                             checksum);
3716         if (status)
3717                 return status;
3718
3719         status = ixgbe_update_flash_X550(hw);
3720
3721         return status;
3722 }
3723
3724 /**
3725  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3726  *  @hw: pointer to hardware structure
3727  *
3728  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3729  **/
3730 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3731 {
3732         s32 status = IXGBE_SUCCESS;
3733         union ixgbe_hic_hdr2 buffer;
3734
3735         DEBUGFUNC("ixgbe_update_flash_X550");
3736
3737         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3738         buffer.req.buf_lenh = 0;
3739         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3740         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3741
3742         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3743                                               sizeof(buffer),
3744                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3745
3746         return status;
3747 }
3748
3749 /**
3750  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3751  *  @hw: pointer to hardware structure
3752  *
3753  *  Determines physical layer capabilities of the current configuration.
3754  **/
3755 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3756 {
3757         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3758         u16 ext_ability = 0;
3759
3760         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3761
3762         hw->phy.ops.identify(hw);
3763
3764         switch (hw->phy.type) {
3765         case ixgbe_phy_x550em_kr:
3766                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3767                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3768                 break;
3769         case ixgbe_phy_x550em_kx4:
3770                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3771                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3772                 break;
3773         case ixgbe_phy_x550em_ext_t:
3774                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3775                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3776                                      &ext_ability);
3777                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3778                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3779                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3780                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3781                 break;
3782         case ixgbe_phy_fw:
3783                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
3784         default:
3785                 break;
3786         }
3787
3788         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3789                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3790
3791         return physical_layer;
3792 }
3793
3794 /**
3795  * ixgbe_get_bus_info_x550em - Set PCI bus info
3796  * @hw: pointer to hardware structure
3797  *
3798  * Sets bus link width and speed to unknown because X550em is
3799  * not a PCI device.
3800  **/
3801 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3802 {
3803
3804         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3805
3806         hw->bus.width = ixgbe_bus_width_unknown;
3807         hw->bus.speed = ixgbe_bus_speed_unknown;
3808
3809         hw->mac.ops.set_lan_id(hw);
3810
3811         return IXGBE_SUCCESS;
3812 }
3813
3814 /**
3815  * ixgbe_disable_rx_x550 - Disable RX unit
3816  *
3817  * Enables the Rx DMA unit for x550
3818  **/
3819 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3820 {
3821         u32 rxctrl, pfdtxgswc;
3822         s32 status;
3823         struct ixgbe_hic_disable_rxen fw_cmd;
3824
3825         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3826
3827         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3828         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3829                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3830                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3831                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3832                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3833                         hw->mac.set_lben = true;
3834                 } else {
3835                         hw->mac.set_lben = false;
3836                 }
3837
3838                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3839                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3840                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3841                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3842
3843                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3844                                         sizeof(struct ixgbe_hic_disable_rxen),
3845                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3846
3847                 /* If we fail - disable RX using register write */
3848                 if (status) {
3849                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3850                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3851                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3852                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3853                         }
3854                 }
3855         }
3856 }
3857
3858 /**
3859  * ixgbe_enter_lplu_x550em - Transition to low power states
3860  *  @hw: pointer to hardware structure
3861  *
3862  * Configures Low Power Link Up on transition to low power states
3863  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3864  * X557 PHY immediately prior to entering LPLU.
3865  **/
3866 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3867 {
3868         u16 an_10g_cntl_reg, autoneg_reg, speed;
3869         s32 status;
3870         ixgbe_link_speed lcd_speed;
3871         u32 save_autoneg;
3872         bool link_up;
3873
3874         /* SW LPLU not required on later HW revisions. */
3875         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3876             (IXGBE_FUSES0_REV_MASK &
3877              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3878                 return IXGBE_SUCCESS;
3879
3880         /* If blocked by MNG FW, then don't restart AN */
3881         if (ixgbe_check_reset_blocked(hw))
3882                 return IXGBE_SUCCESS;
3883
3884         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3885         if (status != IXGBE_SUCCESS)
3886                 return status;
3887
3888         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3889
3890         if (status != IXGBE_SUCCESS)
3891                 return status;
3892
3893         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3894          * disabled, then force link down by entering low power mode.
3895          */
3896         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3897             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3898                 return ixgbe_set_copper_phy_power(hw, FALSE);
3899
3900         /* Determine LCD */
3901         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3902
3903         if (status != IXGBE_SUCCESS)
3904                 return status;
3905
3906         /* If no valid LCD link speed, then force link down and exit. */
3907         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3908                 return ixgbe_set_copper_phy_power(hw, FALSE);
3909
3910         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3911                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3912                                       &speed);
3913
3914         if (status != IXGBE_SUCCESS)
3915                 return status;
3916
3917         /* If no link now, speed is invalid so take link down */
3918         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3919         if (status != IXGBE_SUCCESS)
3920                 return ixgbe_set_copper_phy_power(hw, false);
3921
3922         /* clear everything but the speed bits */
3923         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3924
3925         /* If current speed is already LCD, then exit. */
3926         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3927              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3928             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3929              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3930                 return status;
3931
3932         /* Clear AN completed indication */
3933         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3934                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3935                                       &autoneg_reg);
3936
3937         if (status != IXGBE_SUCCESS)
3938                 return status;
3939
3940         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3941                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3942                              &an_10g_cntl_reg);
3943
3944         if (status != IXGBE_SUCCESS)
3945                 return status;
3946
3947         status = hw->phy.ops.read_reg(hw,
3948                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3949                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3950                              &autoneg_reg);
3951
3952         if (status != IXGBE_SUCCESS)
3953                 return status;
3954
3955         save_autoneg = hw->phy.autoneg_advertised;
3956
3957         /* Setup link at least common link speed */
3958         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3959
3960         /* restore autoneg from before setting lplu speed */
3961         hw->phy.autoneg_advertised = save_autoneg;
3962
3963         return status;
3964 }
3965
3966 /**
3967  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3968  *  @hw: pointer to hardware structure
3969  *  @lcd_speed: pointer to lowest common link speed
3970  *
3971  * Determine lowest common link speed with link partner.
3972  **/
3973 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3974 {
3975         u16 an_lp_status;
3976         s32 status;
3977         u16 word = hw->eeprom.ctrl_word_3;
3978
3979         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3980
3981         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3982                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3983                                       &an_lp_status);
3984
3985         if (status != IXGBE_SUCCESS)
3986                 return status;
3987
3988         /* If link partner advertised 1G, return 1G */
3989         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3990                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3991                 return status;
3992         }
3993
3994         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3995         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3996             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3997                 return status;
3998
3999         /* Link partner not capable of lower speeds, return 10G */
4000         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
4001         return status;
4002 }
4003
4004 /**
4005  *  ixgbe_setup_fc_X550em - Set up flow control
4006  *  @hw: pointer to hardware structure
4007  *
4008  *  Called at init time to set up flow control.
4009  **/
4010 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
4011 {
4012         s32 ret_val = IXGBE_SUCCESS;
4013         u32 pause, asm_dir, reg_val;
4014
4015         DEBUGFUNC("ixgbe_setup_fc_X550em");
4016
4017         /* Validate the requested mode */
4018         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4019                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4020                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4021                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4022                 goto out;
4023         }
4024
4025         /* 10gig parts do not have a word in the EEPROM to determine the
4026          * default flow control setting, so we explicitly set it to full.
4027          */
4028         if (hw->fc.requested_mode == ixgbe_fc_default)
4029                 hw->fc.requested_mode = ixgbe_fc_full;
4030
4031         /* Determine PAUSE and ASM_DIR bits. */
4032         switch (hw->fc.requested_mode) {
4033         case ixgbe_fc_none:
4034                 pause = 0;
4035                 asm_dir = 0;
4036                 break;
4037         case ixgbe_fc_tx_pause:
4038                 pause = 0;
4039                 asm_dir = 1;
4040                 break;
4041         case ixgbe_fc_rx_pause:
4042                 /* Rx Flow control is enabled and Tx Flow control is
4043                  * disabled by software override. Since there really
4044                  * isn't a way to advertise that we are capable of RX
4045                  * Pause ONLY, we will advertise that we support both
4046                  * symmetric and asymmetric Rx PAUSE, as such we fall
4047                  * through to the fc_full statement.  Later, we will
4048                  * disable the adapter's ability to send PAUSE frames.
4049                  */
4050         case ixgbe_fc_full:
4051                 pause = 1;
4052                 asm_dir = 1;
4053                 break;
4054         default:
4055                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4056                         "Flow control param set incorrectly\n");
4057                 ret_val = IXGBE_ERR_CONFIG;
4058                 goto out;
4059         }
4060
4061         switch (hw->device_id) {
4062         case IXGBE_DEV_ID_X550EM_X_KR:
4063         case IXGBE_DEV_ID_X550EM_A_KR:
4064         case IXGBE_DEV_ID_X550EM_A_KR_L:
4065                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
4066                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4067                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
4068                 if (ret_val != IXGBE_SUCCESS)
4069                         goto out;
4070                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4071                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4072                 if (pause)
4073                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4074                 if (asm_dir)
4075                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4076                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
4077                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4078                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
4079
4080                 /* This device does not fully support AN. */
4081                 hw->fc.disable_fc_autoneg = true;
4082                 break;
4083         default:
4084                 break;
4085         }
4086
4087 out:
4088         return ret_val;
4089 }
4090
4091 /**
4092  *  ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
4093  *  @hw: pointer to hardware structure
4094  *
4095  *  Enable flow control according to IEEE clause 37.
4096  **/
4097 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
4098 {
4099         u32 link_s1, lp_an_page_low, an_cntl_1;
4100         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4101         ixgbe_link_speed speed;
4102         bool link_up;
4103
4104         /* AN should have completed when the cable was plugged in.
4105          * Look for reasons to bail out.  Bail out if:
4106          * - FC autoneg is disabled, or if
4107          * - link is not up.
4108          */
4109         if (hw->fc.disable_fc_autoneg) {
4110                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4111                              "Flow control autoneg is disabled");
4112                 goto out;
4113         }
4114
4115         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4116         if (!link_up) {
4117                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4118                 goto out;
4119         }
4120
4121         /* Check at auto-negotiation has completed */
4122         status = hw->mac.ops.read_iosf_sb_reg(hw,
4123                                         IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4124                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4125
4126         if (status != IXGBE_SUCCESS ||
4127             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4128                 DEBUGOUT("Auto-Negotiation did not complete\n");
4129                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4130                 goto out;
4131         }
4132
4133         /* Read the 10g AN autoc and LP ability registers and resolve
4134          * local flow control settings accordingly
4135          */
4136         status = hw->mac.ops.read_iosf_sb_reg(hw,
4137                                 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4138                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4139
4140         if (status != IXGBE_SUCCESS) {
4141                 DEBUGOUT("Auto-Negotiation did not complete\n");
4142                 goto out;
4143         }
4144
4145         status = hw->mac.ops.read_iosf_sb_reg(hw,
4146                                 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4147                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4148
4149         if (status != IXGBE_SUCCESS) {
4150                 DEBUGOUT("Auto-Negotiation did not complete\n");
4151                 goto out;
4152         }
4153
4154         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4155                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4156                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4157                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4158                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4159
4160 out:
4161         if (status == IXGBE_SUCCESS) {
4162                 hw->fc.fc_was_autonegged = true;
4163         } else {
4164                 hw->fc.fc_was_autonegged = false;
4165                 hw->fc.current_mode = hw->fc.requested_mode;
4166         }
4167 }
4168
4169 /**
4170  *  ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4171  *  @hw: pointer to hardware structure
4172  *
4173  **/
4174 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4175 {
4176         hw->fc.fc_was_autonegged = false;
4177         hw->fc.current_mode = hw->fc.requested_mode;
4178 }
4179
4180 /**
4181  *  ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4182  *  @hw: pointer to hardware structure
4183  *
4184  *  Enable flow control according to IEEE clause 37.
4185  **/
4186 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4187 {
4188         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4189         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
4190         ixgbe_link_speed speed;
4191         bool link_up;
4192         u32 fc;
4193
4194         /* AN should have completed when the cable was plugged in.
4195          * Look for reasons to bail out.  Bail out if:
4196          * - FC autoneg is disabled, or if
4197          * - link is not up.
4198          */
4199         if (hw->fc.disable_fc_autoneg) {
4200                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4201                              "Flow control autoneg is disabled");
4202                 goto out;
4203         }
4204
4205         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4206         if (!link_up) {
4207                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4208                 goto out;
4209         }
4210
4211         /* Check if auto-negotiation has completed */
4212         status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
4213         if (status != IXGBE_SUCCESS ||
4214             !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
4215                 DEBUGOUT("Auto-Negotiation did not complete\n");
4216                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4217                 goto out;
4218         }
4219
4220         /* Get the advertized flow control and modify it to indicate
4221          * pause and asymmetric pause instead of rx and tx
4222          */
4223         fc = info[0];
4224         if (fc & FW_PHY_ACT_GET_LINK_INFO_FC_RX)
4225                 fc ^= FW_PHY_ACT_GET_LINK_INFO_FC_TX;
4226
4227         /* Modify link partner's flow control to indicate pause and
4228          * asymmetric pause instead of rx and tx
4229          */
4230         if (fc & FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX)
4231                 fc ^= FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX;
4232
4233         /* Negotiate the flow control */
4234         status = ixgbe_negotiate_fc(hw, fc, fc,
4235                                     FW_PHY_ACT_GET_LINK_INFO_FC_RX,
4236                                     FW_PHY_ACT_GET_LINK_INFO_FC_TX,
4237                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
4238                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
4239
4240 out:
4241         if (status == IXGBE_SUCCESS) {
4242                 hw->fc.fc_was_autonegged = true;
4243         } else {
4244                 hw->fc.fc_was_autonegged = false;
4245                 hw->fc.current_mode = hw->fc.requested_mode;
4246         }
4247 }
4248
4249 /**
4250  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4251  *  @hw: pointer to hardware structure
4252  *
4253  *  Called at init time to set up flow control.
4254  **/
4255 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4256 {
4257         s32 status = IXGBE_SUCCESS;
4258         u32 an_cntl = 0;
4259
4260         DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4261
4262         /* Validate the requested mode */
4263         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4264                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4265                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4266                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4267         }
4268
4269         if (hw->fc.requested_mode == ixgbe_fc_default)
4270                 hw->fc.requested_mode = ixgbe_fc_full;
4271
4272         /* Set up the 1G and 10G flow control advertisement registers so the
4273          * HW will be able to do FC autoneg once the cable is plugged in.  If
4274          * we link at 10G, the 1G advertisement is harmless and vice versa.
4275          */
4276         status = hw->mac.ops.read_iosf_sb_reg(hw,
4277                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4278                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4279
4280         if (status != IXGBE_SUCCESS) {
4281                 DEBUGOUT("Auto-Negotiation did not complete\n");
4282                 return status;
4283         }
4284
4285         /* The possible values of fc.requested_mode are:
4286          * 0: Flow control is completely disabled
4287          * 1: Rx flow control is enabled (we can receive pause frames,
4288          *    but not send pause frames).
4289          * 2: Tx flow control is enabled (we can send pause frames but
4290          *    we do not support receiving pause frames).
4291          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4292          * other: Invalid.
4293          */
4294         switch (hw->fc.requested_mode) {
4295         case ixgbe_fc_none:
4296                 /* Flow control completely disabled by software override. */
4297                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4298                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4299                 break;
4300         case ixgbe_fc_tx_pause:
4301                 /* Tx Flow control is enabled, and Rx Flow control is
4302                  * disabled by software override.
4303                  */
4304                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4305                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4306                 break;
4307         case ixgbe_fc_rx_pause:
4308                 /* Rx Flow control is enabled and Tx Flow control is
4309                  * disabled by software override. Since there really
4310                  * isn't a way to advertise that we are capable of RX
4311                  * Pause ONLY, we will advertise that we support both
4312                  * symmetric and asymmetric Rx PAUSE, as such we fall
4313                  * through to the fc_full statement.  Later, we will
4314                  * disable the adapter's ability to send PAUSE frames.
4315                  */
4316         case ixgbe_fc_full:
4317                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4318                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4319                            IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4320                 break;
4321         default:
4322                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4323                               "Flow control param set incorrectly\n");
4324                 return IXGBE_ERR_CONFIG;
4325         }
4326
4327         status = hw->mac.ops.write_iosf_sb_reg(hw,
4328                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4329                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4330
4331         /* Restart auto-negotiation. */
4332         status = ixgbe_restart_an_internal_phy_x550em(hw);
4333
4334         return status;
4335 }
4336
4337 /**
4338  * ixgbe_set_mux - Set mux for port 1 access with CS4227
4339  * @hw: pointer to hardware structure
4340  * @state: set mux if 1, clear if 0
4341  */
4342 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4343 {
4344         u32 esdp;
4345
4346         if (!hw->bus.lan_id)
4347                 return;
4348         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4349         if (state)
4350                 esdp |= IXGBE_ESDP_SDP1;
4351         else
4352                 esdp &= ~IXGBE_ESDP_SDP1;
4353         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4354         IXGBE_WRITE_FLUSH(hw);
4355 }
4356
4357 /**
4358  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4359  *  @hw: pointer to hardware structure
4360  *  @mask: Mask to specify which semaphore to acquire
4361  *
4362  *  Acquires the SWFW semaphore and sets the I2C MUX
4363  **/
4364 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4365 {
4366         s32 status;
4367
4368         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4369
4370         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4371         if (status)
4372                 return status;
4373
4374         if (mask & IXGBE_GSSR_I2C_MASK)
4375                 ixgbe_set_mux(hw, 1);
4376
4377         return IXGBE_SUCCESS;
4378 }
4379
4380 /**
4381  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4382  *  @hw: pointer to hardware structure
4383  *  @mask: Mask to specify which semaphore to release
4384  *
4385  *  Releases the SWFW semaphore and sets the I2C MUX
4386  **/
4387 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4388 {
4389         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4390
4391         if (mask & IXGBE_GSSR_I2C_MASK)
4392                 ixgbe_set_mux(hw, 0);
4393
4394         ixgbe_release_swfw_sync_X540(hw, mask);
4395 }
4396
4397 /**
4398  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4399  *  @hw: pointer to hardware structure
4400  *  @mask: Mask to specify which semaphore to acquire
4401  *
4402  *  Acquires the SWFW semaphore and get the shared phy token as needed
4403  */
4404 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4405 {
4406         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4407         int retries = FW_PHY_TOKEN_RETRIES;
4408         s32 status = IXGBE_SUCCESS;
4409
4410         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4411
4412         while (--retries) {
4413                 status = IXGBE_SUCCESS;
4414                 if (hmask)
4415                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4416                 if (status)
4417                         return status;
4418                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4419                         return IXGBE_SUCCESS;
4420
4421                 status = ixgbe_get_phy_token(hw);
4422                 if (status == IXGBE_SUCCESS)
4423                         return IXGBE_SUCCESS;
4424
4425                 if (hmask)
4426                         ixgbe_release_swfw_sync_X540(hw, hmask);
4427                 if (status != IXGBE_ERR_TOKEN_RETRY)
4428                         return status;
4429         }
4430
4431         return status;
4432 }
4433
4434 /**
4435  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4436  *  @hw: pointer to hardware structure
4437  *  @mask: Mask to specify which semaphore to release
4438  *
4439  *  Releases the SWFW semaphore and puts the shared phy token as needed
4440  */
4441 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4442 {
4443         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4444
4445         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4446
4447         if (mask & IXGBE_GSSR_TOKEN_SM)
4448                 ixgbe_put_phy_token(hw);
4449
4450         if (hmask)
4451                 ixgbe_release_swfw_sync_X540(hw, hmask);
4452 }
4453
4454 /**
4455  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4456  *  @hw: pointer to hardware structure
4457  *  @reg_addr: 32 bit address of PHY register to read
4458  *  @phy_data: Pointer to read data from PHY register
4459  *
4460  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4461  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4462  *  instances.
4463  **/
4464 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4465                                u32 device_type, u16 *phy_data)
4466 {
4467         s32 status;
4468         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4469
4470         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4471
4472         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4473                 return IXGBE_ERR_SWFW_SYNC;
4474
4475         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4476
4477         hw->mac.ops.release_swfw_sync(hw, mask);
4478
4479         return status;
4480 }
4481
4482 /**
4483  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4484  *  @hw: pointer to hardware structure
4485  *  @reg_addr: 32 bit PHY register to write
4486  *  @device_type: 5 bit device type
4487  *  @phy_data: Data to write to the PHY register
4488  *
4489  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4490  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4491  **/
4492 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4493                                 u32 device_type, u16 phy_data)
4494 {
4495         s32 status;
4496         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4497
4498         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4499
4500         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4501                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4502                                                  phy_data);
4503                 hw->mac.ops.release_swfw_sync(hw, mask);
4504         } else {
4505                 status = IXGBE_ERR_SWFW_SYNC;
4506         }
4507
4508         return status;
4509 }
4510
4511 /**
4512  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4513  * @hw: pointer to hardware structure
4514  *
4515  * Handle external Base T PHY interrupt. If high temperature
4516  * failure alarm then return error, else if link status change
4517  * then setup internal/external PHY link
4518  *
4519  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4520  * failure alarm, else return PHY access status.
4521  */
4522 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4523 {
4524         bool lsc;
4525         u32 status;
4526
4527         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4528
4529         if (status != IXGBE_SUCCESS)
4530                 return status;
4531
4532         if (lsc)
4533                 return ixgbe_setup_internal_phy(hw);
4534
4535         return IXGBE_SUCCESS;
4536 }
4537
4538 /**
4539  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4540  * @hw: pointer to hardware structure
4541  * @speed: new link speed
4542  * @autoneg_wait_to_complete: true when waiting for completion is needed
4543  *
4544  * Setup internal/external PHY link speed based on link speed, then set
4545  * external PHY auto advertised link speed.
4546  *
4547  * Returns error status for any failure
4548  **/
4549 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4550                                   ixgbe_link_speed speed,
4551                                   bool autoneg_wait_to_complete)
4552 {
4553         s32 status;
4554         ixgbe_link_speed force_speed;
4555
4556         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4557
4558         /* Setup internal/external PHY link speed to iXFI (10G), unless
4559          * only 1G is auto advertised then setup KX link.
4560          */
4561         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4562                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4563         else
4564                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4565
4566         /* If X552 and internal link mode is XFI, then setup XFI internal link.
4567          */
4568         if (hw->mac.type == ixgbe_mac_X550EM_x &&
4569             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4570                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4571
4572                 if (status != IXGBE_SUCCESS)
4573                         return status;
4574         }
4575
4576         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4577 }
4578
4579 /**
4580  * ixgbe_check_link_t_X550em - Determine link and speed status
4581  * @hw: pointer to hardware structure
4582  * @speed: pointer to link speed
4583  * @link_up: true when link is up
4584  * @link_up_wait_to_complete: bool used to wait for link up or not
4585  *
4586  * Check that both the MAC and X557 external PHY have link.
4587  **/
4588 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4589                               bool *link_up, bool link_up_wait_to_complete)
4590 {
4591         u32 status;
4592         u16 i, autoneg_status = 0;
4593
4594         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4595                 return IXGBE_ERR_CONFIG;
4596
4597         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4598                                               link_up_wait_to_complete);
4599
4600         /* If check link fails or MAC link is not up, then return */
4601         if (status != IXGBE_SUCCESS || !(*link_up))
4602                 return status;
4603
4604         /* MAC link is up, so check external PHY link.
4605          * X557 PHY. Link status is latching low, and can only be used to detect
4606          * link drop, and not the current status of the link without performing
4607          * back-to-back reads.
4608          */
4609         for (i = 0; i < 2; i++) {
4610                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4611                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4612                                               &autoneg_status);
4613
4614                 if (status != IXGBE_SUCCESS)
4615                         return status;
4616         }
4617
4618         /* If external PHY link is not up, then indicate link not up */
4619         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4620                 *link_up = false;
4621
4622         return IXGBE_SUCCESS;
4623 }
4624
4625 /**
4626  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4627  *  @hw: pointer to hardware structure
4628  **/
4629 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4630 {
4631         s32 status;
4632
4633         status = ixgbe_reset_phy_generic(hw);
4634
4635         if (status != IXGBE_SUCCESS)
4636                 return status;
4637
4638         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4639         return ixgbe_enable_lasi_ext_t_x550em(hw);
4640 }
4641
4642 /**
4643  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4644  *  @hw: pointer to hardware structure
4645  *  @led_idx: led number to turn on
4646  **/
4647 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4648 {
4649         u16 phy_data;
4650
4651         DEBUGFUNC("ixgbe_led_on_t_X550em");
4652
4653         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4654                 return IXGBE_ERR_PARAM;
4655
4656         /* To turn on the LED, set mode to ON. */
4657         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4658                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4659         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4660         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4661                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4662
4663         return IXGBE_SUCCESS;
4664 }
4665
4666 /**
4667  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4668  *  @hw: pointer to hardware structure
4669  *  @led_idx: led number to turn off
4670  **/
4671 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4672 {
4673         u16 phy_data;
4674
4675         DEBUGFUNC("ixgbe_led_off_t_X550em");
4676
4677         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4678                 return IXGBE_ERR_PARAM;
4679
4680         /* To turn on the LED, set mode to ON. */
4681         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4682                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4683         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4684         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4685                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4686
4687         return IXGBE_SUCCESS;
4688 }
4689
4690 /**
4691  *  ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
4692  *  @hw: pointer to the HW structure
4693  *  @maj: driver version major number
4694  *  @min: driver version minor number
4695  *  @build: driver version build number
4696  *  @sub: driver version sub build number
4697  *  @len: length of driver_ver string
4698  *  @driver_ver: driver string
4699  *
4700  *  Sends driver version number to firmware through the manageability
4701  *  block.  On success return IXGBE_SUCCESS
4702  *  else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4703  *  semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4704  **/
4705 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
4706                               u8 build, u8 sub, u16 len, const char *driver_ver)
4707 {
4708         struct ixgbe_hic_drv_info2 fw_cmd;
4709         s32 ret_val = IXGBE_SUCCESS;
4710         int i;
4711
4712         DEBUGFUNC("ixgbe_set_fw_drv_ver_x550");
4713
4714         if ((len == 0) || (driver_ver == NULL) ||
4715            (len > sizeof(fw_cmd.driver_string)))
4716                 return IXGBE_ERR_INVALID_ARGUMENT;
4717
4718         fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4719         fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
4720         fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4721         fw_cmd.port_num = (u8)hw->bus.func;
4722         fw_cmd.ver_maj = maj;
4723         fw_cmd.ver_min = min;
4724         fw_cmd.ver_build = build;
4725         fw_cmd.ver_sub = sub;
4726         fw_cmd.hdr.checksum = 0;
4727         memcpy(fw_cmd.driver_string, driver_ver, len);
4728         fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4729                                 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4730
4731         for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4732                 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4733                                                        sizeof(fw_cmd),
4734                                                        IXGBE_HI_COMMAND_TIMEOUT,
4735                                                        true);
4736                 if (ret_val != IXGBE_SUCCESS)
4737                         continue;
4738
4739                 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4740                     FW_CEM_RESP_STATUS_SUCCESS)
4741                         ret_val = IXGBE_SUCCESS;
4742                 else
4743                         ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4744
4745                 break;
4746         }
4747
4748         return ret_val;
4749 }