1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
42 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
43 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
46 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
47 * @hw: pointer to hardware structure
49 * Initialize the function pointers and assign the MAC type for X550.
50 * Does not touch the hardware.
52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
54 struct ixgbe_mac_info *mac = &hw->mac;
55 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
58 DEBUGFUNC("ixgbe_init_ops_X550");
60 ret_val = ixgbe_init_ops_X540(hw);
61 mac->ops.dmac_config = ixgbe_dmac_config_X550;
62 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
63 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
64 mac->ops.setup_eee = ixgbe_setup_eee_X550;
65 mac->ops.set_source_address_pruning =
66 ixgbe_set_source_address_pruning_X550;
67 mac->ops.set_ethertype_anti_spoofing =
68 ixgbe_set_ethertype_anti_spoofing_X550;
70 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
71 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
72 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
73 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
74 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
75 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
76 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
77 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
78 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
80 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
81 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
82 mac->ops.mdd_event = ixgbe_mdd_event_X550;
83 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
84 mac->ops.disable_rx = ixgbe_disable_rx_x550;
85 switch (hw->device_id) {
86 case IXGBE_DEV_ID_X550EM_X_10G_T:
87 case IXGBE_DEV_ID_X550EM_A_10G_T:
88 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
89 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
98 * ixgbe_read_cs4227 - Read CS4227 register
99 * @hw: pointer to hardware structure
100 * @reg: register number to write
101 * @value: pointer to receive value read
103 * Returns status code
105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
107 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
111 * ixgbe_write_cs4227 - Write CS4227 register
112 * @hw: pointer to hardware structure
113 * @reg: register number to write
114 * @value: value to write to register
116 * Returns status code
118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
120 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
124 * ixgbe_read_pe - Read register from port expander
125 * @hw: pointer to hardware structure
126 * @reg: register number to read
127 * @value: pointer to receive read value
129 * Returns status code
131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
135 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
136 if (status != IXGBE_SUCCESS)
137 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
138 "port expander access failed with %d\n", status);
143 * ixgbe_write_pe - Write register to port expander
144 * @hw: pointer to hardware structure
145 * @reg: register number to write
146 * @value: value to write
148 * Returns status code
150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
154 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
155 if (status != IXGBE_SUCCESS)
156 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
157 "port expander access failed with %d\n", status);
162 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
163 * @hw: pointer to hardware structure
165 * This function assumes that the caller has acquired the proper semaphore.
168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
175 /* Trigger hard reset. */
176 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
177 if (status != IXGBE_SUCCESS)
179 reg |= IXGBE_PE_BIT1;
180 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
181 if (status != IXGBE_SUCCESS)
184 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
185 if (status != IXGBE_SUCCESS)
187 reg &= ~IXGBE_PE_BIT1;
188 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
189 if (status != IXGBE_SUCCESS)
192 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
193 if (status != IXGBE_SUCCESS)
195 reg &= ~IXGBE_PE_BIT1;
196 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
197 if (status != IXGBE_SUCCESS)
200 usec_delay(IXGBE_CS4227_RESET_HOLD);
202 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
203 if (status != IXGBE_SUCCESS)
205 reg |= IXGBE_PE_BIT1;
206 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
207 if (status != IXGBE_SUCCESS)
210 /* Wait for the reset to complete. */
211 msec_delay(IXGBE_CS4227_RESET_DELAY);
212 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
213 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
215 if (status == IXGBE_SUCCESS &&
216 value == IXGBE_CS4227_EEPROM_LOAD_OK)
218 msec_delay(IXGBE_CS4227_CHECK_DELAY);
220 if (retry == IXGBE_CS4227_RETRIES) {
221 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
222 "CS4227 reset did not complete.");
223 return IXGBE_ERR_PHY;
226 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
227 if (status != IXGBE_SUCCESS ||
228 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
229 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
230 "CS4227 EEPROM did not load successfully.");
231 return IXGBE_ERR_PHY;
234 return IXGBE_SUCCESS;
238 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
239 * @hw: pointer to hardware structure
241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
243 s32 status = IXGBE_SUCCESS;
244 u32 swfw_mask = hw->phy.phy_semaphore_mask;
248 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
249 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
250 if (status != IXGBE_SUCCESS) {
251 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
252 "semaphore failed with %d", status);
253 msec_delay(IXGBE_CS4227_CHECK_DELAY);
257 /* Get status of reset flow. */
258 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
260 if (status == IXGBE_SUCCESS &&
261 value == IXGBE_CS4227_RESET_COMPLETE)
264 if (status != IXGBE_SUCCESS ||
265 value != IXGBE_CS4227_RESET_PENDING)
268 /* Reset is pending. Wait and check again. */
269 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
270 msec_delay(IXGBE_CS4227_CHECK_DELAY);
273 /* If still pending, assume other instance failed. */
274 if (retry == IXGBE_CS4227_RETRIES) {
275 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
276 if (status != IXGBE_SUCCESS) {
277 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
278 "semaphore failed with %d", status);
283 /* Reset the CS4227. */
284 status = ixgbe_reset_cs4227(hw);
285 if (status != IXGBE_SUCCESS) {
286 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
287 "CS4227 reset failed: %d", status);
291 /* Reset takes so long, temporarily release semaphore in case the
292 * other driver instance is waiting for the reset indication.
294 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
295 IXGBE_CS4227_RESET_PENDING);
296 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
298 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
299 if (status != IXGBE_SUCCESS) {
300 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
301 "semaphore failed with %d", status);
305 /* Record completion for next time. */
306 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
307 IXGBE_CS4227_RESET_COMPLETE);
310 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
311 msec_delay(hw->eeprom.semaphore_delay);
315 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
316 * @hw: pointer to hardware structure
318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
320 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
322 if (hw->bus.lan_id) {
323 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
324 esdp |= IXGBE_ESDP_SDP1_DIR;
326 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
327 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
328 IXGBE_WRITE_FLUSH(hw);
332 * ixgbe_identify_phy_1g - Get 1g PHY type based on device id
333 * @hw: pointer to hardware structure
337 static s32 ixgbe_identify_phy_1g(struct ixgbe_hw *hw)
341 u32 val = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
343 hw->phy.addr = (val >> 3) & 0x1F;
344 val = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
345 hw->phy.addr, &phy_id_high);
346 if (val || phy_id_high == 0xFFFF) {
347 hw->phy.type = ixgbe_phy_sgmii;
351 val = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
352 hw->phy.addr, &phy_id_low);
356 hw->phy.id = (u32)phy_id_high << 16;
357 hw->phy.id |= phy_id_low & IXGBE_PHY_REVISION_MASK;
358 hw->phy.revision = (u32)phy_id_low & ~IXGBE_PHY_REVISION_MASK;
359 hw->phy.type = ixgbe_phy_m88;
365 * ixgbe_identify_phy_x550em - Get PHY type based on device id
366 * @hw: pointer to hardware structure
370 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
372 switch (hw->device_id) {
373 case IXGBE_DEV_ID_X550EM_A_SFP:
374 hw->phy.phy_semaphore_mask = IXGBE_GSSR_TOKEN_SM;
376 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
378 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
379 return ixgbe_identify_module_generic(hw);
380 case IXGBE_DEV_ID_X550EM_X_SFP:
381 /* set up for CS4227 usage */
382 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
383 ixgbe_setup_mux_ctl(hw);
384 ixgbe_check_cs4227(hw);
387 case IXGBE_DEV_ID_X550EM_A_SFP_N:
388 return ixgbe_identify_module_generic(hw);
390 case IXGBE_DEV_ID_X550EM_X_KX4:
391 hw->phy.type = ixgbe_phy_x550em_kx4;
393 case IXGBE_DEV_ID_X550EM_X_KR:
394 case IXGBE_DEV_ID_X550EM_A_KR:
395 case IXGBE_DEV_ID_X550EM_A_KR_L:
396 hw->phy.type = ixgbe_phy_x550em_kr;
398 case IXGBE_DEV_ID_X550EM_X_1G_T:
399 case IXGBE_DEV_ID_X550EM_X_10G_T:
400 case IXGBE_DEV_ID_X550EM_A_10G_T:
401 return ixgbe_identify_phy_generic(hw);
402 case IXGBE_DEV_ID_X550EM_A_1G_T:
403 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
404 return ixgbe_identify_phy_1g(hw);
408 return IXGBE_SUCCESS;
411 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
412 u32 device_type, u16 *phy_data)
414 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
415 return IXGBE_NOT_IMPLEMENTED;
418 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
419 u32 device_type, u16 phy_data)
421 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
422 return IXGBE_NOT_IMPLEMENTED;
426 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
427 * @hw: pointer to the hardware structure
428 * @addr: I2C bus address to read from
429 * @reg: I2C device register to read from
430 * @val: pointer to location to receive read value
432 * Returns an error code on error.
434 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
437 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
441 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
442 * @hw: pointer to the hardware structure
443 * @addr: I2C bus address to read from
444 * @reg: I2C device register to read from
445 * @val: pointer to location to receive read value
447 * Returns an error code on error.
450 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
453 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
457 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
458 * @hw: pointer to the hardware structure
459 * @addr: I2C bus address to write to
460 * @reg: I2C device register to write to
461 * @val: value to write
463 * Returns an error code on error.
465 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
466 u8 addr, u16 reg, u16 val)
468 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
472 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
473 * @hw: pointer to the hardware structure
474 * @addr: I2C bus address to write to
475 * @reg: I2C device register to write to
476 * @val: value to write
478 * Returns an error code on error.
481 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
482 u8 addr, u16 reg, u16 val)
484 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
488 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
489 * @hw: pointer to hardware structure
491 * Initialize the function pointers and for MAC type X550EM.
492 * Does not touch the hardware.
494 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
496 struct ixgbe_mac_info *mac = &hw->mac;
497 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
498 struct ixgbe_phy_info *phy = &hw->phy;
499 struct ixgbe_link_info *link = &hw->link;
502 DEBUGFUNC("ixgbe_init_ops_X550EM");
504 /* Similar to X550 so start there. */
505 ret_val = ixgbe_init_ops_X550(hw);
507 /* Since this function eventually calls
508 * ixgbe_init_ops_540 by design, we are setting
509 * the pointers to NULL explicitly here to overwrite
510 * the values being set in the x540 function.
512 /* Thermal sensor not supported in x550EM */
513 mac->ops.get_thermal_sensor_data = NULL;
514 mac->ops.init_thermal_sensor_thresh = NULL;
515 mac->thermal_sensor_enabled = false;
517 /* FCOE not supported in x550EM */
518 mac->ops.get_san_mac_addr = NULL;
519 mac->ops.set_san_mac_addr = NULL;
520 mac->ops.get_wwn_prefix = NULL;
521 mac->ops.get_fcoe_boot_status = NULL;
523 /* IPsec not supported in x550EM */
524 mac->ops.disable_sec_rx_path = NULL;
525 mac->ops.enable_sec_rx_path = NULL;
527 /* AUTOC register is not present in x550EM. */
528 mac->ops.prot_autoc_read = NULL;
529 mac->ops.prot_autoc_write = NULL;
531 /* X550EM bus type is internal*/
532 hw->bus.type = ixgbe_bus_type_internal;
533 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
535 if (hw->mac.type == ixgbe_mac_X550EM_x) {
536 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
537 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
538 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
539 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
540 link->ops.read_link = ixgbe_read_i2c_combined_generic;
541 link->ops.read_link_unlocked =
542 ixgbe_read_i2c_combined_generic_unlocked;
543 link->ops.write_link = ixgbe_write_i2c_combined_generic;
544 link->ops.write_link_unlocked =
545 ixgbe_write_i2c_combined_generic_unlocked;
546 link->addr = IXGBE_CS4227;
548 if (hw->mac.type == ixgbe_mac_X550EM_a) {
549 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
550 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
551 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
552 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
555 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
556 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
557 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
558 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
559 mac->ops.get_supported_physical_layer =
560 ixgbe_get_supported_physical_layer_X550em;
562 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
563 mac->ops.setup_fc = ixgbe_setup_fc_generic;
565 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
567 switch (hw->device_id) {
568 case IXGBE_DEV_ID_X550EM_X_KR:
569 case IXGBE_DEV_ID_X550EM_A_KR:
570 case IXGBE_DEV_ID_X550EM_A_KR_L:
573 mac->ops.setup_eee = NULL;
577 phy->ops.init = ixgbe_init_phy_ops_X550em;
578 phy->ops.identify = ixgbe_identify_phy_x550em;
579 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
580 phy->ops.set_phy_power = NULL;
584 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
585 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
586 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
587 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
588 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
589 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
590 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
591 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
597 * ixgbe_dmac_config_X550
598 * @hw: pointer to hardware structure
600 * Configure DMA coalescing. If enabling dmac, dmac is activated.
601 * When disabling dmac, dmac enable dmac bit is cleared.
603 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
605 u32 reg, high_pri_tc;
607 DEBUGFUNC("ixgbe_dmac_config_X550");
609 /* Disable DMA coalescing before configuring */
610 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
611 reg &= ~IXGBE_DMACR_DMAC_EN;
612 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
614 /* Disable DMA Coalescing if the watchdog timer is 0 */
615 if (!hw->mac.dmac_config.watchdog_timer)
618 ixgbe_dmac_config_tcs_X550(hw);
620 /* Configure DMA Coalescing Control Register */
621 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
623 /* Set the watchdog timer in units of 40.96 usec */
624 reg &= ~IXGBE_DMACR_DMACWT_MASK;
625 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
627 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
628 /* If fcoe is enabled, set high priority traffic class */
629 if (hw->mac.dmac_config.fcoe_en) {
630 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
631 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
632 IXGBE_DMACR_HIGH_PRI_TC_MASK);
634 reg |= IXGBE_DMACR_EN_MNG_IND;
636 /* Enable DMA coalescing after configuration */
637 reg |= IXGBE_DMACR_DMAC_EN;
638 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
641 return IXGBE_SUCCESS;
645 * ixgbe_dmac_config_tcs_X550
646 * @hw: pointer to hardware structure
648 * Configure DMA coalescing threshold per TC. The dmac enable bit must
649 * be cleared before configuring.
651 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
653 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
655 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
657 /* Configure DMA coalescing enabled */
658 switch (hw->mac.dmac_config.link_speed) {
659 case IXGBE_LINK_SPEED_100_FULL:
660 pb_headroom = IXGBE_DMACRXT_100M;
662 case IXGBE_LINK_SPEED_1GB_FULL:
663 pb_headroom = IXGBE_DMACRXT_1G;
666 pb_headroom = IXGBE_DMACRXT_10G;
670 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
671 IXGBE_MHADD_MFS_SHIFT) / 1024);
673 /* Set the per Rx packet buffer receive threshold */
674 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
675 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
676 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
678 if (tc < hw->mac.dmac_config.num_tcs) {
680 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
681 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
682 IXGBE_RXPBSIZE_SHIFT;
684 /* Calculate receive buffer threshold in kilobytes */
685 if (rx_pb_size > pb_headroom)
686 rx_pb_size = rx_pb_size - pb_headroom;
690 /* Minimum of MFS shall be set for DMCTH */
691 reg |= (rx_pb_size > maxframe_size_kb) ?
692 rx_pb_size : maxframe_size_kb;
694 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
696 return IXGBE_SUCCESS;
700 * ixgbe_dmac_update_tcs_X550
701 * @hw: pointer to hardware structure
703 * Disables dmac, updates per TC settings, and then enables dmac.
705 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
709 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
711 /* Disable DMA coalescing before configuring */
712 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
713 reg &= ~IXGBE_DMACR_DMAC_EN;
714 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
716 ixgbe_dmac_config_tcs_X550(hw);
718 /* Enable DMA coalescing after configuration */
719 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
720 reg |= IXGBE_DMACR_DMAC_EN;
721 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
723 return IXGBE_SUCCESS;
727 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
728 * @hw: pointer to hardware structure
730 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
731 * ixgbe_hw struct in order to set up EEPROM access.
733 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
735 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
739 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
741 if (eeprom->type == ixgbe_eeprom_uninitialized) {
742 eeprom->semaphore_delay = 10;
743 eeprom->type = ixgbe_flash;
745 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
746 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
747 IXGBE_EEC_SIZE_SHIFT);
748 eeprom->word_size = 1 << (eeprom_size +
749 IXGBE_EEPROM_WORD_SIZE_SHIFT);
751 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
752 eeprom->type, eeprom->word_size);
755 return IXGBE_SUCCESS;
759 * ixgbe_enable_eee_x550 - Enable EEE support
760 * @hw: pointer to hardware structure
762 static s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
768 if (hw->mac.type == ixgbe_mac_X550) {
769 /* Advertise EEE capability */
770 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
771 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
774 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
775 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
776 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
778 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
779 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
781 return IXGBE_SUCCESS;
784 switch (hw->device_id) {
785 case IXGBE_DEV_ID_X550EM_X_KR:
786 case IXGBE_DEV_ID_X550EM_A_KR:
787 case IXGBE_DEV_ID_X550EM_A_KR_L:
788 status = hw->mac.ops.read_iosf_sb_reg(hw,
789 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
790 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
791 if (status != IXGBE_SUCCESS)
794 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
795 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
797 /* Don't advertise FEC capability when EEE enabled. */
798 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
800 status = hw->mac.ops.write_iosf_sb_reg(hw,
801 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
802 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
803 if (status != IXGBE_SUCCESS)
810 return IXGBE_SUCCESS;
814 * ixgbe_disable_eee_x550 - Disable EEE support
815 * @hw: pointer to hardware structure
817 static s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
823 if (hw->mac.type == ixgbe_mac_X550) {
824 /* Disable advertised EEE capability */
825 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
826 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
829 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
830 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
831 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
833 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
834 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
836 return IXGBE_SUCCESS;
839 switch (hw->device_id) {
840 case IXGBE_DEV_ID_X550EM_X_KR:
841 case IXGBE_DEV_ID_X550EM_A_KR:
842 case IXGBE_DEV_ID_X550EM_A_KR_L:
843 status = hw->mac.ops.read_iosf_sb_reg(hw,
844 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
845 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
846 if (status != IXGBE_SUCCESS)
849 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
850 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
852 /* Advertise FEC capability when EEE is disabled. */
853 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
855 status = hw->mac.ops.write_iosf_sb_reg(hw,
856 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
857 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
858 if (status != IXGBE_SUCCESS)
865 return IXGBE_SUCCESS;
869 * ixgbe_setup_eee_X550 - Enable/disable EEE support
870 * @hw: pointer to the HW structure
871 * @enable_eee: boolean flag to enable EEE
873 * Enable/disable EEE based on enable_eee flag.
874 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
878 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
883 DEBUGFUNC("ixgbe_setup_eee_X550");
885 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
886 /* Enable or disable EEE per flag */
888 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
890 /* Not supported on first revision of X550EM_x. */
891 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
892 !(IXGBE_FUSES0_REV_MASK &
893 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
894 return IXGBE_SUCCESS;
895 status = ixgbe_enable_eee_x550(hw);
899 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
901 status = ixgbe_disable_eee_x550(hw);
905 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
907 return IXGBE_SUCCESS;
911 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
912 * @hw: pointer to hardware structure
913 * @enable: enable or disable source address pruning
914 * @pool: Rx pool to set source address pruning for
916 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
921 /* max rx pool is 63 */
925 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
926 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
929 pfflp |= (1ULL << pool);
931 pfflp &= ~(1ULL << pool);
933 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
934 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
938 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
939 * @hw: pointer to hardware structure
940 * @enable: enable or disable switch for Ethertype anti-spoofing
941 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
944 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
947 int vf_target_reg = vf >> 3;
948 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
951 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
953 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
955 pfvfspoof |= (1 << vf_target_shift);
957 pfvfspoof &= ~(1 << vf_target_shift);
959 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
963 * ixgbe_iosf_wait - Wait for IOSF command completion
964 * @hw: pointer to hardware structure
965 * @ctrl: pointer to location to receive final IOSF control value
967 * Returns failing status on timeout
969 * Note: ctrl can be NULL if the IOSF control register value is not needed
971 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
975 /* Check every 10 usec to see if the address cycle completed.
976 * The SB IOSF BUSY bit will clear when the operation is
979 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
980 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
981 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
987 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
988 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
989 return IXGBE_ERR_PHY;
992 return IXGBE_SUCCESS;
996 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
998 * @hw: pointer to hardware structure
999 * @reg_addr: 32 bit PHY register to write
1000 * @device_type: 3 bit device type
1001 * @data: Data to write to the register
1003 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1004 u32 device_type, u32 data)
1006 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1010 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1011 if (ret != IXGBE_SUCCESS)
1014 ret = ixgbe_iosf_wait(hw, NULL);
1015 if (ret != IXGBE_SUCCESS)
1018 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1019 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1021 /* Write IOSF control register */
1022 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1024 /* Write IOSF data register */
1025 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1027 ret = ixgbe_iosf_wait(hw, &command);
1029 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1030 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1031 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1032 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1033 "Failed to write, error %x\n", error);
1034 ret = IXGBE_ERR_PHY;
1038 ixgbe_release_swfw_semaphore(hw, gssr);
1043 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1045 * @hw: pointer to hardware structure
1046 * @reg_addr: 32 bit PHY register to write
1047 * @device_type: 3 bit device type
1048 * @phy_data: Pointer to read data from the register
1050 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1051 u32 device_type, u32 *data)
1053 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1057 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1058 if (ret != IXGBE_SUCCESS)
1061 ret = ixgbe_iosf_wait(hw, NULL);
1062 if (ret != IXGBE_SUCCESS)
1065 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1066 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1068 /* Write IOSF control register */
1069 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1071 ret = ixgbe_iosf_wait(hw, &command);
1073 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1074 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1075 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1076 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1077 "Failed to read, error %x\n", error);
1078 ret = IXGBE_ERR_PHY;
1081 if (ret == IXGBE_SUCCESS)
1082 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1085 ixgbe_release_swfw_semaphore(hw, gssr);
1090 * ixgbe_get_phy_token - Get the token for shared phy access
1091 * @hw: Pointer to hardware structure
1094 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1096 struct ixgbe_hic_phy_token_req token_cmd;
1099 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1100 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1101 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1102 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1103 token_cmd.port_number = hw->bus.lan_id;
1104 token_cmd.command_type = FW_PHY_TOKEN_REQ;
1106 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1108 IXGBE_HI_COMMAND_TIMEOUT,
1112 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1113 return IXGBE_SUCCESS;
1114 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1115 return IXGBE_ERR_FW_RESP_INVALID;
1117 return IXGBE_ERR_TOKEN_RETRY;
1121 * ixgbe_put_phy_token - Put the token for shared phy access
1122 * @hw: Pointer to hardware structure
1125 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1127 struct ixgbe_hic_phy_token_req token_cmd;
1130 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1131 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1132 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1133 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1134 token_cmd.port_number = hw->bus.lan_id;
1135 token_cmd.command_type = FW_PHY_TOKEN_REL;
1137 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1139 IXGBE_HI_COMMAND_TIMEOUT,
1143 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1144 return IXGBE_SUCCESS;
1145 return IXGBE_ERR_FW_RESP_INVALID;
1149 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1150 * of the IOSF device
1151 * @hw: pointer to hardware structure
1152 * @reg_addr: 32 bit PHY register to write
1153 * @device_type: 3 bit device type
1154 * @data: Data to write to the register
1156 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1157 u32 device_type, u32 data)
1159 struct ixgbe_hic_internal_phy_req write_cmd;
1161 UNREFERENCED_1PARAMETER(device_type);
1163 memset(&write_cmd, 0, sizeof(write_cmd));
1164 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1165 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1166 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1167 write_cmd.port_number = hw->bus.lan_id;
1168 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1169 write_cmd.address = (u16)reg_addr;
1170 write_cmd.write_data = data;
1172 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1174 IXGBE_HI_COMMAND_TIMEOUT, false);
1180 * ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
1181 * of the IOSF device.
1182 * @hw: pointer to hardware structure
1183 * @reg_addr: 32 bit PHY register to write
1184 * @device_type: 3 bit device type
1185 * @data: Pointer to read data from the register
1187 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1188 u32 device_type, u32 *data)
1190 struct ixgbe_hic_internal_phy_req read_cmd;
1192 UNREFERENCED_1PARAMETER(device_type);
1194 memset(&read_cmd, 0, sizeof(read_cmd));
1195 read_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1196 read_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1197 read_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1198 read_cmd.port_number = hw->bus.lan_id;
1199 read_cmd.command_type = FW_INT_PHY_REQ_READ;
1200 read_cmd.address = (u16)reg_addr;
1202 status = ixgbe_host_interface_command(hw, (u32 *)&read_cmd,
1204 IXGBE_HI_COMMAND_TIMEOUT, true);
1206 /* Extract the register value from the response. */
1207 *data = ((struct ixgbe_hic_internal_phy_resp *)&read_cmd)->read_data;
1213 * ixgbe_disable_mdd_X550
1214 * @hw: pointer to hardware structure
1216 * Disable malicious driver detection
1218 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1222 DEBUGFUNC("ixgbe_disable_mdd_X550");
1224 /* Disable MDD for TX DMA and interrupt */
1225 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1226 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1227 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1229 /* Disable MDD for RX and interrupt */
1230 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1231 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1232 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1236 * ixgbe_enable_mdd_X550
1237 * @hw: pointer to hardware structure
1239 * Enable malicious driver detection
1241 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1245 DEBUGFUNC("ixgbe_enable_mdd_X550");
1247 /* Enable MDD for TX DMA and interrupt */
1248 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1249 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1250 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1252 /* Enable MDD for RX and interrupt */
1253 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1254 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1255 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1259 * ixgbe_restore_mdd_vf_X550
1260 * @hw: pointer to hardware structure
1263 * Restore VF that was disabled during malicious driver detection event
1265 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1267 u32 idx, reg, num_qs, start_q, bitmask;
1269 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1271 /* Map VF to queues */
1272 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1273 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1274 case IXGBE_MRQC_VMDQRT8TCEN:
1275 num_qs = 8; /* 16 VFs / pools */
1276 bitmask = 0x000000FF;
1278 case IXGBE_MRQC_VMDQRSS32EN:
1279 case IXGBE_MRQC_VMDQRT4TCEN:
1280 num_qs = 4; /* 32 VFs / pools */
1281 bitmask = 0x0000000F;
1283 default: /* 64 VFs / pools */
1285 bitmask = 0x00000003;
1288 start_q = vf * num_qs;
1290 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1293 reg |= (bitmask << (start_q % 32));
1294 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1295 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1299 * ixgbe_mdd_event_X550
1300 * @hw: pointer to hardware structure
1301 * @vf_bitmap: vf bitmap of malicious vfs
1303 * Handle malicious driver detection event.
1305 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1308 u32 i, j, reg, q, shift, vf, idx;
1310 DEBUGFUNC("ixgbe_mdd_event_X550");
1312 /* figure out pool size for mapping to vf's */
1313 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1314 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1315 case IXGBE_MRQC_VMDQRT8TCEN:
1316 shift = 3; /* 16 VFs / pools */
1318 case IXGBE_MRQC_VMDQRSS32EN:
1319 case IXGBE_MRQC_VMDQRT4TCEN:
1320 shift = 2; /* 32 VFs / pools */
1323 shift = 1; /* 64 VFs / pools */
1327 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1328 for (i = 0; i < 4; i++) {
1329 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1330 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1335 /* Get malicious queue */
1336 for (j = 0; j < 32 && wqbr; j++) {
1338 if (!(wqbr & (1 << j)))
1341 /* Get queue from bitmask */
1344 /* Map queue to vf */
1347 /* Set vf bit in vf_bitmap */
1349 vf_bitmap[idx] |= (1 << (vf % 32));
1356 * ixgbe_get_media_type_X550em - Get media type
1357 * @hw: pointer to hardware structure
1359 * Returns the media type (fiber, copper, backplane)
1361 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1363 enum ixgbe_media_type media_type;
1365 DEBUGFUNC("ixgbe_get_media_type_X550em");
1367 /* Detect if there is a copper PHY attached. */
1368 switch (hw->device_id) {
1369 case IXGBE_DEV_ID_X550EM_X_KR:
1370 case IXGBE_DEV_ID_X550EM_X_KX4:
1371 case IXGBE_DEV_ID_X550EM_A_KR:
1372 case IXGBE_DEV_ID_X550EM_A_KR_L:
1373 media_type = ixgbe_media_type_backplane;
1375 case IXGBE_DEV_ID_X550EM_X_SFP:
1376 case IXGBE_DEV_ID_X550EM_A_SFP:
1377 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1378 case IXGBE_DEV_ID_X550EM_A_QSFP:
1379 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1380 media_type = ixgbe_media_type_fiber;
1382 case IXGBE_DEV_ID_X550EM_X_1G_T:
1383 case IXGBE_DEV_ID_X550EM_X_10G_T:
1384 case IXGBE_DEV_ID_X550EM_A_10G_T:
1385 media_type = ixgbe_media_type_copper;
1387 case IXGBE_DEV_ID_X550EM_A_1G_T:
1388 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1389 media_type = ixgbe_media_type_sgmii;
1390 hw->phy.type = ixgbe_phy_sgmii;
1393 media_type = ixgbe_media_type_unknown;
1400 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1401 * @hw: pointer to hardware structure
1402 * @linear: true if SFP module is linear
1404 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1406 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1408 switch (hw->phy.sfp_type) {
1409 case ixgbe_sfp_type_not_present:
1410 return IXGBE_ERR_SFP_NOT_PRESENT;
1411 case ixgbe_sfp_type_da_cu_core0:
1412 case ixgbe_sfp_type_da_cu_core1:
1415 case ixgbe_sfp_type_srlr_core0:
1416 case ixgbe_sfp_type_srlr_core1:
1417 case ixgbe_sfp_type_da_act_lmt_core0:
1418 case ixgbe_sfp_type_da_act_lmt_core1:
1419 case ixgbe_sfp_type_1g_sx_core0:
1420 case ixgbe_sfp_type_1g_sx_core1:
1421 case ixgbe_sfp_type_1g_lx_core0:
1422 case ixgbe_sfp_type_1g_lx_core1:
1425 case ixgbe_sfp_type_unknown:
1426 case ixgbe_sfp_type_1g_cu_core0:
1427 case ixgbe_sfp_type_1g_cu_core1:
1429 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1432 return IXGBE_SUCCESS;
1436 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1437 * @hw: pointer to hardware structure
1439 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1441 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1446 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1448 status = ixgbe_identify_module_generic(hw);
1450 if (status != IXGBE_SUCCESS)
1453 /* Check if SFP module is supported */
1454 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1460 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1461 * @hw: pointer to hardware structure
1463 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1468 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1470 /* Check if SFP module is supported */
1471 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1473 if (status != IXGBE_SUCCESS)
1476 ixgbe_init_mac_link_ops_X550em(hw);
1477 hw->phy.ops.reset = NULL;
1479 return IXGBE_SUCCESS;
1483 * ixgbe_setup_sgmii - Set up link for sgmii
1484 * @hw: pointer to hardware structure
1486 static s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1487 bool autoneg_wait_to_complete)
1489 struct ixgbe_mac_info *mac = &hw->mac;
1492 UNREFERENCED_2PARAMETER(speed, autoneg_wait_to_complete);
1494 rc = mac->ops.read_iosf_sb_reg(hw,
1495 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1496 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1500 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1501 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1502 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1503 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1504 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1505 rc = mac->ops.write_iosf_sb_reg(hw,
1506 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1507 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1511 rc = mac->ops.read_iosf_sb_reg(hw,
1512 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1513 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1517 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1518 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1519 rc = mac->ops.write_iosf_sb_reg(hw,
1520 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1521 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1525 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1526 rc = mac->ops.write_iosf_sb_reg(hw,
1527 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1528 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1534 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1535 * @hw: pointer to hardware structure
1537 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1539 struct ixgbe_mac_info *mac = &hw->mac;
1541 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1543 switch (hw->mac.ops.get_media_type(hw)) {
1544 case ixgbe_media_type_fiber:
1545 /* CS4227 does not support autoneg, so disable the laser control
1546 * functions for SFP+ fiber
1548 mac->ops.disable_tx_laser = NULL;
1549 mac->ops.enable_tx_laser = NULL;
1550 mac->ops.flap_tx_laser = NULL;
1551 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1552 mac->ops.set_rate_select_speed =
1553 ixgbe_set_soft_rate_select_speed;
1554 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1555 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1556 mac->ops.setup_mac_link =
1557 ixgbe_setup_mac_link_sfp_x550a;
1559 mac->ops.setup_mac_link =
1560 ixgbe_setup_mac_link_sfp_x550em;
1562 case ixgbe_media_type_copper:
1563 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1564 mac->ops.check_link = ixgbe_check_link_t_X550em;
1566 case ixgbe_media_type_backplane:
1568 case ixgbe_media_type_sgmii:
1569 mac->ops.setup_link = ixgbe_setup_sgmii;
1577 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1578 * @hw: pointer to hardware structure
1579 * @speed: pointer to link speed
1580 * @autoneg: true when autoneg or autotry is enabled
1582 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1583 ixgbe_link_speed *speed,
1586 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1589 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1591 /* CS4227 SFP must not enable auto-negotiation */
1594 /* Check if 1G SFP module. */
1595 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1596 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1597 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1598 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1599 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1600 return IXGBE_SUCCESS;
1603 /* Link capabilities are based on SFP */
1604 if (hw->phy.multispeed_fiber)
1605 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1606 IXGBE_LINK_SPEED_1GB_FULL;
1608 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1610 switch (hw->phy.type) {
1612 *speed = IXGBE_LINK_SPEED_100_FULL |
1613 IXGBE_LINK_SPEED_1GB_FULL;
1615 case ixgbe_phy_sgmii:
1616 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1619 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1620 IXGBE_LINK_SPEED_1GB_FULL;
1626 return IXGBE_SUCCESS;
1630 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1631 * @hw: pointer to hardware structure
1632 * @lsc: pointer to boolean flag which indicates whether external Base T
1633 * PHY interrupt is lsc
1635 * Determime if external Base T PHY interrupt cause is high temperature
1636 * failure alarm or link status change.
1638 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1639 * failure alarm, else return PHY access status.
1641 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1648 /* Vendor alarm triggered */
1649 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1650 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1653 if (status != IXGBE_SUCCESS ||
1654 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1657 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1658 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1659 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1662 if (status != IXGBE_SUCCESS ||
1663 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1664 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1667 /* Global alarm triggered */
1668 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1669 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1672 if (status != IXGBE_SUCCESS)
1675 /* If high temperature failure, then return over temp error and exit */
1676 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1677 /* power down the PHY in case the PHY FW didn't already */
1678 ixgbe_set_copper_phy_power(hw, false);
1679 return IXGBE_ERR_OVERTEMP;
1680 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1681 /* device fault alarm triggered */
1682 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1683 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1686 if (status != IXGBE_SUCCESS)
1689 /* if device fault was due to high temp alarm handle and exit */
1690 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1691 /* power down the PHY in case the PHY FW didn't */
1692 ixgbe_set_copper_phy_power(hw, false);
1693 return IXGBE_ERR_OVERTEMP;
1697 /* Vendor alarm 2 triggered */
1698 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1699 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1701 if (status != IXGBE_SUCCESS ||
1702 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1705 /* link connect/disconnect event occurred */
1706 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1707 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1709 if (status != IXGBE_SUCCESS)
1713 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1716 return IXGBE_SUCCESS;
1720 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1721 * @hw: pointer to hardware structure
1723 * Enable link status change and temperature failure alarm for the external
1726 * Returns PHY access status
1728 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1734 /* Clear interrupt flags */
1735 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1737 /* Enable link status change alarm */
1738 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1739 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1741 if (status != IXGBE_SUCCESS)
1744 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1746 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1747 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1749 if (status != IXGBE_SUCCESS)
1752 /* Enable high temperature failure and global fault alarms */
1753 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1754 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1757 if (status != IXGBE_SUCCESS)
1760 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1761 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1763 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1764 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1767 if (status != IXGBE_SUCCESS)
1770 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1771 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1772 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1775 if (status != IXGBE_SUCCESS)
1778 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1779 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1781 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1782 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1785 if (status != IXGBE_SUCCESS)
1788 /* Enable chip-wide vendor alarm */
1789 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1790 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1793 if (status != IXGBE_SUCCESS)
1796 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1798 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1799 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1806 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1807 * @hw: pointer to hardware structure
1808 * @speed: link speed
1810 * Configures the integrated KR PHY.
1812 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1813 ixgbe_link_speed speed)
1818 status = hw->mac.ops.read_iosf_sb_reg(hw,
1819 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1820 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1824 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1825 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1826 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1828 /* Advertise 10G support. */
1829 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1830 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1832 /* Advertise 1G support. */
1833 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1834 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1836 /* Restart auto-negotiation. */
1837 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1838 status = hw->mac.ops.write_iosf_sb_reg(hw,
1839 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1840 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1846 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1847 * @hw: pointer to hardware structure
1849 * Initialize any function pointers that were not able to be
1850 * set during init_shared_code because the PHY/SFP type was
1851 * not known. Perform the SFP init if necessary.
1853 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1855 struct ixgbe_phy_info *phy = &hw->phy;
1858 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1860 hw->mac.ops.set_lan_id(hw);
1862 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1863 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1864 ixgbe_setup_mux_ctl(hw);
1866 /* Save NW management interface connected on board. This is used
1867 * to determine internal PHY mode.
1869 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1870 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1873 /* Identify the PHY or SFP module */
1874 ret_val = phy->ops.identify(hw);
1875 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1878 /* Setup function pointers based on detected hardware */
1879 ixgbe_init_mac_link_ops_X550em(hw);
1880 if (phy->sfp_type != ixgbe_sfp_type_unknown)
1881 phy->ops.reset = NULL;
1883 /* Set functions pointers based on phy type */
1884 switch (hw->phy.type) {
1885 case ixgbe_phy_x550em_kx4:
1886 phy->ops.setup_link = NULL;
1887 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1888 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1890 case ixgbe_phy_x550em_kr:
1891 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1892 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1893 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1895 case ixgbe_phy_x550em_ext_t:
1896 /* Save NW management interface connected on board. This is used
1897 * to determine internal PHY mode
1899 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1901 /* If internal link mode is XFI, then setup iXFI internal link,
1902 * else setup KR now.
1904 phy->ops.setup_internal_link =
1905 ixgbe_setup_internal_phy_t_x550em;
1907 /* setup SW LPLU only for first revision of X550EM_x */
1908 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1909 !(IXGBE_FUSES0_REV_MASK &
1910 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1911 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1913 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1914 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1916 case ixgbe_phy_sgmii:
1917 phy->ops.setup_link = NULL;
1928 * ixgbe_set_mdio_speed - Set MDIO clock speed
1929 * @hw: pointer to hardware structure
1931 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
1935 switch (hw->device_id) {
1936 case IXGBE_DEV_ID_X550EM_X_10G_T:
1937 case IXGBE_DEV_ID_X550EM_A_1G_T:
1938 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1939 case IXGBE_DEV_ID_X550EM_A_10G_T:
1940 case IXGBE_DEV_ID_X550EM_A_SFP:
1941 case IXGBE_DEV_ID_X550EM_A_QSFP:
1942 /* Config MDIO clock speed before the first MDIO PHY access */
1943 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1944 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1945 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1953 * ixgbe_reset_hw_X550em - Perform hardware reset
1954 * @hw: pointer to hardware structure
1956 * Resets the hardware by resetting the transmit and receive units, masks
1957 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1960 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1962 ixgbe_link_speed link_speed;
1966 bool link_up = false;
1968 DEBUGFUNC("ixgbe_reset_hw_X550em");
1970 /* Call adapter stop to disable Tx/Rx and clear interrupts */
1971 status = hw->mac.ops.stop_adapter(hw);
1972 if (status != IXGBE_SUCCESS)
1975 /* flush pending Tx transactions */
1976 ixgbe_clear_tx_pending(hw);
1978 ixgbe_set_mdio_speed(hw);
1980 /* PHY ops must be identified and initialized prior to reset */
1981 status = hw->phy.ops.init(hw);
1983 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1986 /* start the external PHY */
1987 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1988 status = ixgbe_init_ext_t_x550em(hw);
1993 /* Setup SFP module if there is one present. */
1994 if (hw->phy.sfp_setup_needed) {
1995 status = hw->mac.ops.setup_sfp(hw);
1996 hw->phy.sfp_setup_needed = false;
1999 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2003 if (!hw->phy.reset_disable && hw->phy.ops.reset)
2004 hw->phy.ops.reset(hw);
2007 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
2008 * If link reset is used when link is up, it might reset the PHY when
2009 * mng is using it. If link is down or the flag to force full link
2010 * reset is set, then perform link reset.
2012 ctrl = IXGBE_CTRL_LNK_RST;
2013 if (!hw->force_full_reset) {
2014 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2016 ctrl = IXGBE_CTRL_RST;
2019 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2020 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2021 IXGBE_WRITE_FLUSH(hw);
2023 /* Poll for reset bit to self-clear meaning reset is complete */
2024 for (i = 0; i < 10; i++) {
2026 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2027 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2031 if (ctrl & IXGBE_CTRL_RST_MASK) {
2032 status = IXGBE_ERR_RESET_FAILED;
2033 DEBUGOUT("Reset polling failed to complete.\n");
2038 /* Double resets are required for recovery from certain error
2039 * conditions. Between resets, it is necessary to stall to
2040 * allow time for any pending HW events to complete.
2042 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2043 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2047 /* Store the permanent mac address */
2048 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2050 /* Store MAC address from RAR0, clear receive address registers, and
2051 * clear the multicast table. Also reset num_rar_entries to 128,
2052 * since we modify this value when programming the SAN MAC address.
2054 hw->mac.num_rar_entries = 128;
2055 hw->mac.ops.init_rx_addrs(hw);
2057 ixgbe_set_mdio_speed(hw);
2059 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2060 ixgbe_setup_mux_ctl(hw);
2066 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2067 * @hw: pointer to hardware structure
2069 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2074 status = hw->phy.ops.read_reg(hw,
2075 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2076 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2079 if (status != IXGBE_SUCCESS)
2082 /* If PHY FW reset completed bit is set then this is the first
2083 * SW instance after a power on so the PHY FW must be un-stalled.
2085 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2086 status = hw->phy.ops.read_reg(hw,
2087 IXGBE_MDIO_GLOBAL_RES_PR_10,
2088 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2091 if (status != IXGBE_SUCCESS)
2094 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2096 status = hw->phy.ops.write_reg(hw,
2097 IXGBE_MDIO_GLOBAL_RES_PR_10,
2098 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2101 if (status != IXGBE_SUCCESS)
2109 * ixgbe_setup_kr_x550em - Configure the KR PHY.
2110 * @hw: pointer to hardware structure
2112 * Configures the integrated KR PHY for X550EM_x.
2114 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2116 if (hw->mac.type != ixgbe_mac_X550EM_x)
2117 return IXGBE_SUCCESS;
2119 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2123 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2124 * @hw: pointer to hardware structure
2126 * Configure the external PHY and the integrated KR PHY for SFP support.
2128 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2129 ixgbe_link_speed speed,
2130 bool autoneg_wait_to_complete)
2133 u16 reg_slice, reg_val;
2134 bool setup_linear = false;
2135 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2137 /* Check if SFP module is supported and linear */
2138 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2140 /* If no SFP module present, then return success. Return success since
2141 * there is no reason to configure CS4227 and SFP not present error is
2142 * not excepted in the setup MAC link flow.
2144 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2145 return IXGBE_SUCCESS;
2147 if (ret_val != IXGBE_SUCCESS)
2150 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2151 /* Configure CS4227 LINE side to 10G SR. */
2152 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2153 (hw->bus.lan_id << 12);
2154 reg_val = IXGBE_CS4227_SPEED_10G;
2155 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2158 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2159 (hw->bus.lan_id << 12);
2160 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2161 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2164 /* Configure CS4227 for HOST connection rate then type. */
2165 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2166 (hw->bus.lan_id << 12);
2167 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2168 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2169 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2172 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2173 (hw->bus.lan_id << 12);
2175 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2177 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2178 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2181 /* Setup XFI internal link. */
2182 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2184 /* Configure internal PHY for KR/KX. */
2185 ixgbe_setup_kr_speed_x550em(hw, speed);
2187 /* Configure CS4227 LINE side to proper mode. */
2188 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2189 (hw->bus.lan_id << 12);
2191 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2193 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2194 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2201 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2202 * @hw: pointer to hardware structure
2204 * Configure the the integrated PHY for SFP support.
2206 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2207 ixgbe_link_speed speed,
2208 bool autoneg_wait_to_complete)
2212 bool setup_linear = false;
2213 u32 reg_slice, reg_phy_int, slice_offset;
2215 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2217 /* Check if SFP module is supported and linear */
2218 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2220 /* If no SFP module present, then return success. Return success since
2221 * SFP not present error is not excepted in the setup MAC link flow.
2223 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2224 return IXGBE_SUCCESS;
2226 if (ret_val != IXGBE_SUCCESS)
2229 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2230 /* Configure internal PHY for native SFI */
2231 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2232 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2233 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
2235 if (ret_val != IXGBE_SUCCESS)
2239 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2240 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2242 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2243 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2246 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2247 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2248 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2250 if (ret_val != IXGBE_SUCCESS)
2253 /* Setup XFI/SFI internal link. */
2254 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2256 /* Configure internal PHY for KR/KX. */
2257 ixgbe_setup_kr_speed_x550em(hw, speed);
2259 /* Get CS4227 MDIO address */
2261 (hw->phy.nw_mng_if_sel &
2262 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD)
2263 >> IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2265 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2267 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2268 return IXGBE_ERR_PHY_ADDR_INVALID;
2271 /* Get external PHY device id */
2272 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2273 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2275 if (ret_val != IXGBE_SUCCESS)
2278 /* When configuring quad port CS4223, the MAC instance is part
2279 * of the slice offset.
2281 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2282 slice_offset = (hw->bus.lan_id +
2283 (hw->bus.instance_id << 1)) << 12;
2285 slice_offset = hw->bus.lan_id << 12;
2287 /* Configure CS4227/CS4223 LINE side to proper mode. */
2288 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2290 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2292 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2293 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2294 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2300 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2301 * @hw: pointer to hardware structure
2303 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2305 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2310 /* Disable training protocol FSM. */
2311 status = ixgbe_read_iosf_sb_reg_x550(hw,
2312 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2313 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2314 if (status != IXGBE_SUCCESS)
2316 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2317 status = ixgbe_write_iosf_sb_reg_x550(hw,
2318 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2319 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2320 if (status != IXGBE_SUCCESS)
2323 /* Disable Flex from training TXFFE. */
2324 status = ixgbe_read_iosf_sb_reg_x550(hw,
2325 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2326 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2327 if (status != IXGBE_SUCCESS)
2329 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2330 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2331 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2332 status = ixgbe_write_iosf_sb_reg_x550(hw,
2333 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2334 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2335 if (status != IXGBE_SUCCESS)
2337 status = ixgbe_read_iosf_sb_reg_x550(hw,
2338 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2339 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2340 if (status != IXGBE_SUCCESS)
2342 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2343 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2344 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2345 status = ixgbe_write_iosf_sb_reg_x550(hw,
2346 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2347 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2348 if (status != IXGBE_SUCCESS)
2351 /* Enable override for coefficients. */
2352 status = ixgbe_read_iosf_sb_reg_x550(hw,
2353 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2354 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2355 if (status != IXGBE_SUCCESS)
2357 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2358 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2359 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2360 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2361 status = ixgbe_write_iosf_sb_reg_x550(hw,
2362 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2363 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2368 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2369 * @hw: pointer to hardware structure
2370 * @speed: the link speed to force
2372 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
2373 * internal and external PHY at a specific speed, without autonegotiation.
2375 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2380 /* Disable AN and force speed to 10G Serial. */
2381 status = ixgbe_read_iosf_sb_reg_x550(hw,
2382 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2383 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2384 if (status != IXGBE_SUCCESS)
2387 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2388 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2390 /* Select forced link speed for internal PHY. */
2392 case IXGBE_LINK_SPEED_10GB_FULL:
2393 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2395 case IXGBE_LINK_SPEED_1GB_FULL:
2396 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2399 /* Other link speeds are not supported by internal KR PHY. */
2400 return IXGBE_ERR_LINK_SETUP;
2403 status = ixgbe_write_iosf_sb_reg_x550(hw,
2404 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2405 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2406 if (status != IXGBE_SUCCESS)
2409 /* Additional configuration needed for x550em_x */
2410 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2411 status = ixgbe_setup_ixfi_x550em_x(hw);
2412 if (status != IXGBE_SUCCESS)
2416 /* Toggle port SW reset by AN reset. */
2417 status = ixgbe_read_iosf_sb_reg_x550(hw,
2418 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2419 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2420 if (status != IXGBE_SUCCESS)
2422 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2423 status = ixgbe_write_iosf_sb_reg_x550(hw,
2424 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2425 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2431 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2432 * @hw: address of hardware structure
2433 * @link_up: address of boolean to indicate link status
2435 * Returns error code if unable to get link status.
2437 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2444 /* read this twice back to back to indicate current status */
2445 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2446 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2448 if (ret != IXGBE_SUCCESS)
2451 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2452 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2454 if (ret != IXGBE_SUCCESS)
2457 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2459 return IXGBE_SUCCESS;
2463 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2464 * @hw: point to hardware structure
2466 * Configures the link between the integrated KR PHY and the external X557 PHY
2467 * The driver will call this function when it gets a link status change
2468 * interrupt from the X557 PHY. This function configures the link speed
2469 * between the PHYs to match the link speed of the BASE-T link.
2471 * A return of a non-zero value indicates an error, and the base driver should
2472 * not report link up.
2474 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2476 ixgbe_link_speed force_speed;
2481 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2482 return IXGBE_ERR_CONFIG;
2484 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2485 /* If link is down, there is no setup necessary so return */
2486 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2487 if (status != IXGBE_SUCCESS)
2491 return IXGBE_SUCCESS;
2493 status = hw->phy.ops.read_reg(hw,
2494 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2495 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2497 if (status != IXGBE_SUCCESS)
2500 /* If link is still down - no setup is required so return */
2501 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2502 if (status != IXGBE_SUCCESS)
2505 return IXGBE_SUCCESS;
2507 /* clear everything but the speed and duplex bits */
2508 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2511 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2512 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2514 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2515 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2518 /* Internal PHY does not support anything else */
2519 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2522 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2524 speed = IXGBE_LINK_SPEED_10GB_FULL |
2525 IXGBE_LINK_SPEED_1GB_FULL;
2526 return ixgbe_setup_kr_speed_x550em(hw, speed);
2531 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2532 * @hw: pointer to hardware structure
2534 * Configures the integrated KR PHY to use internal loopback mode.
2536 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2541 /* Disable AN and force speed to 10G Serial. */
2542 status = hw->mac.ops.read_iosf_sb_reg(hw,
2543 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2544 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2545 if (status != IXGBE_SUCCESS)
2547 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2548 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2549 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2550 status = hw->mac.ops.write_iosf_sb_reg(hw,
2551 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2552 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2553 if (status != IXGBE_SUCCESS)
2556 /* Set near-end loopback clocks. */
2557 status = hw->mac.ops.read_iosf_sb_reg(hw,
2558 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2559 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2560 if (status != IXGBE_SUCCESS)
2562 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2563 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2564 status = hw->mac.ops.write_iosf_sb_reg(hw,
2565 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2566 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2567 if (status != IXGBE_SUCCESS)
2570 /* Set loopback enable. */
2571 status = hw->mac.ops.read_iosf_sb_reg(hw,
2572 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2573 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2574 if (status != IXGBE_SUCCESS)
2576 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2577 status = hw->mac.ops.write_iosf_sb_reg(hw,
2578 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2579 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2580 if (status != IXGBE_SUCCESS)
2583 /* Training bypass. */
2584 status = hw->mac.ops.read_iosf_sb_reg(hw,
2585 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2586 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2587 if (status != IXGBE_SUCCESS)
2589 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2590 status = hw->mac.ops.write_iosf_sb_reg(hw,
2591 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2592 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2598 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2599 * assuming that the semaphore is already obtained.
2600 * @hw: pointer to hardware structure
2601 * @offset: offset of word in the EEPROM to read
2602 * @data: word read from the EEPROM
2604 * Reads a 16 bit word from the EEPROM using the hostif.
2606 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2610 struct ixgbe_hic_read_shadow_ram buffer;
2612 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2613 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2614 buffer.hdr.req.buf_lenh = 0;
2615 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2616 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2618 /* convert offset from words to bytes */
2619 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2621 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2623 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2625 IXGBE_HI_COMMAND_TIMEOUT, false);
2630 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2631 FW_NVM_DATA_OFFSET);
2637 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2638 * @hw: pointer to hardware structure
2639 * @offset: offset of word in the EEPROM to read
2640 * @data: word read from the EEPROM
2642 * Reads a 16 bit word from the EEPROM using the hostif.
2644 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2647 s32 status = IXGBE_SUCCESS;
2649 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2651 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2653 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2654 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2656 status = IXGBE_ERR_SWFW_SYNC;
2663 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2664 * @hw: pointer to hardware structure
2665 * @offset: offset of word in the EEPROM to read
2666 * @words: number of words
2667 * @data: word(s) read from the EEPROM
2669 * Reads a 16 bit word(s) from the EEPROM using the hostif.
2671 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2672 u16 offset, u16 words, u16 *data)
2674 struct ixgbe_hic_read_shadow_ram buffer;
2675 u32 current_word = 0;
2680 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2682 /* Take semaphore for the entire operation. */
2683 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2685 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2689 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2690 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2692 words_to_read = words;
2694 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2695 buffer.hdr.req.buf_lenh = 0;
2696 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2697 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2699 /* convert offset from words to bytes */
2700 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2701 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2703 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2705 IXGBE_HI_COMMAND_TIMEOUT,
2709 DEBUGOUT("Host interface command failed\n");
2713 for (i = 0; i < words_to_read; i++) {
2714 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2716 u32 value = IXGBE_READ_REG(hw, reg);
2718 data[current_word] = (u16)(value & 0xffff);
2721 if (i < words_to_read) {
2723 data[current_word] = (u16)(value & 0xffff);
2727 words -= words_to_read;
2731 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2736 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2737 * @hw: pointer to hardware structure
2738 * @offset: offset of word in the EEPROM to write
2739 * @data: word write to the EEPROM
2741 * Write a 16 bit word to the EEPROM using the hostif.
2743 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2747 struct ixgbe_hic_write_shadow_ram buffer;
2749 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2751 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2752 buffer.hdr.req.buf_lenh = 0;
2753 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2754 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2757 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2759 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2761 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2763 IXGBE_HI_COMMAND_TIMEOUT, false);
2769 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2770 * @hw: pointer to hardware structure
2771 * @offset: offset of word in the EEPROM to write
2772 * @data: word write to the EEPROM
2774 * Write a 16 bit word to the EEPROM using the hostif.
2776 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2779 s32 status = IXGBE_SUCCESS;
2781 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2783 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2785 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2786 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2788 DEBUGOUT("write ee hostif failed to get semaphore");
2789 status = IXGBE_ERR_SWFW_SYNC;
2796 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2797 * @hw: pointer to hardware structure
2798 * @offset: offset of word in the EEPROM to write
2799 * @words: number of words
2800 * @data: word(s) write to the EEPROM
2802 * Write a 16 bit word(s) to the EEPROM using the hostif.
2804 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2805 u16 offset, u16 words, u16 *data)
2807 s32 status = IXGBE_SUCCESS;
2810 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2812 /* Take semaphore for the entire operation. */
2813 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2814 if (status != IXGBE_SUCCESS) {
2815 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2819 for (i = 0; i < words; i++) {
2820 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2823 if (status != IXGBE_SUCCESS) {
2824 DEBUGOUT("Eeprom buffered write failed\n");
2829 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2836 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2837 * @hw: pointer to hardware structure
2838 * @ptr: pointer offset in eeprom
2839 * @size: size of section pointed by ptr, if 0 first word will be used as size
2840 * @csum: address of checksum to update
2842 * Returns error status for any failure
2844 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2845 u16 size, u16 *csum, u16 *buffer,
2850 u16 length, bufsz, i, start;
2853 bufsz = sizeof(buf) / sizeof(buf[0]);
2855 /* Read a chunk at the pointer location */
2857 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2859 DEBUGOUT("Failed to read EEPROM image\n");
2864 if (buffer_size < ptr)
2865 return IXGBE_ERR_PARAM;
2866 local_buffer = &buffer[ptr];
2874 length = local_buffer[0];
2876 /* Skip pointer section if length is invalid. */
2877 if (length == 0xFFFF || length == 0 ||
2878 (ptr + length) >= hw->eeprom.word_size)
2879 return IXGBE_SUCCESS;
2882 if (buffer && ((u32)start + (u32)length > buffer_size))
2883 return IXGBE_ERR_PARAM;
2885 for (i = start; length; i++, length--) {
2886 if (i == bufsz && !buffer) {
2892 /* Read a chunk at the pointer location */
2893 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2896 DEBUGOUT("Failed to read EEPROM image\n");
2900 *csum += local_buffer[i];
2902 return IXGBE_SUCCESS;
2906 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2907 * @hw: pointer to hardware structure
2908 * @buffer: pointer to buffer containing calculated checksum
2909 * @buffer_size: size of buffer
2911 * Returns a negative error code on error, or the 16-bit checksum
2913 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2915 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2919 u16 pointer, i, size;
2921 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2923 hw->eeprom.ops.init_params(hw);
2926 /* Read pointer area */
2927 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2928 IXGBE_EEPROM_LAST_WORD + 1,
2931 DEBUGOUT("Failed to read EEPROM image\n");
2934 local_buffer = eeprom_ptrs;
2936 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2937 return IXGBE_ERR_PARAM;
2938 local_buffer = buffer;
2942 * For X550 hardware include 0x0-0x41 in the checksum, skip the
2943 * checksum word itself
2945 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2946 if (i != IXGBE_EEPROM_CHECKSUM)
2947 checksum += local_buffer[i];
2950 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
2951 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2953 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2954 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2957 pointer = local_buffer[i];
2959 /* Skip pointer section if the pointer is invalid. */
2960 if (pointer == 0xFFFF || pointer == 0 ||
2961 pointer >= hw->eeprom.word_size)
2965 case IXGBE_PCIE_GENERAL_PTR:
2966 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2968 case IXGBE_PCIE_CONFIG0_PTR:
2969 case IXGBE_PCIE_CONFIG1_PTR:
2970 size = IXGBE_PCIE_CONFIG_SIZE;
2977 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2978 buffer, buffer_size);
2983 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2985 return (s32)checksum;
2989 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2990 * @hw: pointer to hardware structure
2992 * Returns a negative error code on error, or the 16-bit checksum
2994 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2996 return ixgbe_calc_checksum_X550(hw, NULL, 0);
3000 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3001 * @hw: pointer to hardware structure
3002 * @checksum_val: calculated checksum
3004 * Performs checksum calculation and validates the EEPROM checksum. If the
3005 * caller does not need checksum_val, the value can be NULL.
3007 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3011 u16 read_checksum = 0;
3013 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3015 /* Read the first word from the EEPROM. If this times out or fails, do
3016 * not continue or we could be in for a very long wait while every
3019 status = hw->eeprom.ops.read(hw, 0, &checksum);
3021 DEBUGOUT("EEPROM read failed\n");
3025 status = hw->eeprom.ops.calc_checksum(hw);
3029 checksum = (u16)(status & 0xffff);
3031 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3036 /* Verify read checksum from EEPROM is the same as
3037 * calculated checksum
3039 if (read_checksum != checksum) {
3040 status = IXGBE_ERR_EEPROM_CHECKSUM;
3041 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3042 "Invalid EEPROM checksum");
3045 /* If the user cares, return the calculated checksum */
3047 *checksum_val = checksum;
3053 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3054 * @hw: pointer to hardware structure
3056 * After writing EEPROM to shadow RAM using EEWR register, software calculates
3057 * checksum and updates the EEPROM and instructs the hardware to update
3060 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3065 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3067 /* Read the first word from the EEPROM. If this times out or fails, do
3068 * not continue or we could be in for a very long wait while every
3071 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3073 DEBUGOUT("EEPROM read failed\n");
3077 status = ixgbe_calc_eeprom_checksum_X550(hw);
3081 checksum = (u16)(status & 0xffff);
3083 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3088 status = ixgbe_update_flash_X550(hw);
3094 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3095 * @hw: pointer to hardware structure
3097 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3099 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3101 s32 status = IXGBE_SUCCESS;
3102 union ixgbe_hic_hdr2 buffer;
3104 DEBUGFUNC("ixgbe_update_flash_X550");
3106 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3107 buffer.req.buf_lenh = 0;
3108 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3109 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3111 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3113 IXGBE_HI_COMMAND_TIMEOUT, false);
3119 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3120 * @hw: pointer to hardware structure
3122 * Determines physical layer capabilities of the current configuration.
3124 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3126 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3127 u16 ext_ability = 0;
3129 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3131 hw->phy.ops.identify(hw);
3133 switch (hw->phy.type) {
3134 case ixgbe_phy_x550em_kr:
3135 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3136 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3138 case ixgbe_phy_x550em_kx4:
3139 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3140 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3142 case ixgbe_phy_x550em_ext_t:
3143 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3144 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3146 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3147 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3148 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3149 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3155 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3156 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3158 return physical_layer;
3162 * ixgbe_get_bus_info_x550em - Set PCI bus info
3163 * @hw: pointer to hardware structure
3165 * Sets bus link width and speed to unknown because X550em is
3168 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3171 DEBUGFUNC("ixgbe_get_bus_info_x550em");
3173 hw->bus.width = ixgbe_bus_width_unknown;
3174 hw->bus.speed = ixgbe_bus_speed_unknown;
3176 hw->mac.ops.set_lan_id(hw);
3178 return IXGBE_SUCCESS;
3182 * ixgbe_disable_rx_x550 - Disable RX unit
3184 * Enables the Rx DMA unit for x550
3186 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3188 u32 rxctrl, pfdtxgswc;
3190 struct ixgbe_hic_disable_rxen fw_cmd;
3192 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3194 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3195 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3196 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3197 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3198 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3199 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3200 hw->mac.set_lben = true;
3202 hw->mac.set_lben = false;
3205 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3206 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3207 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3208 fw_cmd.port_number = (u8)hw->bus.lan_id;
3210 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3211 sizeof(struct ixgbe_hic_disable_rxen),
3212 IXGBE_HI_COMMAND_TIMEOUT, true);
3214 /* If we fail - disable RX using register write */
3216 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3217 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3218 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3219 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3226 * ixgbe_enter_lplu_x550em - Transition to low power states
3227 * @hw: pointer to hardware structure
3229 * Configures Low Power Link Up on transition to low power states
3230 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3231 * X557 PHY immediately prior to entering LPLU.
3233 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3235 u16 an_10g_cntl_reg, autoneg_reg, speed;
3237 ixgbe_link_speed lcd_speed;
3241 /* SW LPLU not required on later HW revisions. */
3242 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3243 (IXGBE_FUSES0_REV_MASK &
3244 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3245 return IXGBE_SUCCESS;
3247 /* If blocked by MNG FW, then don't restart AN */
3248 if (ixgbe_check_reset_blocked(hw))
3249 return IXGBE_SUCCESS;
3251 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3252 if (status != IXGBE_SUCCESS)
3255 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3257 if (status != IXGBE_SUCCESS)
3260 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3261 * disabled, then force link down by entering low power mode.
3263 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3264 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3265 return ixgbe_set_copper_phy_power(hw, FALSE);
3268 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3270 if (status != IXGBE_SUCCESS)
3273 /* If no valid LCD link speed, then force link down and exit. */
3274 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3275 return ixgbe_set_copper_phy_power(hw, FALSE);
3277 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3278 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3281 if (status != IXGBE_SUCCESS)
3284 /* If no link now, speed is invalid so take link down */
3285 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3286 if (status != IXGBE_SUCCESS)
3287 return ixgbe_set_copper_phy_power(hw, false);
3289 /* clear everything but the speed bits */
3290 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3292 /* If current speed is already LCD, then exit. */
3293 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3294 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3295 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3296 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3299 /* Clear AN completed indication */
3300 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3301 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3304 if (status != IXGBE_SUCCESS)
3307 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3308 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3311 if (status != IXGBE_SUCCESS)
3314 status = hw->phy.ops.read_reg(hw,
3315 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3316 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3319 if (status != IXGBE_SUCCESS)
3322 save_autoneg = hw->phy.autoneg_advertised;
3324 /* Setup link at least common link speed */
3325 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3327 /* restore autoneg from before setting lplu speed */
3328 hw->phy.autoneg_advertised = save_autoneg;
3334 * ixgbe_get_lcd_x550em - Determine lowest common denominator
3335 * @hw: pointer to hardware structure
3336 * @lcd_speed: pointer to lowest common link speed
3338 * Determine lowest common link speed with link partner.
3340 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3344 u16 word = hw->eeprom.ctrl_word_3;
3346 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3348 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3349 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3352 if (status != IXGBE_SUCCESS)
3355 /* If link partner advertised 1G, return 1G */
3356 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3357 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3361 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3362 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3363 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3366 /* Link partner not capable of lower speeds, return 10G */
3367 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3372 * ixgbe_setup_fc_X550em - Set up flow control
3373 * @hw: pointer to hardware structure
3375 * Called at init time to set up flow control.
3377 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3379 s32 ret_val = IXGBE_SUCCESS;
3380 u32 pause, asm_dir, reg_val;
3382 DEBUGFUNC("ixgbe_setup_fc_X550em");
3384 /* Validate the requested mode */
3385 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3386 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3387 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3388 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3392 /* 10gig parts do not have a word in the EEPROM to determine the
3393 * default flow control setting, so we explicitly set it to full.
3395 if (hw->fc.requested_mode == ixgbe_fc_default)
3396 hw->fc.requested_mode = ixgbe_fc_full;
3398 /* Determine PAUSE and ASM_DIR bits. */
3399 switch (hw->fc.requested_mode) {
3404 case ixgbe_fc_tx_pause:
3408 case ixgbe_fc_rx_pause:
3409 /* Rx Flow control is enabled and Tx Flow control is
3410 * disabled by software override. Since there really
3411 * isn't a way to advertise that we are capable of RX
3412 * Pause ONLY, we will advertise that we support both
3413 * symmetric and asymmetric Rx PAUSE, as such we fall
3414 * through to the fc_full statement. Later, we will
3415 * disable the adapter's ability to send PAUSE frames.
3422 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3423 "Flow control param set incorrectly\n");
3424 ret_val = IXGBE_ERR_CONFIG;
3428 switch (hw->device_id) {
3429 case IXGBE_DEV_ID_X550EM_X_KR:
3430 case IXGBE_DEV_ID_X550EM_A_KR:
3431 case IXGBE_DEV_ID_X550EM_A_KR_L:
3432 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3433 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3434 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3435 if (ret_val != IXGBE_SUCCESS)
3437 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3438 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3440 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3442 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3443 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3444 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3445 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3447 /* This device does not fully support AN. */
3448 hw->fc.disable_fc_autoneg = true;
3459 * ixgbe_set_mux - Set mux for port 1 access with CS4227
3460 * @hw: pointer to hardware structure
3461 * @state: set mux if 1, clear if 0
3463 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3467 if (!hw->bus.lan_id)
3469 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3471 esdp |= IXGBE_ESDP_SDP1;
3473 esdp &= ~IXGBE_ESDP_SDP1;
3474 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3475 IXGBE_WRITE_FLUSH(hw);
3479 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3480 * @hw: pointer to hardware structure
3481 * @mask: Mask to specify which semaphore to acquire
3483 * Acquires the SWFW semaphore and sets the I2C MUX
3485 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3489 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
3491 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3495 if (mask & IXGBE_GSSR_I2C_MASK)
3496 ixgbe_set_mux(hw, 1);
3498 return IXGBE_SUCCESS;
3502 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3503 * @hw: pointer to hardware structure
3504 * @mask: Mask to specify which semaphore to release
3506 * Releases the SWFW semaphore and sets the I2C MUX
3508 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3510 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3512 if (mask & IXGBE_GSSR_I2C_MASK)
3513 ixgbe_set_mux(hw, 0);
3515 ixgbe_release_swfw_sync_X540(hw, mask);
3519 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
3520 * @hw: pointer to hardware structure
3521 * @mask: Mask to specify which semaphore to acquire
3523 * Acquires the SWFW semaphore and get the shared phy token as needed
3525 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3527 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3528 int retries = FW_PHY_TOKEN_RETRIES;
3529 s32 status = IXGBE_SUCCESS;
3531 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
3535 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3538 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3540 status = ixgbe_get_phy_token(hw);
3541 if (status != IXGBE_ERR_TOKEN_RETRY)
3544 ixgbe_release_swfw_sync_X540(hw, hmask);
3545 msec_delay(FW_PHY_TOKEN_DELAY);
3552 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
3553 * @hw: pointer to hardware structure
3554 * @mask: Mask to specify which semaphore to release
3556 * Releases the SWFW semaphore and puts the shared phy token as needed
3558 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3560 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3562 DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
3564 if (mask & IXGBE_GSSR_TOKEN_SM)
3565 ixgbe_put_phy_token(hw);
3568 ixgbe_release_swfw_sync_X540(hw, hmask);
3572 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
3573 * @hw: pointer to hardware structure
3575 * Handle external Base T PHY interrupt. If high temperature
3576 * failure alarm then return error, else if link status change
3577 * then setup internal/external PHY link
3579 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
3580 * failure alarm, else return PHY access status.
3582 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
3587 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
3589 if (status != IXGBE_SUCCESS)
3593 return ixgbe_setup_internal_phy(hw);
3595 return IXGBE_SUCCESS;
3599 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
3600 * @hw: pointer to hardware structure
3601 * @speed: new link speed
3602 * @autoneg_wait_to_complete: true when waiting for completion is needed
3604 * Setup internal/external PHY link speed based on link speed, then set
3605 * external PHY auto advertised link speed.
3607 * Returns error status for any failure
3609 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3610 ixgbe_link_speed speed,
3611 bool autoneg_wait_to_complete)
3614 ixgbe_link_speed force_speed;
3616 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3618 /* Setup internal/external PHY link speed to iXFI (10G), unless
3619 * only 1G is auto advertised then setup KX link.
3621 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3622 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3624 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3626 /* If internal link mode is XFI, then setup XFI internal link. */
3627 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3628 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3630 if (status != IXGBE_SUCCESS)
3634 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3638 * ixgbe_check_link_t_X550em - Determine link and speed status
3639 * @hw: pointer to hardware structure
3640 * @speed: pointer to link speed
3641 * @link_up: true when link is up
3642 * @link_up_wait_to_complete: bool used to wait for link up or not
3644 * Check that both the MAC and X557 external PHY have link.
3646 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3647 bool *link_up, bool link_up_wait_to_complete)
3652 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3653 return IXGBE_ERR_CONFIG;
3655 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3656 link_up_wait_to_complete);
3658 /* If check link fails or MAC link is not up, then return */
3659 if (status != IXGBE_SUCCESS || !(*link_up))
3662 /* MAC link is up, so check external PHY link.
3663 * Read this twice back to back to indicate current status.
3665 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3666 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3669 if (status != IXGBE_SUCCESS)
3672 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3673 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3676 if (status != IXGBE_SUCCESS)
3679 /* If external PHY link is not up, then indicate link not up */
3680 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3683 return IXGBE_SUCCESS;
3687 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3688 * @hw: pointer to hardware structure
3690 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3694 status = ixgbe_reset_phy_generic(hw);
3696 if (status != IXGBE_SUCCESS)
3699 /* Configure Link Status Alarm and Temperature Threshold interrupts */
3700 return ixgbe_enable_lasi_ext_t_x550em(hw);
3704 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
3705 * @hw: pointer to hardware structure
3706 * @led_idx: led number to turn on
3708 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3712 DEBUGFUNC("ixgbe_led_on_t_X550em");
3714 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3715 return IXGBE_ERR_PARAM;
3717 /* To turn on the LED, set mode to ON. */
3718 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3719 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3720 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3721 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3722 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3724 return IXGBE_SUCCESS;
3728 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3729 * @hw: pointer to hardware structure
3730 * @led_idx: led number to turn off
3732 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3736 DEBUGFUNC("ixgbe_led_off_t_X550em");
3738 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3739 return IXGBE_ERR_PARAM;
3741 /* To turn on the LED, set mode to ON. */
3742 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3743 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3744 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3745 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3746 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3748 return IXGBE_SUCCESS;