drivers/net/ixgbe/base/ixgbe_x550.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2020 Intel Corporation
   3  */
   4
   5 #include "ixgbe_x550.h"
   6 #include "ixgbe_x540.h"
   7 #include "ixgbe_type.h"
   8 #include "ixgbe_api.h"
   9 #include "ixgbe_common.h"
  10 #include "ixgbe_phy.h"
  11
  12 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  13 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  14 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  15 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
  16
  17 /**
  18  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  19  *  @hw: pointer to hardware structure
  20  *
  21  *  Initialize the function pointers and assign the MAC type for X550.
  22  *  Does not touch the hardware.
  23  **/
  24 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  25 {
  26         struct ixgbe_mac_info *mac = &hw->mac;
  27         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  28         s32 ret_val;
  29
  30         DEBUGFUNC("ixgbe_init_ops_X550");
  31
  32         ret_val = ixgbe_init_ops_X540(hw);
  33         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  34         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  35         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  36         mac->ops.setup_eee = NULL;
  37         mac->ops.set_source_address_pruning =
  38                         ixgbe_set_source_address_pruning_X550;
  39         mac->ops.set_ethertype_anti_spoofing =
  40                         ixgbe_set_ethertype_anti_spoofing_X550;
  41
  42         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  43         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  44         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  45         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  46         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  47         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  48         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  49         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  50         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  51
  52         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  53         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  54         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  55         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  56         mac->ops.fw_recovery_mode = ixgbe_fw_recovery_mode_X550;
  57         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  58         /* Manageability interface */
  59         mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
  60         switch (hw->device_id) {
  61         case IXGBE_DEV_ID_X550EM_X_1G_T:
  62                 hw->mac.ops.led_on = NULL;
  63                 hw->mac.ops.led_off = NULL;
  64                 break;
  65         case IXGBE_DEV_ID_X550EM_X_10G_T:
  66         case IXGBE_DEV_ID_X550EM_A_10G_T:
  67                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  68                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  69                 break;
  70         default:
  71                 break;
  72         }
  73         return ret_val;
  74 }
  75
  76 /**
  77  * ixgbe_read_cs4227 - Read CS4227 register
  78  * @hw: pointer to hardware structure
  79  * @reg: register number to write
  80  * @value: pointer to receive value read
  81  *
  82  * Returns status code
  83  **/
  84 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  85 {
  86         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
  87 }
  88
  89 /**
  90  * ixgbe_write_cs4227 - Write CS4227 register
  91  * @hw: pointer to hardware structure
  92  * @reg: register number to write
  93  * @value: value to write to register
  94  *
  95  * Returns status code
  96  **/
  97 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
  98 {
  99         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 100 }
 101
 102 /**
 103  * ixgbe_read_pe - Read register from port expander
 104  * @hw: pointer to hardware structure
 105  * @reg: register number to read
 106  * @value: pointer to receive read value
 107  *
 108  * Returns status code
 109  **/
 110 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 111 {
 112         s32 status;
 113
 114         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 115         if (status != IXGBE_SUCCESS)
 116                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 117                               "port expander access failed with %d\n", status);
 118         return status;
 119 }
 120
 121 /**
 122  * ixgbe_write_pe - Write register to port expander
 123  * @hw: pointer to hardware structure
 124  * @reg: register number to write
 125  * @value: value to write
 126  *
 127  * Returns status code
 128  **/
 129 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 130 {
 131         s32 status;
 132
 133         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 134         if (status != IXGBE_SUCCESS)
 135                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 136                               "port expander access failed with %d\n", status);
 137         return status;
 138 }
 139
 140 /**
 141  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 142  * @hw: pointer to hardware structure
 143  *
 144  * This function assumes that the caller has acquired the proper semaphore.
 145  * Returns error code
 146  **/
 147 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 148 {
 149         s32 status;
 150         u32 retry;
 151         u16 value;
 152         u8 reg;
 153
 154         /* Trigger hard reset. */
 155         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 156         if (status != IXGBE_SUCCESS)
 157                 return status;
 158         reg |= IXGBE_PE_BIT1;
 159         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 160         if (status != IXGBE_SUCCESS)
 161                 return status;
 162
 163         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 164         if (status != IXGBE_SUCCESS)
 165                 return status;
 166         reg &= ~IXGBE_PE_BIT1;
 167         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 168         if (status != IXGBE_SUCCESS)
 169                 return status;
 170
 171         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 172         if (status != IXGBE_SUCCESS)
 173                 return status;
 174         reg &= ~IXGBE_PE_BIT1;
 175         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 176         if (status != IXGBE_SUCCESS)
 177                 return status;
 178
 179         usec_delay(IXGBE_CS4227_RESET_HOLD);
 180
 181         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 182         if (status != IXGBE_SUCCESS)
 183                 return status;
 184         reg |= IXGBE_PE_BIT1;
 185         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 186         if (status != IXGBE_SUCCESS)
 187                 return status;
 188
 189         /* Wait for the reset to complete. */
 190         msec_delay(IXGBE_CS4227_RESET_DELAY);
 191         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 192                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 193                                            &value);
 194                 if (status == IXGBE_SUCCESS &&
 195                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 196                         break;
 197                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 198         }
 199         if (retry == IXGBE_CS4227_RETRIES) {
 200                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 201                         "CS4227 reset did not complete.");
 202                 return IXGBE_ERR_PHY;
 203         }
 204
 205         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 206         if (status != IXGBE_SUCCESS ||
 207             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 208                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 209                         "CS4227 EEPROM did not load successfully.");
 210                 return IXGBE_ERR_PHY;
 211         }
 212
 213         return IXGBE_SUCCESS;
 214 }
 215
 216 /**
 217  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 218  * @hw: pointer to hardware structure
 219  **/
 220 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 221 {
 222         s32 status = IXGBE_SUCCESS;
 223         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 224         u16 value = 0;
 225         u8 retry;
 226
 227         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 228                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 229                 if (status != IXGBE_SUCCESS) {
 230                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 231                                 "semaphore failed with %d", status);
 232                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 233                         continue;
 234                 }
 235
 236                 /* Get status of reset flow. */
 237                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 238
 239                 if (status == IXGBE_SUCCESS &&
 240                     value == IXGBE_CS4227_RESET_COMPLETE)
 241                         goto out;
 242
 243                 if (status != IXGBE_SUCCESS ||
 244                     value != IXGBE_CS4227_RESET_PENDING)
 245                         break;
 246
 247                 /* Reset is pending. Wait and check again. */
 248                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 249                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 250         }
 251
 252         /* If still pending, assume other instance failed. */
 253         if (retry == IXGBE_CS4227_RETRIES) {
 254                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 255                 if (status != IXGBE_SUCCESS) {
 256                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 257                                       "semaphore failed with %d", status);
 258                         return;
 259                 }
 260         }
 261
 262         /* Reset the CS4227. */
 263         status = ixgbe_reset_cs4227(hw);
 264         if (status != IXGBE_SUCCESS) {
 265                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 266                         "CS4227 reset failed: %d", status);
 267                 goto out;
 268         }
 269
 270         /* Reset takes so long, temporarily release semaphore in case the
 271          * other driver instance is waiting for the reset indication.
 272          */
 273         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 274                            IXGBE_CS4227_RESET_PENDING);
 275         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 276         msec_delay(10);
 277         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 278         if (status != IXGBE_SUCCESS) {
 279                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 280                         "semaphore failed with %d", status);
 281                 return;
 282         }
 283
 284         /* Record completion for next time. */
 285         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 286                 IXGBE_CS4227_RESET_COMPLETE);
 287
 288 out:
 289         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 290         msec_delay(hw->eeprom.semaphore_delay);
 291 }
 292
 293 /**
 294  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 295  * @hw: pointer to hardware structure
 296  **/
 297 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 298 {
 299         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 300
 301         if (hw->bus.lan_id) {
 302                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 303                 esdp |= IXGBE_ESDP_SDP1_DIR;
 304         }
 305         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 306         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 307         IXGBE_WRITE_FLUSH(hw);
 308 }
 309
 310 /**
 311  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 312  * @hw: pointer to hardware structure
 313  *
 314  * Returns error code
 315  */
 316 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 317 {
 318         hw->mac.ops.set_lan_id(hw);
 319
 320         ixgbe_read_mng_if_sel_x550em(hw);
 321
 322         switch (hw->device_id) {
 323         case IXGBE_DEV_ID_X550EM_A_SFP:
 324                 return ixgbe_identify_sfp_module_X550em(hw);
 325         case IXGBE_DEV_ID_X550EM_X_SFP:
 326                 /* set up for CS4227 usage */
 327                 ixgbe_setup_mux_ctl(hw);
 328                 ixgbe_check_cs4227(hw);
 329                 /* Fallthrough */
 330
 331         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 332                 return ixgbe_identify_sfp_module_X550em(hw);
 333                 break;
 334         case IXGBE_DEV_ID_X550EM_X_KX4:
 335                 hw->phy.type = ixgbe_phy_x550em_kx4;
 336                 break;
 337         case IXGBE_DEV_ID_X550EM_X_XFI:
 338                 hw->phy.type = ixgbe_phy_x550em_xfi;
 339                 break;
 340         case IXGBE_DEV_ID_X550EM_X_KR:
 341         case IXGBE_DEV_ID_X550EM_A_KR:
 342         case IXGBE_DEV_ID_X550EM_A_KR_L:
 343                 hw->phy.type = ixgbe_phy_x550em_kr;
 344                 break;
 345         case IXGBE_DEV_ID_X550EM_A_10G_T:
 346         case IXGBE_DEV_ID_X550EM_X_10G_T:
 347                 return ixgbe_identify_phy_generic(hw);
 348         case IXGBE_DEV_ID_X550EM_X_1G_T:
 349                 hw->phy.type = ixgbe_phy_ext_1g_t;
 350                 break;
 351         case IXGBE_DEV_ID_X550EM_A_1G_T:
 352         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 353                 hw->phy.type = ixgbe_phy_fw;
 354                 if (hw->bus.lan_id)
 355                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 356                 else
 357                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 358                 break;
 359         default:
 360                 break;
 361         }
 362         return IXGBE_SUCCESS;
 363 }
 364
 365 /**
 366  * ixgbe_fw_phy_activity - Perform an activity on a PHY
 367  * @hw: pointer to hardware structure
 368  * @activity: activity to perform
 369  * @data: Pointer to 4 32-bit words of data
 370  */
 371 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
 372                           u32 (*data)[FW_PHY_ACT_DATA_COUNT])
 373 {
 374         union {
 375                 struct ixgbe_hic_phy_activity_req cmd;
 376                 struct ixgbe_hic_phy_activity_resp rsp;
 377         } hic;
 378         u16 retries = FW_PHY_ACT_RETRIES;
 379         s32 rc;
 380         u16 i;
 381
 382         do {
 383                 memset(&hic, 0, sizeof(hic));
 384                 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
 385                 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
 386                 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 387                 hic.cmd.port_number = hw->bus.lan_id;
 388                 hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity);
 389                 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 390                         hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]);
 391
 392                 rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
 393                                                   sizeof(hic.cmd),
 394                                                   IXGBE_HI_COMMAND_TIMEOUT,
 395                                                   true);
 396                 if (rc != IXGBE_SUCCESS)
 397                         return rc;
 398                 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
 399                     FW_CEM_RESP_STATUS_SUCCESS) {
 400                         for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 401                                 (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]);
 402                         return IXGBE_SUCCESS;
 403                 }
 404                 usec_delay(20);
 405                 --retries;
 406         } while (retries > 0);
 407
 408         return IXGBE_ERR_HOST_INTERFACE_COMMAND;
 409 }
 410
 411 static const struct {
 412         u16 fw_speed;
 413         ixgbe_link_speed phy_speed;
 414 } ixgbe_fw_map[] = {
 415         { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
 416         { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
 417         { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
 418         { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
 419         { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
 420         { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
 421 };
 422
 423 /**
 424  * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
 425  * @hw: pointer to hardware structure
 426  *
 427  * Returns error code
 428  */
 429 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
 430 {
 431         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
 432         u16 phy_speeds;
 433         u16 phy_id_lo;
 434         s32 rc;
 435         u16 i;
 436
 437         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
 438         if (rc)
 439                 return rc;
 440
 441         hw->phy.speeds_supported = 0;
 442         phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
 443         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 444                 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
 445                         hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
 446         }
 447         if (!hw->phy.autoneg_advertised)
 448                 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
 449
 450         hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
 451         phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
 452         hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
 453         hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
 454         if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
 455                 return IXGBE_ERR_PHY_ADDR_INVALID;
 456         return IXGBE_SUCCESS;
 457 }
 458
 459 /**
 460  * ixgbe_identify_phy_fw - Get PHY type based on firmware command
 461  * @hw: pointer to hardware structure
 462  *
 463  * Returns error code
 464  */
 465 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
 466 {
 467         if (hw->bus.lan_id)
 468                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 469         else
 470                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 471
 472         hw->phy.type = ixgbe_phy_fw;
 473         hw->phy.ops.read_reg = NULL;
 474         hw->phy.ops.write_reg = NULL;
 475         return ixgbe_get_phy_id_fw(hw);
 476 }
 477
 478 /**
 479  * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
 480  * @hw: pointer to hardware structure
 481  *
 482  * Returns error code
 483  */
 484 s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
 485 {
 486         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 487
 488         setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
 489         return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
 490 }
 491
 492 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 493                                      u32 device_type, u16 *phy_data)
 494 {
 495         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 496         return IXGBE_NOT_IMPLEMENTED;
 497 }
 498
 499 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 500                                       u32 device_type, u16 phy_data)
 501 {
 502         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 503         return IXGBE_NOT_IMPLEMENTED;
 504 }
 505
 506 /**
 507  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 508  * @hw: pointer to the hardware structure
 509  * @addr: I2C bus address to read from
 510  * @reg: I2C device register to read from
 511  * @val: pointer to location to receive read value
 512  *
 513  * Returns an error code on error.
 514  **/
 515 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 516                                            u16 reg, u16 *val)
 517 {
 518         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 519 }
 520
 521 /**
 522  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 523  * @hw: pointer to the hardware structure
 524  * @addr: I2C bus address to read from
 525  * @reg: I2C device register to read from
 526  * @val: pointer to location to receive read value
 527  *
 528  * Returns an error code on error.
 529  **/
 530 STATIC s32
 531 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 532                                          u16 reg, u16 *val)
 533 {
 534         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 535 }
 536
 537 /**
 538  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 539  * @hw: pointer to the hardware structure
 540  * @addr: I2C bus address to write to
 541  * @reg: I2C device register to write to
 542  * @val: value to write
 543  *
 544  * Returns an error code on error.
 545  **/
 546 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 547                                             u8 addr, u16 reg, u16 val)
 548 {
 549         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 550 }
 551
 552 /**
 553  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 554  * @hw: pointer to the hardware structure
 555  * @addr: I2C bus address to write to
 556  * @reg: I2C device register to write to
 557  * @val: value to write
 558  *
 559  * Returns an error code on error.
 560  **/
 561 STATIC s32
 562 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 563                                           u8 addr, u16 reg, u16 val)
 564 {
 565         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 566 }
 567
 568 /**
 569 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 570 *  @hw: pointer to hardware structure
 571 *
 572 *  Initialize the function pointers and for MAC type X550EM.
 573 *  Does not touch the hardware.
 574 **/
 575 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 576 {
 577         struct ixgbe_mac_info *mac = &hw->mac;
 578         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 579         struct ixgbe_phy_info *phy = &hw->phy;
 580         s32 ret_val;
 581
 582         DEBUGFUNC("ixgbe_init_ops_X550EM");
 583
 584         /* Similar to X550 so start there. */
 585         ret_val = ixgbe_init_ops_X550(hw);
 586
 587         /* Since this function eventually calls
 588          * ixgbe_init_ops_540 by design, we are setting
 589          * the pointers to NULL explicitly here to overwrite
 590          * the values being set in the x540 function.
 591          */
 592         /* Thermal sensor not supported in x550EM */
 593         mac->ops.get_thermal_sensor_data = NULL;
 594         mac->ops.init_thermal_sensor_thresh = NULL;
 595         mac->thermal_sensor_enabled = false;
 596
 597         /* FCOE not supported in x550EM */
 598         mac->ops.get_san_mac_addr = NULL;
 599         mac->ops.set_san_mac_addr = NULL;
 600         mac->ops.get_wwn_prefix = NULL;
 601         mac->ops.get_fcoe_boot_status = NULL;
 602
 603         /* IPsec not supported in x550EM */
 604         mac->ops.disable_sec_rx_path = NULL;
 605         mac->ops.enable_sec_rx_path = NULL;
 606
 607         /* AUTOC register is not present in x550EM. */
 608         mac->ops.prot_autoc_read = NULL;
 609         mac->ops.prot_autoc_write = NULL;
 610
 611         /* X550EM bus type is internal*/
 612         hw->bus.type = ixgbe_bus_type_internal;
 613         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 614
 615
 616         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 617         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 618         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 619         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 620         mac->ops.get_supported_physical_layer =
 621                                     ixgbe_get_supported_physical_layer_X550em;
 622
 623         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 624                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 625         else
 626                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 627
 628         /* PHY */
 629         phy->ops.init = ixgbe_init_phy_ops_X550em;
 630         switch (hw->device_id) {
 631         case IXGBE_DEV_ID_X550EM_A_1G_T:
 632         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 633                 mac->ops.setup_fc = NULL;
 634                 phy->ops.identify = ixgbe_identify_phy_fw;
 635                 phy->ops.set_phy_power = NULL;
 636                 phy->ops.get_firmware_version = NULL;
 637                 break;
 638         case IXGBE_DEV_ID_X550EM_X_1G_T:
 639                 mac->ops.setup_fc = NULL;
 640                 phy->ops.identify = ixgbe_identify_phy_x550em;
 641                 phy->ops.set_phy_power = NULL;
 642                 break;
 643         default:
 644                 phy->ops.identify = ixgbe_identify_phy_x550em;
 645         }
 646
 647         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 648                 phy->ops.set_phy_power = NULL;
 649
 650
 651         /* EEPROM */
 652         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 653         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 654         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 655         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 656         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 657         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 658         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 659         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 660
 661         return ret_val;
 662 }
 663
 664 /**
 665  * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
 666  * @hw: pointer to hardware structure
 667  */
 668 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
 669 {
 670         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 671         s32 rc;
 672         u16 i;
 673
 674         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
 675                 return 0;
 676
 677         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 678                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
 679                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
 680                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
 681         }
 682
 683         switch (hw->fc.requested_mode) {
 684         case ixgbe_fc_full:
 685                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
 686                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 687                 break;
 688         case ixgbe_fc_rx_pause:
 689                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
 690                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 691                 break;
 692         case ixgbe_fc_tx_pause:
 693                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
 694                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 695                 break;
 696         default:
 697                 break;
 698         }
 699
 700         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 701                 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
 702                         setup[0] |= ixgbe_fw_map[i].fw_speed;
 703         }
 704         setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
 705
 706         if (hw->phy.eee_speeds_advertised)
 707                 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
 708
 709         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
 710         if (rc)
 711                 return rc;
 712         if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
 713                 return IXGBE_ERR_OVERTEMP;
 714         return IXGBE_SUCCESS;
 715 }
 716
 717 /**
 718  * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs
 719  * @hw: pointer to hardware structure
 720  *
 721  *  Called at init time to set up flow control.
 722  */
 723 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
 724 {
 725         if (hw->fc.requested_mode == ixgbe_fc_default)
 726                 hw->fc.requested_mode = ixgbe_fc_full;
 727
 728         return ixgbe_setup_fw_link(hw);
 729 }
 730
 731 /**
 732  * ixgbe_setup_eee_fw - Enable/disable EEE support
 733  * @hw: pointer to the HW structure
 734  * @enable_eee: boolean flag to enable EEE
 735  *
 736  * Enable/disable EEE based on enable_eee flag.
 737  * This function controls EEE for firmware-based PHY implementations.
 738  */
 739 static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee)
 740 {
 741         if (!!hw->phy.eee_speeds_advertised == enable_eee)
 742                 return IXGBE_SUCCESS;
 743         if (enable_eee)
 744                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 745         else
 746                 hw->phy.eee_speeds_advertised = 0;
 747         return hw->phy.ops.setup_link(hw);
 748 }
 749
 750 /**
 751 *  ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
 752 *  @hw: pointer to hardware structure
 753 *
 754 *  Initialize the function pointers and for MAC type X550EM_a.
 755 *  Does not touch the hardware.
 756 **/
 757 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
 758 {
 759         struct ixgbe_mac_info *mac = &hw->mac;
 760         s32 ret_val;
 761
 762         DEBUGFUNC("ixgbe_init_ops_X550EM_a");
 763
 764         /* Start with generic X550EM init */
 765         ret_val = ixgbe_init_ops_X550EM(hw);
 766
 767         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
 768             hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
 769                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 770                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 771         } else {
 772                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 773                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 774         }
 775         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 776         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 777
 778         switch (mac->ops.get_media_type(hw)) {
 779         case ixgbe_media_type_fiber:
 780                 mac->ops.setup_fc = NULL;
 781                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
 782                 break;
 783         case ixgbe_media_type_backplane:
 784                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
 785                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
 786                 break;
 787         default:
 788                 break;
 789         }
 790
 791         switch (hw->device_id) {
 792         case IXGBE_DEV_ID_X550EM_A_1G_T:
 793         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 794                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
 795                 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
 796                 mac->ops.setup_eee = ixgbe_setup_eee_fw;
 797                 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
 798                                                IXGBE_LINK_SPEED_1GB_FULL;
 799                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 800                 break;
 801         default:
 802                 break;
 803         }
 804
 805         return ret_val;
 806 }
 807
 808 /**
 809 *  ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
 810 *  @hw: pointer to hardware structure
 811 *
 812 *  Initialize the function pointers and for MAC type X550EM_x.
 813 *  Does not touch the hardware.
 814 **/
 815 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
 816 {
 817         struct ixgbe_mac_info *mac = &hw->mac;
 818         struct ixgbe_link_info *link = &hw->link;
 819         s32 ret_val;
 820
 821         DEBUGFUNC("ixgbe_init_ops_X550EM_x");
 822
 823         /* Start with generic X550EM init */
 824         ret_val = ixgbe_init_ops_X550EM(hw);
 825
 826         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 827         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 828         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 829         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 830         link->ops.read_link = ixgbe_read_i2c_combined_generic;
 831         link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
 832         link->ops.write_link = ixgbe_write_i2c_combined_generic;
 833         link->ops.write_link_unlocked =
 834                                       ixgbe_write_i2c_combined_generic_unlocked;
 835         link->addr = IXGBE_CS4227;
 836
 837         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) {
 838                 mac->ops.setup_fc = NULL;
 839                 mac->ops.setup_eee = NULL;
 840                 mac->ops.init_led_link_act = NULL;
 841         }
 842
 843         return ret_val;
 844 }
 845
 846 /**
 847  *  ixgbe_dmac_config_X550
 848  *  @hw: pointer to hardware structure
 849  *
 850  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 851  *  When disabling dmac, dmac enable dmac bit is cleared.
 852  **/
 853 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 854 {
 855         u32 reg, high_pri_tc;
 856
 857         DEBUGFUNC("ixgbe_dmac_config_X550");
 858
 859         /* Disable DMA coalescing before configuring */
 860         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 861         reg &= ~IXGBE_DMACR_DMAC_EN;
 862         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 863
 864         /* Disable DMA Coalescing if the watchdog timer is 0 */
 865         if (!hw->mac.dmac_config.watchdog_timer)
 866                 goto out;
 867
 868         ixgbe_dmac_config_tcs_X550(hw);
 869
 870         /* Configure DMA Coalescing Control Register */
 871         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 872
 873         /* Set the watchdog timer in units of 40.96 usec */
 874         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 875         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 876
 877         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 878         /* If fcoe is enabled, set high priority traffic class */
 879         if (hw->mac.dmac_config.fcoe_en) {
 880                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 881                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 882                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 883         }
 884         reg |= IXGBE_DMACR_EN_MNG_IND;
 885
 886         /* Enable DMA coalescing after configuration */
 887         reg |= IXGBE_DMACR_DMAC_EN;
 888         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 889
 890 out:
 891         return IXGBE_SUCCESS;
 892 }
 893
 894 /**
 895  *  ixgbe_dmac_config_tcs_X550
 896  *  @hw: pointer to hardware structure
 897  *
 898  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 899  *  be cleared before configuring.
 900  **/
 901 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 902 {
 903         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 904
 905         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 906
 907         /* Configure DMA coalescing enabled */
 908         switch (hw->mac.dmac_config.link_speed) {
 909         case IXGBE_LINK_SPEED_10_FULL:
 910         case IXGBE_LINK_SPEED_100_FULL:
 911                 pb_headroom = IXGBE_DMACRXT_100M;
 912                 break;
 913         case IXGBE_LINK_SPEED_1GB_FULL:
 914                 pb_headroom = IXGBE_DMACRXT_1G;
 915                 break;
 916         default:
 917                 pb_headroom = IXGBE_DMACRXT_10G;
 918                 break;
 919         }
 920
 921         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 922                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 923
 924         /* Set the per Rx packet buffer receive threshold */
 925         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 926                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 927                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 928
 929                 if (tc < hw->mac.dmac_config.num_tcs) {
 930                         /* Get Rx PB size */
 931                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 932                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 933                                 IXGBE_RXPBSIZE_SHIFT;
 934
 935                         /* Calculate receive buffer threshold in kilobytes */
 936                         if (rx_pb_size > pb_headroom)
 937                                 rx_pb_size = rx_pb_size - pb_headroom;
 938                         else
 939                                 rx_pb_size = 0;
 940
 941                         /* Minimum of MFS shall be set for DMCTH */
 942                         reg |= (rx_pb_size > maxframe_size_kb) ?
 943                                 rx_pb_size : maxframe_size_kb;
 944                 }
 945                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 946         }
 947         return IXGBE_SUCCESS;
 948 }
 949
 950 /**
 951  *  ixgbe_dmac_update_tcs_X550
 952  *  @hw: pointer to hardware structure
 953  *
 954  *  Disables dmac, updates per TC settings, and then enables dmac.
 955  **/
 956 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 957 {
 958         u32 reg;
 959
 960         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 961
 962         /* Disable DMA coalescing before configuring */
 963         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 964         reg &= ~IXGBE_DMACR_DMAC_EN;
 965         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 966
 967         ixgbe_dmac_config_tcs_X550(hw);
 968
 969         /* Enable DMA coalescing after configuration */
 970         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 971         reg |= IXGBE_DMACR_DMAC_EN;
 972         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 973
 974         return IXGBE_SUCCESS;
 975 }
 976
 977 /**
 978  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 979  *  @hw: pointer to hardware structure
 980  *
 981  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 982  *  ixgbe_hw struct in order to set up EEPROM access.
 983  **/
 984 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 985 {
 986         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 987         u32 eec;
 988         u16 eeprom_size;
 989
 990         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 991
 992         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 993                 eeprom->semaphore_delay = 10;
 994                 eeprom->type = ixgbe_flash;
 995
 996                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 997                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 998                                     IXGBE_EEC_SIZE_SHIFT);
 999                 eeprom->word_size = 1 << (eeprom_size +
1000                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
1001
1002                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
1003                           eeprom->type, eeprom->word_size);
1004         }
1005
1006         return IXGBE_SUCCESS;
1007 }
1008
1009 /**
1010  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1011  * @hw: pointer to hardware structure
1012  * @enable: enable or disable source address pruning
1013  * @pool: Rx pool to set source address pruning for
1014  **/
1015 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1016                                            unsigned int pool)
1017 {
1018         u64 pfflp;
1019
1020         /* max rx pool is 63 */
1021         if (pool > 63)
1022                 return;
1023
1024         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1025         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1026
1027         if (enable)
1028                 pfflp |= (1ULL << pool);
1029         else
1030                 pfflp &= ~(1ULL << pool);
1031
1032         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1033         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1034 }
1035
1036 /**
1037  *  ixgbe_set_ethertype_anti_spoofing_X550 - Configure Ethertype anti-spoofing
1038  *  @hw: pointer to hardware structure
1039  *  @enable: enable or disable switch for Ethertype anti-spoofing
1040  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1041  *
1042  **/
1043 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1044                 bool enable, int vf)
1045 {
1046         int vf_target_reg = vf >> 3;
1047         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1048         u32 pfvfspoof;
1049
1050         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1051
1052         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1053         if (enable)
1054                 pfvfspoof |= (1 << vf_target_shift);
1055         else
1056                 pfvfspoof &= ~(1 << vf_target_shift);
1057
1058         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1059 }
1060
1061 /**
1062  * ixgbe_iosf_wait - Wait for IOSF command completion
1063  * @hw: pointer to hardware structure
1064  * @ctrl: pointer to location to receive final IOSF control value
1065  *
1066  * Returns failing status on timeout
1067  *
1068  * Note: ctrl can be NULL if the IOSF control register value is not needed
1069  **/
1070 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1071 {
1072         u32 i, command = 0;
1073
1074         /* Check every 10 usec to see if the address cycle completed.
1075          * The SB IOSF BUSY bit will clear when the operation is
1076          * complete
1077          */
1078         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1079                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1080                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1081                         break;
1082                 usec_delay(10);
1083         }
1084         if (ctrl)
1085                 *ctrl = command;
1086         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1087                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1088                 return IXGBE_ERR_PHY;
1089         }
1090
1091         return IXGBE_SUCCESS;
1092 }
1093
1094 /**
1095  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1096  *  of the IOSF device
1097  *  @hw: pointer to hardware structure
1098  *  @reg_addr: 32 bit PHY register to write
1099  *  @device_type: 3 bit device type
1100  *  @data: Data to write to the register
1101  **/
1102 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1103                             u32 device_type, u32 data)
1104 {
1105         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1106         u32 command, error;
1107         s32 ret;
1108
1109         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1110         if (ret != IXGBE_SUCCESS)
1111                 return ret;
1112
1113         ret = ixgbe_iosf_wait(hw, NULL);
1114         if (ret != IXGBE_SUCCESS)
1115                 goto out;
1116
1117         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1118                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1119
1120         /* Write IOSF control register */
1121         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1122
1123         /* Write IOSF data register */
1124         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1125
1126         ret = ixgbe_iosf_wait(hw, &command);
1127
1128         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1129                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1130                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1131                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1132                               "Failed to write, error %x\n", error);
1133                 ret = IXGBE_ERR_PHY;
1134         }
1135
1136 out:
1137         ixgbe_release_swfw_semaphore(hw, gssr);
1138         return ret;
1139 }
1140
1141 /**
1142  *  ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1143  *  @hw: pointer to hardware structure
1144  *  @reg_addr: 32 bit PHY register to write
1145  *  @device_type: 3 bit device type
1146  *  @data: Pointer to read data from the register
1147  **/
1148 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1149                            u32 device_type, u32 *data)
1150 {
1151         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1152         u32 command, error;
1153         s32 ret;
1154
1155         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1156         if (ret != IXGBE_SUCCESS)
1157                 return ret;
1158
1159         ret = ixgbe_iosf_wait(hw, NULL);
1160         if (ret != IXGBE_SUCCESS)
1161                 goto out;
1162
1163         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1164                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1165
1166         /* Write IOSF control register */
1167         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1168
1169         ret = ixgbe_iosf_wait(hw, &command);
1170
1171         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1172                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1173                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1174                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1175                                 "Failed to read, error %x\n", error);
1176                 ret = IXGBE_ERR_PHY;
1177         }
1178
1179         if (ret == IXGBE_SUCCESS)
1180                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1181
1182 out:
1183         ixgbe_release_swfw_semaphore(hw, gssr);
1184         return ret;
1185 }
1186
1187 /**
1188  * ixgbe_get_phy_token - Get the token for shared phy access
1189  * @hw: Pointer to hardware structure
1190  */
1191
1192 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1193 {
1194         struct ixgbe_hic_phy_token_req token_cmd;
1195         s32 status;
1196
1197         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1198         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1199         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1200         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1201         token_cmd.port_number = hw->bus.lan_id;
1202         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1203         token_cmd.pad = 0;
1204         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1205                                               sizeof(token_cmd),
1206                                               IXGBE_HI_COMMAND_TIMEOUT,
1207                                               true);
1208         if (status) {
1209                 DEBUGOUT1("Issuing host interface command failed with Status = %d\n",
1210                           status);
1211                 return status;
1212         }
1213         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1214                 return IXGBE_SUCCESS;
1215         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) {
1216                 DEBUGOUT1("Host interface command returned 0x%08x , returning IXGBE_ERR_FW_RESP_INVALID\n",
1217                           token_cmd.hdr.cmd_or_resp.ret_status);
1218                 return IXGBE_ERR_FW_RESP_INVALID;
1219         }
1220
1221         DEBUGOUT("Returning  IXGBE_ERR_TOKEN_RETRY\n");
1222         return IXGBE_ERR_TOKEN_RETRY;
1223 }
1224
1225 /**
1226  * ixgbe_put_phy_token - Put the token for shared phy access
1227  * @hw: Pointer to hardware structure
1228  */
1229
1230 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1231 {
1232         struct ixgbe_hic_phy_token_req token_cmd;
1233         s32 status;
1234
1235         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1236         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1237         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1238         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1239         token_cmd.port_number = hw->bus.lan_id;
1240         token_cmd.command_type = FW_PHY_TOKEN_REL;
1241         token_cmd.pad = 0;
1242         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1243                                               sizeof(token_cmd),
1244                                               IXGBE_HI_COMMAND_TIMEOUT,
1245                                               true);
1246         if (status)
1247                 return status;
1248         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1249                 return IXGBE_SUCCESS;
1250
1251         DEBUGOUT("Put PHY Token host interface command failed");
1252         return IXGBE_ERR_FW_RESP_INVALID;
1253 }
1254
1255 /**
1256  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1257  *  of the IOSF device
1258  *  @hw: pointer to hardware structure
1259  *  @reg_addr: 32 bit PHY register to write
1260  *  @device_type: 3 bit device type
1261  *  @data: Data to write to the register
1262  **/
1263 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1264                                   u32 device_type, u32 data)
1265 {
1266         struct ixgbe_hic_internal_phy_req write_cmd;
1267         s32 status;
1268         UNREFERENCED_1PARAMETER(device_type);
1269
1270         memset(&write_cmd, 0, sizeof(write_cmd));
1271         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1272         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1273         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1274         write_cmd.port_number = hw->bus.lan_id;
1275         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1276         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1277         write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1278
1279         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1280                                               sizeof(write_cmd),
1281                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1282
1283         return status;
1284 }
1285
1286 /**
1287  *  ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1288  *  @hw: pointer to hardware structure
1289  *  @reg_addr: 32 bit PHY register to write
1290  *  @device_type: 3 bit device type
1291  *  @data: Pointer to read data from the register
1292  **/
1293 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1294                                  u32 device_type, u32 *data)
1295 {
1296         union {
1297                 struct ixgbe_hic_internal_phy_req cmd;
1298                 struct ixgbe_hic_internal_phy_resp rsp;
1299         } hic;
1300         s32 status;
1301         UNREFERENCED_1PARAMETER(device_type);
1302
1303         memset(&hic, 0, sizeof(hic));
1304         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1305         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1306         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1307         hic.cmd.port_number = hw->bus.lan_id;
1308         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1309         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1310
1311         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1312                                               sizeof(hic.cmd),
1313                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1314
1315         /* Extract the register value from the response. */
1316         *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1317
1318         return status;
1319 }
1320
1321 /**
1322  *  ixgbe_disable_mdd_X550
1323  *  @hw: pointer to hardware structure
1324  *
1325  *  Disable malicious driver detection
1326  **/
1327 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1328 {
1329         u32 reg;
1330
1331         DEBUGFUNC("ixgbe_disable_mdd_X550");
1332
1333         /* Disable MDD for TX DMA and interrupt */
1334         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1335         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1336         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1337
1338         /* Disable MDD for RX and interrupt */
1339         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1340         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1341         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1342 }
1343
1344 /**
1345  *  ixgbe_enable_mdd_X550
1346  *  @hw: pointer to hardware structure
1347  *
1348  *  Enable malicious driver detection
1349  **/
1350 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1351 {
1352         u32 reg;
1353
1354         DEBUGFUNC("ixgbe_enable_mdd_X550");
1355
1356         /* Enable MDD for TX DMA and interrupt */
1357         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1358         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1359         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1360
1361         /* Enable MDD for RX and interrupt */
1362         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1363         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1364         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1365 }
1366
1367 /**
1368  *  ixgbe_restore_mdd_vf_X550
1369  *  @hw: pointer to hardware structure
1370  *  @vf: vf index
1371  *
1372  *  Restore VF that was disabled during malicious driver detection event
1373  **/
1374 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1375 {
1376         u32 idx, reg, num_qs, start_q, bitmask;
1377
1378         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1379
1380         /* Map VF to queues */
1381         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1382         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1383         case IXGBE_MRQC_VMDQRT8TCEN:
1384                 num_qs = 8;  /* 16 VFs / pools */
1385                 bitmask = 0x000000FF;
1386                 break;
1387         case IXGBE_MRQC_VMDQRSS32EN:
1388         case IXGBE_MRQC_VMDQRT4TCEN:
1389                 num_qs = 4;  /* 32 VFs / pools */
1390                 bitmask = 0x0000000F;
1391                 break;
1392         default:            /* 64 VFs / pools */
1393                 num_qs = 2;
1394                 bitmask = 0x00000003;
1395                 break;
1396         }
1397         start_q = vf * num_qs;
1398
1399         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1400         idx = start_q / 32;
1401         reg = 0;
1402         reg |= (bitmask << (start_q % 32));
1403         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1404         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1405 }
1406
1407 /**
1408  *  ixgbe_mdd_event_X550
1409  *  @hw: pointer to hardware structure
1410  *  @vf_bitmap: vf bitmap of malicious vfs
1411  *
1412  *  Handle malicious driver detection event.
1413  **/
1414 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1415 {
1416         u32 wqbr;
1417         u32 i, j, reg, q, shift, vf, idx;
1418
1419         DEBUGFUNC("ixgbe_mdd_event_X550");
1420
1421         /* figure out pool size for mapping to vf's */
1422         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1423         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1424         case IXGBE_MRQC_VMDQRT8TCEN:
1425                 shift = 3;  /* 16 VFs / pools */
1426                 break;
1427         case IXGBE_MRQC_VMDQRSS32EN:
1428         case IXGBE_MRQC_VMDQRT4TCEN:
1429                 shift = 2;  /* 32 VFs / pools */
1430                 break;
1431         default:
1432                 shift = 1;  /* 64 VFs / pools */
1433                 break;
1434         }
1435
1436         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1437         for (i = 0; i < 4; i++) {
1438                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1439                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1440
1441                 if (!wqbr)
1442                         continue;
1443
1444                 /* Get malicious queue */
1445                 for (j = 0; j < 32 && wqbr; j++) {
1446
1447                         if (!(wqbr & (1 << j)))
1448                                 continue;
1449
1450                         /* Get queue from bitmask */
1451                         q = j + (i * 32);
1452
1453                         /* Map queue to vf */
1454                         vf = (q >> shift);
1455
1456                         /* Set vf bit in vf_bitmap */
1457                         idx = vf / 32;
1458                         vf_bitmap[idx] |= (1 << (vf % 32));
1459                         wqbr &= ~(1 << j);
1460                 }
1461         }
1462 }
1463
1464 /**
1465  *  ixgbe_get_media_type_X550em - Get media type
1466  *  @hw: pointer to hardware structure
1467  *
1468  *  Returns the media type (fiber, copper, backplane)
1469  */
1470 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1471 {
1472         enum ixgbe_media_type media_type;
1473
1474         DEBUGFUNC("ixgbe_get_media_type_X550em");
1475
1476         /* Detect if there is a copper PHY attached. */
1477         switch (hw->device_id) {
1478         case IXGBE_DEV_ID_X550EM_X_KR:
1479         case IXGBE_DEV_ID_X550EM_X_KX4:
1480         case IXGBE_DEV_ID_X550EM_X_XFI:
1481         case IXGBE_DEV_ID_X550EM_A_KR:
1482         case IXGBE_DEV_ID_X550EM_A_KR_L:
1483                 media_type = ixgbe_media_type_backplane;
1484                 break;
1485         case IXGBE_DEV_ID_X550EM_X_SFP:
1486         case IXGBE_DEV_ID_X550EM_A_SFP:
1487         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1488         case IXGBE_DEV_ID_X550EM_A_QSFP:
1489         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1490                 media_type = ixgbe_media_type_fiber;
1491                 break;
1492         case IXGBE_DEV_ID_X550EM_X_1G_T:
1493         case IXGBE_DEV_ID_X550EM_X_10G_T:
1494         case IXGBE_DEV_ID_X550EM_A_10G_T:
1495                 media_type = ixgbe_media_type_copper;
1496                 break;
1497         case IXGBE_DEV_ID_X550EM_A_SGMII:
1498         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1499                 media_type = ixgbe_media_type_backplane;
1500                 hw->phy.type = ixgbe_phy_sgmii;
1501                 break;
1502         case IXGBE_DEV_ID_X550EM_A_1G_T:
1503         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1504                 media_type = ixgbe_media_type_copper;
1505                 break;
1506         default:
1507                 media_type = ixgbe_media_type_unknown;
1508                 break;
1509         }
1510         return media_type;
1511 }
1512
1513 /**
1514  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1515  *  @hw: pointer to hardware structure
1516  *  @linear: true if SFP module is linear
1517  */
1518 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1519 {
1520         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1521
1522         switch (hw->phy.sfp_type) {
1523         case ixgbe_sfp_type_not_present:
1524                 return IXGBE_ERR_SFP_NOT_PRESENT;
1525         case ixgbe_sfp_type_da_cu_core0:
1526         case ixgbe_sfp_type_da_cu_core1:
1527                 *linear = true;
1528                 break;
1529         case ixgbe_sfp_type_srlr_core0:
1530         case ixgbe_sfp_type_srlr_core1:
1531         case ixgbe_sfp_type_da_act_lmt_core0:
1532         case ixgbe_sfp_type_da_act_lmt_core1:
1533         case ixgbe_sfp_type_1g_sx_core0:
1534         case ixgbe_sfp_type_1g_sx_core1:
1535         case ixgbe_sfp_type_1g_lx_core0:
1536         case ixgbe_sfp_type_1g_lx_core1:
1537         case ixgbe_sfp_type_1g_lha_core0:
1538         case ixgbe_sfp_type_1g_lha_core1:
1539                 *linear = false;
1540                 break;
1541         case ixgbe_sfp_type_unknown:
1542         case ixgbe_sfp_type_1g_cu_core0:
1543         case ixgbe_sfp_type_1g_cu_core1:
1544         default:
1545                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1546         }
1547
1548         return IXGBE_SUCCESS;
1549 }
1550
1551 /**
1552  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1553  *  @hw: pointer to hardware structure
1554  *
1555  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1556  **/
1557 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1558 {
1559         s32 status;
1560         bool linear;
1561
1562         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1563
1564         status = ixgbe_identify_module_generic(hw);
1565
1566         if (status != IXGBE_SUCCESS)
1567                 return status;
1568
1569         /* Check if SFP module is supported */
1570         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1571
1572         return status;
1573 }
1574
1575 /**
1576  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1577  *  @hw: pointer to hardware structure
1578  */
1579 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1580 {
1581         s32 status;
1582         bool linear;
1583
1584         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1585
1586         /* Check if SFP module is supported */
1587         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1588
1589         if (status != IXGBE_SUCCESS)
1590                 return status;
1591
1592         ixgbe_init_mac_link_ops_X550em(hw);
1593         hw->phy.ops.reset = NULL;
1594
1595         return IXGBE_SUCCESS;
1596 }
1597
1598 /**
1599 *  ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1600 *  internal PHY
1601 *  @hw: pointer to hardware structure
1602 **/
1603 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1604 {
1605         s32 status;
1606         u32 link_ctrl;
1607
1608         /* Restart auto-negotiation. */
1609         status = hw->mac.ops.read_iosf_sb_reg(hw,
1610                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1611                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1612
1613         if (status) {
1614                 DEBUGOUT("Auto-negotiation did not complete\n");
1615                 return status;
1616         }
1617
1618         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1619         status = hw->mac.ops.write_iosf_sb_reg(hw,
1620                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1621                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1622
1623         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1624                 u32 flx_mask_st20;
1625
1626                 /* Indicate to FW that AN restart has been asserted */
1627                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1628                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1629                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1630
1631                 if (status) {
1632                         DEBUGOUT("Auto-negotiation did not complete\n");
1633                         return status;
1634                 }
1635
1636                 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1637                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1638                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1639                                 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1640         }
1641
1642         return status;
1643 }
1644
1645 #ifndef PREBOOT_SUPPORT
1646 /**
1647  * ixgbe_setup_sgmii - Set up link for sgmii
1648  * @hw: pointer to hardware structure
1649  * @speed: new link speed
1650  * @autoneg_wait: true when waiting for completion is needed
1651  */
1652 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1653                              bool autoneg_wait)
1654 {
1655         struct ixgbe_mac_info *mac = &hw->mac;
1656         u32 lval, sval, flx_val;
1657         s32 rc;
1658
1659         rc = mac->ops.read_iosf_sb_reg(hw,
1660                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1661                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1662         if (rc)
1663                 return rc;
1664
1665         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1666         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1667         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1668         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1669         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1670         rc = mac->ops.write_iosf_sb_reg(hw,
1671                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1672                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1673         if (rc)
1674                 return rc;
1675
1676         rc = mac->ops.read_iosf_sb_reg(hw,
1677                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1678                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1679         if (rc)
1680                 return rc;
1681
1682         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1683         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1684         rc = mac->ops.write_iosf_sb_reg(hw,
1685                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1686                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1687         if (rc)
1688                 return rc;
1689
1690         rc = mac->ops.read_iosf_sb_reg(hw,
1691                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1692                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1693         if (rc)
1694                 return rc;
1695
1696         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1697         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1698         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1699         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1700         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1701
1702         rc = mac->ops.write_iosf_sb_reg(hw,
1703                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1704                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1705         if (rc)
1706                 return rc;
1707
1708         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1709         if (rc)
1710                 return rc;
1711
1712         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1713 }
1714
1715 #endif /* PREBOOT_SUPPORT */
1716 /**
1717  * ixgbe_setup_sgmii_fw - Set up link for internal PHY SGMII auto-negotiation
1718  * @hw: pointer to hardware structure
1719  * @speed: new link speed
1720  * @autoneg_wait: true when waiting for completion is needed
1721  */
1722 STATIC s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1723                                 bool autoneg_wait)
1724 {
1725         struct ixgbe_mac_info *mac = &hw->mac;
1726         u32 lval, sval, flx_val;
1727         s32 rc;
1728
1729         rc = mac->ops.read_iosf_sb_reg(hw,
1730                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1731                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1732         if (rc)
1733                 return rc;
1734
1735         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1736         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1737         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1738         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1739         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1740         rc = mac->ops.write_iosf_sb_reg(hw,
1741                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1742                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1743         if (rc)
1744                 return rc;
1745
1746         rc = mac->ops.read_iosf_sb_reg(hw,
1747                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1748                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1749         if (rc)
1750                 return rc;
1751
1752         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1753         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1754         rc = mac->ops.write_iosf_sb_reg(hw,
1755                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1756                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1757         if (rc)
1758                 return rc;
1759
1760         rc = mac->ops.write_iosf_sb_reg(hw,
1761                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1762                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1763         if (rc)
1764                 return rc;
1765
1766         rc = mac->ops.read_iosf_sb_reg(hw,
1767                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1768                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1769         if (rc)
1770                 return rc;
1771
1772         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1773         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
1774         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1775         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1776         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1777
1778         rc = mac->ops.write_iosf_sb_reg(hw,
1779                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1780                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1781         if (rc)
1782                 return rc;
1783
1784         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1785
1786         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1787 }
1788
1789 /**
1790  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1791  *  @hw: pointer to hardware structure
1792  */
1793 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1794 {
1795         struct ixgbe_mac_info *mac = &hw->mac;
1796
1797         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1798
1799         switch (hw->mac.ops.get_media_type(hw)) {
1800         case ixgbe_media_type_fiber:
1801                 /* CS4227 does not support autoneg, so disable the laser control
1802                  * functions for SFP+ fiber
1803                  */
1804                 mac->ops.disable_tx_laser = NULL;
1805                 mac->ops.enable_tx_laser = NULL;
1806                 mac->ops.flap_tx_laser = NULL;
1807                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1808                 mac->ops.set_rate_select_speed =
1809                                         ixgbe_set_soft_rate_select_speed;
1810
1811                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1812                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1813                         mac->ops.setup_mac_link =
1814                                                 ixgbe_setup_mac_link_sfp_x550a;
1815                 else
1816                         mac->ops.setup_mac_link =
1817                                                 ixgbe_setup_mac_link_sfp_x550em;
1818                 break;
1819         case ixgbe_media_type_copper:
1820                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T)
1821                         break;
1822                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1823                         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1824                             hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1825                                 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
1826                                 mac->ops.check_link =
1827                                                    ixgbe_check_mac_link_generic;
1828                         } else {
1829                                 mac->ops.setup_link =
1830                                                   ixgbe_setup_mac_link_t_X550em;
1831                         }
1832                 } else {
1833                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1834                         mac->ops.check_link = ixgbe_check_link_t_X550em;
1835                 }
1836                 break;
1837         case ixgbe_media_type_backplane:
1838                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1839                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1840 #ifdef PREBOOT_SUPPORT
1841                         mac->ops.setup_link = ixgbe_setup_sgmii_fw;
1842 #else
1843                         mac->ops.setup_link = ixgbe_setup_sgmii;
1844 #endif /* PREBOOT_SUPPORT */
1845                 break;
1846         default:
1847                 break;
1848         }
1849 }
1850
1851 /**
1852  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1853  *  @hw: pointer to hardware structure
1854  *  @speed: pointer to link speed
1855  *  @autoneg: true when autoneg or autotry is enabled
1856  */
1857 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1858                                        ixgbe_link_speed *speed,
1859                                        bool *autoneg)
1860 {
1861         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1862
1863
1864         if (hw->phy.type == ixgbe_phy_fw) {
1865                 *autoneg = true;
1866                 *speed = hw->phy.speeds_supported;
1867                 return 0;
1868         }
1869
1870         /* SFP */
1871         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1872
1873                 /* CS4227 SFP must not enable auto-negotiation */
1874                 *autoneg = false;
1875
1876                 /* Check if 1G SFP module. */
1877                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1878                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1879                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core0 ||
1880                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core1
1881                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1882                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1883                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1884                         return IXGBE_SUCCESS;
1885                 }
1886
1887                 /* Link capabilities are based on SFP */
1888                 if (hw->phy.multispeed_fiber)
1889                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1890                                  IXGBE_LINK_SPEED_1GB_FULL;
1891                 else
1892                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1893         } else {
1894                 *autoneg = true;
1895
1896                 switch (hw->phy.type) {
1897                 case ixgbe_phy_x550em_xfi:
1898                         *speed = IXGBE_LINK_SPEED_1GB_FULL |
1899                                  IXGBE_LINK_SPEED_10GB_FULL;
1900                         *autoneg = false;
1901                         break;
1902                 case ixgbe_phy_ext_1g_t:
1903 #ifdef PREBOOT_SUPPORT
1904                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1905                         break;
1906 #endif /* PREBOOT_SUPPORT */
1907                 case ixgbe_phy_sgmii:
1908 #ifdef PREBOOT_SUPPORT
1909                         *speed = IXGBE_LINK_SPEED_1GB_FULL |
1910                                  IXGBE_LINK_SPEED_100_FULL |
1911                                  IXGBE_LINK_SPEED_10_FULL;
1912 #else
1913                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1914 #endif /* PREBOOT_SUPPORT */
1915                         break;
1916                 case ixgbe_phy_x550em_kr:
1917                         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1918                                 /* check different backplane modes */
1919                                 if (hw->phy.nw_mng_if_sel &
1920                                            IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
1921                                         *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
1922                                         break;
1923                                 } else if (hw->device_id ==
1924                                                    IXGBE_DEV_ID_X550EM_A_KR_L) {
1925                                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1926                                         break;
1927                                 }
1928                         }
1929                         /* fall through */
1930                 default:
1931                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1932                                  IXGBE_LINK_SPEED_1GB_FULL;
1933                         break;
1934                 }
1935         }
1936
1937         return IXGBE_SUCCESS;
1938 }
1939
1940 /**
1941  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1942  * @hw: pointer to hardware structure
1943  * @lsc: pointer to boolean flag which indicates whether external Base T
1944  *       PHY interrupt is lsc
1945  *
1946  * Determime if external Base T PHY interrupt cause is high temperature
1947  * failure alarm or link status change.
1948  *
1949  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1950  * failure alarm, else return PHY access status.
1951  */
1952 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1953 {
1954         u32 status;
1955         u16 reg;
1956
1957         *lsc = false;
1958
1959         /* Vendor alarm triggered */
1960         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1961                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1962                                       &reg);
1963
1964         if (status != IXGBE_SUCCESS ||
1965             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1966                 return status;
1967
1968         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1969         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1970                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1971                                       &reg);
1972
1973         if (status != IXGBE_SUCCESS ||
1974             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1975             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1976                 return status;
1977
1978         /* Global alarm triggered */
1979         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1980                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1981                                       &reg);
1982
1983         if (status != IXGBE_SUCCESS)
1984                 return status;
1985
1986         /* If high temperature failure, then return over temp error and exit */
1987         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1988                 /* power down the PHY in case the PHY FW didn't already */
1989                 ixgbe_set_copper_phy_power(hw, false);
1990                 return IXGBE_ERR_OVERTEMP;
1991         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1992                 /*  device fault alarm triggered */
1993                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1994                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1995                                           &reg);
1996
1997                 if (status != IXGBE_SUCCESS)
1998                         return status;
1999
2000                 /* if device fault was due to high temp alarm handle and exit */
2001                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2002                         /* power down the PHY in case the PHY FW didn't */
2003                         ixgbe_set_copper_phy_power(hw, false);
2004                         return IXGBE_ERR_OVERTEMP;
2005                 }
2006         }
2007
2008         /* Vendor alarm 2 triggered */
2009         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2010                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2011
2012         if (status != IXGBE_SUCCESS ||
2013             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2014                 return status;
2015
2016         /* link connect/disconnect event occurred */
2017         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2018                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2019
2020         if (status != IXGBE_SUCCESS)
2021                 return status;
2022
2023         /* Indicate LSC */
2024         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2025                 *lsc = true;
2026
2027         return IXGBE_SUCCESS;
2028 }
2029
2030 /**
2031  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2032  * @hw: pointer to hardware structure
2033  *
2034  * Enable link status change and temperature failure alarm for the external
2035  * Base T PHY
2036  *
2037  * Returns PHY access status
2038  */
2039 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2040 {
2041         u32 status;
2042         u16 reg;
2043         bool lsc;
2044
2045         /* Clear interrupt flags */
2046         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2047
2048         /* Enable link status change alarm */
2049
2050         /* Enable the LASI interrupts on X552 devices to receive notifications
2051          * of the link configurations of the external PHY and correspondingly
2052          * support the configuration of the internal iXFI link, since iXFI does
2053          * not support auto-negotiation. This is not required for X553 devices
2054          * having KR support, which performs auto-negotiations and which is used
2055          * as the internal link to the external PHY. Hence adding a check here
2056          * to avoid enabling LASI interrupts for X553 devices.
2057          */
2058         if (hw->mac.type != ixgbe_mac_X550EM_a) {
2059                 status = hw->phy.ops.read_reg(hw,
2060                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2061                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2062
2063                 if (status != IXGBE_SUCCESS)
2064                         return status;
2065
2066                 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2067
2068                 status = hw->phy.ops.write_reg(hw,
2069                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2070                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2071
2072                 if (status != IXGBE_SUCCESS)
2073                         return status;
2074         }
2075
2076         /* Enable high temperature failure and global fault alarms */
2077         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2078                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2079                                       &reg);
2080
2081         if (status != IXGBE_SUCCESS)
2082                 return status;
2083
2084         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2085                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2086
2087         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2088                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2089                                        reg);
2090
2091         if (status != IXGBE_SUCCESS)
2092                 return status;
2093
2094         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2095         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2096                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2097                                       &reg);
2098
2099         if (status != IXGBE_SUCCESS)
2100                 return status;
2101
2102         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2103                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2104
2105         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2106                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2107                                        reg);
2108
2109         if (status != IXGBE_SUCCESS)
2110                 return status;
2111
2112         /* Enable chip-wide vendor alarm */
2113         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2114                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2115                                       &reg);
2116
2117         if (status != IXGBE_SUCCESS)
2118                 return status;
2119
2120         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2121
2122         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2123                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2124                                        reg);
2125
2126         return status;
2127 }
2128
2129 /**
2130  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2131  *  @hw: pointer to hardware structure
2132  *  @speed: link speed
2133  *
2134  *  Configures the integrated KR PHY.
2135  **/
2136 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2137                                        ixgbe_link_speed speed)
2138 {
2139         s32 status;
2140         u32 reg_val;
2141
2142         status = hw->mac.ops.read_iosf_sb_reg(hw,
2143                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2144                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2145         if (status)
2146                 return status;
2147
2148         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2149         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2150                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2151
2152         /* Advertise 10G support. */
2153         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2154                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2155
2156         /* Advertise 1G support. */
2157         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2158                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2159
2160         status = hw->mac.ops.write_iosf_sb_reg(hw,
2161                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2162                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2163
2164         if (hw->mac.type == ixgbe_mac_X550EM_a) {
2165                 /* Set lane mode  to KR auto negotiation */
2166                 status = hw->mac.ops.read_iosf_sb_reg(hw,
2167                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2168                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2169
2170                 if (status)
2171                         return status;
2172
2173                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2174                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2175                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2176                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2177                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2178
2179                 status = hw->mac.ops.write_iosf_sb_reg(hw,
2180                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2181                                     IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2182         }
2183
2184         return ixgbe_restart_an_internal_phy_x550em(hw);
2185 }
2186
2187 /**
2188  * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
2189  * @hw: pointer to hardware structure
2190  */
2191 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
2192 {
2193         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2194         s32 rc;
2195
2196         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2197                 return IXGBE_SUCCESS;
2198
2199         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
2200         if (rc)
2201                 return rc;
2202         memset(store, 0, sizeof(store));
2203
2204         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
2205         if (rc)
2206                 return rc;
2207
2208         return ixgbe_setup_fw_link(hw);
2209 }
2210
2211 /**
2212  * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
2213  * @hw: pointer to hardware structure
2214  */
2215 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
2216 {
2217         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2218         s32 rc;
2219
2220         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
2221         if (rc)
2222                 return rc;
2223
2224         if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
2225                 ixgbe_shutdown_fw_phy(hw);
2226                 return IXGBE_ERR_OVERTEMP;
2227         }
2228         return IXGBE_SUCCESS;
2229 }
2230
2231 /**
2232  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2233  *  @hw: pointer to hardware structure
2234  *
2235  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2236  *  values.
2237  **/
2238 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2239 {
2240         /* Save NW management interface connected on board. This is used
2241          * to determine internal PHY mode.
2242          */
2243         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2244
2245         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2246          * PHY address. This register field was has only been used for X552.
2247          */
2248         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2249             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2250                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2251                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2252                                IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2253         }
2254
2255         return IXGBE_SUCCESS;
2256 }
2257
2258 /**
2259  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2260  *  @hw: pointer to hardware structure
2261  *
2262  *  Initialize any function pointers that were not able to be
2263  *  set during init_shared_code because the PHY/SFP type was
2264  *  not known.  Perform the SFP init if necessary.
2265  */
2266 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2267 {
2268         struct ixgbe_phy_info *phy = &hw->phy;
2269         s32 ret_val;
2270
2271         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2272
2273         hw->mac.ops.set_lan_id(hw);
2274         ixgbe_read_mng_if_sel_x550em(hw);
2275
2276         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2277                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2278                 ixgbe_setup_mux_ctl(hw);
2279                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2280         }
2281
2282         switch (hw->device_id) {
2283         case IXGBE_DEV_ID_X550EM_A_1G_T:
2284         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2285                 phy->ops.read_reg_mdi = NULL;
2286                 phy->ops.write_reg_mdi = NULL;
2287                 hw->phy.ops.read_reg = NULL;
2288                 hw->phy.ops.write_reg = NULL;
2289                 phy->ops.check_overtemp = ixgbe_check_overtemp_fw;
2290                 if (hw->bus.lan_id)
2291                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2292                 else
2293                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2294
2295                 break;
2296         case IXGBE_DEV_ID_X550EM_A_10G_T:
2297         case IXGBE_DEV_ID_X550EM_A_SFP:
2298                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2299                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2300                 if (hw->bus.lan_id)
2301                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2302                 else
2303                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2304                 break;
2305         case IXGBE_DEV_ID_X550EM_X_SFP:
2306                 /* set up for CS4227 usage */
2307                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2308                 break;
2309         case IXGBE_DEV_ID_X550EM_X_1G_T:
2310                 phy->ops.read_reg_mdi = NULL;
2311                 phy->ops.write_reg_mdi = NULL;
2312         default:
2313                 break;
2314         }
2315
2316         /* Identify the PHY or SFP module */
2317         ret_val = phy->ops.identify(hw);
2318         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED ||
2319             ret_val == IXGBE_ERR_PHY_ADDR_INVALID)
2320                 return ret_val;
2321
2322         /* Setup function pointers based on detected hardware */
2323         ixgbe_init_mac_link_ops_X550em(hw);
2324         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2325                 phy->ops.reset = NULL;
2326
2327         /* Set functions pointers based on phy type */
2328         switch (hw->phy.type) {
2329         case ixgbe_phy_x550em_kx4:
2330                 phy->ops.setup_link = NULL;
2331                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2332                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2333                 break;
2334         case ixgbe_phy_x550em_kr:
2335                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2336                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2337                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2338                 break;
2339         case ixgbe_phy_ext_1g_t:
2340                 /* link is managed by FW */
2341                 phy->ops.setup_link = NULL;
2342                 phy->ops.reset = NULL;
2343                 break;
2344         case ixgbe_phy_x550em_xfi:
2345                 /* link is managed by HW */
2346                 phy->ops.setup_link = NULL;
2347                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2348                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2349                 break;
2350         case ixgbe_phy_x550em_ext_t:
2351                 /* If internal link mode is XFI, then setup iXFI internal link,
2352                  * else setup KR now.
2353                  */
2354                 phy->ops.setup_internal_link =
2355                                               ixgbe_setup_internal_phy_t_x550em;
2356
2357                 /* setup SW LPLU only for first revision of X550EM_x */
2358                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2359                     !(IXGBE_FUSES0_REV_MASK &
2360                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2361                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2362
2363                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2364                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2365                 break;
2366         case ixgbe_phy_sgmii:
2367                 phy->ops.setup_link = NULL;
2368                 break;
2369         case ixgbe_phy_fw:
2370                 phy->ops.setup_link = ixgbe_setup_fw_link;
2371                 phy->ops.reset = ixgbe_reset_phy_fw;
2372                 break;
2373         default:
2374                 break;
2375         }
2376         return ret_val;
2377 }
2378
2379 /**
2380  * ixgbe_set_mdio_speed - Set MDIO clock speed
2381  *  @hw: pointer to hardware structure
2382  */
2383 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2384 {
2385         u32 hlreg0;
2386
2387         switch (hw->device_id) {
2388         case IXGBE_DEV_ID_X550EM_X_10G_T:
2389         case IXGBE_DEV_ID_X550EM_A_SGMII:
2390         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2391         case IXGBE_DEV_ID_X550EM_A_10G_T:
2392         case IXGBE_DEV_ID_X550EM_A_SFP:
2393         case IXGBE_DEV_ID_X550EM_A_QSFP:
2394                 /* Config MDIO clock speed before the first MDIO PHY access */
2395                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2396                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2397                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2398                 break;
2399         case IXGBE_DEV_ID_X550EM_A_1G_T:
2400         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2401                 /* Select fast MDIO clock speed for these devices */
2402                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2403                 hlreg0 |= IXGBE_HLREG0_MDCSPD;
2404                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2405                 break;
2406         default:
2407                 break;
2408         }
2409 }
2410
2411 /**
2412  *  ixgbe_reset_hw_X550em - Perform hardware reset
2413  *  @hw: pointer to hardware structure
2414  *
2415  *  Resets the hardware by resetting the transmit and receive units, masks
2416  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2417  *  reset.
2418  */
2419 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2420 {
2421         ixgbe_link_speed link_speed;
2422         s32 status;
2423         u32 ctrl = 0;
2424         u32 i;
2425         bool link_up = false;
2426         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2427
2428         DEBUGFUNC("ixgbe_reset_hw_X550em");
2429
2430         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2431         status = hw->mac.ops.stop_adapter(hw);
2432         if (status != IXGBE_SUCCESS) {
2433                 DEBUGOUT1("Failed to stop adapter, STATUS = %d\n", status);
2434                 return status;
2435         }
2436         /* flush pending Tx transactions */
2437         ixgbe_clear_tx_pending(hw);
2438
2439         ixgbe_set_mdio_speed(hw);
2440
2441         /* PHY ops must be identified and initialized prior to reset */
2442         status = hw->phy.ops.init(hw);
2443
2444         if (status)
2445                 DEBUGOUT1("Failed to initialize PHY ops, STATUS = %d\n",
2446                           status);
2447
2448         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED ||
2449             status == IXGBE_ERR_PHY_ADDR_INVALID) {
2450                 DEBUGOUT("Returning from reset HW due to PHY init failure\n");
2451                 return status;
2452         }
2453
2454         /* start the external PHY */
2455         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2456                 status = ixgbe_init_ext_t_x550em(hw);
2457                 if (status) {
2458                         DEBUGOUT1("Failed to start the external PHY, STATUS = %d\n",
2459                                   status);
2460                         return status;
2461                 }
2462         }
2463
2464         /* Setup SFP module if there is one present. */
2465         if (hw->phy.sfp_setup_needed) {
2466                 status = hw->mac.ops.setup_sfp(hw);
2467                 hw->phy.sfp_setup_needed = false;
2468         }
2469
2470         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2471                 return status;
2472
2473         /* Reset PHY */
2474         if (!hw->phy.reset_disable && hw->phy.ops.reset) {
2475                 if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP)
2476                         return IXGBE_ERR_OVERTEMP;
2477         }
2478
2479 mac_reset_top:
2480         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2481          * If link reset is used when link is up, it might reset the PHY when
2482          * mng is using it.  If link is down or the flag to force full link
2483          * reset is set, then perform link reset.
2484          */
2485         ctrl = IXGBE_CTRL_LNK_RST;
2486         if (!hw->force_full_reset) {
2487                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2488                 if (link_up)
2489                         ctrl = IXGBE_CTRL_RST;
2490         }
2491
2492         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2493         if (status != IXGBE_SUCCESS) {
2494                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
2495                         "semaphore failed with %d", status);
2496                 return IXGBE_ERR_SWFW_SYNC;
2497         }
2498         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2499         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2500         IXGBE_WRITE_FLUSH(hw);
2501         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2502
2503         /* Poll for reset bit to self-clear meaning reset is complete */
2504         for (i = 0; i < 10; i++) {
2505                 usec_delay(1);
2506                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2507                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2508                         break;
2509         }
2510
2511         if (ctrl & IXGBE_CTRL_RST_MASK) {
2512                 status = IXGBE_ERR_RESET_FAILED;
2513                 DEBUGOUT("Reset polling failed to complete.\n");
2514         }
2515
2516         msec_delay(50);
2517
2518         /* Double resets are required for recovery from certain error
2519          * conditions.  Between resets, it is necessary to stall to
2520          * allow time for any pending HW events to complete.
2521          */
2522         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2523                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2524                 goto mac_reset_top;
2525         }
2526
2527         /* Store the permanent mac address */
2528         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2529
2530         /* Store MAC address from RAR0, clear receive address registers, and
2531          * clear the multicast table.  Also reset num_rar_entries to 128,
2532          * since we modify this value when programming the SAN MAC address.
2533          */
2534         hw->mac.num_rar_entries = 128;
2535         hw->mac.ops.init_rx_addrs(hw);
2536
2537         ixgbe_set_mdio_speed(hw);
2538
2539         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2540                 ixgbe_setup_mux_ctl(hw);
2541
2542         if (status != IXGBE_SUCCESS)
2543                 DEBUGOUT1("Reset HW failed, STATUS = %d\n", status);
2544
2545         return status;
2546 }
2547
2548 /**
2549  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2550  * @hw: pointer to hardware structure
2551  */
2552 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2553 {
2554         u32 status;
2555         u16 reg;
2556
2557         status = hw->phy.ops.read_reg(hw,
2558                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2559                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2560                                       &reg);
2561
2562         if (status != IXGBE_SUCCESS)
2563                 return status;
2564
2565         /* If PHY FW reset completed bit is set then this is the first
2566          * SW instance after a power on so the PHY FW must be un-stalled.
2567          */
2568         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2569                 status = hw->phy.ops.read_reg(hw,
2570                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2571                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2572                                         &reg);
2573
2574                 if (status != IXGBE_SUCCESS)
2575                         return status;
2576
2577                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2578
2579                 status = hw->phy.ops.write_reg(hw,
2580                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2581                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2582                                         reg);
2583
2584                 if (status != IXGBE_SUCCESS)
2585                         return status;
2586         }
2587
2588         return status;
2589 }
2590
2591 /**
2592  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2593  *  @hw: pointer to hardware structure
2594  **/
2595 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2596 {
2597         /* leave link alone for 2.5G */
2598         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2599                 return IXGBE_SUCCESS;
2600
2601         if (ixgbe_check_reset_blocked(hw))
2602                 return 0;
2603
2604         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2605 }
2606
2607 /**
2608  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2609  *  @hw: pointer to hardware structure
2610  *  @speed: new link speed
2611  *  @autoneg_wait_to_complete: unused
2612  *
2613  *  Configure the external PHY and the integrated KR PHY for SFP support.
2614  **/
2615 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2616                                     ixgbe_link_speed speed,
2617                                     bool autoneg_wait_to_complete)
2618 {
2619         s32 ret_val;
2620         u16 reg_slice, reg_val;
2621         bool setup_linear = false;
2622         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2623
2624         /* Check if SFP module is supported and linear */
2625         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2626
2627         /* If no SFP module present, then return success. Return success since
2628          * there is no reason to configure CS4227 and SFP not present error is
2629          * not excepted in the setup MAC link flow.
2630          */
2631         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2632                 return IXGBE_SUCCESS;
2633
2634         if (ret_val != IXGBE_SUCCESS)
2635                 return ret_val;
2636
2637         /* Configure internal PHY for KR/KX. */
2638         ixgbe_setup_kr_speed_x550em(hw, speed);
2639
2640         /* Configure CS4227 LINE side to proper mode. */
2641         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2642                     (hw->bus.lan_id << 12);
2643         if (setup_linear)
2644                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2645         else
2646                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2647         ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2648                                           reg_val);
2649         return ret_val;
2650 }
2651
2652 /**
2653  *  ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2654  *  @hw: pointer to hardware structure
2655  *  @speed: the link speed to force
2656  *
2657  *  Configures the integrated PHY for native SFI mode. Used to connect the
2658  *  internal PHY directly to an SFP cage, without autonegotiation.
2659  **/
2660 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2661 {
2662         struct ixgbe_mac_info *mac = &hw->mac;
2663         s32 status;
2664         u32 reg_val;
2665
2666         /* Disable all AN and force speed to 10G Serial. */
2667         status = mac->ops.read_iosf_sb_reg(hw,
2668                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2669                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2670         if (status != IXGBE_SUCCESS)
2671                 return status;
2672
2673         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2674         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2675         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2676         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2677
2678         /* Select forced link speed for internal PHY. */
2679         switch (*speed) {
2680         case IXGBE_LINK_SPEED_10GB_FULL:
2681                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2682                 break;
2683         case IXGBE_LINK_SPEED_1GB_FULL:
2684                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2685                 break;
2686         default:
2687                 /* Other link speeds are not supported by internal PHY. */
2688                 return IXGBE_ERR_LINK_SETUP;
2689         }
2690
2691         status = mac->ops.write_iosf_sb_reg(hw,
2692                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2693                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2694
2695         /* Toggle port SW reset by AN reset. */
2696         status = ixgbe_restart_an_internal_phy_x550em(hw);
2697
2698         return status;
2699 }
2700
2701 /**
2702  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2703  *  @hw: pointer to hardware structure
2704  *  @speed: new link speed
2705  *  @autoneg_wait_to_complete: unused
2706  *
2707  *  Configure the integrated PHY for SFP support.
2708  **/
2709 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2710                                     ixgbe_link_speed speed,
2711                                     bool autoneg_wait_to_complete)
2712 {
2713         s32 ret_val;
2714         u16 reg_phy_ext;
2715         bool setup_linear = false;
2716         u32 reg_slice, reg_phy_int, slice_offset;
2717
2718         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2719
2720         /* Check if SFP module is supported and linear */
2721         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2722
2723         /* If no SFP module present, then return success. Return success since
2724          * SFP not present error is not excepted in the setup MAC link flow.
2725          */
2726         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2727                 return IXGBE_SUCCESS;
2728
2729         if (ret_val != IXGBE_SUCCESS)
2730                 return ret_val;
2731
2732         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2733                 /* Configure internal PHY for native SFI based on module type */
2734                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2735                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2736                                    IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2737
2738                 if (ret_val != IXGBE_SUCCESS)
2739                         return ret_val;
2740
2741                 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2742                 if (!setup_linear)
2743                         reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2744
2745                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2746                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2747                                    IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2748
2749                 if (ret_val != IXGBE_SUCCESS)
2750                         return ret_val;
2751
2752                 /* Setup SFI internal link. */
2753                 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2754         } else {
2755                 /* Configure internal PHY for KR/KX. */
2756                 ixgbe_setup_kr_speed_x550em(hw, speed);
2757
2758                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2759                         /* Find Address */
2760                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2761                         return IXGBE_ERR_PHY_ADDR_INVALID;
2762                 }
2763
2764                 /* Get external PHY SKU id */
2765                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
2766                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2767
2768                 if (ret_val != IXGBE_SUCCESS)
2769                         return ret_val;
2770
2771                 /* When configuring quad port CS4223, the MAC instance is part
2772                  * of the slice offset.
2773                  */
2774                 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
2775                         slice_offset = (hw->bus.lan_id +
2776                                         (hw->bus.instance_id << 1)) << 12;
2777                 else
2778                         slice_offset = hw->bus.lan_id << 12;
2779
2780                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2781                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2782
2783                 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2784                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2785
2786                 if (ret_val != IXGBE_SUCCESS)
2787                         return ret_val;
2788
2789                 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
2790                                  (IXGBE_CS4227_EDC_MODE_SR << 1));
2791
2792                 if (setup_linear)
2793                         reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2794                 else
2795                         reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2796                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2797                                          IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2798
2799                 /* Flush previous write with a read */
2800                 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2801                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2802         }
2803         return ret_val;
2804 }
2805
2806 /**
2807  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2808  *  @hw: pointer to hardware structure
2809  *
2810  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2811  **/
2812 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2813 {
2814         struct ixgbe_mac_info *mac = &hw->mac;
2815         s32 status;
2816         u32 reg_val;
2817
2818         /* Disable training protocol FSM. */
2819         status = mac->ops.read_iosf_sb_reg(hw,
2820                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2821                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2822         if (status != IXGBE_SUCCESS)
2823                 return status;
2824         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2825         status = mac->ops.write_iosf_sb_reg(hw,
2826                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2827                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2828         if (status != IXGBE_SUCCESS)
2829                 return status;
2830
2831         /* Disable Flex from training TXFFE. */
2832         status = mac->ops.read_iosf_sb_reg(hw,
2833                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2834                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2835         if (status != IXGBE_SUCCESS)
2836                 return status;
2837         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2838         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2839         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2840         status = mac->ops.write_iosf_sb_reg(hw,
2841                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2842                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2843         if (status != IXGBE_SUCCESS)
2844                 return status;
2845         status = mac->ops.read_iosf_sb_reg(hw,
2846                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2847                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2848         if (status != IXGBE_SUCCESS)
2849                 return status;
2850         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2851         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2852         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2853         status = mac->ops.write_iosf_sb_reg(hw,
2854                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2855                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2856         if (status != IXGBE_SUCCESS)
2857                 return status;
2858
2859         /* Enable override for coefficients. */
2860         status = mac->ops.read_iosf_sb_reg(hw,
2861                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2862                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2863         if (status != IXGBE_SUCCESS)
2864                 return status;
2865         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2866         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2867         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2868         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2869         status = mac->ops.write_iosf_sb_reg(hw,
2870                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2871                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2872         return status;
2873 }
2874
2875 /**
2876  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2877  *  @hw: pointer to hardware structure
2878  *  @speed: the link speed to force
2879  *
2880  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2881  *  internal and external PHY at a specific speed, without autonegotiation.
2882  **/
2883 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2884 {
2885         struct ixgbe_mac_info *mac = &hw->mac;
2886         s32 status;
2887         u32 reg_val;
2888
2889         /* iXFI is only supported with X552 */
2890         if (mac->type != ixgbe_mac_X550EM_x)
2891                 return IXGBE_ERR_LINK_SETUP;
2892
2893         /* Disable AN and force speed to 10G Serial. */
2894         status = mac->ops.read_iosf_sb_reg(hw,
2895                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2896                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2897         if (status != IXGBE_SUCCESS)
2898                 return status;
2899
2900         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2901         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2902
2903         /* Select forced link speed for internal PHY. */
2904         switch (*speed) {
2905         case IXGBE_LINK_SPEED_10GB_FULL:
2906                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2907                 break;
2908         case IXGBE_LINK_SPEED_1GB_FULL:
2909                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2910                 break;
2911         default:
2912                 /* Other link speeds are not supported by internal KR PHY. */
2913                 return IXGBE_ERR_LINK_SETUP;
2914         }
2915
2916         status = mac->ops.write_iosf_sb_reg(hw,
2917                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2918                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2919         if (status != IXGBE_SUCCESS)
2920                 return status;
2921
2922         /* Additional configuration needed for x550em_x */
2923         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2924                 status = ixgbe_setup_ixfi_x550em_x(hw);
2925                 if (status != IXGBE_SUCCESS)
2926                         return status;
2927         }
2928
2929         /* Toggle port SW reset by AN reset. */
2930         status = ixgbe_restart_an_internal_phy_x550em(hw);
2931
2932         return status;
2933 }
2934
2935 /**
2936  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2937  * @hw: address of hardware structure
2938  * @link_up: address of boolean to indicate link status
2939  *
2940  * Returns error code if unable to get link status.
2941  */
2942 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2943 {
2944         u32 ret;
2945         u16 autoneg_status;
2946
2947         *link_up = false;
2948
2949         /* read this twice back to back to indicate current status */
2950         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2951                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2952                                    &autoneg_status);
2953         if (ret != IXGBE_SUCCESS)
2954                 return ret;
2955
2956         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2957                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2958                                    &autoneg_status);
2959         if (ret != IXGBE_SUCCESS)
2960                 return ret;
2961
2962         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2963
2964         return IXGBE_SUCCESS;
2965 }
2966
2967 /**
2968  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2969  * @hw: point to hardware structure
2970  *
2971  * Configures the link between the integrated KR PHY and the external X557 PHY
2972  * The driver will call this function when it gets a link status change
2973  * interrupt from the X557 PHY. This function configures the link speed
2974  * between the PHYs to match the link speed of the BASE-T link.
2975  *
2976  * A return of a non-zero value indicates an error, and the base driver should
2977  * not report link up.
2978  */
2979 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2980 {
2981         ixgbe_link_speed force_speed;
2982         bool link_up;
2983         u32 status;
2984         u16 speed;
2985
2986         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2987                 return IXGBE_ERR_CONFIG;
2988
2989         if (hw->mac.type == ixgbe_mac_X550EM_x &&
2990             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2991                 /* If link is down, there is no setup necessary so return  */
2992                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2993                 if (status != IXGBE_SUCCESS)
2994                         return status;
2995
2996                 if (!link_up)
2997                         return IXGBE_SUCCESS;
2998
2999                 status = hw->phy.ops.read_reg(hw,
3000                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3001                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3002                                               &speed);
3003                 if (status != IXGBE_SUCCESS)
3004                         return status;
3005
3006                 /* If link is still down - no setup is required so return */
3007                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3008                 if (status != IXGBE_SUCCESS)
3009                         return status;
3010                 if (!link_up)
3011                         return IXGBE_SUCCESS;
3012
3013                 /* clear everything but the speed and duplex bits */
3014                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3015
3016                 switch (speed) {
3017                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3018                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3019                         break;
3020                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3021                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3022                         break;
3023                 default:
3024                         /* Internal PHY does not support anything else */
3025                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
3026                 }
3027
3028                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3029         } else {
3030                 speed = IXGBE_LINK_SPEED_10GB_FULL |
3031                         IXGBE_LINK_SPEED_1GB_FULL;
3032                 return ixgbe_setup_kr_speed_x550em(hw, speed);
3033         }
3034 }
3035
3036 /**
3037  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3038  *  @hw: pointer to hardware structure
3039  *
3040  *  Configures the integrated KR PHY to use internal loopback mode.
3041  **/
3042 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3043 {
3044         s32 status;
3045         u32 reg_val;
3046
3047         /* Disable AN and force speed to 10G Serial. */
3048         status = hw->mac.ops.read_iosf_sb_reg(hw,
3049                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3050                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3051         if (status != IXGBE_SUCCESS)
3052                 return status;
3053         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3054         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3055         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3056         status = hw->mac.ops.write_iosf_sb_reg(hw,
3057                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3058                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3059         if (status != IXGBE_SUCCESS)
3060                 return status;
3061
3062         /* Set near-end loopback clocks. */
3063         status = hw->mac.ops.read_iosf_sb_reg(hw,
3064                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3065                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3066         if (status != IXGBE_SUCCESS)
3067                 return status;
3068         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3069         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3070         status = hw->mac.ops.write_iosf_sb_reg(hw,
3071                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3072                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3073         if (status != IXGBE_SUCCESS)
3074                 return status;
3075
3076         /* Set loopback enable. */
3077         status = hw->mac.ops.read_iosf_sb_reg(hw,
3078                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3079                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3080         if (status != IXGBE_SUCCESS)
3081                 return status;
3082         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3083         status = hw->mac.ops.write_iosf_sb_reg(hw,
3084                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3085                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3086         if (status != IXGBE_SUCCESS)
3087                 return status;
3088
3089         /* Training bypass. */
3090         status = hw->mac.ops.read_iosf_sb_reg(hw,
3091                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3092                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3093         if (status != IXGBE_SUCCESS)
3094                 return status;
3095         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3096         status = hw->mac.ops.write_iosf_sb_reg(hw,
3097                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3098                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3099
3100         return status;
3101 }
3102
3103 /**
3104  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3105  *  assuming that the semaphore is already obtained.
3106  *  @hw: pointer to hardware structure
3107  *  @offset: offset of  word in the EEPROM to read
3108  *  @data: word read from the EEPROM
3109  *
3110  *  Reads a 16 bit word from the EEPROM using the hostif.
3111  **/
3112 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3113 {
3114         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3115         struct ixgbe_hic_read_shadow_ram buffer;
3116         s32 status;
3117
3118         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3119         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3120         buffer.hdr.req.buf_lenh = 0;
3121         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3122         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3123
3124         /* convert offset from words to bytes */
3125         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3126         /* one word */
3127         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3128         buffer.pad2 = 0;
3129         buffer.pad3 = 0;
3130
3131         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3132         if (status)
3133                 return status;
3134
3135         status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3136                                     IXGBE_HI_COMMAND_TIMEOUT);
3137         if (!status) {
3138                 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3139                                                   FW_NVM_DATA_OFFSET);
3140         }
3141
3142         hw->mac.ops.release_swfw_sync(hw, mask);
3143         return status;
3144 }
3145
3146 /**
3147  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3148  *  @hw: pointer to hardware structure
3149  *  @offset: offset of  word in the EEPROM to read
3150  *  @words: number of words
3151  *  @data: word(s) read from the EEPROM
3152  *
3153  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
3154  **/
3155 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3156                                      u16 offset, u16 words, u16 *data)
3157 {
3158         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3159         struct ixgbe_hic_read_shadow_ram buffer;
3160         u32 current_word = 0;
3161         u16 words_to_read;
3162         s32 status;
3163         u32 i;
3164
3165         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3166
3167         /* Take semaphore for the entire operation. */
3168         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3169         if (status) {
3170                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3171                 return status;
3172         }
3173
3174         while (words) {
3175                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3176                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3177                 else
3178                         words_to_read = words;
3179
3180                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3181                 buffer.hdr.req.buf_lenh = 0;
3182                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3183                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3184
3185                 /* convert offset from words to bytes */
3186                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3187                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3188                 buffer.pad2 = 0;
3189                 buffer.pad3 = 0;
3190
3191                 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3192                                             IXGBE_HI_COMMAND_TIMEOUT);
3193
3194                 if (status) {
3195                         DEBUGOUT("Host interface command failed\n");
3196                         goto out;
3197                 }
3198
3199                 for (i = 0; i < words_to_read; i++) {
3200                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3201                                   2 * i;
3202                         u32 value = IXGBE_READ_REG(hw, reg);
3203
3204                         data[current_word] = (u16)(value & 0xffff);
3205                         current_word++;
3206                         i++;
3207                         if (i < words_to_read) {
3208                                 value >>= 16;
3209                                 data[current_word] = (u16)(value & 0xffff);
3210                                 current_word++;
3211                         }
3212                 }
3213                 words -= words_to_read;
3214         }
3215
3216 out:
3217         hw->mac.ops.release_swfw_sync(hw, mask);
3218         return status;
3219 }
3220
3221 /**
3222  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3223  *  @hw: pointer to hardware structure
3224  *  @offset: offset of  word in the EEPROM to write
3225  *  @data: word write to the EEPROM
3226  *
3227  *  Write a 16 bit word to the EEPROM using the hostif.
3228  **/
3229 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3230                                     u16 data)
3231 {
3232         s32 status;
3233         struct ixgbe_hic_write_shadow_ram buffer;
3234
3235         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3236
3237         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3238         buffer.hdr.req.buf_lenh = 0;
3239         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3240         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3241
3242          /* one word */
3243         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3244         buffer.data = data;
3245         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3246
3247         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3248                                               sizeof(buffer),
3249                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3250
3251         return status;
3252 }
3253
3254 /**
3255  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3256  *  @hw: pointer to hardware structure
3257  *  @offset: offset of  word in the EEPROM to write
3258  *  @data: word write to the EEPROM
3259  *
3260  *  Write a 16 bit word to the EEPROM using the hostif.
3261  **/
3262 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3263                                u16 data)
3264 {
3265         s32 status = IXGBE_SUCCESS;
3266
3267         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3268
3269         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3270             IXGBE_SUCCESS) {
3271                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3272                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3273         } else {
3274                 DEBUGOUT("write ee hostif failed to get semaphore");
3275                 status = IXGBE_ERR_SWFW_SYNC;
3276         }
3277
3278         return status;
3279 }
3280
3281 /**
3282  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3283  *  @hw: pointer to hardware structure
3284  *  @offset: offset of  word in the EEPROM to write
3285  *  @words: number of words
3286  *  @data: word(s) write to the EEPROM
3287  *
3288  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3289  **/
3290 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3291                                       u16 offset, u16 words, u16 *data)
3292 {
3293         s32 status = IXGBE_SUCCESS;
3294         u32 i = 0;
3295
3296         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3297
3298         /* Take semaphore for the entire operation. */
3299         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3300         if (status != IXGBE_SUCCESS) {
3301                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3302                 goto out;
3303         }
3304
3305         for (i = 0; i < words; i++) {
3306                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3307                                                          data[i]);
3308
3309                 if (status != IXGBE_SUCCESS) {
3310                         DEBUGOUT("Eeprom buffered write failed\n");
3311                         break;
3312                 }
3313         }
3314
3315         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3316 out:
3317
3318         return status;
3319 }
3320
3321 /**
3322  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3323  * @hw: pointer to hardware structure
3324  * @ptr: pointer offset in eeprom
3325  * @size: size of section pointed by ptr, if 0 first word will be used as size
3326  * @csum: address of checksum to update
3327  * @buffer: pointer to buffer containing calculated checksum
3328  * @buffer_size: size of buffer
3329  *
3330  * Returns error status for any failure
3331  */
3332 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3333                                    u16 size, u16 *csum, u16 *buffer,
3334                                    u32 buffer_size)
3335 {
3336         u16 buf[256];
3337         s32 status;
3338         u16 length, bufsz, i, start;
3339         u16 *local_buffer;
3340
3341         bufsz = sizeof(buf) / sizeof(buf[0]);
3342
3343         /* Read a chunk at the pointer location */
3344         if (!buffer) {
3345                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3346                 if (status) {
3347                         DEBUGOUT("Failed to read EEPROM image\n");
3348                         return status;
3349                 }
3350                 local_buffer = buf;
3351         } else {
3352                 if (buffer_size < ptr)
3353                         return  IXGBE_ERR_PARAM;
3354                 local_buffer = &buffer[ptr];
3355         }
3356
3357         if (size) {
3358                 start = 0;
3359                 length = size;
3360         } else {
3361                 start = 1;
3362                 length = local_buffer[0];
3363
3364                 /* Skip pointer section if length is invalid. */
3365                 if (length == 0xFFFF || length == 0 ||
3366                     (ptr + length) >= hw->eeprom.word_size)
3367                         return IXGBE_SUCCESS;
3368         }
3369
3370         if (buffer && ((u32)start + (u32)length > buffer_size))
3371                 return IXGBE_ERR_PARAM;
3372
3373         for (i = start; length; i++, length--) {
3374                 if (i == bufsz && !buffer) {
3375                         ptr += bufsz;
3376                         i = 0;
3377                         if (length < bufsz)
3378                                 bufsz = length;
3379
3380                         /* Read a chunk at the pointer location */
3381                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3382                                                                   bufsz, buf);
3383                         if (status) {
3384                                 DEBUGOUT("Failed to read EEPROM image\n");
3385                                 return status;
3386                         }
3387                 }
3388                 *csum += local_buffer[i];
3389         }
3390         return IXGBE_SUCCESS;
3391 }
3392
3393 /**
3394  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3395  *  @hw: pointer to hardware structure
3396  *  @buffer: pointer to buffer containing calculated checksum
3397  *  @buffer_size: size of buffer
3398  *
3399  *  Returns a negative error code on error, or the 16-bit checksum
3400  **/
3401 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3402 {
3403         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3404         u16 *local_buffer;
3405         s32 status;
3406         u16 checksum = 0;
3407         u16 pointer, i, size;
3408
3409         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3410
3411         hw->eeprom.ops.init_params(hw);
3412
3413         if (!buffer) {
3414                 /* Read pointer area */
3415                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3416                                                      IXGBE_EEPROM_LAST_WORD + 1,
3417                                                      eeprom_ptrs);
3418                 if (status) {
3419                         DEBUGOUT("Failed to read EEPROM image\n");
3420                         return status;
3421                 }
3422                 local_buffer = eeprom_ptrs;
3423         } else {
3424                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3425                         return IXGBE_ERR_PARAM;
3426                 local_buffer = buffer;
3427         }
3428
3429         /*
3430          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3431          * checksum word itself
3432          */
3433         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3434                 if (i != IXGBE_EEPROM_CHECKSUM)
3435                         checksum += local_buffer[i];
3436
3437         /*
3438          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3439          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3440          */
3441         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3442                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3443                         continue;
3444
3445                 pointer = local_buffer[i];
3446
3447                 /* Skip pointer section if the pointer is invalid. */
3448                 if (pointer == 0xFFFF || pointer == 0 ||
3449                     pointer >= hw->eeprom.word_size)
3450                         continue;
3451
3452                 switch (i) {
3453                 case IXGBE_PCIE_GENERAL_PTR:
3454                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3455                         break;
3456                 case IXGBE_PCIE_CONFIG0_PTR:
3457                 case IXGBE_PCIE_CONFIG1_PTR:
3458                         size = IXGBE_PCIE_CONFIG_SIZE;
3459                         break;
3460                 default:
3461                         size = 0;
3462                         break;
3463                 }
3464
3465                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3466                                                 buffer, buffer_size);
3467                 if (status)
3468                         return status;
3469         }
3470
3471         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3472
3473         return (s32)checksum;
3474 }
3475
3476 /**
3477  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3478  *  @hw: pointer to hardware structure
3479  *
3480  *  Returns a negative error code on error, or the 16-bit checksum
3481  **/
3482 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3483 {
3484         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3485 }
3486
3487 /**
3488  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3489  *  @hw: pointer to hardware structure
3490  *  @checksum_val: calculated checksum
3491  *
3492  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3493  *  caller does not need checksum_val, the value can be NULL.
3494  **/
3495 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3496 {
3497         s32 status;
3498         u16 checksum;
3499         u16 read_checksum = 0;
3500
3501         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3502
3503         /* Read the first word from the EEPROM. If this times out or fails, do
3504          * not continue or we could be in for a very long wait while every
3505          * EEPROM read fails
3506          */
3507         status = hw->eeprom.ops.read(hw, 0, &checksum);
3508         if (status) {
3509                 DEBUGOUT("EEPROM read failed\n");
3510                 return status;
3511         }
3512
3513         status = hw->eeprom.ops.calc_checksum(hw);
3514         if (status < 0)
3515                 return status;
3516
3517         checksum = (u16)(status & 0xffff);
3518
3519         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3520                                            &read_checksum);
3521         if (status)
3522                 return status;
3523
3524         /* Verify read checksum from EEPROM is the same as
3525          * calculated checksum
3526          */
3527         if (read_checksum != checksum) {
3528                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3529                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3530                              "Invalid EEPROM checksum");
3531         }
3532
3533         /* If the user cares, return the calculated checksum */
3534         if (checksum_val)
3535                 *checksum_val = checksum;
3536
3537         return status;
3538 }
3539
3540 /**
3541  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3542  * @hw: pointer to hardware structure
3543  *
3544  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3545  * checksum and updates the EEPROM and instructs the hardware to update
3546  * the flash.
3547  **/
3548 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3549 {
3550         s32 status;
3551         u16 checksum = 0;
3552
3553         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3554
3555         /* Read the first word from the EEPROM. If this times out or fails, do
3556          * not continue or we could be in for a very long wait while every
3557          * EEPROM read fails
3558          */
3559         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3560         if (status) {
3561                 DEBUGOUT("EEPROM read failed\n");
3562                 return status;
3563         }
3564
3565         status = ixgbe_calc_eeprom_checksum_X550(hw);
3566         if (status < 0)
3567                 return status;
3568
3569         checksum = (u16)(status & 0xffff);
3570
3571         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3572                                             checksum);
3573         if (status)
3574                 return status;
3575
3576         status = ixgbe_update_flash_X550(hw);
3577
3578         return status;
3579 }
3580
3581 /**
3582  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3583  *  @hw: pointer to hardware structure
3584  *
3585  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3586  **/
3587 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3588 {
3589         s32 status = IXGBE_SUCCESS;
3590         union ixgbe_hic_hdr2 buffer;
3591
3592         DEBUGFUNC("ixgbe_update_flash_X550");
3593
3594         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3595         buffer.req.buf_lenh = 0;
3596         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3597         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3598
3599         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3600                                               sizeof(buffer),
3601                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3602
3603         return status;
3604 }
3605
3606 /**
3607  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3608  *  @hw: pointer to hardware structure
3609  *
3610  *  Determines physical layer capabilities of the current configuration.
3611  **/
3612 u64 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3613 {
3614         u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3615         u16 ext_ability = 0;
3616
3617         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3618
3619         hw->phy.ops.identify(hw);
3620
3621         switch (hw->phy.type) {
3622         case ixgbe_phy_x550em_kr:
3623                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
3624                         if (hw->phy.nw_mng_if_sel &
3625                             IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
3626                                 physical_layer =
3627                                         IXGBE_PHYSICAL_LAYER_2500BASE_KX;
3628                                 break;
3629                         } else if (hw->device_id ==
3630                                    IXGBE_DEV_ID_X550EM_A_KR_L) {
3631                                 physical_layer =
3632                                         IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3633                                 break;
3634                         }
3635                 }
3636                 /* fall through */
3637         case ixgbe_phy_x550em_xfi:
3638                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3639                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3640                 break;
3641         case ixgbe_phy_x550em_kx4:
3642                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3643                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3644                 break;
3645         case ixgbe_phy_x550em_ext_t:
3646                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3647                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3648                                      &ext_ability);
3649                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3650                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3651                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3652                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3653                 break;
3654         case ixgbe_phy_fw:
3655                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_1GB_FULL)
3656                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3657                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_100_FULL)
3658                         physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
3659                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_10_FULL)
3660                         physical_layer |= IXGBE_PHYSICAL_LAYER_10BASE_T;
3661                 break;
3662         case ixgbe_phy_sgmii:
3663 #ifdef PREBOOT_SUPPORT
3664                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
3665                                  IXGBE_PHYSICAL_LAYER_100BASE_TX |
3666                                  IXGBE_PHYSICAL_LAYER_10BASE_T;
3667 #else
3668                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3669 #endif /* PREBOOT_SUPPORT */
3670                 break;
3671         case ixgbe_phy_ext_1g_t:
3672                 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3673                 break;
3674         default:
3675                 break;
3676         }
3677
3678         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3679                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3680
3681         return physical_layer;
3682 }
3683
3684 /**
3685  * ixgbe_get_bus_info_x550em - Set PCI bus info
3686  * @hw: pointer to hardware structure
3687  *
3688  * Sets bus link width and speed to unknown because X550em is
3689  * not a PCI device.
3690  **/
3691 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3692 {
3693
3694         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3695
3696         hw->bus.width = ixgbe_bus_width_unknown;
3697         hw->bus.speed = ixgbe_bus_speed_unknown;
3698
3699         hw->mac.ops.set_lan_id(hw);
3700
3701         return IXGBE_SUCCESS;
3702 }
3703
3704 /**
3705  * ixgbe_disable_rx_x550 - Disable RX unit
3706  * @hw: pointer to hardware structure
3707  *
3708  * Enables the Rx DMA unit for x550
3709  **/
3710 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3711 {
3712         u32 rxctrl, pfdtxgswc;
3713         s32 status;
3714         struct ixgbe_hic_disable_rxen fw_cmd;
3715
3716         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3717
3718         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3719         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3720                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3721                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3722                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3723                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3724                         hw->mac.set_lben = true;
3725                 } else {
3726                         hw->mac.set_lben = false;
3727                 }
3728
3729                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3730                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3731                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3732                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3733
3734                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3735                                         sizeof(struct ixgbe_hic_disable_rxen),
3736                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3737
3738                 /* If we fail - disable RX using register write */
3739                 if (status) {
3740                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3741                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3742                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3743                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3744                         }
3745                 }
3746         }
3747 }
3748
3749 /**
3750  * ixgbe_enter_lplu_x550em - Transition to low power states
3751  *  @hw: pointer to hardware structure
3752  *
3753  * Configures Low Power Link Up on transition to low power states
3754  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3755  * X557 PHY immediately prior to entering LPLU.
3756  **/
3757 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3758 {
3759         u16 an_10g_cntl_reg, autoneg_reg, speed;
3760         s32 status;
3761         ixgbe_link_speed lcd_speed;
3762         u32 save_autoneg;
3763         bool link_up;
3764
3765         /* SW LPLU not required on later HW revisions. */
3766         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3767             (IXGBE_FUSES0_REV_MASK &
3768              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3769                 return IXGBE_SUCCESS;
3770
3771         /* If blocked by MNG FW, then don't restart AN */
3772         if (ixgbe_check_reset_blocked(hw))
3773                 return IXGBE_SUCCESS;
3774
3775         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3776         if (status != IXGBE_SUCCESS)
3777                 return status;
3778
3779         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3780
3781         if (status != IXGBE_SUCCESS)
3782                 return status;
3783
3784         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3785          * disabled, then force link down by entering low power mode.
3786          */
3787         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3788             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3789                 return ixgbe_set_copper_phy_power(hw, FALSE);
3790
3791         /* Determine LCD */
3792         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3793
3794         if (status != IXGBE_SUCCESS)
3795                 return status;
3796
3797         /* If no valid LCD link speed, then force link down and exit. */
3798         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3799                 return ixgbe_set_copper_phy_power(hw, FALSE);
3800
3801         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3802                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3803                                       &speed);
3804
3805         if (status != IXGBE_SUCCESS)
3806                 return status;
3807
3808         /* If no link now, speed is invalid so take link down */
3809         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3810         if (status != IXGBE_SUCCESS)
3811                 return ixgbe_set_copper_phy_power(hw, false);
3812
3813         /* clear everything but the speed bits */
3814         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3815
3816         /* If current speed is already LCD, then exit. */
3817         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3818              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3819             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3820              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3821                 return status;
3822
3823         /* Clear AN completed indication */
3824         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3825                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3826                                       &autoneg_reg);
3827
3828         if (status != IXGBE_SUCCESS)
3829                 return status;
3830
3831         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3832                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3833                              &an_10g_cntl_reg);
3834
3835         if (status != IXGBE_SUCCESS)
3836                 return status;
3837
3838         status = hw->phy.ops.read_reg(hw,
3839                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3840                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3841                              &autoneg_reg);
3842
3843         if (status != IXGBE_SUCCESS)
3844                 return status;
3845
3846         save_autoneg = hw->phy.autoneg_advertised;
3847
3848         /* Setup link at least common link speed */
3849         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3850
3851         /* restore autoneg from before setting lplu speed */
3852         hw->phy.autoneg_advertised = save_autoneg;
3853
3854         return status;
3855 }
3856
3857 /**
3858  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3859  *  @hw: pointer to hardware structure
3860  *  @lcd_speed: pointer to lowest common link speed
3861  *
3862  * Determine lowest common link speed with link partner.
3863  **/
3864 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3865 {
3866         u16 an_lp_status;
3867         s32 status;
3868         u16 word = hw->eeprom.ctrl_word_3;
3869
3870         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3871
3872         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3873                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3874                                       &an_lp_status);
3875
3876         if (status != IXGBE_SUCCESS)
3877                 return status;
3878
3879         /* If link partner advertised 1G, return 1G */
3880         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3881                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3882                 return status;
3883         }
3884
3885         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3886         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3887             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3888                 return status;
3889
3890         /* Link partner not capable of lower speeds, return 10G */
3891         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3892         return status;
3893 }
3894
3895 /**
3896  *  ixgbe_setup_fc_X550em - Set up flow control
3897  *  @hw: pointer to hardware structure
3898  *
3899  *  Called at init time to set up flow control.
3900  **/
3901 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3902 {
3903         s32 ret_val = IXGBE_SUCCESS;
3904         u32 pause, asm_dir, reg_val;
3905
3906         DEBUGFUNC("ixgbe_setup_fc_X550em");
3907
3908         /* Validate the requested mode */
3909         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3910                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3911                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3912                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3913                 goto out;
3914         }
3915
3916         /* 10gig parts do not have a word in the EEPROM to determine the
3917          * default flow control setting, so we explicitly set it to full.
3918          */
3919         if (hw->fc.requested_mode == ixgbe_fc_default)
3920                 hw->fc.requested_mode = ixgbe_fc_full;
3921
3922         /* Determine PAUSE and ASM_DIR bits. */
3923         switch (hw->fc.requested_mode) {
3924         case ixgbe_fc_none:
3925                 pause = 0;
3926                 asm_dir = 0;
3927                 break;
3928         case ixgbe_fc_tx_pause:
3929                 pause = 0;
3930                 asm_dir = 1;
3931                 break;
3932         case ixgbe_fc_rx_pause:
3933                 /* Rx Flow control is enabled and Tx Flow control is
3934                  * disabled by software override. Since there really
3935                  * isn't a way to advertise that we are capable of RX
3936                  * Pause ONLY, we will advertise that we support both
3937                  * symmetric and asymmetric Rx PAUSE, as such we fall
3938                  * through to the fc_full statement.  Later, we will
3939                  * disable the adapter's ability to send PAUSE frames.
3940                  */
3941         case ixgbe_fc_full:
3942                 pause = 1;
3943                 asm_dir = 1;
3944                 break;
3945         default:
3946                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3947                         "Flow control param set incorrectly\n");
3948                 ret_val = IXGBE_ERR_CONFIG;
3949                 goto out;
3950         }
3951
3952         switch (hw->device_id) {
3953         case IXGBE_DEV_ID_X550EM_X_KR:
3954         case IXGBE_DEV_ID_X550EM_A_KR:
3955         case IXGBE_DEV_ID_X550EM_A_KR_L:
3956                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3957                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3958                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3959                 if (ret_val != IXGBE_SUCCESS)
3960                         goto out;
3961                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3962                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3963                 if (pause)
3964                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3965                 if (asm_dir)
3966                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3967                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3968                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3969                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3970
3971                 /* This device does not fully support AN. */
3972                 hw->fc.disable_fc_autoneg = true;
3973                 break;
3974         case IXGBE_DEV_ID_X550EM_X_XFI:
3975                 hw->fc.disable_fc_autoneg = true;
3976                 break;
3977         default:
3978                 break;
3979         }
3980
3981 out:
3982         return ret_val;
3983 }
3984
3985 /**
3986  *  ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
3987  *  @hw: pointer to hardware structure
3988  *
3989  *  Enable flow control according to IEEE clause 37.
3990  **/
3991 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
3992 {
3993         u32 link_s1, lp_an_page_low, an_cntl_1;
3994         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3995         ixgbe_link_speed speed;
3996         bool link_up;
3997
3998         /* AN should have completed when the cable was plugged in.
3999          * Look for reasons to bail out.  Bail out if:
4000          * - FC autoneg is disabled, or if
4001          * - link is not up.
4002          */
4003         if (hw->fc.disable_fc_autoneg) {
4004                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4005                              "Flow control autoneg is disabled");
4006                 goto out;
4007         }
4008
4009         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4010         if (!link_up) {
4011                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4012                 goto out;
4013         }
4014
4015         /* Check at auto-negotiation has completed */
4016         status = hw->mac.ops.read_iosf_sb_reg(hw,
4017                                         IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4018                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4019
4020         if (status != IXGBE_SUCCESS ||
4021             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4022                 DEBUGOUT("Auto-Negotiation did not complete\n");
4023                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4024                 goto out;
4025         }
4026
4027         /* Read the 10g AN autoc and LP ability registers and resolve
4028          * local flow control settings accordingly
4029          */
4030         status = hw->mac.ops.read_iosf_sb_reg(hw,
4031                                 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4032                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4033
4034         if (status != IXGBE_SUCCESS) {
4035                 DEBUGOUT("Auto-Negotiation did not complete\n");
4036                 goto out;
4037         }
4038
4039         status = hw->mac.ops.read_iosf_sb_reg(hw,
4040                                 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4041                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4042
4043         if (status != IXGBE_SUCCESS) {
4044                 DEBUGOUT("Auto-Negotiation did not complete\n");
4045                 goto out;
4046         }
4047
4048         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4049                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4050                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4051                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4052                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4053
4054 out:
4055         if (status == IXGBE_SUCCESS) {
4056                 hw->fc.fc_was_autonegged = true;
4057         } else {
4058                 hw->fc.fc_was_autonegged = false;
4059                 hw->fc.current_mode = hw->fc.requested_mode;
4060         }
4061 }
4062
4063 /**
4064  *  ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4065  *  @hw: pointer to hardware structure
4066  *
4067  **/
4068 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4069 {
4070         hw->fc.fc_was_autonegged = false;
4071         hw->fc.current_mode = hw->fc.requested_mode;
4072 }
4073
4074 /**
4075  *  ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4076  *  @hw: pointer to hardware structure
4077  *
4078  *  Enable flow control according to IEEE clause 37.
4079  **/
4080 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4081 {
4082         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4083         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
4084         ixgbe_link_speed speed;
4085         bool link_up;
4086
4087         /* AN should have completed when the cable was plugged in.
4088          * Look for reasons to bail out.  Bail out if:
4089          * - FC autoneg is disabled, or if
4090          * - link is not up.
4091          */
4092         if (hw->fc.disable_fc_autoneg) {
4093                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4094                              "Flow control autoneg is disabled");
4095                 goto out;
4096         }
4097
4098         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4099         if (!link_up) {
4100                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4101                 goto out;
4102         }
4103
4104         /* Check if auto-negotiation has completed */
4105         status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
4106         if (status != IXGBE_SUCCESS ||
4107             !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
4108                 DEBUGOUT("Auto-Negotiation did not complete\n");
4109                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4110                 goto out;
4111         }
4112
4113         /* Negotiate the flow control */
4114         status = ixgbe_negotiate_fc(hw, info[0], info[0],
4115                                     FW_PHY_ACT_GET_LINK_INFO_FC_RX,
4116                                     FW_PHY_ACT_GET_LINK_INFO_FC_TX,
4117                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
4118                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
4119
4120 out:
4121         if (status == IXGBE_SUCCESS) {
4122                 hw->fc.fc_was_autonegged = true;
4123         } else {
4124                 hw->fc.fc_was_autonegged = false;
4125                 hw->fc.current_mode = hw->fc.requested_mode;
4126         }
4127 }
4128
4129 /**
4130  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4131  *  @hw: pointer to hardware structure
4132  *
4133  *  Called at init time to set up flow control.
4134  **/
4135 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4136 {
4137         s32 status = IXGBE_SUCCESS;
4138         u32 an_cntl = 0;
4139
4140         DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4141
4142         /* Validate the requested mode */
4143         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4144                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4145                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4146                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4147         }
4148
4149         if (hw->fc.requested_mode == ixgbe_fc_default)
4150                 hw->fc.requested_mode = ixgbe_fc_full;
4151
4152         /* Set up the 1G and 10G flow control advertisement registers so the
4153          * HW will be able to do FC autoneg once the cable is plugged in.  If
4154          * we link at 10G, the 1G advertisement is harmless and vice versa.
4155          */
4156         status = hw->mac.ops.read_iosf_sb_reg(hw,
4157                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4158                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4159
4160         if (status != IXGBE_SUCCESS) {
4161                 DEBUGOUT("Auto-Negotiation did not complete\n");
4162                 return status;
4163         }
4164
4165         /* The possible values of fc.requested_mode are:
4166          * 0: Flow control is completely disabled
4167          * 1: Rx flow control is enabled (we can receive pause frames,
4168          *    but not send pause frames).
4169          * 2: Tx flow control is enabled (we can send pause frames but
4170          *    we do not support receiving pause frames).
4171          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4172          * other: Invalid.
4173          */
4174         switch (hw->fc.requested_mode) {
4175         case ixgbe_fc_none:
4176                 /* Flow control completely disabled by software override. */
4177                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4178                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4179                 break;
4180         case ixgbe_fc_tx_pause:
4181                 /* Tx Flow control is enabled, and Rx Flow control is
4182                  * disabled by software override.
4183                  */
4184                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4185                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4186                 break;
4187         case ixgbe_fc_rx_pause:
4188                 /* Rx Flow control is enabled and Tx Flow control is
4189                  * disabled by software override. Since there really
4190                  * isn't a way to advertise that we are capable of RX
4191                  * Pause ONLY, we will advertise that we support both
4192                  * symmetric and asymmetric Rx PAUSE, as such we fall
4193                  * through to the fc_full statement.  Later, we will
4194                  * disable the adapter's ability to send PAUSE frames.
4195                  */
4196         case ixgbe_fc_full:
4197                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4198                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4199                            IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4200                 break;
4201         default:
4202                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4203                               "Flow control param set incorrectly\n");
4204                 return IXGBE_ERR_CONFIG;
4205         }
4206
4207         status = hw->mac.ops.write_iosf_sb_reg(hw,
4208                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4209                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4210
4211         /* Restart auto-negotiation. */
4212         status = ixgbe_restart_an_internal_phy_x550em(hw);
4213
4214         return status;
4215 }
4216
4217 /**
4218  * ixgbe_set_mux - Set mux for port 1 access with CS4227
4219  * @hw: pointer to hardware structure
4220  * @state: set mux if 1, clear if 0
4221  */
4222 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4223 {
4224         u32 esdp;
4225
4226         if (!hw->bus.lan_id)
4227                 return;
4228         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4229         if (state)
4230                 esdp |= IXGBE_ESDP_SDP1;
4231         else
4232                 esdp &= ~IXGBE_ESDP_SDP1;
4233         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4234         IXGBE_WRITE_FLUSH(hw);
4235 }
4236
4237 /**
4238  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4239  *  @hw: pointer to hardware structure
4240  *  @mask: Mask to specify which semaphore to acquire
4241  *
4242  *  Acquires the SWFW semaphore and sets the I2C MUX
4243  **/
4244 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4245 {
4246         s32 status;
4247
4248         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4249
4250         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4251         if (status)
4252                 return status;
4253
4254         if (mask & IXGBE_GSSR_I2C_MASK)
4255                 ixgbe_set_mux(hw, 1);
4256
4257         return IXGBE_SUCCESS;
4258 }
4259
4260 /**
4261  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4262  *  @hw: pointer to hardware structure
4263  *  @mask: Mask to specify which semaphore to release
4264  *
4265  *  Releases the SWFW semaphore and sets the I2C MUX
4266  **/
4267 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4268 {
4269         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4270
4271         if (mask & IXGBE_GSSR_I2C_MASK)
4272                 ixgbe_set_mux(hw, 0);
4273
4274         ixgbe_release_swfw_sync_X540(hw, mask);
4275 }
4276
4277 /**
4278  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4279  *  @hw: pointer to hardware structure
4280  *  @mask: Mask to specify which semaphore to acquire
4281  *
4282  *  Acquires the SWFW semaphore and get the shared phy token as needed
4283  */
4284 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4285 {
4286         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4287         int retries = FW_PHY_TOKEN_RETRIES;
4288         s32 status = IXGBE_SUCCESS;
4289
4290         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4291
4292         while (--retries) {
4293                 status = IXGBE_SUCCESS;
4294                 if (hmask)
4295                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4296                 if (status) {
4297                         DEBUGOUT1("Could not acquire SWFW semaphore, Status = %d\n",
4298                                   status);
4299                         return status;
4300                 }
4301                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4302                         return IXGBE_SUCCESS;
4303
4304                 status = ixgbe_get_phy_token(hw);
4305                 if (status == IXGBE_ERR_TOKEN_RETRY)
4306                         DEBUGOUT1("Could not acquire PHY token, Status = %d\n",
4307                                   status);
4308
4309                 if (status == IXGBE_SUCCESS)
4310                         return IXGBE_SUCCESS;
4311
4312                 if (hmask)
4313                         ixgbe_release_swfw_sync_X540(hw, hmask);
4314
4315                 if (status != IXGBE_ERR_TOKEN_RETRY) {
4316                         DEBUGOUT1("Unable to retry acquiring the PHY token, Status = %d\n",
4317                                   status);
4318                         return status;
4319                 }
4320         }
4321
4322         DEBUGOUT1("Semaphore acquisition retries failed!: PHY ID = 0x%08X\n",
4323                   hw->phy.id);
4324         return status;
4325 }
4326
4327 /**
4328  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4329  *  @hw: pointer to hardware structure
4330  *  @mask: Mask to specify which semaphore to release
4331  *
4332  *  Releases the SWFW semaphore and puts the shared phy token as needed
4333  */
4334 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4335 {
4336         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4337
4338         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4339
4340         if (mask & IXGBE_GSSR_TOKEN_SM)
4341                 ixgbe_put_phy_token(hw);
4342
4343         if (hmask)
4344                 ixgbe_release_swfw_sync_X540(hw, hmask);
4345 }
4346
4347 /**
4348  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4349  *  @hw: pointer to hardware structure
4350  *  @reg_addr: 32 bit address of PHY register to read
4351  *  @device_type: 5 bit device type
4352  *  @phy_data: Pointer to read data from PHY register
4353  *
4354  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4355  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4356  *  instances.
4357  **/
4358 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4359                                u32 device_type, u16 *phy_data)
4360 {
4361         s32 status;
4362         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4363
4364         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4365
4366         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4367                 return IXGBE_ERR_SWFW_SYNC;
4368
4369         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4370
4371         hw->mac.ops.release_swfw_sync(hw, mask);
4372
4373         return status;
4374 }
4375
4376 /**
4377  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4378  *  @hw: pointer to hardware structure
4379  *  @reg_addr: 32 bit PHY register to write
4380  *  @device_type: 5 bit device type
4381  *  @phy_data: Data to write to the PHY register
4382  *
4383  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4384  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4385  **/
4386 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4387                                 u32 device_type, u16 phy_data)
4388 {
4389         s32 status;
4390         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4391
4392         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4393
4394         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4395                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4396                                                  phy_data);
4397                 hw->mac.ops.release_swfw_sync(hw, mask);
4398         } else {
4399                 status = IXGBE_ERR_SWFW_SYNC;
4400         }
4401
4402         return status;
4403 }
4404
4405 /**
4406  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4407  * @hw: pointer to hardware structure
4408  *
4409  * Handle external Base T PHY interrupt. If high temperature
4410  * failure alarm then return error, else if link status change
4411  * then setup internal/external PHY link
4412  *
4413  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4414  * failure alarm, else return PHY access status.
4415  */
4416 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4417 {
4418         bool lsc;
4419         u32 status;
4420
4421         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4422
4423         if (status != IXGBE_SUCCESS)
4424                 return status;
4425
4426         if (lsc)
4427                 return ixgbe_setup_internal_phy(hw);
4428
4429         return IXGBE_SUCCESS;
4430 }
4431
4432 /**
4433  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4434  * @hw: pointer to hardware structure
4435  * @speed: new link speed
4436  * @autoneg_wait_to_complete: true when waiting for completion is needed
4437  *
4438  * Setup internal/external PHY link speed based on link speed, then set
4439  * external PHY auto advertised link speed.
4440  *
4441  * Returns error status for any failure
4442  **/
4443 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4444                                   ixgbe_link_speed speed,
4445                                   bool autoneg_wait_to_complete)
4446 {
4447         s32 status;
4448         ixgbe_link_speed force_speed;
4449         u32 i;
4450         bool link_up = false;
4451
4452         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4453
4454         /* Setup internal/external PHY link speed to iXFI (10G), unless
4455          * only 1G is auto advertised then setup KX link.
4456          */
4457         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4458                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4459         else
4460                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4461
4462         /* If X552 and internal link mode is XFI, then setup XFI internal link.
4463          */
4464         if (hw->mac.type == ixgbe_mac_X550EM_x &&
4465             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4466                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4467
4468                 if (status != IXGBE_SUCCESS)
4469                         return status;
4470
4471                 /* Wait for the controller to acquire link */
4472                 for (i = 0; i < 10; i++) {
4473                         msec_delay(100);
4474
4475                         status = ixgbe_check_link(hw, &force_speed, &link_up,
4476                                                   false);
4477                         if (status != IXGBE_SUCCESS)
4478                                 return status;
4479
4480                         if (link_up)
4481                                 break;
4482                 }
4483         }
4484
4485         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4486 }
4487
4488 /**
4489  * ixgbe_check_link_t_X550em - Determine link and speed status
4490  * @hw: pointer to hardware structure
4491  * @speed: pointer to link speed
4492  * @link_up: true when link is up
4493  * @link_up_wait_to_complete: bool used to wait for link up or not
4494  *
4495  * Check that both the MAC and X557 external PHY have link.
4496  **/
4497 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4498                               bool *link_up, bool link_up_wait_to_complete)
4499 {
4500         u32 status;
4501         u16 i, autoneg_status = 0;
4502
4503         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4504                 return IXGBE_ERR_CONFIG;
4505
4506         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4507                                               link_up_wait_to_complete);
4508
4509         /* If check link fails or MAC link is not up, then return */
4510         if (status != IXGBE_SUCCESS || !(*link_up))
4511                 return status;
4512
4513         /* MAC link is up, so check external PHY link.
4514          * X557 PHY. Link status is latching low, and can only be used to detect
4515          * link drop, and not the current status of the link without performing
4516          * back-to-back reads.
4517          */
4518         for (i = 0; i < 2; i++) {
4519                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4520                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4521                                               &autoneg_status);
4522
4523                 if (status != IXGBE_SUCCESS)
4524                         return status;
4525         }
4526
4527         /* If external PHY link is not up, then indicate link not up */
4528         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4529                 *link_up = false;
4530
4531         return IXGBE_SUCCESS;
4532 }
4533
4534 /**
4535  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4536  *  @hw: pointer to hardware structure
4537  **/
4538 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4539 {
4540         s32 status;
4541
4542         status = ixgbe_reset_phy_generic(hw);
4543
4544         if (status != IXGBE_SUCCESS)
4545                 return status;
4546
4547         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4548         return ixgbe_enable_lasi_ext_t_x550em(hw);
4549 }
4550
4551 /**
4552  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4553  *  @hw: pointer to hardware structure
4554  *  @led_idx: led number to turn on
4555  **/
4556 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4557 {
4558         u16 phy_data;
4559
4560         DEBUGFUNC("ixgbe_led_on_t_X550em");
4561
4562         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4563                 return IXGBE_ERR_PARAM;
4564
4565         /* To turn on the LED, set mode to ON. */
4566         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4567                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4568         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4569         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4570                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4571
4572         /* Some designs have the LEDs wired to the MAC */
4573         return ixgbe_led_on_generic(hw, led_idx);
4574 }
4575
4576 /**
4577  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4578  *  @hw: pointer to hardware structure
4579  *  @led_idx: led number to turn off
4580  **/
4581 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4582 {
4583         u16 phy_data;
4584
4585         DEBUGFUNC("ixgbe_led_off_t_X550em");
4586
4587         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4588                 return IXGBE_ERR_PARAM;
4589
4590         /* To turn on the LED, set mode to ON. */
4591         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4592                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4593         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4594         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4595                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4596
4597         /* Some designs have the LEDs wired to the MAC */
4598         return ixgbe_led_off_generic(hw, led_idx);
4599 }
4600
4601 /**
4602  *  ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
4603  *  @hw: pointer to the HW structure
4604  *  @maj: driver version major number
4605  *  @min: driver version minor number
4606  *  @build: driver version build number
4607  *  @sub: driver version sub build number
4608  *  @len: length of driver_ver string
4609  *  @driver_ver: driver string
4610  *
4611  *  Sends driver version number to firmware through the manageability
4612  *  block.  On success return IXGBE_SUCCESS
4613  *  else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4614  *  semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4615  **/
4616 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
4617                               u8 build, u8 sub, u16 len, const char *driver_ver)
4618 {
4619         struct ixgbe_hic_drv_info2 fw_cmd;
4620         s32 ret_val = IXGBE_SUCCESS;
4621         int i;
4622
4623         DEBUGFUNC("ixgbe_set_fw_drv_ver_x550");
4624
4625         if ((len == 0) || (driver_ver == NULL) ||
4626            (len > sizeof(fw_cmd.driver_string)))
4627                 return IXGBE_ERR_INVALID_ARGUMENT;
4628
4629         fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4630         fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
4631         fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4632         fw_cmd.port_num = (u8)hw->bus.func;
4633         fw_cmd.ver_maj = maj;
4634         fw_cmd.ver_min = min;
4635         fw_cmd.ver_build = build;
4636         fw_cmd.ver_sub = sub;
4637         fw_cmd.hdr.checksum = 0;
4638         memcpy(fw_cmd.driver_string, driver_ver, len);
4639         fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4640                                 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4641
4642         for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4643                 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4644                                                        sizeof(fw_cmd),
4645                                                        IXGBE_HI_COMMAND_TIMEOUT,
4646                                                        true);
4647                 if (ret_val != IXGBE_SUCCESS)
4648                         continue;
4649
4650                 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4651                     FW_CEM_RESP_STATUS_SUCCESS)
4652                         ret_val = IXGBE_SUCCESS;
4653                 else
4654                         ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4655
4656                 break;
4657         }
4658
4659         return ret_val;
4660 }
4661
4662 /**
4663  * ixgbe_fw_recovery_mode_X550 - Check FW NVM recovery mode
4664  * @hw: pointer t hardware structure
4665  *
4666  * Returns true if in FW NVM recovery mode.
4667  **/
4668 bool ixgbe_fw_recovery_mode_X550(struct ixgbe_hw *hw)
4669 {
4670         u32 fwsm;
4671
4672         fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
4673
4674         return !!(fwsm & IXGBE_FWSM_FW_NVM_RECOVERY_MODE);
4675 }