drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42
  43 /**
  44  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  45  *  @hw: pointer to hardware structure
  46  *
  47  *  Initialize the function pointers and assign the MAC type for X550.
  48  *  Does not touch the hardware.
  49  **/
  50 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  51 {
  52         struct ixgbe_mac_info *mac = &hw->mac;
  53         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  54         s32 ret_val;
  55
  56         DEBUGFUNC("ixgbe_init_ops_X550");
  57
  58         ret_val = ixgbe_init_ops_X540(hw);
  59         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  60         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  61         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  62         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  63         mac->ops.set_source_address_pruning =
  64                         ixgbe_set_source_address_pruning_X550;
  65         mac->ops.set_ethertype_anti_spoofing =
  66                         ixgbe_set_ethertype_anti_spoofing_X550;
  67
  68         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  69         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  70         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  71         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  72         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  73         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  74         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  75         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  76         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  77
  78         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  79         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  80         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  81         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  82         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  83         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
  84                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  85                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  86         }
  87         return ret_val;
  88 }
  89
  90 /**
  91  * ixgbe_read_cs4227 - Read CS4227 register
  92  * @hw: pointer to hardware structure
  93  * @reg: register number to write
  94  * @value: pointer to receive value read
  95  *
  96  * Returns status code
  97  **/
  98 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  99 {
 100         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 101 }
 102
 103 /**
 104  * ixgbe_write_cs4227 - Write CS4227 register
 105  * @hw: pointer to hardware structure
 106  * @reg: register number to write
 107  * @value: value to write to register
 108  *
 109  * Returns status code
 110  **/
 111 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 112 {
 113         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 114 }
 115
 116 /**
 117  * ixgbe_read_pe - Read register from port expander
 118  * @hw: pointer to hardware structure
 119  * @reg: register number to read
 120  * @value: pointer to receive read value
 121  *
 122  * Returns status code
 123  **/
 124 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 125 {
 126         s32 status;
 127
 128         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 129         if (status != IXGBE_SUCCESS)
 130                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 131                               "port expander access failed with %d\n", status);
 132         return status;
 133 }
 134
 135 /**
 136  * ixgbe_write_pe - Write register to port expander
 137  * @hw: pointer to hardware structure
 138  * @reg: register number to write
 139  * @value: value to write
 140  *
 141  * Returns status code
 142  **/
 143 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 144 {
 145         s32 status;
 146
 147         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 148         if (status != IXGBE_SUCCESS)
 149                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 150                               "port expander access failed with %d\n", status);
 151         return status;
 152 }
 153
 154 /**
 155  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 156  * @hw: pointer to hardware structure
 157  *
 158  * This function assumes that the caller has acquired the proper semaphore.
 159  * Returns error code
 160  **/
 161 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 162 {
 163         s32 status;
 164         u32 retry;
 165         u16 value;
 166         u8 reg;
 167
 168         /* Trigger hard reset. */
 169         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 170         if (status != IXGBE_SUCCESS)
 171                 return status;
 172         reg |= IXGBE_PE_BIT1;
 173         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 174         if (status != IXGBE_SUCCESS)
 175                 return status;
 176
 177         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 178         if (status != IXGBE_SUCCESS)
 179                 return status;
 180         reg &= ~IXGBE_PE_BIT1;
 181         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 182         if (status != IXGBE_SUCCESS)
 183                 return status;
 184
 185         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 186         if (status != IXGBE_SUCCESS)
 187                 return status;
 188         reg &= ~IXGBE_PE_BIT1;
 189         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 190         if (status != IXGBE_SUCCESS)
 191                 return status;
 192
 193         usec_delay(IXGBE_CS4227_RESET_HOLD);
 194
 195         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 196         if (status != IXGBE_SUCCESS)
 197                 return status;
 198         reg |= IXGBE_PE_BIT1;
 199         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 200         if (status != IXGBE_SUCCESS)
 201                 return status;
 202
 203         /* Wait for the reset to complete. */
 204         msec_delay(IXGBE_CS4227_RESET_DELAY);
 205         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 206                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 207                                            &value);
 208                 if (status == IXGBE_SUCCESS &&
 209                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 210                         break;
 211                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 212         }
 213         if (retry == IXGBE_CS4227_RETRIES) {
 214                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 215                         "CS4227 reset did not complete.");
 216                 return IXGBE_ERR_PHY;
 217         }
 218
 219         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 220         if (status != IXGBE_SUCCESS ||
 221             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 222                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 223                         "CS4227 EEPROM did not load successfully.");
 224                 return IXGBE_ERR_PHY;
 225         }
 226
 227         return IXGBE_SUCCESS;
 228 }
 229
 230 /**
 231  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 232  * @hw: pointer to hardware structure
 233  **/
 234 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 235 {
 236         s32 status = IXGBE_SUCCESS;
 237         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 238         u16 value = 0;
 239         u8 retry;
 240
 241         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 242                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 243                 if (status != IXGBE_SUCCESS) {
 244                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 245                                 "semaphore failed with %d", status);
 246                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 247                         continue;
 248                 }
 249
 250                 /* Get status of reset flow. */
 251                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 252
 253                 if (status == IXGBE_SUCCESS &&
 254                     value == IXGBE_CS4227_RESET_COMPLETE)
 255                         goto out;
 256
 257                 if (status != IXGBE_SUCCESS ||
 258                     value != IXGBE_CS4227_RESET_PENDING)
 259                         break;
 260
 261                 /* Reset is pending. Wait and check again. */
 262                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 263                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 264         }
 265
 266         /* If still pending, assume other instance failed. */
 267         if (retry == IXGBE_CS4227_RETRIES) {
 268                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 269                 if (status != IXGBE_SUCCESS) {
 270                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 271                                       "semaphore failed with %d", status);
 272                         return;
 273                 }
 274         }
 275
 276         /* Reset the CS4227. */
 277         status = ixgbe_reset_cs4227(hw);
 278         if (status != IXGBE_SUCCESS) {
 279                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 280                         "CS4227 reset failed: %d", status);
 281                 goto out;
 282         }
 283
 284         /* Reset takes so long, temporarily release semaphore in case the
 285          * other driver instance is waiting for the reset indication.
 286          */
 287         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 288                            IXGBE_CS4227_RESET_PENDING);
 289         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 290         msec_delay(10);
 291         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 292         if (status != IXGBE_SUCCESS) {
 293                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 294                         "semaphore failed with %d", status);
 295                 return;
 296         }
 297
 298         /* Record completion for next time. */
 299         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 300                 IXGBE_CS4227_RESET_COMPLETE);
 301
 302 out:
 303         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 304         msec_delay(hw->eeprom.semaphore_delay);
 305 }
 306
 307 /**
 308  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 309  * @hw: pointer to hardware structure
 310  **/
 311 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 312 {
 313         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 314
 315         if (hw->bus.lan_id) {
 316                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 317                 esdp |= IXGBE_ESDP_SDP1_DIR;
 318         }
 319         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 320         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 321         IXGBE_WRITE_FLUSH(hw);
 322 }
 323
 324 /**
 325  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 326  * @hw: pointer to hardware structure
 327  *
 328  * Returns error code
 329  */
 330 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 331 {
 332         switch (hw->device_id) {
 333         case IXGBE_DEV_ID_X550EM_X_SFP:
 334                 /* set up for CS4227 usage */
 335                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 336                 ixgbe_setup_mux_ctl(hw);
 337                 ixgbe_check_cs4227(hw);
 338
 339                 return ixgbe_identify_module_generic(hw);
 340                 break;
 341         case IXGBE_DEV_ID_X550EM_X_KX4:
 342                 hw->phy.type = ixgbe_phy_x550em_kx4;
 343                 break;
 344         case IXGBE_DEV_ID_X550EM_X_KR:
 345                 hw->phy.type = ixgbe_phy_x550em_kr;
 346                 break;
 347         case IXGBE_DEV_ID_X550EM_X_1G_T:
 348         case IXGBE_DEV_ID_X550EM_X_10G_T:
 349                 return ixgbe_identify_phy_generic(hw);
 350         default:
 351                 break;
 352         }
 353         return IXGBE_SUCCESS;
 354 }
 355
 356 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 357                                      u32 device_type, u16 *phy_data)
 358 {
 359         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 360         return IXGBE_NOT_IMPLEMENTED;
 361 }
 362
 363 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 364                                       u32 device_type, u16 phy_data)
 365 {
 366         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 367         return IXGBE_NOT_IMPLEMENTED;
 368 }
 369
 370 /**
 371 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 372 *  @hw: pointer to hardware structure
 373 *
 374 *  Initialize the function pointers and for MAC type X550EM.
 375 *  Does not touch the hardware.
 376 **/
 377 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 378 {
 379         struct ixgbe_mac_info *mac = &hw->mac;
 380         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 381         struct ixgbe_phy_info *phy = &hw->phy;
 382         s32 ret_val;
 383
 384         DEBUGFUNC("ixgbe_init_ops_X550EM");
 385
 386         /* Similar to X550 so start there. */
 387         ret_val = ixgbe_init_ops_X550(hw);
 388
 389         /* Since this function eventually calls
 390          * ixgbe_init_ops_540 by design, we are setting
 391          * the pointers to NULL explicitly here to overwrite
 392          * the values being set in the x540 function.
 393          */
 394         /* Thermal sensor not supported in x550EM */
 395         mac->ops.get_thermal_sensor_data = NULL;
 396         mac->ops.init_thermal_sensor_thresh = NULL;
 397         mac->thermal_sensor_enabled = false;
 398
 399         /* FCOE not supported in x550EM */
 400         mac->ops.get_san_mac_addr = NULL;
 401         mac->ops.set_san_mac_addr = NULL;
 402         mac->ops.get_wwn_prefix = NULL;
 403         mac->ops.get_fcoe_boot_status = NULL;
 404
 405         /* IPsec not supported in x550EM */
 406         mac->ops.disable_sec_rx_path = NULL;
 407         mac->ops.enable_sec_rx_path = NULL;
 408
 409         /* AUTOC register is not present in x550EM. */
 410         mac->ops.prot_autoc_read = NULL;
 411         mac->ops.prot_autoc_write = NULL;
 412
 413         /* X550EM bus type is internal*/
 414         hw->bus.type = ixgbe_bus_type_internal;
 415         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 416
 417         if (hw->mac.type == ixgbe_mac_X550EM_x) {
 418                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 419                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 420                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 421                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 422         }
 423
 424         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 425         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 426         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 427         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 428         mac->ops.get_supported_physical_layer =
 429                                     ixgbe_get_supported_physical_layer_X550em;
 430
 431         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 432                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 433         else
 434                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 435
 436
 437         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
 438                 mac->ops.setup_eee = NULL;
 439
 440         /* PHY */
 441         phy->ops.init = ixgbe_init_phy_ops_X550em;
 442         phy->ops.identify = ixgbe_identify_phy_x550em;
 443         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 444                 phy->ops.set_phy_power = NULL;
 445
 446
 447         /* EEPROM */
 448         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 449         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 450         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 451         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 452         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 453         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 454         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 455         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 456
 457         return ret_val;
 458 }
 459
 460 /**
 461  *  ixgbe_dmac_config_X550
 462  *  @hw: pointer to hardware structure
 463  *
 464  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 465  *  When disabling dmac, dmac enable dmac bit is cleared.
 466  **/
 467 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 468 {
 469         u32 reg, high_pri_tc;
 470
 471         DEBUGFUNC("ixgbe_dmac_config_X550");
 472
 473         /* Disable DMA coalescing before configuring */
 474         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 475         reg &= ~IXGBE_DMACR_DMAC_EN;
 476         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 477
 478         /* Disable DMA Coalescing if the watchdog timer is 0 */
 479         if (!hw->mac.dmac_config.watchdog_timer)
 480                 goto out;
 481
 482         ixgbe_dmac_config_tcs_X550(hw);
 483
 484         /* Configure DMA Coalescing Control Register */
 485         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 486
 487         /* Set the watchdog timer in units of 40.96 usec */
 488         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 489         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 490
 491         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 492         /* If fcoe is enabled, set high priority traffic class */
 493         if (hw->mac.dmac_config.fcoe_en) {
 494                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 495                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 496                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 497         }
 498         reg |= IXGBE_DMACR_EN_MNG_IND;
 499
 500         /* Enable DMA coalescing after configuration */
 501         reg |= IXGBE_DMACR_DMAC_EN;
 502         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 503
 504 out:
 505         return IXGBE_SUCCESS;
 506 }
 507
 508 /**
 509  *  ixgbe_dmac_config_tcs_X550
 510  *  @hw: pointer to hardware structure
 511  *
 512  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 513  *  be cleared before configuring.
 514  **/
 515 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 516 {
 517         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 518
 519         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 520
 521         /* Configure DMA coalescing enabled */
 522         switch (hw->mac.dmac_config.link_speed) {
 523         case IXGBE_LINK_SPEED_100_FULL:
 524                 pb_headroom = IXGBE_DMACRXT_100M;
 525                 break;
 526         case IXGBE_LINK_SPEED_1GB_FULL:
 527                 pb_headroom = IXGBE_DMACRXT_1G;
 528                 break;
 529         default:
 530                 pb_headroom = IXGBE_DMACRXT_10G;
 531                 break;
 532         }
 533
 534         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 535                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 536
 537         /* Set the per Rx packet buffer receive threshold */
 538         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 539                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 540                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 541
 542                 if (tc < hw->mac.dmac_config.num_tcs) {
 543                         /* Get Rx PB size */
 544                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 545                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 546                                 IXGBE_RXPBSIZE_SHIFT;
 547
 548                         /* Calculate receive buffer threshold in kilobytes */
 549                         if (rx_pb_size > pb_headroom)
 550                                 rx_pb_size = rx_pb_size - pb_headroom;
 551                         else
 552                                 rx_pb_size = 0;
 553
 554                         /* Minimum of MFS shall be set for DMCTH */
 555                         reg |= (rx_pb_size > maxframe_size_kb) ?
 556                                 rx_pb_size : maxframe_size_kb;
 557                 }
 558                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 559         }
 560         return IXGBE_SUCCESS;
 561 }
 562
 563 /**
 564  *  ixgbe_dmac_update_tcs_X550
 565  *  @hw: pointer to hardware structure
 566  *
 567  *  Disables dmac, updates per TC settings, and then enables dmac.
 568  **/
 569 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 570 {
 571         u32 reg;
 572
 573         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 574
 575         /* Disable DMA coalescing before configuring */
 576         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 577         reg &= ~IXGBE_DMACR_DMAC_EN;
 578         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 579
 580         ixgbe_dmac_config_tcs_X550(hw);
 581
 582         /* Enable DMA coalescing after configuration */
 583         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 584         reg |= IXGBE_DMACR_DMAC_EN;
 585         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 586
 587         return IXGBE_SUCCESS;
 588 }
 589
 590 /**
 591  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 592  *  @hw: pointer to hardware structure
 593  *
 594  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 595  *  ixgbe_hw struct in order to set up EEPROM access.
 596  **/
 597 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 598 {
 599         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 600         u32 eec;
 601         u16 eeprom_size;
 602
 603         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 604
 605         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 606                 eeprom->semaphore_delay = 10;
 607                 eeprom->type = ixgbe_flash;
 608
 609                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 610                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 611                                     IXGBE_EEC_SIZE_SHIFT);
 612                 eeprom->word_size = 1 << (eeprom_size +
 613                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 614
 615                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 616                           eeprom->type, eeprom->word_size);
 617         }
 618
 619         return IXGBE_SUCCESS;
 620 }
 621
 622 /**
 623  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 624  *  @hw: pointer to the HW structure
 625  *  @enable_eee: boolean flag to enable EEE
 626  *
 627  *  Enable/disable EEE based on enable_eee flag.
 628  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 629  *  are modified.
 630  *
 631  **/
 632 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 633 {
 634         u32 eeer;
 635         u16 autoneg_eee_reg;
 636         u32 link_reg;
 637         s32 status;
 638         u32 fuse;
 639
 640         DEBUGFUNC("ixgbe_setup_eee_X550");
 641
 642         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 643         /* Enable or disable EEE per flag */
 644         if (enable_eee) {
 645                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 646
 647                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 648                         /* Advertise EEE capability */
 649                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 650                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 651
 652                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 653                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 654                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 655
 656                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 657                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 658                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 659                         /* Not supported on first revision. */
 660                         fuse = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
 661                         if (!(fuse & IXGBE_FUSES0_REV1))
 662                                 return IXGBE_SUCCESS;
 663
 664                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 665                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 666                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 667                         if (status != IXGBE_SUCCESS)
 668                                 return status;
 669
 670                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 671                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 672
 673                         /* Don't advertise FEC capability when EEE enabled. */
 674                         link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 675
 676                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 677                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 678                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 679                         if (status != IXGBE_SUCCESS)
 680                                 return status;
 681                 }
 682         } else {
 683                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 684
 685                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 686                         /* Disable advertised EEE capability */
 687                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 688                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 689
 690                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 691                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 692                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 693
 694                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 695                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 696                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 697                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 698                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 699                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 700                         if (status != IXGBE_SUCCESS)
 701                                 return status;
 702
 703                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 704                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 705
 706                         /* Advertise FEC capability when EEE is disabled. */
 707                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 708
 709                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 710                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 711                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 712                         if (status != IXGBE_SUCCESS)
 713                                 return status;
 714                 }
 715         }
 716         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 717
 718         return IXGBE_SUCCESS;
 719 }
 720
 721 /**
 722  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 723  * @hw: pointer to hardware structure
 724  * @enable: enable or disable source address pruning
 725  * @pool: Rx pool to set source address pruning for
 726  **/
 727 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 728                                            unsigned int pool)
 729 {
 730         u64 pfflp;
 731
 732         /* max rx pool is 63 */
 733         if (pool > 63)
 734                 return;
 735
 736         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 737         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 738
 739         if (enable)
 740                 pfflp |= (1ULL << pool);
 741         else
 742                 pfflp &= ~(1ULL << pool);
 743
 744         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 745         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 746 }
 747
 748 /**
 749  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 750  *  @hw: pointer to hardware structure
 751  *  @enable: enable or disable switch for Ethertype anti-spoofing
 752  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 753  *
 754  **/
 755 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 756                 bool enable, int vf)
 757 {
 758         int vf_target_reg = vf >> 3;
 759         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 760         u32 pfvfspoof;
 761
 762         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 763
 764         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 765         if (enable)
 766                 pfvfspoof |= (1 << vf_target_shift);
 767         else
 768                 pfvfspoof &= ~(1 << vf_target_shift);
 769
 770         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 771 }
 772
 773 /**
 774  * ixgbe_iosf_wait - Wait for IOSF command completion
 775  * @hw: pointer to hardware structure
 776  * @ctrl: pointer to location to receive final IOSF control value
 777  *
 778  * Returns failing status on timeout
 779  *
 780  * Note: ctrl can be NULL if the IOSF control register value is not needed
 781  **/
 782 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 783 {
 784         u32 i, command = 0;
 785
 786         /* Check every 10 usec to see if the address cycle completed.
 787          * The SB IOSF BUSY bit will clear when the operation is
 788          * complete
 789          */
 790         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 791                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 792                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 793                         break;
 794                 usec_delay(10);
 795         }
 796         if (ctrl)
 797                 *ctrl = command;
 798         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 799                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
 800                 return IXGBE_ERR_PHY;
 801         }
 802
 803         return IXGBE_SUCCESS;
 804 }
 805
 806 /**
 807  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 808  *  device
 809  *  @hw: pointer to hardware structure
 810  *  @reg_addr: 32 bit PHY register to write
 811  *  @device_type: 3 bit device type
 812  *  @data: Data to write to the register
 813  **/
 814 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 815                             u32 device_type, u32 data)
 816 {
 817         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 818         u32 command, error;
 819         s32 ret;
 820
 821         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 822         if (ret != IXGBE_SUCCESS)
 823                 return ret;
 824
 825         ret = ixgbe_iosf_wait(hw, NULL);
 826         if (ret != IXGBE_SUCCESS)
 827                 goto out;
 828
 829         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 830                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 831
 832         /* Write IOSF control register */
 833         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 834
 835         /* Write IOSF data register */
 836         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 837
 838         ret = ixgbe_iosf_wait(hw, &command);
 839
 840         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 841                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 842                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 843                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 844                               "Failed to write, error %x\n", error);
 845                 ret = IXGBE_ERR_PHY;
 846         }
 847
 848 out:
 849         ixgbe_release_swfw_semaphore(hw, gssr);
 850         return ret;
 851 }
 852
 853 /**
 854  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 855  *  device
 856  *  @hw: pointer to hardware structure
 857  *  @reg_addr: 32 bit PHY register to write
 858  *  @device_type: 3 bit device type
 859  *  @phy_data: Pointer to read data from the register
 860  **/
 861 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 862                            u32 device_type, u32 *data)
 863 {
 864         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 865         u32 command, error;
 866         s32 ret;
 867
 868         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 869         if (ret != IXGBE_SUCCESS)
 870                 return ret;
 871
 872         ret = ixgbe_iosf_wait(hw, NULL);
 873         if (ret != IXGBE_SUCCESS)
 874                 goto out;
 875
 876         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 877                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 878
 879         /* Write IOSF control register */
 880         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 881
 882         ret = ixgbe_iosf_wait(hw, &command);
 883
 884         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 885                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 886                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 887                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 888                                 "Failed to read, error %x\n", error);
 889                 ret = IXGBE_ERR_PHY;
 890         }
 891
 892         if (ret == IXGBE_SUCCESS)
 893                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 894
 895 out:
 896         ixgbe_release_swfw_semaphore(hw, gssr);
 897         return ret;
 898 }
 899
 900 /**
 901  *  ixgbe_disable_mdd_X550
 902  *  @hw: pointer to hardware structure
 903  *
 904  *  Disable malicious driver detection
 905  **/
 906 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 907 {
 908         u32 reg;
 909
 910         DEBUGFUNC("ixgbe_disable_mdd_X550");
 911
 912         /* Disable MDD for TX DMA and interrupt */
 913         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 914         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 915         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 916
 917         /* Disable MDD for RX and interrupt */
 918         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 919         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 920         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 921 }
 922
 923 /**
 924  *  ixgbe_enable_mdd_X550
 925  *  @hw: pointer to hardware structure
 926  *
 927  *  Enable malicious driver detection
 928  **/
 929 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 930 {
 931         u32 reg;
 932
 933         DEBUGFUNC("ixgbe_enable_mdd_X550");
 934
 935         /* Enable MDD for TX DMA and interrupt */
 936         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 937         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 938         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 939
 940         /* Enable MDD for RX and interrupt */
 941         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 942         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 943         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 944 }
 945
 946 /**
 947  *  ixgbe_restore_mdd_vf_X550
 948  *  @hw: pointer to hardware structure
 949  *  @vf: vf index
 950  *
 951  *  Restore VF that was disabled during malicious driver detection event
 952  **/
 953 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 954 {
 955         u32 idx, reg, num_qs, start_q, bitmask;
 956
 957         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 958
 959         /* Map VF to queues */
 960         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 961         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 962         case IXGBE_MRQC_VMDQRT8TCEN:
 963                 num_qs = 8;  /* 16 VFs / pools */
 964                 bitmask = 0x000000FF;
 965                 break;
 966         case IXGBE_MRQC_VMDQRSS32EN:
 967         case IXGBE_MRQC_VMDQRT4TCEN:
 968                 num_qs = 4;  /* 32 VFs / pools */
 969                 bitmask = 0x0000000F;
 970                 break;
 971         default:            /* 64 VFs / pools */
 972                 num_qs = 2;
 973                 bitmask = 0x00000003;
 974                 break;
 975         }
 976         start_q = vf * num_qs;
 977
 978         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 979         idx = start_q / 32;
 980         reg = 0;
 981         reg |= (bitmask << (start_q % 32));
 982         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 983         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 984 }
 985
 986 /**
 987  *  ixgbe_mdd_event_X550
 988  *  @hw: pointer to hardware structure
 989  *  @vf_bitmap: vf bitmap of malicious vfs
 990  *
 991  *  Handle malicious driver detection event.
 992  **/
 993 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 994 {
 995         u32 wqbr;
 996         u32 i, j, reg, q, shift, vf, idx;
 997
 998         DEBUGFUNC("ixgbe_mdd_event_X550");
 999
1000         /* figure out pool size for mapping to vf's */
1001         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1002         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1003         case IXGBE_MRQC_VMDQRT8TCEN:
1004                 shift = 3;  /* 16 VFs / pools */
1005                 break;
1006         case IXGBE_MRQC_VMDQRSS32EN:
1007         case IXGBE_MRQC_VMDQRT4TCEN:
1008                 shift = 2;  /* 32 VFs / pools */
1009                 break;
1010         default:
1011                 shift = 1;  /* 64 VFs / pools */
1012                 break;
1013         }
1014
1015         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1016         for (i = 0; i < 4; i++) {
1017                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1018                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1019
1020                 if (!wqbr)
1021                         continue;
1022
1023                 /* Get malicious queue */
1024                 for (j = 0; j < 32 && wqbr; j++) {
1025
1026                         if (!(wqbr & (1 << j)))
1027                                 continue;
1028
1029                         /* Get queue from bitmask */
1030                         q = j + (i * 32);
1031
1032                         /* Map queue to vf */
1033                         vf = (q >> shift);
1034
1035                         /* Set vf bit in vf_bitmap */
1036                         idx = vf / 32;
1037                         vf_bitmap[idx] |= (1 << (vf % 32));
1038                         wqbr &= ~(1 << j);
1039                 }
1040         }
1041 }
1042
1043 /**
1044  *  ixgbe_get_media_type_X550em - Get media type
1045  *  @hw: pointer to hardware structure
1046  *
1047  *  Returns the media type (fiber, copper, backplane)
1048  */
1049 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1050 {
1051         enum ixgbe_media_type media_type;
1052
1053         DEBUGFUNC("ixgbe_get_media_type_X550em");
1054
1055         /* Detect if there is a copper PHY attached. */
1056         switch (hw->device_id) {
1057         case IXGBE_DEV_ID_X550EM_X_KR:
1058         case IXGBE_DEV_ID_X550EM_X_KX4:
1059                 media_type = ixgbe_media_type_backplane;
1060                 break;
1061         case IXGBE_DEV_ID_X550EM_X_SFP:
1062                 media_type = ixgbe_media_type_fiber;
1063                 break;
1064         case IXGBE_DEV_ID_X550EM_X_1G_T:
1065         case IXGBE_DEV_ID_X550EM_X_10G_T:
1066                 media_type = ixgbe_media_type_copper;
1067                 break;
1068         default:
1069                 media_type = ixgbe_media_type_unknown;
1070                 break;
1071         }
1072         return media_type;
1073 }
1074
1075 /**
1076  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1077  *  @hw: pointer to hardware structure
1078  *  @linear: true if SFP module is linear
1079  */
1080 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1081 {
1082         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1083
1084         switch (hw->phy.sfp_type) {
1085         case ixgbe_sfp_type_not_present:
1086                 return IXGBE_ERR_SFP_NOT_PRESENT;
1087         case ixgbe_sfp_type_da_cu_core0:
1088         case ixgbe_sfp_type_da_cu_core1:
1089                 *linear = true;
1090                 break;
1091         case ixgbe_sfp_type_srlr_core0:
1092         case ixgbe_sfp_type_srlr_core1:
1093         case ixgbe_sfp_type_da_act_lmt_core0:
1094         case ixgbe_sfp_type_da_act_lmt_core1:
1095         case ixgbe_sfp_type_1g_sx_core0:
1096         case ixgbe_sfp_type_1g_sx_core1:
1097         case ixgbe_sfp_type_1g_lx_core0:
1098         case ixgbe_sfp_type_1g_lx_core1:
1099                 *linear = false;
1100                 break;
1101         case ixgbe_sfp_type_unknown:
1102         case ixgbe_sfp_type_1g_cu_core0:
1103         case ixgbe_sfp_type_1g_cu_core1:
1104         default:
1105                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1106         }
1107
1108         return IXGBE_SUCCESS;
1109 }
1110
1111 /**
1112  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1113  *  @hw: pointer to hardware structure
1114  *
1115  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1116  **/
1117 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1118 {
1119         s32 status;
1120         bool linear;
1121
1122         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1123
1124         status = ixgbe_identify_module_generic(hw);
1125
1126         if (status != IXGBE_SUCCESS)
1127                 return status;
1128
1129         /* Check if SFP module is supported */
1130         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1131
1132         return status;
1133 }
1134
1135 /**
1136  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1137  *  @hw: pointer to hardware structure
1138  */
1139 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1140 {
1141         s32 status;
1142         bool linear;
1143
1144         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1145
1146         /* Check if SFP module is supported */
1147         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1148
1149         if (status != IXGBE_SUCCESS)
1150                 return status;
1151
1152         ixgbe_init_mac_link_ops_X550em(hw);
1153         hw->phy.ops.reset = NULL;
1154
1155         return IXGBE_SUCCESS;
1156 }
1157
1158 /**
1159  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1160  *  @hw: pointer to hardware structure
1161  */
1162 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1163 {
1164         struct ixgbe_mac_info *mac = &hw->mac;
1165
1166         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1167
1168          switch (hw->mac.ops.get_media_type(hw)) {
1169          case ixgbe_media_type_fiber:
1170                 /* CS4227 does not support autoneg, so disable the laser control
1171                  * functions for SFP+ fiber
1172                  */
1173                 mac->ops.disable_tx_laser = NULL;
1174                 mac->ops.enable_tx_laser = NULL;
1175                 mac->ops.flap_tx_laser = NULL;
1176                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1177                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1178                 mac->ops.set_rate_select_speed =
1179                                         ixgbe_set_soft_rate_select_speed;
1180                 break;
1181         case ixgbe_media_type_copper:
1182                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1183                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1184                 break;
1185         default:
1186                 break;
1187          }
1188 }
1189
1190 /**
1191  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1192  *  @hw: pointer to hardware structure
1193  *  @speed: pointer to link speed
1194  *  @autoneg: true when autoneg or autotry is enabled
1195  */
1196 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1197                                        ixgbe_link_speed *speed,
1198                                        bool *autoneg)
1199 {
1200         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1201
1202         /* SFP */
1203         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1204
1205                 /* CS4227 SFP must not enable auto-negotiation */
1206                 *autoneg = false;
1207
1208                 /* Check if 1G SFP module. */
1209                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1210                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1211                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1212                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1213                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1214                         return IXGBE_SUCCESS;
1215                 }
1216
1217                 /* Link capabilities are based on SFP */
1218                 if (hw->phy.multispeed_fiber)
1219                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1220                                  IXGBE_LINK_SPEED_1GB_FULL;
1221                 else
1222                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1223         } else {
1224                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1225                          IXGBE_LINK_SPEED_1GB_FULL;
1226                 *autoneg = true;
1227         }
1228
1229         return IXGBE_SUCCESS;
1230 }
1231
1232 /**
1233  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1234  * @hw: pointer to hardware structure
1235  * @lsc: pointer to boolean flag which indicates whether external Base T
1236  *       PHY interrupt is lsc
1237  *
1238  * Determime if external Base T PHY interrupt cause is high temperature
1239  * failure alarm or link status change.
1240  *
1241  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1242  * failure alarm, else return PHY access status.
1243  */
1244 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1245 {
1246         u32 status;
1247         u16 reg;
1248
1249         *lsc = false;
1250
1251         /* Vendor alarm triggered */
1252         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1253                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1254                                       &reg);
1255
1256         if (status != IXGBE_SUCCESS ||
1257             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1258                 return status;
1259
1260         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1261         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1262                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1263                                       &reg);
1264
1265         if (status != IXGBE_SUCCESS ||
1266             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1267             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1268                 return status;
1269
1270         /* High temperature failure alarm triggered */
1271         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1272                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1273                                       &reg);
1274
1275         if (status != IXGBE_SUCCESS)
1276                 return status;
1277
1278         /* If high temperature failure, then return over temp error and exit */
1279         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1280                 /* power down the PHY in case the PHY FW didn't already */
1281                 ixgbe_set_copper_phy_power(hw, false);
1282                 return IXGBE_ERR_OVERTEMP;
1283         }
1284
1285         /* Vendor alarm 2 triggered */
1286         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1287                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1288
1289         if (status != IXGBE_SUCCESS ||
1290             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1291                 return status;
1292
1293         /* link connect/disconnect event occurred */
1294         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1295                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1296
1297         if (status != IXGBE_SUCCESS)
1298                 return status;
1299
1300         /* Indicate LSC */
1301         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1302                 *lsc = true;
1303
1304         return IXGBE_SUCCESS;
1305 }
1306
1307 /**
1308  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1309  * @hw: pointer to hardware structure
1310  *
1311  * Enable link status change and temperature failure alarm for the external
1312  * Base T PHY
1313  *
1314  * Returns PHY access status
1315  */
1316 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1317 {
1318         u32 status;
1319         u16 reg;
1320         bool lsc;
1321
1322         /* Clear interrupt flags */
1323         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1324
1325         /* Enable link status change alarm */
1326         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1327                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1328
1329         if (status != IXGBE_SUCCESS)
1330                 return status;
1331
1332         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1333
1334         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1335                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1336
1337         if (status != IXGBE_SUCCESS)
1338                 return status;
1339
1340         /* Enables high temperature failure alarm */
1341         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1342                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1343                                       &reg);
1344
1345         if (status != IXGBE_SUCCESS)
1346                 return status;
1347
1348         reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1349
1350         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1351                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1352                                        reg);
1353
1354         if (status != IXGBE_SUCCESS)
1355                 return status;
1356
1357         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1358         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1359                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1360                                       &reg);
1361
1362         if (status != IXGBE_SUCCESS)
1363                 return status;
1364
1365         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1366                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1367
1368         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1369                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1370                                        reg);
1371
1372         if (status != IXGBE_SUCCESS)
1373                 return status;
1374
1375         /* Enable chip-wide vendor alarm */
1376         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1377                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1378                                       &reg);
1379
1380         if (status != IXGBE_SUCCESS)
1381                 return status;
1382
1383         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1384
1385         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1386                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1387                                        reg);
1388
1389         return status;
1390 }
1391
1392 /**
1393  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1394  *  @hw: pointer to hardware structure
1395  *  @speed: link speed
1396  *
1397  *  Configures the integrated KR PHY.
1398  **/
1399 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1400                                        ixgbe_link_speed speed)
1401 {
1402         s32 status;
1403         u32 reg_val;
1404
1405         status = ixgbe_read_iosf_sb_reg_x550(hw,
1406                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1407                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1408         if (status)
1409                 return status;
1410
1411         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1412         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1413                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1414
1415         /* Advertise 10G support. */
1416         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1417                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1418
1419         /* Advertise 1G support. */
1420         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1421                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1422
1423         /* Restart auto-negotiation. */
1424         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1425         status = ixgbe_write_iosf_sb_reg_x550(hw,
1426                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1427                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1428
1429         return status;
1430 }
1431
1432 /**
1433  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1434  *  @hw: pointer to hardware structure
1435  *
1436  *  Initialize any function pointers that were not able to be
1437  *  set during init_shared_code because the PHY/SFP type was
1438  *  not known.  Perform the SFP init if necessary.
1439  */
1440 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1441 {
1442         struct ixgbe_phy_info *phy = &hw->phy;
1443         s32 ret_val;
1444
1445         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1446
1447         hw->mac.ops.set_lan_id(hw);
1448
1449         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1450                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1451                 ixgbe_setup_mux_ctl(hw);
1452
1453                 /* Save NW management interface connected on board. This is used
1454                  * to determine internal PHY mode.
1455                  */
1456                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1457                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1458         }
1459
1460         /* Identify the PHY or SFP module */
1461         ret_val = phy->ops.identify(hw);
1462         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1463                 return ret_val;
1464
1465         /* Setup function pointers based on detected hardware */
1466         ixgbe_init_mac_link_ops_X550em(hw);
1467         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1468                 phy->ops.reset = NULL;
1469
1470         /* Set functions pointers based on phy type */
1471         switch (hw->phy.type) {
1472         case ixgbe_phy_x550em_kx4:
1473                 phy->ops.setup_link = NULL;
1474                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1475                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1476                 break;
1477         case ixgbe_phy_x550em_kr:
1478                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1479                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1480                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1481                 break;
1482         case ixgbe_phy_x550em_ext_t:
1483                 /* Save NW management interface connected on board. This is used
1484                  * to determine internal PHY mode
1485                  */
1486                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1487
1488                 /* If internal link mode is XFI, then setup iXFI internal link,
1489                  * else setup KR now.
1490                  */
1491                 phy->ops.setup_internal_link =
1492                                               ixgbe_setup_internal_phy_t_x550em;
1493
1494                 /* setup SW LPLU only for first revision */
1495                 if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw,
1496                                                        IXGBE_FUSES0_GROUP(0))))
1497                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1498
1499                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1500                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1501                 break;
1502         default:
1503                 break;
1504         }
1505         return ret_val;
1506 }
1507
1508 /**
1509  *  ixgbe_reset_hw_X550em - Perform hardware reset
1510  *  @hw: pointer to hardware structure
1511  *
1512  *  Resets the hardware by resetting the transmit and receive units, masks
1513  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1514  *  reset.
1515  */
1516 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1517 {
1518         ixgbe_link_speed link_speed;
1519         s32 status;
1520         u32 ctrl = 0;
1521         u32 i;
1522         u32 hlreg0;
1523         bool link_up = false;
1524
1525         DEBUGFUNC("ixgbe_reset_hw_X550em");
1526
1527         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1528         status = hw->mac.ops.stop_adapter(hw);
1529         if (status != IXGBE_SUCCESS)
1530                 return status;
1531
1532         /* flush pending Tx transactions */
1533         ixgbe_clear_tx_pending(hw);
1534
1535         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
1536                 /* Config MDIO clock speed before the first MDIO PHY access */
1537                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1538                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1539                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1540         }
1541
1542         /* PHY ops must be identified and initialized prior to reset */
1543         status = hw->phy.ops.init(hw);
1544
1545         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1546                 return status;
1547
1548         /* start the external PHY */
1549         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1550                 status = ixgbe_init_ext_t_x550em(hw);
1551                 if (status)
1552                         return status;
1553         }
1554
1555         /* Setup SFP module if there is one present. */
1556         if (hw->phy.sfp_setup_needed) {
1557                 status = hw->mac.ops.setup_sfp(hw);
1558                 hw->phy.sfp_setup_needed = false;
1559         }
1560
1561         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1562                 return status;
1563
1564         /* Reset PHY */
1565         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1566                 hw->phy.ops.reset(hw);
1567
1568 mac_reset_top:
1569         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1570          * If link reset is used when link is up, it might reset the PHY when
1571          * mng is using it.  If link is down or the flag to force full link
1572          * reset is set, then perform link reset.
1573          */
1574         ctrl = IXGBE_CTRL_LNK_RST;
1575         if (!hw->force_full_reset) {
1576                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1577                 if (link_up)
1578                         ctrl = IXGBE_CTRL_RST;
1579         }
1580
1581         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1582         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1583         IXGBE_WRITE_FLUSH(hw);
1584
1585         /* Poll for reset bit to self-clear meaning reset is complete */
1586         for (i = 0; i < 10; i++) {
1587                 usec_delay(1);
1588                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1589                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1590                         break;
1591         }
1592
1593         if (ctrl & IXGBE_CTRL_RST_MASK) {
1594                 status = IXGBE_ERR_RESET_FAILED;
1595                 DEBUGOUT("Reset polling failed to complete.\n");
1596         }
1597
1598         msec_delay(50);
1599
1600         /* Double resets are required for recovery from certain error
1601          * conditions.  Between resets, it is necessary to stall to
1602          * allow time for any pending HW events to complete.
1603          */
1604         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1605                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1606                 goto mac_reset_top;
1607         }
1608
1609         /* Store the permanent mac address */
1610         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1611
1612         /* Store MAC address from RAR0, clear receive address registers, and
1613          * clear the multicast table.  Also reset num_rar_entries to 128,
1614          * since we modify this value when programming the SAN MAC address.
1615          */
1616         hw->mac.num_rar_entries = 128;
1617         hw->mac.ops.init_rx_addrs(hw);
1618
1619         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1620                 ixgbe_setup_mux_ctl(hw);
1621
1622         return status;
1623 }
1624
1625 /**
1626  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1627  * @hw: pointer to hardware structure
1628  */
1629 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1630 {
1631         u32 status;
1632         u16 reg;
1633
1634         status = hw->phy.ops.read_reg(hw,
1635                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1636                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1637                                       &reg);
1638
1639         if (status != IXGBE_SUCCESS)
1640                 return status;
1641
1642         /* If PHY FW reset completed bit is set then this is the first
1643          * SW instance after a power on so the PHY FW must be un-stalled.
1644          */
1645         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1646                 status = hw->phy.ops.read_reg(hw,
1647                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1648                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1649                                         &reg);
1650
1651                 if (status != IXGBE_SUCCESS)
1652                         return status;
1653
1654                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1655
1656                 status = hw->phy.ops.write_reg(hw,
1657                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1658                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1659                                         reg);
1660
1661                 if (status != IXGBE_SUCCESS)
1662                         return status;
1663         }
1664
1665         return status;
1666 }
1667
1668 /**
1669  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1670  *  @hw: pointer to hardware structure
1671  *
1672  *  Configures the integrated KR PHY.
1673  **/
1674 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1675 {
1676         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1677 }
1678
1679 /**
1680  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
1681  *  @hw: pointer to hardware structure
1682  *
1683  *  Configure the external PHY and the integrated KR PHY for SFP support.
1684  **/
1685 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1686                                     ixgbe_link_speed speed,
1687                                     bool autoneg_wait_to_complete)
1688 {
1689         s32 ret_val;
1690         u16 reg_slice, reg_val;
1691         bool setup_linear = false;
1692         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1693
1694         /* Check if SFP module is supported and linear */
1695         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1696
1697         /* If no SFP module present, then return success. Return success since
1698          * there is no reason to configure CS4227 and SFP not present error is
1699          * not excepted in the setup MAC link flow.
1700          */
1701         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1702                 return IXGBE_SUCCESS;
1703
1704         if (ret_val != IXGBE_SUCCESS)
1705                 return ret_val;
1706
1707         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1708                 /* Configure CS4227 LINE side to 10G SR. */
1709                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
1710                             (hw->bus.lan_id << 12);
1711                 reg_val = IXGBE_CS4227_SPEED_10G;
1712                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1713                                                    reg_val);
1714
1715                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1716                             (hw->bus.lan_id << 12);
1717                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1718                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1719                                                    reg_val);
1720
1721                 /* Configure CS4227 for HOST connection rate then type. */
1722                 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
1723                             (hw->bus.lan_id << 12);
1724                 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
1725                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1726                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1727                                                    reg_val);
1728
1729                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
1730                             (hw->bus.lan_id << 12);
1731                 if (setup_linear)
1732                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1733                 else
1734                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1735                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1736                                                    reg_val);
1737
1738                 /* Setup XFI internal link. */
1739                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1740         } else {
1741                 /* Configure internal PHY for KR/KX. */
1742                 ixgbe_setup_kr_speed_x550em(hw, speed);
1743
1744                 /* Configure CS4227 LINE side to proper mode. */
1745                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1746                             (hw->bus.lan_id << 12);
1747                 if (setup_linear)
1748                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1749                 else
1750                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1751                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1752                                                    reg_val);
1753         }
1754         return ret_val;
1755 }
1756
1757 /**
1758  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
1759  *  @hw: pointer to hardware structure
1760  *
1761  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
1762  **/
1763 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
1764 {
1765         s32 status;
1766         u32 reg_val;
1767
1768         /* Disable training protocol FSM. */
1769         status = ixgbe_read_iosf_sb_reg_x550(hw,
1770                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1771                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1772         if (status != IXGBE_SUCCESS)
1773                 return status;
1774         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1775         status = ixgbe_write_iosf_sb_reg_x550(hw,
1776                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1777                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1778         if (status != IXGBE_SUCCESS)
1779                 return status;
1780
1781         /* Disable Flex from training TXFFE. */
1782         status = ixgbe_read_iosf_sb_reg_x550(hw,
1783                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1784                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1785         if (status != IXGBE_SUCCESS)
1786                 return status;
1787         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1788         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1789         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1790         status = ixgbe_write_iosf_sb_reg_x550(hw,
1791                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1792                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1793         if (status != IXGBE_SUCCESS)
1794                 return status;
1795         status = ixgbe_read_iosf_sb_reg_x550(hw,
1796                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1797                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1798         if (status != IXGBE_SUCCESS)
1799                 return status;
1800         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1801         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1802         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1803         status = ixgbe_write_iosf_sb_reg_x550(hw,
1804                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1805                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1806         if (status != IXGBE_SUCCESS)
1807                 return status;
1808
1809         /* Enable override for coefficients. */
1810         status = ixgbe_read_iosf_sb_reg_x550(hw,
1811                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1812                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1813         if (status != IXGBE_SUCCESS)
1814                 return status;
1815         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1816         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1817         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1818         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1819         status = ixgbe_write_iosf_sb_reg_x550(hw,
1820                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1821                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1822         return status;
1823 }
1824
1825 /**
1826  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1827  *  @hw: pointer to hardware structure
1828  *  @speed: the link speed to force
1829  *
1830  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1831  *  internal and external PHY at a specific speed, without autonegotiation.
1832  **/
1833 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1834 {
1835         s32 status;
1836         u32 reg_val;
1837
1838         /* Disable AN and force speed to 10G Serial. */
1839         status = ixgbe_read_iosf_sb_reg_x550(hw,
1840                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1841                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1842         if (status != IXGBE_SUCCESS)
1843                 return status;
1844
1845         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1846         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1847
1848         /* Select forced link speed for internal PHY. */
1849         switch (*speed) {
1850         case IXGBE_LINK_SPEED_10GB_FULL:
1851                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1852                 break;
1853         case IXGBE_LINK_SPEED_1GB_FULL:
1854                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1855                 break;
1856         default:
1857                 /* Other link speeds are not supported by internal KR PHY. */
1858                 return IXGBE_ERR_LINK_SETUP;
1859         }
1860
1861         status = ixgbe_write_iosf_sb_reg_x550(hw,
1862                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1863                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1864         if (status != IXGBE_SUCCESS)
1865                 return status;
1866
1867         /* Additional configuration needed for x550em_x */
1868         if (hw->mac.type == ixgbe_mac_X550EM_x) {
1869                 status = ixgbe_setup_ixfi_x550em_x(hw);
1870                 if (status != IXGBE_SUCCESS)
1871                         return status;
1872         }
1873
1874         /* Toggle port SW reset by AN reset. */
1875         status = ixgbe_read_iosf_sb_reg_x550(hw,
1876                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1877                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1878         if (status != IXGBE_SUCCESS)
1879                 return status;
1880         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1881         status = ixgbe_write_iosf_sb_reg_x550(hw,
1882                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1883                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1884
1885         return status;
1886 }
1887
1888 /**
1889  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
1890  * @hw: address of hardware structure
1891  * @link_up: address of boolean to indicate link status
1892  *
1893  * Returns error code if unable to get link status.
1894  */
1895 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
1896 {
1897         u32 ret;
1898         u16 autoneg_status;
1899
1900         *link_up = false;
1901
1902         /* read this twice back to back to indicate current status */
1903         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1904                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1905                                    &autoneg_status);
1906         if (ret != IXGBE_SUCCESS)
1907                 return ret;
1908
1909         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1910                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1911                                    &autoneg_status);
1912         if (ret != IXGBE_SUCCESS)
1913                 return ret;
1914
1915         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
1916
1917         return IXGBE_SUCCESS;
1918 }
1919
1920 /**
1921  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1922  * @hw: point to hardware structure
1923  *
1924  * Configures the link between the integrated KR PHY and the external X557 PHY
1925  * The driver will call this function when it gets a link status change
1926  * interrupt from the X557 PHY. This function configures the link speed
1927  * between the PHYs to match the link speed of the BASE-T link.
1928  *
1929  * A return of a non-zero value indicates an error, and the base driver should
1930  * not report link up.
1931  */
1932 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1933 {
1934         ixgbe_link_speed force_speed;
1935         bool link_up;
1936         u32 status;
1937         u16 speed;
1938
1939         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1940                 return IXGBE_ERR_CONFIG;
1941
1942         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1943                 /* If link is down, there is no setup necessary so return  */
1944                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1945                 if (status != IXGBE_SUCCESS)
1946                         return status;
1947
1948                 if (!link_up)
1949                         return IXGBE_SUCCESS;
1950
1951                 status = hw->phy.ops.read_reg(hw,
1952                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1953                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1954                                               &speed);
1955                 if (status != IXGBE_SUCCESS)
1956                         return status;
1957
1958                 /* If link is still down - no setup is required so return */
1959                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1960                 if (status != IXGBE_SUCCESS)
1961                         return status;
1962                 if (!link_up)
1963                         return IXGBE_SUCCESS;
1964
1965                 /* clear everything but the speed and duplex bits */
1966                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1967
1968                 switch (speed) {
1969                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1970                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1971                         break;
1972                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1973                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1974                         break;
1975                 default:
1976                         /* Internal PHY does not support anything else */
1977                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
1978                 }
1979
1980                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1981         } else {
1982                 speed = IXGBE_LINK_SPEED_10GB_FULL |
1983                         IXGBE_LINK_SPEED_1GB_FULL;
1984                 return ixgbe_setup_kr_speed_x550em(hw, speed);
1985         }
1986 }
1987
1988 /**
1989  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1990  *  @hw: pointer to hardware structure
1991  *
1992  *  Configures the integrated KR PHY to use internal loopback mode.
1993  **/
1994 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1995 {
1996         s32 status;
1997         u32 reg_val;
1998
1999         /* Disable AN and force speed to 10G Serial. */
2000         status = ixgbe_read_iosf_sb_reg_x550(hw,
2001                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2002                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2003         if (status != IXGBE_SUCCESS)
2004                 return status;
2005         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2006         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2007         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2008         status = ixgbe_write_iosf_sb_reg_x550(hw,
2009                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2010                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2011         if (status != IXGBE_SUCCESS)
2012                 return status;
2013
2014         /* Set near-end loopback clocks. */
2015         status = ixgbe_read_iosf_sb_reg_x550(hw,
2016                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2017                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2018         if (status != IXGBE_SUCCESS)
2019                 return status;
2020         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2021         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2022         status = ixgbe_write_iosf_sb_reg_x550(hw,
2023                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2024                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2025         if (status != IXGBE_SUCCESS)
2026                 return status;
2027
2028         /* Set loopback enable. */
2029         status = ixgbe_read_iosf_sb_reg_x550(hw,
2030                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2031                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2032         if (status != IXGBE_SUCCESS)
2033                 return status;
2034         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2035         status = ixgbe_write_iosf_sb_reg_x550(hw,
2036                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2037                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2038         if (status != IXGBE_SUCCESS)
2039                 return status;
2040
2041         /* Training bypass. */
2042         status = ixgbe_read_iosf_sb_reg_x550(hw,
2043                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2044                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2045         if (status != IXGBE_SUCCESS)
2046                 return status;
2047         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2048         status = ixgbe_write_iosf_sb_reg_x550(hw,
2049                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2050                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2051
2052         return status;
2053 }
2054
2055 /**
2056  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2057  *  assuming that the semaphore is already obtained.
2058  *  @hw: pointer to hardware structure
2059  *  @offset: offset of  word in the EEPROM to read
2060  *  @data: word read from the EEPROM
2061  *
2062  *  Reads a 16 bit word from the EEPROM using the hostif.
2063  **/
2064 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2065                                    u16 *data)
2066 {
2067         s32 status;
2068         struct ixgbe_hic_read_shadow_ram buffer;
2069
2070         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2071         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2072         buffer.hdr.req.buf_lenh = 0;
2073         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2074         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2075
2076         /* convert offset from words to bytes */
2077         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2078         /* one word */
2079         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2080
2081         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2082                                               sizeof(buffer),
2083                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2084
2085         if (status)
2086                 return status;
2087
2088         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2089                                           FW_NVM_DATA_OFFSET);
2090
2091         return 0;
2092 }
2093
2094 /**
2095  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2096  *  @hw: pointer to hardware structure
2097  *  @offset: offset of  word in the EEPROM to read
2098  *  @data: word read from the EEPROM
2099  *
2100  *  Reads a 16 bit word from the EEPROM using the hostif.
2101  **/
2102 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2103                               u16 *data)
2104 {
2105         s32 status = IXGBE_SUCCESS;
2106
2107         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2108
2109         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2110             IXGBE_SUCCESS) {
2111                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2112                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2113         } else {
2114                 status = IXGBE_ERR_SWFW_SYNC;
2115         }
2116
2117         return status;
2118 }
2119
2120 /**
2121  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2122  *  @hw: pointer to hardware structure
2123  *  @offset: offset of  word in the EEPROM to read
2124  *  @words: number of words
2125  *  @data: word(s) read from the EEPROM
2126  *
2127  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
2128  **/
2129 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2130                                      u16 offset, u16 words, u16 *data)
2131 {
2132         struct ixgbe_hic_read_shadow_ram buffer;
2133         u32 current_word = 0;
2134         u16 words_to_read;
2135         s32 status;
2136         u32 i;
2137
2138         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2139
2140         /* Take semaphore for the entire operation. */
2141         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2142         if (status) {
2143                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2144                 return status;
2145         }
2146         while (words) {
2147                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2148                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2149                 else
2150                         words_to_read = words;
2151
2152                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2153                 buffer.hdr.req.buf_lenh = 0;
2154                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2155                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2156
2157                 /* convert offset from words to bytes */
2158                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2159                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2160
2161                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2162                                                       sizeof(buffer),
2163                                                       IXGBE_HI_COMMAND_TIMEOUT,
2164                                                       false);
2165
2166                 if (status) {
2167                         DEBUGOUT("Host interface command failed\n");
2168                         goto out;
2169                 }
2170
2171                 for (i = 0; i < words_to_read; i++) {
2172                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2173                                   2 * i;
2174                         u32 value = IXGBE_READ_REG(hw, reg);
2175
2176                         data[current_word] = (u16)(value & 0xffff);
2177                         current_word++;
2178                         i++;
2179                         if (i < words_to_read) {
2180                                 value >>= 16;
2181                                 data[current_word] = (u16)(value & 0xffff);
2182                                 current_word++;
2183                         }
2184                 }
2185                 words -= words_to_read;
2186         }
2187
2188 out:
2189         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2190         return status;
2191 }
2192
2193 /**
2194  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2195  *  @hw: pointer to hardware structure
2196  *  @offset: offset of  word in the EEPROM to write
2197  *  @data: word write to the EEPROM
2198  *
2199  *  Write a 16 bit word to the EEPROM using the hostif.
2200  **/
2201 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2202                                     u16 data)
2203 {
2204         s32 status;
2205         struct ixgbe_hic_write_shadow_ram buffer;
2206
2207         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2208
2209         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2210         buffer.hdr.req.buf_lenh = 0;
2211         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2212         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2213
2214          /* one word */
2215         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2216         buffer.data = data;
2217         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2218
2219         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2220                                               sizeof(buffer),
2221                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2222
2223         return status;
2224 }
2225
2226 /**
2227  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2228  *  @hw: pointer to hardware structure
2229  *  @offset: offset of  word in the EEPROM to write
2230  *  @data: word write to the EEPROM
2231  *
2232  *  Write a 16 bit word to the EEPROM using the hostif.
2233  **/
2234 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2235                                u16 data)
2236 {
2237         s32 status = IXGBE_SUCCESS;
2238
2239         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2240
2241         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2242             IXGBE_SUCCESS) {
2243                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2244                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2245         } else {
2246                 DEBUGOUT("write ee hostif failed to get semaphore");
2247                 status = IXGBE_ERR_SWFW_SYNC;
2248         }
2249
2250         return status;
2251 }
2252
2253 /**
2254  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2255  *  @hw: pointer to hardware structure
2256  *  @offset: offset of  word in the EEPROM to write
2257  *  @words: number of words
2258  *  @data: word(s) write to the EEPROM
2259  *
2260  *  Write a 16 bit word(s) to the EEPROM using the hostif.
2261  **/
2262 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2263                                       u16 offset, u16 words, u16 *data)
2264 {
2265         s32 status = IXGBE_SUCCESS;
2266         u32 i = 0;
2267
2268         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2269
2270         /* Take semaphore for the entire operation. */
2271         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2272         if (status != IXGBE_SUCCESS) {
2273                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2274                 goto out;
2275         }
2276
2277         for (i = 0; i < words; i++) {
2278                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2279                                                          data[i]);
2280
2281                 if (status != IXGBE_SUCCESS) {
2282                         DEBUGOUT("Eeprom buffered write failed\n");
2283                         break;
2284                 }
2285         }
2286
2287         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2288 out:
2289
2290         return status;
2291 }
2292
2293 /**
2294  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2295  * @hw: pointer to hardware structure
2296  * @ptr: pointer offset in eeprom
2297  * @size: size of section pointed by ptr, if 0 first word will be used as size
2298  * @csum: address of checksum to update
2299  *
2300  * Returns error status for any failure
2301  */
2302 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2303                                    u16 size, u16 *csum, u16 *buffer,
2304                                    u32 buffer_size)
2305 {
2306         u16 buf[256];
2307         s32 status;
2308         u16 length, bufsz, i, start;
2309         u16 *local_buffer;
2310
2311         bufsz = sizeof(buf) / sizeof(buf[0]);
2312
2313         /* Read a chunk at the pointer location */
2314         if (!buffer) {
2315                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2316                 if (status) {
2317                         DEBUGOUT("Failed to read EEPROM image\n");
2318                         return status;
2319                 }
2320                 local_buffer = buf;
2321         } else {
2322                 if (buffer_size < ptr)
2323                         return  IXGBE_ERR_PARAM;
2324                 local_buffer = &buffer[ptr];
2325         }
2326
2327         if (size) {
2328                 start = 0;
2329                 length = size;
2330         } else {
2331                 start = 1;
2332                 length = local_buffer[0];
2333
2334                 /* Skip pointer section if length is invalid. */
2335                 if (length == 0xFFFF || length == 0 ||
2336                     (ptr + length) >= hw->eeprom.word_size)
2337                         return IXGBE_SUCCESS;
2338         }
2339
2340         if (buffer && ((u32)start + (u32)length > buffer_size))
2341                 return IXGBE_ERR_PARAM;
2342
2343         for (i = start; length; i++, length--) {
2344                 if (i == bufsz && !buffer) {
2345                         ptr += bufsz;
2346                         i = 0;
2347                         if (length < bufsz)
2348                                 bufsz = length;
2349
2350                         /* Read a chunk at the pointer location */
2351                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2352                                                                   bufsz, buf);
2353                         if (status) {
2354                                 DEBUGOUT("Failed to read EEPROM image\n");
2355                                 return status;
2356                         }
2357                 }
2358                 *csum += local_buffer[i];
2359         }
2360         return IXGBE_SUCCESS;
2361 }
2362
2363 /**
2364  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2365  *  @hw: pointer to hardware structure
2366  *  @buffer: pointer to buffer containing calculated checksum
2367  *  @buffer_size: size of buffer
2368  *
2369  *  Returns a negative error code on error, or the 16-bit checksum
2370  **/
2371 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2372 {
2373         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2374         u16 *local_buffer;
2375         s32 status;
2376         u16 checksum = 0;
2377         u16 pointer, i, size;
2378
2379         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2380
2381         hw->eeprom.ops.init_params(hw);
2382
2383         if (!buffer) {
2384                 /* Read pointer area */
2385                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2386                                                      IXGBE_EEPROM_LAST_WORD + 1,
2387                                                      eeprom_ptrs);
2388                 if (status) {
2389                         DEBUGOUT("Failed to read EEPROM image\n");
2390                         return status;
2391                 }
2392                 local_buffer = eeprom_ptrs;
2393         } else {
2394                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2395                         return IXGBE_ERR_PARAM;
2396                 local_buffer = buffer;
2397         }
2398
2399         /*
2400          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2401          * checksum word itself
2402          */
2403         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2404                 if (i != IXGBE_EEPROM_CHECKSUM)
2405                         checksum += local_buffer[i];
2406
2407         /*
2408          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2409          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2410          */
2411         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2412                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2413                         continue;
2414
2415                 pointer = local_buffer[i];
2416
2417                 /* Skip pointer section if the pointer is invalid. */
2418                 if (pointer == 0xFFFF || pointer == 0 ||
2419                     pointer >= hw->eeprom.word_size)
2420                         continue;
2421
2422                 switch (i) {
2423                 case IXGBE_PCIE_GENERAL_PTR:
2424                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2425                         break;
2426                 case IXGBE_PCIE_CONFIG0_PTR:
2427                 case IXGBE_PCIE_CONFIG1_PTR:
2428                         size = IXGBE_PCIE_CONFIG_SIZE;
2429                         break;
2430                 default:
2431                         size = 0;
2432                         break;
2433                 }
2434
2435                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2436                                                 buffer, buffer_size);
2437                 if (status)
2438                         return status;
2439         }
2440
2441         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2442
2443         return (s32)checksum;
2444 }
2445
2446 /**
2447  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2448  *  @hw: pointer to hardware structure
2449  *
2450  *  Returns a negative error code on error, or the 16-bit checksum
2451  **/
2452 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2453 {
2454         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2455 }
2456
2457 /**
2458  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2459  *  @hw: pointer to hardware structure
2460  *  @checksum_val: calculated checksum
2461  *
2462  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2463  *  caller does not need checksum_val, the value can be NULL.
2464  **/
2465 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2466 {
2467         s32 status;
2468         u16 checksum;
2469         u16 read_checksum = 0;
2470
2471         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2472
2473         /* Read the first word from the EEPROM. If this times out or fails, do
2474          * not continue or we could be in for a very long wait while every
2475          * EEPROM read fails
2476          */
2477         status = hw->eeprom.ops.read(hw, 0, &checksum);
2478         if (status) {
2479                 DEBUGOUT("EEPROM read failed\n");
2480                 return status;
2481         }
2482
2483         status = hw->eeprom.ops.calc_checksum(hw);
2484         if (status < 0)
2485                 return status;
2486
2487         checksum = (u16)(status & 0xffff);
2488
2489         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2490                                            &read_checksum);
2491         if (status)
2492                 return status;
2493
2494         /* Verify read checksum from EEPROM is the same as
2495          * calculated checksum
2496          */
2497         if (read_checksum != checksum) {
2498                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2499                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2500                              "Invalid EEPROM checksum");
2501         }
2502
2503         /* If the user cares, return the calculated checksum */
2504         if (checksum_val)
2505                 *checksum_val = checksum;
2506
2507         return status;
2508 }
2509
2510 /**
2511  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2512  * @hw: pointer to hardware structure
2513  *
2514  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2515  * checksum and updates the EEPROM and instructs the hardware to update
2516  * the flash.
2517  **/
2518 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2519 {
2520         s32 status;
2521         u16 checksum = 0;
2522
2523         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2524
2525         /* Read the first word from the EEPROM. If this times out or fails, do
2526          * not continue or we could be in for a very long wait while every
2527          * EEPROM read fails
2528          */
2529         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2530         if (status) {
2531                 DEBUGOUT("EEPROM read failed\n");
2532                 return status;
2533         }
2534
2535         status = ixgbe_calc_eeprom_checksum_X550(hw);
2536         if (status < 0)
2537                 return status;
2538
2539         checksum = (u16)(status & 0xffff);
2540
2541         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2542                                             checksum);
2543         if (status)
2544                 return status;
2545
2546         status = ixgbe_update_flash_X550(hw);
2547
2548         return status;
2549 }
2550
2551 /**
2552  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2553  *  @hw: pointer to hardware structure
2554  *
2555  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2556  **/
2557 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2558 {
2559         s32 status = IXGBE_SUCCESS;
2560         union ixgbe_hic_hdr2 buffer;
2561
2562         DEBUGFUNC("ixgbe_update_flash_X550");
2563
2564         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2565         buffer.req.buf_lenh = 0;
2566         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2567         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2568
2569         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2570                                               sizeof(buffer),
2571                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2572
2573         return status;
2574 }
2575
2576 /**
2577  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2578  *  @hw: pointer to hardware structure
2579  *
2580  *  Determines physical layer capabilities of the current configuration.
2581  **/
2582 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2583 {
2584         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2585         u16 ext_ability = 0;
2586
2587         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2588
2589         hw->phy.ops.identify(hw);
2590
2591         switch (hw->phy.type) {
2592         case ixgbe_phy_x550em_kr:
2593                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2594                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2595                 break;
2596         case ixgbe_phy_x550em_kx4:
2597                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2598                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2599                 break;
2600         case ixgbe_phy_x550em_ext_t:
2601                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2602                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2603                                      &ext_ability);
2604                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2605                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2606                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2607                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2608                 break;
2609         default:
2610                 break;
2611         }
2612
2613         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2614                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2615
2616         return physical_layer;
2617 }
2618
2619 /**
2620  * ixgbe_get_bus_info_x550em - Set PCI bus info
2621  * @hw: pointer to hardware structure
2622  *
2623  * Sets bus link width and speed to unknown because X550em is
2624  * not a PCI device.
2625  **/
2626 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2627 {
2628
2629         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2630
2631         hw->bus.width = ixgbe_bus_width_unknown;
2632         hw->bus.speed = ixgbe_bus_speed_unknown;
2633
2634         hw->mac.ops.set_lan_id(hw);
2635
2636         return IXGBE_SUCCESS;
2637 }
2638
2639 /**
2640  * ixgbe_disable_rx_x550 - Disable RX unit
2641  *
2642  * Enables the Rx DMA unit for x550
2643  **/
2644 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2645 {
2646         u32 rxctrl, pfdtxgswc;
2647         s32 status;
2648         struct ixgbe_hic_disable_rxen fw_cmd;
2649
2650         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2651
2652         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2653         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2654                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2655                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2656                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2657                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2658                         hw->mac.set_lben = true;
2659                 } else {
2660                         hw->mac.set_lben = false;
2661                 }
2662
2663                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2664                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2665                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2666                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2667
2668                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2669                                         sizeof(struct ixgbe_hic_disable_rxen),
2670                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2671
2672                 /* If we fail - disable RX using register write */
2673                 if (status) {
2674                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2675                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2676                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2677                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2678                         }
2679                 }
2680         }
2681 }
2682
2683 /**
2684  * ixgbe_enter_lplu_x550em - Transition to low power states
2685  *  @hw: pointer to hardware structure
2686  *
2687  * Configures Low Power Link Up on transition to low power states
2688  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2689  * X557 PHY immediately prior to entering LPLU.
2690  **/
2691 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2692 {
2693         u16 an_10g_cntl_reg, autoneg_reg, speed;
2694         s32 status;
2695         ixgbe_link_speed lcd_speed;
2696         u32 save_autoneg;
2697         bool link_up;
2698
2699         /* SW LPLU not required on later HW revisions. */
2700         if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))
2701                 return IXGBE_SUCCESS;
2702
2703         /* If blocked by MNG FW, then don't restart AN */
2704         if (ixgbe_check_reset_blocked(hw))
2705                 return IXGBE_SUCCESS;
2706
2707         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2708         if (status != IXGBE_SUCCESS)
2709                 return status;
2710
2711         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2712
2713         if (status != IXGBE_SUCCESS)
2714                 return status;
2715
2716         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2717          * disabled, then force link down by entering low power mode.
2718          */
2719         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2720             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2721                 return ixgbe_set_copper_phy_power(hw, FALSE);
2722
2723         /* Determine LCD */
2724         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2725
2726         if (status != IXGBE_SUCCESS)
2727                 return status;
2728
2729         /* If no valid LCD link speed, then force link down and exit. */
2730         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2731                 return ixgbe_set_copper_phy_power(hw, FALSE);
2732
2733         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2734                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2735                                       &speed);
2736
2737         if (status != IXGBE_SUCCESS)
2738                 return status;
2739
2740         /* If no link now, speed is invalid so take link down */
2741         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2742         if (status != IXGBE_SUCCESS)
2743                 return ixgbe_set_copper_phy_power(hw, false);
2744
2745         /* clear everything but the speed bits */
2746         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2747
2748         /* If current speed is already LCD, then exit. */
2749         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2750              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2751             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2752              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2753                 return status;
2754
2755         /* Clear AN completed indication */
2756         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2757                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2758                                       &autoneg_reg);
2759
2760         if (status != IXGBE_SUCCESS)
2761                 return status;
2762
2763         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2764                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2765                              &an_10g_cntl_reg);
2766
2767         if (status != IXGBE_SUCCESS)
2768                 return status;
2769
2770         status = hw->phy.ops.read_reg(hw,
2771                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2772                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2773                              &autoneg_reg);
2774
2775         if (status != IXGBE_SUCCESS)
2776                 return status;
2777
2778         save_autoneg = hw->phy.autoneg_advertised;
2779
2780         /* Setup link at least common link speed */
2781         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2782
2783         /* restore autoneg from before setting lplu speed */
2784         hw->phy.autoneg_advertised = save_autoneg;
2785
2786         return status;
2787 }
2788
2789 /**
2790  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2791  *  @hw: pointer to hardware structure
2792  *  @lcd_speed: pointer to lowest common link speed
2793  *
2794  * Determine lowest common link speed with link partner.
2795  **/
2796 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2797 {
2798         u16 an_lp_status;
2799         s32 status;
2800         u16 word = hw->eeprom.ctrl_word_3;
2801
2802         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2803
2804         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2805                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2806                                       &an_lp_status);
2807
2808         if (status != IXGBE_SUCCESS)
2809                 return status;
2810
2811         /* If link partner advertised 1G, return 1G */
2812         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2813                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2814                 return status;
2815         }
2816
2817         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2818         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2819             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2820                 return status;
2821
2822         /* Link partner not capable of lower speeds, return 10G */
2823         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2824         return status;
2825 }
2826
2827 /**
2828  *  ixgbe_setup_fc_X550em - Set up flow control
2829  *  @hw: pointer to hardware structure
2830  *
2831  *  Called at init time to set up flow control.
2832  **/
2833 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2834 {
2835         s32 ret_val = IXGBE_SUCCESS;
2836         u32 pause, asm_dir, reg_val;
2837
2838         DEBUGFUNC("ixgbe_setup_fc_X550em");
2839
2840         /* Validate the requested mode */
2841         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2842                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2843                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2844                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2845                 goto out;
2846         }
2847
2848         /* 10gig parts do not have a word in the EEPROM to determine the
2849          * default flow control setting, so we explicitly set it to full.
2850          */
2851         if (hw->fc.requested_mode == ixgbe_fc_default)
2852                 hw->fc.requested_mode = ixgbe_fc_full;
2853
2854         /* Determine PAUSE and ASM_DIR bits. */
2855         switch (hw->fc.requested_mode) {
2856         case ixgbe_fc_none:
2857                 pause = 0;
2858                 asm_dir = 0;
2859                 break;
2860         case ixgbe_fc_tx_pause:
2861                 pause = 0;
2862                 asm_dir = 1;
2863                 break;
2864         case ixgbe_fc_rx_pause:
2865                 /* Rx Flow control is enabled and Tx Flow control is
2866                  * disabled by software override. Since there really
2867                  * isn't a way to advertise that we are capable of RX
2868                  * Pause ONLY, we will advertise that we support both
2869                  * symmetric and asymmetric Rx PAUSE, as such we fall
2870                  * through to the fc_full statement.  Later, we will
2871                  * disable the adapter's ability to send PAUSE frames.
2872                  */
2873         case ixgbe_fc_full:
2874                 pause = 1;
2875                 asm_dir = 1;
2876                 break;
2877         default:
2878                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2879                         "Flow control param set incorrectly\n");
2880                 ret_val = IXGBE_ERR_CONFIG;
2881                 goto out;
2882         }
2883
2884         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
2885                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2886                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2887                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2888                 if (ret_val != IXGBE_SUCCESS)
2889                         goto out;
2890                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2891                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2892                 if (pause)
2893                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2894                 if (asm_dir)
2895                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2896                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2897                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2898                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2899
2900                 /* This device does not fully support AN. */
2901                 hw->fc.disable_fc_autoneg = true;
2902         }
2903
2904 out:
2905         return ret_val;
2906 }
2907
2908 /**
2909  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2910  * @hw: pointer to hardware structure
2911  * @state: set mux if 1, clear if 0
2912  */
2913 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2914 {
2915         u32 esdp;
2916
2917         if (!hw->bus.lan_id)
2918                 return;
2919         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2920         if (state)
2921                 esdp |= IXGBE_ESDP_SDP1;
2922         else
2923                 esdp &= ~IXGBE_ESDP_SDP1;
2924         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2925         IXGBE_WRITE_FLUSH(hw);
2926 }
2927
2928 /**
2929  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2930  *  @hw: pointer to hardware structure
2931  *  @mask: Mask to specify which semaphore to acquire
2932  *
2933  *  Acquires the SWFW semaphore and sets the I2C MUX
2934  **/
2935 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2936 {
2937         s32 status;
2938
2939         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2940
2941         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2942         if (status)
2943                 return status;
2944
2945         if (mask & IXGBE_GSSR_I2C_MASK)
2946                 ixgbe_set_mux(hw, 1);
2947
2948         return IXGBE_SUCCESS;
2949 }
2950
2951 /**
2952  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2953  *  @hw: pointer to hardware structure
2954  *  @mask: Mask to specify which semaphore to release
2955  *
2956  *  Releases the SWFW semaphore and sets the I2C MUX
2957  **/
2958 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2959 {
2960         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2961
2962         if (mask & IXGBE_GSSR_I2C_MASK)
2963                 ixgbe_set_mux(hw, 0);
2964
2965         ixgbe_release_swfw_sync_X540(hw, mask);
2966 }
2967
2968 /**
2969  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2970  * @hw: pointer to hardware structure
2971  *
2972  * Handle external Base T PHY interrupt. If high temperature
2973  * failure alarm then return error, else if link status change
2974  * then setup internal/external PHY link
2975  *
2976  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2977  * failure alarm, else return PHY access status.
2978  */
2979 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2980 {
2981         bool lsc;
2982         u32 status;
2983
2984         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2985
2986         if (status != IXGBE_SUCCESS)
2987                 return status;
2988
2989         if (lsc)
2990                 return ixgbe_setup_internal_phy(hw);
2991
2992         return IXGBE_SUCCESS;
2993 }
2994
2995 /**
2996  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
2997  * @hw: pointer to hardware structure
2998  * @speed: new link speed
2999  * @autoneg_wait_to_complete: true when waiting for completion is needed
3000  *
3001  * Setup internal/external PHY link speed based on link speed, then set
3002  * external PHY auto advertised link speed.
3003  *
3004  * Returns error status for any failure
3005  **/
3006 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3007                                   ixgbe_link_speed speed,
3008                                   bool autoneg_wait_to_complete)
3009 {
3010         s32 status;
3011         ixgbe_link_speed force_speed;
3012
3013         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3014
3015         /* Setup internal/external PHY link speed to iXFI (10G), unless
3016          * only 1G is auto advertised then setup KX link.
3017          */
3018         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3019                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3020         else
3021                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3022
3023         /* If internal link mode is XFI, then setup XFI internal link. */
3024         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3025                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3026
3027                 if (status != IXGBE_SUCCESS)
3028                         return status;
3029         }
3030
3031         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3032 }
3033
3034 /**
3035  * ixgbe_check_link_t_X550em - Determine link and speed status
3036  * @hw: pointer to hardware structure
3037  * @speed: pointer to link speed
3038  * @link_up: true when link is up
3039  * @link_up_wait_to_complete: bool used to wait for link up or not
3040  *
3041  * Check that both the MAC and X557 external PHY have link.
3042  **/
3043 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3044                               bool *link_up, bool link_up_wait_to_complete)
3045 {
3046         u32 status;
3047         u16 autoneg_status;
3048
3049         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3050                 return IXGBE_ERR_CONFIG;
3051
3052         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3053                                               link_up_wait_to_complete);
3054
3055         /* If check link fails or MAC link is not up, then return */
3056         if (status != IXGBE_SUCCESS || !(*link_up))
3057                 return status;
3058
3059         /* MAC link is up, so check external PHY link.
3060          * Read this twice back to back to indicate current status.
3061          */
3062         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3063                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3064                                       &autoneg_status);
3065
3066         if (status != IXGBE_SUCCESS)
3067                 return status;
3068
3069         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3070                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3071                                       &autoneg_status);
3072
3073         if (status != IXGBE_SUCCESS)
3074                 return status;
3075
3076         /* If external PHY link is not up, then indicate link not up */
3077         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3078                 *link_up = false;
3079
3080         return IXGBE_SUCCESS;
3081 }
3082
3083 /**
3084  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3085  *  @hw: pointer to hardware structure
3086  **/
3087 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3088 {
3089         s32 status;
3090
3091         status = ixgbe_reset_phy_generic(hw);
3092
3093         if (status != IXGBE_SUCCESS)
3094                 return status;
3095
3096         /* Configure Link Status Alarm and Temperature Threshold interrupts */
3097         return ixgbe_enable_lasi_ext_t_x550em(hw);
3098 }
3099
3100 /**
3101  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
3102  *  @hw: pointer to hardware structure
3103  *  @led_idx: led number to turn on
3104  **/
3105 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3106 {
3107         u16 phy_data;
3108
3109         DEBUGFUNC("ixgbe_led_on_t_X550em");
3110
3111         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3112                 return IXGBE_ERR_PARAM;
3113
3114         /* To turn on the LED, set mode to ON. */
3115         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3116                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3117         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3118         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3119                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3120
3121         return IXGBE_SUCCESS;
3122 }
3123
3124 /**
3125  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3126  *  @hw: pointer to hardware structure
3127  *  @led_idx: led number to turn off
3128  **/
3129 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3130 {
3131         u16 phy_data;
3132
3133         DEBUGFUNC("ixgbe_led_off_t_X550em");
3134
3135         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3136                 return IXGBE_ERR_PARAM;
3137
3138         /* To turn on the LED, set mode to ON. */
3139         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3140                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3141         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3142         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3143                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3144
3145         return IXGBE_SUCCESS;
3146 }
3147