1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
13 #include <netinet/in.h>
14 #include <rte_string_fns.h>
15 #include <rte_byteorder.h>
16 #include <rte_common.h>
17 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_branch_prediction.h>
25 #include <rte_memory.h>
26 #include <rte_kvargs.h>
28 #include <rte_alarm.h>
29 #include <rte_ether.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
32 #include <rte_malloc.h>
33 #include <rte_random.h>
35 #include <rte_hash_crc.h>
36 #ifdef RTE_LIBRTE_SECURITY
37 #include <rte_security_driver.h>
40 #include "ixgbe_logs.h"
41 #include "base/ixgbe_api.h"
42 #include "base/ixgbe_vf.h"
43 #include "base/ixgbe_common.h"
44 #include "ixgbe_ethdev.h"
45 #include "ixgbe_bypass.h"
46 #include "ixgbe_rxtx.h"
47 #include "base/ixgbe_type.h"
48 #include "base/ixgbe_phy.h"
49 #include "ixgbe_regs.h"
52 * High threshold controlling when to start sending XOFF frames. Must be at
53 * least 8 bytes less than receive packet buffer size. This value is in units
56 #define IXGBE_FC_HI 0x80
59 * Low threshold controlling when to start sending XON frames. This value is
60 * in units of 1024 bytes.
62 #define IXGBE_FC_LO 0x40
64 /* Timer value included in XOFF frames. */
65 #define IXGBE_FC_PAUSE 0x680
67 /*Default value of Max Rx Queue*/
68 #define IXGBE_MAX_RX_QUEUE_NUM 128
70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
71 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
72 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
74 #define IXGBE_MMW_SIZE_DEFAULT 0x4
75 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
76 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
79 * Default values for RX/TX configuration
81 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
82 #define IXGBE_DEFAULT_RX_PTHRESH 8
83 #define IXGBE_DEFAULT_RX_HTHRESH 8
84 #define IXGBE_DEFAULT_RX_WTHRESH 0
86 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
87 #define IXGBE_DEFAULT_TX_PTHRESH 32
88 #define IXGBE_DEFAULT_TX_HTHRESH 0
89 #define IXGBE_DEFAULT_TX_WTHRESH 0
90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
92 /* Bit shift and mask */
93 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
94 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
95 #define IXGBE_8_BIT_WIDTH CHAR_BIT
96 #define IXGBE_8_BIT_MASK UINT8_MAX
98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
102 /* Additional timesync values. */
103 #define NSEC_PER_SEC 1000000000L
104 #define IXGBE_INCVAL_10GB 0x66666666
105 #define IXGBE_INCVAL_1GB 0x40000000
106 #define IXGBE_INCVAL_100 0x50000000
107 #define IXGBE_INCVAL_SHIFT_10GB 28
108 #define IXGBE_INCVAL_SHIFT_1GB 24
109 #define IXGBE_INCVAL_SHIFT_100 21
110 #define IXGBE_INCVAL_SHIFT_82599 7
111 #define IXGBE_INCPER_SHIFT_82599 24
113 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
115 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
117 #define IXGBE_ETAG_ETYPE 0x00005084
118 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
119 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
120 #define IXGBE_RAH_ADTYPE 0x40000000
121 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
122 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
125 #define IXGBE_QDE_STRIP_TAG 0x00000004
126 #define IXGBE_VTEICR_MASK 0x07
128 #define IXGBE_EXVET_VET_EXT_SHIFT 16
129 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK "pflink_fullchk"
133 static const char * const ixgbevf_valid_arguments[] = {
134 IXGBEVF_DEVARG_PFLINK_FULLCHK,
138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
150 static void ixgbe_dev_close(struct rte_eth_dev *dev);
151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
157 int wait_to_complete);
158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
159 struct rte_eth_stats *stats);
160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
161 struct rte_eth_xstat *xstats, unsigned n);
162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
163 struct rte_eth_xstat *xstats, unsigned n);
165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
166 uint64_t *values, unsigned int n);
167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
170 struct rte_eth_xstat_name *xstats_names,
172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
173 struct rte_eth_xstat_name *xstats_names, unsigned limit);
174 static int ixgbe_dev_xstats_get_names_by_id(
175 struct rte_eth_dev *dev,
176 struct rte_eth_xstat_name *xstats_names,
179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
186 struct rte_eth_dev_info *dev_info);
187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
189 struct rte_eth_dev_info *dev_info);
190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
193 uint16_t vlan_id, int on);
194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
195 enum rte_vlan_type vlan_type,
197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
198 uint16_t queue, bool on);
199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
213 struct rte_eth_fc_conf *fc_conf);
214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
215 struct rte_eth_fc_conf *fc_conf);
216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
217 struct rte_eth_pfc_conf *pfc_conf);
218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
219 struct rte_eth_rss_reta_entry64 *reta_conf,
221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
222 struct rte_eth_rss_reta_entry64 *reta_conf,
224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
230 static void ixgbe_dev_interrupt_handler(void *param);
231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
232 static void ixgbe_dev_setup_link_alarm_handler(void *param);
234 static int ixgbe_add_rar(struct rte_eth_dev *dev,
235 struct rte_ether_addr *mac_addr,
236 uint32_t index, uint32_t pool);
237 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
238 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
239 struct rte_ether_addr *mac_addr);
240 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
241 static bool is_device_supported(struct rte_eth_dev *dev,
242 struct rte_pci_driver *drv);
244 /* For Virtual Function support */
245 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
246 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
247 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
248 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
249 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
250 int wait_to_complete);
251 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
252 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
253 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
254 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
255 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
256 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
257 struct rte_eth_stats *stats);
258 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
259 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
260 uint16_t vlan_id, int on);
261 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
262 uint16_t queue, int on);
263 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
264 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
265 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
266 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
268 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
270 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
271 uint8_t queue, uint8_t msix_vector);
272 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
273 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
274 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
275 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
276 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
278 /* For Eth VMDQ APIs support */
279 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
280 rte_ether_addr * mac_addr, uint8_t on);
281 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
282 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
283 struct rte_eth_mirror_conf *mirror_conf,
284 uint8_t rule_id, uint8_t on);
285 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
287 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
289 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
291 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
292 uint8_t queue, uint8_t msix_vector);
293 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
295 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
296 struct rte_ether_addr *mac_addr,
297 uint32_t index, uint32_t pool);
298 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
299 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
300 struct rte_ether_addr *mac_addr);
301 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
302 struct rte_eth_syn_filter *filter);
303 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
304 enum rte_filter_op filter_op,
306 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
307 struct ixgbe_5tuple_filter *filter);
308 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
309 struct ixgbe_5tuple_filter *filter);
310 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
311 enum rte_filter_op filter_op,
313 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
314 struct rte_eth_ntuple_filter *filter);
315 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
316 enum rte_filter_op filter_op,
318 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
319 struct rte_eth_ethertype_filter *filter);
320 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
321 enum rte_filter_type filter_type,
322 enum rte_filter_op filter_op,
324 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
326 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
327 struct rte_ether_addr *mc_addr_set,
328 uint32_t nb_mc_addr);
329 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
330 struct rte_eth_dcb_info *dcb_info);
332 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
333 static int ixgbe_get_regs(struct rte_eth_dev *dev,
334 struct rte_dev_reg_info *regs);
335 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
336 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
337 struct rte_dev_eeprom_info *eeprom);
338 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
339 struct rte_dev_eeprom_info *eeprom);
341 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
342 struct rte_eth_dev_module_info *modinfo);
343 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
344 struct rte_dev_eeprom_info *info);
346 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
347 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
348 struct rte_dev_reg_info *regs);
350 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
351 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
352 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
353 struct timespec *timestamp,
355 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
356 struct timespec *timestamp);
357 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
358 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
359 struct timespec *timestamp);
360 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
361 const struct timespec *timestamp);
362 static void ixgbevf_dev_interrupt_handler(void *param);
364 static int ixgbe_dev_l2_tunnel_eth_type_conf
365 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
366 static int ixgbe_dev_l2_tunnel_offload_set
367 (struct rte_eth_dev *dev,
368 struct rte_eth_l2_tunnel_conf *l2_tunnel,
371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
372 enum rte_filter_op filter_op,
375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
376 struct rte_eth_udp_tunnel *udp_tunnel);
377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
378 struct rte_eth_udp_tunnel *udp_tunnel);
379 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
380 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
383 * Define VF Stats MACRO for Non "cleared on read" register
385 #define UPDATE_VF_STAT(reg, last, cur) \
387 uint32_t latest = IXGBE_READ_REG(hw, reg); \
388 cur += (latest - last) & UINT_MAX; \
392 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
394 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
395 u64 new_msb = IXGBE_READ_REG(hw, msb); \
396 u64 latest = ((new_msb << 32) | new_lsb); \
397 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
401 #define IXGBE_SET_HWSTRIP(h, q) do {\
402 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
403 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
404 (h)->bitmap[idx] |= 1 << bit;\
407 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
408 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
409 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
410 (h)->bitmap[idx] &= ~(1 << bit);\
413 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
414 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
415 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
416 (r) = (h)->bitmap[idx] >> bit & 1;\
419 int ixgbe_logtype_init;
420 int ixgbe_logtype_driver;
422 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
423 int ixgbe_logtype_rx;
425 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
426 int ixgbe_logtype_tx;
428 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
429 int ixgbe_logtype_tx_free;
433 * The set of PCI devices this driver supports
435 static const struct rte_pci_id pci_id_ixgbe_map[] = {
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
483 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
484 #ifdef RTE_LIBRTE_IXGBE_BYPASS
485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
487 { .vendor_id = 0, /* sentinel */ },
491 * The set of PCI devices this driver supports (for 82599 VF)
493 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
494 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
495 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
500 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
501 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
502 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
503 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
504 { .vendor_id = 0, /* sentinel */ },
507 static const struct rte_eth_desc_lim rx_desc_lim = {
508 .nb_max = IXGBE_MAX_RING_DESC,
509 .nb_min = IXGBE_MIN_RING_DESC,
510 .nb_align = IXGBE_RXD_ALIGN,
513 static const struct rte_eth_desc_lim tx_desc_lim = {
514 .nb_max = IXGBE_MAX_RING_DESC,
515 .nb_min = IXGBE_MIN_RING_DESC,
516 .nb_align = IXGBE_TXD_ALIGN,
517 .nb_seg_max = IXGBE_TX_MAX_SEG,
518 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
521 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
522 .dev_configure = ixgbe_dev_configure,
523 .dev_start = ixgbe_dev_start,
524 .dev_stop = ixgbe_dev_stop,
525 .dev_set_link_up = ixgbe_dev_set_link_up,
526 .dev_set_link_down = ixgbe_dev_set_link_down,
527 .dev_close = ixgbe_dev_close,
528 .dev_reset = ixgbe_dev_reset,
529 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
530 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
531 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
532 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
533 .link_update = ixgbe_dev_link_update,
534 .stats_get = ixgbe_dev_stats_get,
535 .xstats_get = ixgbe_dev_xstats_get,
536 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
537 .stats_reset = ixgbe_dev_stats_reset,
538 .xstats_reset = ixgbe_dev_xstats_reset,
539 .xstats_get_names = ixgbe_dev_xstats_get_names,
540 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
541 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
542 .fw_version_get = ixgbe_fw_version_get,
543 .dev_infos_get = ixgbe_dev_info_get,
544 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
545 .mtu_set = ixgbe_dev_mtu_set,
546 .vlan_filter_set = ixgbe_vlan_filter_set,
547 .vlan_tpid_set = ixgbe_vlan_tpid_set,
548 .vlan_offload_set = ixgbe_vlan_offload_set,
549 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
550 .rx_queue_start = ixgbe_dev_rx_queue_start,
551 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
552 .tx_queue_start = ixgbe_dev_tx_queue_start,
553 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
554 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
555 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
556 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
557 .rx_queue_release = ixgbe_dev_rx_queue_release,
558 .rx_queue_count = ixgbe_dev_rx_queue_count,
559 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
560 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
561 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
562 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
563 .tx_queue_release = ixgbe_dev_tx_queue_release,
564 .dev_led_on = ixgbe_dev_led_on,
565 .dev_led_off = ixgbe_dev_led_off,
566 .flow_ctrl_get = ixgbe_flow_ctrl_get,
567 .flow_ctrl_set = ixgbe_flow_ctrl_set,
568 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
569 .mac_addr_add = ixgbe_add_rar,
570 .mac_addr_remove = ixgbe_remove_rar,
571 .mac_addr_set = ixgbe_set_default_mac_addr,
572 .uc_hash_table_set = ixgbe_uc_hash_table_set,
573 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
574 .mirror_rule_set = ixgbe_mirror_rule_set,
575 .mirror_rule_reset = ixgbe_mirror_rule_reset,
576 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
577 .reta_update = ixgbe_dev_rss_reta_update,
578 .reta_query = ixgbe_dev_rss_reta_query,
579 .rss_hash_update = ixgbe_dev_rss_hash_update,
580 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
581 .filter_ctrl = ixgbe_dev_filter_ctrl,
582 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
583 .rxq_info_get = ixgbe_rxq_info_get,
584 .txq_info_get = ixgbe_txq_info_get,
585 .timesync_enable = ixgbe_timesync_enable,
586 .timesync_disable = ixgbe_timesync_disable,
587 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
588 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
589 .get_reg = ixgbe_get_regs,
590 .get_eeprom_length = ixgbe_get_eeprom_length,
591 .get_eeprom = ixgbe_get_eeprom,
592 .set_eeprom = ixgbe_set_eeprom,
593 .get_module_info = ixgbe_get_module_info,
594 .get_module_eeprom = ixgbe_get_module_eeprom,
595 .get_dcb_info = ixgbe_dev_get_dcb_info,
596 .timesync_adjust_time = ixgbe_timesync_adjust_time,
597 .timesync_read_time = ixgbe_timesync_read_time,
598 .timesync_write_time = ixgbe_timesync_write_time,
599 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
600 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
601 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
602 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
603 .tm_ops_get = ixgbe_tm_ops_get,
607 * dev_ops for virtual function, bare necessities for basic vf
608 * operation have been implemented
610 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
611 .dev_configure = ixgbevf_dev_configure,
612 .dev_start = ixgbevf_dev_start,
613 .dev_stop = ixgbevf_dev_stop,
614 .link_update = ixgbevf_dev_link_update,
615 .stats_get = ixgbevf_dev_stats_get,
616 .xstats_get = ixgbevf_dev_xstats_get,
617 .stats_reset = ixgbevf_dev_stats_reset,
618 .xstats_reset = ixgbevf_dev_stats_reset,
619 .xstats_get_names = ixgbevf_dev_xstats_get_names,
620 .dev_close = ixgbevf_dev_close,
621 .dev_reset = ixgbevf_dev_reset,
622 .promiscuous_enable = ixgbevf_dev_promiscuous_enable,
623 .promiscuous_disable = ixgbevf_dev_promiscuous_disable,
624 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
625 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
626 .dev_infos_get = ixgbevf_dev_info_get,
627 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
628 .mtu_set = ixgbevf_dev_set_mtu,
629 .vlan_filter_set = ixgbevf_vlan_filter_set,
630 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
631 .vlan_offload_set = ixgbevf_vlan_offload_set,
632 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
633 .rx_queue_release = ixgbe_dev_rx_queue_release,
634 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
635 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
636 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
637 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
638 .tx_queue_release = ixgbe_dev_tx_queue_release,
639 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
640 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
641 .mac_addr_add = ixgbevf_add_mac_addr,
642 .mac_addr_remove = ixgbevf_remove_mac_addr,
643 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
644 .rxq_info_get = ixgbe_rxq_info_get,
645 .txq_info_get = ixgbe_txq_info_get,
646 .mac_addr_set = ixgbevf_set_default_mac_addr,
647 .get_reg = ixgbevf_get_regs,
648 .reta_update = ixgbe_dev_rss_reta_update,
649 .reta_query = ixgbe_dev_rss_reta_query,
650 .rss_hash_update = ixgbe_dev_rss_hash_update,
651 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
654 /* store statistics names and its offset in stats structure */
655 struct rte_ixgbe_xstats_name_off {
656 char name[RTE_ETH_XSTATS_NAME_SIZE];
660 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
661 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
662 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
663 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
664 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
665 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
666 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
667 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
668 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
669 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
670 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
671 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
672 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
673 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
674 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
675 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
677 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
679 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
680 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
681 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
682 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
683 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
684 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
685 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
686 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
687 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
688 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
689 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
690 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
691 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
692 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
693 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
694 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
695 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
697 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
699 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
700 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
701 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
702 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
704 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
706 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
708 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
710 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
712 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
714 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
717 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
718 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
719 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
721 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
722 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
723 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
724 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
725 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
727 {"rx_fcoe_no_direct_data_placement_ext_buff",
728 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
730 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
732 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
734 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
736 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
738 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
741 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
742 sizeof(rte_ixgbe_stats_strings[0]))
744 /* MACsec statistics */
745 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
746 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
748 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
749 out_pkts_encrypted)},
750 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
751 out_pkts_protected)},
752 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
753 out_octets_encrypted)},
754 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
755 out_octets_protected)},
756 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
758 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
760 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
762 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
763 in_pkts_unknownsci)},
764 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
765 in_octets_decrypted)},
766 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
767 in_octets_validated)},
768 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
770 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
772 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
774 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
776 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
778 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
780 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
782 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
783 in_pkts_notusingsa)},
786 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
787 sizeof(rte_ixgbe_macsec_strings[0]))
789 /* Per-queue statistics */
790 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
791 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
792 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
793 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
794 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
797 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
798 sizeof(rte_ixgbe_rxq_strings[0]))
799 #define IXGBE_NB_RXQ_PRIO_VALUES 8
801 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
802 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
803 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
804 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
808 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
809 sizeof(rte_ixgbe_txq_strings[0]))
810 #define IXGBE_NB_TXQ_PRIO_VALUES 8
812 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
813 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
816 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
817 sizeof(rte_ixgbevf_stats_strings[0]))
820 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
823 ixgbe_is_sfp(struct ixgbe_hw *hw)
825 switch (hw->phy.type) {
826 case ixgbe_phy_sfp_avago:
827 case ixgbe_phy_sfp_ftl:
828 case ixgbe_phy_sfp_intel:
829 case ixgbe_phy_sfp_unknown:
830 case ixgbe_phy_sfp_passive_tyco:
831 case ixgbe_phy_sfp_passive_unknown:
838 static inline int32_t
839 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
844 status = ixgbe_reset_hw(hw);
846 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
847 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
848 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
849 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
850 IXGBE_WRITE_FLUSH(hw);
852 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
853 status = IXGBE_SUCCESS;
858 ixgbe_enable_intr(struct rte_eth_dev *dev)
860 struct ixgbe_interrupt *intr =
861 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
862 struct ixgbe_hw *hw =
863 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
865 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
866 IXGBE_WRITE_FLUSH(hw);
870 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
873 ixgbe_disable_intr(struct ixgbe_hw *hw)
875 PMD_INIT_FUNC_TRACE();
877 if (hw->mac.type == ixgbe_mac_82598EB) {
878 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
880 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
881 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
882 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
884 IXGBE_WRITE_FLUSH(hw);
888 * This function resets queue statistics mapping registers.
889 * From Niantic datasheet, Initialization of Statistics section:
890 * "...if software requires the queue counters, the RQSMR and TQSM registers
891 * must be re-programmed following a device reset.
894 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
898 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
899 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
900 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
906 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
911 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
912 #define NB_QMAP_FIELDS_PER_QSM_REG 4
913 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
915 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
916 struct ixgbe_stat_mapping_registers *stat_mappings =
917 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
918 uint32_t qsmr_mask = 0;
919 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
923 if ((hw->mac.type != ixgbe_mac_82599EB) &&
924 (hw->mac.type != ixgbe_mac_X540) &&
925 (hw->mac.type != ixgbe_mac_X550) &&
926 (hw->mac.type != ixgbe_mac_X550EM_x) &&
927 (hw->mac.type != ixgbe_mac_X550EM_a))
930 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
931 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
934 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
935 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
936 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
939 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
941 /* Now clear any previous stat_idx set */
942 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
944 stat_mappings->tqsm[n] &= ~clearing_mask;
946 stat_mappings->rqsmr[n] &= ~clearing_mask;
948 q_map = (uint32_t)stat_idx;
949 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
950 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
952 stat_mappings->tqsm[n] |= qsmr_mask;
954 stat_mappings->rqsmr[n] |= qsmr_mask;
956 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
957 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
959 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
960 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
962 /* Now write the mapping in the appropriate register */
964 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
965 stat_mappings->rqsmr[n], n);
966 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
968 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
969 stat_mappings->tqsm[n], n);
970 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
976 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
978 struct ixgbe_stat_mapping_registers *stat_mappings =
979 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
980 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
983 /* write whatever was in stat mapping table to the NIC */
984 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
986 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
989 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
994 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
997 struct ixgbe_dcb_tc_config *tc;
998 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1000 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1001 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1002 for (i = 0; i < dcb_max_tc; i++) {
1003 tc = &dcb_config->tc_config[i];
1004 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1005 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1006 (uint8_t)(100/dcb_max_tc + (i & 1));
1007 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1008 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1009 (uint8_t)(100/dcb_max_tc + (i & 1));
1010 tc->pfc = ixgbe_dcb_pfc_disabled;
1013 /* Initialize default user to priority mapping, UPx->TC0 */
1014 tc = &dcb_config->tc_config[0];
1015 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1016 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1017 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1018 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1019 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1021 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1022 dcb_config->pfc_mode_enable = false;
1023 dcb_config->vt_mode = true;
1024 dcb_config->round_robin_enable = false;
1025 /* support all DCB capabilities in 82599 */
1026 dcb_config->support.capabilities = 0xFF;
1028 /*we only support 4 Tcs for X540, X550 */
1029 if (hw->mac.type == ixgbe_mac_X540 ||
1030 hw->mac.type == ixgbe_mac_X550 ||
1031 hw->mac.type == ixgbe_mac_X550EM_x ||
1032 hw->mac.type == ixgbe_mac_X550EM_a) {
1033 dcb_config->num_tcs.pg_tcs = 4;
1034 dcb_config->num_tcs.pfc_tcs = 4;
1039 * Ensure that all locks are released before first NVM or PHY access
1042 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1047 * Phy lock should not fail in this early stage. If this is the case,
1048 * it is due to an improper exit of the application.
1049 * So force the release of the faulty lock. Release of common lock
1050 * is done automatically by swfw_sync function.
1052 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1053 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1054 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1056 ixgbe_release_swfw_semaphore(hw, mask);
1059 * These ones are more tricky since they are common to all ports; but
1060 * swfw_sync retries last long enough (1s) to be almost sure that if
1061 * lock can not be taken it is due to an improper lock of the
1064 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1065 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1066 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1068 ixgbe_release_swfw_semaphore(hw, mask);
1072 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1073 * It returns 0 on success.
1076 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1078 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1079 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1080 struct ixgbe_hw *hw =
1081 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1082 struct ixgbe_vfta *shadow_vfta =
1083 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1084 struct ixgbe_hwstrip *hwstrip =
1085 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1086 struct ixgbe_dcb_config *dcb_config =
1087 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1088 struct ixgbe_filter_info *filter_info =
1089 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1090 struct ixgbe_bw_conf *bw_conf =
1091 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1096 PMD_INIT_FUNC_TRACE();
1098 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1099 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1100 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1101 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1104 * For secondary processes, we don't initialise any further as primary
1105 * has already done this work. Only check we don't need a different
1106 * RX and TX function.
1108 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1109 struct ixgbe_tx_queue *txq;
1110 /* TX queue function in primary, set by last queue initialized
1111 * Tx queue may not initialized by primary process
1113 if (eth_dev->data->tx_queues) {
1114 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1115 ixgbe_set_tx_function(eth_dev, txq);
1117 /* Use default TX function if we get here */
1118 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1119 "Using default TX function.");
1122 ixgbe_set_rx_function(eth_dev);
1127 rte_eth_copy_pci_info(eth_dev, pci_dev);
1129 /* Vendor and Device ID need to be set before init of shared code */
1130 hw->device_id = pci_dev->id.device_id;
1131 hw->vendor_id = pci_dev->id.vendor_id;
1132 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1133 hw->allow_unsupported_sfp = 1;
1135 /* Initialize the shared code (base driver) */
1136 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1137 diag = ixgbe_bypass_init_shared_code(hw);
1139 diag = ixgbe_init_shared_code(hw);
1140 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1142 if (diag != IXGBE_SUCCESS) {
1143 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1147 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1148 PMD_INIT_LOG(ERR, "\nERROR: "
1149 "Firmware recovery mode detected. Limiting functionality.\n"
1150 "Refer to the Intel(R) Ethernet Adapters and Devices "
1151 "User Guide for details on firmware recovery mode.");
1155 /* pick up the PCI bus settings for reporting later */
1156 ixgbe_get_bus_info(hw);
1158 /* Unlock any pending hardware semaphore */
1159 ixgbe_swfw_lock_reset(hw);
1161 #ifdef RTE_LIBRTE_SECURITY
1162 /* Initialize security_ctx only for primary process*/
1163 if (ixgbe_ipsec_ctx_create(eth_dev))
1167 /* Initialize DCB configuration*/
1168 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1169 ixgbe_dcb_init(hw, dcb_config);
1170 /* Get Hardware Flow Control setting */
1171 hw->fc.requested_mode = ixgbe_fc_full;
1172 hw->fc.current_mode = ixgbe_fc_full;
1173 hw->fc.pause_time = IXGBE_FC_PAUSE;
1174 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1175 hw->fc.low_water[i] = IXGBE_FC_LO;
1176 hw->fc.high_water[i] = IXGBE_FC_HI;
1178 hw->fc.send_xon = 1;
1180 /* Make sure we have a good EEPROM before we read from it */
1181 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1182 if (diag != IXGBE_SUCCESS) {
1183 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1187 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1188 diag = ixgbe_bypass_init_hw(hw);
1190 diag = ixgbe_init_hw(hw);
1191 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1194 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1195 * is called too soon after the kernel driver unbinding/binding occurs.
1196 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1197 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1198 * also called. See ixgbe_identify_phy_82599(). The reason for the
1199 * failure is not known, and only occuts when virtualisation features
1200 * are disabled in the bios. A delay of 100ms was found to be enough by
1201 * trial-and-error, and is doubled to be safe.
1203 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1205 diag = ixgbe_init_hw(hw);
1208 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1209 diag = IXGBE_SUCCESS;
1211 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1212 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1213 "LOM. Please be aware there may be issues associated "
1214 "with your hardware.");
1215 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1216 "please contact your Intel or hardware representative "
1217 "who provided you with this hardware.");
1218 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1219 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1221 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1225 /* Reset the hw statistics */
1226 ixgbe_dev_stats_reset(eth_dev);
1228 /* disable interrupt */
1229 ixgbe_disable_intr(hw);
1231 /* reset mappings for queue statistics hw counters*/
1232 ixgbe_reset_qstat_mappings(hw);
1234 /* Allocate memory for storing MAC addresses */
1235 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1236 hw->mac.num_rar_entries, 0);
1237 if (eth_dev->data->mac_addrs == NULL) {
1239 "Failed to allocate %u bytes needed to store "
1241 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1244 /* Copy the permanent MAC address */
1245 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1246 ð_dev->data->mac_addrs[0]);
1248 /* Allocate memory for storing hash filter MAC addresses */
1249 eth_dev->data->hash_mac_addrs = rte_zmalloc(
1250 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1251 if (eth_dev->data->hash_mac_addrs == NULL) {
1253 "Failed to allocate %d bytes needed to store MAC addresses",
1254 RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1258 /* Pass the information to the rte_eth_dev_close() that it should also
1259 * release the private port resources.
1261 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1263 /* initialize the vfta */
1264 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1266 /* initialize the hw strip bitmap*/
1267 memset(hwstrip, 0, sizeof(*hwstrip));
1269 /* initialize PF if max_vfs not zero */
1270 ixgbe_pf_host_init(eth_dev);
1272 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1273 /* let hardware know driver is loaded */
1274 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1275 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1276 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1277 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1278 IXGBE_WRITE_FLUSH(hw);
1280 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1281 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1282 (int) hw->mac.type, (int) hw->phy.type,
1283 (int) hw->phy.sfp_type);
1285 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1286 (int) hw->mac.type, (int) hw->phy.type);
1288 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1289 eth_dev->data->port_id, pci_dev->id.vendor_id,
1290 pci_dev->id.device_id);
1292 rte_intr_callback_register(intr_handle,
1293 ixgbe_dev_interrupt_handler, eth_dev);
1295 /* enable uio/vfio intr/eventfd mapping */
1296 rte_intr_enable(intr_handle);
1298 /* enable support intr */
1299 ixgbe_enable_intr(eth_dev);
1301 /* initialize filter info */
1302 memset(filter_info, 0,
1303 sizeof(struct ixgbe_filter_info));
1305 /* initialize 5tuple filter list */
1306 TAILQ_INIT(&filter_info->fivetuple_list);
1308 /* initialize flow director filter list & hash */
1309 ixgbe_fdir_filter_init(eth_dev);
1311 /* initialize l2 tunnel filter list & hash */
1312 ixgbe_l2_tn_filter_init(eth_dev);
1314 /* initialize flow filter lists */
1315 ixgbe_filterlist_init();
1317 /* initialize bandwidth configuration info */
1318 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1320 /* initialize Traffic Manager configuration */
1321 ixgbe_tm_conf_init(eth_dev);
1327 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1329 PMD_INIT_FUNC_TRACE();
1331 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1334 ixgbe_dev_close(eth_dev);
1339 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1341 struct ixgbe_filter_info *filter_info =
1342 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1343 struct ixgbe_5tuple_filter *p_5tuple;
1345 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1346 TAILQ_REMOVE(&filter_info->fivetuple_list,
1351 memset(filter_info->fivetuple_mask, 0,
1352 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1357 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1359 struct ixgbe_hw_fdir_info *fdir_info =
1360 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1361 struct ixgbe_fdir_filter *fdir_filter;
1363 if (fdir_info->hash_map)
1364 rte_free(fdir_info->hash_map);
1365 if (fdir_info->hash_handle)
1366 rte_hash_free(fdir_info->hash_handle);
1368 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1369 TAILQ_REMOVE(&fdir_info->fdir_list,
1372 rte_free(fdir_filter);
1378 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1380 struct ixgbe_l2_tn_info *l2_tn_info =
1381 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1382 struct ixgbe_l2_tn_filter *l2_tn_filter;
1384 if (l2_tn_info->hash_map)
1385 rte_free(l2_tn_info->hash_map);
1386 if (l2_tn_info->hash_handle)
1387 rte_hash_free(l2_tn_info->hash_handle);
1389 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1390 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1393 rte_free(l2_tn_filter);
1399 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1401 struct ixgbe_hw_fdir_info *fdir_info =
1402 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1403 char fdir_hash_name[RTE_HASH_NAMESIZE];
1404 struct rte_hash_parameters fdir_hash_params = {
1405 .name = fdir_hash_name,
1406 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1407 .key_len = sizeof(union ixgbe_atr_input),
1408 .hash_func = rte_hash_crc,
1409 .hash_func_init_val = 0,
1410 .socket_id = rte_socket_id(),
1413 TAILQ_INIT(&fdir_info->fdir_list);
1414 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1415 "fdir_%s", eth_dev->device->name);
1416 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1417 if (!fdir_info->hash_handle) {
1418 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1421 fdir_info->hash_map = rte_zmalloc("ixgbe",
1422 sizeof(struct ixgbe_fdir_filter *) *
1423 IXGBE_MAX_FDIR_FILTER_NUM,
1425 if (!fdir_info->hash_map) {
1427 "Failed to allocate memory for fdir hash map!");
1430 fdir_info->mask_added = FALSE;
1435 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1437 struct ixgbe_l2_tn_info *l2_tn_info =
1438 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1439 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1440 struct rte_hash_parameters l2_tn_hash_params = {
1441 .name = l2_tn_hash_name,
1442 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1443 .key_len = sizeof(struct ixgbe_l2_tn_key),
1444 .hash_func = rte_hash_crc,
1445 .hash_func_init_val = 0,
1446 .socket_id = rte_socket_id(),
1449 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1450 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1451 "l2_tn_%s", eth_dev->device->name);
1452 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1453 if (!l2_tn_info->hash_handle) {
1454 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1457 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1458 sizeof(struct ixgbe_l2_tn_filter *) *
1459 IXGBE_MAX_L2_TN_FILTER_NUM,
1461 if (!l2_tn_info->hash_map) {
1463 "Failed to allocate memory for L2 TN hash map!");
1466 l2_tn_info->e_tag_en = FALSE;
1467 l2_tn_info->e_tag_fwd_en = FALSE;
1468 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1473 * Negotiate mailbox API version with the PF.
1474 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1475 * Then we try to negotiate starting with the most recent one.
1476 * If all negotiation attempts fail, then we will proceed with
1477 * the default one (ixgbe_mbox_api_10).
1480 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1484 /* start with highest supported, proceed down */
1485 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1493 i != RTE_DIM(sup_ver) &&
1494 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1500 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1504 /* Set Organizationally Unique Identifier (OUI) prefix. */
1505 mac_addr->addr_bytes[0] = 0x00;
1506 mac_addr->addr_bytes[1] = 0x09;
1507 mac_addr->addr_bytes[2] = 0xC0;
1508 /* Force indication of locally assigned MAC address. */
1509 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1510 /* Generate the last 3 bytes of the MAC address with a random number. */
1511 random = rte_rand();
1512 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1516 devarg_handle_int(__rte_unused const char *key, const char *value,
1519 uint16_t *n = extra_args;
1521 if (value == NULL || extra_args == NULL)
1524 *n = (uint16_t)strtoul(value, NULL, 0);
1525 if (*n == USHRT_MAX && errno == ERANGE)
1532 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1533 struct rte_devargs *devargs)
1535 struct rte_kvargs *kvlist;
1536 uint16_t pflink_fullchk;
1538 if (devargs == NULL)
1541 kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1545 if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1546 rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1547 devarg_handle_int, &pflink_fullchk) == 0 &&
1548 pflink_fullchk == 1)
1549 adapter->pflink_fullchk = 1;
1551 rte_kvargs_free(kvlist);
1555 * Virtual Function device init
1558 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1562 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1563 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1564 struct ixgbe_hw *hw =
1565 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1566 struct ixgbe_vfta *shadow_vfta =
1567 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1568 struct ixgbe_hwstrip *hwstrip =
1569 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1570 struct rte_ether_addr *perm_addr =
1571 (struct rte_ether_addr *)hw->mac.perm_addr;
1573 PMD_INIT_FUNC_TRACE();
1575 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1576 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1577 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1579 /* for secondary processes, we don't initialise any further as primary
1580 * has already done this work. Only check we don't need a different
1583 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1584 struct ixgbe_tx_queue *txq;
1585 /* TX queue function in primary, set by last queue initialized
1586 * Tx queue may not initialized by primary process
1588 if (eth_dev->data->tx_queues) {
1589 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1590 ixgbe_set_tx_function(eth_dev, txq);
1592 /* Use default TX function if we get here */
1593 PMD_INIT_LOG(NOTICE,
1594 "No TX queues configured yet. Using default TX function.");
1597 ixgbe_set_rx_function(eth_dev);
1602 ixgbevf_parse_devargs(eth_dev->data->dev_private,
1603 pci_dev->device.devargs);
1605 rte_eth_copy_pci_info(eth_dev, pci_dev);
1607 hw->device_id = pci_dev->id.device_id;
1608 hw->vendor_id = pci_dev->id.vendor_id;
1609 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1611 /* initialize the vfta */
1612 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1614 /* initialize the hw strip bitmap*/
1615 memset(hwstrip, 0, sizeof(*hwstrip));
1617 /* Initialize the shared code (base driver) */
1618 diag = ixgbe_init_shared_code(hw);
1619 if (diag != IXGBE_SUCCESS) {
1620 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1624 /* init_mailbox_params */
1625 hw->mbx.ops.init_params(hw);
1627 /* Reset the hw statistics */
1628 ixgbevf_dev_stats_reset(eth_dev);
1630 /* Disable the interrupts for VF */
1631 ixgbevf_intr_disable(eth_dev);
1633 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1634 diag = hw->mac.ops.reset_hw(hw);
1637 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1638 * the underlying PF driver has not assigned a MAC address to the VF.
1639 * In this case, assign a random MAC address.
1641 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1642 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1644 * This error code will be propagated to the app by
1645 * rte_eth_dev_reset, so use a public error code rather than
1646 * the internal-only IXGBE_ERR_RESET_FAILED
1651 /* negotiate mailbox API version to use with the PF. */
1652 ixgbevf_negotiate_api(hw);
1654 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1655 ixgbevf_get_queues(hw, &tcs, &tc);
1657 /* Allocate memory for storing MAC addresses */
1658 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1659 hw->mac.num_rar_entries, 0);
1660 if (eth_dev->data->mac_addrs == NULL) {
1662 "Failed to allocate %u bytes needed to store "
1664 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1668 /* Pass the information to the rte_eth_dev_close() that it should also
1669 * release the private port resources.
1671 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1673 /* Generate a random MAC address, if none was assigned by PF. */
1674 if (rte_is_zero_ether_addr(perm_addr)) {
1675 generate_random_mac_addr(perm_addr);
1676 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1678 rte_free(eth_dev->data->mac_addrs);
1679 eth_dev->data->mac_addrs = NULL;
1682 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1683 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1684 "%02x:%02x:%02x:%02x:%02x:%02x",
1685 perm_addr->addr_bytes[0],
1686 perm_addr->addr_bytes[1],
1687 perm_addr->addr_bytes[2],
1688 perm_addr->addr_bytes[3],
1689 perm_addr->addr_bytes[4],
1690 perm_addr->addr_bytes[5]);
1693 /* Copy the permanent MAC address */
1694 rte_ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1696 /* reset the hardware with the new settings */
1697 diag = hw->mac.ops.start_hw(hw);
1703 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1707 rte_intr_callback_register(intr_handle,
1708 ixgbevf_dev_interrupt_handler, eth_dev);
1709 rte_intr_enable(intr_handle);
1710 ixgbevf_intr_enable(eth_dev);
1712 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1713 eth_dev->data->port_id, pci_dev->id.vendor_id,
1714 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1719 /* Virtual Function device uninit */
1722 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1724 PMD_INIT_FUNC_TRACE();
1726 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1729 ixgbevf_dev_close(eth_dev);
1735 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1736 struct rte_pci_device *pci_dev)
1738 char name[RTE_ETH_NAME_MAX_LEN];
1739 struct rte_eth_dev *pf_ethdev;
1740 struct rte_eth_devargs eth_da;
1743 if (pci_dev->device.devargs) {
1744 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1749 memset(ð_da, 0, sizeof(eth_da));
1751 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1752 sizeof(struct ixgbe_adapter),
1753 eth_dev_pci_specific_init, pci_dev,
1754 eth_ixgbe_dev_init, NULL);
1756 if (retval || eth_da.nb_representor_ports < 1)
1759 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1760 if (pf_ethdev == NULL)
1763 /* probe VF representor ports */
1764 for (i = 0; i < eth_da.nb_representor_ports; i++) {
1765 struct ixgbe_vf_info *vfinfo;
1766 struct ixgbe_vf_representor representor;
1768 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1769 pf_ethdev->data->dev_private);
1770 if (vfinfo == NULL) {
1772 "no virtual functions supported by PF");
1776 representor.vf_id = eth_da.representor_ports[i];
1777 representor.switch_domain_id = vfinfo->switch_domain_id;
1778 representor.pf_ethdev = pf_ethdev;
1780 /* representor port net_bdf_port */
1781 snprintf(name, sizeof(name), "net_%s_representor_%d",
1782 pci_dev->device.name,
1783 eth_da.representor_ports[i]);
1785 retval = rte_eth_dev_create(&pci_dev->device, name,
1786 sizeof(struct ixgbe_vf_representor), NULL, NULL,
1787 ixgbe_vf_representor_init, &representor);
1790 PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1791 "representor %s.", name);
1797 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1799 struct rte_eth_dev *ethdev;
1801 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1805 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1806 return rte_eth_dev_pci_generic_remove(pci_dev,
1807 ixgbe_vf_representor_uninit);
1809 return rte_eth_dev_pci_generic_remove(pci_dev,
1810 eth_ixgbe_dev_uninit);
1813 static struct rte_pci_driver rte_ixgbe_pmd = {
1814 .id_table = pci_id_ixgbe_map,
1815 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1816 .probe = eth_ixgbe_pci_probe,
1817 .remove = eth_ixgbe_pci_remove,
1820 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1821 struct rte_pci_device *pci_dev)
1823 return rte_eth_dev_pci_generic_probe(pci_dev,
1824 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1827 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1829 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1833 * virtual function driver struct
1835 static struct rte_pci_driver rte_ixgbevf_pmd = {
1836 .id_table = pci_id_ixgbevf_map,
1837 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1838 .probe = eth_ixgbevf_pci_probe,
1839 .remove = eth_ixgbevf_pci_remove,
1843 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1845 struct ixgbe_hw *hw =
1846 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1847 struct ixgbe_vfta *shadow_vfta =
1848 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1853 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1854 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1855 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1860 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1862 /* update local VFTA copy */
1863 shadow_vfta->vfta[vid_idx] = vfta;
1869 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1872 ixgbe_vlan_hw_strip_enable(dev, queue);
1874 ixgbe_vlan_hw_strip_disable(dev, queue);
1878 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1879 enum rte_vlan_type vlan_type,
1882 struct ixgbe_hw *hw =
1883 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1888 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1889 qinq &= IXGBE_DMATXCTL_GDV;
1891 switch (vlan_type) {
1892 case ETH_VLAN_TYPE_INNER:
1894 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1895 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1896 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1897 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1898 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1899 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1900 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1903 PMD_DRV_LOG(ERR, "Inner type is not supported"
1907 case ETH_VLAN_TYPE_OUTER:
1909 /* Only the high 16-bits is valid */
1910 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1911 IXGBE_EXVET_VET_EXT_SHIFT);
1913 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1914 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1915 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1916 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1917 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1918 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1919 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1925 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1933 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1935 struct ixgbe_hw *hw =
1936 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1939 PMD_INIT_FUNC_TRACE();
1941 /* Filter Table Disable */
1942 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1943 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1945 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1949 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1951 struct ixgbe_hw *hw =
1952 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1953 struct ixgbe_vfta *shadow_vfta =
1954 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1958 PMD_INIT_FUNC_TRACE();
1960 /* Filter Table Enable */
1961 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1962 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1963 vlnctrl |= IXGBE_VLNCTRL_VFE;
1965 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1967 /* write whatever is in local vfta copy */
1968 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1969 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1973 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1975 struct ixgbe_hwstrip *hwstrip =
1976 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1977 struct ixgbe_rx_queue *rxq;
1979 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1983 IXGBE_SET_HWSTRIP(hwstrip, queue);
1985 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1987 if (queue >= dev->data->nb_rx_queues)
1990 rxq = dev->data->rx_queues[queue];
1993 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1994 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1996 rxq->vlan_flags = PKT_RX_VLAN;
1997 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2002 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2004 struct ixgbe_hw *hw =
2005 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2008 PMD_INIT_FUNC_TRACE();
2010 if (hw->mac.type == ixgbe_mac_82598EB) {
2011 /* No queue level support */
2012 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2016 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2017 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2018 ctrl &= ~IXGBE_RXDCTL_VME;
2019 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2021 /* record those setting for HW strip per queue */
2022 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2026 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2028 struct ixgbe_hw *hw =
2029 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2032 PMD_INIT_FUNC_TRACE();
2034 if (hw->mac.type == ixgbe_mac_82598EB) {
2035 /* No queue level supported */
2036 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2040 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2041 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2042 ctrl |= IXGBE_RXDCTL_VME;
2043 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2045 /* record those setting for HW strip per queue */
2046 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2050 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2052 struct ixgbe_hw *hw =
2053 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2056 PMD_INIT_FUNC_TRACE();
2058 /* DMATXCTRL: Geric Double VLAN Disable */
2059 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2060 ctrl &= ~IXGBE_DMATXCTL_GDV;
2061 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2063 /* CTRL_EXT: Global Double VLAN Disable */
2064 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2065 ctrl &= ~IXGBE_EXTENDED_VLAN;
2066 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2071 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2073 struct ixgbe_hw *hw =
2074 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2077 PMD_INIT_FUNC_TRACE();
2079 /* DMATXCTRL: Geric Double VLAN Enable */
2080 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2081 ctrl |= IXGBE_DMATXCTL_GDV;
2082 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2084 /* CTRL_EXT: Global Double VLAN Enable */
2085 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2086 ctrl |= IXGBE_EXTENDED_VLAN;
2087 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2089 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2090 if (hw->mac.type == ixgbe_mac_X550 ||
2091 hw->mac.type == ixgbe_mac_X550EM_x ||
2092 hw->mac.type == ixgbe_mac_X550EM_a) {
2093 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2094 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2095 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2099 * VET EXT field in the EXVET register = 0x8100 by default
2100 * So no need to change. Same to VT field of DMATXCTL register
2105 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2107 struct ixgbe_hw *hw =
2108 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2109 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2112 struct ixgbe_rx_queue *rxq;
2115 PMD_INIT_FUNC_TRACE();
2117 if (hw->mac.type == ixgbe_mac_82598EB) {
2118 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2119 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2120 ctrl |= IXGBE_VLNCTRL_VME;
2121 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2123 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2124 ctrl &= ~IXGBE_VLNCTRL_VME;
2125 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2129 * Other 10G NIC, the VLAN strip can be setup
2130 * per queue in RXDCTL
2132 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2133 rxq = dev->data->rx_queues[i];
2134 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2135 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2136 ctrl |= IXGBE_RXDCTL_VME;
2139 ctrl &= ~IXGBE_RXDCTL_VME;
2142 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2144 /* record those setting for HW strip per queue */
2145 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2151 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2154 struct rte_eth_rxmode *rxmode;
2155 struct ixgbe_rx_queue *rxq;
2157 if (mask & ETH_VLAN_STRIP_MASK) {
2158 rxmode = &dev->data->dev_conf.rxmode;
2159 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2160 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2161 rxq = dev->data->rx_queues[i];
2162 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2165 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2166 rxq = dev->data->rx_queues[i];
2167 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2173 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2175 struct rte_eth_rxmode *rxmode;
2176 rxmode = &dev->data->dev_conf.rxmode;
2178 if (mask & ETH_VLAN_STRIP_MASK) {
2179 ixgbe_vlan_hw_strip_config(dev);
2182 if (mask & ETH_VLAN_FILTER_MASK) {
2183 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2184 ixgbe_vlan_hw_filter_enable(dev);
2186 ixgbe_vlan_hw_filter_disable(dev);
2189 if (mask & ETH_VLAN_EXTEND_MASK) {
2190 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2191 ixgbe_vlan_hw_extend_enable(dev);
2193 ixgbe_vlan_hw_extend_disable(dev);
2200 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2202 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2204 ixgbe_vlan_offload_config(dev, mask);
2210 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2212 struct ixgbe_hw *hw =
2213 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2214 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2215 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2217 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2218 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2222 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2224 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2229 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2232 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2238 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2239 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2240 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2241 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2246 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2248 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2249 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2250 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2251 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2253 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2254 /* check multi-queue mode */
2255 switch (dev_conf->rxmode.mq_mode) {
2256 case ETH_MQ_RX_VMDQ_DCB:
2257 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2259 case ETH_MQ_RX_VMDQ_DCB_RSS:
2260 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2261 PMD_INIT_LOG(ERR, "SRIOV active,"
2262 " unsupported mq_mode rx %d.",
2263 dev_conf->rxmode.mq_mode);
2266 case ETH_MQ_RX_VMDQ_RSS:
2267 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2268 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2269 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2270 PMD_INIT_LOG(ERR, "SRIOV is active,"
2271 " invalid queue number"
2272 " for VMDQ RSS, allowed"
2273 " value are 1, 2 or 4.");
2277 case ETH_MQ_RX_VMDQ_ONLY:
2278 case ETH_MQ_RX_NONE:
2279 /* if nothing mq mode configure, use default scheme */
2280 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2282 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2283 /* SRIOV only works in VMDq enable mode */
2284 PMD_INIT_LOG(ERR, "SRIOV is active,"
2285 " wrong mq_mode rx %d.",
2286 dev_conf->rxmode.mq_mode);
2290 switch (dev_conf->txmode.mq_mode) {
2291 case ETH_MQ_TX_VMDQ_DCB:
2292 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2293 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2295 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2296 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2300 /* check valid queue number */
2301 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2302 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2303 PMD_INIT_LOG(ERR, "SRIOV is active,"
2304 " nb_rx_q=%d nb_tx_q=%d queue number"
2305 " must be less than or equal to %d.",
2307 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2311 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2312 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2316 /* check configuration for vmdb+dcb mode */
2317 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2318 const struct rte_eth_vmdq_dcb_conf *conf;
2320 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2321 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2322 IXGBE_VMDQ_DCB_NB_QUEUES);
2325 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2326 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2327 conf->nb_queue_pools == ETH_32_POOLS)) {
2328 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2329 " nb_queue_pools must be %d or %d.",
2330 ETH_16_POOLS, ETH_32_POOLS);
2334 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2335 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2337 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2338 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2339 IXGBE_VMDQ_DCB_NB_QUEUES);
2342 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2343 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2344 conf->nb_queue_pools == ETH_32_POOLS)) {
2345 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2346 " nb_queue_pools != %d and"
2347 " nb_queue_pools != %d.",
2348 ETH_16_POOLS, ETH_32_POOLS);
2353 /* For DCB mode check our configuration before we go further */
2354 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2355 const struct rte_eth_dcb_rx_conf *conf;
2357 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2358 if (!(conf->nb_tcs == ETH_4_TCS ||
2359 conf->nb_tcs == ETH_8_TCS)) {
2360 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2361 " and nb_tcs != %d.",
2362 ETH_4_TCS, ETH_8_TCS);
2367 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2368 const struct rte_eth_dcb_tx_conf *conf;
2370 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2371 if (!(conf->nb_tcs == ETH_4_TCS ||
2372 conf->nb_tcs == ETH_8_TCS)) {
2373 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2374 " and nb_tcs != %d.",
2375 ETH_4_TCS, ETH_8_TCS);
2381 * When DCB/VT is off, maximum number of queues changes,
2382 * except for 82598EB, which remains constant.
2384 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2385 hw->mac.type != ixgbe_mac_82598EB) {
2386 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2388 "Neither VT nor DCB are enabled, "
2390 IXGBE_NONE_MODE_TX_NB_QUEUES);
2399 ixgbe_dev_configure(struct rte_eth_dev *dev)
2401 struct ixgbe_interrupt *intr =
2402 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2403 struct ixgbe_adapter *adapter = dev->data->dev_private;
2406 PMD_INIT_FUNC_TRACE();
2408 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2409 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2411 /* multipe queue mode checking */
2412 ret = ixgbe_check_mq_mode(dev);
2414 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2419 /* set flag to update link status after init */
2420 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2423 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2424 * allocation or vector Rx preconditions we will reset it.
2426 adapter->rx_bulk_alloc_allowed = true;
2427 adapter->rx_vec_allowed = true;
2433 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2435 struct ixgbe_hw *hw =
2436 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2437 struct ixgbe_interrupt *intr =
2438 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2441 /* only set up it on X550EM_X */
2442 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2443 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2444 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2445 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2446 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2447 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2452 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2453 uint16_t tx_rate, uint64_t q_msk)
2455 struct ixgbe_hw *hw;
2456 struct ixgbe_vf_info *vfinfo;
2457 struct rte_eth_link link;
2458 uint8_t nb_q_per_pool;
2459 uint32_t queue_stride;
2460 uint32_t queue_idx, idx = 0, vf_idx;
2462 uint16_t total_rate = 0;
2463 struct rte_pci_device *pci_dev;
2466 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2467 ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2471 if (vf >= pci_dev->max_vfs)
2474 if (tx_rate > link.link_speed)
2480 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2481 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2482 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2483 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2484 queue_idx = vf * queue_stride;
2485 queue_end = queue_idx + nb_q_per_pool - 1;
2486 if (queue_end >= hw->mac.max_tx_queues)
2490 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2493 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2495 total_rate += vfinfo[vf_idx].tx_rate[idx];
2501 /* Store tx_rate for this vf. */
2502 for (idx = 0; idx < nb_q_per_pool; idx++) {
2503 if (((uint64_t)0x1 << idx) & q_msk) {
2504 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2505 vfinfo[vf].tx_rate[idx] = tx_rate;
2506 total_rate += tx_rate;
2510 if (total_rate > dev->data->dev_link.link_speed) {
2511 /* Reset stored TX rate of the VF if it causes exceed
2514 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2518 /* Set RTTBCNRC of each queue/pool for vf X */
2519 for (; queue_idx <= queue_end; queue_idx++) {
2521 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2529 * Configure device link speed and setup link.
2530 * It returns 0 on success.
2533 ixgbe_dev_start(struct rte_eth_dev *dev)
2535 struct ixgbe_hw *hw =
2536 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2537 struct ixgbe_vf_info *vfinfo =
2538 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2539 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2540 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2541 uint32_t intr_vector = 0;
2542 int err, link_up = 0, negotiate = 0;
2544 uint32_t allowed_speeds = 0;
2548 uint32_t *link_speeds;
2549 struct ixgbe_tm_conf *tm_conf =
2550 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2551 struct ixgbe_macsec_setting *macsec_ctrl =
2552 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2554 PMD_INIT_FUNC_TRACE();
2556 /* IXGBE devices don't support:
2557 * - half duplex (checked afterwards for valid speeds)
2558 * - fixed speed: TODO implement
2560 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2562 "Invalid link_speeds for port %u, fix speed not supported",
2563 dev->data->port_id);
2567 /* Stop the link setup handler before resetting the HW. */
2568 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2570 /* disable uio/vfio intr/eventfd mapping */
2571 rte_intr_disable(intr_handle);
2574 hw->adapter_stopped = 0;
2575 ixgbe_stop_adapter(hw);
2577 /* reinitialize adapter
2578 * this calls reset and start
2580 status = ixgbe_pf_reset_hw(hw);
2583 hw->mac.ops.start_hw(hw);
2584 hw->mac.get_link_status = true;
2586 /* configure PF module if SRIOV enabled */
2587 ixgbe_pf_host_configure(dev);
2589 ixgbe_dev_phy_intr_setup(dev);
2591 /* check and configure queue intr-vector mapping */
2592 if ((rte_intr_cap_multiple(intr_handle) ||
2593 !RTE_ETH_DEV_SRIOV(dev).active) &&
2594 dev->data->dev_conf.intr_conf.rxq != 0) {
2595 intr_vector = dev->data->nb_rx_queues;
2596 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2597 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2598 IXGBE_MAX_INTR_QUEUE_NUM);
2601 if (rte_intr_efd_enable(intr_handle, intr_vector))
2605 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2606 intr_handle->intr_vec =
2607 rte_zmalloc("intr_vec",
2608 dev->data->nb_rx_queues * sizeof(int), 0);
2609 if (intr_handle->intr_vec == NULL) {
2610 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2611 " intr_vec", dev->data->nb_rx_queues);
2616 /* confiugre msix for sleep until rx interrupt */
2617 ixgbe_configure_msix(dev);
2619 /* initialize transmission unit */
2620 ixgbe_dev_tx_init(dev);
2622 /* This can fail when allocating mbufs for descriptor rings */
2623 err = ixgbe_dev_rx_init(dev);
2625 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2629 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2630 ETH_VLAN_EXTEND_MASK;
2631 err = ixgbe_vlan_offload_config(dev, mask);
2633 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2637 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2638 /* Enable vlan filtering for VMDq */
2639 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2642 /* Configure DCB hw */
2643 ixgbe_configure_dcb(dev);
2645 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2646 err = ixgbe_fdir_configure(dev);
2651 /* Restore vf rate limit */
2652 if (vfinfo != NULL) {
2653 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2654 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2655 if (vfinfo[vf].tx_rate[idx] != 0)
2656 ixgbe_set_vf_rate_limit(
2658 vfinfo[vf].tx_rate[idx],
2662 ixgbe_restore_statistics_mapping(dev);
2664 err = ixgbe_dev_rxtx_start(dev);
2666 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2670 /* Skip link setup if loopback mode is enabled. */
2671 if (dev->data->dev_conf.lpbk_mode != 0) {
2672 err = ixgbe_check_supported_loopback_mode(dev);
2674 PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2677 goto skip_link_setup;
2681 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2682 err = hw->mac.ops.setup_sfp(hw);
2687 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2688 /* Turn on the copper */
2689 ixgbe_set_phy_power(hw, true);
2691 /* Turn on the laser */
2692 ixgbe_enable_tx_laser(hw);
2695 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2698 dev->data->dev_link.link_status = link_up;
2700 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2704 switch (hw->mac.type) {
2705 case ixgbe_mac_X550:
2706 case ixgbe_mac_X550EM_x:
2707 case ixgbe_mac_X550EM_a:
2708 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2709 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G |
2711 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2712 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2713 allowed_speeds = ETH_LINK_SPEED_10M |
2714 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2717 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2721 link_speeds = &dev->data->dev_conf.link_speeds;
2722 if (*link_speeds & ~allowed_speeds) {
2723 PMD_INIT_LOG(ERR, "Invalid link setting");
2728 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2729 switch (hw->mac.type) {
2730 case ixgbe_mac_82598EB:
2731 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2733 case ixgbe_mac_82599EB:
2734 case ixgbe_mac_X540:
2735 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2737 case ixgbe_mac_X550:
2738 case ixgbe_mac_X550EM_x:
2739 case ixgbe_mac_X550EM_a:
2740 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2743 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2746 if (*link_speeds & ETH_LINK_SPEED_10G)
2747 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2748 if (*link_speeds & ETH_LINK_SPEED_5G)
2749 speed |= IXGBE_LINK_SPEED_5GB_FULL;
2750 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2751 speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2752 if (*link_speeds & ETH_LINK_SPEED_1G)
2753 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2754 if (*link_speeds & ETH_LINK_SPEED_100M)
2755 speed |= IXGBE_LINK_SPEED_100_FULL;
2756 if (*link_speeds & ETH_LINK_SPEED_10M)
2757 speed |= IXGBE_LINK_SPEED_10_FULL;
2760 err = ixgbe_setup_link(hw, speed, link_up);
2766 if (rte_intr_allow_others(intr_handle)) {
2767 /* check if lsc interrupt is enabled */
2768 if (dev->data->dev_conf.intr_conf.lsc != 0)
2769 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2771 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2772 ixgbe_dev_macsec_interrupt_setup(dev);
2774 rte_intr_callback_unregister(intr_handle,
2775 ixgbe_dev_interrupt_handler, dev);
2776 if (dev->data->dev_conf.intr_conf.lsc != 0)
2777 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2778 " no intr multiplex");
2781 /* check if rxq interrupt is enabled */
2782 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2783 rte_intr_dp_is_en(intr_handle))
2784 ixgbe_dev_rxq_interrupt_setup(dev);
2786 /* enable uio/vfio intr/eventfd mapping */
2787 rte_intr_enable(intr_handle);
2789 /* resume enabled intr since hw reset */
2790 ixgbe_enable_intr(dev);
2791 ixgbe_l2_tunnel_conf(dev);
2792 ixgbe_filter_restore(dev);
2794 if (tm_conf->root && !tm_conf->committed)
2795 PMD_DRV_LOG(WARNING,
2796 "please call hierarchy_commit() "
2797 "before starting the port");
2800 * Update link status right before return, because it may
2801 * start link configuration process in a separate thread.
2803 ixgbe_dev_link_update(dev, 0);
2805 /* setup the macsec ctrl register */
2806 ixgbe_dev_macsec_register_enable(dev, macsec_ctrl);
2811 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2812 ixgbe_dev_clear_queues(dev);
2817 * Stop device: disable rx and tx functions to allow for reconfiguring.
2820 ixgbe_dev_stop(struct rte_eth_dev *dev)
2822 struct rte_eth_link link;
2823 struct ixgbe_adapter *adapter = dev->data->dev_private;
2824 struct ixgbe_hw *hw =
2825 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2826 struct ixgbe_vf_info *vfinfo =
2827 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2828 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2829 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2831 struct ixgbe_tm_conf *tm_conf =
2832 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2834 if (hw->adapter_stopped)
2837 PMD_INIT_FUNC_TRACE();
2839 /* disable mecsec register */
2840 ixgbe_dev_macsec_register_disable(dev);
2842 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2844 /* disable interrupts */
2845 ixgbe_disable_intr(hw);
2848 ixgbe_pf_reset_hw(hw);
2849 hw->adapter_stopped = 0;
2852 ixgbe_stop_adapter(hw);
2854 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2855 vfinfo[vf].clear_to_send = false;
2857 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2858 /* Turn off the copper */
2859 ixgbe_set_phy_power(hw, false);
2861 /* Turn off the laser */
2862 ixgbe_disable_tx_laser(hw);
2865 ixgbe_dev_clear_queues(dev);
2867 /* Clear stored conf */
2868 dev->data->scattered_rx = 0;
2871 /* Clear recorded link status */
2872 memset(&link, 0, sizeof(link));
2873 rte_eth_linkstatus_set(dev, &link);
2875 if (!rte_intr_allow_others(intr_handle))
2876 /* resume to the default handler */
2877 rte_intr_callback_register(intr_handle,
2878 ixgbe_dev_interrupt_handler,
2881 /* Clean datapath event and queue/vec mapping */
2882 rte_intr_efd_disable(intr_handle);
2883 if (intr_handle->intr_vec != NULL) {
2884 rte_free(intr_handle->intr_vec);
2885 intr_handle->intr_vec = NULL;
2888 /* reset hierarchy commit */
2889 tm_conf->committed = false;
2891 adapter->rss_reta_updated = 0;
2893 hw->adapter_stopped = true;
2897 * Set device link up: enable tx.
2900 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2902 struct ixgbe_hw *hw =
2903 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2904 if (hw->mac.type == ixgbe_mac_82599EB) {
2905 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2906 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2907 /* Not suported in bypass mode */
2908 PMD_INIT_LOG(ERR, "Set link up is not supported "
2909 "by device id 0x%x", hw->device_id);
2915 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2916 /* Turn on the copper */
2917 ixgbe_set_phy_power(hw, true);
2919 /* Turn on the laser */
2920 ixgbe_enable_tx_laser(hw);
2921 ixgbe_dev_link_update(dev, 0);
2928 * Set device link down: disable tx.
2931 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2933 struct ixgbe_hw *hw =
2934 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2935 if (hw->mac.type == ixgbe_mac_82599EB) {
2936 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2937 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2938 /* Not suported in bypass mode */
2939 PMD_INIT_LOG(ERR, "Set link down is not supported "
2940 "by device id 0x%x", hw->device_id);
2946 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2947 /* Turn off the copper */
2948 ixgbe_set_phy_power(hw, false);
2950 /* Turn off the laser */
2951 ixgbe_disable_tx_laser(hw);
2952 ixgbe_dev_link_update(dev, 0);
2959 * Reset and stop device.
2962 ixgbe_dev_close(struct rte_eth_dev *dev)
2964 struct ixgbe_hw *hw =
2965 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2966 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2967 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2971 PMD_INIT_FUNC_TRACE();
2973 ixgbe_pf_reset_hw(hw);
2975 ixgbe_dev_stop(dev);
2977 ixgbe_dev_free_queues(dev);
2979 ixgbe_disable_pcie_master(hw);
2981 /* reprogram the RAR[0] in case user changed it. */
2982 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2984 dev->dev_ops = NULL;
2985 dev->rx_pkt_burst = NULL;
2986 dev->tx_pkt_burst = NULL;
2988 /* Unlock any pending hardware semaphore */
2989 ixgbe_swfw_lock_reset(hw);
2991 /* disable uio intr before callback unregister */
2992 rte_intr_disable(intr_handle);
2995 ret = rte_intr_callback_unregister(intr_handle,
2996 ixgbe_dev_interrupt_handler, dev);
2997 if (ret >= 0 || ret == -ENOENT) {
2999 } else if (ret != -EAGAIN) {
3001 "intr callback unregister failed: %d",
3005 } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3007 /* cancel the delay handler before remove dev */
3008 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3010 /* uninitialize PF if max_vfs not zero */
3011 ixgbe_pf_host_uninit(dev);
3013 /* remove all the fdir filters & hash */
3014 ixgbe_fdir_filter_uninit(dev);
3016 /* remove all the L2 tunnel filters & hash */
3017 ixgbe_l2_tn_filter_uninit(dev);
3019 /* Remove all ntuple filters of the device */
3020 ixgbe_ntuple_filter_uninit(dev);
3022 /* clear all the filters list */
3023 ixgbe_filterlist_flush();
3025 /* Remove all Traffic Manager configuration */
3026 ixgbe_tm_conf_uninit(dev);
3028 #ifdef RTE_LIBRTE_SECURITY
3029 rte_free(dev->security_ctx);
3038 ixgbe_dev_reset(struct rte_eth_dev *dev)
3042 /* When a DPDK PMD PF begin to reset PF port, it should notify all
3043 * its VF to make them align with it. The detailed notification
3044 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3045 * To avoid unexpected behavior in VF, currently reset of PF with
3046 * SR-IOV activation is not supported. It might be supported later.
3048 if (dev->data->sriov.active)
3051 ret = eth_ixgbe_dev_uninit(dev);
3055 ret = eth_ixgbe_dev_init(dev, NULL);
3061 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3062 struct ixgbe_hw_stats *hw_stats,
3063 struct ixgbe_macsec_stats *macsec_stats,
3064 uint64_t *total_missed_rx, uint64_t *total_qbrc,
3065 uint64_t *total_qprc, uint64_t *total_qprdc)
3067 uint32_t bprc, lxon, lxoff, total;
3068 uint32_t delta_gprc = 0;
3070 /* Workaround for RX byte count not including CRC bytes when CRC
3071 * strip is enabled. CRC bytes are removed from counters when crc_strip
3074 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3075 IXGBE_HLREG0_RXCRCSTRP);
3077 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3078 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3079 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3080 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3082 for (i = 0; i < 8; i++) {
3083 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3085 /* global total per queue */
3086 hw_stats->mpc[i] += mp;
3087 /* Running comprehensive total for stats display */
3088 *total_missed_rx += hw_stats->mpc[i];
3089 if (hw->mac.type == ixgbe_mac_82598EB) {
3090 hw_stats->rnbc[i] +=
3091 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3092 hw_stats->pxonrxc[i] +=
3093 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3094 hw_stats->pxoffrxc[i] +=
3095 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3097 hw_stats->pxonrxc[i] +=
3098 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3099 hw_stats->pxoffrxc[i] +=
3100 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3101 hw_stats->pxon2offc[i] +=
3102 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3104 hw_stats->pxontxc[i] +=
3105 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3106 hw_stats->pxofftxc[i] +=
3107 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3109 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3110 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3111 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3112 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3114 delta_gprc += delta_qprc;
3116 hw_stats->qprc[i] += delta_qprc;
3117 hw_stats->qptc[i] += delta_qptc;
3119 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3120 hw_stats->qbrc[i] +=
3121 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3123 hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3125 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3126 hw_stats->qbtc[i] +=
3127 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3129 hw_stats->qprdc[i] += delta_qprdc;
3130 *total_qprdc += hw_stats->qprdc[i];
3132 *total_qprc += hw_stats->qprc[i];
3133 *total_qbrc += hw_stats->qbrc[i];
3135 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3136 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3137 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3140 * An errata states that gprc actually counts good + missed packets:
3141 * Workaround to set gprc to summated queue packet receives
3143 hw_stats->gprc = *total_qprc;
3145 if (hw->mac.type != ixgbe_mac_82598EB) {
3146 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3147 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3148 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3149 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3150 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3151 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3152 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3153 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3155 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3156 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3157 /* 82598 only has a counter in the high register */
3158 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3159 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3160 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3162 uint64_t old_tpr = hw_stats->tpr;
3164 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3165 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3168 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3170 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3171 hw_stats->gptc += delta_gptc;
3172 hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3173 hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3176 * Workaround: mprc hardware is incorrectly counting
3177 * broadcasts, so for now we subtract those.
3179 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3180 hw_stats->bprc += bprc;
3181 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3182 if (hw->mac.type == ixgbe_mac_82598EB)
3183 hw_stats->mprc -= bprc;
3185 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3186 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3187 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3188 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3189 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3190 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3192 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3193 hw_stats->lxontxc += lxon;
3194 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3195 hw_stats->lxofftxc += lxoff;
3196 total = lxon + lxoff;
3198 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3199 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3200 hw_stats->gptc -= total;
3201 hw_stats->mptc -= total;
3202 hw_stats->ptc64 -= total;
3203 hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3205 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3206 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3207 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3208 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3209 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3210 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3211 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3212 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3213 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3214 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3215 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3216 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3217 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3218 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3219 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3220 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3221 /* Only read FCOE on 82599 */
3222 if (hw->mac.type != ixgbe_mac_82598EB) {
3223 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3224 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3225 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3226 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3227 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3230 /* Flow Director Stats registers */
3231 if (hw->mac.type != ixgbe_mac_82598EB) {
3232 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3233 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3234 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3235 IXGBE_FDIRUSTAT) & 0xFFFF;
3236 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3237 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3238 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3239 IXGBE_FDIRFSTAT) & 0xFFFF;
3240 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3241 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3243 /* MACsec Stats registers */
3244 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3245 macsec_stats->out_pkts_encrypted +=
3246 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3247 macsec_stats->out_pkts_protected +=
3248 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3249 macsec_stats->out_octets_encrypted +=
3250 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3251 macsec_stats->out_octets_protected +=
3252 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3253 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3254 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3255 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3256 macsec_stats->in_pkts_unknownsci +=
3257 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3258 macsec_stats->in_octets_decrypted +=
3259 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3260 macsec_stats->in_octets_validated +=
3261 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3262 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3263 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3264 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3265 for (i = 0; i < 2; i++) {
3266 macsec_stats->in_pkts_ok +=
3267 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3268 macsec_stats->in_pkts_invalid +=
3269 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3270 macsec_stats->in_pkts_notvalid +=
3271 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3273 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3274 macsec_stats->in_pkts_notusingsa +=
3275 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3279 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3282 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3284 struct ixgbe_hw *hw =
3285 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3286 struct ixgbe_hw_stats *hw_stats =
3287 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3288 struct ixgbe_macsec_stats *macsec_stats =
3289 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3290 dev->data->dev_private);
3291 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3294 total_missed_rx = 0;
3299 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3300 &total_qbrc, &total_qprc, &total_qprdc);
3305 /* Fill out the rte_eth_stats statistics structure */
3306 stats->ipackets = total_qprc;
3307 stats->ibytes = total_qbrc;
3308 stats->opackets = hw_stats->gptc;
3309 stats->obytes = hw_stats->gotc;
3311 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3312 stats->q_ipackets[i] = hw_stats->qprc[i];
3313 stats->q_opackets[i] = hw_stats->qptc[i];
3314 stats->q_ibytes[i] = hw_stats->qbrc[i];
3315 stats->q_obytes[i] = hw_stats->qbtc[i];
3316 stats->q_errors[i] = hw_stats->qprdc[i];
3320 stats->imissed = total_missed_rx;
3321 stats->ierrors = hw_stats->crcerrs +
3338 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3340 struct ixgbe_hw_stats *stats =
3341 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3343 /* HW registers are cleared on read */
3344 ixgbe_dev_stats_get(dev, NULL);
3346 /* Reset software totals */
3347 memset(stats, 0, sizeof(*stats));
3352 /* This function calculates the number of xstats based on the current config */
3354 ixgbe_xstats_calc_num(void) {
3355 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3356 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3357 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3360 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3361 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3363 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3364 unsigned stat, i, count;
3366 if (xstats_names != NULL) {
3369 /* Note: limit >= cnt_stats checked upstream
3370 * in rte_eth_xstats_names()
3373 /* Extended stats from ixgbe_hw_stats */
3374 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3375 strlcpy(xstats_names[count].name,
3376 rte_ixgbe_stats_strings[i].name,
3377 sizeof(xstats_names[count].name));
3382 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3383 strlcpy(xstats_names[count].name,
3384 rte_ixgbe_macsec_strings[i].name,
3385 sizeof(xstats_names[count].name));
3389 /* RX Priority Stats */
3390 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3391 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3392 snprintf(xstats_names[count].name,
3393 sizeof(xstats_names[count].name),
3394 "rx_priority%u_%s", i,
3395 rte_ixgbe_rxq_strings[stat].name);
3400 /* TX Priority Stats */
3401 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3402 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3403 snprintf(xstats_names[count].name,
3404 sizeof(xstats_names[count].name),
3405 "tx_priority%u_%s", i,
3406 rte_ixgbe_txq_strings[stat].name);
3414 static int ixgbe_dev_xstats_get_names_by_id(
3415 struct rte_eth_dev *dev,
3416 struct rte_eth_xstat_name *xstats_names,
3417 const uint64_t *ids,
3421 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3422 unsigned int stat, i, count;
3424 if (xstats_names != NULL) {
3427 /* Note: limit >= cnt_stats checked upstream
3428 * in rte_eth_xstats_names()
3431 /* Extended stats from ixgbe_hw_stats */
3432 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3433 strlcpy(xstats_names[count].name,
3434 rte_ixgbe_stats_strings[i].name,
3435 sizeof(xstats_names[count].name));
3440 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3441 strlcpy(xstats_names[count].name,
3442 rte_ixgbe_macsec_strings[i].name,
3443 sizeof(xstats_names[count].name));
3447 /* RX Priority Stats */
3448 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3449 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3450 snprintf(xstats_names[count].name,
3451 sizeof(xstats_names[count].name),
3452 "rx_priority%u_%s", i,
3453 rte_ixgbe_rxq_strings[stat].name);
3458 /* TX Priority Stats */
3459 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3460 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3461 snprintf(xstats_names[count].name,
3462 sizeof(xstats_names[count].name),
3463 "tx_priority%u_%s", i,
3464 rte_ixgbe_txq_strings[stat].name);
3473 uint16_t size = ixgbe_xstats_calc_num();
3474 struct rte_eth_xstat_name xstats_names_copy[size];
3476 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3479 for (i = 0; i < limit; i++) {
3480 if (ids[i] >= size) {
3481 PMD_INIT_LOG(ERR, "id value isn't valid");
3484 strcpy(xstats_names[i].name,
3485 xstats_names_copy[ids[i]].name);
3490 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3491 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3495 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3498 if (xstats_names != NULL)
3499 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3500 strlcpy(xstats_names[i].name,
3501 rte_ixgbevf_stats_strings[i].name,
3502 sizeof(xstats_names[i].name));
3503 return IXGBEVF_NB_XSTATS;
3507 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3510 struct ixgbe_hw *hw =
3511 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3512 struct ixgbe_hw_stats *hw_stats =
3513 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3514 struct ixgbe_macsec_stats *macsec_stats =
3515 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3516 dev->data->dev_private);
3517 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3518 unsigned i, stat, count = 0;
3520 count = ixgbe_xstats_calc_num();
3525 total_missed_rx = 0;
3530 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3531 &total_qbrc, &total_qprc, &total_qprdc);
3533 /* If this is a reset xstats is NULL, and we have cleared the
3534 * registers by reading them.
3539 /* Extended stats from ixgbe_hw_stats */
3541 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3542 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3543 rte_ixgbe_stats_strings[i].offset);
3544 xstats[count].id = count;
3549 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3550 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3551 rte_ixgbe_macsec_strings[i].offset);
3552 xstats[count].id = count;
3556 /* RX Priority Stats */
3557 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3558 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3559 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3560 rte_ixgbe_rxq_strings[stat].offset +
3561 (sizeof(uint64_t) * i));
3562 xstats[count].id = count;
3567 /* TX Priority Stats */
3568 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3569 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3570 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3571 rte_ixgbe_txq_strings[stat].offset +
3572 (sizeof(uint64_t) * i));
3573 xstats[count].id = count;
3581 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3582 uint64_t *values, unsigned int n)
3585 struct ixgbe_hw *hw =
3586 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3587 struct ixgbe_hw_stats *hw_stats =
3588 IXGBE_DEV_PRIVATE_TO_STATS(
3589 dev->data->dev_private);
3590 struct ixgbe_macsec_stats *macsec_stats =
3591 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3592 dev->data->dev_private);
3593 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3594 unsigned int i, stat, count = 0;
3596 count = ixgbe_xstats_calc_num();
3598 if (!ids && n < count)
3601 total_missed_rx = 0;
3606 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3607 &total_missed_rx, &total_qbrc, &total_qprc,
3610 /* If this is a reset xstats is NULL, and we have cleared the
3611 * registers by reading them.
3613 if (!ids && !values)
3616 /* Extended stats from ixgbe_hw_stats */
3618 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3619 values[count] = *(uint64_t *)(((char *)hw_stats) +
3620 rte_ixgbe_stats_strings[i].offset);
3625 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3626 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3627 rte_ixgbe_macsec_strings[i].offset);
3631 /* RX Priority Stats */
3632 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3633 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3635 *(uint64_t *)(((char *)hw_stats) +
3636 rte_ixgbe_rxq_strings[stat].offset +
3637 (sizeof(uint64_t) * i));
3642 /* TX Priority Stats */
3643 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3644 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3646 *(uint64_t *)(((char *)hw_stats) +
3647 rte_ixgbe_txq_strings[stat].offset +
3648 (sizeof(uint64_t) * i));
3656 uint16_t size = ixgbe_xstats_calc_num();
3657 uint64_t values_copy[size];
3659 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3661 for (i = 0; i < n; i++) {
3662 if (ids[i] >= size) {
3663 PMD_INIT_LOG(ERR, "id value isn't valid");
3666 values[i] = values_copy[ids[i]];
3672 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3674 struct ixgbe_hw_stats *stats =
3675 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3676 struct ixgbe_macsec_stats *macsec_stats =
3677 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3678 dev->data->dev_private);
3680 unsigned count = ixgbe_xstats_calc_num();
3682 /* HW registers are cleared on read */
3683 ixgbe_dev_xstats_get(dev, NULL, count);
3685 /* Reset software totals */
3686 memset(stats, 0, sizeof(*stats));
3687 memset(macsec_stats, 0, sizeof(*macsec_stats));
3693 ixgbevf_update_stats(struct rte_eth_dev *dev)
3695 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3696 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3697 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3699 /* Good Rx packet, include VF loopback */
3700 UPDATE_VF_STAT(IXGBE_VFGPRC,
3701 hw_stats->last_vfgprc, hw_stats->vfgprc);
3703 /* Good Rx octets, include VF loopback */
3704 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3705 hw_stats->last_vfgorc, hw_stats->vfgorc);
3707 /* Good Tx packet, include VF loopback */
3708 UPDATE_VF_STAT(IXGBE_VFGPTC,
3709 hw_stats->last_vfgptc, hw_stats->vfgptc);
3711 /* Good Tx octets, include VF loopback */
3712 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3713 hw_stats->last_vfgotc, hw_stats->vfgotc);
3715 /* Rx Multicst Packet */
3716 UPDATE_VF_STAT(IXGBE_VFMPRC,
3717 hw_stats->last_vfmprc, hw_stats->vfmprc);
3721 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3724 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3725 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3728 if (n < IXGBEVF_NB_XSTATS)
3729 return IXGBEVF_NB_XSTATS;
3731 ixgbevf_update_stats(dev);
3736 /* Extended stats */
3737 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3739 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3740 rte_ixgbevf_stats_strings[i].offset);
3743 return IXGBEVF_NB_XSTATS;
3747 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3749 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3750 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3752 ixgbevf_update_stats(dev);
3757 stats->ipackets = hw_stats->vfgprc;
3758 stats->ibytes = hw_stats->vfgorc;
3759 stats->opackets = hw_stats->vfgptc;
3760 stats->obytes = hw_stats->vfgotc;
3765 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3767 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3768 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3770 /* Sync HW register to the last stats */
3771 ixgbevf_dev_stats_get(dev, NULL);
3773 /* reset HW current stats*/
3774 hw_stats->vfgprc = 0;
3775 hw_stats->vfgorc = 0;
3776 hw_stats->vfgptc = 0;
3777 hw_stats->vfgotc = 0;
3783 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3785 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3786 u16 eeprom_verh, eeprom_verl;
3790 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3791 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3793 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3794 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3796 ret += 1; /* add the size of '\0' */
3797 if (fw_size < (u32)ret)
3804 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3806 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3807 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3808 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3810 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3811 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3812 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3814 * When DCB/VT is off, maximum number of queues changes,
3815 * except for 82598EB, which remains constant.
3817 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3818 hw->mac.type != ixgbe_mac_82598EB)
3819 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3821 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3822 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3823 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3824 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3825 dev_info->max_vfs = pci_dev->max_vfs;
3826 if (hw->mac.type == ixgbe_mac_82598EB)
3827 dev_info->max_vmdq_pools = ETH_16_POOLS;
3829 dev_info->max_vmdq_pools = ETH_64_POOLS;
3830 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3831 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3832 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3833 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3834 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3835 dev_info->rx_queue_offload_capa);
3836 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3837 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3839 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3841 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3842 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3843 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3845 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3850 dev_info->default_txconf = (struct rte_eth_txconf) {
3852 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3853 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3854 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3856 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3857 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3861 dev_info->rx_desc_lim = rx_desc_lim;
3862 dev_info->tx_desc_lim = tx_desc_lim;
3864 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3865 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3866 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3868 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3869 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3870 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3871 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3872 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3874 if (hw->mac.type == ixgbe_mac_X540 ||
3875 hw->mac.type == ixgbe_mac_X540_vf ||
3876 hw->mac.type == ixgbe_mac_X550 ||
3877 hw->mac.type == ixgbe_mac_X550_vf) {
3878 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3880 if (hw->mac.type == ixgbe_mac_X550) {
3881 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3882 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3885 /* Driver-preferred Rx/Tx parameters */
3886 dev_info->default_rxportconf.burst_size = 32;
3887 dev_info->default_txportconf.burst_size = 32;
3888 dev_info->default_rxportconf.nb_queues = 1;
3889 dev_info->default_txportconf.nb_queues = 1;
3890 dev_info->default_rxportconf.ring_size = 256;
3891 dev_info->default_txportconf.ring_size = 256;
3896 static const uint32_t *
3897 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3899 static const uint32_t ptypes[] = {
3900 /* For non-vec functions,
3901 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3902 * for vec functions,
3903 * refers to _recv_raw_pkts_vec().
3907 RTE_PTYPE_L3_IPV4_EXT,
3909 RTE_PTYPE_L3_IPV6_EXT,
3913 RTE_PTYPE_TUNNEL_IP,
3914 RTE_PTYPE_INNER_L3_IPV6,
3915 RTE_PTYPE_INNER_L3_IPV6_EXT,
3916 RTE_PTYPE_INNER_L4_TCP,
3917 RTE_PTYPE_INNER_L4_UDP,
3921 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3922 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3923 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3924 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3927 #if defined(RTE_ARCH_X86) || defined(RTE_MACHINE_CPUFLAG_NEON)
3928 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3929 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3936 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3937 struct rte_eth_dev_info *dev_info)
3939 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3940 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3942 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3943 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3944 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3945 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3946 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3947 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3948 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3949 dev_info->max_vfs = pci_dev->max_vfs;
3950 if (hw->mac.type == ixgbe_mac_82598EB)
3951 dev_info->max_vmdq_pools = ETH_16_POOLS;
3953 dev_info->max_vmdq_pools = ETH_64_POOLS;
3954 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3955 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3956 dev_info->rx_queue_offload_capa);
3957 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3958 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3959 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3960 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3961 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3963 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3965 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3966 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3967 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3969 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3974 dev_info->default_txconf = (struct rte_eth_txconf) {
3976 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3977 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3978 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3980 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3981 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3985 dev_info->rx_desc_lim = rx_desc_lim;
3986 dev_info->tx_desc_lim = tx_desc_lim;
3992 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3993 int *link_up, int wait_to_complete)
3995 struct ixgbe_adapter *adapter = container_of(hw,
3996 struct ixgbe_adapter, hw);
3997 struct ixgbe_mbx_info *mbx = &hw->mbx;
3998 struct ixgbe_mac_info *mac = &hw->mac;
3999 uint32_t links_reg, in_msg;
4002 /* If we were hit with a reset drop the link */
4003 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4004 mac->get_link_status = true;
4006 if (!mac->get_link_status)
4009 /* if link status is down no point in checking to see if pf is up */
4010 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4011 if (!(links_reg & IXGBE_LINKS_UP))
4014 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4015 * before the link status is correct
4017 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4020 for (i = 0; i < 5; i++) {
4022 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4024 if (!(links_reg & IXGBE_LINKS_UP))
4029 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4030 case IXGBE_LINKS_SPEED_10G_82599:
4031 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4032 if (hw->mac.type >= ixgbe_mac_X550) {
4033 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4034 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4037 case IXGBE_LINKS_SPEED_1G_82599:
4038 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4040 case IXGBE_LINKS_SPEED_100_82599:
4041 *speed = IXGBE_LINK_SPEED_100_FULL;
4042 if (hw->mac.type == ixgbe_mac_X550) {
4043 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4044 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4047 case IXGBE_LINKS_SPEED_10_X550EM_A:
4048 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4049 /* Since Reserved in older MAC's */
4050 if (hw->mac.type >= ixgbe_mac_X550)
4051 *speed = IXGBE_LINK_SPEED_10_FULL;
4054 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4057 if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4058 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4059 mac->get_link_status = true;
4061 mac->get_link_status = false;
4066 /* if the read failed it could just be a mailbox collision, best wait
4067 * until we are called again and don't report an error
4069 if (mbx->ops.read(hw, &in_msg, 1, 0))
4072 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4073 /* msg is not CTS and is NACK we must have lost CTS status */
4074 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4075 mac->get_link_status = false;
4079 /* the pf is talking, if we timed out in the past we reinit */
4080 if (!mbx->timeout) {
4085 /* if we passed all the tests above then the link is up and we no
4086 * longer need to check for link
4088 mac->get_link_status = false;
4091 *link_up = !mac->get_link_status;
4096 ixgbe_dev_setup_link_alarm_handler(void *param)
4098 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4099 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4100 struct ixgbe_interrupt *intr =
4101 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4103 bool autoneg = false;
4105 speed = hw->phy.autoneg_advertised;
4107 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4109 ixgbe_setup_link(hw, speed, true);
4111 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4114 /* return 0 means link status changed, -1 means not changed */
4116 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4117 int wait_to_complete, int vf)
4119 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4120 struct rte_eth_link link;
4121 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4122 struct ixgbe_interrupt *intr =
4123 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4129 memset(&link, 0, sizeof(link));
4130 link.link_status = ETH_LINK_DOWN;
4131 link.link_speed = ETH_SPEED_NUM_NONE;
4132 link.link_duplex = ETH_LINK_HALF_DUPLEX;
4133 link.link_autoneg = ETH_LINK_AUTONEG;
4135 hw->mac.get_link_status = true;
4137 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4138 return rte_eth_linkstatus_set(dev, &link);
4140 /* check if it needs to wait to complete, if lsc interrupt is enabled */
4141 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4145 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4147 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4150 link.link_speed = ETH_SPEED_NUM_100M;
4151 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4152 return rte_eth_linkstatus_set(dev, &link);
4155 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4156 if ((esdp_reg & IXGBE_ESDP_SDP3))
4160 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4161 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4162 rte_eal_alarm_set(10,
4163 ixgbe_dev_setup_link_alarm_handler, dev);
4165 return rte_eth_linkstatus_set(dev, &link);
4168 link.link_status = ETH_LINK_UP;
4169 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4171 switch (link_speed) {
4173 case IXGBE_LINK_SPEED_UNKNOWN:
4174 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4175 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4176 link.link_speed = ETH_SPEED_NUM_10M;
4178 link.link_speed = ETH_SPEED_NUM_100M;
4181 case IXGBE_LINK_SPEED_100_FULL:
4182 link.link_speed = ETH_SPEED_NUM_100M;
4185 case IXGBE_LINK_SPEED_1GB_FULL:
4186 link.link_speed = ETH_SPEED_NUM_1G;
4189 case IXGBE_LINK_SPEED_2_5GB_FULL:
4190 link.link_speed = ETH_SPEED_NUM_2_5G;
4193 case IXGBE_LINK_SPEED_5GB_FULL:
4194 link.link_speed = ETH_SPEED_NUM_5G;
4197 case IXGBE_LINK_SPEED_10GB_FULL:
4198 link.link_speed = ETH_SPEED_NUM_10G;
4202 return rte_eth_linkstatus_set(dev, &link);
4206 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4208 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4212 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4214 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4218 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4220 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4223 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4224 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4225 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4231 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4233 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4236 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4237 fctrl &= (~IXGBE_FCTRL_UPE);
4238 if (dev->data->all_multicast == 1)
4239 fctrl |= IXGBE_FCTRL_MPE;
4241 fctrl &= (~IXGBE_FCTRL_MPE);
4242 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4248 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4250 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4253 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4254 fctrl |= IXGBE_FCTRL_MPE;
4255 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4261 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4263 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4266 if (dev->data->promiscuous == 1)
4267 return 0; /* must remain in all_multicast mode */
4269 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4270 fctrl &= (~IXGBE_FCTRL_MPE);
4271 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4277 * It clears the interrupt causes and enables the interrupt.
4278 * It will be called once only during nic initialized.
4281 * Pointer to struct rte_eth_dev.
4283 * Enable or Disable.
4286 * - On success, zero.
4287 * - On failure, a negative value.
4290 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4292 struct ixgbe_interrupt *intr =
4293 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4295 ixgbe_dev_link_status_print(dev);
4297 intr->mask |= IXGBE_EICR_LSC;
4299 intr->mask &= ~IXGBE_EICR_LSC;
4305 * It clears the interrupt causes and enables the interrupt.
4306 * It will be called once only during nic initialized.
4309 * Pointer to struct rte_eth_dev.
4312 * - On success, zero.
4313 * - On failure, a negative value.
4316 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4318 struct ixgbe_interrupt *intr =
4319 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4321 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4327 * It clears the interrupt causes and enables the interrupt.
4328 * It will be called once only during nic initialized.
4331 * Pointer to struct rte_eth_dev.
4334 * - On success, zero.
4335 * - On failure, a negative value.
4338 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4340 struct ixgbe_interrupt *intr =
4341 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4343 intr->mask |= IXGBE_EICR_LINKSEC;
4349 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4352 * Pointer to struct rte_eth_dev.
4355 * - On success, zero.
4356 * - On failure, a negative value.
4359 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4362 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4363 struct ixgbe_interrupt *intr =
4364 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4366 /* clear all cause mask */
4367 ixgbe_disable_intr(hw);
4369 /* read-on-clear nic registers here */
4370 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4371 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4375 /* set flag for async link update */
4376 if (eicr & IXGBE_EICR_LSC)
4377 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4379 if (eicr & IXGBE_EICR_MAILBOX)
4380 intr->flags |= IXGBE_FLAG_MAILBOX;
4382 if (eicr & IXGBE_EICR_LINKSEC)
4383 intr->flags |= IXGBE_FLAG_MACSEC;
4385 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4386 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4387 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4388 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4394 * It gets and then prints the link status.
4397 * Pointer to struct rte_eth_dev.
4400 * - On success, zero.
4401 * - On failure, a negative value.
4404 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4406 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4407 struct rte_eth_link link;
4409 rte_eth_linkstatus_get(dev, &link);
4411 if (link.link_status) {
4412 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4413 (int)(dev->data->port_id),
4414 (unsigned)link.link_speed,
4415 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4416 "full-duplex" : "half-duplex");
4418 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4419 (int)(dev->data->port_id));
4421 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4422 pci_dev->addr.domain,
4424 pci_dev->addr.devid,
4425 pci_dev->addr.function);
4429 * It executes link_update after knowing an interrupt occurred.
4432 * Pointer to struct rte_eth_dev.
4435 * - On success, zero.
4436 * - On failure, a negative value.
4439 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4441 struct ixgbe_interrupt *intr =
4442 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4444 struct ixgbe_hw *hw =
4445 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4447 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4449 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4450 ixgbe_pf_mbx_process(dev);
4451 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4454 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4455 ixgbe_handle_lasi(hw);
4456 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4459 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4460 struct rte_eth_link link;
4462 /* get the link status before link update, for predicting later */
4463 rte_eth_linkstatus_get(dev, &link);
4465 ixgbe_dev_link_update(dev, 0);
4468 if (!link.link_status)
4469 /* handle it 1 sec later, wait it being stable */
4470 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4471 /* likely to down */
4473 /* handle it 4 sec later, wait it being stable */
4474 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4476 ixgbe_dev_link_status_print(dev);
4477 if (rte_eal_alarm_set(timeout * 1000,
4478 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4479 PMD_DRV_LOG(ERR, "Error setting alarm");
4481 /* remember original mask */
4482 intr->mask_original = intr->mask;
4483 /* only disable lsc interrupt */
4484 intr->mask &= ~IXGBE_EIMS_LSC;
4488 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4489 ixgbe_enable_intr(dev);
4495 * Interrupt handler which shall be registered for alarm callback for delayed
4496 * handling specific interrupt to wait for the stable nic state. As the
4497 * NIC interrupt state is not stable for ixgbe after link is just down,
4498 * it needs to wait 4 seconds to get the stable status.
4501 * Pointer to interrupt handle.
4503 * The address of parameter (struct rte_eth_dev *) regsitered before.
4509 ixgbe_dev_interrupt_delayed_handler(void *param)
4511 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4512 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4513 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4514 struct ixgbe_interrupt *intr =
4515 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4516 struct ixgbe_hw *hw =
4517 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4520 ixgbe_disable_intr(hw);
4522 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4523 if (eicr & IXGBE_EICR_MAILBOX)
4524 ixgbe_pf_mbx_process(dev);
4526 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4527 ixgbe_handle_lasi(hw);
4528 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4531 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4532 ixgbe_dev_link_update(dev, 0);
4533 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4534 ixgbe_dev_link_status_print(dev);
4535 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4539 if (intr->flags & IXGBE_FLAG_MACSEC) {
4540 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4542 intr->flags &= ~IXGBE_FLAG_MACSEC;
4545 /* restore original mask */
4546 intr->mask = intr->mask_original;
4547 intr->mask_original = 0;
4549 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4550 ixgbe_enable_intr(dev);
4551 rte_intr_ack(intr_handle);
4555 * Interrupt handler triggered by NIC for handling
4556 * specific interrupt.
4559 * Pointer to interrupt handle.
4561 * The address of parameter (struct rte_eth_dev *) regsitered before.
4567 ixgbe_dev_interrupt_handler(void *param)
4569 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4571 ixgbe_dev_interrupt_get_status(dev);
4572 ixgbe_dev_interrupt_action(dev);
4576 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4578 struct ixgbe_hw *hw;
4580 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4581 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4585 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4587 struct ixgbe_hw *hw;
4589 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4590 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4594 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4596 struct ixgbe_hw *hw;
4602 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4604 fc_conf->pause_time = hw->fc.pause_time;
4605 fc_conf->high_water = hw->fc.high_water[0];
4606 fc_conf->low_water = hw->fc.low_water[0];
4607 fc_conf->send_xon = hw->fc.send_xon;
4608 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4611 * Return rx_pause status according to actual setting of
4614 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4615 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4621 * Return tx_pause status according to actual setting of
4624 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4625 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4630 if (rx_pause && tx_pause)
4631 fc_conf->mode = RTE_FC_FULL;
4633 fc_conf->mode = RTE_FC_RX_PAUSE;
4635 fc_conf->mode = RTE_FC_TX_PAUSE;
4637 fc_conf->mode = RTE_FC_NONE;
4643 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4645 struct ixgbe_hw *hw;
4647 uint32_t rx_buf_size;
4648 uint32_t max_high_water;
4650 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4657 PMD_INIT_FUNC_TRACE();
4659 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4660 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4661 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4664 * At least reserve one Ethernet frame for watermark
4665 * high_water/low_water in kilo bytes for ixgbe
4667 max_high_water = (rx_buf_size -
4668 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4669 if ((fc_conf->high_water > max_high_water) ||
4670 (fc_conf->high_water < fc_conf->low_water)) {
4671 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4672 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4676 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4677 hw->fc.pause_time = fc_conf->pause_time;
4678 hw->fc.high_water[0] = fc_conf->high_water;
4679 hw->fc.low_water[0] = fc_conf->low_water;
4680 hw->fc.send_xon = fc_conf->send_xon;
4681 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4683 err = ixgbe_fc_enable(hw);
4685 /* Not negotiated is not an error case */
4686 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4688 /* check if we want to forward MAC frames - driver doesn't have native
4689 * capability to do that, so we'll write the registers ourselves */
4691 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4693 /* set or clear MFLCN.PMCF bit depending on configuration */
4694 if (fc_conf->mac_ctrl_frame_fwd != 0)
4695 mflcn |= IXGBE_MFLCN_PMCF;
4697 mflcn &= ~IXGBE_MFLCN_PMCF;
4699 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4700 IXGBE_WRITE_FLUSH(hw);
4705 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4710 * ixgbe_pfc_enable_generic - Enable flow control
4711 * @hw: pointer to hardware structure
4712 * @tc_num: traffic class number
4713 * Enable flow control according to the current settings.
4716 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4719 uint32_t mflcn_reg, fccfg_reg;
4721 uint32_t fcrtl, fcrth;
4725 /* Validate the water mark configuration */
4726 if (!hw->fc.pause_time) {
4727 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4731 /* Low water mark of zero causes XOFF floods */
4732 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4733 /* High/Low water can not be 0 */
4734 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4735 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4736 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4740 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4741 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4742 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4746 /* Negotiate the fc mode to use */
4747 ixgbe_fc_autoneg(hw);
4749 /* Disable any previous flow control settings */
4750 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4751 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4753 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4754 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4756 switch (hw->fc.current_mode) {
4759 * If the count of enabled RX Priority Flow control >1,
4760 * and the TX pause can not be disabled
4763 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4764 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4765 if (reg & IXGBE_FCRTH_FCEN)
4769 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4771 case ixgbe_fc_rx_pause:
4773 * Rx Flow control is enabled and Tx Flow control is
4774 * disabled by software override. Since there really
4775 * isn't a way to advertise that we are capable of RX
4776 * Pause ONLY, we will advertise that we support both
4777 * symmetric and asymmetric Rx PAUSE. Later, we will
4778 * disable the adapter's ability to send PAUSE frames.
4780 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4782 * If the count of enabled RX Priority Flow control >1,
4783 * and the TX pause can not be disabled
4786 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4787 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4788 if (reg & IXGBE_FCRTH_FCEN)
4792 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4794 case ixgbe_fc_tx_pause:
4796 * Tx Flow control is enabled, and Rx Flow control is
4797 * disabled by software override.
4799 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4802 /* Flow control (both Rx and Tx) is enabled by SW override. */
4803 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4804 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4807 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4808 ret_val = IXGBE_ERR_CONFIG;
4812 /* Set 802.3x based flow control settings. */
4813 mflcn_reg |= IXGBE_MFLCN_DPF;
4814 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4815 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4817 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4818 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4819 hw->fc.high_water[tc_num]) {
4820 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4821 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4822 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4824 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4826 * In order to prevent Tx hangs when the internal Tx
4827 * switch is enabled we must set the high water mark
4828 * to the maximum FCRTH value. This allows the Tx
4829 * switch to function even under heavy Rx workloads.
4831 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4833 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4835 /* Configure pause time (2 TCs per register) */
4836 reg = hw->fc.pause_time * 0x00010001;
4837 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4838 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4840 /* Configure flow control refresh threshold value */
4841 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4848 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4850 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4851 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4853 if (hw->mac.type != ixgbe_mac_82598EB) {
4854 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4860 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4863 uint32_t rx_buf_size;
4864 uint32_t max_high_water;
4866 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4867 struct ixgbe_hw *hw =
4868 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4869 struct ixgbe_dcb_config *dcb_config =
4870 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4872 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4879 PMD_INIT_FUNC_TRACE();
4881 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4882 tc_num = map[pfc_conf->priority];
4883 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4884 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4886 * At least reserve one Ethernet frame for watermark
4887 * high_water/low_water in kilo bytes for ixgbe
4889 max_high_water = (rx_buf_size -
4890 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4891 if ((pfc_conf->fc.high_water > max_high_water) ||
4892 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4893 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4894 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4898 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4899 hw->fc.pause_time = pfc_conf->fc.pause_time;
4900 hw->fc.send_xon = pfc_conf->fc.send_xon;
4901 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4902 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4904 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4906 /* Not negotiated is not an error case */
4907 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4910 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4915 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4916 struct rte_eth_rss_reta_entry64 *reta_conf,
4919 uint16_t i, sp_reta_size;
4922 uint16_t idx, shift;
4923 struct ixgbe_adapter *adapter = dev->data->dev_private;
4924 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4927 PMD_INIT_FUNC_TRACE();
4929 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4930 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4935 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4936 if (reta_size != sp_reta_size) {
4937 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4938 "(%d) doesn't match the number hardware can supported "
4939 "(%d)", reta_size, sp_reta_size);
4943 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4944 idx = i / RTE_RETA_GROUP_SIZE;
4945 shift = i % RTE_RETA_GROUP_SIZE;
4946 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4950 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4951 if (mask == IXGBE_4_BIT_MASK)
4954 r = IXGBE_READ_REG(hw, reta_reg);
4955 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4956 if (mask & (0x1 << j))
4957 reta |= reta_conf[idx].reta[shift + j] <<
4960 reta |= r & (IXGBE_8_BIT_MASK <<
4963 IXGBE_WRITE_REG(hw, reta_reg, reta);
4965 adapter->rss_reta_updated = 1;
4971 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4972 struct rte_eth_rss_reta_entry64 *reta_conf,
4975 uint16_t i, sp_reta_size;
4978 uint16_t idx, shift;
4979 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4982 PMD_INIT_FUNC_TRACE();
4983 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4984 if (reta_size != sp_reta_size) {
4985 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4986 "(%d) doesn't match the number hardware can supported "
4987 "(%d)", reta_size, sp_reta_size);
4991 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4992 idx = i / RTE_RETA_GROUP_SIZE;
4993 shift = i % RTE_RETA_GROUP_SIZE;
4994 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4999 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5000 reta = IXGBE_READ_REG(hw, reta_reg);
5001 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5002 if (mask & (0x1 << j))
5003 reta_conf[idx].reta[shift + j] =
5004 ((reta >> (CHAR_BIT * j)) &
5013 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5014 uint32_t index, uint32_t pool)
5016 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5017 uint32_t enable_addr = 1;
5019 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5024 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5026 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5028 ixgbe_clear_rar(hw, index);
5032 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5034 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5036 ixgbe_remove_rar(dev, 0);
5037 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5043 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5045 if (strcmp(dev->device->driver->name, drv->driver.name))
5052 is_ixgbe_supported(struct rte_eth_dev *dev)
5054 return is_device_supported(dev, &rte_ixgbe_pmd);
5058 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5062 struct ixgbe_hw *hw;
5063 struct rte_eth_dev_info dev_info;
5064 uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5065 struct rte_eth_dev_data *dev_data = dev->data;
5068 ret = ixgbe_dev_info_get(dev, &dev_info);
5072 /* check that mtu is within the allowed range */
5073 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5076 /* If device is started, refuse mtu that requires the support of
5077 * scattered packets when this feature has not been enabled before.
5079 if (dev_data->dev_started && !dev_data->scattered_rx &&
5080 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5081 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5082 PMD_INIT_LOG(ERR, "Stop port first.");
5086 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5087 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5089 /* switch to jumbo mode if needed */
5090 if (frame_size > RTE_ETHER_MAX_LEN) {
5091 dev->data->dev_conf.rxmode.offloads |=
5092 DEV_RX_OFFLOAD_JUMBO_FRAME;
5093 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5095 dev->data->dev_conf.rxmode.offloads &=
5096 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5097 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5099 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5101 /* update max frame size */
5102 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5104 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5105 maxfrs &= 0x0000FFFF;
5106 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5107 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5113 * Virtual Function operations
5116 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5118 struct ixgbe_interrupt *intr =
5119 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5120 struct ixgbe_hw *hw =
5121 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5123 PMD_INIT_FUNC_TRACE();
5125 /* Clear interrupt mask to stop from interrupts being generated */
5126 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5128 IXGBE_WRITE_FLUSH(hw);
5130 /* Clear mask value. */
5135 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5137 struct ixgbe_interrupt *intr =
5138 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5139 struct ixgbe_hw *hw =
5140 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5142 PMD_INIT_FUNC_TRACE();
5144 /* VF enable interrupt autoclean */
5145 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5146 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5147 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5149 IXGBE_WRITE_FLUSH(hw);
5151 /* Save IXGBE_VTEIMS value to mask. */
5152 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5156 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5158 struct rte_eth_conf *conf = &dev->data->dev_conf;
5159 struct ixgbe_adapter *adapter = dev->data->dev_private;
5161 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5162 dev->data->port_id);
5164 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5165 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5168 * VF has no ability to enable/disable HW CRC
5169 * Keep the persistent behavior the same as Host PF
5171 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5172 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5173 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5174 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5177 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5178 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5179 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5184 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5185 * allocation or vector Rx preconditions we will reset it.
5187 adapter->rx_bulk_alloc_allowed = true;
5188 adapter->rx_vec_allowed = true;
5194 ixgbevf_dev_start(struct rte_eth_dev *dev)
5196 struct ixgbe_hw *hw =
5197 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5198 uint32_t intr_vector = 0;
5199 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5200 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5204 PMD_INIT_FUNC_TRACE();
5206 /* Stop the link setup handler before resetting the HW. */
5207 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5209 err = hw->mac.ops.reset_hw(hw);
5211 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5214 hw->mac.get_link_status = true;
5216 /* negotiate mailbox API version to use with the PF. */
5217 ixgbevf_negotiate_api(hw);
5219 ixgbevf_dev_tx_init(dev);
5221 /* This can fail when allocating mbufs for descriptor rings */
5222 err = ixgbevf_dev_rx_init(dev);
5224 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5225 ixgbe_dev_clear_queues(dev);
5230 ixgbevf_set_vfta_all(dev, 1);
5233 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5234 ETH_VLAN_EXTEND_MASK;
5235 err = ixgbevf_vlan_offload_config(dev, mask);
5237 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5238 ixgbe_dev_clear_queues(dev);
5242 ixgbevf_dev_rxtx_start(dev);
5244 /* check and configure queue intr-vector mapping */
5245 if (rte_intr_cap_multiple(intr_handle) &&
5246 dev->data->dev_conf.intr_conf.rxq) {
5247 /* According to datasheet, only vector 0/1/2 can be used,
5248 * now only one vector is used for Rx queue
5251 if (rte_intr_efd_enable(intr_handle, intr_vector))
5255 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5256 intr_handle->intr_vec =
5257 rte_zmalloc("intr_vec",
5258 dev->data->nb_rx_queues * sizeof(int), 0);
5259 if (intr_handle->intr_vec == NULL) {
5260 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5261 " intr_vec", dev->data->nb_rx_queues);
5265 ixgbevf_configure_msix(dev);
5267 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5268 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5269 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5270 * is not cleared, it will fail when following rte_intr_enable( ) tries
5271 * to map Rx queue interrupt to other VFIO vectors.
5272 * So clear uio/vfio intr/evevnfd first to avoid failure.
5274 rte_intr_disable(intr_handle);
5276 rte_intr_enable(intr_handle);
5278 /* Re-enable interrupt for VF */
5279 ixgbevf_intr_enable(dev);
5282 * Update link status right before return, because it may
5283 * start link configuration process in a separate thread.
5285 ixgbevf_dev_link_update(dev, 0);
5287 hw->adapter_stopped = false;
5293 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5295 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5296 struct ixgbe_adapter *adapter = dev->data->dev_private;
5297 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5298 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5300 if (hw->adapter_stopped)
5303 PMD_INIT_FUNC_TRACE();
5305 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5307 ixgbevf_intr_disable(dev);
5309 hw->adapter_stopped = 1;
5310 ixgbe_stop_adapter(hw);
5313 * Clear what we set, but we still keep shadow_vfta to
5314 * restore after device starts
5316 ixgbevf_set_vfta_all(dev, 0);
5318 /* Clear stored conf */
5319 dev->data->scattered_rx = 0;
5321 ixgbe_dev_clear_queues(dev);
5323 /* Clean datapath event and queue/vec mapping */
5324 rte_intr_efd_disable(intr_handle);
5325 if (intr_handle->intr_vec != NULL) {
5326 rte_free(intr_handle->intr_vec);
5327 intr_handle->intr_vec = NULL;
5330 adapter->rss_reta_updated = 0;
5334 ixgbevf_dev_close(struct rte_eth_dev *dev)
5336 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5337 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5338 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5340 PMD_INIT_FUNC_TRACE();
5344 ixgbevf_dev_stop(dev);
5346 ixgbe_dev_free_queues(dev);
5349 * Remove the VF MAC address ro ensure
5350 * that the VF traffic goes to the PF
5351 * after stop, close and detach of the VF
5353 ixgbevf_remove_mac_addr(dev, 0);
5355 dev->dev_ops = NULL;
5356 dev->rx_pkt_burst = NULL;
5357 dev->tx_pkt_burst = NULL;
5359 rte_intr_disable(intr_handle);
5360 rte_intr_callback_unregister(intr_handle,
5361 ixgbevf_dev_interrupt_handler, dev);
5368 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5372 ret = eth_ixgbevf_dev_uninit(dev);
5376 ret = eth_ixgbevf_dev_init(dev);
5381 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5383 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5384 struct ixgbe_vfta *shadow_vfta =
5385 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5386 int i = 0, j = 0, vfta = 0, mask = 1;
5388 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5389 vfta = shadow_vfta->vfta[i];
5392 for (j = 0; j < 32; j++) {
5394 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5404 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5406 struct ixgbe_hw *hw =
5407 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5408 struct ixgbe_vfta *shadow_vfta =
5409 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5410 uint32_t vid_idx = 0;
5411 uint32_t vid_bit = 0;
5414 PMD_INIT_FUNC_TRACE();
5416 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5417 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5419 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5422 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5423 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5425 /* Save what we set and retore it after device reset */
5427 shadow_vfta->vfta[vid_idx] |= vid_bit;
5429 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5435 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5437 struct ixgbe_hw *hw =
5438 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5441 PMD_INIT_FUNC_TRACE();
5443 if (queue >= hw->mac.max_rx_queues)
5446 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5448 ctrl |= IXGBE_RXDCTL_VME;
5450 ctrl &= ~IXGBE_RXDCTL_VME;
5451 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5453 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5457 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5459 struct ixgbe_rx_queue *rxq;
5463 /* VF function only support hw strip feature, others are not support */
5464 if (mask & ETH_VLAN_STRIP_MASK) {
5465 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5466 rxq = dev->data->rx_queues[i];
5467 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5468 ixgbevf_vlan_strip_queue_set(dev, i, on);
5476 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5478 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5480 ixgbevf_vlan_offload_config(dev, mask);
5486 ixgbe_vt_check(struct ixgbe_hw *hw)
5490 /* if Virtualization Technology is enabled */
5491 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5492 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5493 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5501 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5503 uint32_t vector = 0;
5505 switch (hw->mac.mc_filter_type) {
5506 case 0: /* use bits [47:36] of the address */
5507 vector = ((uc_addr->addr_bytes[4] >> 4) |
5508 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5510 case 1: /* use bits [46:35] of the address */
5511 vector = ((uc_addr->addr_bytes[4] >> 3) |
5512 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5514 case 2: /* use bits [45:34] of the address */
5515 vector = ((uc_addr->addr_bytes[4] >> 2) |
5516 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5518 case 3: /* use bits [43:32] of the address */
5519 vector = ((uc_addr->addr_bytes[4]) |
5520 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5522 default: /* Invalid mc_filter_type */
5526 /* vector can only be 12-bits or boundary will be exceeded */
5532 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5533 struct rte_ether_addr *mac_addr, uint8_t on)
5540 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5541 const uint32_t ixgbe_uta_bit_shift = 5;
5542 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5543 const uint32_t bit1 = 0x1;
5545 struct ixgbe_hw *hw =
5546 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5547 struct ixgbe_uta_info *uta_info =
5548 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5550 /* The UTA table only exists on 82599 hardware and newer */
5551 if (hw->mac.type < ixgbe_mac_82599EB)
5554 vector = ixgbe_uta_vector(hw, mac_addr);
5555 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5556 uta_shift = vector & ixgbe_uta_bit_mask;
5558 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5562 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5564 uta_info->uta_in_use++;
5565 reg_val |= (bit1 << uta_shift);
5566 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5568 uta_info->uta_in_use--;
5569 reg_val &= ~(bit1 << uta_shift);
5570 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5573 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5575 if (uta_info->uta_in_use > 0)
5576 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5577 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5579 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5585 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5588 struct ixgbe_hw *hw =
5589 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5590 struct ixgbe_uta_info *uta_info =
5591 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5593 /* The UTA table only exists on 82599 hardware and newer */
5594 if (hw->mac.type < ixgbe_mac_82599EB)
5598 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5599 uta_info->uta_shadow[i] = ~0;
5600 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5603 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5604 uta_info->uta_shadow[i] = 0;
5605 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5613 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5615 uint32_t new_val = orig_val;
5617 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5618 new_val |= IXGBE_VMOLR_AUPE;
5619 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5620 new_val |= IXGBE_VMOLR_ROMPE;
5621 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5622 new_val |= IXGBE_VMOLR_ROPE;
5623 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5624 new_val |= IXGBE_VMOLR_BAM;
5625 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5626 new_val |= IXGBE_VMOLR_MPE;
5631 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5632 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5633 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5634 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5635 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5636 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5637 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5640 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5641 struct rte_eth_mirror_conf *mirror_conf,
5642 uint8_t rule_id, uint8_t on)
5644 uint32_t mr_ctl, vlvf;
5645 uint32_t mp_lsb = 0;
5646 uint32_t mv_msb = 0;
5647 uint32_t mv_lsb = 0;
5648 uint32_t mp_msb = 0;
5651 uint64_t vlan_mask = 0;
5653 const uint8_t pool_mask_offset = 32;
5654 const uint8_t vlan_mask_offset = 32;
5655 const uint8_t dst_pool_offset = 8;
5656 const uint8_t rule_mr_offset = 4;
5657 const uint8_t mirror_rule_mask = 0x0F;
5659 struct ixgbe_mirror_info *mr_info =
5660 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5661 struct ixgbe_hw *hw =
5662 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5663 uint8_t mirror_type = 0;
5665 if (ixgbe_vt_check(hw) < 0)
5668 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5671 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5672 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5673 mirror_conf->rule_type);
5677 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5678 mirror_type |= IXGBE_MRCTL_VLME;
5679 /* Check if vlan id is valid and find conresponding VLAN ID
5682 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5683 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5684 /* search vlan id related pool vlan filter
5687 reg_index = ixgbe_find_vlvf_slot(
5689 mirror_conf->vlan.vlan_id[i],
5693 vlvf = IXGBE_READ_REG(hw,
5694 IXGBE_VLVF(reg_index));
5695 if ((vlvf & IXGBE_VLVF_VIEN) &&
5696 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5697 mirror_conf->vlan.vlan_id[i]))
5698 vlan_mask |= (1ULL << reg_index);
5705 mv_lsb = vlan_mask & 0xFFFFFFFF;
5706 mv_msb = vlan_mask >> vlan_mask_offset;
5708 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5709 mirror_conf->vlan.vlan_mask;
5710 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5711 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5712 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5713 mirror_conf->vlan.vlan_id[i];
5718 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5719 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5720 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5725 * if enable pool mirror, write related pool mask register,if disable
5726 * pool mirror, clear PFMRVM register
5728 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5729 mirror_type |= IXGBE_MRCTL_VPME;
5731 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5732 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5733 mr_info->mr_conf[rule_id].pool_mask =
5734 mirror_conf->pool_mask;
5739 mr_info->mr_conf[rule_id].pool_mask = 0;
5742 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5743 mirror_type |= IXGBE_MRCTL_UPME;
5744 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5745 mirror_type |= IXGBE_MRCTL_DPME;
5747 /* read mirror control register and recalculate it */
5748 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5751 mr_ctl |= mirror_type;
5752 mr_ctl &= mirror_rule_mask;
5753 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5755 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5758 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5759 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5761 /* write mirrror control register */
5762 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5764 /* write pool mirrror control register */
5765 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5766 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5767 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5770 /* write VLAN mirrror control register */
5771 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5772 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5773 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5781 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5784 uint32_t lsb_val = 0;
5785 uint32_t msb_val = 0;
5786 const uint8_t rule_mr_offset = 4;
5788 struct ixgbe_hw *hw =
5789 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5790 struct ixgbe_mirror_info *mr_info =
5791 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5793 if (ixgbe_vt_check(hw) < 0)
5796 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5799 memset(&mr_info->mr_conf[rule_id], 0,
5800 sizeof(struct rte_eth_mirror_conf));
5802 /* clear PFVMCTL register */
5803 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5805 /* clear pool mask register */
5806 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5807 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5809 /* clear vlan mask register */
5810 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5811 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5817 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5819 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5820 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5821 struct ixgbe_interrupt *intr =
5822 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5823 struct ixgbe_hw *hw =
5824 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5825 uint32_t vec = IXGBE_MISC_VEC_ID;
5827 if (rte_intr_allow_others(intr_handle))
5828 vec = IXGBE_RX_VEC_START;
5829 intr->mask |= (1 << vec);
5830 RTE_SET_USED(queue_id);
5831 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5833 rte_intr_ack(intr_handle);
5839 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5841 struct ixgbe_interrupt *intr =
5842 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5843 struct ixgbe_hw *hw =
5844 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5845 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5846 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5847 uint32_t vec = IXGBE_MISC_VEC_ID;
5849 if (rte_intr_allow_others(intr_handle))
5850 vec = IXGBE_RX_VEC_START;
5851 intr->mask &= ~(1 << vec);
5852 RTE_SET_USED(queue_id);
5853 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5859 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5861 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5862 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5864 struct ixgbe_hw *hw =
5865 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5866 struct ixgbe_interrupt *intr =
5867 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5869 if (queue_id < 16) {
5870 ixgbe_disable_intr(hw);
5871 intr->mask |= (1 << queue_id);
5872 ixgbe_enable_intr(dev);
5873 } else if (queue_id < 32) {
5874 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5875 mask &= (1 << queue_id);
5876 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5877 } else if (queue_id < 64) {
5878 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5879 mask &= (1 << (queue_id - 32));
5880 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5882 rte_intr_ack(intr_handle);
5888 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5891 struct ixgbe_hw *hw =
5892 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5893 struct ixgbe_interrupt *intr =
5894 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5896 if (queue_id < 16) {
5897 ixgbe_disable_intr(hw);
5898 intr->mask &= ~(1 << queue_id);
5899 ixgbe_enable_intr(dev);
5900 } else if (queue_id < 32) {
5901 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5902 mask &= ~(1 << queue_id);
5903 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5904 } else if (queue_id < 64) {
5905 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5906 mask &= ~(1 << (queue_id - 32));
5907 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5914 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5915 uint8_t queue, uint8_t msix_vector)
5919 if (direction == -1) {
5921 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5922 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5925 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5927 /* rx or tx cause */
5928 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5929 idx = ((16 * (queue & 1)) + (8 * direction));
5930 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5931 tmp &= ~(0xFF << idx);
5932 tmp |= (msix_vector << idx);
5933 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5938 * set the IVAR registers, mapping interrupt causes to vectors
5940 * pointer to ixgbe_hw struct
5942 * 0 for Rx, 1 for Tx, -1 for other causes
5944 * queue to map the corresponding interrupt to
5946 * the vector to map to the corresponding queue
5949 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5950 uint8_t queue, uint8_t msix_vector)
5954 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5955 if (hw->mac.type == ixgbe_mac_82598EB) {
5956 if (direction == -1)
5958 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5959 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5960 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5961 tmp |= (msix_vector << (8 * (queue & 0x3)));
5962 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5963 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5964 (hw->mac.type == ixgbe_mac_X540) ||
5965 (hw->mac.type == ixgbe_mac_X550) ||
5966 (hw->mac.type == ixgbe_mac_X550EM_x)) {
5967 if (direction == -1) {
5969 idx = ((queue & 1) * 8);
5970 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5971 tmp &= ~(0xFF << idx);
5972 tmp |= (msix_vector << idx);
5973 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5975 /* rx or tx causes */
5976 idx = ((16 * (queue & 1)) + (8 * direction));
5977 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5978 tmp &= ~(0xFF << idx);
5979 tmp |= (msix_vector << idx);
5980 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5986 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5988 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5989 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5990 struct ixgbe_hw *hw =
5991 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5993 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5994 uint32_t base = IXGBE_MISC_VEC_ID;
5996 /* Configure VF other cause ivar */
5997 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5999 /* won't configure msix register if no mapping is done
6000 * between intr vector and event fd.
6002 if (!rte_intr_dp_is_en(intr_handle))
6005 if (rte_intr_allow_others(intr_handle)) {
6006 base = IXGBE_RX_VEC_START;
6007 vector_idx = IXGBE_RX_VEC_START;
6010 /* Configure all RX queues of VF */
6011 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6012 /* Force all queue use vector 0,
6013 * as IXGBE_VF_MAXMSIVECOTR = 1
6015 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6016 intr_handle->intr_vec[q_idx] = vector_idx;
6017 if (vector_idx < base + intr_handle->nb_efd - 1)
6021 /* As RX queue setting above show, all queues use the vector 0.
6022 * Set only the ITR value of IXGBE_MISC_VEC_ID.
6024 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6025 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6026 | IXGBE_EITR_CNT_WDIS);
6030 * Sets up the hardware to properly generate MSI-X interrupts
6032 * board private structure
6035 ixgbe_configure_msix(struct rte_eth_dev *dev)
6037 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6038 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6039 struct ixgbe_hw *hw =
6040 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6041 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6042 uint32_t vec = IXGBE_MISC_VEC_ID;
6046 /* won't configure msix register if no mapping is done
6047 * between intr vector and event fd
6048 * but if misx has been enabled already, need to configure
6049 * auto clean, auto mask and throttling.
6051 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6052 if (!rte_intr_dp_is_en(intr_handle) &&
6053 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6056 if (rte_intr_allow_others(intr_handle))
6057 vec = base = IXGBE_RX_VEC_START;
6059 /* setup GPIE for MSI-x mode */
6060 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6061 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6062 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6063 /* auto clearing and auto setting corresponding bits in EIMS
6064 * when MSI-X interrupt is triggered
6066 if (hw->mac.type == ixgbe_mac_82598EB) {
6067 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6069 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6070 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6072 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6074 /* Populate the IVAR table and set the ITR values to the
6075 * corresponding register.
6077 if (rte_intr_dp_is_en(intr_handle)) {
6078 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6080 /* by default, 1:1 mapping */
6081 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6082 intr_handle->intr_vec[queue_id] = vec;
6083 if (vec < base + intr_handle->nb_efd - 1)
6087 switch (hw->mac.type) {
6088 case ixgbe_mac_82598EB:
6089 ixgbe_set_ivar_map(hw, -1,
6090 IXGBE_IVAR_OTHER_CAUSES_INDEX,
6093 case ixgbe_mac_82599EB:
6094 case ixgbe_mac_X540:
6095 case ixgbe_mac_X550:
6096 case ixgbe_mac_X550EM_x:
6097 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6103 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6104 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6105 | IXGBE_EITR_CNT_WDIS);
6107 /* set up to autoclear timer, and the vectors */
6108 mask = IXGBE_EIMS_ENABLE_MASK;
6109 mask &= ~(IXGBE_EIMS_OTHER |
6110 IXGBE_EIMS_MAILBOX |
6113 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6117 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6118 uint16_t queue_idx, uint16_t tx_rate)
6120 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6121 struct rte_eth_rxmode *rxmode;
6122 uint32_t rf_dec, rf_int;
6124 uint16_t link_speed = dev->data->dev_link.link_speed;
6126 if (queue_idx >= hw->mac.max_tx_queues)
6130 /* Calculate the rate factor values to set */
6131 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6132 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6133 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6135 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6136 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6137 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6138 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6143 rxmode = &dev->data->dev_conf.rxmode;
6145 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6146 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6149 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6150 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6151 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6152 IXGBE_MMW_SIZE_JUMBO_FRAME);
6154 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6155 IXGBE_MMW_SIZE_DEFAULT);
6157 /* Set RTTBCNRC of queue X */
6158 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6159 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6160 IXGBE_WRITE_FLUSH(hw);
6166 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6167 __attribute__((unused)) uint32_t index,
6168 __attribute__((unused)) uint32_t pool)
6170 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6174 * On a 82599 VF, adding again the same MAC addr is not an idempotent
6175 * operation. Trap this case to avoid exhausting the [very limited]
6176 * set of PF resources used to store VF MAC addresses.
6178 if (memcmp(hw->mac.perm_addr, mac_addr,
6179 sizeof(struct rte_ether_addr)) == 0)
6181 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6183 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6184 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6185 mac_addr->addr_bytes[0],
6186 mac_addr->addr_bytes[1],
6187 mac_addr->addr_bytes[2],
6188 mac_addr->addr_bytes[3],
6189 mac_addr->addr_bytes[4],
6190 mac_addr->addr_bytes[5],
6196 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6198 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6199 struct rte_ether_addr *perm_addr =
6200 (struct rte_ether_addr *)hw->mac.perm_addr;
6201 struct rte_ether_addr *mac_addr;
6206 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6207 * not support the deletion of a given MAC address.
6208 * Instead, it imposes to delete all MAC addresses, then to add again
6209 * all MAC addresses with the exception of the one to be deleted.
6211 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6214 * Add again all MAC addresses, with the exception of the deleted one
6215 * and of the permanent MAC address.
6217 for (i = 0, mac_addr = dev->data->mac_addrs;
6218 i < hw->mac.num_rar_entries; i++, mac_addr++) {
6219 /* Skip the deleted MAC address */
6222 /* Skip NULL MAC addresses */
6223 if (rte_is_zero_ether_addr(mac_addr))
6225 /* Skip the permanent MAC address */
6226 if (memcmp(perm_addr, mac_addr,
6227 sizeof(struct rte_ether_addr)) == 0)
6229 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6232 "Adding again MAC address "
6233 "%02x:%02x:%02x:%02x:%02x:%02x failed "
6235 mac_addr->addr_bytes[0],
6236 mac_addr->addr_bytes[1],
6237 mac_addr->addr_bytes[2],
6238 mac_addr->addr_bytes[3],
6239 mac_addr->addr_bytes[4],
6240 mac_addr->addr_bytes[5],
6246 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6247 struct rte_ether_addr *addr)
6249 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6251 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6257 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6258 struct rte_eth_syn_filter *filter,
6261 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6262 struct ixgbe_filter_info *filter_info =
6263 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6267 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6270 syn_info = filter_info->syn_info;
6273 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6275 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6276 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6278 if (filter->hig_pri)
6279 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6281 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6283 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6284 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6286 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6289 filter_info->syn_info = synqf;
6290 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6291 IXGBE_WRITE_FLUSH(hw);
6296 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6297 struct rte_eth_syn_filter *filter)
6299 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6300 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6302 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6303 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6304 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6311 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6312 enum rte_filter_op filter_op,
6315 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6318 MAC_TYPE_FILTER_SUP(hw->mac.type);
6320 if (filter_op == RTE_ETH_FILTER_NOP)
6324 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6329 switch (filter_op) {
6330 case RTE_ETH_FILTER_ADD:
6331 ret = ixgbe_syn_filter_set(dev,
6332 (struct rte_eth_syn_filter *)arg,
6335 case RTE_ETH_FILTER_DELETE:
6336 ret = ixgbe_syn_filter_set(dev,
6337 (struct rte_eth_syn_filter *)arg,
6340 case RTE_ETH_FILTER_GET:
6341 ret = ixgbe_syn_filter_get(dev,
6342 (struct rte_eth_syn_filter *)arg);
6345 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6354 static inline enum ixgbe_5tuple_protocol
6355 convert_protocol_type(uint8_t protocol_value)
6357 if (protocol_value == IPPROTO_TCP)
6358 return IXGBE_FILTER_PROTOCOL_TCP;
6359 else if (protocol_value == IPPROTO_UDP)
6360 return IXGBE_FILTER_PROTOCOL_UDP;
6361 else if (protocol_value == IPPROTO_SCTP)
6362 return IXGBE_FILTER_PROTOCOL_SCTP;
6364 return IXGBE_FILTER_PROTOCOL_NONE;
6367 /* inject a 5-tuple filter to HW */
6369 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6370 struct ixgbe_5tuple_filter *filter)
6372 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6374 uint32_t ftqf, sdpqf;
6375 uint32_t l34timir = 0;
6376 uint8_t mask = 0xff;
6380 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6381 IXGBE_SDPQF_DSTPORT_SHIFT);
6382 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6384 ftqf = (uint32_t)(filter->filter_info.proto &
6385 IXGBE_FTQF_PROTOCOL_MASK);
6386 ftqf |= (uint32_t)((filter->filter_info.priority &
6387 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6388 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6389 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6390 if (filter->filter_info.dst_ip_mask == 0)
6391 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6392 if (filter->filter_info.src_port_mask == 0)
6393 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6394 if (filter->filter_info.dst_port_mask == 0)
6395 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6396 if (filter->filter_info.proto_mask == 0)
6397 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6398 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6399 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6400 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6402 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6403 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6404 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6405 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6407 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6408 l34timir |= (uint32_t)(filter->queue <<
6409 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6410 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6414 * add a 5tuple filter
6417 * dev: Pointer to struct rte_eth_dev.
6418 * index: the index the filter allocates.
6419 * filter: ponter to the filter that will be added.
6420 * rx_queue: the queue id the filter assigned to.
6423 * - On success, zero.
6424 * - On failure, a negative value.
6427 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6428 struct ixgbe_5tuple_filter *filter)
6430 struct ixgbe_filter_info *filter_info =
6431 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6435 * look for an unused 5tuple filter index,
6436 * and insert the filter to list.
6438 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6439 idx = i / (sizeof(uint32_t) * NBBY);
6440 shift = i % (sizeof(uint32_t) * NBBY);
6441 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6442 filter_info->fivetuple_mask[idx] |= 1 << shift;
6444 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6450 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6451 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6455 ixgbe_inject_5tuple_filter(dev, filter);
6461 * remove a 5tuple filter
6464 * dev: Pointer to struct rte_eth_dev.
6465 * filter: the pointer of the filter will be removed.
6468 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6469 struct ixgbe_5tuple_filter *filter)
6471 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6472 struct ixgbe_filter_info *filter_info =
6473 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6474 uint16_t index = filter->index;
6476 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6477 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6478 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6481 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6482 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6483 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6484 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6485 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6489 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6491 struct ixgbe_hw *hw;
6492 uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6493 struct rte_eth_dev_data *dev_data = dev->data;
6495 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6497 if (mtu < RTE_ETHER_MIN_MTU ||
6498 max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6501 /* If device is started, refuse mtu that requires the support of
6502 * scattered packets when this feature has not been enabled before.
6504 if (dev_data->dev_started && !dev_data->scattered_rx &&
6505 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6506 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6507 PMD_INIT_LOG(ERR, "Stop port first.");
6512 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6513 * request of the version 2.0 of the mailbox API.
6514 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6515 * of the mailbox API.
6516 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6517 * prior to 3.11.33 which contains the following change:
6518 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6520 ixgbevf_rlpml_set_vf(hw, max_frame);
6522 /* update max frame size */
6523 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6527 static inline struct ixgbe_5tuple_filter *
6528 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6529 struct ixgbe_5tuple_filter_info *key)
6531 struct ixgbe_5tuple_filter *it;
6533 TAILQ_FOREACH(it, filter_list, entries) {
6534 if (memcmp(key, &it->filter_info,
6535 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6542 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6544 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6545 struct ixgbe_5tuple_filter_info *filter_info)
6547 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6548 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6549 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6552 switch (filter->dst_ip_mask) {
6554 filter_info->dst_ip_mask = 0;
6555 filter_info->dst_ip = filter->dst_ip;
6558 filter_info->dst_ip_mask = 1;
6561 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6565 switch (filter->src_ip_mask) {
6567 filter_info->src_ip_mask = 0;
6568 filter_info->src_ip = filter->src_ip;
6571 filter_info->src_ip_mask = 1;
6574 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6578 switch (filter->dst_port_mask) {
6580 filter_info->dst_port_mask = 0;
6581 filter_info->dst_port = filter->dst_port;
6584 filter_info->dst_port_mask = 1;
6587 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6591 switch (filter->src_port_mask) {
6593 filter_info->src_port_mask = 0;
6594 filter_info->src_port = filter->src_port;
6597 filter_info->src_port_mask = 1;
6600 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6604 switch (filter->proto_mask) {
6606 filter_info->proto_mask = 0;
6607 filter_info->proto =
6608 convert_protocol_type(filter->proto);
6611 filter_info->proto_mask = 1;
6614 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6618 filter_info->priority = (uint8_t)filter->priority;
6623 * add or delete a ntuple filter
6626 * dev: Pointer to struct rte_eth_dev.
6627 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6628 * add: if true, add filter, if false, remove filter
6631 * - On success, zero.
6632 * - On failure, a negative value.
6635 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6636 struct rte_eth_ntuple_filter *ntuple_filter,
6639 struct ixgbe_filter_info *filter_info =
6640 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6641 struct ixgbe_5tuple_filter_info filter_5tuple;
6642 struct ixgbe_5tuple_filter *filter;
6645 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6646 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6650 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6651 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6655 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6657 if (filter != NULL && add) {
6658 PMD_DRV_LOG(ERR, "filter exists.");
6661 if (filter == NULL && !add) {
6662 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6667 filter = rte_zmalloc("ixgbe_5tuple_filter",
6668 sizeof(struct ixgbe_5tuple_filter), 0);
6671 rte_memcpy(&filter->filter_info,
6673 sizeof(struct ixgbe_5tuple_filter_info));
6674 filter->queue = ntuple_filter->queue;
6675 ret = ixgbe_add_5tuple_filter(dev, filter);
6681 ixgbe_remove_5tuple_filter(dev, filter);
6687 * get a ntuple filter
6690 * dev: Pointer to struct rte_eth_dev.
6691 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6694 * - On success, zero.
6695 * - On failure, a negative value.
6698 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6699 struct rte_eth_ntuple_filter *ntuple_filter)
6701 struct ixgbe_filter_info *filter_info =
6702 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6703 struct ixgbe_5tuple_filter_info filter_5tuple;
6704 struct ixgbe_5tuple_filter *filter;
6707 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6708 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6712 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6713 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6717 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6719 if (filter == NULL) {
6720 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6723 ntuple_filter->queue = filter->queue;
6728 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6729 * @dev: pointer to rte_eth_dev structure
6730 * @filter_op:operation will be taken.
6731 * @arg: a pointer to specific structure corresponding to the filter_op
6734 * - On success, zero.
6735 * - On failure, a negative value.
6738 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6739 enum rte_filter_op filter_op,
6742 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6745 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6747 if (filter_op == RTE_ETH_FILTER_NOP)
6751 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6756 switch (filter_op) {
6757 case RTE_ETH_FILTER_ADD:
6758 ret = ixgbe_add_del_ntuple_filter(dev,
6759 (struct rte_eth_ntuple_filter *)arg,
6762 case RTE_ETH_FILTER_DELETE:
6763 ret = ixgbe_add_del_ntuple_filter(dev,
6764 (struct rte_eth_ntuple_filter *)arg,
6767 case RTE_ETH_FILTER_GET:
6768 ret = ixgbe_get_ntuple_filter(dev,
6769 (struct rte_eth_ntuple_filter *)arg);
6772 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6780 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6781 struct rte_eth_ethertype_filter *filter,
6784 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6785 struct ixgbe_filter_info *filter_info =
6786 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6790 struct ixgbe_ethertype_filter ethertype_filter;
6792 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6795 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6796 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6797 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6798 " ethertype filter.", filter->ether_type);
6802 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6803 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6806 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6807 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6811 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6812 if (ret >= 0 && add) {
6813 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6814 filter->ether_type);
6817 if (ret < 0 && !add) {
6818 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6819 filter->ether_type);
6824 etqf = IXGBE_ETQF_FILTER_EN;
6825 etqf |= (uint32_t)filter->ether_type;
6826 etqs |= (uint32_t)((filter->queue <<
6827 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6828 IXGBE_ETQS_RX_QUEUE);
6829 etqs |= IXGBE_ETQS_QUEUE_EN;
6831 ethertype_filter.ethertype = filter->ether_type;
6832 ethertype_filter.etqf = etqf;
6833 ethertype_filter.etqs = etqs;
6834 ethertype_filter.conf = FALSE;
6835 ret = ixgbe_ethertype_filter_insert(filter_info,
6838 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6842 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6846 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6847 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6848 IXGBE_WRITE_FLUSH(hw);
6854 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6855 struct rte_eth_ethertype_filter *filter)
6857 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6858 struct ixgbe_filter_info *filter_info =
6859 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6860 uint32_t etqf, etqs;
6863 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6865 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6866 filter->ether_type);
6870 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6871 if (etqf & IXGBE_ETQF_FILTER_EN) {
6872 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6873 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6875 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6876 IXGBE_ETQS_RX_QUEUE_SHIFT;
6883 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6884 * @dev: pointer to rte_eth_dev structure
6885 * @filter_op:operation will be taken.
6886 * @arg: a pointer to specific structure corresponding to the filter_op
6889 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6890 enum rte_filter_op filter_op,
6893 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6896 MAC_TYPE_FILTER_SUP(hw->mac.type);
6898 if (filter_op == RTE_ETH_FILTER_NOP)
6902 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6907 switch (filter_op) {
6908 case RTE_ETH_FILTER_ADD:
6909 ret = ixgbe_add_del_ethertype_filter(dev,
6910 (struct rte_eth_ethertype_filter *)arg,
6913 case RTE_ETH_FILTER_DELETE:
6914 ret = ixgbe_add_del_ethertype_filter(dev,
6915 (struct rte_eth_ethertype_filter *)arg,
6918 case RTE_ETH_FILTER_GET:
6919 ret = ixgbe_get_ethertype_filter(dev,
6920 (struct rte_eth_ethertype_filter *)arg);
6923 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6931 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6932 enum rte_filter_type filter_type,
6933 enum rte_filter_op filter_op,
6938 switch (filter_type) {
6939 case RTE_ETH_FILTER_NTUPLE:
6940 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6942 case RTE_ETH_FILTER_ETHERTYPE:
6943 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6945 case RTE_ETH_FILTER_SYN:
6946 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6948 case RTE_ETH_FILTER_FDIR:
6949 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6951 case RTE_ETH_FILTER_L2_TUNNEL:
6952 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6954 case RTE_ETH_FILTER_GENERIC:
6955 if (filter_op != RTE_ETH_FILTER_GET)
6957 *(const void **)arg = &ixgbe_flow_ops;
6960 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6970 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6971 u8 **mc_addr_ptr, u32 *vmdq)
6976 mc_addr = *mc_addr_ptr;
6977 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6982 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6983 struct rte_ether_addr *mc_addr_set,
6984 uint32_t nb_mc_addr)
6986 struct ixgbe_hw *hw;
6989 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6990 mc_addr_list = (u8 *)mc_addr_set;
6991 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6992 ixgbe_dev_addr_list_itr, TRUE);
6996 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6998 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6999 uint64_t systime_cycles;
7001 switch (hw->mac.type) {
7002 case ixgbe_mac_X550:
7003 case ixgbe_mac_X550EM_x:
7004 case ixgbe_mac_X550EM_a:
7005 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
7006 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7007 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7011 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7012 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7016 return systime_cycles;
7020 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7022 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7023 uint64_t rx_tstamp_cycles;
7025 switch (hw->mac.type) {
7026 case ixgbe_mac_X550:
7027 case ixgbe_mac_X550EM_x:
7028 case ixgbe_mac_X550EM_a:
7029 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7030 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7031 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7035 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7036 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7037 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7041 return rx_tstamp_cycles;
7045 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7047 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7048 uint64_t tx_tstamp_cycles;
7050 switch (hw->mac.type) {
7051 case ixgbe_mac_X550:
7052 case ixgbe_mac_X550EM_x:
7053 case ixgbe_mac_X550EM_a:
7054 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7055 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7056 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7060 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7061 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7062 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7066 return tx_tstamp_cycles;
7070 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7072 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7073 struct ixgbe_adapter *adapter = dev->data->dev_private;
7074 struct rte_eth_link link;
7075 uint32_t incval = 0;
7078 /* Get current link speed. */
7079 ixgbe_dev_link_update(dev, 1);
7080 rte_eth_linkstatus_get(dev, &link);
7082 switch (link.link_speed) {
7083 case ETH_SPEED_NUM_100M:
7084 incval = IXGBE_INCVAL_100;
7085 shift = IXGBE_INCVAL_SHIFT_100;
7087 case ETH_SPEED_NUM_1G:
7088 incval = IXGBE_INCVAL_1GB;
7089 shift = IXGBE_INCVAL_SHIFT_1GB;
7091 case ETH_SPEED_NUM_10G:
7093 incval = IXGBE_INCVAL_10GB;
7094 shift = IXGBE_INCVAL_SHIFT_10GB;
7098 switch (hw->mac.type) {
7099 case ixgbe_mac_X550:
7100 case ixgbe_mac_X550EM_x:
7101 case ixgbe_mac_X550EM_a:
7102 /* Independent of link speed. */
7104 /* Cycles read will be interpreted as ns. */
7107 case ixgbe_mac_X540:
7108 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7110 case ixgbe_mac_82599EB:
7111 incval >>= IXGBE_INCVAL_SHIFT_82599;
7112 shift -= IXGBE_INCVAL_SHIFT_82599;
7113 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7114 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7117 /* Not supported. */
7121 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7122 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7123 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7125 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7126 adapter->systime_tc.cc_shift = shift;
7127 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7129 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7130 adapter->rx_tstamp_tc.cc_shift = shift;
7131 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7133 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7134 adapter->tx_tstamp_tc.cc_shift = shift;
7135 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7139 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7141 struct ixgbe_adapter *adapter = dev->data->dev_private;
7143 adapter->systime_tc.nsec += delta;
7144 adapter->rx_tstamp_tc.nsec += delta;
7145 adapter->tx_tstamp_tc.nsec += delta;
7151 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7154 struct ixgbe_adapter *adapter = dev->data->dev_private;
7156 ns = rte_timespec_to_ns(ts);
7157 /* Set the timecounters to a new value. */
7158 adapter->systime_tc.nsec = ns;
7159 adapter->rx_tstamp_tc.nsec = ns;
7160 adapter->tx_tstamp_tc.nsec = ns;
7166 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7168 uint64_t ns, systime_cycles;
7169 struct ixgbe_adapter *adapter = dev->data->dev_private;
7171 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7172 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7173 *ts = rte_ns_to_timespec(ns);
7179 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7181 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7185 /* Stop the timesync system time. */
7186 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7187 /* Reset the timesync system time value. */
7188 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7189 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7191 /* Enable system time for platforms where it isn't on by default. */
7192 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7193 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7194 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7196 ixgbe_start_timecounters(dev);
7198 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7199 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7200 (RTE_ETHER_TYPE_1588 |
7201 IXGBE_ETQF_FILTER_EN |
7204 /* Enable timestamping of received PTP packets. */
7205 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7206 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7207 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7209 /* Enable timestamping of transmitted PTP packets. */
7210 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7211 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7212 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7214 IXGBE_WRITE_FLUSH(hw);
7220 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7222 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7225 /* Disable timestamping of transmitted PTP packets. */
7226 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7227 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7228 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7230 /* Disable timestamping of received PTP packets. */
7231 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7232 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7233 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7235 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7236 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7238 /* Stop incrementating the System Time registers. */
7239 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7245 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7246 struct timespec *timestamp,
7247 uint32_t flags __rte_unused)
7249 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7250 struct ixgbe_adapter *adapter = dev->data->dev_private;
7251 uint32_t tsync_rxctl;
7252 uint64_t rx_tstamp_cycles;
7255 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7256 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7259 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7260 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7261 *timestamp = rte_ns_to_timespec(ns);
7267 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7268 struct timespec *timestamp)
7270 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7271 struct ixgbe_adapter *adapter = dev->data->dev_private;
7272 uint32_t tsync_txctl;
7273 uint64_t tx_tstamp_cycles;
7276 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7277 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7280 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7281 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7282 *timestamp = rte_ns_to_timespec(ns);
7288 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7290 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7293 const struct reg_info *reg_group;
7294 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7295 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7297 while ((reg_group = reg_set[g_ind++]))
7298 count += ixgbe_regs_group_count(reg_group);
7304 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7308 const struct reg_info *reg_group;
7310 while ((reg_group = ixgbevf_regs[g_ind++]))
7311 count += ixgbe_regs_group_count(reg_group);
7317 ixgbe_get_regs(struct rte_eth_dev *dev,
7318 struct rte_dev_reg_info *regs)
7320 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7321 uint32_t *data = regs->data;
7324 const struct reg_info *reg_group;
7325 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7326 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7329 regs->length = ixgbe_get_reg_length(dev);
7330 regs->width = sizeof(uint32_t);
7334 /* Support only full register dump */
7335 if ((regs->length == 0) ||
7336 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7337 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7339 while ((reg_group = reg_set[g_ind++]))
7340 count += ixgbe_read_regs_group(dev, &data[count],
7349 ixgbevf_get_regs(struct rte_eth_dev *dev,
7350 struct rte_dev_reg_info *regs)
7352 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7353 uint32_t *data = regs->data;
7356 const struct reg_info *reg_group;
7359 regs->length = ixgbevf_get_reg_length(dev);
7360 regs->width = sizeof(uint32_t);
7364 /* Support only full register dump */
7365 if ((regs->length == 0) ||
7366 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7367 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7369 while ((reg_group = ixgbevf_regs[g_ind++]))
7370 count += ixgbe_read_regs_group(dev, &data[count],
7379 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7381 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7383 /* Return unit is byte count */
7384 return hw->eeprom.word_size * 2;
7388 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7389 struct rte_dev_eeprom_info *in_eeprom)
7391 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7392 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7393 uint16_t *data = in_eeprom->data;
7396 first = in_eeprom->offset >> 1;
7397 length = in_eeprom->length >> 1;
7398 if ((first > hw->eeprom.word_size) ||
7399 ((first + length) > hw->eeprom.word_size))
7402 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7404 return eeprom->ops.read_buffer(hw, first, length, data);
7408 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7409 struct rte_dev_eeprom_info *in_eeprom)
7411 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7412 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7413 uint16_t *data = in_eeprom->data;
7416 first = in_eeprom->offset >> 1;
7417 length = in_eeprom->length >> 1;
7418 if ((first > hw->eeprom.word_size) ||
7419 ((first + length) > hw->eeprom.word_size))
7422 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7424 return eeprom->ops.write_buffer(hw, first, length, data);
7428 ixgbe_get_module_info(struct rte_eth_dev *dev,
7429 struct rte_eth_dev_module_info *modinfo)
7431 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7433 uint8_t sff8472_rev, addr_mode;
7434 bool page_swap = false;
7436 /* Check whether we support SFF-8472 or not */
7437 status = hw->phy.ops.read_i2c_eeprom(hw,
7438 IXGBE_SFF_SFF_8472_COMP,
7443 /* addressing mode is not supported */
7444 status = hw->phy.ops.read_i2c_eeprom(hw,
7445 IXGBE_SFF_SFF_8472_SWAP,
7450 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7452 "Address change required to access page 0xA2, "
7453 "but not supported. Please report the module "
7454 "type to the driver maintainers.");
7458 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7459 /* We have a SFP, but it does not support SFF-8472 */
7460 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7461 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7463 /* We have a SFP which supports a revision of SFF-8472. */
7464 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7465 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7472 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7473 struct rte_dev_eeprom_info *info)
7475 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7476 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7477 uint8_t databyte = 0xFF;
7478 uint8_t *data = info->data;
7481 if (info->length == 0)
7484 for (i = info->offset; i < info->offset + info->length; i++) {
7485 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7486 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7488 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7493 data[i - info->offset] = databyte;
7500 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7502 case ixgbe_mac_X550:
7503 case ixgbe_mac_X550EM_x:
7504 case ixgbe_mac_X550EM_a:
7505 return ETH_RSS_RETA_SIZE_512;
7506 case ixgbe_mac_X550_vf:
7507 case ixgbe_mac_X550EM_x_vf:
7508 case ixgbe_mac_X550EM_a_vf:
7509 return ETH_RSS_RETA_SIZE_64;
7510 case ixgbe_mac_X540_vf:
7511 case ixgbe_mac_82599_vf:
7514 return ETH_RSS_RETA_SIZE_128;
7519 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7521 case ixgbe_mac_X550:
7522 case ixgbe_mac_X550EM_x:
7523 case ixgbe_mac_X550EM_a:
7524 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7525 return IXGBE_RETA(reta_idx >> 2);
7527 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7528 case ixgbe_mac_X550_vf:
7529 case ixgbe_mac_X550EM_x_vf:
7530 case ixgbe_mac_X550EM_a_vf:
7531 return IXGBE_VFRETA(reta_idx >> 2);
7533 return IXGBE_RETA(reta_idx >> 2);
7538 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7540 case ixgbe_mac_X550_vf:
7541 case ixgbe_mac_X550EM_x_vf:
7542 case ixgbe_mac_X550EM_a_vf:
7543 return IXGBE_VFMRQC;
7550 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7552 case ixgbe_mac_X550_vf:
7553 case ixgbe_mac_X550EM_x_vf:
7554 case ixgbe_mac_X550EM_a_vf:
7555 return IXGBE_VFRSSRK(i);
7557 return IXGBE_RSSRK(i);
7562 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7564 case ixgbe_mac_82599_vf:
7565 case ixgbe_mac_X540_vf:
7573 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7574 struct rte_eth_dcb_info *dcb_info)
7576 struct ixgbe_dcb_config *dcb_config =
7577 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7578 struct ixgbe_dcb_tc_config *tc;
7579 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7583 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7584 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7586 dcb_info->nb_tcs = 1;
7588 tc_queue = &dcb_info->tc_queue;
7589 nb_tcs = dcb_info->nb_tcs;
7591 if (dcb_config->vt_mode) { /* vt is enabled*/
7592 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7593 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7594 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7595 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7596 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7597 for (j = 0; j < nb_tcs; j++) {
7598 tc_queue->tc_rxq[0][j].base = j;
7599 tc_queue->tc_rxq[0][j].nb_queue = 1;
7600 tc_queue->tc_txq[0][j].base = j;
7601 tc_queue->tc_txq[0][j].nb_queue = 1;
7604 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7605 for (j = 0; j < nb_tcs; j++) {
7606 tc_queue->tc_rxq[i][j].base =
7608 tc_queue->tc_rxq[i][j].nb_queue = 1;
7609 tc_queue->tc_txq[i][j].base =
7611 tc_queue->tc_txq[i][j].nb_queue = 1;
7615 } else { /* vt is disabled*/
7616 struct rte_eth_dcb_rx_conf *rx_conf =
7617 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7618 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7619 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7620 if (dcb_info->nb_tcs == ETH_4_TCS) {
7621 for (i = 0; i < dcb_info->nb_tcs; i++) {
7622 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7623 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7625 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7626 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7627 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7628 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7629 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7630 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7631 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7632 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7633 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7634 for (i = 0; i < dcb_info->nb_tcs; i++) {
7635 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7636 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7638 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7639 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7640 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7641 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7642 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7643 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7644 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7645 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7646 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7647 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7648 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7649 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7650 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7651 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7652 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7653 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7656 for (i = 0; i < dcb_info->nb_tcs; i++) {
7657 tc = &dcb_config->tc_config[i];
7658 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7663 /* Update e-tag ether type */
7665 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7666 uint16_t ether_type)
7668 uint32_t etag_etype;
7670 if (hw->mac.type != ixgbe_mac_X550 &&
7671 hw->mac.type != ixgbe_mac_X550EM_x &&
7672 hw->mac.type != ixgbe_mac_X550EM_a) {
7676 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7677 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7678 etag_etype |= ether_type;
7679 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7680 IXGBE_WRITE_FLUSH(hw);
7685 /* Config l2 tunnel ether type */
7687 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7688 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7691 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7692 struct ixgbe_l2_tn_info *l2_tn_info =
7693 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7695 if (l2_tunnel == NULL)
7698 switch (l2_tunnel->l2_tunnel_type) {
7699 case RTE_L2_TUNNEL_TYPE_E_TAG:
7700 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7701 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7704 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7712 /* Enable e-tag tunnel */
7714 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7716 uint32_t etag_etype;
7718 if (hw->mac.type != ixgbe_mac_X550 &&
7719 hw->mac.type != ixgbe_mac_X550EM_x &&
7720 hw->mac.type != ixgbe_mac_X550EM_a) {
7724 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7725 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7726 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7727 IXGBE_WRITE_FLUSH(hw);
7732 /* Enable l2 tunnel */
7734 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7735 enum rte_eth_tunnel_type l2_tunnel_type)
7738 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7739 struct ixgbe_l2_tn_info *l2_tn_info =
7740 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7742 switch (l2_tunnel_type) {
7743 case RTE_L2_TUNNEL_TYPE_E_TAG:
7744 l2_tn_info->e_tag_en = TRUE;
7745 ret = ixgbe_e_tag_enable(hw);
7748 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7756 /* Disable e-tag tunnel */
7758 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7760 uint32_t etag_etype;
7762 if (hw->mac.type != ixgbe_mac_X550 &&
7763 hw->mac.type != ixgbe_mac_X550EM_x &&
7764 hw->mac.type != ixgbe_mac_X550EM_a) {
7768 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7769 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7770 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7771 IXGBE_WRITE_FLUSH(hw);
7776 /* Disable l2 tunnel */
7778 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7779 enum rte_eth_tunnel_type l2_tunnel_type)
7782 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7783 struct ixgbe_l2_tn_info *l2_tn_info =
7784 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7786 switch (l2_tunnel_type) {
7787 case RTE_L2_TUNNEL_TYPE_E_TAG:
7788 l2_tn_info->e_tag_en = FALSE;
7789 ret = ixgbe_e_tag_disable(hw);
7792 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7801 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7802 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7805 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7806 uint32_t i, rar_entries;
7807 uint32_t rar_low, rar_high;
7809 if (hw->mac.type != ixgbe_mac_X550 &&
7810 hw->mac.type != ixgbe_mac_X550EM_x &&
7811 hw->mac.type != ixgbe_mac_X550EM_a) {
7815 rar_entries = ixgbe_get_num_rx_addrs(hw);
7817 for (i = 1; i < rar_entries; i++) {
7818 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7819 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7820 if ((rar_high & IXGBE_RAH_AV) &&
7821 (rar_high & IXGBE_RAH_ADTYPE) &&
7822 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7823 l2_tunnel->tunnel_id)) {
7824 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7825 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7827 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7837 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7838 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7841 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7842 uint32_t i, rar_entries;
7843 uint32_t rar_low, rar_high;
7845 if (hw->mac.type != ixgbe_mac_X550 &&
7846 hw->mac.type != ixgbe_mac_X550EM_x &&
7847 hw->mac.type != ixgbe_mac_X550EM_a) {
7851 /* One entry for one tunnel. Try to remove potential existing entry. */
7852 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7854 rar_entries = ixgbe_get_num_rx_addrs(hw);
7856 for (i = 1; i < rar_entries; i++) {
7857 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7858 if (rar_high & IXGBE_RAH_AV) {
7861 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7862 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7863 rar_low = l2_tunnel->tunnel_id;
7865 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7866 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7872 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7873 " Please remove a rule before adding a new one.");
7877 static inline struct ixgbe_l2_tn_filter *
7878 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7879 struct ixgbe_l2_tn_key *key)
7883 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7887 return l2_tn_info->hash_map[ret];
7891 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7892 struct ixgbe_l2_tn_filter *l2_tn_filter)
7896 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7897 &l2_tn_filter->key);
7901 "Failed to insert L2 tunnel filter"
7902 " to hash table %d!",
7907 l2_tn_info->hash_map[ret] = l2_tn_filter;
7909 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7915 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7916 struct ixgbe_l2_tn_key *key)
7919 struct ixgbe_l2_tn_filter *l2_tn_filter;
7921 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7925 "No such L2 tunnel filter to delete %d!",
7930 l2_tn_filter = l2_tn_info->hash_map[ret];
7931 l2_tn_info->hash_map[ret] = NULL;
7933 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7934 rte_free(l2_tn_filter);
7939 /* Add l2 tunnel filter */
7941 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7942 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7946 struct ixgbe_l2_tn_info *l2_tn_info =
7947 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7948 struct ixgbe_l2_tn_key key;
7949 struct ixgbe_l2_tn_filter *node;
7952 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7953 key.tn_id = l2_tunnel->tunnel_id;
7955 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7959 "The L2 tunnel filter already exists!");
7963 node = rte_zmalloc("ixgbe_l2_tn",
7964 sizeof(struct ixgbe_l2_tn_filter),
7969 rte_memcpy(&node->key,
7971 sizeof(struct ixgbe_l2_tn_key));
7972 node->pool = l2_tunnel->pool;
7973 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7980 switch (l2_tunnel->l2_tunnel_type) {
7981 case RTE_L2_TUNNEL_TYPE_E_TAG:
7982 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7985 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7990 if ((!restore) && (ret < 0))
7991 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7996 /* Delete l2 tunnel filter */
7998 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7999 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8002 struct ixgbe_l2_tn_info *l2_tn_info =
8003 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8004 struct ixgbe_l2_tn_key key;
8006 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8007 key.tn_id = l2_tunnel->tunnel_id;
8008 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8012 switch (l2_tunnel->l2_tunnel_type) {
8013 case RTE_L2_TUNNEL_TYPE_E_TAG:
8014 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8017 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8026 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8027 * @dev: pointer to rte_eth_dev structure
8028 * @filter_op:operation will be taken.
8029 * @arg: a pointer to specific structure corresponding to the filter_op
8032 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8033 enum rte_filter_op filter_op,
8038 if (filter_op == RTE_ETH_FILTER_NOP)
8042 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8047 switch (filter_op) {
8048 case RTE_ETH_FILTER_ADD:
8049 ret = ixgbe_dev_l2_tunnel_filter_add
8051 (struct rte_eth_l2_tunnel_conf *)arg,
8054 case RTE_ETH_FILTER_DELETE:
8055 ret = ixgbe_dev_l2_tunnel_filter_del
8057 (struct rte_eth_l2_tunnel_conf *)arg);
8060 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8068 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8072 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8074 if (hw->mac.type != ixgbe_mac_X550 &&
8075 hw->mac.type != ixgbe_mac_X550EM_x &&
8076 hw->mac.type != ixgbe_mac_X550EM_a) {
8080 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8081 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8083 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8084 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8089 /* Enable l2 tunnel forwarding */
8091 ixgbe_dev_l2_tunnel_forwarding_enable
8092 (struct rte_eth_dev *dev,
8093 enum rte_eth_tunnel_type l2_tunnel_type)
8095 struct ixgbe_l2_tn_info *l2_tn_info =
8096 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8099 switch (l2_tunnel_type) {
8100 case RTE_L2_TUNNEL_TYPE_E_TAG:
8101 l2_tn_info->e_tag_fwd_en = TRUE;
8102 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8105 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8113 /* Disable l2 tunnel forwarding */
8115 ixgbe_dev_l2_tunnel_forwarding_disable
8116 (struct rte_eth_dev *dev,
8117 enum rte_eth_tunnel_type l2_tunnel_type)
8119 struct ixgbe_l2_tn_info *l2_tn_info =
8120 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8123 switch (l2_tunnel_type) {
8124 case RTE_L2_TUNNEL_TYPE_E_TAG:
8125 l2_tn_info->e_tag_fwd_en = FALSE;
8126 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8129 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8138 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8139 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8142 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8144 uint32_t vmtir, vmvir;
8145 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8147 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8149 "VF id %u should be less than %u",
8155 if (hw->mac.type != ixgbe_mac_X550 &&
8156 hw->mac.type != ixgbe_mac_X550EM_x &&
8157 hw->mac.type != ixgbe_mac_X550EM_a) {
8162 vmtir = l2_tunnel->tunnel_id;
8166 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8168 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8169 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8171 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8172 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8177 /* Enable l2 tunnel tag insertion */
8179 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8180 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8184 switch (l2_tunnel->l2_tunnel_type) {
8185 case RTE_L2_TUNNEL_TYPE_E_TAG:
8186 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8189 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8197 /* Disable l2 tunnel tag insertion */
8199 ixgbe_dev_l2_tunnel_insertion_disable
8200 (struct rte_eth_dev *dev,
8201 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8205 switch (l2_tunnel->l2_tunnel_type) {
8206 case RTE_L2_TUNNEL_TYPE_E_TAG:
8207 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8210 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8219 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8224 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8226 if (hw->mac.type != ixgbe_mac_X550 &&
8227 hw->mac.type != ixgbe_mac_X550EM_x &&
8228 hw->mac.type != ixgbe_mac_X550EM_a) {
8232 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8234 qde |= IXGBE_QDE_STRIP_TAG;
8236 qde &= ~IXGBE_QDE_STRIP_TAG;
8237 qde &= ~IXGBE_QDE_READ;
8238 qde |= IXGBE_QDE_WRITE;
8239 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8244 /* Enable l2 tunnel tag stripping */
8246 ixgbe_dev_l2_tunnel_stripping_enable
8247 (struct rte_eth_dev *dev,
8248 enum rte_eth_tunnel_type l2_tunnel_type)
8252 switch (l2_tunnel_type) {
8253 case RTE_L2_TUNNEL_TYPE_E_TAG:
8254 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8257 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8265 /* Disable l2 tunnel tag stripping */
8267 ixgbe_dev_l2_tunnel_stripping_disable
8268 (struct rte_eth_dev *dev,
8269 enum rte_eth_tunnel_type l2_tunnel_type)
8273 switch (l2_tunnel_type) {
8274 case RTE_L2_TUNNEL_TYPE_E_TAG:
8275 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8278 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8286 /* Enable/disable l2 tunnel offload functions */
8288 ixgbe_dev_l2_tunnel_offload_set
8289 (struct rte_eth_dev *dev,
8290 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8296 if (l2_tunnel == NULL)
8300 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8302 ret = ixgbe_dev_l2_tunnel_enable(
8304 l2_tunnel->l2_tunnel_type);
8306 ret = ixgbe_dev_l2_tunnel_disable(
8308 l2_tunnel->l2_tunnel_type);
8311 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8313 ret = ixgbe_dev_l2_tunnel_insertion_enable(
8317 ret = ixgbe_dev_l2_tunnel_insertion_disable(
8322 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8324 ret = ixgbe_dev_l2_tunnel_stripping_enable(
8326 l2_tunnel->l2_tunnel_type);
8328 ret = ixgbe_dev_l2_tunnel_stripping_disable(
8330 l2_tunnel->l2_tunnel_type);
8333 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8335 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8337 l2_tunnel->l2_tunnel_type);
8339 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8341 l2_tunnel->l2_tunnel_type);
8348 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8351 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8352 IXGBE_WRITE_FLUSH(hw);
8357 /* There's only one register for VxLAN UDP port.
8358 * So, we cannot add several ports. Will update it.
8361 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8365 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8369 return ixgbe_update_vxlan_port(hw, port);
8372 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8373 * UDP port, it must have a value.
8374 * So, will reset it to the original value 0.
8377 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8382 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8384 if (cur_port != port) {
8385 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8389 return ixgbe_update_vxlan_port(hw, 0);
8392 /* Add UDP tunneling port */
8394 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8395 struct rte_eth_udp_tunnel *udp_tunnel)
8398 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8400 if (hw->mac.type != ixgbe_mac_X550 &&
8401 hw->mac.type != ixgbe_mac_X550EM_x &&
8402 hw->mac.type != ixgbe_mac_X550EM_a) {
8406 if (udp_tunnel == NULL)
8409 switch (udp_tunnel->prot_type) {
8410 case RTE_TUNNEL_TYPE_VXLAN:
8411 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8414 case RTE_TUNNEL_TYPE_GENEVE:
8415 case RTE_TUNNEL_TYPE_TEREDO:
8416 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8421 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8429 /* Remove UDP tunneling port */
8431 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8432 struct rte_eth_udp_tunnel *udp_tunnel)
8435 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8437 if (hw->mac.type != ixgbe_mac_X550 &&
8438 hw->mac.type != ixgbe_mac_X550EM_x &&
8439 hw->mac.type != ixgbe_mac_X550EM_a) {
8443 if (udp_tunnel == NULL)
8446 switch (udp_tunnel->prot_type) {
8447 case RTE_TUNNEL_TYPE_VXLAN:
8448 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8450 case RTE_TUNNEL_TYPE_GENEVE:
8451 case RTE_TUNNEL_TYPE_TEREDO:
8452 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8456 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8465 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8467 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8470 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8474 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8486 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8488 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8491 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8495 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8507 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8509 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8511 int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8513 switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8517 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8529 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8531 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8534 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8538 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8549 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8551 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8554 /* peek the message first */
8555 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8557 /* PF reset VF event */
8558 if (in_msg == IXGBE_PF_CONTROL_MSG) {
8559 /* dummy mbx read to ack pf */
8560 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8562 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8568 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8571 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8572 struct ixgbe_interrupt *intr =
8573 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8574 ixgbevf_intr_disable(dev);
8576 /* read-on-clear nic registers here */
8577 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8580 /* only one misc vector supported - mailbox */
8581 eicr &= IXGBE_VTEICR_MASK;
8582 if (eicr == IXGBE_MISC_VEC_ID)
8583 intr->flags |= IXGBE_FLAG_MAILBOX;
8589 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8591 struct ixgbe_interrupt *intr =
8592 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8594 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8595 ixgbevf_mbx_process(dev);
8596 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8599 ixgbevf_intr_enable(dev);
8605 ixgbevf_dev_interrupt_handler(void *param)
8607 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8609 ixgbevf_dev_interrupt_get_status(dev);
8610 ixgbevf_dev_interrupt_action(dev);
8614 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8615 * @hw: pointer to hardware structure
8617 * Stops the transmit data path and waits for the HW to internally empty
8618 * the Tx security block
8620 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8622 #define IXGBE_MAX_SECTX_POLL 40
8627 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8628 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8629 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8630 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8631 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8632 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8634 /* Use interrupt-safe sleep just in case */
8638 /* For informational purposes only */
8639 if (i >= IXGBE_MAX_SECTX_POLL)
8640 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8641 "path fully disabled. Continuing with init.");
8643 return IXGBE_SUCCESS;
8647 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8648 * @hw: pointer to hardware structure
8650 * Enables the transmit data path.
8652 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8656 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8657 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8658 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8659 IXGBE_WRITE_FLUSH(hw);
8661 return IXGBE_SUCCESS;
8664 /* restore n-tuple filter */
8666 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8668 struct ixgbe_filter_info *filter_info =
8669 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8670 struct ixgbe_5tuple_filter *node;
8672 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8673 ixgbe_inject_5tuple_filter(dev, node);
8677 /* restore ethernet type filter */
8679 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8681 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8682 struct ixgbe_filter_info *filter_info =
8683 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8686 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8687 if (filter_info->ethertype_mask & (1 << i)) {
8688 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8689 filter_info->ethertype_filters[i].etqf);
8690 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8691 filter_info->ethertype_filters[i].etqs);
8692 IXGBE_WRITE_FLUSH(hw);
8697 /* restore SYN filter */
8699 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8701 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8702 struct ixgbe_filter_info *filter_info =
8703 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8706 synqf = filter_info->syn_info;
8708 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8709 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8710 IXGBE_WRITE_FLUSH(hw);
8714 /* restore L2 tunnel filter */
8716 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8718 struct ixgbe_l2_tn_info *l2_tn_info =
8719 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8720 struct ixgbe_l2_tn_filter *node;
8721 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8723 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8724 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8725 l2_tn_conf.tunnel_id = node->key.tn_id;
8726 l2_tn_conf.pool = node->pool;
8727 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8731 /* restore rss filter */
8733 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8735 struct ixgbe_filter_info *filter_info =
8736 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8738 if (filter_info->rss_info.conf.queue_num)
8739 ixgbe_config_rss_filter(dev,
8740 &filter_info->rss_info, TRUE);
8744 ixgbe_filter_restore(struct rte_eth_dev *dev)
8746 ixgbe_ntuple_filter_restore(dev);
8747 ixgbe_ethertype_filter_restore(dev);
8748 ixgbe_syn_filter_restore(dev);
8749 ixgbe_fdir_filter_restore(dev);
8750 ixgbe_l2_tn_filter_restore(dev);
8751 ixgbe_rss_filter_restore(dev);
8757 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8759 struct ixgbe_l2_tn_info *l2_tn_info =
8760 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8761 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8763 if (l2_tn_info->e_tag_en)
8764 (void)ixgbe_e_tag_enable(hw);
8766 if (l2_tn_info->e_tag_fwd_en)
8767 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8769 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8772 /* remove all the n-tuple filters */
8774 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8776 struct ixgbe_filter_info *filter_info =
8777 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8778 struct ixgbe_5tuple_filter *p_5tuple;
8780 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8781 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8784 /* remove all the ether type filters */
8786 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8788 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8789 struct ixgbe_filter_info *filter_info =
8790 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8793 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8794 if (filter_info->ethertype_mask & (1 << i) &&
8795 !filter_info->ethertype_filters[i].conf) {
8796 (void)ixgbe_ethertype_filter_remove(filter_info,
8798 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8799 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8800 IXGBE_WRITE_FLUSH(hw);
8805 /* remove the SYN filter */
8807 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8809 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8810 struct ixgbe_filter_info *filter_info =
8811 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8813 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8814 filter_info->syn_info = 0;
8816 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8817 IXGBE_WRITE_FLUSH(hw);
8821 /* remove all the L2 tunnel filters */
8823 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8825 struct ixgbe_l2_tn_info *l2_tn_info =
8826 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8827 struct ixgbe_l2_tn_filter *l2_tn_filter;
8828 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8831 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8832 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8833 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8834 l2_tn_conf.pool = l2_tn_filter->pool;
8835 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8844 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8845 struct ixgbe_macsec_setting *macsec_setting)
8847 struct ixgbe_macsec_setting *macsec =
8848 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8850 macsec->encrypt_en = macsec_setting->encrypt_en;
8851 macsec->replayprotect_en = macsec_setting->replayprotect_en;
8855 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8857 struct ixgbe_macsec_setting *macsec =
8858 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8860 macsec->encrypt_en = 0;
8861 macsec->replayprotect_en = 0;
8865 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8866 struct ixgbe_macsec_setting *macsec_setting)
8868 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8870 uint8_t en = macsec_setting->encrypt_en;
8871 uint8_t rp = macsec_setting->replayprotect_en;
8875 * As no ixgbe_disable_sec_rx_path equivalent is
8876 * implemented for tx in the base code, and we are
8877 * not allowed to modify the base code in DPDK, so
8878 * just call the hand-written one directly for now.
8879 * The hardware support has been checked by
8880 * ixgbe_disable_sec_rx_path().
8882 ixgbe_disable_sec_tx_path_generic(hw);
8884 /* Enable Ethernet CRC (required by MACsec offload) */
8885 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8886 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8887 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8889 /* Enable the TX and RX crypto engines */
8890 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8891 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8892 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8894 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8895 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8896 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8898 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8899 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8901 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8903 /* Enable SA lookup */
8904 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8905 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8906 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8907 IXGBE_LSECTXCTRL_AUTH;
8908 ctrl |= IXGBE_LSECTXCTRL_AISCI;
8909 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8910 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8911 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8913 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8914 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8915 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8916 ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8918 ctrl |= IXGBE_LSECRXCTRL_RP;
8920 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8921 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8923 /* Start the data paths */
8924 ixgbe_enable_sec_rx_path(hw);
8927 * As no ixgbe_enable_sec_rx_path equivalent is
8928 * implemented for tx in the base code, and we are
8929 * not allowed to modify the base code in DPDK, so
8930 * just call the hand-written one directly for now.
8932 ixgbe_enable_sec_tx_path_generic(hw);
8936 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8938 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8943 * As no ixgbe_disable_sec_rx_path equivalent is
8944 * implemented for tx in the base code, and we are
8945 * not allowed to modify the base code in DPDK, so
8946 * just call the hand-written one directly for now.
8947 * The hardware support has been checked by
8948 * ixgbe_disable_sec_rx_path().
8950 ixgbe_disable_sec_tx_path_generic(hw);
8952 /* Disable the TX and RX crypto engines */
8953 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8954 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8955 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8957 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8958 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8959 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8961 /* Disable SA lookup */
8962 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8963 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8964 ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8965 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8967 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8968 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8969 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8970 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8972 /* Start the data paths */
8973 ixgbe_enable_sec_rx_path(hw);
8976 * As no ixgbe_enable_sec_rx_path equivalent is
8977 * implemented for tx in the base code, and we are
8978 * not allowed to modify the base code in DPDK, so
8979 * just call the hand-written one directly for now.
8981 ixgbe_enable_sec_tx_path_generic(hw);
8984 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8985 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8986 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8987 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8988 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8989 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8990 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8991 IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8993 RTE_INIT(ixgbe_init_log)
8995 ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8996 if (ixgbe_logtype_init >= 0)
8997 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8998 ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8999 if (ixgbe_logtype_driver >= 0)
9000 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
9001 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
9002 ixgbe_logtype_rx = rte_log_register("pmd.net.ixgbe.rx");
9003 if (ixgbe_logtype_rx >= 0)
9004 rte_log_set_level(ixgbe_logtype_rx, RTE_LOG_DEBUG);
9007 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
9008 ixgbe_logtype_tx = rte_log_register("pmd.net.ixgbe.tx");
9009 if (ixgbe_logtype_tx >= 0)
9010 rte_log_set_level(ixgbe_logtype_tx, RTE_LOG_DEBUG);
9013 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9014 ixgbe_logtype_tx_free = rte_log_register("pmd.net.ixgbe.tx_free");
9015 if (ixgbe_logtype_tx_free >= 0)
9016 rte_log_set_level(ixgbe_logtype_tx_free, RTE_LOG_DEBUG);