4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
64 #include "ixgbe_logs.h"
65 #include "base/ixgbe_api.h"
66 #include "base/ixgbe_vf.h"
67 #include "base/ixgbe_common.h"
68 #include "ixgbe_ethdev.h"
69 #include "ixgbe_bypass.h"
70 #include "ixgbe_rxtx.h"
71 #include "base/ixgbe_type.h"
72 #include "base/ixgbe_phy.h"
73 #include "ixgbe_regs.h"
76 * High threshold controlling when to start sending XOFF frames. Must be at
77 * least 8 bytes less than receive packet buffer size. This value is in units
80 #define IXGBE_FC_HI 0x80
83 * Low threshold controlling when to start sending XON frames. This value is
84 * in units of 1024 bytes.
86 #define IXGBE_FC_LO 0x40
88 /* Default minimum inter-interrupt interval for EITR configuration */
89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
91 /* Timer value included in XOFF frames. */
92 #define IXGBE_FC_PAUSE 0x680
94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
95 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
96 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
98 #define IXGBE_MMW_SIZE_DEFAULT 0x4
99 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
100 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
103 * Default values for RX/TX configuration
105 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
106 #define IXGBE_DEFAULT_RX_PTHRESH 8
107 #define IXGBE_DEFAULT_RX_HTHRESH 8
108 #define IXGBE_DEFAULT_RX_WTHRESH 0
110 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
111 #define IXGBE_DEFAULT_TX_PTHRESH 32
112 #define IXGBE_DEFAULT_TX_HTHRESH 0
113 #define IXGBE_DEFAULT_TX_WTHRESH 0
114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
116 /* Bit shift and mask */
117 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
118 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
119 #define IXGBE_8_BIT_WIDTH CHAR_BIT
120 #define IXGBE_8_BIT_MASK UINT8_MAX
122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
126 #define IXGBE_HKEY_MAX_INDEX 10
128 /* Additional timesync values. */
129 #define IXGBE_TIMINCA_16NS_SHIFT 24
130 #define IXGBE_TIMINCA_INCVALUE 16000000
131 #define IXGBE_TIMINCA_INIT ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
132 | IXGBE_TIMINCA_INCVALUE)
134 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
135 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
136 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
137 static int ixgbe_dev_start(struct rte_eth_dev *dev);
138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
139 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
140 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
142 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
143 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
144 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
145 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
146 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
147 int wait_to_complete);
148 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
149 struct rte_eth_stats *stats);
150 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
151 struct rte_eth_xstats *xstats, unsigned n);
152 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
153 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
154 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
158 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
159 struct rte_eth_dev_info *dev_info);
160 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
161 struct rte_eth_dev_info *dev_info);
162 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
164 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
165 uint16_t vlan_id, int on);
166 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
167 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
168 uint16_t queue, bool on);
169 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
171 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
172 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
173 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
174 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
175 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
177 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
178 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
179 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
180 struct rte_eth_fc_conf *fc_conf);
181 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
182 struct rte_eth_fc_conf *fc_conf);
183 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
184 struct rte_eth_pfc_conf *pfc_conf);
185 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
186 struct rte_eth_rss_reta_entry64 *reta_conf,
188 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
189 struct rte_eth_rss_reta_entry64 *reta_conf,
191 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
192 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
194 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
196 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
197 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
198 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
200 static void ixgbe_dev_interrupt_delayed_handler(void *param);
201 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
202 uint32_t index, uint32_t pool);
203 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
204 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
205 struct ether_addr *mac_addr);
206 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
208 /* For Virtual Function support */
209 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
210 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
211 static int ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev);
212 static int ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev);
213 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
214 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
215 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
216 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
217 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
218 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
219 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
220 struct rte_eth_stats *stats);
221 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
222 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
223 uint16_t vlan_id, int on);
224 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
225 uint16_t queue, int on);
226 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
227 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
228 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
231 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
233 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
235 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
236 uint8_t queue, uint8_t msix_vector);
238 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
240 /* For Eth VMDQ APIs support */
241 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
242 ether_addr* mac_addr,uint8_t on);
243 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
244 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
245 uint16_t rx_mask, uint8_t on);
246 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
247 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
248 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
249 uint64_t pool_mask,uint8_t vlan_on);
250 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
251 struct rte_eth_mirror_conf *mirror_conf,
252 uint8_t rule_id, uint8_t on);
253 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
256 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
258 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
260 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
261 uint8_t queue, uint8_t msix_vector);
263 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
265 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
266 uint16_t queue_idx, uint16_t tx_rate);
267 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
268 uint16_t tx_rate, uint64_t q_msk);
270 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
271 struct ether_addr *mac_addr,
272 uint32_t index, uint32_t pool);
273 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
274 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
275 struct ether_addr *mac_addr);
276 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
277 struct rte_eth_syn_filter *filter,
279 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
280 struct rte_eth_syn_filter *filter);
281 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
282 enum rte_filter_op filter_op,
284 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
285 struct ixgbe_5tuple_filter *filter);
286 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
287 struct ixgbe_5tuple_filter *filter);
288 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
289 struct rte_eth_ntuple_filter *filter,
291 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
292 enum rte_filter_op filter_op,
294 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
295 struct rte_eth_ntuple_filter *filter);
296 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
297 struct rte_eth_ethertype_filter *filter,
299 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
300 enum rte_filter_op filter_op,
302 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
303 struct rte_eth_ethertype_filter *filter);
304 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
305 enum rte_filter_type filter_type,
306 enum rte_filter_op filter_op,
308 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
310 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
311 struct ether_addr *mc_addr_set,
312 uint32_t nb_mc_addr);
314 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
315 static int ixgbe_get_regs(struct rte_eth_dev *dev,
316 struct rte_dev_reg_info *regs);
317 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
318 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
319 struct rte_dev_eeprom_info *eeprom);
320 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
321 struct rte_dev_eeprom_info *eeprom);
323 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
324 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
325 struct rte_dev_reg_info *regs);
327 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
328 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
329 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
330 struct timespec *timestamp,
332 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
333 struct timespec *timestamp);
336 * Define VF Stats MACRO for Non "cleared on read" register
338 #define UPDATE_VF_STAT(reg, last, cur) \
340 uint32_t latest = IXGBE_READ_REG(hw, reg); \
341 cur += latest - last; \
345 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
347 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
348 u64 new_msb = IXGBE_READ_REG(hw, msb); \
349 u64 latest = ((new_msb << 32) | new_lsb); \
350 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
354 #define IXGBE_SET_HWSTRIP(h, q) do{\
355 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
356 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
357 (h)->bitmap[idx] |= 1 << bit;\
360 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
361 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
362 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
363 (h)->bitmap[idx] &= ~(1 << bit);\
366 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
367 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
368 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
369 (r) = (h)->bitmap[idx] >> bit & 1;\
373 * The set of PCI devices this driver supports
375 static const struct rte_pci_id pci_id_ixgbe_map[] = {
377 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
378 #include "rte_pci_dev_ids.h"
380 { .vendor_id = 0, /* sentinel */ },
385 * The set of PCI devices this driver supports (for 82599 VF)
387 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
389 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
390 #include "rte_pci_dev_ids.h"
391 { .vendor_id = 0, /* sentinel */ },
395 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
396 .dev_configure = ixgbe_dev_configure,
397 .dev_start = ixgbe_dev_start,
398 .dev_stop = ixgbe_dev_stop,
399 .dev_set_link_up = ixgbe_dev_set_link_up,
400 .dev_set_link_down = ixgbe_dev_set_link_down,
401 .dev_close = ixgbe_dev_close,
402 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
403 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
404 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
405 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
406 .link_update = ixgbe_dev_link_update,
407 .stats_get = ixgbe_dev_stats_get,
408 .xstats_get = ixgbe_dev_xstats_get,
409 .stats_reset = ixgbe_dev_stats_reset,
410 .xstats_reset = ixgbe_dev_xstats_reset,
411 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
412 .dev_infos_get = ixgbe_dev_info_get,
413 .mtu_set = ixgbe_dev_mtu_set,
414 .vlan_filter_set = ixgbe_vlan_filter_set,
415 .vlan_tpid_set = ixgbe_vlan_tpid_set,
416 .vlan_offload_set = ixgbe_vlan_offload_set,
417 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
418 .rx_queue_start = ixgbe_dev_rx_queue_start,
419 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
420 .tx_queue_start = ixgbe_dev_tx_queue_start,
421 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
422 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
424 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
425 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
427 .rx_queue_release = ixgbe_dev_rx_queue_release,
428 .rx_queue_count = ixgbe_dev_rx_queue_count,
429 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
430 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
431 .tx_queue_release = ixgbe_dev_tx_queue_release,
432 .dev_led_on = ixgbe_dev_led_on,
433 .dev_led_off = ixgbe_dev_led_off,
434 .flow_ctrl_get = ixgbe_flow_ctrl_get,
435 .flow_ctrl_set = ixgbe_flow_ctrl_set,
436 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
437 .mac_addr_add = ixgbe_add_rar,
438 .mac_addr_remove = ixgbe_remove_rar,
439 .mac_addr_set = ixgbe_set_default_mac_addr,
440 .uc_hash_table_set = ixgbe_uc_hash_table_set,
441 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
442 .mirror_rule_set = ixgbe_mirror_rule_set,
443 .mirror_rule_reset = ixgbe_mirror_rule_reset,
444 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
445 .set_vf_rx = ixgbe_set_pool_rx,
446 .set_vf_tx = ixgbe_set_pool_tx,
447 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
448 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
449 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
450 .reta_update = ixgbe_dev_rss_reta_update,
451 .reta_query = ixgbe_dev_rss_reta_query,
452 #ifdef RTE_NIC_BYPASS
453 .bypass_init = ixgbe_bypass_init,
454 .bypass_state_set = ixgbe_bypass_state_store,
455 .bypass_state_show = ixgbe_bypass_state_show,
456 .bypass_event_set = ixgbe_bypass_event_store,
457 .bypass_event_show = ixgbe_bypass_event_show,
458 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
459 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
460 .bypass_ver_show = ixgbe_bypass_ver_show,
461 .bypass_wd_reset = ixgbe_bypass_wd_reset,
462 #endif /* RTE_NIC_BYPASS */
463 .rss_hash_update = ixgbe_dev_rss_hash_update,
464 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
465 .filter_ctrl = ixgbe_dev_filter_ctrl,
466 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
467 .timesync_enable = ixgbe_timesync_enable,
468 .timesync_disable = ixgbe_timesync_disable,
469 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
470 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
471 .get_reg_length = ixgbe_get_reg_length,
472 .get_reg = ixgbe_get_regs,
473 .get_eeprom_length = ixgbe_get_eeprom_length,
474 .get_eeprom = ixgbe_get_eeprom,
475 .set_eeprom = ixgbe_set_eeprom,
479 * dev_ops for virtual function, bare necessities for basic vf
480 * operation have been implemented
482 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
483 .dev_configure = ixgbevf_dev_configure,
484 .dev_start = ixgbevf_dev_start,
485 .dev_stop = ixgbevf_dev_stop,
486 .link_update = ixgbe_dev_link_update,
487 .stats_get = ixgbevf_dev_stats_get,
488 .stats_reset = ixgbevf_dev_stats_reset,
489 .dev_close = ixgbevf_dev_close,
490 .dev_infos_get = ixgbevf_dev_info_get,
491 .mtu_set = ixgbevf_dev_set_mtu,
492 .vlan_filter_set = ixgbevf_vlan_filter_set,
493 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
494 .vlan_offload_set = ixgbevf_vlan_offload_set,
495 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
496 .rx_queue_release = ixgbe_dev_rx_queue_release,
497 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
498 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
499 .tx_queue_release = ixgbe_dev_tx_queue_release,
501 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
502 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
504 .mac_addr_add = ixgbevf_add_mac_addr,
505 .mac_addr_remove = ixgbevf_remove_mac_addr,
506 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
507 .mac_addr_set = ixgbevf_set_default_mac_addr,
508 .get_reg_length = ixgbevf_get_reg_length,
509 .get_reg = ixgbevf_get_regs,
512 /* store statistics names and its offset in stats structure */
513 struct rte_ixgbe_xstats_name_off {
514 char name[RTE_ETH_XSTATS_NAME_SIZE];
518 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
519 {"rx_illegal_byte_err", offsetof(struct ixgbe_hw_stats, errbc)},
520 {"rx_len_err", offsetof(struct ixgbe_hw_stats, rlec)},
521 {"rx_undersize_count", offsetof(struct ixgbe_hw_stats, ruc)},
522 {"rx_oversize_count", offsetof(struct ixgbe_hw_stats, roc)},
523 {"rx_fragment_count", offsetof(struct ixgbe_hw_stats, rfc)},
524 {"rx_jabber_count", offsetof(struct ixgbe_hw_stats, rjc)},
525 {"l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
526 {"mac_local_fault", offsetof(struct ixgbe_hw_stats, mlfc)},
527 {"mac_remote_fault", offsetof(struct ixgbe_hw_stats, mrfc)},
528 {"mac_short_pkt_discard", offsetof(struct ixgbe_hw_stats, mspdc)},
529 {"fccrc_error", offsetof(struct ixgbe_hw_stats, fccrc)},
530 {"fcoe_drop", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
531 {"fc_last_error", offsetof(struct ixgbe_hw_stats, fclast)},
532 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
533 {"rx_phy_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
534 {"mgmt_pkts_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
535 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
536 {"fdir_match", offsetof(struct ixgbe_hw_stats, fdirmatch)},
537 {"fdir_miss", offsetof(struct ixgbe_hw_stats, fdirmiss)},
538 {"tx_flow_control_xon", offsetof(struct ixgbe_hw_stats, lxontxc)},
539 {"rx_flow_control_xon", offsetof(struct ixgbe_hw_stats, lxonrxc)},
540 {"tx_flow_control_xoff", offsetof(struct ixgbe_hw_stats, lxofftxc)},
541 {"rx_flow_control_xoff", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
544 #define IXGBE_NB_XSTATS (sizeof(rte_ixgbe_stats_strings) / \
545 sizeof(rte_ixgbe_stats_strings[0]))
548 * Atomically reads the link status information from global
549 * structure rte_eth_dev.
552 * - Pointer to the structure rte_eth_dev to read from.
553 * - Pointer to the buffer to be saved with the link status.
556 * - On success, zero.
557 * - On failure, negative value.
560 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
561 struct rte_eth_link *link)
563 struct rte_eth_link *dst = link;
564 struct rte_eth_link *src = &(dev->data->dev_link);
566 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
567 *(uint64_t *)src) == 0)
574 * Atomically writes the link status information into global
575 * structure rte_eth_dev.
578 * - Pointer to the structure rte_eth_dev to read from.
579 * - Pointer to the buffer to be saved with the link status.
582 * - On success, zero.
583 * - On failure, negative value.
586 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
587 struct rte_eth_link *link)
589 struct rte_eth_link *dst = &(dev->data->dev_link);
590 struct rte_eth_link *src = link;
592 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
593 *(uint64_t *)src) == 0)
600 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
603 ixgbe_is_sfp(struct ixgbe_hw *hw)
605 switch (hw->phy.type) {
606 case ixgbe_phy_sfp_avago:
607 case ixgbe_phy_sfp_ftl:
608 case ixgbe_phy_sfp_intel:
609 case ixgbe_phy_sfp_unknown:
610 case ixgbe_phy_sfp_passive_tyco:
611 case ixgbe_phy_sfp_passive_unknown:
618 static inline int32_t
619 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
624 status = ixgbe_reset_hw(hw);
626 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
627 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
628 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
629 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
630 IXGBE_WRITE_FLUSH(hw);
636 ixgbe_enable_intr(struct rte_eth_dev *dev)
638 struct ixgbe_interrupt *intr =
639 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
640 struct ixgbe_hw *hw =
641 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
643 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
644 IXGBE_WRITE_FLUSH(hw);
648 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
651 ixgbe_disable_intr(struct ixgbe_hw *hw)
653 PMD_INIT_FUNC_TRACE();
655 if (hw->mac.type == ixgbe_mac_82598EB) {
656 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
658 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
659 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
660 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
662 IXGBE_WRITE_FLUSH(hw);
666 * This function resets queue statistics mapping registers.
667 * From Niantic datasheet, Initialization of Statistics section:
668 * "...if software requires the queue counters, the RQSMR and TQSM registers
669 * must be re-programmed following a device reset.
672 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
676 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
677 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
678 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
684 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
689 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
690 #define NB_QMAP_FIELDS_PER_QSM_REG 4
691 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
693 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
694 struct ixgbe_stat_mapping_registers *stat_mappings =
695 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
696 uint32_t qsmr_mask = 0;
697 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
701 if ((hw->mac.type != ixgbe_mac_82599EB) &&
702 (hw->mac.type != ixgbe_mac_X540) &&
703 (hw->mac.type != ixgbe_mac_X550) &&
704 (hw->mac.type != ixgbe_mac_X550EM_x))
707 PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
708 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
711 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
712 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
713 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
716 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
718 /* Now clear any previous stat_idx set */
719 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
721 stat_mappings->tqsm[n] &= ~clearing_mask;
723 stat_mappings->rqsmr[n] &= ~clearing_mask;
725 q_map = (uint32_t)stat_idx;
726 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
727 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
729 stat_mappings->tqsm[n] |= qsmr_mask;
731 stat_mappings->rqsmr[n] |= qsmr_mask;
733 PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
734 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
736 PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
737 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
739 /* Now write the mapping in the appropriate register */
741 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
742 stat_mappings->rqsmr[n], n);
743 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
746 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
747 stat_mappings->tqsm[n], n);
748 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
754 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
756 struct ixgbe_stat_mapping_registers *stat_mappings =
757 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
758 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
761 /* write whatever was in stat mapping table to the NIC */
762 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
764 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
767 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
772 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
775 struct ixgbe_dcb_tc_config *tc;
776 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
778 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
779 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
780 for (i = 0; i < dcb_max_tc; i++) {
781 tc = &dcb_config->tc_config[i];
782 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
783 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
784 (uint8_t)(100/dcb_max_tc + (i & 1));
785 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
786 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
787 (uint8_t)(100/dcb_max_tc + (i & 1));
788 tc->pfc = ixgbe_dcb_pfc_disabled;
791 /* Initialize default user to priority mapping, UPx->TC0 */
792 tc = &dcb_config->tc_config[0];
793 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
794 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
795 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
796 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
797 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
799 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
800 dcb_config->pfc_mode_enable = false;
801 dcb_config->vt_mode = true;
802 dcb_config->round_robin_enable = false;
803 /* support all DCB capabilities in 82599 */
804 dcb_config->support.capabilities = 0xFF;
806 /*we only support 4 Tcs for X540, X550 */
807 if (hw->mac.type == ixgbe_mac_X540 ||
808 hw->mac.type == ixgbe_mac_X550 ||
809 hw->mac.type == ixgbe_mac_X550EM_x) {
810 dcb_config->num_tcs.pg_tcs = 4;
811 dcb_config->num_tcs.pfc_tcs = 4;
816 * Ensure that all locks are released before first NVM or PHY access
819 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
824 * Phy lock should not fail in this early stage. If this is the case,
825 * it is due to an improper exit of the application.
826 * So force the release of the faulty lock. Release of common lock
827 * is done automatically by swfw_sync function.
829 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
830 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
831 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
833 ixgbe_release_swfw_semaphore(hw, mask);
836 * These ones are more tricky since they are common to all ports; but
837 * swfw_sync retries last long enough (1s) to be almost sure that if
838 * lock can not be taken it is due to an improper lock of the
841 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
842 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
843 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
845 ixgbe_release_swfw_semaphore(hw, mask);
849 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
850 * It returns 0 on success.
853 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
855 struct rte_pci_device *pci_dev;
856 struct ixgbe_hw *hw =
857 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
858 struct ixgbe_vfta * shadow_vfta =
859 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
860 struct ixgbe_hwstrip *hwstrip =
861 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
862 struct ixgbe_dcb_config *dcb_config =
863 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
864 struct ixgbe_filter_info *filter_info =
865 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
870 PMD_INIT_FUNC_TRACE();
872 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
873 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
874 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
877 * For secondary processes, we don't initialise any further as primary
878 * has already done this work. Only check we don't need a different
879 * RX and TX function.
881 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
882 struct ixgbe_tx_queue *txq;
883 /* TX queue function in primary, set by last queue initialized
884 * Tx queue may not initialized by primary process */
885 if (eth_dev->data->tx_queues) {
886 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
887 ixgbe_set_tx_function(eth_dev, txq);
889 /* Use default TX function if we get here */
890 PMD_INIT_LOG(INFO, "No TX queues configured yet. "
891 "Using default TX function.");
894 ixgbe_set_rx_function(eth_dev);
898 pci_dev = eth_dev->pci_dev;
900 /* Vendor and Device ID need to be set before init of shared code */
901 hw->device_id = pci_dev->id.device_id;
902 hw->vendor_id = pci_dev->id.vendor_id;
903 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
904 hw->allow_unsupported_sfp = 1;
906 /* Initialize the shared code (base driver) */
907 #ifdef RTE_NIC_BYPASS
908 diag = ixgbe_bypass_init_shared_code(hw);
910 diag = ixgbe_init_shared_code(hw);
911 #endif /* RTE_NIC_BYPASS */
913 if (diag != IXGBE_SUCCESS) {
914 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
918 /* pick up the PCI bus settings for reporting later */
919 ixgbe_get_bus_info(hw);
921 /* Unlock any pending hardware semaphore */
922 ixgbe_swfw_lock_reset(hw);
924 /* Initialize DCB configuration*/
925 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
926 ixgbe_dcb_init(hw,dcb_config);
927 /* Get Hardware Flow Control setting */
928 hw->fc.requested_mode = ixgbe_fc_full;
929 hw->fc.current_mode = ixgbe_fc_full;
930 hw->fc.pause_time = IXGBE_FC_PAUSE;
931 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
932 hw->fc.low_water[i] = IXGBE_FC_LO;
933 hw->fc.high_water[i] = IXGBE_FC_HI;
937 /* Make sure we have a good EEPROM before we read from it */
938 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
939 if (diag != IXGBE_SUCCESS) {
940 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
944 #ifdef RTE_NIC_BYPASS
945 diag = ixgbe_bypass_init_hw(hw);
947 diag = ixgbe_init_hw(hw);
948 #endif /* RTE_NIC_BYPASS */
951 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
952 * is called too soon after the kernel driver unbinding/binding occurs.
953 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
954 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
955 * also called. See ixgbe_identify_phy_82599(). The reason for the
956 * failure is not known, and only occuts when virtualisation features
957 * are disabled in the bios. A delay of 100ms was found to be enough by
958 * trial-and-error, and is doubled to be safe.
960 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
962 diag = ixgbe_init_hw(hw);
965 if (diag == IXGBE_ERR_EEPROM_VERSION) {
966 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
967 "LOM. Please be aware there may be issues associated "
968 "with your hardware.");
969 PMD_INIT_LOG(ERR, "If you are experiencing problems "
970 "please contact your Intel or hardware representative "
971 "who provided you with this hardware.");
972 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
973 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
975 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
979 /* Reset the hw statistics */
980 ixgbe_dev_stats_reset(eth_dev);
982 /* disable interrupt */
983 ixgbe_disable_intr(hw);
985 /* reset mappings for queue statistics hw counters*/
986 ixgbe_reset_qstat_mappings(hw);
988 /* Allocate memory for storing MAC addresses */
989 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
990 hw->mac.num_rar_entries, 0);
991 if (eth_dev->data->mac_addrs == NULL) {
993 "Failed to allocate %u bytes needed to store "
995 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
998 /* Copy the permanent MAC address */
999 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1000 ð_dev->data->mac_addrs[0]);
1002 /* Allocate memory for storing hash filter MAC addresses */
1003 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1004 IXGBE_VMDQ_NUM_UC_MAC, 0);
1005 if (eth_dev->data->hash_mac_addrs == NULL) {
1007 "Failed to allocate %d bytes needed to store MAC addresses",
1008 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1012 /* initialize the vfta */
1013 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1015 /* initialize the hw strip bitmap*/
1016 memset(hwstrip, 0, sizeof(*hwstrip));
1018 /* initialize PF if max_vfs not zero */
1019 ixgbe_pf_host_init(eth_dev);
1021 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1022 /* let hardware know driver is loaded */
1023 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1024 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1025 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1026 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1027 IXGBE_WRITE_FLUSH(hw);
1029 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1030 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1031 (int) hw->mac.type, (int) hw->phy.type,
1032 (int) hw->phy.sfp_type);
1034 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1035 (int) hw->mac.type, (int) hw->phy.type);
1037 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1038 eth_dev->data->port_id, pci_dev->id.vendor_id,
1039 pci_dev->id.device_id);
1041 /* enable support intr */
1042 ixgbe_enable_intr(eth_dev);
1044 /* initialize 5tuple filter list */
1045 TAILQ_INIT(&filter_info->fivetuple_list);
1046 memset(filter_info->fivetuple_mask, 0,
1047 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1053 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1055 struct rte_pci_device *pci_dev;
1056 struct ixgbe_hw *hw;
1058 PMD_INIT_FUNC_TRACE();
1060 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1063 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1064 pci_dev = eth_dev->pci_dev;
1066 if (hw->adapter_stopped == 0)
1067 ixgbe_dev_close(eth_dev);
1069 eth_dev->dev_ops = NULL;
1070 eth_dev->rx_pkt_burst = NULL;
1071 eth_dev->tx_pkt_burst = NULL;
1073 /* Unlock any pending hardware semaphore */
1074 ixgbe_swfw_lock_reset(hw);
1076 /* disable uio intr before callback unregister */
1077 rte_intr_disable(&(pci_dev->intr_handle));
1078 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1079 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1081 /* uninitialize PF if max_vfs not zero */
1082 ixgbe_pf_host_uninit(eth_dev);
1084 rte_free(eth_dev->data->mac_addrs);
1085 eth_dev->data->mac_addrs = NULL;
1087 rte_free(eth_dev->data->hash_mac_addrs);
1088 eth_dev->data->hash_mac_addrs = NULL;
1094 * Negotiate mailbox API version with the PF.
1095 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1096 * Then we try to negotiate starting with the most recent one.
1097 * If all negotiation attempts fail, then we will proceed with
1098 * the default one (ixgbe_mbox_api_10).
1101 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1105 /* start with highest supported, proceed down */
1106 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1112 i != RTE_DIM(sup_ver) &&
1113 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1119 generate_random_mac_addr(struct ether_addr *mac_addr)
1123 /* Set Organizationally Unique Identifier (OUI) prefix. */
1124 mac_addr->addr_bytes[0] = 0x00;
1125 mac_addr->addr_bytes[1] = 0x09;
1126 mac_addr->addr_bytes[2] = 0xC0;
1127 /* Force indication of locally assigned MAC address. */
1128 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1129 /* Generate the last 3 bytes of the MAC address with a random number. */
1130 random = rte_rand();
1131 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1135 * Virtual Function device init
1138 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1142 struct rte_pci_device *pci_dev;
1143 struct ixgbe_hw *hw =
1144 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1145 struct ixgbe_vfta * shadow_vfta =
1146 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1147 struct ixgbe_hwstrip *hwstrip =
1148 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1149 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1151 PMD_INIT_FUNC_TRACE();
1153 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1154 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1155 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1157 /* for secondary processes, we don't initialise any further as primary
1158 * has already done this work. Only check we don't need a different
1160 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1161 if (eth_dev->data->scattered_rx)
1162 eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1166 pci_dev = eth_dev->pci_dev;
1168 hw->device_id = pci_dev->id.device_id;
1169 hw->vendor_id = pci_dev->id.vendor_id;
1170 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1172 /* initialize the vfta */
1173 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1175 /* initialize the hw strip bitmap*/
1176 memset(hwstrip, 0, sizeof(*hwstrip));
1178 /* Initialize the shared code (base driver) */
1179 diag = ixgbe_init_shared_code(hw);
1180 if (diag != IXGBE_SUCCESS) {
1181 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1185 /* init_mailbox_params */
1186 hw->mbx.ops.init_params(hw);
1188 /* Reset the hw statistics */
1189 ixgbevf_dev_stats_reset(eth_dev);
1191 /* Disable the interrupts for VF */
1192 ixgbevf_intr_disable(hw);
1194 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1195 diag = hw->mac.ops.reset_hw(hw);
1198 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1199 * the underlying PF driver has not assigned a MAC address to the VF.
1200 * In this case, assign a random MAC address.
1202 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1203 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1207 /* negotiate mailbox API version to use with the PF. */
1208 ixgbevf_negotiate_api(hw);
1210 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1211 ixgbevf_get_queues(hw, &tcs, &tc);
1213 /* Allocate memory for storing MAC addresses */
1214 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1215 hw->mac.num_rar_entries, 0);
1216 if (eth_dev->data->mac_addrs == NULL) {
1218 "Failed to allocate %u bytes needed to store "
1220 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1224 /* Generate a random MAC address, if none was assigned by PF. */
1225 if (is_zero_ether_addr(perm_addr)) {
1226 generate_random_mac_addr(perm_addr);
1227 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1229 rte_free(eth_dev->data->mac_addrs);
1230 eth_dev->data->mac_addrs = NULL;
1233 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1234 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1235 "%02x:%02x:%02x:%02x:%02x:%02x",
1236 perm_addr->addr_bytes[0],
1237 perm_addr->addr_bytes[1],
1238 perm_addr->addr_bytes[2],
1239 perm_addr->addr_bytes[3],
1240 perm_addr->addr_bytes[4],
1241 perm_addr->addr_bytes[5]);
1244 /* Copy the permanent MAC address */
1245 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1247 /* reset the hardware with the new settings */
1248 diag = hw->mac.ops.start_hw(hw);
1254 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1258 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1259 eth_dev->data->port_id, pci_dev->id.vendor_id,
1260 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1265 /* Virtual Function device uninit */
1268 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1270 struct ixgbe_hw *hw;
1273 PMD_INIT_FUNC_TRACE();
1275 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1278 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1280 if (hw->adapter_stopped == 0)
1281 ixgbevf_dev_close(eth_dev);
1283 eth_dev->dev_ops = NULL;
1284 eth_dev->rx_pkt_burst = NULL;
1285 eth_dev->tx_pkt_burst = NULL;
1287 /* Disable the interrupts for VF */
1288 ixgbevf_intr_disable(hw);
1290 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1291 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1292 eth_dev->data->rx_queues[i] = NULL;
1294 eth_dev->data->nb_rx_queues = 0;
1296 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1297 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1298 eth_dev->data->tx_queues[i] = NULL;
1300 eth_dev->data->nb_tx_queues = 0;
1302 rte_free(eth_dev->data->mac_addrs);
1303 eth_dev->data->mac_addrs = NULL;
1308 static struct eth_driver rte_ixgbe_pmd = {
1310 .name = "rte_ixgbe_pmd",
1311 .id_table = pci_id_ixgbe_map,
1312 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1313 RTE_PCI_DRV_DETACHABLE,
1315 .eth_dev_init = eth_ixgbe_dev_init,
1316 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1317 .dev_private_size = sizeof(struct ixgbe_adapter),
1321 * virtual function driver struct
1323 static struct eth_driver rte_ixgbevf_pmd = {
1325 .name = "rte_ixgbevf_pmd",
1326 .id_table = pci_id_ixgbevf_map,
1327 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1329 .eth_dev_init = eth_ixgbevf_dev_init,
1330 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1331 .dev_private_size = sizeof(struct ixgbe_adapter),
1335 * Driver initialization routine.
1336 * Invoked once at EAL init time.
1337 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1340 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1342 PMD_INIT_FUNC_TRACE();
1344 rte_eth_driver_register(&rte_ixgbe_pmd);
1349 * VF Driver initialization routine.
1350 * Invoked one at EAL init time.
1351 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1354 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1356 PMD_INIT_FUNC_TRACE();
1358 rte_eth_driver_register(&rte_ixgbevf_pmd);
1363 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1365 struct ixgbe_hw *hw =
1366 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1367 struct ixgbe_vfta * shadow_vfta =
1368 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1373 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1374 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1375 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1380 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1382 /* update local VFTA copy */
1383 shadow_vfta->vfta[vid_idx] = vfta;
1389 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1392 ixgbe_vlan_hw_strip_enable(dev, queue);
1394 ixgbe_vlan_hw_strip_disable(dev, queue);
1398 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1400 struct ixgbe_hw *hw =
1401 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1403 /* Only the high 16-bits is valid */
1404 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1408 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1410 struct ixgbe_hw *hw =
1411 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1414 PMD_INIT_FUNC_TRACE();
1416 /* Filter Table Disable */
1417 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1418 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1420 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1424 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1426 struct ixgbe_hw *hw =
1427 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428 struct ixgbe_vfta * shadow_vfta =
1429 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1433 PMD_INIT_FUNC_TRACE();
1435 /* Filter Table Enable */
1436 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1437 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1438 vlnctrl |= IXGBE_VLNCTRL_VFE;
1440 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1442 /* write whatever is in local vfta copy */
1443 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1444 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1448 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1450 struct ixgbe_hwstrip *hwstrip =
1451 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1453 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1457 IXGBE_SET_HWSTRIP(hwstrip, queue);
1459 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1463 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1465 struct ixgbe_hw *hw =
1466 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1469 PMD_INIT_FUNC_TRACE();
1471 if (hw->mac.type == ixgbe_mac_82598EB) {
1472 /* No queue level support */
1473 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1477 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1478 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1479 ctrl &= ~IXGBE_RXDCTL_VME;
1480 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1482 /* record those setting for HW strip per queue */
1483 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1487 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1489 struct ixgbe_hw *hw =
1490 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1493 PMD_INIT_FUNC_TRACE();
1495 if (hw->mac.type == ixgbe_mac_82598EB) {
1496 /* No queue level supported */
1497 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1501 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1502 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1503 ctrl |= IXGBE_RXDCTL_VME;
1504 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1506 /* record those setting for HW strip per queue */
1507 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1511 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1513 struct ixgbe_hw *hw =
1514 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1518 PMD_INIT_FUNC_TRACE();
1520 if (hw->mac.type == ixgbe_mac_82598EB) {
1521 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1522 ctrl &= ~IXGBE_VLNCTRL_VME;
1523 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1526 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1527 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1528 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1529 ctrl &= ~IXGBE_RXDCTL_VME;
1530 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1532 /* record those setting for HW strip per queue */
1533 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1539 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1541 struct ixgbe_hw *hw =
1542 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1546 PMD_INIT_FUNC_TRACE();
1548 if (hw->mac.type == ixgbe_mac_82598EB) {
1549 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1550 ctrl |= IXGBE_VLNCTRL_VME;
1551 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1554 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1555 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1556 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1557 ctrl |= IXGBE_RXDCTL_VME;
1558 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1560 /* record those setting for HW strip per queue */
1561 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1567 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1569 struct ixgbe_hw *hw =
1570 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1573 PMD_INIT_FUNC_TRACE();
1575 /* DMATXCTRL: Geric Double VLAN Disable */
1576 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1577 ctrl &= ~IXGBE_DMATXCTL_GDV;
1578 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1580 /* CTRL_EXT: Global Double VLAN Disable */
1581 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1582 ctrl &= ~IXGBE_EXTENDED_VLAN;
1583 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1588 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1590 struct ixgbe_hw *hw =
1591 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1594 PMD_INIT_FUNC_TRACE();
1596 /* DMATXCTRL: Geric Double VLAN Enable */
1597 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1598 ctrl |= IXGBE_DMATXCTL_GDV;
1599 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1601 /* CTRL_EXT: Global Double VLAN Enable */
1602 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1603 ctrl |= IXGBE_EXTENDED_VLAN;
1604 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1607 * VET EXT field in the EXVET register = 0x8100 by default
1608 * So no need to change. Same to VT field of DMATXCTL register
1613 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1615 if(mask & ETH_VLAN_STRIP_MASK){
1616 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1617 ixgbe_vlan_hw_strip_enable_all(dev);
1619 ixgbe_vlan_hw_strip_disable_all(dev);
1622 if(mask & ETH_VLAN_FILTER_MASK){
1623 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1624 ixgbe_vlan_hw_filter_enable(dev);
1626 ixgbe_vlan_hw_filter_disable(dev);
1629 if(mask & ETH_VLAN_EXTEND_MASK){
1630 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1631 ixgbe_vlan_hw_extend_enable(dev);
1633 ixgbe_vlan_hw_extend_disable(dev);
1638 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1640 struct ixgbe_hw *hw =
1641 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1642 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1643 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1644 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1645 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1649 ixgbe_dev_configure(struct rte_eth_dev *dev)
1651 struct ixgbe_interrupt *intr =
1652 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1653 struct ixgbe_adapter *adapter =
1654 (struct ixgbe_adapter *)dev->data->dev_private;
1656 PMD_INIT_FUNC_TRACE();
1658 /* set flag to update link status after init */
1659 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1662 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1663 * allocation or vector Rx preconditions we will reset it.
1665 adapter->rx_bulk_alloc_allowed = true;
1666 adapter->rx_vec_allowed = true;
1672 * Configure device link speed and setup link.
1673 * It returns 0 on success.
1676 ixgbe_dev_start(struct rte_eth_dev *dev)
1678 struct ixgbe_hw *hw =
1679 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1680 struct ixgbe_vf_info *vfinfo =
1681 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1682 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1684 uint32_t intr_vector = 0;
1686 int err, link_up = 0, negotiate = 0;
1692 PMD_INIT_FUNC_TRACE();
1694 /* IXGBE devices don't support half duplex */
1695 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1696 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1697 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1698 dev->data->dev_conf.link_duplex,
1699 dev->data->port_id);
1704 hw->adapter_stopped = 0;
1705 ixgbe_stop_adapter(hw);
1707 /* reinitialize adapter
1708 * this calls reset and start */
1709 status = ixgbe_pf_reset_hw(hw);
1712 hw->mac.ops.start_hw(hw);
1713 hw->mac.get_link_status = true;
1715 /* configure PF module if SRIOV enabled */
1716 ixgbe_pf_host_configure(dev);
1719 /* check and configure queue intr-vector mapping */
1720 if (dev->data->dev_conf.intr_conf.rxq != 0)
1721 intr_vector = dev->data->nb_rx_queues;
1723 if (rte_intr_efd_enable(intr_handle, intr_vector))
1726 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1727 intr_handle->intr_vec =
1728 rte_zmalloc("intr_vec",
1729 dev->data->nb_rx_queues * sizeof(int),
1731 if (intr_handle->intr_vec == NULL) {
1732 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1733 " intr_vec\n", dev->data->nb_rx_queues);
1739 /* confiugre msix for sleep until rx interrupt */
1740 ixgbe_configure_msix(dev);
1742 /* initialize transmission unit */
1743 ixgbe_dev_tx_init(dev);
1745 /* This can fail when allocating mbufs for descriptor rings */
1746 err = ixgbe_dev_rx_init(dev);
1748 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1752 err = ixgbe_dev_rxtx_start(dev);
1754 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1758 /* Skip link setup if loopback mode is enabled for 82599. */
1759 if (hw->mac.type == ixgbe_mac_82599EB &&
1760 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1761 goto skip_link_setup;
1763 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1764 err = hw->mac.ops.setup_sfp(hw);
1769 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1770 /* Turn on the copper */
1771 ixgbe_set_phy_power(hw, true);
1773 /* Turn on the laser */
1774 ixgbe_enable_tx_laser(hw);
1777 err = ixgbe_check_link(hw, &speed, &link_up, 0);
1780 dev->data->dev_link.link_status = link_up;
1782 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1786 switch(dev->data->dev_conf.link_speed) {
1787 case ETH_LINK_SPEED_AUTONEG:
1788 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1789 IXGBE_LINK_SPEED_82599_AUTONEG :
1790 IXGBE_LINK_SPEED_82598_AUTONEG;
1792 case ETH_LINK_SPEED_100:
1794 * Invalid for 82598 but error will be detected by
1795 * ixgbe_setup_link()
1797 speed = IXGBE_LINK_SPEED_100_FULL;
1799 case ETH_LINK_SPEED_1000:
1800 speed = IXGBE_LINK_SPEED_1GB_FULL;
1802 case ETH_LINK_SPEED_10000:
1803 speed = IXGBE_LINK_SPEED_10GB_FULL;
1806 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1807 dev->data->dev_conf.link_speed,
1808 dev->data->port_id);
1812 err = ixgbe_setup_link(hw, speed, link_up);
1818 /* check if lsc interrupt is enabled */
1819 if (dev->data->dev_conf.intr_conf.lsc != 0) {
1820 if (rte_intr_allow_others(intr_handle)) {
1821 rte_intr_callback_register(intr_handle,
1822 ixgbe_dev_interrupt_handler,
1824 ixgbe_dev_lsc_interrupt_setup(dev);
1826 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1827 " no intr multiplex\n");
1831 /* check if rxq interrupt is enabled */
1832 if (dev->data->dev_conf.intr_conf.rxq != 0)
1833 ixgbe_dev_rxq_interrupt_setup(dev);
1836 /* enable uio/vfio intr/eventfd mapping */
1837 rte_intr_enable(intr_handle);
1839 /* resume enabled intr since hw reset */
1840 ixgbe_enable_intr(dev);
1842 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1843 ETH_VLAN_EXTEND_MASK;
1844 ixgbe_vlan_offload_set(dev, mask);
1846 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1847 /* Enable vlan filtering for VMDq */
1848 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1851 /* Configure DCB hw */
1852 ixgbe_configure_dcb(dev);
1854 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1855 err = ixgbe_fdir_configure(dev);
1860 /* Restore vf rate limit */
1861 if (vfinfo != NULL) {
1862 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1863 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1864 if (vfinfo[vf].tx_rate[idx] != 0)
1865 ixgbe_set_vf_rate_limit(dev, vf,
1866 vfinfo[vf].tx_rate[idx],
1870 ixgbe_restore_statistics_mapping(dev);
1875 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1876 ixgbe_dev_clear_queues(dev);
1881 * Stop device: disable rx and tx functions to allow for reconfiguring.
1884 ixgbe_dev_stop(struct rte_eth_dev *dev)
1886 struct rte_eth_link link;
1887 struct ixgbe_hw *hw =
1888 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1889 struct ixgbe_vf_info *vfinfo =
1890 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1891 struct ixgbe_filter_info *filter_info =
1892 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1893 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
1894 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1897 PMD_INIT_FUNC_TRACE();
1899 /* disable interrupts */
1900 ixgbe_disable_intr(hw);
1902 /* disable intr eventfd mapping */
1903 rte_intr_disable(intr_handle);
1906 ixgbe_pf_reset_hw(hw);
1907 hw->adapter_stopped = 0;
1910 ixgbe_stop_adapter(hw);
1912 for (vf = 0; vfinfo != NULL &&
1913 vf < dev->pci_dev->max_vfs; vf++)
1914 vfinfo[vf].clear_to_send = false;
1916 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1917 /* Turn off the copper */
1918 ixgbe_set_phy_power(hw, false);
1920 /* Turn off the laser */
1921 ixgbe_disable_tx_laser(hw);
1924 ixgbe_dev_clear_queues(dev);
1926 /* Clear stored conf */
1927 dev->data->scattered_rx = 0;
1930 /* Clear recorded link status */
1931 memset(&link, 0, sizeof(link));
1932 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1934 /* Remove all ntuple filters of the device */
1935 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1936 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1937 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1938 TAILQ_REMOVE(&filter_info->fivetuple_list,
1942 memset(filter_info->fivetuple_mask, 0,
1943 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1946 /* Clean datapath event and queue/vec mapping */
1947 rte_intr_efd_disable(intr_handle);
1948 if (intr_handle->intr_vec != NULL) {
1949 rte_free(intr_handle->intr_vec);
1950 intr_handle->intr_vec = NULL;
1956 * Set device link up: enable tx.
1959 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1961 struct ixgbe_hw *hw =
1962 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1963 if (hw->mac.type == ixgbe_mac_82599EB) {
1964 #ifdef RTE_NIC_BYPASS
1965 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1966 /* Not suported in bypass mode */
1967 PMD_INIT_LOG(ERR, "Set link up is not supported "
1968 "by device id 0x%x", hw->device_id);
1974 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1975 /* Turn on the copper */
1976 ixgbe_set_phy_power(hw, true);
1978 /* Turn on the laser */
1979 ixgbe_enable_tx_laser(hw);
1986 * Set device link down: disable tx.
1989 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1991 struct ixgbe_hw *hw =
1992 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1993 if (hw->mac.type == ixgbe_mac_82599EB) {
1994 #ifdef RTE_NIC_BYPASS
1995 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1996 /* Not suported in bypass mode */
1997 PMD_INIT_LOG(ERR, "Set link down is not supported "
1998 "by device id 0x%x", hw->device_id);
2004 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2005 /* Turn off the copper */
2006 ixgbe_set_phy_power(hw, false);
2008 /* Turn off the laser */
2009 ixgbe_disable_tx_laser(hw);
2016 * Reest and stop device.
2019 ixgbe_dev_close(struct rte_eth_dev *dev)
2021 struct ixgbe_hw *hw =
2022 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2024 PMD_INIT_FUNC_TRACE();
2026 ixgbe_pf_reset_hw(hw);
2028 ixgbe_dev_stop(dev);
2029 hw->adapter_stopped = 1;
2031 ixgbe_dev_free_queues(dev);
2033 ixgbe_disable_pcie_master(hw);
2035 /* reprogram the RAR[0] in case user changed it. */
2036 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2040 ixgbe_read_stats_registers(struct ixgbe_hw *hw, struct ixgbe_hw_stats
2041 *hw_stats, uint64_t *total_missed_rx,
2042 uint64_t *total_qbrc, uint64_t *total_qprc,
2043 uint64_t *rxnfgpc, uint64_t *txdgpc,
2044 uint64_t *total_qprdc)
2046 uint32_t bprc, lxon, lxoff, total;
2049 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2050 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2051 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2052 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2054 for (i = 0; i < 8; i++) {
2056 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2057 /* global total per queue */
2058 hw_stats->mpc[i] += mp;
2059 /* Running comprehensive total for stats display */
2060 *total_missed_rx += hw_stats->mpc[i];
2061 if (hw->mac.type == ixgbe_mac_82598EB)
2062 hw_stats->rnbc[i] +=
2063 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2064 hw_stats->pxontxc[i] +=
2065 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2066 hw_stats->pxonrxc[i] +=
2067 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2068 hw_stats->pxofftxc[i] +=
2069 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2070 hw_stats->pxoffrxc[i] +=
2071 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2072 hw_stats->pxon2offc[i] +=
2073 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2075 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2076 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2077 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2078 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2079 hw_stats->qbrc[i] +=
2080 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2081 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2082 hw_stats->qbtc[i] +=
2083 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2084 *total_qprdc += hw_stats->qprdc[i] +=
2085 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2087 *total_qprc += hw_stats->qprc[i];
2088 *total_qbrc += hw_stats->qbrc[i];
2090 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2091 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2092 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2094 /* Note that gprc counts missed packets */
2095 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2096 *rxnfgpc += IXGBE_READ_REG(hw, IXGBE_RXNFGPC);
2097 *txdgpc += IXGBE_READ_REG(hw, IXGBE_TXDGPC);
2099 if (hw->mac.type != ixgbe_mac_82598EB) {
2100 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2101 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2102 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2103 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2104 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2105 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2106 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2107 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2109 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2110 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2111 /* 82598 only has a counter in the high register */
2112 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2113 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2114 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2118 * Workaround: mprc hardware is incorrectly counting
2119 * broadcasts, so for now we subtract those.
2121 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2122 hw_stats->bprc += bprc;
2123 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2124 if (hw->mac.type == ixgbe_mac_82598EB)
2125 hw_stats->mprc -= bprc;
2127 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2128 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2129 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2130 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2131 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2132 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2134 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2135 hw_stats->lxontxc += lxon;
2136 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2137 hw_stats->lxofftxc += lxoff;
2138 total = lxon + lxoff;
2140 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2141 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2142 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2143 hw_stats->gptc -= total;
2144 hw_stats->mptc -= total;
2145 hw_stats->ptc64 -= total;
2146 hw_stats->gotc -= total * ETHER_MIN_LEN;
2148 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2149 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2150 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2151 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2152 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2153 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2154 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2155 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2156 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2157 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2158 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2159 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2160 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2161 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2162 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2163 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2164 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2165 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2166 /* Only read FCOE on 82599 */
2167 if (hw->mac.type != ixgbe_mac_82598EB) {
2168 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2169 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2170 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2171 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2172 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2175 /* Flow Director Stats registers */
2176 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2177 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2181 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2184 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2186 struct ixgbe_hw *hw =
2187 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2188 struct ixgbe_hw_stats *hw_stats =
2189 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2190 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2191 uint64_t rxnfgpc, txdgpc;
2194 total_missed_rx = 0;
2201 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2202 &total_qprc, &rxnfgpc, &txdgpc, &total_qprdc);
2207 /* Fill out the rte_eth_stats statistics structure */
2208 stats->ipackets = total_qprc;
2209 stats->ibytes = total_qbrc;
2210 stats->opackets = hw_stats->gptc;
2211 stats->obytes = hw_stats->gotc;
2213 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2214 stats->q_ipackets[i] = hw_stats->qprc[i];
2215 stats->q_opackets[i] = hw_stats->qptc[i];
2216 stats->q_ibytes[i] = hw_stats->qbrc[i];
2217 stats->q_obytes[i] = hw_stats->qbtc[i];
2218 stats->q_errors[i] = hw_stats->qprdc[i];
2222 stats->ierrors = hw_stats->crcerrs +
2238 /*txdgpc: packets that are DMA'ed*/
2239 /*gptc: packets that are sent*/
2240 stats->oerrors = txdgpc - hw_stats->gptc;
2244 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2246 struct ixgbe_hw_stats *stats =
2247 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2249 /* HW registers are cleared on read */
2250 ixgbe_dev_stats_get(dev, NULL);
2252 /* Reset software totals */
2253 memset(stats, 0, sizeof(*stats));
2257 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2260 struct ixgbe_hw *hw =
2261 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2262 struct ixgbe_hw_stats *hw_stats =
2263 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2264 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2265 uint64_t rxnfgpc, txdgpc;
2266 unsigned i, count = IXGBE_NB_XSTATS;
2271 total_missed_rx = 0;
2278 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2279 &total_qprc, &rxnfgpc, &txdgpc, &total_qprdc);
2281 /* If this is a reset xstats is NULL, and we have cleared the
2282 * registers by reading them.
2287 /* Extended stats */
2288 for (i = 0; i < IXGBE_NB_XSTATS; i++) {
2289 snprintf(xstats[i].name, sizeof(xstats[i].name),
2290 "%s", rte_ixgbe_stats_strings[i].name);
2291 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2292 rte_ixgbe_stats_strings[i].offset);
2299 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2301 struct ixgbe_hw_stats *stats =
2302 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2304 /* HW registers are cleared on read */
2305 ixgbe_dev_xstats_get(dev, NULL, IXGBE_NB_XSTATS);
2307 /* Reset software totals */
2308 memset(stats, 0, sizeof(*stats));
2312 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2314 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2315 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2316 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2318 /* Good Rx packet, include VF loopback */
2319 UPDATE_VF_STAT(IXGBE_VFGPRC,
2320 hw_stats->last_vfgprc, hw_stats->vfgprc);
2322 /* Good Rx octets, include VF loopback */
2323 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2324 hw_stats->last_vfgorc, hw_stats->vfgorc);
2326 /* Good Tx packet, include VF loopback */
2327 UPDATE_VF_STAT(IXGBE_VFGPTC,
2328 hw_stats->last_vfgptc, hw_stats->vfgptc);
2330 /* Good Tx octets, include VF loopback */
2331 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2332 hw_stats->last_vfgotc, hw_stats->vfgotc);
2334 /* Rx Multicst Packet */
2335 UPDATE_VF_STAT(IXGBE_VFMPRC,
2336 hw_stats->last_vfmprc, hw_stats->vfmprc);
2341 stats->ipackets = hw_stats->vfgprc;
2342 stats->ibytes = hw_stats->vfgorc;
2343 stats->opackets = hw_stats->vfgptc;
2344 stats->obytes = hw_stats->vfgotc;
2345 stats->imcasts = hw_stats->vfmprc;
2346 /* stats->imcasts should be removed as imcasts is deprecated */
2350 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2352 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2353 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2355 /* Sync HW register to the last stats */
2356 ixgbevf_dev_stats_get(dev, NULL);
2358 /* reset HW current stats*/
2359 hw_stats->vfgprc = 0;
2360 hw_stats->vfgorc = 0;
2361 hw_stats->vfgptc = 0;
2362 hw_stats->vfgotc = 0;
2363 hw_stats->vfmprc = 0;
2368 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2370 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2372 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2373 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2374 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2375 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2376 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2377 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2378 dev_info->max_vfs = dev->pci_dev->max_vfs;
2379 if (hw->mac.type == ixgbe_mac_82598EB)
2380 dev_info->max_vmdq_pools = ETH_16_POOLS;
2382 dev_info->max_vmdq_pools = ETH_64_POOLS;
2383 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2384 dev_info->rx_offload_capa =
2385 DEV_RX_OFFLOAD_VLAN_STRIP |
2386 DEV_RX_OFFLOAD_IPV4_CKSUM |
2387 DEV_RX_OFFLOAD_UDP_CKSUM |
2388 DEV_RX_OFFLOAD_TCP_CKSUM;
2391 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2394 if ((hw->mac.type == ixgbe_mac_82599EB ||
2395 hw->mac.type == ixgbe_mac_X540) &&
2396 !RTE_ETH_DEV_SRIOV(dev).active)
2397 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2399 dev_info->tx_offload_capa =
2400 DEV_TX_OFFLOAD_VLAN_INSERT |
2401 DEV_TX_OFFLOAD_IPV4_CKSUM |
2402 DEV_TX_OFFLOAD_UDP_CKSUM |
2403 DEV_TX_OFFLOAD_TCP_CKSUM |
2404 DEV_TX_OFFLOAD_SCTP_CKSUM |
2405 DEV_TX_OFFLOAD_TCP_TSO;
2407 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2409 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2410 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2411 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2413 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2417 dev_info->default_txconf = (struct rte_eth_txconf) {
2419 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2420 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2421 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2423 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2424 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2425 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2426 ETH_TXQ_FLAGS_NOOFFLOADS,
2428 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2429 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2430 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2434 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2435 struct rte_eth_dev_info *dev_info)
2437 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2439 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2440 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2441 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2442 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2443 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2444 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2445 dev_info->max_vfs = dev->pci_dev->max_vfs;
2446 if (hw->mac.type == ixgbe_mac_82598EB)
2447 dev_info->max_vmdq_pools = ETH_16_POOLS;
2449 dev_info->max_vmdq_pools = ETH_64_POOLS;
2450 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2451 DEV_RX_OFFLOAD_IPV4_CKSUM |
2452 DEV_RX_OFFLOAD_UDP_CKSUM |
2453 DEV_RX_OFFLOAD_TCP_CKSUM;
2454 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2455 DEV_TX_OFFLOAD_IPV4_CKSUM |
2456 DEV_TX_OFFLOAD_UDP_CKSUM |
2457 DEV_TX_OFFLOAD_TCP_CKSUM |
2458 DEV_TX_OFFLOAD_SCTP_CKSUM;
2460 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2462 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2463 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2464 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2466 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2470 dev_info->default_txconf = (struct rte_eth_txconf) {
2472 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2473 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2474 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2476 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2477 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2478 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2479 ETH_TXQ_FLAGS_NOOFFLOADS,
2483 /* return 0 means link status changed, -1 means not changed */
2485 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2487 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2488 struct rte_eth_link link, old;
2489 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2493 link.link_status = 0;
2494 link.link_speed = 0;
2495 link.link_duplex = 0;
2496 memset(&old, 0, sizeof(old));
2497 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2499 hw->mac.get_link_status = true;
2501 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2502 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2503 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2505 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2508 link.link_speed = ETH_LINK_SPEED_100;
2509 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2510 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2511 if (link.link_status == old.link_status)
2517 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2518 if (link.link_status == old.link_status)
2522 link.link_status = 1;
2523 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2525 switch (link_speed) {
2527 case IXGBE_LINK_SPEED_UNKNOWN:
2528 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2529 link.link_speed = ETH_LINK_SPEED_100;
2532 case IXGBE_LINK_SPEED_100_FULL:
2533 link.link_speed = ETH_LINK_SPEED_100;
2536 case IXGBE_LINK_SPEED_1GB_FULL:
2537 link.link_speed = ETH_LINK_SPEED_1000;
2540 case IXGBE_LINK_SPEED_10GB_FULL:
2541 link.link_speed = ETH_LINK_SPEED_10000;
2544 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2546 if (link.link_status == old.link_status)
2553 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2555 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2558 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2559 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2560 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2564 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2566 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2569 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2570 fctrl &= (~IXGBE_FCTRL_UPE);
2571 if (dev->data->all_multicast == 1)
2572 fctrl |= IXGBE_FCTRL_MPE;
2574 fctrl &= (~IXGBE_FCTRL_MPE);
2575 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2579 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2581 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2584 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2585 fctrl |= IXGBE_FCTRL_MPE;
2586 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2590 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2592 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2595 if (dev->data->promiscuous == 1)
2596 return; /* must remain in all_multicast mode */
2598 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2599 fctrl &= (~IXGBE_FCTRL_MPE);
2600 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2604 * It clears the interrupt causes and enables the interrupt.
2605 * It will be called once only during nic initialized.
2608 * Pointer to struct rte_eth_dev.
2611 * - On success, zero.
2612 * - On failure, a negative value.
2615 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2617 struct ixgbe_interrupt *intr =
2618 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2620 ixgbe_dev_link_status_print(dev);
2621 intr->mask |= IXGBE_EICR_LSC;
2627 * It clears the interrupt causes and enables the interrupt.
2628 * It will be called once only during nic initialized.
2631 * Pointer to struct rte_eth_dev.
2634 * - On success, zero.
2635 * - On failure, a negative value.
2639 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2641 struct ixgbe_interrupt *intr =
2642 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2644 intr->mask |= IXGBE_EICR_RTX_QUEUE;
2651 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2654 * Pointer to struct rte_eth_dev.
2657 * - On success, zero.
2658 * - On failure, a negative value.
2661 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2664 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2665 struct ixgbe_interrupt *intr =
2666 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2668 /* clear all cause mask */
2669 ixgbe_disable_intr(hw);
2671 /* read-on-clear nic registers here */
2672 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2673 PMD_DRV_LOG(INFO, "eicr %x", eicr);
2677 /* set flag for async link update */
2678 if (eicr & IXGBE_EICR_LSC)
2679 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2681 if (eicr & IXGBE_EICR_MAILBOX)
2682 intr->flags |= IXGBE_FLAG_MAILBOX;
2688 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
2691 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2692 struct ixgbe_interrupt *intr =
2693 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2695 /* clear all cause mask */
2696 ixgbevf_intr_disable(hw);
2698 /* read-on-clear nic registers here */
2699 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
2700 PMD_DRV_LOG(INFO, "eicr %x", eicr);
2704 /* set flag for async link update */
2705 if (eicr & IXGBE_EICR_LSC)
2706 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2712 * It gets and then prints the link status.
2715 * Pointer to struct rte_eth_dev.
2718 * - On success, zero.
2719 * - On failure, a negative value.
2722 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2724 struct rte_eth_link link;
2726 memset(&link, 0, sizeof(link));
2727 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2728 if (link.link_status) {
2729 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2730 (int)(dev->data->port_id),
2731 (unsigned)link.link_speed,
2732 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2733 "full-duplex" : "half-duplex");
2735 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2736 (int)(dev->data->port_id));
2738 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2739 dev->pci_dev->addr.domain,
2740 dev->pci_dev->addr.bus,
2741 dev->pci_dev->addr.devid,
2742 dev->pci_dev->addr.function);
2746 * It executes link_update after knowing an interrupt occurred.
2749 * Pointer to struct rte_eth_dev.
2752 * - On success, zero.
2753 * - On failure, a negative value.
2756 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2758 struct ixgbe_interrupt *intr =
2759 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2761 struct rte_eth_link link;
2762 int intr_enable_delay = false;
2764 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2766 if (intr->flags & IXGBE_FLAG_MAILBOX) {
2767 ixgbe_pf_mbx_process(dev);
2768 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2771 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2772 /* get the link status before link update, for predicting later */
2773 memset(&link, 0, sizeof(link));
2774 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2776 ixgbe_dev_link_update(dev, 0);
2779 if (!link.link_status)
2780 /* handle it 1 sec later, wait it being stable */
2781 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2782 /* likely to down */
2784 /* handle it 4 sec later, wait it being stable */
2785 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2787 ixgbe_dev_link_status_print(dev);
2789 intr_enable_delay = true;
2792 if (intr_enable_delay) {
2793 if (rte_eal_alarm_set(timeout * 1000,
2794 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2795 PMD_DRV_LOG(ERR, "Error setting alarm");
2797 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2798 ixgbe_enable_intr(dev);
2799 rte_intr_enable(&(dev->pci_dev->intr_handle));
2807 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
2809 struct ixgbe_hw *hw =
2810 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2812 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2813 ixgbevf_intr_enable(hw);
2814 rte_intr_enable(&dev->pci_dev->intr_handle);
2819 * Interrupt handler which shall be registered for alarm callback for delayed
2820 * handling specific interrupt to wait for the stable nic state. As the
2821 * NIC interrupt state is not stable for ixgbe after link is just down,
2822 * it needs to wait 4 seconds to get the stable status.
2825 * Pointer to interrupt handle.
2827 * The address of parameter (struct rte_eth_dev *) regsitered before.
2833 ixgbe_dev_interrupt_delayed_handler(void *param)
2835 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2836 struct ixgbe_interrupt *intr =
2837 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2838 struct ixgbe_hw *hw =
2839 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2842 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2843 if (eicr & IXGBE_EICR_MAILBOX)
2844 ixgbe_pf_mbx_process(dev);
2846 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2847 ixgbe_dev_link_update(dev, 0);
2848 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2849 ixgbe_dev_link_status_print(dev);
2850 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2853 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2854 ixgbe_enable_intr(dev);
2855 rte_intr_enable(&(dev->pci_dev->intr_handle));
2859 * Interrupt handler triggered by NIC for handling
2860 * specific interrupt.
2863 * Pointer to interrupt handle.
2865 * The address of parameter (struct rte_eth_dev *) regsitered before.
2871 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2874 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2876 ixgbe_dev_interrupt_get_status(dev);
2877 ixgbe_dev_interrupt_action(dev);
2881 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2884 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2886 ixgbevf_dev_interrupt_get_status(dev);
2887 ixgbevf_dev_interrupt_action(dev);
2891 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2893 struct ixgbe_hw *hw;
2895 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2896 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2900 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2902 struct ixgbe_hw *hw;
2904 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2905 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2909 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2911 struct ixgbe_hw *hw;
2917 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2919 fc_conf->pause_time = hw->fc.pause_time;
2920 fc_conf->high_water = hw->fc.high_water[0];
2921 fc_conf->low_water = hw->fc.low_water[0];
2922 fc_conf->send_xon = hw->fc.send_xon;
2923 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2926 * Return rx_pause status according to actual setting of
2929 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2930 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2936 * Return tx_pause status according to actual setting of
2939 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2940 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2945 if (rx_pause && tx_pause)
2946 fc_conf->mode = RTE_FC_FULL;
2948 fc_conf->mode = RTE_FC_RX_PAUSE;
2950 fc_conf->mode = RTE_FC_TX_PAUSE;
2952 fc_conf->mode = RTE_FC_NONE;
2958 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2960 struct ixgbe_hw *hw;
2962 uint32_t rx_buf_size;
2963 uint32_t max_high_water;
2965 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2972 PMD_INIT_FUNC_TRACE();
2974 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2975 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2976 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2979 * At least reserve one Ethernet frame for watermark
2980 * high_water/low_water in kilo bytes for ixgbe
2982 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2983 if ((fc_conf->high_water > max_high_water) ||
2984 (fc_conf->high_water < fc_conf->low_water)) {
2985 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2986 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2990 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2991 hw->fc.pause_time = fc_conf->pause_time;
2992 hw->fc.high_water[0] = fc_conf->high_water;
2993 hw->fc.low_water[0] = fc_conf->low_water;
2994 hw->fc.send_xon = fc_conf->send_xon;
2995 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
2997 err = ixgbe_fc_enable(hw);
2999 /* Not negotiated is not an error case */
3000 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3002 /* check if we want to forward MAC frames - driver doesn't have native
3003 * capability to do that, so we'll write the registers ourselves */
3005 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3007 /* set or clear MFLCN.PMCF bit depending on configuration */
3008 if (fc_conf->mac_ctrl_frame_fwd != 0)
3009 mflcn |= IXGBE_MFLCN_PMCF;
3011 mflcn &= ~IXGBE_MFLCN_PMCF;
3013 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3014 IXGBE_WRITE_FLUSH(hw);
3019 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3024 * ixgbe_pfc_enable_generic - Enable flow control
3025 * @hw: pointer to hardware structure
3026 * @tc_num: traffic class number
3027 * Enable flow control according to the current settings.
3030 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3033 uint32_t mflcn_reg, fccfg_reg;
3035 uint32_t fcrtl, fcrth;
3039 /* Validate the water mark configuration */
3040 if (!hw->fc.pause_time) {
3041 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3045 /* Low water mark of zero causes XOFF floods */
3046 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3047 /* High/Low water can not be 0 */
3048 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
3049 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3050 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3054 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3055 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3056 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3060 /* Negotiate the fc mode to use */
3061 ixgbe_fc_autoneg(hw);
3063 /* Disable any previous flow control settings */
3064 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3065 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3067 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3068 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3070 switch (hw->fc.current_mode) {
3073 * If the count of enabled RX Priority Flow control >1,
3074 * and the TX pause can not be disabled
3077 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3078 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3079 if (reg & IXGBE_FCRTH_FCEN)
3083 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3085 case ixgbe_fc_rx_pause:
3087 * Rx Flow control is enabled and Tx Flow control is
3088 * disabled by software override. Since there really
3089 * isn't a way to advertise that we are capable of RX
3090 * Pause ONLY, we will advertise that we support both
3091 * symmetric and asymmetric Rx PAUSE. Later, we will
3092 * disable the adapter's ability to send PAUSE frames.
3094 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3096 * If the count of enabled RX Priority Flow control >1,
3097 * and the TX pause can not be disabled
3100 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3101 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3102 if (reg & IXGBE_FCRTH_FCEN)
3106 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3108 case ixgbe_fc_tx_pause:
3110 * Tx Flow control is enabled, and Rx Flow control is
3111 * disabled by software override.
3113 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3116 /* Flow control (both Rx and Tx) is enabled by SW override. */
3117 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3118 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3121 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3122 ret_val = IXGBE_ERR_CONFIG;
3127 /* Set 802.3x based flow control settings. */
3128 mflcn_reg |= IXGBE_MFLCN_DPF;
3129 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3130 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3132 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3133 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3134 hw->fc.high_water[tc_num]) {
3135 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3136 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3137 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3139 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3141 * In order to prevent Tx hangs when the internal Tx
3142 * switch is enabled we must set the high water mark
3143 * to the maximum FCRTH value. This allows the Tx
3144 * switch to function even under heavy Rx workloads.
3146 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3148 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3150 /* Configure pause time (2 TCs per register) */
3151 reg = hw->fc.pause_time * 0x00010001;
3152 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3153 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3155 /* Configure flow control refresh threshold value */
3156 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3163 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3165 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3166 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3168 if(hw->mac.type != ixgbe_mac_82598EB) {
3169 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3175 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3178 uint32_t rx_buf_size;
3179 uint32_t max_high_water;
3181 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3182 struct ixgbe_hw *hw =
3183 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3184 struct ixgbe_dcb_config *dcb_config =
3185 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3187 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3194 PMD_INIT_FUNC_TRACE();
3196 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3197 tc_num = map[pfc_conf->priority];
3198 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3199 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3201 * At least reserve one Ethernet frame for watermark
3202 * high_water/low_water in kilo bytes for ixgbe
3204 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3205 if ((pfc_conf->fc.high_water > max_high_water) ||
3206 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3207 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3208 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3212 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3213 hw->fc.pause_time = pfc_conf->fc.pause_time;
3214 hw->fc.send_xon = pfc_conf->fc.send_xon;
3215 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
3216 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3218 err = ixgbe_dcb_pfc_enable(dev,tc_num);
3220 /* Not negotiated is not an error case */
3221 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3224 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3229 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3230 struct rte_eth_rss_reta_entry64 *reta_conf,
3235 uint16_t idx, shift;
3236 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3238 PMD_INIT_FUNC_TRACE();
3239 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3240 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3241 "(%d) doesn't match the number hardware can supported "
3242 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3246 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3247 idx = i / RTE_RETA_GROUP_SIZE;
3248 shift = i % RTE_RETA_GROUP_SIZE;
3249 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3253 if (mask == IXGBE_4_BIT_MASK)
3256 r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
3257 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3258 if (mask & (0x1 << j))
3259 reta |= reta_conf[idx].reta[shift + j] <<
3262 reta |= r & (IXGBE_8_BIT_MASK <<
3265 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3272 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3273 struct rte_eth_rss_reta_entry64 *reta_conf,
3278 uint16_t idx, shift;
3279 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3281 PMD_INIT_FUNC_TRACE();
3282 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3283 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3284 "(%d) doesn't match the number hardware can supported "
3285 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3289 for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
3290 idx = i / RTE_RETA_GROUP_SIZE;
3291 shift = i % RTE_RETA_GROUP_SIZE;
3292 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3297 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
3298 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3299 if (mask & (0x1 << j))
3300 reta_conf[idx].reta[shift + j] =
3301 ((reta >> (CHAR_BIT * j)) &
3310 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3311 uint32_t index, uint32_t pool)
3313 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3314 uint32_t enable_addr = 1;
3316 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3320 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3322 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3324 ixgbe_clear_rar(hw, index);
3328 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3330 ixgbe_remove_rar(dev, 0);
3332 ixgbe_add_rar(dev, addr, 0, 0);
3336 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3340 struct ixgbe_hw *hw;
3341 struct rte_eth_dev_info dev_info;
3342 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3344 ixgbe_dev_info_get(dev, &dev_info);
3346 /* check that mtu is within the allowed range */
3347 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3350 /* refuse mtu that requires the support of scattered packets when this
3351 * feature has not been enabled before. */
3352 if (!dev->data->scattered_rx &&
3353 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3354 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3357 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3358 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3360 /* switch to jumbo mode if needed */
3361 if (frame_size > ETHER_MAX_LEN) {
3362 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3363 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3365 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3366 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3368 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3370 /* update max frame size */
3371 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3373 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3374 maxfrs &= 0x0000FFFF;
3375 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3376 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3382 * Virtual Function operations
3385 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3387 PMD_INIT_FUNC_TRACE();
3389 /* Clear interrupt mask to stop from interrupts being generated */
3390 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3392 IXGBE_WRITE_FLUSH(hw);
3396 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3398 PMD_INIT_FUNC_TRACE();
3400 /* VF enable interrupt autoclean */
3401 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3402 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3403 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3405 IXGBE_WRITE_FLUSH(hw);
3409 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3411 struct rte_eth_conf* conf = &dev->data->dev_conf;
3412 struct ixgbe_adapter *adapter =
3413 (struct ixgbe_adapter *)dev->data->dev_private;
3415 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3416 dev->data->port_id);
3419 * VF has no ability to enable/disable HW CRC
3420 * Keep the persistent behavior the same as Host PF
3422 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3423 if (!conf->rxmode.hw_strip_crc) {
3424 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
3425 conf->rxmode.hw_strip_crc = 1;
3428 if (conf->rxmode.hw_strip_crc) {
3429 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
3430 conf->rxmode.hw_strip_crc = 0;
3435 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3436 * allocation or vector Rx preconditions we will reset it.
3438 adapter->rx_bulk_alloc_allowed = true;
3439 adapter->rx_vec_allowed = true;
3445 ixgbevf_dev_start(struct rte_eth_dev *dev)
3447 struct ixgbe_hw *hw =
3448 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3450 uint32_t intr_vector = 0;
3452 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3456 PMD_INIT_FUNC_TRACE();
3458 hw->mac.ops.reset_hw(hw);
3459 hw->mac.get_link_status = true;
3461 /* negotiate mailbox API version to use with the PF. */
3462 ixgbevf_negotiate_api(hw);
3464 ixgbevf_dev_tx_init(dev);
3466 /* This can fail when allocating mbufs for descriptor rings */
3467 err = ixgbevf_dev_rx_init(dev);
3469 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3470 ixgbe_dev_clear_queues(dev);
3475 ixgbevf_set_vfta_all(dev,1);
3478 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3479 ETH_VLAN_EXTEND_MASK;
3480 ixgbevf_vlan_offload_set(dev, mask);
3482 ixgbevf_dev_rxtx_start(dev);
3485 /* check and configure queue intr-vector mapping */
3486 if (dev->data->dev_conf.intr_conf.rxq != 0)
3487 intr_vector = dev->data->nb_rx_queues;
3489 if (rte_intr_efd_enable(intr_handle, intr_vector))
3492 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3493 intr_handle->intr_vec =
3494 rte_zmalloc("intr_vec",
3495 dev->data->nb_rx_queues * sizeof(int), 0);
3496 if (intr_handle->intr_vec == NULL) {
3497 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3498 " intr_vec\n", dev->data->nb_rx_queues);
3503 ixgbevf_configure_msix(dev);
3505 if (dev->data->dev_conf.intr_conf.lsc != 0) {
3506 if (rte_intr_allow_others(intr_handle))
3507 rte_intr_callback_register(intr_handle,
3508 ixgbevf_dev_interrupt_handler,
3511 PMD_INIT_LOG(INFO, "lsc won't enable because of"
3512 " no intr multiplex\n");
3515 rte_intr_enable(intr_handle);
3517 /* Re-enable interrupt for VF */
3518 ixgbevf_intr_enable(hw);
3524 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3526 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3527 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3529 PMD_INIT_FUNC_TRACE();
3531 hw->adapter_stopped = 1;
3532 ixgbe_stop_adapter(hw);
3535 * Clear what we set, but we still keep shadow_vfta to
3536 * restore after device starts
3538 ixgbevf_set_vfta_all(dev,0);
3540 /* Clear stored conf */
3541 dev->data->scattered_rx = 0;
3543 ixgbe_dev_clear_queues(dev);
3545 /* disable intr eventfd mapping */
3546 rte_intr_disable(intr_handle);
3549 /* Clean datapath event and queue/vec mapping */
3550 rte_intr_efd_disable(intr_handle);
3551 if (intr_handle->intr_vec != NULL) {
3552 rte_free(intr_handle->intr_vec);
3553 intr_handle->intr_vec = NULL;
3559 ixgbevf_dev_close(struct rte_eth_dev *dev)
3561 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3563 struct rte_pci_device *pci_dev;
3566 PMD_INIT_FUNC_TRACE();
3570 ixgbevf_dev_stop(dev);
3572 ixgbe_dev_free_queues(dev);
3574 /* reprogram the RAR[0] in case user changed it. */
3575 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3578 pci_dev = dev->pci_dev;
3579 if (pci_dev->intr_handle.intr_vec) {
3580 rte_free(pci_dev->intr_handle.intr_vec);
3581 pci_dev->intr_handle.intr_vec = NULL;
3586 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3588 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3589 struct ixgbe_vfta * shadow_vfta =
3590 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3591 int i = 0, j = 0, vfta = 0, mask = 1;
3593 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3594 vfta = shadow_vfta->vfta[i];
3597 for (j = 0; j < 32; j++){
3599 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3608 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3610 struct ixgbe_hw *hw =
3611 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3612 struct ixgbe_vfta * shadow_vfta =
3613 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3614 uint32_t vid_idx = 0;
3615 uint32_t vid_bit = 0;
3618 PMD_INIT_FUNC_TRACE();
3620 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3621 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3623 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3626 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3627 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3629 /* Save what we set and retore it after device reset */
3631 shadow_vfta->vfta[vid_idx] |= vid_bit;
3633 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3639 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3641 struct ixgbe_hw *hw =
3642 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3645 PMD_INIT_FUNC_TRACE();
3647 if(queue >= hw->mac.max_rx_queues)
3650 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3652 ctrl |= IXGBE_RXDCTL_VME;
3654 ctrl &= ~IXGBE_RXDCTL_VME;
3655 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3657 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3661 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3663 struct ixgbe_hw *hw =
3664 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3668 /* VF function only support hw strip feature, others are not support */
3669 if(mask & ETH_VLAN_STRIP_MASK){
3670 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3672 for(i=0; i < hw->mac.max_rx_queues; i++)
3673 ixgbevf_vlan_strip_queue_set(dev,i,on);
3678 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3682 /* we only need to do this if VMDq is enabled */
3683 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3684 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3685 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3693 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3695 uint32_t vector = 0;
3696 switch (hw->mac.mc_filter_type) {
3697 case 0: /* use bits [47:36] of the address */
3698 vector = ((uc_addr->addr_bytes[4] >> 4) |
3699 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3701 case 1: /* use bits [46:35] of the address */
3702 vector = ((uc_addr->addr_bytes[4] >> 3) |
3703 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3705 case 2: /* use bits [45:34] of the address */
3706 vector = ((uc_addr->addr_bytes[4] >> 2) |
3707 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3709 case 3: /* use bits [43:32] of the address */
3710 vector = ((uc_addr->addr_bytes[4]) |
3711 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3713 default: /* Invalid mc_filter_type */
3717 /* vector can only be 12-bits or boundary will be exceeded */
3723 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3731 const uint32_t ixgbe_uta_idx_mask = 0x7F;
3732 const uint32_t ixgbe_uta_bit_shift = 5;
3733 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3734 const uint32_t bit1 = 0x1;
3736 struct ixgbe_hw *hw =
3737 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3738 struct ixgbe_uta_info *uta_info =
3739 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3741 /* The UTA table only exists on 82599 hardware and newer */
3742 if (hw->mac.type < ixgbe_mac_82599EB)
3745 vector = ixgbe_uta_vector(hw,mac_addr);
3746 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3747 uta_shift = vector & ixgbe_uta_bit_mask;
3749 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3753 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3755 uta_info->uta_in_use++;
3756 reg_val |= (bit1 << uta_shift);
3757 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3759 uta_info->uta_in_use--;
3760 reg_val &= ~(bit1 << uta_shift);
3761 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3764 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3766 if (uta_info->uta_in_use > 0)
3767 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3768 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3770 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3776 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3779 struct ixgbe_hw *hw =
3780 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3781 struct ixgbe_uta_info *uta_info =
3782 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3784 /* The UTA table only exists on 82599 hardware and newer */
3785 if (hw->mac.type < ixgbe_mac_82599EB)
3789 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3790 uta_info->uta_shadow[i] = ~0;
3791 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3794 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3795 uta_info->uta_shadow[i] = 0;
3796 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3804 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3806 uint32_t new_val = orig_val;
3808 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3809 new_val |= IXGBE_VMOLR_AUPE;
3810 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3811 new_val |= IXGBE_VMOLR_ROMPE;
3812 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3813 new_val |= IXGBE_VMOLR_ROPE;
3814 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3815 new_val |= IXGBE_VMOLR_BAM;
3816 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3817 new_val |= IXGBE_VMOLR_MPE;
3823 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3824 uint16_t rx_mask, uint8_t on)
3828 struct ixgbe_hw *hw =
3829 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3830 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3832 if (hw->mac.type == ixgbe_mac_82598EB) {
3833 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3834 " on 82599 hardware and newer");
3837 if (ixgbe_vmdq_mode_check(hw) < 0)
3840 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3847 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3853 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3857 const uint8_t bit1 = 0x1;
3859 struct ixgbe_hw *hw =
3860 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3862 if (ixgbe_vmdq_mode_check(hw) < 0)
3865 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3866 reg = IXGBE_READ_REG(hw, addr);
3874 IXGBE_WRITE_REG(hw, addr,reg);
3880 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3884 const uint8_t bit1 = 0x1;
3886 struct ixgbe_hw *hw =
3887 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3889 if (ixgbe_vmdq_mode_check(hw) < 0)
3892 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3893 reg = IXGBE_READ_REG(hw, addr);
3901 IXGBE_WRITE_REG(hw, addr,reg);
3907 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3908 uint64_t pool_mask, uint8_t vlan_on)
3912 struct ixgbe_hw *hw =
3913 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3915 if (ixgbe_vmdq_mode_check(hw) < 0)
3917 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3918 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3919 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3927 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
3928 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
3929 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
3930 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
3931 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
3932 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
3933 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
3936 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3937 struct rte_eth_mirror_conf *mirror_conf,
3938 uint8_t rule_id, uint8_t on)
3940 uint32_t mr_ctl,vlvf;
3941 uint32_t mp_lsb = 0;
3942 uint32_t mv_msb = 0;
3943 uint32_t mv_lsb = 0;
3944 uint32_t mp_msb = 0;
3947 uint64_t vlan_mask = 0;
3949 const uint8_t pool_mask_offset = 32;
3950 const uint8_t vlan_mask_offset = 32;
3951 const uint8_t dst_pool_offset = 8;
3952 const uint8_t rule_mr_offset = 4;
3953 const uint8_t mirror_rule_mask= 0x0F;
3955 struct ixgbe_mirror_info *mr_info =
3956 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3957 struct ixgbe_hw *hw =
3958 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3959 uint8_t mirror_type = 0;
3961 if (ixgbe_vmdq_mode_check(hw) < 0)
3964 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
3967 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
3968 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
3969 mirror_conf->rule_type);
3973 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
3974 mirror_type |= IXGBE_MRCTL_VLME;
3975 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3976 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3977 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3978 /* search vlan id related pool vlan filter index */
3979 reg_index = ixgbe_find_vlvf_slot(hw,
3980 mirror_conf->vlan.vlan_id[i]);
3983 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3984 if ((vlvf & IXGBE_VLVF_VIEN) &&
3985 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
3986 mirror_conf->vlan.vlan_id[i]))
3987 vlan_mask |= (1ULL << reg_index);
3994 mv_lsb = vlan_mask & 0xFFFFFFFF;
3995 mv_msb = vlan_mask >> vlan_mask_offset;
3997 mr_info->mr_conf[rule_id].vlan.vlan_mask =
3998 mirror_conf->vlan.vlan_mask;
3999 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4000 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
4001 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4002 mirror_conf->vlan.vlan_id[i];
4007 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4008 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4009 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4014 * if enable pool mirror, write related pool mask register,if disable
4015 * pool mirror, clear PFMRVM register
4017 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4018 mirror_type |= IXGBE_MRCTL_VPME;
4020 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4021 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4022 mr_info->mr_conf[rule_id].pool_mask =
4023 mirror_conf->pool_mask;
4028 mr_info->mr_conf[rule_id].pool_mask = 0;
4031 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4032 mirror_type |= IXGBE_MRCTL_UPME;
4033 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4034 mirror_type |= IXGBE_MRCTL_DPME;
4036 /* read mirror control register and recalculate it */
4037 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4040 mr_ctl |= mirror_type;
4041 mr_ctl &= mirror_rule_mask;
4042 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4044 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4046 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4047 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4049 /* write mirrror control register */
4050 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4052 /* write pool mirrror control register */
4053 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4054 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4055 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4058 /* write VLAN mirrror control register */
4059 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4060 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4061 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4069 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4072 uint32_t lsb_val = 0;
4073 uint32_t msb_val = 0;
4074 const uint8_t rule_mr_offset = 4;
4076 struct ixgbe_hw *hw =
4077 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4078 struct ixgbe_mirror_info *mr_info =
4079 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4081 if (ixgbe_vmdq_mode_check(hw) < 0)
4084 memset(&mr_info->mr_conf[rule_id], 0,
4085 sizeof(struct rte_eth_mirror_conf));
4087 /* clear PFVMCTL register */
4088 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4090 /* clear pool mask register */
4091 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4092 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4094 /* clear vlan mask register */
4095 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4096 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4103 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4106 struct ixgbe_hw *hw =
4107 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4109 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4110 mask |= (1 << queue_id);
4111 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4113 rte_intr_enable(&dev->pci_dev->intr_handle);
4119 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4122 struct ixgbe_hw *hw =
4123 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4125 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4126 mask &= ~(1 << queue_id);
4127 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4133 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4136 struct ixgbe_hw *hw =
4137 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4138 struct ixgbe_interrupt *intr =
4139 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4141 if (queue_id < 16) {
4142 ixgbe_disable_intr(hw);
4143 intr->mask |= (1 << queue_id);
4144 ixgbe_enable_intr(dev);
4145 } else if (queue_id < 32) {
4146 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4147 mask &= (1 << queue_id);
4148 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4149 } else if (queue_id < 64) {
4150 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4151 mask &= (1 << (queue_id - 32));
4152 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4154 rte_intr_enable(&dev->pci_dev->intr_handle);
4160 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4163 struct ixgbe_hw *hw =
4164 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4165 struct ixgbe_interrupt *intr =
4166 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4168 if (queue_id < 16) {
4169 ixgbe_disable_intr(hw);
4170 intr->mask &= ~(1 << queue_id);
4171 ixgbe_enable_intr(dev);
4172 } else if (queue_id < 32) {
4173 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4174 mask &= ~(1 << queue_id);
4175 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4176 } else if (queue_id < 64) {
4177 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4178 mask &= ~(1 << (queue_id - 32));
4179 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4186 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4187 uint8_t queue, uint8_t msix_vector)
4191 if (direction == -1) {
4193 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4194 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4197 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4199 /* rx or tx cause */
4200 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4201 idx = ((16 * (queue & 1)) + (8 * direction));
4202 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4203 tmp &= ~(0xFF << idx);
4204 tmp |= (msix_vector << idx);
4205 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4210 * set the IVAR registers, mapping interrupt causes to vectors
4212 * pointer to ixgbe_hw struct
4214 * 0 for Rx, 1 for Tx, -1 for other causes
4216 * queue to map the corresponding interrupt to
4218 * the vector to map to the corresponding queue
4221 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4222 uint8_t queue, uint8_t msix_vector)
4226 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4227 if (hw->mac.type == ixgbe_mac_82598EB) {
4228 if (direction == -1)
4230 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4231 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4232 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4233 tmp |= (msix_vector << (8 * (queue & 0x3)));
4234 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4235 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4236 (hw->mac.type == ixgbe_mac_X540)) {
4237 if (direction == -1) {
4239 idx = ((queue & 1) * 8);
4240 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4241 tmp &= ~(0xFF << idx);
4242 tmp |= (msix_vector << idx);
4243 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4245 /* rx or tx causes */
4246 idx = ((16 * (queue & 1)) + (8 * direction));
4247 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4248 tmp &= ~(0xFF << idx);
4249 tmp |= (msix_vector << idx);
4250 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4257 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4259 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4261 struct ixgbe_hw *hw =
4262 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4264 uint32_t vector_idx = 0;
4267 /* won't configure msix register if no mapping is done
4268 * between intr vector and event fd.
4270 if (!rte_intr_dp_is_en(intr_handle))
4274 /* Configure all RX queues of VF */
4275 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4276 /* Force all queue use vector 0,
4277 * as IXGBE_VF_MAXMSIVECOTR = 1
4279 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4280 intr_handle->intr_vec[q_idx] = vector_idx;
4283 /* Configure VF Rx queue ivar */
4284 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4289 * Sets up the hardware to properly generate MSI-X interrupts
4291 * board private structure
4294 ixgbe_configure_msix(struct rte_eth_dev *dev)
4296 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4298 struct ixgbe_hw *hw =
4299 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4300 uint32_t queue_id, vec = 0;
4305 /* won't configure msix register if no mapping is done
4306 * between intr vector and event fd
4308 if (!rte_intr_dp_is_en(intr_handle))
4312 /* setup GPIE for MSI-x mode */
4313 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4314 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4315 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4316 /* auto clearing and auto setting corresponding bits in EIMS
4317 * when MSI-X interrupt is triggered
4319 if (hw->mac.type == ixgbe_mac_82598EB) {
4320 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4322 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4323 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4325 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4327 /* Populate the IVAR table and set the ITR values to the
4328 * corresponding register.
4330 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4332 /* by default, 1:1 mapping */
4333 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4334 intr_handle->intr_vec[queue_id] = vec;
4335 if (vec < intr_handle->nb_efd - 1)
4339 switch (hw->mac.type) {
4340 case ixgbe_mac_82598EB:
4341 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4342 intr_handle->max_intr - 1);
4344 case ixgbe_mac_82599EB:
4345 case ixgbe_mac_X540:
4346 ixgbe_set_ivar_map(hw, -1, 1, intr_handle->max_intr - 1);
4351 IXGBE_WRITE_REG(hw, IXGBE_EITR(queue_id),
4352 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4354 /* set up to autoclear timer, and the vectors */
4355 mask = IXGBE_EIMS_ENABLE_MASK;
4356 mask &= ~(IXGBE_EIMS_OTHER |
4357 IXGBE_EIMS_MAILBOX |
4360 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4364 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4365 uint16_t queue_idx, uint16_t tx_rate)
4367 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4368 uint32_t rf_dec, rf_int;
4370 uint16_t link_speed = dev->data->dev_link.link_speed;
4372 if (queue_idx >= hw->mac.max_tx_queues)
4376 /* Calculate the rate factor values to set */
4377 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4378 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4379 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4381 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4382 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4383 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4384 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4390 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4391 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4394 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4395 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4396 IXGBE_MAX_JUMBO_FRAME_SIZE))
4397 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4398 IXGBE_MMW_SIZE_JUMBO_FRAME);
4400 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4401 IXGBE_MMW_SIZE_DEFAULT);
4403 /* Set RTTBCNRC of queue X */
4404 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4405 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4406 IXGBE_WRITE_FLUSH(hw);
4411 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4412 uint16_t tx_rate, uint64_t q_msk)
4414 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4415 struct ixgbe_vf_info *vfinfo =
4416 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4417 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4418 uint32_t queue_stride =
4419 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4420 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4421 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4422 uint16_t total_rate = 0;
4424 if (queue_end >= hw->mac.max_tx_queues)
4427 if (vfinfo != NULL) {
4428 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4431 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4433 total_rate += vfinfo[vf_idx].tx_rate[idx];
4438 /* Store tx_rate for this vf. */
4439 for (idx = 0; idx < nb_q_per_pool; idx++) {
4440 if (((uint64_t)0x1 << idx) & q_msk) {
4441 if (vfinfo[vf].tx_rate[idx] != tx_rate)
4442 vfinfo[vf].tx_rate[idx] = tx_rate;
4443 total_rate += tx_rate;
4447 if (total_rate > dev->data->dev_link.link_speed) {
4449 * Reset stored TX rate of the VF if it causes exceed
4452 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4456 /* Set RTTBCNRC of each queue/pool for vf X */
4457 for (; queue_idx <= queue_end; queue_idx++) {
4459 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4467 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4468 __attribute__((unused)) uint32_t index,
4469 __attribute__((unused)) uint32_t pool)
4471 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4475 * On a 82599 VF, adding again the same MAC addr is not an idempotent
4476 * operation. Trap this case to avoid exhausting the [very limited]
4477 * set of PF resources used to store VF MAC addresses.
4479 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4481 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4484 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4488 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4490 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4491 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4492 struct ether_addr *mac_addr;
4497 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4498 * not support the deletion of a given MAC address.
4499 * Instead, it imposes to delete all MAC addresses, then to add again
4500 * all MAC addresses with the exception of the one to be deleted.
4502 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4505 * Add again all MAC addresses, with the exception of the deleted one
4506 * and of the permanent MAC address.
4508 for (i = 0, mac_addr = dev->data->mac_addrs;
4509 i < hw->mac.num_rar_entries; i++, mac_addr++) {
4510 /* Skip the deleted MAC address */
4513 /* Skip NULL MAC addresses */
4514 if (is_zero_ether_addr(mac_addr))
4516 /* Skip the permanent MAC address */
4517 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4519 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4522 "Adding again MAC address "
4523 "%02x:%02x:%02x:%02x:%02x:%02x failed "
4525 mac_addr->addr_bytes[0],
4526 mac_addr->addr_bytes[1],
4527 mac_addr->addr_bytes[2],
4528 mac_addr->addr_bytes[3],
4529 mac_addr->addr_bytes[4],
4530 mac_addr->addr_bytes[5],
4536 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4538 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4540 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4543 #define MAC_TYPE_FILTER_SUP(type) do {\
4544 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4545 (type) != ixgbe_mac_X550)\
4550 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4551 struct rte_eth_syn_filter *filter,
4554 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4557 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4560 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4563 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4565 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4566 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4568 if (filter->hig_pri)
4569 synqf |= IXGBE_SYN_FILTER_SYNQFP;
4571 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4573 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4575 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4577 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4578 IXGBE_WRITE_FLUSH(hw);
4583 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4584 struct rte_eth_syn_filter *filter)
4586 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4587 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4589 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4590 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4591 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4598 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4599 enum rte_filter_op filter_op,
4602 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4605 MAC_TYPE_FILTER_SUP(hw->mac.type);
4607 if (filter_op == RTE_ETH_FILTER_NOP)
4611 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4616 switch (filter_op) {
4617 case RTE_ETH_FILTER_ADD:
4618 ret = ixgbe_syn_filter_set(dev,
4619 (struct rte_eth_syn_filter *)arg,
4622 case RTE_ETH_FILTER_DELETE:
4623 ret = ixgbe_syn_filter_set(dev,
4624 (struct rte_eth_syn_filter *)arg,
4627 case RTE_ETH_FILTER_GET:
4628 ret = ixgbe_syn_filter_get(dev,
4629 (struct rte_eth_syn_filter *)arg);
4632 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
4641 static inline enum ixgbe_5tuple_protocol
4642 convert_protocol_type(uint8_t protocol_value)
4644 if (protocol_value == IPPROTO_TCP)
4645 return IXGBE_FILTER_PROTOCOL_TCP;
4646 else if (protocol_value == IPPROTO_UDP)
4647 return IXGBE_FILTER_PROTOCOL_UDP;
4648 else if (protocol_value == IPPROTO_SCTP)
4649 return IXGBE_FILTER_PROTOCOL_SCTP;
4651 return IXGBE_FILTER_PROTOCOL_NONE;
4655 * add a 5tuple filter
4658 * dev: Pointer to struct rte_eth_dev.
4659 * index: the index the filter allocates.
4660 * filter: ponter to the filter that will be added.
4661 * rx_queue: the queue id the filter assigned to.
4664 * - On success, zero.
4665 * - On failure, a negative value.
4668 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
4669 struct ixgbe_5tuple_filter *filter)
4671 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4672 struct ixgbe_filter_info *filter_info =
4673 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4675 uint32_t ftqf, sdpqf;
4676 uint32_t l34timir = 0;
4677 uint8_t mask = 0xff;
4680 * look for an unused 5tuple filter index,
4681 * and insert the filter to list.
4683 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
4684 idx = i / (sizeof(uint32_t) * NBBY);
4685 shift = i % (sizeof(uint32_t) * NBBY);
4686 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
4687 filter_info->fivetuple_mask[idx] |= 1 << shift;
4689 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4695 if (i >= IXGBE_MAX_FTQF_FILTERS) {
4696 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4700 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
4701 IXGBE_SDPQF_DSTPORT_SHIFT);
4702 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
4704 ftqf = (uint32_t)(filter->filter_info.proto &
4705 IXGBE_FTQF_PROTOCOL_MASK);
4706 ftqf |= (uint32_t)((filter->filter_info.priority &
4707 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
4708 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
4709 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
4710 if (filter->filter_info.dst_ip_mask == 0)
4711 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
4712 if (filter->filter_info.src_port_mask == 0)
4713 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
4714 if (filter->filter_info.dst_port_mask == 0)
4715 mask &= IXGBE_FTQF_DEST_PORT_MASK;
4716 if (filter->filter_info.proto_mask == 0)
4717 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
4718 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
4719 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
4720 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
4722 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
4723 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
4724 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
4725 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
4727 l34timir |= IXGBE_L34T_IMIR_RESERVE;
4728 l34timir |= (uint32_t)(filter->queue <<
4729 IXGBE_L34T_IMIR_QUEUE_SHIFT);
4730 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
4735 * remove a 5tuple filter
4738 * dev: Pointer to struct rte_eth_dev.
4739 * filter: the pointer of the filter will be removed.
4742 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
4743 struct ixgbe_5tuple_filter *filter)
4745 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4746 struct ixgbe_filter_info *filter_info =
4747 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4748 uint16_t index = filter->index;
4750 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
4751 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
4752 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4755 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
4756 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
4757 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
4758 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
4759 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
4763 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
4765 struct ixgbe_hw *hw;
4766 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4768 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4770 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
4773 /* refuse mtu that requires the support of scattered packets when this
4774 * feature has not been enabled before. */
4775 if (!dev->data->scattered_rx &&
4776 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
4777 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4781 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
4782 * request of the version 2.0 of the mailbox API.
4783 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
4784 * of the mailbox API.
4785 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
4786 * prior to 3.11.33 which contains the following change:
4787 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4789 ixgbevf_rlpml_set_vf(hw, max_frame);
4791 /* update max frame size */
4792 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4796 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
4797 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
4801 static inline struct ixgbe_5tuple_filter *
4802 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
4803 struct ixgbe_5tuple_filter_info *key)
4805 struct ixgbe_5tuple_filter *it;
4807 TAILQ_FOREACH(it, filter_list, entries) {
4808 if (memcmp(key, &it->filter_info,
4809 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
4816 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
4818 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
4819 struct ixgbe_5tuple_filter_info *filter_info)
4821 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
4822 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
4823 filter->priority < IXGBE_5TUPLE_MIN_PRI)
4826 switch (filter->dst_ip_mask) {
4828 filter_info->dst_ip_mask = 0;
4829 filter_info->dst_ip = filter->dst_ip;
4832 filter_info->dst_ip_mask = 1;
4835 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4839 switch (filter->src_ip_mask) {
4841 filter_info->src_ip_mask = 0;
4842 filter_info->src_ip = filter->src_ip;
4845 filter_info->src_ip_mask = 1;
4848 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4852 switch (filter->dst_port_mask) {
4854 filter_info->dst_port_mask = 0;
4855 filter_info->dst_port = filter->dst_port;
4858 filter_info->dst_port_mask = 1;
4861 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4865 switch (filter->src_port_mask) {
4867 filter_info->src_port_mask = 0;
4868 filter_info->src_port = filter->src_port;
4871 filter_info->src_port_mask = 1;
4874 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4878 switch (filter->proto_mask) {
4880 filter_info->proto_mask = 0;
4881 filter_info->proto =
4882 convert_protocol_type(filter->proto);
4885 filter_info->proto_mask = 1;
4888 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4892 filter_info->priority = (uint8_t)filter->priority;
4897 * add or delete a ntuple filter
4900 * dev: Pointer to struct rte_eth_dev.
4901 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4902 * add: if true, add filter, if false, remove filter
4905 * - On success, zero.
4906 * - On failure, a negative value.
4909 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4910 struct rte_eth_ntuple_filter *ntuple_filter,
4913 struct ixgbe_filter_info *filter_info =
4914 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4915 struct ixgbe_5tuple_filter_info filter_5tuple;
4916 struct ixgbe_5tuple_filter *filter;
4919 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4920 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4924 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4925 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4929 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4931 if (filter != NULL && add) {
4932 PMD_DRV_LOG(ERR, "filter exists.");
4935 if (filter == NULL && !add) {
4936 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4941 filter = rte_zmalloc("ixgbe_5tuple_filter",
4942 sizeof(struct ixgbe_5tuple_filter), 0);
4945 (void)rte_memcpy(&filter->filter_info,
4947 sizeof(struct ixgbe_5tuple_filter_info));
4948 filter->queue = ntuple_filter->queue;
4949 ret = ixgbe_add_5tuple_filter(dev, filter);
4955 ixgbe_remove_5tuple_filter(dev, filter);
4961 * get a ntuple filter
4964 * dev: Pointer to struct rte_eth_dev.
4965 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4968 * - On success, zero.
4969 * - On failure, a negative value.
4972 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
4973 struct rte_eth_ntuple_filter *ntuple_filter)
4975 struct ixgbe_filter_info *filter_info =
4976 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4977 struct ixgbe_5tuple_filter_info filter_5tuple;
4978 struct ixgbe_5tuple_filter *filter;
4981 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4982 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4986 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4987 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4991 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4993 if (filter == NULL) {
4994 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4997 ntuple_filter->queue = filter->queue;
5002 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5003 * @dev: pointer to rte_eth_dev structure
5004 * @filter_op:operation will be taken.
5005 * @arg: a pointer to specific structure corresponding to the filter_op
5008 * - On success, zero.
5009 * - On failure, a negative value.
5012 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5013 enum rte_filter_op filter_op,
5016 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5019 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5021 if (filter_op == RTE_ETH_FILTER_NOP)
5025 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5030 switch (filter_op) {
5031 case RTE_ETH_FILTER_ADD:
5032 ret = ixgbe_add_del_ntuple_filter(dev,
5033 (struct rte_eth_ntuple_filter *)arg,
5036 case RTE_ETH_FILTER_DELETE:
5037 ret = ixgbe_add_del_ntuple_filter(dev,
5038 (struct rte_eth_ntuple_filter *)arg,
5041 case RTE_ETH_FILTER_GET:
5042 ret = ixgbe_get_ntuple_filter(dev,
5043 (struct rte_eth_ntuple_filter *)arg);
5046 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5054 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5059 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5060 if (filter_info->ethertype_filters[i] == ethertype &&
5061 (filter_info->ethertype_mask & (1 << i)))
5068 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5073 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5074 if (!(filter_info->ethertype_mask & (1 << i))) {
5075 filter_info->ethertype_mask |= 1 << i;
5076 filter_info->ethertype_filters[i] = ethertype;
5084 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5087 if (idx >= IXGBE_MAX_ETQF_FILTERS)
5089 filter_info->ethertype_mask &= ~(1 << idx);
5090 filter_info->ethertype_filters[idx] = 0;
5095 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5096 struct rte_eth_ethertype_filter *filter,
5099 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5100 struct ixgbe_filter_info *filter_info =
5101 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5106 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5109 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5110 filter->ether_type == ETHER_TYPE_IPv6) {
5111 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5112 " ethertype filter.", filter->ether_type);
5116 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5117 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5120 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5121 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5125 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5126 if (ret >= 0 && add) {
5127 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5128 filter->ether_type);
5131 if (ret < 0 && !add) {
5132 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5133 filter->ether_type);
5138 ret = ixgbe_ethertype_filter_insert(filter_info,
5139 filter->ether_type);
5141 PMD_DRV_LOG(ERR, "ethertype filters are full.");
5144 etqf = IXGBE_ETQF_FILTER_EN;
5145 etqf |= (uint32_t)filter->ether_type;
5146 etqs |= (uint32_t)((filter->queue <<
5147 IXGBE_ETQS_RX_QUEUE_SHIFT) &
5148 IXGBE_ETQS_RX_QUEUE);
5149 etqs |= IXGBE_ETQS_QUEUE_EN;
5151 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5155 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5156 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5157 IXGBE_WRITE_FLUSH(hw);
5163 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5164 struct rte_eth_ethertype_filter *filter)
5166 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5167 struct ixgbe_filter_info *filter_info =
5168 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5169 uint32_t etqf, etqs;
5172 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5174 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5175 filter->ether_type);
5179 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5180 if (etqf & IXGBE_ETQF_FILTER_EN) {
5181 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5182 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5184 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5185 IXGBE_ETQS_RX_QUEUE_SHIFT;
5192 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5193 * @dev: pointer to rte_eth_dev structure
5194 * @filter_op:operation will be taken.
5195 * @arg: a pointer to specific structure corresponding to the filter_op
5198 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5199 enum rte_filter_op filter_op,
5202 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5205 MAC_TYPE_FILTER_SUP(hw->mac.type);
5207 if (filter_op == RTE_ETH_FILTER_NOP)
5211 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5216 switch (filter_op) {
5217 case RTE_ETH_FILTER_ADD:
5218 ret = ixgbe_add_del_ethertype_filter(dev,
5219 (struct rte_eth_ethertype_filter *)arg,
5222 case RTE_ETH_FILTER_DELETE:
5223 ret = ixgbe_add_del_ethertype_filter(dev,
5224 (struct rte_eth_ethertype_filter *)arg,
5227 case RTE_ETH_FILTER_GET:
5228 ret = ixgbe_get_ethertype_filter(dev,
5229 (struct rte_eth_ethertype_filter *)arg);
5232 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5240 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5241 enum rte_filter_type filter_type,
5242 enum rte_filter_op filter_op,
5247 switch (filter_type) {
5248 case RTE_ETH_FILTER_NTUPLE:
5249 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5251 case RTE_ETH_FILTER_ETHERTYPE:
5252 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5254 case RTE_ETH_FILTER_SYN:
5255 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5257 case RTE_ETH_FILTER_FDIR:
5258 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5261 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5270 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5271 u8 **mc_addr_ptr, u32 *vmdq)
5276 mc_addr = *mc_addr_ptr;
5277 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5282 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5283 struct ether_addr *mc_addr_set,
5284 uint32_t nb_mc_addr)
5286 struct ixgbe_hw *hw;
5289 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5290 mc_addr_list = (u8 *)mc_addr_set;
5291 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5292 ixgbe_dev_addr_list_itr, TRUE);
5296 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5298 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5302 /* Enable system time for platforms where it isn't on by default. */
5303 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5304 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5305 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5307 /* Start incrementing the register used to timestamp PTP packets. */
5308 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
5310 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5311 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5313 IXGBE_ETQF_FILTER_EN |
5316 /* Enable timestamping of received PTP packets. */
5317 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5318 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5319 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5321 /* Enable timestamping of transmitted PTP packets. */
5322 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5323 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5324 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5330 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5332 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5335 /* Disable timestamping of transmitted PTP packets. */
5336 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5337 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5338 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5340 /* Disable timestamping of received PTP packets. */
5341 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5342 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5343 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5345 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5346 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5348 /* Stop incrementating the System Time registers. */
5349 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5355 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5356 struct timespec *timestamp,
5357 uint32_t flags __rte_unused)
5359 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5360 uint32_t tsync_rxctl;
5364 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5365 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5368 rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5369 rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
5371 timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
5372 timestamp->tv_nsec = 0;
5378 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5379 struct timespec *timestamp)
5381 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5382 uint32_t tsync_txctl;
5386 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5387 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5390 tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5391 tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
5393 timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
5394 timestamp->tv_nsec = 0;
5400 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5402 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5405 const struct reg_info *reg_group;
5406 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5407 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5409 while ((reg_group = reg_set[g_ind++]))
5410 count += ixgbe_regs_group_count(reg_group);
5416 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5420 const struct reg_info *reg_group;
5422 while ((reg_group = ixgbevf_regs[g_ind++]))
5423 count += ixgbe_regs_group_count(reg_group);
5429 ixgbe_get_regs(struct rte_eth_dev *dev,
5430 struct rte_dev_reg_info *regs)
5432 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5433 uint32_t *data = regs->data;
5436 const struct reg_info *reg_group;
5437 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5438 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5440 /* Support only full register dump */
5441 if ((regs->length == 0) ||
5442 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
5443 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5445 while ((reg_group = reg_set[g_ind++]))
5446 count += ixgbe_read_regs_group(dev, &data[count],
5455 ixgbevf_get_regs(struct rte_eth_dev *dev,
5456 struct rte_dev_reg_info *regs)
5458 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5459 uint32_t *data = regs->data;
5462 const struct reg_info *reg_group;
5464 /* Support only full register dump */
5465 if ((regs->length == 0) ||
5466 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
5467 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5469 while ((reg_group = ixgbevf_regs[g_ind++]))
5470 count += ixgbe_read_regs_group(dev, &data[count],
5479 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
5481 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5483 /* Return unit is byte count */
5484 return hw->eeprom.word_size * 2;
5488 ixgbe_get_eeprom(struct rte_eth_dev *dev,
5489 struct rte_dev_eeprom_info *in_eeprom)
5491 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5492 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5493 uint16_t *data = in_eeprom->data;
5496 first = in_eeprom->offset >> 1;
5497 length = in_eeprom->length >> 1;
5498 if ((first >= hw->eeprom.word_size) ||
5499 ((first + length) >= hw->eeprom.word_size))
5502 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5504 return eeprom->ops.read_buffer(hw, first, length, data);
5508 ixgbe_set_eeprom(struct rte_eth_dev *dev,
5509 struct rte_dev_eeprom_info *in_eeprom)
5511 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5512 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5513 uint16_t *data = in_eeprom->data;
5516 first = in_eeprom->offset >> 1;
5517 length = in_eeprom->length >> 1;
5518 if ((first >= hw->eeprom.word_size) ||
5519 ((first + length) >= hw->eeprom.word_size))
5522 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5524 return eeprom->ops.write_buffer(hw, first, length, data);
5527 static struct rte_driver rte_ixgbe_driver = {
5529 .init = rte_ixgbe_pmd_init,
5532 static struct rte_driver rte_ixgbevf_driver = {
5534 .init = rte_ixgbevf_pmd_init,
5537 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
5538 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);