1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
13 #include <netinet/in.h>
14 #include <rte_string_fns.h>
15 #include <rte_byteorder.h>
16 #include <rte_common.h>
17 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_branch_prediction.h>
25 #include <rte_memory.h>
26 #include <rte_kvargs.h>
28 #include <rte_alarm.h>
29 #include <rte_ether.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
32 #include <rte_malloc.h>
33 #include <rte_random.h>
35 #include <rte_hash_crc.h>
36 #ifdef RTE_LIBRTE_SECURITY
37 #include <rte_security_driver.h>
40 #include "ixgbe_logs.h"
41 #include "base/ixgbe_api.h"
42 #include "base/ixgbe_vf.h"
43 #include "base/ixgbe_common.h"
44 #include "ixgbe_ethdev.h"
45 #include "ixgbe_bypass.h"
46 #include "ixgbe_rxtx.h"
47 #include "base/ixgbe_type.h"
48 #include "base/ixgbe_phy.h"
49 #include "ixgbe_regs.h"
52 * High threshold controlling when to start sending XOFF frames. Must be at
53 * least 8 bytes less than receive packet buffer size. This value is in units
56 #define IXGBE_FC_HI 0x80
59 * Low threshold controlling when to start sending XON frames. This value is
60 * in units of 1024 bytes.
62 #define IXGBE_FC_LO 0x40
64 /* Timer value included in XOFF frames. */
65 #define IXGBE_FC_PAUSE 0x680
67 /*Default value of Max Rx Queue*/
68 #define IXGBE_MAX_RX_QUEUE_NUM 128
70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
71 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
72 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
74 #define IXGBE_MMW_SIZE_DEFAULT 0x4
75 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
76 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
79 * Default values for RX/TX configuration
81 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
82 #define IXGBE_DEFAULT_RX_PTHRESH 8
83 #define IXGBE_DEFAULT_RX_HTHRESH 8
84 #define IXGBE_DEFAULT_RX_WTHRESH 0
86 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
87 #define IXGBE_DEFAULT_TX_PTHRESH 32
88 #define IXGBE_DEFAULT_TX_HTHRESH 0
89 #define IXGBE_DEFAULT_TX_WTHRESH 0
90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
92 /* Bit shift and mask */
93 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
94 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
95 #define IXGBE_8_BIT_WIDTH CHAR_BIT
96 #define IXGBE_8_BIT_MASK UINT8_MAX
98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
102 /* Additional timesync values. */
103 #define NSEC_PER_SEC 1000000000L
104 #define IXGBE_INCVAL_10GB 0x66666666
105 #define IXGBE_INCVAL_1GB 0x40000000
106 #define IXGBE_INCVAL_100 0x50000000
107 #define IXGBE_INCVAL_SHIFT_10GB 28
108 #define IXGBE_INCVAL_SHIFT_1GB 24
109 #define IXGBE_INCVAL_SHIFT_100 21
110 #define IXGBE_INCVAL_SHIFT_82599 7
111 #define IXGBE_INCPER_SHIFT_82599 24
113 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
115 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
117 #define IXGBE_ETAG_ETYPE 0x00005084
118 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
119 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
120 #define IXGBE_RAH_ADTYPE 0x40000000
121 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
122 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
125 #define IXGBE_QDE_STRIP_TAG 0x00000004
126 #define IXGBE_VTEICR_MASK 0x07
128 #define IXGBE_EXVET_VET_EXT_SHIFT 16
129 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK "pflink_fullchk"
133 static const char * const ixgbevf_valid_arguments[] = {
134 IXGBEVF_DEVARG_PFLINK_FULLCHK,
138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
150 static void ixgbe_dev_close(struct rte_eth_dev *dev);
151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
157 int wait_to_complete);
158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
159 struct rte_eth_stats *stats);
160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
161 struct rte_eth_xstat *xstats, unsigned n);
162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
163 struct rte_eth_xstat *xstats, unsigned n);
165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
166 uint64_t *values, unsigned int n);
167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
170 struct rte_eth_xstat_name *xstats_names,
172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
173 struct rte_eth_xstat_name *xstats_names, unsigned limit);
174 static int ixgbe_dev_xstats_get_names_by_id(
175 struct rte_eth_dev *dev,
176 struct rte_eth_xstat_name *xstats_names,
179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
186 struct rte_eth_dev_info *dev_info);
187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
189 struct rte_eth_dev_info *dev_info);
190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
193 uint16_t vlan_id, int on);
194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
195 enum rte_vlan_type vlan_type,
197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
198 uint16_t queue, bool on);
199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
213 struct rte_eth_fc_conf *fc_conf);
214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
215 struct rte_eth_fc_conf *fc_conf);
216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
217 struct rte_eth_pfc_conf *pfc_conf);
218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
219 struct rte_eth_rss_reta_entry64 *reta_conf,
221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
222 struct rte_eth_rss_reta_entry64 *reta_conf,
224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
230 static void ixgbe_dev_interrupt_handler(void *param);
231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
232 static void ixgbe_dev_setup_link_alarm_handler(void *param);
234 static int ixgbe_add_rar(struct rte_eth_dev *dev,
235 struct rte_ether_addr *mac_addr,
236 uint32_t index, uint32_t pool);
237 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
238 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
239 struct rte_ether_addr *mac_addr);
240 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
241 static bool is_device_supported(struct rte_eth_dev *dev,
242 struct rte_pci_driver *drv);
244 /* For Virtual Function support */
245 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
246 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
247 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
248 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
249 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
250 int wait_to_complete);
251 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
252 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
253 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
254 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
255 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
256 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
257 struct rte_eth_stats *stats);
258 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
259 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
260 uint16_t vlan_id, int on);
261 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
262 uint16_t queue, int on);
263 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
264 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
265 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
266 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
268 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
270 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
271 uint8_t queue, uint8_t msix_vector);
272 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
273 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
274 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
275 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
276 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
278 /* For Eth VMDQ APIs support */
279 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
280 rte_ether_addr * mac_addr, uint8_t on);
281 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
282 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
283 struct rte_eth_mirror_conf *mirror_conf,
284 uint8_t rule_id, uint8_t on);
285 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
287 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
289 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
291 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
292 uint8_t queue, uint8_t msix_vector);
293 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
295 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
296 struct rte_ether_addr *mac_addr,
297 uint32_t index, uint32_t pool);
298 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
299 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
300 struct rte_ether_addr *mac_addr);
301 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
302 struct rte_eth_syn_filter *filter);
303 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
304 enum rte_filter_op filter_op,
306 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
307 struct ixgbe_5tuple_filter *filter);
308 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
309 struct ixgbe_5tuple_filter *filter);
310 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
311 enum rte_filter_op filter_op,
313 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
314 struct rte_eth_ntuple_filter *filter);
315 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
316 enum rte_filter_op filter_op,
318 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
319 struct rte_eth_ethertype_filter *filter);
320 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
321 enum rte_filter_type filter_type,
322 enum rte_filter_op filter_op,
324 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
326 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
327 struct rte_ether_addr *mc_addr_set,
328 uint32_t nb_mc_addr);
329 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
330 struct rte_eth_dcb_info *dcb_info);
332 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
333 static int ixgbe_get_regs(struct rte_eth_dev *dev,
334 struct rte_dev_reg_info *regs);
335 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
336 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
337 struct rte_dev_eeprom_info *eeprom);
338 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
339 struct rte_dev_eeprom_info *eeprom);
341 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
342 struct rte_eth_dev_module_info *modinfo);
343 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
344 struct rte_dev_eeprom_info *info);
346 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
347 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
348 struct rte_dev_reg_info *regs);
350 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
351 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
352 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
353 struct timespec *timestamp,
355 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
356 struct timespec *timestamp);
357 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
358 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
359 struct timespec *timestamp);
360 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
361 const struct timespec *timestamp);
362 static void ixgbevf_dev_interrupt_handler(void *param);
364 static int ixgbe_dev_l2_tunnel_eth_type_conf
365 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
366 static int ixgbe_dev_l2_tunnel_offload_set
367 (struct rte_eth_dev *dev,
368 struct rte_eth_l2_tunnel_conf *l2_tunnel,
371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
372 enum rte_filter_op filter_op,
375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
376 struct rte_eth_udp_tunnel *udp_tunnel);
377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
378 struct rte_eth_udp_tunnel *udp_tunnel);
379 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
380 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
383 * Define VF Stats MACRO for Non "cleared on read" register
385 #define UPDATE_VF_STAT(reg, last, cur) \
387 uint32_t latest = IXGBE_READ_REG(hw, reg); \
388 cur += (latest - last) & UINT_MAX; \
392 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
394 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
395 u64 new_msb = IXGBE_READ_REG(hw, msb); \
396 u64 latest = ((new_msb << 32) | new_lsb); \
397 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
401 #define IXGBE_SET_HWSTRIP(h, q) do {\
402 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
403 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
404 (h)->bitmap[idx] |= 1 << bit;\
407 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
408 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
409 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
410 (h)->bitmap[idx] &= ~(1 << bit);\
413 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
414 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
415 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
416 (r) = (h)->bitmap[idx] >> bit & 1;\
419 int ixgbe_logtype_init;
420 int ixgbe_logtype_driver;
423 * The set of PCI devices this driver supports
425 static const struct rte_pci_id pci_id_ixgbe_map[] = {
426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
474 #ifdef RTE_LIBRTE_IXGBE_BYPASS
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
477 { .vendor_id = 0, /* sentinel */ },
481 * The set of PCI devices this driver supports (for 82599 VF)
483 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
484 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
486 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
487 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
488 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
489 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
490 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
491 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
492 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
493 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
494 { .vendor_id = 0, /* sentinel */ },
497 static const struct rte_eth_desc_lim rx_desc_lim = {
498 .nb_max = IXGBE_MAX_RING_DESC,
499 .nb_min = IXGBE_MIN_RING_DESC,
500 .nb_align = IXGBE_RXD_ALIGN,
503 static const struct rte_eth_desc_lim tx_desc_lim = {
504 .nb_max = IXGBE_MAX_RING_DESC,
505 .nb_min = IXGBE_MIN_RING_DESC,
506 .nb_align = IXGBE_TXD_ALIGN,
507 .nb_seg_max = IXGBE_TX_MAX_SEG,
508 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
511 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
512 .dev_configure = ixgbe_dev_configure,
513 .dev_start = ixgbe_dev_start,
514 .dev_stop = ixgbe_dev_stop,
515 .dev_set_link_up = ixgbe_dev_set_link_up,
516 .dev_set_link_down = ixgbe_dev_set_link_down,
517 .dev_close = ixgbe_dev_close,
518 .dev_reset = ixgbe_dev_reset,
519 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
520 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
521 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
522 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
523 .link_update = ixgbe_dev_link_update,
524 .stats_get = ixgbe_dev_stats_get,
525 .xstats_get = ixgbe_dev_xstats_get,
526 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
527 .stats_reset = ixgbe_dev_stats_reset,
528 .xstats_reset = ixgbe_dev_xstats_reset,
529 .xstats_get_names = ixgbe_dev_xstats_get_names,
530 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
531 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
532 .fw_version_get = ixgbe_fw_version_get,
533 .dev_infos_get = ixgbe_dev_info_get,
534 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
535 .mtu_set = ixgbe_dev_mtu_set,
536 .vlan_filter_set = ixgbe_vlan_filter_set,
537 .vlan_tpid_set = ixgbe_vlan_tpid_set,
538 .vlan_offload_set = ixgbe_vlan_offload_set,
539 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
540 .rx_queue_start = ixgbe_dev_rx_queue_start,
541 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
542 .tx_queue_start = ixgbe_dev_tx_queue_start,
543 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
544 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
545 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
546 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
547 .rx_queue_release = ixgbe_dev_rx_queue_release,
548 .rx_queue_count = ixgbe_dev_rx_queue_count,
549 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
550 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
551 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
552 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
553 .tx_queue_release = ixgbe_dev_tx_queue_release,
554 .dev_led_on = ixgbe_dev_led_on,
555 .dev_led_off = ixgbe_dev_led_off,
556 .flow_ctrl_get = ixgbe_flow_ctrl_get,
557 .flow_ctrl_set = ixgbe_flow_ctrl_set,
558 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
559 .mac_addr_add = ixgbe_add_rar,
560 .mac_addr_remove = ixgbe_remove_rar,
561 .mac_addr_set = ixgbe_set_default_mac_addr,
562 .uc_hash_table_set = ixgbe_uc_hash_table_set,
563 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
564 .mirror_rule_set = ixgbe_mirror_rule_set,
565 .mirror_rule_reset = ixgbe_mirror_rule_reset,
566 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
567 .reta_update = ixgbe_dev_rss_reta_update,
568 .reta_query = ixgbe_dev_rss_reta_query,
569 .rss_hash_update = ixgbe_dev_rss_hash_update,
570 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
571 .filter_ctrl = ixgbe_dev_filter_ctrl,
572 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
573 .rxq_info_get = ixgbe_rxq_info_get,
574 .txq_info_get = ixgbe_txq_info_get,
575 .timesync_enable = ixgbe_timesync_enable,
576 .timesync_disable = ixgbe_timesync_disable,
577 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
578 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
579 .get_reg = ixgbe_get_regs,
580 .get_eeprom_length = ixgbe_get_eeprom_length,
581 .get_eeprom = ixgbe_get_eeprom,
582 .set_eeprom = ixgbe_set_eeprom,
583 .get_module_info = ixgbe_get_module_info,
584 .get_module_eeprom = ixgbe_get_module_eeprom,
585 .get_dcb_info = ixgbe_dev_get_dcb_info,
586 .timesync_adjust_time = ixgbe_timesync_adjust_time,
587 .timesync_read_time = ixgbe_timesync_read_time,
588 .timesync_write_time = ixgbe_timesync_write_time,
589 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
590 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
591 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
592 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
593 .tm_ops_get = ixgbe_tm_ops_get,
597 * dev_ops for virtual function, bare necessities for basic vf
598 * operation have been implemented
600 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
601 .dev_configure = ixgbevf_dev_configure,
602 .dev_start = ixgbevf_dev_start,
603 .dev_stop = ixgbevf_dev_stop,
604 .link_update = ixgbevf_dev_link_update,
605 .stats_get = ixgbevf_dev_stats_get,
606 .xstats_get = ixgbevf_dev_xstats_get,
607 .stats_reset = ixgbevf_dev_stats_reset,
608 .xstats_reset = ixgbevf_dev_stats_reset,
609 .xstats_get_names = ixgbevf_dev_xstats_get_names,
610 .dev_close = ixgbevf_dev_close,
611 .dev_reset = ixgbevf_dev_reset,
612 .promiscuous_enable = ixgbevf_dev_promiscuous_enable,
613 .promiscuous_disable = ixgbevf_dev_promiscuous_disable,
614 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
615 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
616 .dev_infos_get = ixgbevf_dev_info_get,
617 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
618 .mtu_set = ixgbevf_dev_set_mtu,
619 .vlan_filter_set = ixgbevf_vlan_filter_set,
620 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
621 .vlan_offload_set = ixgbevf_vlan_offload_set,
622 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
623 .rx_queue_release = ixgbe_dev_rx_queue_release,
624 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
625 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
626 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
627 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
628 .tx_queue_release = ixgbe_dev_tx_queue_release,
629 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
630 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
631 .mac_addr_add = ixgbevf_add_mac_addr,
632 .mac_addr_remove = ixgbevf_remove_mac_addr,
633 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
634 .rxq_info_get = ixgbe_rxq_info_get,
635 .txq_info_get = ixgbe_txq_info_get,
636 .mac_addr_set = ixgbevf_set_default_mac_addr,
637 .get_reg = ixgbevf_get_regs,
638 .reta_update = ixgbe_dev_rss_reta_update,
639 .reta_query = ixgbe_dev_rss_reta_query,
640 .rss_hash_update = ixgbe_dev_rss_hash_update,
641 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
644 /* store statistics names and its offset in stats structure */
645 struct rte_ixgbe_xstats_name_off {
646 char name[RTE_ETH_XSTATS_NAME_SIZE];
650 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
651 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
652 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
653 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
654 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
655 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
656 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
657 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
658 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
659 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
660 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
661 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
662 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
663 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
664 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
665 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
667 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
669 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
670 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
671 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
672 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
673 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
674 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
675 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
676 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
677 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
678 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
679 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
680 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
681 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
682 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
683 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
684 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
685 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
687 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
689 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
690 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
691 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
692 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
694 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
696 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
698 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
700 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
702 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
704 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
707 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
708 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
709 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
711 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
712 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
713 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
714 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
715 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
717 {"rx_fcoe_no_direct_data_placement_ext_buff",
718 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
720 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
722 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
724 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
726 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
728 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
731 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
732 sizeof(rte_ixgbe_stats_strings[0]))
734 /* MACsec statistics */
735 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
736 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
738 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
739 out_pkts_encrypted)},
740 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
741 out_pkts_protected)},
742 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
743 out_octets_encrypted)},
744 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
745 out_octets_protected)},
746 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
748 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
750 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
752 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
753 in_pkts_unknownsci)},
754 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
755 in_octets_decrypted)},
756 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
757 in_octets_validated)},
758 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
760 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
762 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
764 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
766 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
768 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
770 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
772 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
773 in_pkts_notusingsa)},
776 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
777 sizeof(rte_ixgbe_macsec_strings[0]))
779 /* Per-queue statistics */
780 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
781 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
782 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
783 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
784 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
787 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
788 sizeof(rte_ixgbe_rxq_strings[0]))
789 #define IXGBE_NB_RXQ_PRIO_VALUES 8
791 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
792 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
793 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
794 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
798 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
799 sizeof(rte_ixgbe_txq_strings[0]))
800 #define IXGBE_NB_TXQ_PRIO_VALUES 8
802 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
803 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
806 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
807 sizeof(rte_ixgbevf_stats_strings[0]))
810 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
813 ixgbe_is_sfp(struct ixgbe_hw *hw)
815 switch (hw->phy.type) {
816 case ixgbe_phy_sfp_avago:
817 case ixgbe_phy_sfp_ftl:
818 case ixgbe_phy_sfp_intel:
819 case ixgbe_phy_sfp_unknown:
820 case ixgbe_phy_sfp_passive_tyco:
821 case ixgbe_phy_sfp_passive_unknown:
828 static inline int32_t
829 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
834 status = ixgbe_reset_hw(hw);
836 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
837 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
838 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
839 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
840 IXGBE_WRITE_FLUSH(hw);
842 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
843 status = IXGBE_SUCCESS;
848 ixgbe_enable_intr(struct rte_eth_dev *dev)
850 struct ixgbe_interrupt *intr =
851 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
852 struct ixgbe_hw *hw =
853 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
855 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
856 IXGBE_WRITE_FLUSH(hw);
860 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
863 ixgbe_disable_intr(struct ixgbe_hw *hw)
865 PMD_INIT_FUNC_TRACE();
867 if (hw->mac.type == ixgbe_mac_82598EB) {
868 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
870 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
871 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
872 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
874 IXGBE_WRITE_FLUSH(hw);
878 * This function resets queue statistics mapping registers.
879 * From Niantic datasheet, Initialization of Statistics section:
880 * "...if software requires the queue counters, the RQSMR and TQSM registers
881 * must be re-programmed following a device reset.
884 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
888 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
889 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
890 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
896 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
901 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
902 #define NB_QMAP_FIELDS_PER_QSM_REG 4
903 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
905 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
906 struct ixgbe_stat_mapping_registers *stat_mappings =
907 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
908 uint32_t qsmr_mask = 0;
909 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
913 if ((hw->mac.type != ixgbe_mac_82599EB) &&
914 (hw->mac.type != ixgbe_mac_X540) &&
915 (hw->mac.type != ixgbe_mac_X550) &&
916 (hw->mac.type != ixgbe_mac_X550EM_x) &&
917 (hw->mac.type != ixgbe_mac_X550EM_a))
920 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
921 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
924 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
925 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
926 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
929 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
931 /* Now clear any previous stat_idx set */
932 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
934 stat_mappings->tqsm[n] &= ~clearing_mask;
936 stat_mappings->rqsmr[n] &= ~clearing_mask;
938 q_map = (uint32_t)stat_idx;
939 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
940 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
942 stat_mappings->tqsm[n] |= qsmr_mask;
944 stat_mappings->rqsmr[n] |= qsmr_mask;
946 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
947 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
949 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
950 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
952 /* Now write the mapping in the appropriate register */
954 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
955 stat_mappings->rqsmr[n], n);
956 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
958 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
959 stat_mappings->tqsm[n], n);
960 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
966 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
968 struct ixgbe_stat_mapping_registers *stat_mappings =
969 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
970 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
973 /* write whatever was in stat mapping table to the NIC */
974 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
976 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
979 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
984 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
987 struct ixgbe_dcb_tc_config *tc;
988 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
990 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
991 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
992 for (i = 0; i < dcb_max_tc; i++) {
993 tc = &dcb_config->tc_config[i];
994 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
995 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
996 (uint8_t)(100/dcb_max_tc + (i & 1));
997 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
998 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
999 (uint8_t)(100/dcb_max_tc + (i & 1));
1000 tc->pfc = ixgbe_dcb_pfc_disabled;
1003 /* Initialize default user to priority mapping, UPx->TC0 */
1004 tc = &dcb_config->tc_config[0];
1005 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1006 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1007 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1008 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1009 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1011 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1012 dcb_config->pfc_mode_enable = false;
1013 dcb_config->vt_mode = true;
1014 dcb_config->round_robin_enable = false;
1015 /* support all DCB capabilities in 82599 */
1016 dcb_config->support.capabilities = 0xFF;
1018 /*we only support 4 Tcs for X540, X550 */
1019 if (hw->mac.type == ixgbe_mac_X540 ||
1020 hw->mac.type == ixgbe_mac_X550 ||
1021 hw->mac.type == ixgbe_mac_X550EM_x ||
1022 hw->mac.type == ixgbe_mac_X550EM_a) {
1023 dcb_config->num_tcs.pg_tcs = 4;
1024 dcb_config->num_tcs.pfc_tcs = 4;
1029 * Ensure that all locks are released before first NVM or PHY access
1032 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1037 * Phy lock should not fail in this early stage. If this is the case,
1038 * it is due to an improper exit of the application.
1039 * So force the release of the faulty lock. Release of common lock
1040 * is done automatically by swfw_sync function.
1042 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1043 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1044 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1046 ixgbe_release_swfw_semaphore(hw, mask);
1049 * These ones are more tricky since they are common to all ports; but
1050 * swfw_sync retries last long enough (1s) to be almost sure that if
1051 * lock can not be taken it is due to an improper lock of the
1054 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1055 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1056 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1058 ixgbe_release_swfw_semaphore(hw, mask);
1062 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1063 * It returns 0 on success.
1066 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1068 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1069 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1070 struct ixgbe_hw *hw =
1071 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1072 struct ixgbe_vfta *shadow_vfta =
1073 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1074 struct ixgbe_hwstrip *hwstrip =
1075 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1076 struct ixgbe_dcb_config *dcb_config =
1077 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1078 struct ixgbe_filter_info *filter_info =
1079 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1080 struct ixgbe_bw_conf *bw_conf =
1081 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1086 PMD_INIT_FUNC_TRACE();
1088 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1089 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1090 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1091 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1094 * For secondary processes, we don't initialise any further as primary
1095 * has already done this work. Only check we don't need a different
1096 * RX and TX function.
1098 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1099 struct ixgbe_tx_queue *txq;
1100 /* TX queue function in primary, set by last queue initialized
1101 * Tx queue may not initialized by primary process
1103 if (eth_dev->data->tx_queues) {
1104 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1105 ixgbe_set_tx_function(eth_dev, txq);
1107 /* Use default TX function if we get here */
1108 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1109 "Using default TX function.");
1112 ixgbe_set_rx_function(eth_dev);
1117 rte_eth_copy_pci_info(eth_dev, pci_dev);
1119 /* Vendor and Device ID need to be set before init of shared code */
1120 hw->device_id = pci_dev->id.device_id;
1121 hw->vendor_id = pci_dev->id.vendor_id;
1122 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1123 hw->allow_unsupported_sfp = 1;
1125 /* Initialize the shared code (base driver) */
1126 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1127 diag = ixgbe_bypass_init_shared_code(hw);
1129 diag = ixgbe_init_shared_code(hw);
1130 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1132 if (diag != IXGBE_SUCCESS) {
1133 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1137 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1138 PMD_INIT_LOG(ERR, "\nERROR: "
1139 "Firmware recovery mode detected. Limiting functionality.\n"
1140 "Refer to the Intel(R) Ethernet Adapters and Devices "
1141 "User Guide for details on firmware recovery mode.");
1145 /* pick up the PCI bus settings for reporting later */
1146 ixgbe_get_bus_info(hw);
1148 /* Unlock any pending hardware semaphore */
1149 ixgbe_swfw_lock_reset(hw);
1151 #ifdef RTE_LIBRTE_SECURITY
1152 /* Initialize security_ctx only for primary process*/
1153 if (ixgbe_ipsec_ctx_create(eth_dev))
1157 /* Initialize DCB configuration*/
1158 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1159 ixgbe_dcb_init(hw, dcb_config);
1160 /* Get Hardware Flow Control setting */
1161 hw->fc.requested_mode = ixgbe_fc_full;
1162 hw->fc.current_mode = ixgbe_fc_full;
1163 hw->fc.pause_time = IXGBE_FC_PAUSE;
1164 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1165 hw->fc.low_water[i] = IXGBE_FC_LO;
1166 hw->fc.high_water[i] = IXGBE_FC_HI;
1168 hw->fc.send_xon = 1;
1170 /* Make sure we have a good EEPROM before we read from it */
1171 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1172 if (diag != IXGBE_SUCCESS) {
1173 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1177 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1178 diag = ixgbe_bypass_init_hw(hw);
1180 diag = ixgbe_init_hw(hw);
1181 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1184 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1185 * is called too soon after the kernel driver unbinding/binding occurs.
1186 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1187 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1188 * also called. See ixgbe_identify_phy_82599(). The reason for the
1189 * failure is not known, and only occuts when virtualisation features
1190 * are disabled in the bios. A delay of 100ms was found to be enough by
1191 * trial-and-error, and is doubled to be safe.
1193 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1195 diag = ixgbe_init_hw(hw);
1198 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1199 diag = IXGBE_SUCCESS;
1201 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1202 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1203 "LOM. Please be aware there may be issues associated "
1204 "with your hardware.");
1205 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1206 "please contact your Intel or hardware representative "
1207 "who provided you with this hardware.");
1208 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1209 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1211 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1215 /* Reset the hw statistics */
1216 ixgbe_dev_stats_reset(eth_dev);
1218 /* disable interrupt */
1219 ixgbe_disable_intr(hw);
1221 /* reset mappings for queue statistics hw counters*/
1222 ixgbe_reset_qstat_mappings(hw);
1224 /* Allocate memory for storing MAC addresses */
1225 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1226 hw->mac.num_rar_entries, 0);
1227 if (eth_dev->data->mac_addrs == NULL) {
1229 "Failed to allocate %u bytes needed to store "
1231 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1234 /* Copy the permanent MAC address */
1235 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1236 ð_dev->data->mac_addrs[0]);
1238 /* Allocate memory for storing hash filter MAC addresses */
1239 eth_dev->data->hash_mac_addrs = rte_zmalloc(
1240 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1241 if (eth_dev->data->hash_mac_addrs == NULL) {
1243 "Failed to allocate %d bytes needed to store MAC addresses",
1244 RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1248 /* initialize the vfta */
1249 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1251 /* initialize the hw strip bitmap*/
1252 memset(hwstrip, 0, sizeof(*hwstrip));
1254 /* initialize PF if max_vfs not zero */
1255 ixgbe_pf_host_init(eth_dev);
1257 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1258 /* let hardware know driver is loaded */
1259 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1260 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1261 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1262 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1263 IXGBE_WRITE_FLUSH(hw);
1265 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1266 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1267 (int) hw->mac.type, (int) hw->phy.type,
1268 (int) hw->phy.sfp_type);
1270 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1271 (int) hw->mac.type, (int) hw->phy.type);
1273 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1274 eth_dev->data->port_id, pci_dev->id.vendor_id,
1275 pci_dev->id.device_id);
1277 rte_intr_callback_register(intr_handle,
1278 ixgbe_dev_interrupt_handler, eth_dev);
1280 /* enable uio/vfio intr/eventfd mapping */
1281 rte_intr_enable(intr_handle);
1283 /* enable support intr */
1284 ixgbe_enable_intr(eth_dev);
1286 /* initialize filter info */
1287 memset(filter_info, 0,
1288 sizeof(struct ixgbe_filter_info));
1290 /* initialize 5tuple filter list */
1291 TAILQ_INIT(&filter_info->fivetuple_list);
1293 /* initialize flow director filter list & hash */
1294 ixgbe_fdir_filter_init(eth_dev);
1296 /* initialize l2 tunnel filter list & hash */
1297 ixgbe_l2_tn_filter_init(eth_dev);
1299 /* initialize flow filter lists */
1300 ixgbe_filterlist_init();
1302 /* initialize bandwidth configuration info */
1303 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1305 /* initialize Traffic Manager configuration */
1306 ixgbe_tm_conf_init(eth_dev);
1312 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1314 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1315 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1316 struct ixgbe_hw *hw;
1320 PMD_INIT_FUNC_TRACE();
1322 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1325 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1327 if (hw->adapter_stopped == 0)
1328 ixgbe_dev_close(eth_dev);
1330 eth_dev->dev_ops = NULL;
1331 eth_dev->rx_pkt_burst = NULL;
1332 eth_dev->tx_pkt_burst = NULL;
1334 /* Unlock any pending hardware semaphore */
1335 ixgbe_swfw_lock_reset(hw);
1337 /* disable uio intr before callback unregister */
1338 rte_intr_disable(intr_handle);
1341 ret = rte_intr_callback_unregister(intr_handle,
1342 ixgbe_dev_interrupt_handler, eth_dev);
1345 } else if (ret != -EAGAIN) {
1347 "intr callback unregister failed: %d",
1352 } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1354 /* cancel the delay handler before remove dev */
1355 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, eth_dev);
1357 /* cancel the link handler before remove dev */
1358 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, eth_dev);
1360 /* uninitialize PF if max_vfs not zero */
1361 ixgbe_pf_host_uninit(eth_dev);
1363 /* remove all the fdir filters & hash */
1364 ixgbe_fdir_filter_uninit(eth_dev);
1366 /* remove all the L2 tunnel filters & hash */
1367 ixgbe_l2_tn_filter_uninit(eth_dev);
1369 /* Remove all ntuple filters of the device */
1370 ixgbe_ntuple_filter_uninit(eth_dev);
1372 /* clear all the filters list */
1373 ixgbe_filterlist_flush();
1375 /* Remove all Traffic Manager configuration */
1376 ixgbe_tm_conf_uninit(eth_dev);
1378 #ifdef RTE_LIBRTE_SECURITY
1379 rte_free(eth_dev->security_ctx);
1385 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1387 struct ixgbe_filter_info *filter_info =
1388 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1389 struct ixgbe_5tuple_filter *p_5tuple;
1391 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1392 TAILQ_REMOVE(&filter_info->fivetuple_list,
1397 memset(filter_info->fivetuple_mask, 0,
1398 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1403 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1405 struct ixgbe_hw_fdir_info *fdir_info =
1406 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1407 struct ixgbe_fdir_filter *fdir_filter;
1409 if (fdir_info->hash_map)
1410 rte_free(fdir_info->hash_map);
1411 if (fdir_info->hash_handle)
1412 rte_hash_free(fdir_info->hash_handle);
1414 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1415 TAILQ_REMOVE(&fdir_info->fdir_list,
1418 rte_free(fdir_filter);
1424 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1426 struct ixgbe_l2_tn_info *l2_tn_info =
1427 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1428 struct ixgbe_l2_tn_filter *l2_tn_filter;
1430 if (l2_tn_info->hash_map)
1431 rte_free(l2_tn_info->hash_map);
1432 if (l2_tn_info->hash_handle)
1433 rte_hash_free(l2_tn_info->hash_handle);
1435 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1436 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1439 rte_free(l2_tn_filter);
1445 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1447 struct ixgbe_hw_fdir_info *fdir_info =
1448 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1449 char fdir_hash_name[RTE_HASH_NAMESIZE];
1450 struct rte_hash_parameters fdir_hash_params = {
1451 .name = fdir_hash_name,
1452 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1453 .key_len = sizeof(union ixgbe_atr_input),
1454 .hash_func = rte_hash_crc,
1455 .hash_func_init_val = 0,
1456 .socket_id = rte_socket_id(),
1459 TAILQ_INIT(&fdir_info->fdir_list);
1460 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1461 "fdir_%s", eth_dev->device->name);
1462 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1463 if (!fdir_info->hash_handle) {
1464 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1467 fdir_info->hash_map = rte_zmalloc("ixgbe",
1468 sizeof(struct ixgbe_fdir_filter *) *
1469 IXGBE_MAX_FDIR_FILTER_NUM,
1471 if (!fdir_info->hash_map) {
1473 "Failed to allocate memory for fdir hash map!");
1476 fdir_info->mask_added = FALSE;
1481 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1483 struct ixgbe_l2_tn_info *l2_tn_info =
1484 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1485 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1486 struct rte_hash_parameters l2_tn_hash_params = {
1487 .name = l2_tn_hash_name,
1488 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1489 .key_len = sizeof(struct ixgbe_l2_tn_key),
1490 .hash_func = rte_hash_crc,
1491 .hash_func_init_val = 0,
1492 .socket_id = rte_socket_id(),
1495 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1496 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1497 "l2_tn_%s", eth_dev->device->name);
1498 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1499 if (!l2_tn_info->hash_handle) {
1500 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1503 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1504 sizeof(struct ixgbe_l2_tn_filter *) *
1505 IXGBE_MAX_L2_TN_FILTER_NUM,
1507 if (!l2_tn_info->hash_map) {
1509 "Failed to allocate memory for L2 TN hash map!");
1512 l2_tn_info->e_tag_en = FALSE;
1513 l2_tn_info->e_tag_fwd_en = FALSE;
1514 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1519 * Negotiate mailbox API version with the PF.
1520 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1521 * Then we try to negotiate starting with the most recent one.
1522 * If all negotiation attempts fail, then we will proceed with
1523 * the default one (ixgbe_mbox_api_10).
1526 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1530 /* start with highest supported, proceed down */
1531 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1539 i != RTE_DIM(sup_ver) &&
1540 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1546 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1550 /* Set Organizationally Unique Identifier (OUI) prefix. */
1551 mac_addr->addr_bytes[0] = 0x00;
1552 mac_addr->addr_bytes[1] = 0x09;
1553 mac_addr->addr_bytes[2] = 0xC0;
1554 /* Force indication of locally assigned MAC address. */
1555 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1556 /* Generate the last 3 bytes of the MAC address with a random number. */
1557 random = rte_rand();
1558 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1562 devarg_handle_int(__rte_unused const char *key, const char *value,
1565 uint16_t *n = extra_args;
1567 if (value == NULL || extra_args == NULL)
1570 *n = (uint16_t)strtoul(value, NULL, 0);
1571 if (*n == USHRT_MAX && errno == ERANGE)
1578 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1579 struct rte_devargs *devargs)
1581 struct rte_kvargs *kvlist;
1582 uint16_t pflink_fullchk;
1584 if (devargs == NULL)
1587 kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1591 if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1592 rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1593 devarg_handle_int, &pflink_fullchk) == 0 &&
1594 pflink_fullchk == 1)
1595 adapter->pflink_fullchk = 1;
1597 rte_kvargs_free(kvlist);
1601 * Virtual Function device init
1604 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1608 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1609 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1610 struct ixgbe_hw *hw =
1611 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1612 struct ixgbe_vfta *shadow_vfta =
1613 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1614 struct ixgbe_hwstrip *hwstrip =
1615 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1616 struct rte_ether_addr *perm_addr =
1617 (struct rte_ether_addr *)hw->mac.perm_addr;
1619 PMD_INIT_FUNC_TRACE();
1621 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1622 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1623 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1625 /* for secondary processes, we don't initialise any further as primary
1626 * has already done this work. Only check we don't need a different
1629 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1630 struct ixgbe_tx_queue *txq;
1631 /* TX queue function in primary, set by last queue initialized
1632 * Tx queue may not initialized by primary process
1634 if (eth_dev->data->tx_queues) {
1635 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1636 ixgbe_set_tx_function(eth_dev, txq);
1638 /* Use default TX function if we get here */
1639 PMD_INIT_LOG(NOTICE,
1640 "No TX queues configured yet. Using default TX function.");
1643 ixgbe_set_rx_function(eth_dev);
1648 ixgbevf_parse_devargs(eth_dev->data->dev_private,
1649 pci_dev->device.devargs);
1651 rte_eth_copy_pci_info(eth_dev, pci_dev);
1653 hw->device_id = pci_dev->id.device_id;
1654 hw->vendor_id = pci_dev->id.vendor_id;
1655 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1657 /* initialize the vfta */
1658 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1660 /* initialize the hw strip bitmap*/
1661 memset(hwstrip, 0, sizeof(*hwstrip));
1663 /* Initialize the shared code (base driver) */
1664 diag = ixgbe_init_shared_code(hw);
1665 if (diag != IXGBE_SUCCESS) {
1666 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1670 /* init_mailbox_params */
1671 hw->mbx.ops.init_params(hw);
1673 /* Reset the hw statistics */
1674 ixgbevf_dev_stats_reset(eth_dev);
1676 /* Disable the interrupts for VF */
1677 ixgbevf_intr_disable(eth_dev);
1679 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1680 diag = hw->mac.ops.reset_hw(hw);
1683 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1684 * the underlying PF driver has not assigned a MAC address to the VF.
1685 * In this case, assign a random MAC address.
1687 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1688 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1690 * This error code will be propagated to the app by
1691 * rte_eth_dev_reset, so use a public error code rather than
1692 * the internal-only IXGBE_ERR_RESET_FAILED
1697 /* negotiate mailbox API version to use with the PF. */
1698 ixgbevf_negotiate_api(hw);
1700 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1701 ixgbevf_get_queues(hw, &tcs, &tc);
1703 /* Allocate memory for storing MAC addresses */
1704 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1705 hw->mac.num_rar_entries, 0);
1706 if (eth_dev->data->mac_addrs == NULL) {
1708 "Failed to allocate %u bytes needed to store "
1710 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1714 /* Generate a random MAC address, if none was assigned by PF. */
1715 if (rte_is_zero_ether_addr(perm_addr)) {
1716 generate_random_mac_addr(perm_addr);
1717 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1719 rte_free(eth_dev->data->mac_addrs);
1720 eth_dev->data->mac_addrs = NULL;
1723 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1724 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1725 "%02x:%02x:%02x:%02x:%02x:%02x",
1726 perm_addr->addr_bytes[0],
1727 perm_addr->addr_bytes[1],
1728 perm_addr->addr_bytes[2],
1729 perm_addr->addr_bytes[3],
1730 perm_addr->addr_bytes[4],
1731 perm_addr->addr_bytes[5]);
1734 /* Copy the permanent MAC address */
1735 rte_ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1737 /* reset the hardware with the new settings */
1738 diag = hw->mac.ops.start_hw(hw);
1744 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1748 rte_intr_callback_register(intr_handle,
1749 ixgbevf_dev_interrupt_handler, eth_dev);
1750 rte_intr_enable(intr_handle);
1751 ixgbevf_intr_enable(eth_dev);
1753 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1754 eth_dev->data->port_id, pci_dev->id.vendor_id,
1755 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1760 /* Virtual Function device uninit */
1763 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1765 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1766 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1767 struct ixgbe_hw *hw;
1769 PMD_INIT_FUNC_TRACE();
1771 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1774 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1776 if (hw->adapter_stopped == 0)
1777 ixgbevf_dev_close(eth_dev);
1779 eth_dev->dev_ops = NULL;
1780 eth_dev->rx_pkt_burst = NULL;
1781 eth_dev->tx_pkt_burst = NULL;
1783 /* Disable the interrupts for VF */
1784 ixgbevf_intr_disable(eth_dev);
1786 rte_intr_disable(intr_handle);
1787 rte_intr_callback_unregister(intr_handle,
1788 ixgbevf_dev_interrupt_handler, eth_dev);
1794 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1795 struct rte_pci_device *pci_dev)
1797 char name[RTE_ETH_NAME_MAX_LEN];
1798 struct rte_eth_dev *pf_ethdev;
1799 struct rte_eth_devargs eth_da;
1802 if (pci_dev->device.devargs) {
1803 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1808 memset(ð_da, 0, sizeof(eth_da));
1810 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1811 sizeof(struct ixgbe_adapter),
1812 eth_dev_pci_specific_init, pci_dev,
1813 eth_ixgbe_dev_init, NULL);
1815 if (retval || eth_da.nb_representor_ports < 1)
1818 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1819 if (pf_ethdev == NULL)
1822 /* probe VF representor ports */
1823 for (i = 0; i < eth_da.nb_representor_ports; i++) {
1824 struct ixgbe_vf_info *vfinfo;
1825 struct ixgbe_vf_representor representor;
1827 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1828 pf_ethdev->data->dev_private);
1829 if (vfinfo == NULL) {
1831 "no virtual functions supported by PF");
1835 representor.vf_id = eth_da.representor_ports[i];
1836 representor.switch_domain_id = vfinfo->switch_domain_id;
1837 representor.pf_ethdev = pf_ethdev;
1839 /* representor port net_bdf_port */
1840 snprintf(name, sizeof(name), "net_%s_representor_%d",
1841 pci_dev->device.name,
1842 eth_da.representor_ports[i]);
1844 retval = rte_eth_dev_create(&pci_dev->device, name,
1845 sizeof(struct ixgbe_vf_representor), NULL, NULL,
1846 ixgbe_vf_representor_init, &representor);
1849 PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1850 "representor %s.", name);
1856 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1858 struct rte_eth_dev *ethdev;
1860 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1864 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1865 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1867 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1870 static struct rte_pci_driver rte_ixgbe_pmd = {
1871 .id_table = pci_id_ixgbe_map,
1872 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1873 .probe = eth_ixgbe_pci_probe,
1874 .remove = eth_ixgbe_pci_remove,
1877 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1878 struct rte_pci_device *pci_dev)
1880 return rte_eth_dev_pci_generic_probe(pci_dev,
1881 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1884 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1886 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1890 * virtual function driver struct
1892 static struct rte_pci_driver rte_ixgbevf_pmd = {
1893 .id_table = pci_id_ixgbevf_map,
1894 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1895 .probe = eth_ixgbevf_pci_probe,
1896 .remove = eth_ixgbevf_pci_remove,
1900 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1902 struct ixgbe_hw *hw =
1903 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1904 struct ixgbe_vfta *shadow_vfta =
1905 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1910 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1911 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1912 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1917 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1919 /* update local VFTA copy */
1920 shadow_vfta->vfta[vid_idx] = vfta;
1926 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1929 ixgbe_vlan_hw_strip_enable(dev, queue);
1931 ixgbe_vlan_hw_strip_disable(dev, queue);
1935 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1936 enum rte_vlan_type vlan_type,
1939 struct ixgbe_hw *hw =
1940 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1945 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1946 qinq &= IXGBE_DMATXCTL_GDV;
1948 switch (vlan_type) {
1949 case ETH_VLAN_TYPE_INNER:
1951 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1952 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1953 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1954 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1955 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1956 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1957 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1960 PMD_DRV_LOG(ERR, "Inner type is not supported"
1964 case ETH_VLAN_TYPE_OUTER:
1966 /* Only the high 16-bits is valid */
1967 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1968 IXGBE_EXVET_VET_EXT_SHIFT);
1970 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1971 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1972 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1973 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1974 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1975 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1976 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1982 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1990 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1992 struct ixgbe_hw *hw =
1993 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1996 PMD_INIT_FUNC_TRACE();
1998 /* Filter Table Disable */
1999 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2000 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2002 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2006 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2008 struct ixgbe_hw *hw =
2009 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2010 struct ixgbe_vfta *shadow_vfta =
2011 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2015 PMD_INIT_FUNC_TRACE();
2017 /* Filter Table Enable */
2018 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2019 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2020 vlnctrl |= IXGBE_VLNCTRL_VFE;
2022 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2024 /* write whatever is in local vfta copy */
2025 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
2026 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
2030 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
2032 struct ixgbe_hwstrip *hwstrip =
2033 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
2034 struct ixgbe_rx_queue *rxq;
2036 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
2040 IXGBE_SET_HWSTRIP(hwstrip, queue);
2042 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
2044 if (queue >= dev->data->nb_rx_queues)
2047 rxq = dev->data->rx_queues[queue];
2050 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2051 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2053 rxq->vlan_flags = PKT_RX_VLAN;
2054 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2059 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2061 struct ixgbe_hw *hw =
2062 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2065 PMD_INIT_FUNC_TRACE();
2067 if (hw->mac.type == ixgbe_mac_82598EB) {
2068 /* No queue level support */
2069 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2073 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2074 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2075 ctrl &= ~IXGBE_RXDCTL_VME;
2076 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2078 /* record those setting for HW strip per queue */
2079 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2083 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2085 struct ixgbe_hw *hw =
2086 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2089 PMD_INIT_FUNC_TRACE();
2091 if (hw->mac.type == ixgbe_mac_82598EB) {
2092 /* No queue level supported */
2093 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2097 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2098 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2099 ctrl |= IXGBE_RXDCTL_VME;
2100 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2102 /* record those setting for HW strip per queue */
2103 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2107 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2109 struct ixgbe_hw *hw =
2110 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2113 PMD_INIT_FUNC_TRACE();
2115 /* DMATXCTRL: Geric Double VLAN Disable */
2116 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2117 ctrl &= ~IXGBE_DMATXCTL_GDV;
2118 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2120 /* CTRL_EXT: Global Double VLAN Disable */
2121 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2122 ctrl &= ~IXGBE_EXTENDED_VLAN;
2123 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2128 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2130 struct ixgbe_hw *hw =
2131 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134 PMD_INIT_FUNC_TRACE();
2136 /* DMATXCTRL: Geric Double VLAN Enable */
2137 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2138 ctrl |= IXGBE_DMATXCTL_GDV;
2139 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2141 /* CTRL_EXT: Global Double VLAN Enable */
2142 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2143 ctrl |= IXGBE_EXTENDED_VLAN;
2144 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2146 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2147 if (hw->mac.type == ixgbe_mac_X550 ||
2148 hw->mac.type == ixgbe_mac_X550EM_x ||
2149 hw->mac.type == ixgbe_mac_X550EM_a) {
2150 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2151 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2152 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2156 * VET EXT field in the EXVET register = 0x8100 by default
2157 * So no need to change. Same to VT field of DMATXCTL register
2162 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2164 struct ixgbe_hw *hw =
2165 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2166 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2169 struct ixgbe_rx_queue *rxq;
2172 PMD_INIT_FUNC_TRACE();
2174 if (hw->mac.type == ixgbe_mac_82598EB) {
2175 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2176 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2177 ctrl |= IXGBE_VLNCTRL_VME;
2178 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2180 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2181 ctrl &= ~IXGBE_VLNCTRL_VME;
2182 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2186 * Other 10G NIC, the VLAN strip can be setup
2187 * per queue in RXDCTL
2189 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2190 rxq = dev->data->rx_queues[i];
2191 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2192 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2193 ctrl |= IXGBE_RXDCTL_VME;
2196 ctrl &= ~IXGBE_RXDCTL_VME;
2199 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2201 /* record those setting for HW strip per queue */
2202 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2208 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2211 struct rte_eth_rxmode *rxmode;
2212 struct ixgbe_rx_queue *rxq;
2214 if (mask & ETH_VLAN_STRIP_MASK) {
2215 rxmode = &dev->data->dev_conf.rxmode;
2216 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2217 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2218 rxq = dev->data->rx_queues[i];
2219 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2222 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2223 rxq = dev->data->rx_queues[i];
2224 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2230 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2232 struct rte_eth_rxmode *rxmode;
2233 rxmode = &dev->data->dev_conf.rxmode;
2235 if (mask & ETH_VLAN_STRIP_MASK) {
2236 ixgbe_vlan_hw_strip_config(dev);
2239 if (mask & ETH_VLAN_FILTER_MASK) {
2240 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2241 ixgbe_vlan_hw_filter_enable(dev);
2243 ixgbe_vlan_hw_filter_disable(dev);
2246 if (mask & ETH_VLAN_EXTEND_MASK) {
2247 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2248 ixgbe_vlan_hw_extend_enable(dev);
2250 ixgbe_vlan_hw_extend_disable(dev);
2257 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2259 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2261 ixgbe_vlan_offload_config(dev, mask);
2267 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2269 struct ixgbe_hw *hw =
2270 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2271 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2272 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2274 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2275 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2279 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2281 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2286 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2289 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2295 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2296 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2297 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2298 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2303 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2305 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2306 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2307 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2308 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2310 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2311 /* check multi-queue mode */
2312 switch (dev_conf->rxmode.mq_mode) {
2313 case ETH_MQ_RX_VMDQ_DCB:
2314 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2316 case ETH_MQ_RX_VMDQ_DCB_RSS:
2317 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2318 PMD_INIT_LOG(ERR, "SRIOV active,"
2319 " unsupported mq_mode rx %d.",
2320 dev_conf->rxmode.mq_mode);
2323 case ETH_MQ_RX_VMDQ_RSS:
2324 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2325 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2326 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2327 PMD_INIT_LOG(ERR, "SRIOV is active,"
2328 " invalid queue number"
2329 " for VMDQ RSS, allowed"
2330 " value are 1, 2 or 4.");
2334 case ETH_MQ_RX_VMDQ_ONLY:
2335 case ETH_MQ_RX_NONE:
2336 /* if nothing mq mode configure, use default scheme */
2337 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2339 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2340 /* SRIOV only works in VMDq enable mode */
2341 PMD_INIT_LOG(ERR, "SRIOV is active,"
2342 " wrong mq_mode rx %d.",
2343 dev_conf->rxmode.mq_mode);
2347 switch (dev_conf->txmode.mq_mode) {
2348 case ETH_MQ_TX_VMDQ_DCB:
2349 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2350 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2352 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2353 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2357 /* check valid queue number */
2358 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2359 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2360 PMD_INIT_LOG(ERR, "SRIOV is active,"
2361 " nb_rx_q=%d nb_tx_q=%d queue number"
2362 " must be less than or equal to %d.",
2364 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2368 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2369 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2373 /* check configuration for vmdb+dcb mode */
2374 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2375 const struct rte_eth_vmdq_dcb_conf *conf;
2377 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2378 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2379 IXGBE_VMDQ_DCB_NB_QUEUES);
2382 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2383 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2384 conf->nb_queue_pools == ETH_32_POOLS)) {
2385 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2386 " nb_queue_pools must be %d or %d.",
2387 ETH_16_POOLS, ETH_32_POOLS);
2391 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2392 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2394 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2395 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2396 IXGBE_VMDQ_DCB_NB_QUEUES);
2399 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2400 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2401 conf->nb_queue_pools == ETH_32_POOLS)) {
2402 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2403 " nb_queue_pools != %d and"
2404 " nb_queue_pools != %d.",
2405 ETH_16_POOLS, ETH_32_POOLS);
2410 /* For DCB mode check our configuration before we go further */
2411 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2412 const struct rte_eth_dcb_rx_conf *conf;
2414 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2415 if (!(conf->nb_tcs == ETH_4_TCS ||
2416 conf->nb_tcs == ETH_8_TCS)) {
2417 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2418 " and nb_tcs != %d.",
2419 ETH_4_TCS, ETH_8_TCS);
2424 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2425 const struct rte_eth_dcb_tx_conf *conf;
2427 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2428 if (!(conf->nb_tcs == ETH_4_TCS ||
2429 conf->nb_tcs == ETH_8_TCS)) {
2430 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2431 " and nb_tcs != %d.",
2432 ETH_4_TCS, ETH_8_TCS);
2438 * When DCB/VT is off, maximum number of queues changes,
2439 * except for 82598EB, which remains constant.
2441 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2442 hw->mac.type != ixgbe_mac_82598EB) {
2443 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2445 "Neither VT nor DCB are enabled, "
2447 IXGBE_NONE_MODE_TX_NB_QUEUES);
2456 ixgbe_dev_configure(struct rte_eth_dev *dev)
2458 struct ixgbe_interrupt *intr =
2459 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2460 struct ixgbe_adapter *adapter = dev->data->dev_private;
2463 PMD_INIT_FUNC_TRACE();
2464 /* multipe queue mode checking */
2465 ret = ixgbe_check_mq_mode(dev);
2467 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2472 /* set flag to update link status after init */
2473 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2476 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2477 * allocation or vector Rx preconditions we will reset it.
2479 adapter->rx_bulk_alloc_allowed = true;
2480 adapter->rx_vec_allowed = true;
2486 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2488 struct ixgbe_hw *hw =
2489 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2490 struct ixgbe_interrupt *intr =
2491 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2494 /* only set up it on X550EM_X */
2495 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2496 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2497 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2498 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2499 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2500 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2505 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2506 uint16_t tx_rate, uint64_t q_msk)
2508 struct ixgbe_hw *hw;
2509 struct ixgbe_vf_info *vfinfo;
2510 struct rte_eth_link link;
2511 uint8_t nb_q_per_pool;
2512 uint32_t queue_stride;
2513 uint32_t queue_idx, idx = 0, vf_idx;
2515 uint16_t total_rate = 0;
2516 struct rte_pci_device *pci_dev;
2519 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2520 ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2524 if (vf >= pci_dev->max_vfs)
2527 if (tx_rate > link.link_speed)
2533 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2534 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2535 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2536 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2537 queue_idx = vf * queue_stride;
2538 queue_end = queue_idx + nb_q_per_pool - 1;
2539 if (queue_end >= hw->mac.max_tx_queues)
2543 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2546 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2548 total_rate += vfinfo[vf_idx].tx_rate[idx];
2554 /* Store tx_rate for this vf. */
2555 for (idx = 0; idx < nb_q_per_pool; idx++) {
2556 if (((uint64_t)0x1 << idx) & q_msk) {
2557 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2558 vfinfo[vf].tx_rate[idx] = tx_rate;
2559 total_rate += tx_rate;
2563 if (total_rate > dev->data->dev_link.link_speed) {
2564 /* Reset stored TX rate of the VF if it causes exceed
2567 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2571 /* Set RTTBCNRC of each queue/pool for vf X */
2572 for (; queue_idx <= queue_end; queue_idx++) {
2574 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2582 * Configure device link speed and setup link.
2583 * It returns 0 on success.
2586 ixgbe_dev_start(struct rte_eth_dev *dev)
2588 struct ixgbe_hw *hw =
2589 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2590 struct ixgbe_vf_info *vfinfo =
2591 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2592 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2593 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2594 uint32_t intr_vector = 0;
2595 int err, link_up = 0, negotiate = 0;
2597 uint32_t allowed_speeds = 0;
2601 uint32_t *link_speeds;
2602 struct ixgbe_tm_conf *tm_conf =
2603 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2605 PMD_INIT_FUNC_TRACE();
2607 /* IXGBE devices don't support:
2608 * - half duplex (checked afterwards for valid speeds)
2609 * - fixed speed: TODO implement
2611 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2613 "Invalid link_speeds for port %u, fix speed not supported",
2614 dev->data->port_id);
2618 /* Stop the link setup handler before resetting the HW. */
2619 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2621 /* disable uio/vfio intr/eventfd mapping */
2622 rte_intr_disable(intr_handle);
2625 hw->adapter_stopped = 0;
2626 ixgbe_stop_adapter(hw);
2628 /* reinitialize adapter
2629 * this calls reset and start
2631 status = ixgbe_pf_reset_hw(hw);
2634 hw->mac.ops.start_hw(hw);
2635 hw->mac.get_link_status = true;
2637 /* configure PF module if SRIOV enabled */
2638 ixgbe_pf_host_configure(dev);
2640 ixgbe_dev_phy_intr_setup(dev);
2642 /* check and configure queue intr-vector mapping */
2643 if ((rte_intr_cap_multiple(intr_handle) ||
2644 !RTE_ETH_DEV_SRIOV(dev).active) &&
2645 dev->data->dev_conf.intr_conf.rxq != 0) {
2646 intr_vector = dev->data->nb_rx_queues;
2647 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2648 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2649 IXGBE_MAX_INTR_QUEUE_NUM);
2652 if (rte_intr_efd_enable(intr_handle, intr_vector))
2656 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2657 intr_handle->intr_vec =
2658 rte_zmalloc("intr_vec",
2659 dev->data->nb_rx_queues * sizeof(int), 0);
2660 if (intr_handle->intr_vec == NULL) {
2661 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2662 " intr_vec", dev->data->nb_rx_queues);
2667 /* confiugre msix for sleep until rx interrupt */
2668 ixgbe_configure_msix(dev);
2670 /* initialize transmission unit */
2671 ixgbe_dev_tx_init(dev);
2673 /* This can fail when allocating mbufs for descriptor rings */
2674 err = ixgbe_dev_rx_init(dev);
2676 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2680 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2681 ETH_VLAN_EXTEND_MASK;
2682 err = ixgbe_vlan_offload_config(dev, mask);
2684 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2688 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2689 /* Enable vlan filtering for VMDq */
2690 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2693 /* Configure DCB hw */
2694 ixgbe_configure_dcb(dev);
2696 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2697 err = ixgbe_fdir_configure(dev);
2702 /* Restore vf rate limit */
2703 if (vfinfo != NULL) {
2704 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2705 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2706 if (vfinfo[vf].tx_rate[idx] != 0)
2707 ixgbe_set_vf_rate_limit(
2709 vfinfo[vf].tx_rate[idx],
2713 ixgbe_restore_statistics_mapping(dev);
2715 err = ixgbe_dev_rxtx_start(dev);
2717 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2721 /* Skip link setup if loopback mode is enabled. */
2722 if (dev->data->dev_conf.lpbk_mode != 0) {
2723 err = ixgbe_check_supported_loopback_mode(dev);
2725 PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2728 goto skip_link_setup;
2732 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2733 err = hw->mac.ops.setup_sfp(hw);
2738 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2739 /* Turn on the copper */
2740 ixgbe_set_phy_power(hw, true);
2742 /* Turn on the laser */
2743 ixgbe_enable_tx_laser(hw);
2746 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2749 dev->data->dev_link.link_status = link_up;
2751 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2755 switch (hw->mac.type) {
2756 case ixgbe_mac_X550:
2757 case ixgbe_mac_X550EM_x:
2758 case ixgbe_mac_X550EM_a:
2759 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2760 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G |
2762 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2763 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2764 allowed_speeds = ETH_LINK_SPEED_10M |
2765 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2768 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2772 link_speeds = &dev->data->dev_conf.link_speeds;
2773 if (*link_speeds & ~allowed_speeds) {
2774 PMD_INIT_LOG(ERR, "Invalid link setting");
2779 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2780 switch (hw->mac.type) {
2781 case ixgbe_mac_82598EB:
2782 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2784 case ixgbe_mac_82599EB:
2785 case ixgbe_mac_X540:
2786 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2788 case ixgbe_mac_X550:
2789 case ixgbe_mac_X550EM_x:
2790 case ixgbe_mac_X550EM_a:
2791 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2794 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2797 if (*link_speeds & ETH_LINK_SPEED_10G)
2798 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2799 if (*link_speeds & ETH_LINK_SPEED_5G)
2800 speed |= IXGBE_LINK_SPEED_5GB_FULL;
2801 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2802 speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2803 if (*link_speeds & ETH_LINK_SPEED_1G)
2804 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2805 if (*link_speeds & ETH_LINK_SPEED_100M)
2806 speed |= IXGBE_LINK_SPEED_100_FULL;
2807 if (*link_speeds & ETH_LINK_SPEED_10M)
2808 speed |= IXGBE_LINK_SPEED_10_FULL;
2811 err = ixgbe_setup_link(hw, speed, link_up);
2817 if (rte_intr_allow_others(intr_handle)) {
2818 /* check if lsc interrupt is enabled */
2819 if (dev->data->dev_conf.intr_conf.lsc != 0)
2820 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2822 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2823 ixgbe_dev_macsec_interrupt_setup(dev);
2825 rte_intr_callback_unregister(intr_handle,
2826 ixgbe_dev_interrupt_handler, dev);
2827 if (dev->data->dev_conf.intr_conf.lsc != 0)
2828 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2829 " no intr multiplex");
2832 /* check if rxq interrupt is enabled */
2833 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2834 rte_intr_dp_is_en(intr_handle))
2835 ixgbe_dev_rxq_interrupt_setup(dev);
2837 /* enable uio/vfio intr/eventfd mapping */
2838 rte_intr_enable(intr_handle);
2840 /* resume enabled intr since hw reset */
2841 ixgbe_enable_intr(dev);
2842 ixgbe_l2_tunnel_conf(dev);
2843 ixgbe_filter_restore(dev);
2845 if (tm_conf->root && !tm_conf->committed)
2846 PMD_DRV_LOG(WARNING,
2847 "please call hierarchy_commit() "
2848 "before starting the port");
2851 * Update link status right before return, because it may
2852 * start link configuration process in a separate thread.
2854 ixgbe_dev_link_update(dev, 0);
2859 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2860 ixgbe_dev_clear_queues(dev);
2865 * Stop device: disable rx and tx functions to allow for reconfiguring.
2868 ixgbe_dev_stop(struct rte_eth_dev *dev)
2870 struct rte_eth_link link;
2871 struct ixgbe_adapter *adapter = dev->data->dev_private;
2872 struct ixgbe_hw *hw =
2873 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2874 struct ixgbe_vf_info *vfinfo =
2875 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2876 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2877 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2879 struct ixgbe_tm_conf *tm_conf =
2880 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2882 PMD_INIT_FUNC_TRACE();
2884 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2886 /* disable interrupts */
2887 ixgbe_disable_intr(hw);
2890 ixgbe_pf_reset_hw(hw);
2891 hw->adapter_stopped = 0;
2894 ixgbe_stop_adapter(hw);
2896 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2897 vfinfo[vf].clear_to_send = false;
2899 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2900 /* Turn off the copper */
2901 ixgbe_set_phy_power(hw, false);
2903 /* Turn off the laser */
2904 ixgbe_disable_tx_laser(hw);
2907 ixgbe_dev_clear_queues(dev);
2909 /* Clear stored conf */
2910 dev->data->scattered_rx = 0;
2913 /* Clear recorded link status */
2914 memset(&link, 0, sizeof(link));
2915 rte_eth_linkstatus_set(dev, &link);
2917 if (!rte_intr_allow_others(intr_handle))
2918 /* resume to the default handler */
2919 rte_intr_callback_register(intr_handle,
2920 ixgbe_dev_interrupt_handler,
2923 /* Clean datapath event and queue/vec mapping */
2924 rte_intr_efd_disable(intr_handle);
2925 if (intr_handle->intr_vec != NULL) {
2926 rte_free(intr_handle->intr_vec);
2927 intr_handle->intr_vec = NULL;
2930 /* reset hierarchy commit */
2931 tm_conf->committed = false;
2933 adapter->rss_reta_updated = 0;
2937 * Set device link up: enable tx.
2940 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2942 struct ixgbe_hw *hw =
2943 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2944 if (hw->mac.type == ixgbe_mac_82599EB) {
2945 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2946 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2947 /* Not suported in bypass mode */
2948 PMD_INIT_LOG(ERR, "Set link up is not supported "
2949 "by device id 0x%x", hw->device_id);
2955 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2956 /* Turn on the copper */
2957 ixgbe_set_phy_power(hw, true);
2959 /* Turn on the laser */
2960 ixgbe_enable_tx_laser(hw);
2967 * Set device link down: disable tx.
2970 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2972 struct ixgbe_hw *hw =
2973 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2974 if (hw->mac.type == ixgbe_mac_82599EB) {
2975 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2976 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2977 /* Not suported in bypass mode */
2978 PMD_INIT_LOG(ERR, "Set link down is not supported "
2979 "by device id 0x%x", hw->device_id);
2985 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2986 /* Turn off the copper */
2987 ixgbe_set_phy_power(hw, false);
2989 /* Turn off the laser */
2990 ixgbe_disable_tx_laser(hw);
2997 * Reset and stop device.
3000 ixgbe_dev_close(struct rte_eth_dev *dev)
3002 struct ixgbe_hw *hw =
3003 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3005 PMD_INIT_FUNC_TRACE();
3007 ixgbe_pf_reset_hw(hw);
3009 ixgbe_dev_stop(dev);
3010 hw->adapter_stopped = 1;
3012 ixgbe_dev_free_queues(dev);
3014 ixgbe_disable_pcie_master(hw);
3016 /* reprogram the RAR[0] in case user changed it. */
3017 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3024 ixgbe_dev_reset(struct rte_eth_dev *dev)
3028 /* When a DPDK PMD PF begin to reset PF port, it should notify all
3029 * its VF to make them align with it. The detailed notification
3030 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3031 * To avoid unexpected behavior in VF, currently reset of PF with
3032 * SR-IOV activation is not supported. It might be supported later.
3034 if (dev->data->sriov.active)
3037 ret = eth_ixgbe_dev_uninit(dev);
3041 ret = eth_ixgbe_dev_init(dev, NULL);
3047 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3048 struct ixgbe_hw_stats *hw_stats,
3049 struct ixgbe_macsec_stats *macsec_stats,
3050 uint64_t *total_missed_rx, uint64_t *total_qbrc,
3051 uint64_t *total_qprc, uint64_t *total_qprdc)
3053 uint32_t bprc, lxon, lxoff, total;
3054 uint32_t delta_gprc = 0;
3056 /* Workaround for RX byte count not including CRC bytes when CRC
3057 * strip is enabled. CRC bytes are removed from counters when crc_strip
3060 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3061 IXGBE_HLREG0_RXCRCSTRP);
3063 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3064 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3065 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3066 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3068 for (i = 0; i < 8; i++) {
3069 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3071 /* global total per queue */
3072 hw_stats->mpc[i] += mp;
3073 /* Running comprehensive total for stats display */
3074 *total_missed_rx += hw_stats->mpc[i];
3075 if (hw->mac.type == ixgbe_mac_82598EB) {
3076 hw_stats->rnbc[i] +=
3077 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3078 hw_stats->pxonrxc[i] +=
3079 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3080 hw_stats->pxoffrxc[i] +=
3081 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3083 hw_stats->pxonrxc[i] +=
3084 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3085 hw_stats->pxoffrxc[i] +=
3086 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3087 hw_stats->pxon2offc[i] +=
3088 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3090 hw_stats->pxontxc[i] +=
3091 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3092 hw_stats->pxofftxc[i] +=
3093 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3095 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3096 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3097 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3098 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3100 delta_gprc += delta_qprc;
3102 hw_stats->qprc[i] += delta_qprc;
3103 hw_stats->qptc[i] += delta_qptc;
3105 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3106 hw_stats->qbrc[i] +=
3107 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3109 hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3111 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3112 hw_stats->qbtc[i] +=
3113 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3115 hw_stats->qprdc[i] += delta_qprdc;
3116 *total_qprdc += hw_stats->qprdc[i];
3118 *total_qprc += hw_stats->qprc[i];
3119 *total_qbrc += hw_stats->qbrc[i];
3121 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3122 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3123 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3126 * An errata states that gprc actually counts good + missed packets:
3127 * Workaround to set gprc to summated queue packet receives
3129 hw_stats->gprc = *total_qprc;
3131 if (hw->mac.type != ixgbe_mac_82598EB) {
3132 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3133 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3134 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3135 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3136 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3137 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3138 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3139 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3141 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3142 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3143 /* 82598 only has a counter in the high register */
3144 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3145 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3146 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3148 uint64_t old_tpr = hw_stats->tpr;
3150 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3151 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3154 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3156 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3157 hw_stats->gptc += delta_gptc;
3158 hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3159 hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3162 * Workaround: mprc hardware is incorrectly counting
3163 * broadcasts, so for now we subtract those.
3165 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3166 hw_stats->bprc += bprc;
3167 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3168 if (hw->mac.type == ixgbe_mac_82598EB)
3169 hw_stats->mprc -= bprc;
3171 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3172 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3173 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3174 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3175 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3176 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3178 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3179 hw_stats->lxontxc += lxon;
3180 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3181 hw_stats->lxofftxc += lxoff;
3182 total = lxon + lxoff;
3184 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3185 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3186 hw_stats->gptc -= total;
3187 hw_stats->mptc -= total;
3188 hw_stats->ptc64 -= total;
3189 hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3191 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3192 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3193 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3194 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3195 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3196 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3197 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3198 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3199 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3200 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3201 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3202 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3203 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3204 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3205 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3206 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3207 /* Only read FCOE on 82599 */
3208 if (hw->mac.type != ixgbe_mac_82598EB) {
3209 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3210 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3211 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3212 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3213 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3216 /* Flow Director Stats registers */
3217 if (hw->mac.type != ixgbe_mac_82598EB) {
3218 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3219 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3220 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3221 IXGBE_FDIRUSTAT) & 0xFFFF;
3222 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3223 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3224 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3225 IXGBE_FDIRFSTAT) & 0xFFFF;
3226 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3227 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3229 /* MACsec Stats registers */
3230 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3231 macsec_stats->out_pkts_encrypted +=
3232 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3233 macsec_stats->out_pkts_protected +=
3234 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3235 macsec_stats->out_octets_encrypted +=
3236 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3237 macsec_stats->out_octets_protected +=
3238 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3239 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3240 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3241 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3242 macsec_stats->in_pkts_unknownsci +=
3243 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3244 macsec_stats->in_octets_decrypted +=
3245 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3246 macsec_stats->in_octets_validated +=
3247 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3248 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3249 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3250 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3251 for (i = 0; i < 2; i++) {
3252 macsec_stats->in_pkts_ok +=
3253 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3254 macsec_stats->in_pkts_invalid +=
3255 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3256 macsec_stats->in_pkts_notvalid +=
3257 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3259 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3260 macsec_stats->in_pkts_notusingsa +=
3261 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3265 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3268 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3270 struct ixgbe_hw *hw =
3271 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3272 struct ixgbe_hw_stats *hw_stats =
3273 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3274 struct ixgbe_macsec_stats *macsec_stats =
3275 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3276 dev->data->dev_private);
3277 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3280 total_missed_rx = 0;
3285 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3286 &total_qbrc, &total_qprc, &total_qprdc);
3291 /* Fill out the rte_eth_stats statistics structure */
3292 stats->ipackets = total_qprc;
3293 stats->ibytes = total_qbrc;
3294 stats->opackets = hw_stats->gptc;
3295 stats->obytes = hw_stats->gotc;
3297 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3298 stats->q_ipackets[i] = hw_stats->qprc[i];
3299 stats->q_opackets[i] = hw_stats->qptc[i];
3300 stats->q_ibytes[i] = hw_stats->qbrc[i];
3301 stats->q_obytes[i] = hw_stats->qbtc[i];
3302 stats->q_errors[i] = hw_stats->qprdc[i];
3306 stats->imissed = total_missed_rx;
3307 stats->ierrors = hw_stats->crcerrs +
3324 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3326 struct ixgbe_hw_stats *stats =
3327 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3329 /* HW registers are cleared on read */
3330 ixgbe_dev_stats_get(dev, NULL);
3332 /* Reset software totals */
3333 memset(stats, 0, sizeof(*stats));
3338 /* This function calculates the number of xstats based on the current config */
3340 ixgbe_xstats_calc_num(void) {
3341 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3342 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3343 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3346 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3347 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3349 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3350 unsigned stat, i, count;
3352 if (xstats_names != NULL) {
3355 /* Note: limit >= cnt_stats checked upstream
3356 * in rte_eth_xstats_names()
3359 /* Extended stats from ixgbe_hw_stats */
3360 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3361 strlcpy(xstats_names[count].name,
3362 rte_ixgbe_stats_strings[i].name,
3363 sizeof(xstats_names[count].name));
3368 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3369 strlcpy(xstats_names[count].name,
3370 rte_ixgbe_macsec_strings[i].name,
3371 sizeof(xstats_names[count].name));
3375 /* RX Priority Stats */
3376 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3377 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3378 snprintf(xstats_names[count].name,
3379 sizeof(xstats_names[count].name),
3380 "rx_priority%u_%s", i,
3381 rte_ixgbe_rxq_strings[stat].name);
3386 /* TX Priority Stats */
3387 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3388 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3389 snprintf(xstats_names[count].name,
3390 sizeof(xstats_names[count].name),
3391 "tx_priority%u_%s", i,
3392 rte_ixgbe_txq_strings[stat].name);
3400 static int ixgbe_dev_xstats_get_names_by_id(
3401 struct rte_eth_dev *dev,
3402 struct rte_eth_xstat_name *xstats_names,
3403 const uint64_t *ids,
3407 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3408 unsigned int stat, i, count;
3410 if (xstats_names != NULL) {
3413 /* Note: limit >= cnt_stats checked upstream
3414 * in rte_eth_xstats_names()
3417 /* Extended stats from ixgbe_hw_stats */
3418 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3419 strlcpy(xstats_names[count].name,
3420 rte_ixgbe_stats_strings[i].name,
3421 sizeof(xstats_names[count].name));
3426 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3427 strlcpy(xstats_names[count].name,
3428 rte_ixgbe_macsec_strings[i].name,
3429 sizeof(xstats_names[count].name));
3433 /* RX Priority Stats */
3434 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3435 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3436 snprintf(xstats_names[count].name,
3437 sizeof(xstats_names[count].name),
3438 "rx_priority%u_%s", i,
3439 rte_ixgbe_rxq_strings[stat].name);
3444 /* TX Priority Stats */
3445 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3446 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3447 snprintf(xstats_names[count].name,
3448 sizeof(xstats_names[count].name),
3449 "tx_priority%u_%s", i,
3450 rte_ixgbe_txq_strings[stat].name);
3459 uint16_t size = ixgbe_xstats_calc_num();
3460 struct rte_eth_xstat_name xstats_names_copy[size];
3462 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3465 for (i = 0; i < limit; i++) {
3466 if (ids[i] >= size) {
3467 PMD_INIT_LOG(ERR, "id value isn't valid");
3470 strcpy(xstats_names[i].name,
3471 xstats_names_copy[ids[i]].name);
3476 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3477 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3481 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3484 if (xstats_names != NULL)
3485 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3486 strlcpy(xstats_names[i].name,
3487 rte_ixgbevf_stats_strings[i].name,
3488 sizeof(xstats_names[i].name));
3489 return IXGBEVF_NB_XSTATS;
3493 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3496 struct ixgbe_hw *hw =
3497 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3498 struct ixgbe_hw_stats *hw_stats =
3499 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3500 struct ixgbe_macsec_stats *macsec_stats =
3501 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3502 dev->data->dev_private);
3503 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3504 unsigned i, stat, count = 0;
3506 count = ixgbe_xstats_calc_num();
3511 total_missed_rx = 0;
3516 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3517 &total_qbrc, &total_qprc, &total_qprdc);
3519 /* If this is a reset xstats is NULL, and we have cleared the
3520 * registers by reading them.
3525 /* Extended stats from ixgbe_hw_stats */
3527 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3528 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3529 rte_ixgbe_stats_strings[i].offset);
3530 xstats[count].id = count;
3535 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3536 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3537 rte_ixgbe_macsec_strings[i].offset);
3538 xstats[count].id = count;
3542 /* RX Priority Stats */
3543 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3544 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3545 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3546 rte_ixgbe_rxq_strings[stat].offset +
3547 (sizeof(uint64_t) * i));
3548 xstats[count].id = count;
3553 /* TX Priority Stats */
3554 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3555 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3556 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3557 rte_ixgbe_txq_strings[stat].offset +
3558 (sizeof(uint64_t) * i));
3559 xstats[count].id = count;
3567 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3568 uint64_t *values, unsigned int n)
3571 struct ixgbe_hw *hw =
3572 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3573 struct ixgbe_hw_stats *hw_stats =
3574 IXGBE_DEV_PRIVATE_TO_STATS(
3575 dev->data->dev_private);
3576 struct ixgbe_macsec_stats *macsec_stats =
3577 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3578 dev->data->dev_private);
3579 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3580 unsigned int i, stat, count = 0;
3582 count = ixgbe_xstats_calc_num();
3584 if (!ids && n < count)
3587 total_missed_rx = 0;
3592 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3593 &total_missed_rx, &total_qbrc, &total_qprc,
3596 /* If this is a reset xstats is NULL, and we have cleared the
3597 * registers by reading them.
3599 if (!ids && !values)
3602 /* Extended stats from ixgbe_hw_stats */
3604 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3605 values[count] = *(uint64_t *)(((char *)hw_stats) +
3606 rte_ixgbe_stats_strings[i].offset);
3611 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3612 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3613 rte_ixgbe_macsec_strings[i].offset);
3617 /* RX Priority Stats */
3618 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3619 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3621 *(uint64_t *)(((char *)hw_stats) +
3622 rte_ixgbe_rxq_strings[stat].offset +
3623 (sizeof(uint64_t) * i));
3628 /* TX Priority Stats */
3629 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3630 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3632 *(uint64_t *)(((char *)hw_stats) +
3633 rte_ixgbe_txq_strings[stat].offset +
3634 (sizeof(uint64_t) * i));
3642 uint16_t size = ixgbe_xstats_calc_num();
3643 uint64_t values_copy[size];
3645 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3647 for (i = 0; i < n; i++) {
3648 if (ids[i] >= size) {
3649 PMD_INIT_LOG(ERR, "id value isn't valid");
3652 values[i] = values_copy[ids[i]];
3658 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3660 struct ixgbe_hw_stats *stats =
3661 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3662 struct ixgbe_macsec_stats *macsec_stats =
3663 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3664 dev->data->dev_private);
3666 unsigned count = ixgbe_xstats_calc_num();
3668 /* HW registers are cleared on read */
3669 ixgbe_dev_xstats_get(dev, NULL, count);
3671 /* Reset software totals */
3672 memset(stats, 0, sizeof(*stats));
3673 memset(macsec_stats, 0, sizeof(*macsec_stats));
3679 ixgbevf_update_stats(struct rte_eth_dev *dev)
3681 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3682 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3683 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3685 /* Good Rx packet, include VF loopback */
3686 UPDATE_VF_STAT(IXGBE_VFGPRC,
3687 hw_stats->last_vfgprc, hw_stats->vfgprc);
3689 /* Good Rx octets, include VF loopback */
3690 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3691 hw_stats->last_vfgorc, hw_stats->vfgorc);
3693 /* Good Tx packet, include VF loopback */
3694 UPDATE_VF_STAT(IXGBE_VFGPTC,
3695 hw_stats->last_vfgptc, hw_stats->vfgptc);
3697 /* Good Tx octets, include VF loopback */
3698 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3699 hw_stats->last_vfgotc, hw_stats->vfgotc);
3701 /* Rx Multicst Packet */
3702 UPDATE_VF_STAT(IXGBE_VFMPRC,
3703 hw_stats->last_vfmprc, hw_stats->vfmprc);
3707 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3710 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3711 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3714 if (n < IXGBEVF_NB_XSTATS)
3715 return IXGBEVF_NB_XSTATS;
3717 ixgbevf_update_stats(dev);
3722 /* Extended stats */
3723 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3725 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3726 rte_ixgbevf_stats_strings[i].offset);
3729 return IXGBEVF_NB_XSTATS;
3733 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3735 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3736 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3738 ixgbevf_update_stats(dev);
3743 stats->ipackets = hw_stats->vfgprc;
3744 stats->ibytes = hw_stats->vfgorc;
3745 stats->opackets = hw_stats->vfgptc;
3746 stats->obytes = hw_stats->vfgotc;
3751 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3753 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3754 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3756 /* Sync HW register to the last stats */
3757 ixgbevf_dev_stats_get(dev, NULL);
3759 /* reset HW current stats*/
3760 hw_stats->vfgprc = 0;
3761 hw_stats->vfgorc = 0;
3762 hw_stats->vfgptc = 0;
3763 hw_stats->vfgotc = 0;
3769 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3771 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3772 u16 eeprom_verh, eeprom_verl;
3776 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3777 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3779 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3780 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3782 ret += 1; /* add the size of '\0' */
3783 if (fw_size < (u32)ret)
3790 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3792 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3793 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3794 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3796 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3797 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3798 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3800 * When DCB/VT is off, maximum number of queues changes,
3801 * except for 82598EB, which remains constant.
3803 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3804 hw->mac.type != ixgbe_mac_82598EB)
3805 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3807 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3808 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3809 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3810 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3811 dev_info->max_vfs = pci_dev->max_vfs;
3812 if (hw->mac.type == ixgbe_mac_82598EB)
3813 dev_info->max_vmdq_pools = ETH_16_POOLS;
3815 dev_info->max_vmdq_pools = ETH_64_POOLS;
3816 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3817 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3818 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3819 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3820 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3821 dev_info->rx_queue_offload_capa);
3822 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3823 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3825 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3827 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3828 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3829 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3831 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3836 dev_info->default_txconf = (struct rte_eth_txconf) {
3838 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3839 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3840 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3842 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3843 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3847 dev_info->rx_desc_lim = rx_desc_lim;
3848 dev_info->tx_desc_lim = tx_desc_lim;
3850 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3851 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3852 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3854 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3855 if (hw->mac.type == ixgbe_mac_X540 ||
3856 hw->mac.type == ixgbe_mac_X540_vf ||
3857 hw->mac.type == ixgbe_mac_X550 ||
3858 hw->mac.type == ixgbe_mac_X550_vf) {
3859 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3861 if (hw->mac.type == ixgbe_mac_X550) {
3862 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3863 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3866 /* Driver-preferred Rx/Tx parameters */
3867 dev_info->default_rxportconf.burst_size = 32;
3868 dev_info->default_txportconf.burst_size = 32;
3869 dev_info->default_rxportconf.nb_queues = 1;
3870 dev_info->default_txportconf.nb_queues = 1;
3871 dev_info->default_rxportconf.ring_size = 256;
3872 dev_info->default_txportconf.ring_size = 256;
3877 static const uint32_t *
3878 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3880 static const uint32_t ptypes[] = {
3881 /* For non-vec functions,
3882 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3883 * for vec functions,
3884 * refers to _recv_raw_pkts_vec().
3888 RTE_PTYPE_L3_IPV4_EXT,
3890 RTE_PTYPE_L3_IPV6_EXT,
3894 RTE_PTYPE_TUNNEL_IP,
3895 RTE_PTYPE_INNER_L3_IPV6,
3896 RTE_PTYPE_INNER_L3_IPV6_EXT,
3897 RTE_PTYPE_INNER_L4_TCP,
3898 RTE_PTYPE_INNER_L4_UDP,
3902 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3903 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3904 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3905 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3908 #if defined(RTE_ARCH_X86)
3909 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3910 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3917 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3918 struct rte_eth_dev_info *dev_info)
3920 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3921 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3923 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3924 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3925 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3926 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3927 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3928 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3929 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3930 dev_info->max_vfs = pci_dev->max_vfs;
3931 if (hw->mac.type == ixgbe_mac_82598EB)
3932 dev_info->max_vmdq_pools = ETH_16_POOLS;
3934 dev_info->max_vmdq_pools = ETH_64_POOLS;
3935 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3936 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3937 dev_info->rx_queue_offload_capa);
3938 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3939 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3940 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3941 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3942 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3944 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3946 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3947 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3948 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3950 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3955 dev_info->default_txconf = (struct rte_eth_txconf) {
3957 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3958 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3959 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3961 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3962 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3966 dev_info->rx_desc_lim = rx_desc_lim;
3967 dev_info->tx_desc_lim = tx_desc_lim;
3973 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3974 int *link_up, int wait_to_complete)
3976 struct ixgbe_adapter *adapter = container_of(hw,
3977 struct ixgbe_adapter, hw);
3978 struct ixgbe_mbx_info *mbx = &hw->mbx;
3979 struct ixgbe_mac_info *mac = &hw->mac;
3980 uint32_t links_reg, in_msg;
3983 /* If we were hit with a reset drop the link */
3984 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3985 mac->get_link_status = true;
3987 if (!mac->get_link_status)
3990 /* if link status is down no point in checking to see if pf is up */
3991 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3992 if (!(links_reg & IXGBE_LINKS_UP))
3995 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3996 * before the link status is correct
3998 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4001 for (i = 0; i < 5; i++) {
4003 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4005 if (!(links_reg & IXGBE_LINKS_UP))
4010 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4011 case IXGBE_LINKS_SPEED_10G_82599:
4012 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4013 if (hw->mac.type >= ixgbe_mac_X550) {
4014 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4015 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4018 case IXGBE_LINKS_SPEED_1G_82599:
4019 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4021 case IXGBE_LINKS_SPEED_100_82599:
4022 *speed = IXGBE_LINK_SPEED_100_FULL;
4023 if (hw->mac.type == ixgbe_mac_X550) {
4024 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4025 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4028 case IXGBE_LINKS_SPEED_10_X550EM_A:
4029 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4030 /* Since Reserved in older MAC's */
4031 if (hw->mac.type >= ixgbe_mac_X550)
4032 *speed = IXGBE_LINK_SPEED_10_FULL;
4035 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4038 if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4039 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4040 mac->get_link_status = true;
4042 mac->get_link_status = false;
4047 /* if the read failed it could just be a mailbox collision, best wait
4048 * until we are called again and don't report an error
4050 if (mbx->ops.read(hw, &in_msg, 1, 0))
4053 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4054 /* msg is not CTS and is NACK we must have lost CTS status */
4055 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4056 mac->get_link_status = false;
4060 /* the pf is talking, if we timed out in the past we reinit */
4061 if (!mbx->timeout) {
4066 /* if we passed all the tests above then the link is up and we no
4067 * longer need to check for link
4069 mac->get_link_status = false;
4072 *link_up = !mac->get_link_status;
4077 ixgbe_dev_setup_link_alarm_handler(void *param)
4079 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4080 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4081 struct ixgbe_interrupt *intr =
4082 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4084 bool autoneg = false;
4086 speed = hw->phy.autoneg_advertised;
4088 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4090 ixgbe_setup_link(hw, speed, true);
4092 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4095 /* return 0 means link status changed, -1 means not changed */
4097 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4098 int wait_to_complete, int vf)
4100 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4101 struct rte_eth_link link;
4102 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4103 struct ixgbe_interrupt *intr =
4104 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4109 memset(&link, 0, sizeof(link));
4110 link.link_status = ETH_LINK_DOWN;
4111 link.link_speed = ETH_SPEED_NUM_NONE;
4112 link.link_duplex = ETH_LINK_HALF_DUPLEX;
4113 link.link_autoneg = ETH_LINK_AUTONEG;
4115 hw->mac.get_link_status = true;
4117 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4118 return rte_eth_linkstatus_set(dev, &link);
4120 /* check if it needs to wait to complete, if lsc interrupt is enabled */
4121 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4125 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4127 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4130 link.link_speed = ETH_SPEED_NUM_100M;
4131 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4132 return rte_eth_linkstatus_set(dev, &link);
4136 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4137 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4138 rte_eal_alarm_set(10,
4139 ixgbe_dev_setup_link_alarm_handler, dev);
4141 return rte_eth_linkstatus_set(dev, &link);
4144 link.link_status = ETH_LINK_UP;
4145 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4147 switch (link_speed) {
4149 case IXGBE_LINK_SPEED_UNKNOWN:
4150 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4151 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4152 link.link_speed = ETH_SPEED_NUM_10M;
4154 link.link_speed = ETH_SPEED_NUM_100M;
4157 case IXGBE_LINK_SPEED_100_FULL:
4158 link.link_speed = ETH_SPEED_NUM_100M;
4161 case IXGBE_LINK_SPEED_1GB_FULL:
4162 link.link_speed = ETH_SPEED_NUM_1G;
4165 case IXGBE_LINK_SPEED_2_5GB_FULL:
4166 link.link_speed = ETH_SPEED_NUM_2_5G;
4169 case IXGBE_LINK_SPEED_5GB_FULL:
4170 link.link_speed = ETH_SPEED_NUM_5G;
4173 case IXGBE_LINK_SPEED_10GB_FULL:
4174 link.link_speed = ETH_SPEED_NUM_10G;
4178 return rte_eth_linkstatus_set(dev, &link);
4182 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4184 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4188 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4190 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4194 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4196 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4199 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4200 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4201 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4207 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4209 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4212 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4213 fctrl &= (~IXGBE_FCTRL_UPE);
4214 if (dev->data->all_multicast == 1)
4215 fctrl |= IXGBE_FCTRL_MPE;
4217 fctrl &= (~IXGBE_FCTRL_MPE);
4218 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4224 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4226 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4229 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4230 fctrl |= IXGBE_FCTRL_MPE;
4231 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4237 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4239 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4242 if (dev->data->promiscuous == 1)
4243 return 0; /* must remain in all_multicast mode */
4245 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4246 fctrl &= (~IXGBE_FCTRL_MPE);
4247 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4253 * It clears the interrupt causes and enables the interrupt.
4254 * It will be called once only during nic initialized.
4257 * Pointer to struct rte_eth_dev.
4259 * Enable or Disable.
4262 * - On success, zero.
4263 * - On failure, a negative value.
4266 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4268 struct ixgbe_interrupt *intr =
4269 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4271 ixgbe_dev_link_status_print(dev);
4273 intr->mask |= IXGBE_EICR_LSC;
4275 intr->mask &= ~IXGBE_EICR_LSC;
4281 * It clears the interrupt causes and enables the interrupt.
4282 * It will be called once only during nic initialized.
4285 * Pointer to struct rte_eth_dev.
4288 * - On success, zero.
4289 * - On failure, a negative value.
4292 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4294 struct ixgbe_interrupt *intr =
4295 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4297 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4303 * It clears the interrupt causes and enables the interrupt.
4304 * It will be called once only during nic initialized.
4307 * Pointer to struct rte_eth_dev.
4310 * - On success, zero.
4311 * - On failure, a negative value.
4314 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4316 struct ixgbe_interrupt *intr =
4317 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4319 intr->mask |= IXGBE_EICR_LINKSEC;
4325 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4328 * Pointer to struct rte_eth_dev.
4331 * - On success, zero.
4332 * - On failure, a negative value.
4335 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4338 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4339 struct ixgbe_interrupt *intr =
4340 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4342 /* clear all cause mask */
4343 ixgbe_disable_intr(hw);
4345 /* read-on-clear nic registers here */
4346 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4347 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4351 /* set flag for async link update */
4352 if (eicr & IXGBE_EICR_LSC)
4353 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4355 if (eicr & IXGBE_EICR_MAILBOX)
4356 intr->flags |= IXGBE_FLAG_MAILBOX;
4358 if (eicr & IXGBE_EICR_LINKSEC)
4359 intr->flags |= IXGBE_FLAG_MACSEC;
4361 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4362 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4363 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4364 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4370 * It gets and then prints the link status.
4373 * Pointer to struct rte_eth_dev.
4376 * - On success, zero.
4377 * - On failure, a negative value.
4380 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4382 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4383 struct rte_eth_link link;
4385 rte_eth_linkstatus_get(dev, &link);
4387 if (link.link_status) {
4388 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4389 (int)(dev->data->port_id),
4390 (unsigned)link.link_speed,
4391 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4392 "full-duplex" : "half-duplex");
4394 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4395 (int)(dev->data->port_id));
4397 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4398 pci_dev->addr.domain,
4400 pci_dev->addr.devid,
4401 pci_dev->addr.function);
4405 * It executes link_update after knowing an interrupt occurred.
4408 * Pointer to struct rte_eth_dev.
4411 * - On success, zero.
4412 * - On failure, a negative value.
4415 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4417 struct ixgbe_interrupt *intr =
4418 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4420 struct ixgbe_hw *hw =
4421 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4423 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4425 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4426 ixgbe_pf_mbx_process(dev);
4427 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4430 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4431 ixgbe_handle_lasi(hw);
4432 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4435 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4436 struct rte_eth_link link;
4438 /* get the link status before link update, for predicting later */
4439 rte_eth_linkstatus_get(dev, &link);
4441 ixgbe_dev_link_update(dev, 0);
4444 if (!link.link_status)
4445 /* handle it 1 sec later, wait it being stable */
4446 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4447 /* likely to down */
4449 /* handle it 4 sec later, wait it being stable */
4450 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4452 ixgbe_dev_link_status_print(dev);
4453 if (rte_eal_alarm_set(timeout * 1000,
4454 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4455 PMD_DRV_LOG(ERR, "Error setting alarm");
4457 /* remember original mask */
4458 intr->mask_original = intr->mask;
4459 /* only disable lsc interrupt */
4460 intr->mask &= ~IXGBE_EIMS_LSC;
4464 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4465 ixgbe_enable_intr(dev);
4471 * Interrupt handler which shall be registered for alarm callback for delayed
4472 * handling specific interrupt to wait for the stable nic state. As the
4473 * NIC interrupt state is not stable for ixgbe after link is just down,
4474 * it needs to wait 4 seconds to get the stable status.
4477 * Pointer to interrupt handle.
4479 * The address of parameter (struct rte_eth_dev *) regsitered before.
4485 ixgbe_dev_interrupt_delayed_handler(void *param)
4487 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4488 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4489 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4490 struct ixgbe_interrupt *intr =
4491 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4492 struct ixgbe_hw *hw =
4493 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4496 ixgbe_disable_intr(hw);
4498 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4499 if (eicr & IXGBE_EICR_MAILBOX)
4500 ixgbe_pf_mbx_process(dev);
4502 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4503 ixgbe_handle_lasi(hw);
4504 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4507 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4508 ixgbe_dev_link_update(dev, 0);
4509 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4510 ixgbe_dev_link_status_print(dev);
4511 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4515 if (intr->flags & IXGBE_FLAG_MACSEC) {
4516 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4518 intr->flags &= ~IXGBE_FLAG_MACSEC;
4521 /* restore original mask */
4522 intr->mask = intr->mask_original;
4523 intr->mask_original = 0;
4525 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4526 ixgbe_enable_intr(dev);
4527 rte_intr_ack(intr_handle);
4531 * Interrupt handler triggered by NIC for handling
4532 * specific interrupt.
4535 * Pointer to interrupt handle.
4537 * The address of parameter (struct rte_eth_dev *) regsitered before.
4543 ixgbe_dev_interrupt_handler(void *param)
4545 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4547 ixgbe_dev_interrupt_get_status(dev);
4548 ixgbe_dev_interrupt_action(dev);
4552 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4554 struct ixgbe_hw *hw;
4556 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4557 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4561 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4563 struct ixgbe_hw *hw;
4565 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4566 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4570 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4572 struct ixgbe_hw *hw;
4578 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4580 fc_conf->pause_time = hw->fc.pause_time;
4581 fc_conf->high_water = hw->fc.high_water[0];
4582 fc_conf->low_water = hw->fc.low_water[0];
4583 fc_conf->send_xon = hw->fc.send_xon;
4584 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4587 * Return rx_pause status according to actual setting of
4590 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4591 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4597 * Return tx_pause status according to actual setting of
4600 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4601 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4606 if (rx_pause && tx_pause)
4607 fc_conf->mode = RTE_FC_FULL;
4609 fc_conf->mode = RTE_FC_RX_PAUSE;
4611 fc_conf->mode = RTE_FC_TX_PAUSE;
4613 fc_conf->mode = RTE_FC_NONE;
4619 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4621 struct ixgbe_hw *hw;
4623 uint32_t rx_buf_size;
4624 uint32_t max_high_water;
4626 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4633 PMD_INIT_FUNC_TRACE();
4635 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4636 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4637 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4640 * At least reserve one Ethernet frame for watermark
4641 * high_water/low_water in kilo bytes for ixgbe
4643 max_high_water = (rx_buf_size -
4644 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4645 if ((fc_conf->high_water > max_high_water) ||
4646 (fc_conf->high_water < fc_conf->low_water)) {
4647 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4648 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4652 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4653 hw->fc.pause_time = fc_conf->pause_time;
4654 hw->fc.high_water[0] = fc_conf->high_water;
4655 hw->fc.low_water[0] = fc_conf->low_water;
4656 hw->fc.send_xon = fc_conf->send_xon;
4657 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4659 err = ixgbe_fc_enable(hw);
4661 /* Not negotiated is not an error case */
4662 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4664 /* check if we want to forward MAC frames - driver doesn't have native
4665 * capability to do that, so we'll write the registers ourselves */
4667 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4669 /* set or clear MFLCN.PMCF bit depending on configuration */
4670 if (fc_conf->mac_ctrl_frame_fwd != 0)
4671 mflcn |= IXGBE_MFLCN_PMCF;
4673 mflcn &= ~IXGBE_MFLCN_PMCF;
4675 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4676 IXGBE_WRITE_FLUSH(hw);
4681 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4686 * ixgbe_pfc_enable_generic - Enable flow control
4687 * @hw: pointer to hardware structure
4688 * @tc_num: traffic class number
4689 * Enable flow control according to the current settings.
4692 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4695 uint32_t mflcn_reg, fccfg_reg;
4697 uint32_t fcrtl, fcrth;
4701 /* Validate the water mark configuration */
4702 if (!hw->fc.pause_time) {
4703 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4707 /* Low water mark of zero causes XOFF floods */
4708 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4709 /* High/Low water can not be 0 */
4710 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4711 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4712 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4716 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4717 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4718 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4722 /* Negotiate the fc mode to use */
4723 ixgbe_fc_autoneg(hw);
4725 /* Disable any previous flow control settings */
4726 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4727 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4729 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4730 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4732 switch (hw->fc.current_mode) {
4735 * If the count of enabled RX Priority Flow control >1,
4736 * and the TX pause can not be disabled
4739 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4740 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4741 if (reg & IXGBE_FCRTH_FCEN)
4745 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4747 case ixgbe_fc_rx_pause:
4749 * Rx Flow control is enabled and Tx Flow control is
4750 * disabled by software override. Since there really
4751 * isn't a way to advertise that we are capable of RX
4752 * Pause ONLY, we will advertise that we support both
4753 * symmetric and asymmetric Rx PAUSE. Later, we will
4754 * disable the adapter's ability to send PAUSE frames.
4756 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4758 * If the count of enabled RX Priority Flow control >1,
4759 * and the TX pause can not be disabled
4762 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4763 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4764 if (reg & IXGBE_FCRTH_FCEN)
4768 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4770 case ixgbe_fc_tx_pause:
4772 * Tx Flow control is enabled, and Rx Flow control is
4773 * disabled by software override.
4775 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4778 /* Flow control (both Rx and Tx) is enabled by SW override. */
4779 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4780 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4783 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4784 ret_val = IXGBE_ERR_CONFIG;
4788 /* Set 802.3x based flow control settings. */
4789 mflcn_reg |= IXGBE_MFLCN_DPF;
4790 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4791 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4793 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4794 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4795 hw->fc.high_water[tc_num]) {
4796 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4797 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4798 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4800 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4802 * In order to prevent Tx hangs when the internal Tx
4803 * switch is enabled we must set the high water mark
4804 * to the maximum FCRTH value. This allows the Tx
4805 * switch to function even under heavy Rx workloads.
4807 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4809 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4811 /* Configure pause time (2 TCs per register) */
4812 reg = hw->fc.pause_time * 0x00010001;
4813 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4814 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4816 /* Configure flow control refresh threshold value */
4817 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4824 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4826 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4827 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4829 if (hw->mac.type != ixgbe_mac_82598EB) {
4830 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4836 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4839 uint32_t rx_buf_size;
4840 uint32_t max_high_water;
4842 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4843 struct ixgbe_hw *hw =
4844 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4845 struct ixgbe_dcb_config *dcb_config =
4846 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4848 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4855 PMD_INIT_FUNC_TRACE();
4857 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4858 tc_num = map[pfc_conf->priority];
4859 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4860 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4862 * At least reserve one Ethernet frame for watermark
4863 * high_water/low_water in kilo bytes for ixgbe
4865 max_high_water = (rx_buf_size -
4866 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4867 if ((pfc_conf->fc.high_water > max_high_water) ||
4868 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4869 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4870 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4874 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4875 hw->fc.pause_time = pfc_conf->fc.pause_time;
4876 hw->fc.send_xon = pfc_conf->fc.send_xon;
4877 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4878 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4880 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4882 /* Not negotiated is not an error case */
4883 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4886 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4891 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4892 struct rte_eth_rss_reta_entry64 *reta_conf,
4895 uint16_t i, sp_reta_size;
4898 uint16_t idx, shift;
4899 struct ixgbe_adapter *adapter = dev->data->dev_private;
4900 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4903 PMD_INIT_FUNC_TRACE();
4905 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4906 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4911 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4912 if (reta_size != sp_reta_size) {
4913 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4914 "(%d) doesn't match the number hardware can supported "
4915 "(%d)", reta_size, sp_reta_size);
4919 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4920 idx = i / RTE_RETA_GROUP_SIZE;
4921 shift = i % RTE_RETA_GROUP_SIZE;
4922 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4926 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4927 if (mask == IXGBE_4_BIT_MASK)
4930 r = IXGBE_READ_REG(hw, reta_reg);
4931 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4932 if (mask & (0x1 << j))
4933 reta |= reta_conf[idx].reta[shift + j] <<
4936 reta |= r & (IXGBE_8_BIT_MASK <<
4939 IXGBE_WRITE_REG(hw, reta_reg, reta);
4941 adapter->rss_reta_updated = 1;
4947 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4948 struct rte_eth_rss_reta_entry64 *reta_conf,
4951 uint16_t i, sp_reta_size;
4954 uint16_t idx, shift;
4955 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4958 PMD_INIT_FUNC_TRACE();
4959 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4960 if (reta_size != sp_reta_size) {
4961 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4962 "(%d) doesn't match the number hardware can supported "
4963 "(%d)", reta_size, sp_reta_size);
4967 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4968 idx = i / RTE_RETA_GROUP_SIZE;
4969 shift = i % RTE_RETA_GROUP_SIZE;
4970 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4975 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4976 reta = IXGBE_READ_REG(hw, reta_reg);
4977 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4978 if (mask & (0x1 << j))
4979 reta_conf[idx].reta[shift + j] =
4980 ((reta >> (CHAR_BIT * j)) &
4989 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
4990 uint32_t index, uint32_t pool)
4992 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4993 uint32_t enable_addr = 1;
4995 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5000 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5002 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5004 ixgbe_clear_rar(hw, index);
5008 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5010 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5012 ixgbe_remove_rar(dev, 0);
5013 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5019 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5021 if (strcmp(dev->device->driver->name, drv->driver.name))
5028 is_ixgbe_supported(struct rte_eth_dev *dev)
5030 return is_device_supported(dev, &rte_ixgbe_pmd);
5034 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5038 struct ixgbe_hw *hw;
5039 struct rte_eth_dev_info dev_info;
5040 uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5041 struct rte_eth_dev_data *dev_data = dev->data;
5044 ret = ixgbe_dev_info_get(dev, &dev_info);
5048 /* check that mtu is within the allowed range */
5049 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5052 /* If device is started, refuse mtu that requires the support of
5053 * scattered packets when this feature has not been enabled before.
5055 if (dev_data->dev_started && !dev_data->scattered_rx &&
5056 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5057 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5058 PMD_INIT_LOG(ERR, "Stop port first.");
5062 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5063 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5065 /* switch to jumbo mode if needed */
5066 if (frame_size > RTE_ETHER_MAX_LEN) {
5067 dev->data->dev_conf.rxmode.offloads |=
5068 DEV_RX_OFFLOAD_JUMBO_FRAME;
5069 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5071 dev->data->dev_conf.rxmode.offloads &=
5072 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5073 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5075 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5077 /* update max frame size */
5078 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5080 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5081 maxfrs &= 0x0000FFFF;
5082 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5083 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5089 * Virtual Function operations
5092 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5094 struct ixgbe_interrupt *intr =
5095 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5096 struct ixgbe_hw *hw =
5097 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5099 PMD_INIT_FUNC_TRACE();
5101 /* Clear interrupt mask to stop from interrupts being generated */
5102 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5104 IXGBE_WRITE_FLUSH(hw);
5106 /* Clear mask value. */
5111 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5113 struct ixgbe_interrupt *intr =
5114 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5115 struct ixgbe_hw *hw =
5116 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5118 PMD_INIT_FUNC_TRACE();
5120 /* VF enable interrupt autoclean */
5121 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5122 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5123 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5125 IXGBE_WRITE_FLUSH(hw);
5127 /* Save IXGBE_VTEIMS value to mask. */
5128 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5132 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5134 struct rte_eth_conf *conf = &dev->data->dev_conf;
5135 struct ixgbe_adapter *adapter = dev->data->dev_private;
5137 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5138 dev->data->port_id);
5141 * VF has no ability to enable/disable HW CRC
5142 * Keep the persistent behavior the same as Host PF
5144 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5145 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5146 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5147 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5150 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5151 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5152 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5157 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5158 * allocation or vector Rx preconditions we will reset it.
5160 adapter->rx_bulk_alloc_allowed = true;
5161 adapter->rx_vec_allowed = true;
5167 ixgbevf_dev_start(struct rte_eth_dev *dev)
5169 struct ixgbe_hw *hw =
5170 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5171 uint32_t intr_vector = 0;
5172 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5173 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5177 PMD_INIT_FUNC_TRACE();
5179 /* Stop the link setup handler before resetting the HW. */
5180 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5182 err = hw->mac.ops.reset_hw(hw);
5184 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5187 hw->mac.get_link_status = true;
5189 /* negotiate mailbox API version to use with the PF. */
5190 ixgbevf_negotiate_api(hw);
5192 ixgbevf_dev_tx_init(dev);
5194 /* This can fail when allocating mbufs for descriptor rings */
5195 err = ixgbevf_dev_rx_init(dev);
5197 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5198 ixgbe_dev_clear_queues(dev);
5203 ixgbevf_set_vfta_all(dev, 1);
5206 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5207 ETH_VLAN_EXTEND_MASK;
5208 err = ixgbevf_vlan_offload_config(dev, mask);
5210 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5211 ixgbe_dev_clear_queues(dev);
5215 ixgbevf_dev_rxtx_start(dev);
5217 /* check and configure queue intr-vector mapping */
5218 if (rte_intr_cap_multiple(intr_handle) &&
5219 dev->data->dev_conf.intr_conf.rxq) {
5220 /* According to datasheet, only vector 0/1/2 can be used,
5221 * now only one vector is used for Rx queue
5224 if (rte_intr_efd_enable(intr_handle, intr_vector))
5228 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5229 intr_handle->intr_vec =
5230 rte_zmalloc("intr_vec",
5231 dev->data->nb_rx_queues * sizeof(int), 0);
5232 if (intr_handle->intr_vec == NULL) {
5233 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5234 " intr_vec", dev->data->nb_rx_queues);
5238 ixgbevf_configure_msix(dev);
5240 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5241 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5242 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5243 * is not cleared, it will fail when following rte_intr_enable( ) tries
5244 * to map Rx queue interrupt to other VFIO vectors.
5245 * So clear uio/vfio intr/evevnfd first to avoid failure.
5247 rte_intr_disable(intr_handle);
5249 rte_intr_enable(intr_handle);
5251 /* Re-enable interrupt for VF */
5252 ixgbevf_intr_enable(dev);
5255 * Update link status right before return, because it may
5256 * start link configuration process in a separate thread.
5258 ixgbevf_dev_link_update(dev, 0);
5264 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5266 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5267 struct ixgbe_adapter *adapter = dev->data->dev_private;
5268 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5269 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5271 PMD_INIT_FUNC_TRACE();
5273 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5275 ixgbevf_intr_disable(dev);
5277 hw->adapter_stopped = 1;
5278 ixgbe_stop_adapter(hw);
5281 * Clear what we set, but we still keep shadow_vfta to
5282 * restore after device starts
5284 ixgbevf_set_vfta_all(dev, 0);
5286 /* Clear stored conf */
5287 dev->data->scattered_rx = 0;
5289 ixgbe_dev_clear_queues(dev);
5291 /* Clean datapath event and queue/vec mapping */
5292 rte_intr_efd_disable(intr_handle);
5293 if (intr_handle->intr_vec != NULL) {
5294 rte_free(intr_handle->intr_vec);
5295 intr_handle->intr_vec = NULL;
5298 adapter->rss_reta_updated = 0;
5302 ixgbevf_dev_close(struct rte_eth_dev *dev)
5304 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5306 PMD_INIT_FUNC_TRACE();
5310 ixgbevf_dev_stop(dev);
5312 ixgbe_dev_free_queues(dev);
5315 * Remove the VF MAC address ro ensure
5316 * that the VF traffic goes to the PF
5317 * after stop, close and detach of the VF
5319 ixgbevf_remove_mac_addr(dev, 0);
5326 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5330 ret = eth_ixgbevf_dev_uninit(dev);
5334 ret = eth_ixgbevf_dev_init(dev);
5339 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5341 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5342 struct ixgbe_vfta *shadow_vfta =
5343 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5344 int i = 0, j = 0, vfta = 0, mask = 1;
5346 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5347 vfta = shadow_vfta->vfta[i];
5350 for (j = 0; j < 32; j++) {
5352 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5362 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5364 struct ixgbe_hw *hw =
5365 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5366 struct ixgbe_vfta *shadow_vfta =
5367 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5368 uint32_t vid_idx = 0;
5369 uint32_t vid_bit = 0;
5372 PMD_INIT_FUNC_TRACE();
5374 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5375 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5377 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5380 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5381 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5383 /* Save what we set and retore it after device reset */
5385 shadow_vfta->vfta[vid_idx] |= vid_bit;
5387 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5393 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5395 struct ixgbe_hw *hw =
5396 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5399 PMD_INIT_FUNC_TRACE();
5401 if (queue >= hw->mac.max_rx_queues)
5404 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5406 ctrl |= IXGBE_RXDCTL_VME;
5408 ctrl &= ~IXGBE_RXDCTL_VME;
5409 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5411 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5415 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5417 struct ixgbe_rx_queue *rxq;
5421 /* VF function only support hw strip feature, others are not support */
5422 if (mask & ETH_VLAN_STRIP_MASK) {
5423 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5424 rxq = dev->data->rx_queues[i];
5425 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5426 ixgbevf_vlan_strip_queue_set(dev, i, on);
5434 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5436 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5438 ixgbevf_vlan_offload_config(dev, mask);
5444 ixgbe_vt_check(struct ixgbe_hw *hw)
5448 /* if Virtualization Technology is enabled */
5449 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5450 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5451 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5459 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5461 uint32_t vector = 0;
5463 switch (hw->mac.mc_filter_type) {
5464 case 0: /* use bits [47:36] of the address */
5465 vector = ((uc_addr->addr_bytes[4] >> 4) |
5466 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5468 case 1: /* use bits [46:35] of the address */
5469 vector = ((uc_addr->addr_bytes[4] >> 3) |
5470 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5472 case 2: /* use bits [45:34] of the address */
5473 vector = ((uc_addr->addr_bytes[4] >> 2) |
5474 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5476 case 3: /* use bits [43:32] of the address */
5477 vector = ((uc_addr->addr_bytes[4]) |
5478 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5480 default: /* Invalid mc_filter_type */
5484 /* vector can only be 12-bits or boundary will be exceeded */
5490 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5491 struct rte_ether_addr *mac_addr, uint8_t on)
5498 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5499 const uint32_t ixgbe_uta_bit_shift = 5;
5500 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5501 const uint32_t bit1 = 0x1;
5503 struct ixgbe_hw *hw =
5504 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5505 struct ixgbe_uta_info *uta_info =
5506 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5508 /* The UTA table only exists on 82599 hardware and newer */
5509 if (hw->mac.type < ixgbe_mac_82599EB)
5512 vector = ixgbe_uta_vector(hw, mac_addr);
5513 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5514 uta_shift = vector & ixgbe_uta_bit_mask;
5516 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5520 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5522 uta_info->uta_in_use++;
5523 reg_val |= (bit1 << uta_shift);
5524 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5526 uta_info->uta_in_use--;
5527 reg_val &= ~(bit1 << uta_shift);
5528 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5531 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5533 if (uta_info->uta_in_use > 0)
5534 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5535 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5537 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5543 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5546 struct ixgbe_hw *hw =
5547 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5548 struct ixgbe_uta_info *uta_info =
5549 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5551 /* The UTA table only exists on 82599 hardware and newer */
5552 if (hw->mac.type < ixgbe_mac_82599EB)
5556 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5557 uta_info->uta_shadow[i] = ~0;
5558 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5561 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5562 uta_info->uta_shadow[i] = 0;
5563 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5571 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5573 uint32_t new_val = orig_val;
5575 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5576 new_val |= IXGBE_VMOLR_AUPE;
5577 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5578 new_val |= IXGBE_VMOLR_ROMPE;
5579 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5580 new_val |= IXGBE_VMOLR_ROPE;
5581 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5582 new_val |= IXGBE_VMOLR_BAM;
5583 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5584 new_val |= IXGBE_VMOLR_MPE;
5589 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5590 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5591 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5592 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5593 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5594 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5595 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5598 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5599 struct rte_eth_mirror_conf *mirror_conf,
5600 uint8_t rule_id, uint8_t on)
5602 uint32_t mr_ctl, vlvf;
5603 uint32_t mp_lsb = 0;
5604 uint32_t mv_msb = 0;
5605 uint32_t mv_lsb = 0;
5606 uint32_t mp_msb = 0;
5609 uint64_t vlan_mask = 0;
5611 const uint8_t pool_mask_offset = 32;
5612 const uint8_t vlan_mask_offset = 32;
5613 const uint8_t dst_pool_offset = 8;
5614 const uint8_t rule_mr_offset = 4;
5615 const uint8_t mirror_rule_mask = 0x0F;
5617 struct ixgbe_mirror_info *mr_info =
5618 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5619 struct ixgbe_hw *hw =
5620 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5621 uint8_t mirror_type = 0;
5623 if (ixgbe_vt_check(hw) < 0)
5626 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5629 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5630 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5631 mirror_conf->rule_type);
5635 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5636 mirror_type |= IXGBE_MRCTL_VLME;
5637 /* Check if vlan id is valid and find conresponding VLAN ID
5640 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5641 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5642 /* search vlan id related pool vlan filter
5645 reg_index = ixgbe_find_vlvf_slot(
5647 mirror_conf->vlan.vlan_id[i],
5651 vlvf = IXGBE_READ_REG(hw,
5652 IXGBE_VLVF(reg_index));
5653 if ((vlvf & IXGBE_VLVF_VIEN) &&
5654 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5655 mirror_conf->vlan.vlan_id[i]))
5656 vlan_mask |= (1ULL << reg_index);
5663 mv_lsb = vlan_mask & 0xFFFFFFFF;
5664 mv_msb = vlan_mask >> vlan_mask_offset;
5666 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5667 mirror_conf->vlan.vlan_mask;
5668 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5669 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5670 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5671 mirror_conf->vlan.vlan_id[i];
5676 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5677 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5678 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5683 * if enable pool mirror, write related pool mask register,if disable
5684 * pool mirror, clear PFMRVM register
5686 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5687 mirror_type |= IXGBE_MRCTL_VPME;
5689 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5690 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5691 mr_info->mr_conf[rule_id].pool_mask =
5692 mirror_conf->pool_mask;
5697 mr_info->mr_conf[rule_id].pool_mask = 0;
5700 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5701 mirror_type |= IXGBE_MRCTL_UPME;
5702 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5703 mirror_type |= IXGBE_MRCTL_DPME;
5705 /* read mirror control register and recalculate it */
5706 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5709 mr_ctl |= mirror_type;
5710 mr_ctl &= mirror_rule_mask;
5711 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5713 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5716 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5717 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5719 /* write mirrror control register */
5720 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5722 /* write pool mirrror control register */
5723 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5724 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5725 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5728 /* write VLAN mirrror control register */
5729 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5730 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5731 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5739 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5742 uint32_t lsb_val = 0;
5743 uint32_t msb_val = 0;
5744 const uint8_t rule_mr_offset = 4;
5746 struct ixgbe_hw *hw =
5747 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5748 struct ixgbe_mirror_info *mr_info =
5749 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5751 if (ixgbe_vt_check(hw) < 0)
5754 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5757 memset(&mr_info->mr_conf[rule_id], 0,
5758 sizeof(struct rte_eth_mirror_conf));
5760 /* clear PFVMCTL register */
5761 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5763 /* clear pool mask register */
5764 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5765 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5767 /* clear vlan mask register */
5768 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5769 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5775 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5777 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5778 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5779 struct ixgbe_interrupt *intr =
5780 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5781 struct ixgbe_hw *hw =
5782 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5783 uint32_t vec = IXGBE_MISC_VEC_ID;
5785 if (rte_intr_allow_others(intr_handle))
5786 vec = IXGBE_RX_VEC_START;
5787 intr->mask |= (1 << vec);
5788 RTE_SET_USED(queue_id);
5789 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5791 rte_intr_ack(intr_handle);
5797 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5799 struct ixgbe_interrupt *intr =
5800 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5801 struct ixgbe_hw *hw =
5802 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5803 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5804 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5805 uint32_t vec = IXGBE_MISC_VEC_ID;
5807 if (rte_intr_allow_others(intr_handle))
5808 vec = IXGBE_RX_VEC_START;
5809 intr->mask &= ~(1 << vec);
5810 RTE_SET_USED(queue_id);
5811 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5817 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5819 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5820 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5822 struct ixgbe_hw *hw =
5823 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5824 struct ixgbe_interrupt *intr =
5825 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5827 if (queue_id < 16) {
5828 ixgbe_disable_intr(hw);
5829 intr->mask |= (1 << queue_id);
5830 ixgbe_enable_intr(dev);
5831 } else if (queue_id < 32) {
5832 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5833 mask &= (1 << queue_id);
5834 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5835 } else if (queue_id < 64) {
5836 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5837 mask &= (1 << (queue_id - 32));
5838 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5840 rte_intr_ack(intr_handle);
5846 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5849 struct ixgbe_hw *hw =
5850 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5851 struct ixgbe_interrupt *intr =
5852 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5854 if (queue_id < 16) {
5855 ixgbe_disable_intr(hw);
5856 intr->mask &= ~(1 << queue_id);
5857 ixgbe_enable_intr(dev);
5858 } else if (queue_id < 32) {
5859 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5860 mask &= ~(1 << queue_id);
5861 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5862 } else if (queue_id < 64) {
5863 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5864 mask &= ~(1 << (queue_id - 32));
5865 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5872 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5873 uint8_t queue, uint8_t msix_vector)
5877 if (direction == -1) {
5879 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5880 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5883 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5885 /* rx or tx cause */
5886 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5887 idx = ((16 * (queue & 1)) + (8 * direction));
5888 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5889 tmp &= ~(0xFF << idx);
5890 tmp |= (msix_vector << idx);
5891 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5896 * set the IVAR registers, mapping interrupt causes to vectors
5898 * pointer to ixgbe_hw struct
5900 * 0 for Rx, 1 for Tx, -1 for other causes
5902 * queue to map the corresponding interrupt to
5904 * the vector to map to the corresponding queue
5907 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5908 uint8_t queue, uint8_t msix_vector)
5912 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5913 if (hw->mac.type == ixgbe_mac_82598EB) {
5914 if (direction == -1)
5916 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5917 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5918 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5919 tmp |= (msix_vector << (8 * (queue & 0x3)));
5920 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5921 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5922 (hw->mac.type == ixgbe_mac_X540) ||
5923 (hw->mac.type == ixgbe_mac_X550) ||
5924 (hw->mac.type == ixgbe_mac_X550EM_x)) {
5925 if (direction == -1) {
5927 idx = ((queue & 1) * 8);
5928 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5929 tmp &= ~(0xFF << idx);
5930 tmp |= (msix_vector << idx);
5931 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5933 /* rx or tx causes */
5934 idx = ((16 * (queue & 1)) + (8 * direction));
5935 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5936 tmp &= ~(0xFF << idx);
5937 tmp |= (msix_vector << idx);
5938 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5944 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5946 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5947 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5948 struct ixgbe_hw *hw =
5949 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5951 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5952 uint32_t base = IXGBE_MISC_VEC_ID;
5954 /* Configure VF other cause ivar */
5955 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5957 /* won't configure msix register if no mapping is done
5958 * between intr vector and event fd.
5960 if (!rte_intr_dp_is_en(intr_handle))
5963 if (rte_intr_allow_others(intr_handle)) {
5964 base = IXGBE_RX_VEC_START;
5965 vector_idx = IXGBE_RX_VEC_START;
5968 /* Configure all RX queues of VF */
5969 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5970 /* Force all queue use vector 0,
5971 * as IXGBE_VF_MAXMSIVECOTR = 1
5973 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5974 intr_handle->intr_vec[q_idx] = vector_idx;
5975 if (vector_idx < base + intr_handle->nb_efd - 1)
5979 /* As RX queue setting above show, all queues use the vector 0.
5980 * Set only the ITR value of IXGBE_MISC_VEC_ID.
5982 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5983 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5984 | IXGBE_EITR_CNT_WDIS);
5988 * Sets up the hardware to properly generate MSI-X interrupts
5990 * board private structure
5993 ixgbe_configure_msix(struct rte_eth_dev *dev)
5995 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5996 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5997 struct ixgbe_hw *hw =
5998 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5999 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6000 uint32_t vec = IXGBE_MISC_VEC_ID;
6004 /* won't configure msix register if no mapping is done
6005 * between intr vector and event fd
6006 * but if misx has been enabled already, need to configure
6007 * auto clean, auto mask and throttling.
6009 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6010 if (!rte_intr_dp_is_en(intr_handle) &&
6011 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6014 if (rte_intr_allow_others(intr_handle))
6015 vec = base = IXGBE_RX_VEC_START;
6017 /* setup GPIE for MSI-x mode */
6018 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6019 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6020 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6021 /* auto clearing and auto setting corresponding bits in EIMS
6022 * when MSI-X interrupt is triggered
6024 if (hw->mac.type == ixgbe_mac_82598EB) {
6025 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6027 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6028 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6030 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6032 /* Populate the IVAR table and set the ITR values to the
6033 * corresponding register.
6035 if (rte_intr_dp_is_en(intr_handle)) {
6036 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6038 /* by default, 1:1 mapping */
6039 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6040 intr_handle->intr_vec[queue_id] = vec;
6041 if (vec < base + intr_handle->nb_efd - 1)
6045 switch (hw->mac.type) {
6046 case ixgbe_mac_82598EB:
6047 ixgbe_set_ivar_map(hw, -1,
6048 IXGBE_IVAR_OTHER_CAUSES_INDEX,
6051 case ixgbe_mac_82599EB:
6052 case ixgbe_mac_X540:
6053 case ixgbe_mac_X550:
6054 case ixgbe_mac_X550EM_x:
6055 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6061 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6062 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6063 | IXGBE_EITR_CNT_WDIS);
6065 /* set up to autoclear timer, and the vectors */
6066 mask = IXGBE_EIMS_ENABLE_MASK;
6067 mask &= ~(IXGBE_EIMS_OTHER |
6068 IXGBE_EIMS_MAILBOX |
6071 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6075 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6076 uint16_t queue_idx, uint16_t tx_rate)
6078 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6079 struct rte_eth_rxmode *rxmode;
6080 uint32_t rf_dec, rf_int;
6082 uint16_t link_speed = dev->data->dev_link.link_speed;
6084 if (queue_idx >= hw->mac.max_tx_queues)
6088 /* Calculate the rate factor values to set */
6089 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6090 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6091 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6093 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6094 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6095 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6096 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6101 rxmode = &dev->data->dev_conf.rxmode;
6103 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6104 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6107 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6108 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6109 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6110 IXGBE_MMW_SIZE_JUMBO_FRAME);
6112 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6113 IXGBE_MMW_SIZE_DEFAULT);
6115 /* Set RTTBCNRC of queue X */
6116 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6117 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6118 IXGBE_WRITE_FLUSH(hw);
6124 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6125 __attribute__((unused)) uint32_t index,
6126 __attribute__((unused)) uint32_t pool)
6128 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6132 * On a 82599 VF, adding again the same MAC addr is not an idempotent
6133 * operation. Trap this case to avoid exhausting the [very limited]
6134 * set of PF resources used to store VF MAC addresses.
6136 if (memcmp(hw->mac.perm_addr, mac_addr,
6137 sizeof(struct rte_ether_addr)) == 0)
6139 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6141 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6142 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6143 mac_addr->addr_bytes[0],
6144 mac_addr->addr_bytes[1],
6145 mac_addr->addr_bytes[2],
6146 mac_addr->addr_bytes[3],
6147 mac_addr->addr_bytes[4],
6148 mac_addr->addr_bytes[5],
6154 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6156 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6157 struct rte_ether_addr *perm_addr =
6158 (struct rte_ether_addr *)hw->mac.perm_addr;
6159 struct rte_ether_addr *mac_addr;
6164 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6165 * not support the deletion of a given MAC address.
6166 * Instead, it imposes to delete all MAC addresses, then to add again
6167 * all MAC addresses with the exception of the one to be deleted.
6169 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6172 * Add again all MAC addresses, with the exception of the deleted one
6173 * and of the permanent MAC address.
6175 for (i = 0, mac_addr = dev->data->mac_addrs;
6176 i < hw->mac.num_rar_entries; i++, mac_addr++) {
6177 /* Skip the deleted MAC address */
6180 /* Skip NULL MAC addresses */
6181 if (rte_is_zero_ether_addr(mac_addr))
6183 /* Skip the permanent MAC address */
6184 if (memcmp(perm_addr, mac_addr,
6185 sizeof(struct rte_ether_addr)) == 0)
6187 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6190 "Adding again MAC address "
6191 "%02x:%02x:%02x:%02x:%02x:%02x failed "
6193 mac_addr->addr_bytes[0],
6194 mac_addr->addr_bytes[1],
6195 mac_addr->addr_bytes[2],
6196 mac_addr->addr_bytes[3],
6197 mac_addr->addr_bytes[4],
6198 mac_addr->addr_bytes[5],
6204 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6205 struct rte_ether_addr *addr)
6207 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6209 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6215 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6216 struct rte_eth_syn_filter *filter,
6219 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6220 struct ixgbe_filter_info *filter_info =
6221 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6225 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6228 syn_info = filter_info->syn_info;
6231 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6233 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6234 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6236 if (filter->hig_pri)
6237 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6239 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6241 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6242 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6244 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6247 filter_info->syn_info = synqf;
6248 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6249 IXGBE_WRITE_FLUSH(hw);
6254 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6255 struct rte_eth_syn_filter *filter)
6257 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6258 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6260 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6261 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6262 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6269 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6270 enum rte_filter_op filter_op,
6273 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6276 MAC_TYPE_FILTER_SUP(hw->mac.type);
6278 if (filter_op == RTE_ETH_FILTER_NOP)
6282 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6287 switch (filter_op) {
6288 case RTE_ETH_FILTER_ADD:
6289 ret = ixgbe_syn_filter_set(dev,
6290 (struct rte_eth_syn_filter *)arg,
6293 case RTE_ETH_FILTER_DELETE:
6294 ret = ixgbe_syn_filter_set(dev,
6295 (struct rte_eth_syn_filter *)arg,
6298 case RTE_ETH_FILTER_GET:
6299 ret = ixgbe_syn_filter_get(dev,
6300 (struct rte_eth_syn_filter *)arg);
6303 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6312 static inline enum ixgbe_5tuple_protocol
6313 convert_protocol_type(uint8_t protocol_value)
6315 if (protocol_value == IPPROTO_TCP)
6316 return IXGBE_FILTER_PROTOCOL_TCP;
6317 else if (protocol_value == IPPROTO_UDP)
6318 return IXGBE_FILTER_PROTOCOL_UDP;
6319 else if (protocol_value == IPPROTO_SCTP)
6320 return IXGBE_FILTER_PROTOCOL_SCTP;
6322 return IXGBE_FILTER_PROTOCOL_NONE;
6325 /* inject a 5-tuple filter to HW */
6327 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6328 struct ixgbe_5tuple_filter *filter)
6330 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6332 uint32_t ftqf, sdpqf;
6333 uint32_t l34timir = 0;
6334 uint8_t mask = 0xff;
6338 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6339 IXGBE_SDPQF_DSTPORT_SHIFT);
6340 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6342 ftqf = (uint32_t)(filter->filter_info.proto &
6343 IXGBE_FTQF_PROTOCOL_MASK);
6344 ftqf |= (uint32_t)((filter->filter_info.priority &
6345 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6346 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6347 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6348 if (filter->filter_info.dst_ip_mask == 0)
6349 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6350 if (filter->filter_info.src_port_mask == 0)
6351 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6352 if (filter->filter_info.dst_port_mask == 0)
6353 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6354 if (filter->filter_info.proto_mask == 0)
6355 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6356 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6357 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6358 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6360 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6361 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6362 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6363 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6365 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6366 l34timir |= (uint32_t)(filter->queue <<
6367 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6368 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6372 * add a 5tuple filter
6375 * dev: Pointer to struct rte_eth_dev.
6376 * index: the index the filter allocates.
6377 * filter: ponter to the filter that will be added.
6378 * rx_queue: the queue id the filter assigned to.
6381 * - On success, zero.
6382 * - On failure, a negative value.
6385 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6386 struct ixgbe_5tuple_filter *filter)
6388 struct ixgbe_filter_info *filter_info =
6389 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6393 * look for an unused 5tuple filter index,
6394 * and insert the filter to list.
6396 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6397 idx = i / (sizeof(uint32_t) * NBBY);
6398 shift = i % (sizeof(uint32_t) * NBBY);
6399 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6400 filter_info->fivetuple_mask[idx] |= 1 << shift;
6402 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6408 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6409 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6413 ixgbe_inject_5tuple_filter(dev, filter);
6419 * remove a 5tuple filter
6422 * dev: Pointer to struct rte_eth_dev.
6423 * filter: the pointer of the filter will be removed.
6426 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6427 struct ixgbe_5tuple_filter *filter)
6429 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6430 struct ixgbe_filter_info *filter_info =
6431 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6432 uint16_t index = filter->index;
6434 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6435 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6436 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6439 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6440 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6441 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6442 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6443 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6447 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6449 struct ixgbe_hw *hw;
6450 uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6451 struct rte_eth_dev_data *dev_data = dev->data;
6453 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6455 if (mtu < RTE_ETHER_MIN_MTU ||
6456 max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6459 /* If device is started, refuse mtu that requires the support of
6460 * scattered packets when this feature has not been enabled before.
6462 if (dev_data->dev_started && !dev_data->scattered_rx &&
6463 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6464 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6465 PMD_INIT_LOG(ERR, "Stop port first.");
6470 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6471 * request of the version 2.0 of the mailbox API.
6472 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6473 * of the mailbox API.
6474 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6475 * prior to 3.11.33 which contains the following change:
6476 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6478 ixgbevf_rlpml_set_vf(hw, max_frame);
6480 /* update max frame size */
6481 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6485 static inline struct ixgbe_5tuple_filter *
6486 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6487 struct ixgbe_5tuple_filter_info *key)
6489 struct ixgbe_5tuple_filter *it;
6491 TAILQ_FOREACH(it, filter_list, entries) {
6492 if (memcmp(key, &it->filter_info,
6493 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6500 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6502 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6503 struct ixgbe_5tuple_filter_info *filter_info)
6505 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6506 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6507 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6510 switch (filter->dst_ip_mask) {
6512 filter_info->dst_ip_mask = 0;
6513 filter_info->dst_ip = filter->dst_ip;
6516 filter_info->dst_ip_mask = 1;
6519 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6523 switch (filter->src_ip_mask) {
6525 filter_info->src_ip_mask = 0;
6526 filter_info->src_ip = filter->src_ip;
6529 filter_info->src_ip_mask = 1;
6532 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6536 switch (filter->dst_port_mask) {
6538 filter_info->dst_port_mask = 0;
6539 filter_info->dst_port = filter->dst_port;
6542 filter_info->dst_port_mask = 1;
6545 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6549 switch (filter->src_port_mask) {
6551 filter_info->src_port_mask = 0;
6552 filter_info->src_port = filter->src_port;
6555 filter_info->src_port_mask = 1;
6558 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6562 switch (filter->proto_mask) {
6564 filter_info->proto_mask = 0;
6565 filter_info->proto =
6566 convert_protocol_type(filter->proto);
6569 filter_info->proto_mask = 1;
6572 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6576 filter_info->priority = (uint8_t)filter->priority;
6581 * add or delete a ntuple filter
6584 * dev: Pointer to struct rte_eth_dev.
6585 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6586 * add: if true, add filter, if false, remove filter
6589 * - On success, zero.
6590 * - On failure, a negative value.
6593 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6594 struct rte_eth_ntuple_filter *ntuple_filter,
6597 struct ixgbe_filter_info *filter_info =
6598 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6599 struct ixgbe_5tuple_filter_info filter_5tuple;
6600 struct ixgbe_5tuple_filter *filter;
6603 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6604 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6608 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6609 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6613 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6615 if (filter != NULL && add) {
6616 PMD_DRV_LOG(ERR, "filter exists.");
6619 if (filter == NULL && !add) {
6620 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6625 filter = rte_zmalloc("ixgbe_5tuple_filter",
6626 sizeof(struct ixgbe_5tuple_filter), 0);
6629 rte_memcpy(&filter->filter_info,
6631 sizeof(struct ixgbe_5tuple_filter_info));
6632 filter->queue = ntuple_filter->queue;
6633 ret = ixgbe_add_5tuple_filter(dev, filter);
6639 ixgbe_remove_5tuple_filter(dev, filter);
6645 * get a ntuple filter
6648 * dev: Pointer to struct rte_eth_dev.
6649 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6652 * - On success, zero.
6653 * - On failure, a negative value.
6656 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6657 struct rte_eth_ntuple_filter *ntuple_filter)
6659 struct ixgbe_filter_info *filter_info =
6660 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6661 struct ixgbe_5tuple_filter_info filter_5tuple;
6662 struct ixgbe_5tuple_filter *filter;
6665 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6666 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6670 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6671 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6675 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6677 if (filter == NULL) {
6678 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6681 ntuple_filter->queue = filter->queue;
6686 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6687 * @dev: pointer to rte_eth_dev structure
6688 * @filter_op:operation will be taken.
6689 * @arg: a pointer to specific structure corresponding to the filter_op
6692 * - On success, zero.
6693 * - On failure, a negative value.
6696 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6697 enum rte_filter_op filter_op,
6700 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6703 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6705 if (filter_op == RTE_ETH_FILTER_NOP)
6709 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6714 switch (filter_op) {
6715 case RTE_ETH_FILTER_ADD:
6716 ret = ixgbe_add_del_ntuple_filter(dev,
6717 (struct rte_eth_ntuple_filter *)arg,
6720 case RTE_ETH_FILTER_DELETE:
6721 ret = ixgbe_add_del_ntuple_filter(dev,
6722 (struct rte_eth_ntuple_filter *)arg,
6725 case RTE_ETH_FILTER_GET:
6726 ret = ixgbe_get_ntuple_filter(dev,
6727 (struct rte_eth_ntuple_filter *)arg);
6730 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6738 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6739 struct rte_eth_ethertype_filter *filter,
6742 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6743 struct ixgbe_filter_info *filter_info =
6744 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6748 struct ixgbe_ethertype_filter ethertype_filter;
6750 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6753 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6754 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6755 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6756 " ethertype filter.", filter->ether_type);
6760 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6761 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6764 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6765 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6769 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6770 if (ret >= 0 && add) {
6771 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6772 filter->ether_type);
6775 if (ret < 0 && !add) {
6776 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6777 filter->ether_type);
6782 etqf = IXGBE_ETQF_FILTER_EN;
6783 etqf |= (uint32_t)filter->ether_type;
6784 etqs |= (uint32_t)((filter->queue <<
6785 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6786 IXGBE_ETQS_RX_QUEUE);
6787 etqs |= IXGBE_ETQS_QUEUE_EN;
6789 ethertype_filter.ethertype = filter->ether_type;
6790 ethertype_filter.etqf = etqf;
6791 ethertype_filter.etqs = etqs;
6792 ethertype_filter.conf = FALSE;
6793 ret = ixgbe_ethertype_filter_insert(filter_info,
6796 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6800 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6804 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6805 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6806 IXGBE_WRITE_FLUSH(hw);
6812 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6813 struct rte_eth_ethertype_filter *filter)
6815 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6816 struct ixgbe_filter_info *filter_info =
6817 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6818 uint32_t etqf, etqs;
6821 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6823 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6824 filter->ether_type);
6828 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6829 if (etqf & IXGBE_ETQF_FILTER_EN) {
6830 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6831 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6833 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6834 IXGBE_ETQS_RX_QUEUE_SHIFT;
6841 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6842 * @dev: pointer to rte_eth_dev structure
6843 * @filter_op:operation will be taken.
6844 * @arg: a pointer to specific structure corresponding to the filter_op
6847 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6848 enum rte_filter_op filter_op,
6851 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6854 MAC_TYPE_FILTER_SUP(hw->mac.type);
6856 if (filter_op == RTE_ETH_FILTER_NOP)
6860 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6865 switch (filter_op) {
6866 case RTE_ETH_FILTER_ADD:
6867 ret = ixgbe_add_del_ethertype_filter(dev,
6868 (struct rte_eth_ethertype_filter *)arg,
6871 case RTE_ETH_FILTER_DELETE:
6872 ret = ixgbe_add_del_ethertype_filter(dev,
6873 (struct rte_eth_ethertype_filter *)arg,
6876 case RTE_ETH_FILTER_GET:
6877 ret = ixgbe_get_ethertype_filter(dev,
6878 (struct rte_eth_ethertype_filter *)arg);
6881 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6889 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6890 enum rte_filter_type filter_type,
6891 enum rte_filter_op filter_op,
6896 switch (filter_type) {
6897 case RTE_ETH_FILTER_NTUPLE:
6898 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6900 case RTE_ETH_FILTER_ETHERTYPE:
6901 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6903 case RTE_ETH_FILTER_SYN:
6904 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6906 case RTE_ETH_FILTER_FDIR:
6907 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6909 case RTE_ETH_FILTER_L2_TUNNEL:
6910 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6912 case RTE_ETH_FILTER_GENERIC:
6913 if (filter_op != RTE_ETH_FILTER_GET)
6915 *(const void **)arg = &ixgbe_flow_ops;
6918 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6928 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6929 u8 **mc_addr_ptr, u32 *vmdq)
6934 mc_addr = *mc_addr_ptr;
6935 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6940 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6941 struct rte_ether_addr *mc_addr_set,
6942 uint32_t nb_mc_addr)
6944 struct ixgbe_hw *hw;
6947 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6948 mc_addr_list = (u8 *)mc_addr_set;
6949 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6950 ixgbe_dev_addr_list_itr, TRUE);
6954 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6956 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6957 uint64_t systime_cycles;
6959 switch (hw->mac.type) {
6960 case ixgbe_mac_X550:
6961 case ixgbe_mac_X550EM_x:
6962 case ixgbe_mac_X550EM_a:
6963 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6964 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6965 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6969 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6970 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6974 return systime_cycles;
6978 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6980 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6981 uint64_t rx_tstamp_cycles;
6983 switch (hw->mac.type) {
6984 case ixgbe_mac_X550:
6985 case ixgbe_mac_X550EM_x:
6986 case ixgbe_mac_X550EM_a:
6987 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6988 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6989 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6993 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6994 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6995 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6999 return rx_tstamp_cycles;
7003 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7005 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7006 uint64_t tx_tstamp_cycles;
7008 switch (hw->mac.type) {
7009 case ixgbe_mac_X550:
7010 case ixgbe_mac_X550EM_x:
7011 case ixgbe_mac_X550EM_a:
7012 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7013 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7014 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7018 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7019 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7020 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7024 return tx_tstamp_cycles;
7028 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7030 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7031 struct ixgbe_adapter *adapter = dev->data->dev_private;
7032 struct rte_eth_link link;
7033 uint32_t incval = 0;
7036 /* Get current link speed. */
7037 ixgbe_dev_link_update(dev, 1);
7038 rte_eth_linkstatus_get(dev, &link);
7040 switch (link.link_speed) {
7041 case ETH_SPEED_NUM_100M:
7042 incval = IXGBE_INCVAL_100;
7043 shift = IXGBE_INCVAL_SHIFT_100;
7045 case ETH_SPEED_NUM_1G:
7046 incval = IXGBE_INCVAL_1GB;
7047 shift = IXGBE_INCVAL_SHIFT_1GB;
7049 case ETH_SPEED_NUM_10G:
7051 incval = IXGBE_INCVAL_10GB;
7052 shift = IXGBE_INCVAL_SHIFT_10GB;
7056 switch (hw->mac.type) {
7057 case ixgbe_mac_X550:
7058 case ixgbe_mac_X550EM_x:
7059 case ixgbe_mac_X550EM_a:
7060 /* Independent of link speed. */
7062 /* Cycles read will be interpreted as ns. */
7065 case ixgbe_mac_X540:
7066 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7068 case ixgbe_mac_82599EB:
7069 incval >>= IXGBE_INCVAL_SHIFT_82599;
7070 shift -= IXGBE_INCVAL_SHIFT_82599;
7071 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7072 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7075 /* Not supported. */
7079 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7080 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7081 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7083 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7084 adapter->systime_tc.cc_shift = shift;
7085 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7087 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7088 adapter->rx_tstamp_tc.cc_shift = shift;
7089 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7091 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7092 adapter->tx_tstamp_tc.cc_shift = shift;
7093 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7097 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7099 struct ixgbe_adapter *adapter = dev->data->dev_private;
7101 adapter->systime_tc.nsec += delta;
7102 adapter->rx_tstamp_tc.nsec += delta;
7103 adapter->tx_tstamp_tc.nsec += delta;
7109 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7112 struct ixgbe_adapter *adapter = dev->data->dev_private;
7114 ns = rte_timespec_to_ns(ts);
7115 /* Set the timecounters to a new value. */
7116 adapter->systime_tc.nsec = ns;
7117 adapter->rx_tstamp_tc.nsec = ns;
7118 adapter->tx_tstamp_tc.nsec = ns;
7124 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7126 uint64_t ns, systime_cycles;
7127 struct ixgbe_adapter *adapter = dev->data->dev_private;
7129 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7130 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7131 *ts = rte_ns_to_timespec(ns);
7137 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7139 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7143 /* Stop the timesync system time. */
7144 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7145 /* Reset the timesync system time value. */
7146 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7147 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7149 /* Enable system time for platforms where it isn't on by default. */
7150 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7151 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7152 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7154 ixgbe_start_timecounters(dev);
7156 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7157 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7158 (RTE_ETHER_TYPE_1588 |
7159 IXGBE_ETQF_FILTER_EN |
7162 /* Enable timestamping of received PTP packets. */
7163 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7164 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7165 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7167 /* Enable timestamping of transmitted PTP packets. */
7168 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7169 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7170 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7172 IXGBE_WRITE_FLUSH(hw);
7178 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7180 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7183 /* Disable timestamping of transmitted PTP packets. */
7184 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7185 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7186 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7188 /* Disable timestamping of received PTP packets. */
7189 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7190 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7191 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7193 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7194 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7196 /* Stop incrementating the System Time registers. */
7197 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7203 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7204 struct timespec *timestamp,
7205 uint32_t flags __rte_unused)
7207 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7208 struct ixgbe_adapter *adapter = dev->data->dev_private;
7209 uint32_t tsync_rxctl;
7210 uint64_t rx_tstamp_cycles;
7213 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7214 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7217 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7218 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7219 *timestamp = rte_ns_to_timespec(ns);
7225 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7226 struct timespec *timestamp)
7228 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7229 struct ixgbe_adapter *adapter = dev->data->dev_private;
7230 uint32_t tsync_txctl;
7231 uint64_t tx_tstamp_cycles;
7234 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7235 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7238 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7239 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7240 *timestamp = rte_ns_to_timespec(ns);
7246 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7248 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7251 const struct reg_info *reg_group;
7252 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7253 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7255 while ((reg_group = reg_set[g_ind++]))
7256 count += ixgbe_regs_group_count(reg_group);
7262 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7266 const struct reg_info *reg_group;
7268 while ((reg_group = ixgbevf_regs[g_ind++]))
7269 count += ixgbe_regs_group_count(reg_group);
7275 ixgbe_get_regs(struct rte_eth_dev *dev,
7276 struct rte_dev_reg_info *regs)
7278 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7279 uint32_t *data = regs->data;
7282 const struct reg_info *reg_group;
7283 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7284 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7287 regs->length = ixgbe_get_reg_length(dev);
7288 regs->width = sizeof(uint32_t);
7292 /* Support only full register dump */
7293 if ((regs->length == 0) ||
7294 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7295 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7297 while ((reg_group = reg_set[g_ind++]))
7298 count += ixgbe_read_regs_group(dev, &data[count],
7307 ixgbevf_get_regs(struct rte_eth_dev *dev,
7308 struct rte_dev_reg_info *regs)
7310 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7311 uint32_t *data = regs->data;
7314 const struct reg_info *reg_group;
7317 regs->length = ixgbevf_get_reg_length(dev);
7318 regs->width = sizeof(uint32_t);
7322 /* Support only full register dump */
7323 if ((regs->length == 0) ||
7324 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7325 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7327 while ((reg_group = ixgbevf_regs[g_ind++]))
7328 count += ixgbe_read_regs_group(dev, &data[count],
7337 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7339 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7341 /* Return unit is byte count */
7342 return hw->eeprom.word_size * 2;
7346 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7347 struct rte_dev_eeprom_info *in_eeprom)
7349 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7350 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7351 uint16_t *data = in_eeprom->data;
7354 first = in_eeprom->offset >> 1;
7355 length = in_eeprom->length >> 1;
7356 if ((first > hw->eeprom.word_size) ||
7357 ((first + length) > hw->eeprom.word_size))
7360 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7362 return eeprom->ops.read_buffer(hw, first, length, data);
7366 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7367 struct rte_dev_eeprom_info *in_eeprom)
7369 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7370 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7371 uint16_t *data = in_eeprom->data;
7374 first = in_eeprom->offset >> 1;
7375 length = in_eeprom->length >> 1;
7376 if ((first > hw->eeprom.word_size) ||
7377 ((first + length) > hw->eeprom.word_size))
7380 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7382 return eeprom->ops.write_buffer(hw, first, length, data);
7386 ixgbe_get_module_info(struct rte_eth_dev *dev,
7387 struct rte_eth_dev_module_info *modinfo)
7389 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7391 uint8_t sff8472_rev, addr_mode;
7392 bool page_swap = false;
7394 /* Check whether we support SFF-8472 or not */
7395 status = hw->phy.ops.read_i2c_eeprom(hw,
7396 IXGBE_SFF_SFF_8472_COMP,
7401 /* addressing mode is not supported */
7402 status = hw->phy.ops.read_i2c_eeprom(hw,
7403 IXGBE_SFF_SFF_8472_SWAP,
7408 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7410 "Address change required to access page 0xA2, "
7411 "but not supported. Please report the module "
7412 "type to the driver maintainers.");
7416 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7417 /* We have a SFP, but it does not support SFF-8472 */
7418 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7419 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7421 /* We have a SFP which supports a revision of SFF-8472. */
7422 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7423 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7430 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7431 struct rte_dev_eeprom_info *info)
7433 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7434 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7435 uint8_t databyte = 0xFF;
7436 uint8_t *data = info->data;
7439 if (info->length == 0)
7442 for (i = info->offset; i < info->offset + info->length; i++) {
7443 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7444 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7446 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7451 data[i - info->offset] = databyte;
7458 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7460 case ixgbe_mac_X550:
7461 case ixgbe_mac_X550EM_x:
7462 case ixgbe_mac_X550EM_a:
7463 return ETH_RSS_RETA_SIZE_512;
7464 case ixgbe_mac_X550_vf:
7465 case ixgbe_mac_X550EM_x_vf:
7466 case ixgbe_mac_X550EM_a_vf:
7467 return ETH_RSS_RETA_SIZE_64;
7468 case ixgbe_mac_X540_vf:
7469 case ixgbe_mac_82599_vf:
7472 return ETH_RSS_RETA_SIZE_128;
7477 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7479 case ixgbe_mac_X550:
7480 case ixgbe_mac_X550EM_x:
7481 case ixgbe_mac_X550EM_a:
7482 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7483 return IXGBE_RETA(reta_idx >> 2);
7485 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7486 case ixgbe_mac_X550_vf:
7487 case ixgbe_mac_X550EM_x_vf:
7488 case ixgbe_mac_X550EM_a_vf:
7489 return IXGBE_VFRETA(reta_idx >> 2);
7491 return IXGBE_RETA(reta_idx >> 2);
7496 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7498 case ixgbe_mac_X550_vf:
7499 case ixgbe_mac_X550EM_x_vf:
7500 case ixgbe_mac_X550EM_a_vf:
7501 return IXGBE_VFMRQC;
7508 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7510 case ixgbe_mac_X550_vf:
7511 case ixgbe_mac_X550EM_x_vf:
7512 case ixgbe_mac_X550EM_a_vf:
7513 return IXGBE_VFRSSRK(i);
7515 return IXGBE_RSSRK(i);
7520 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7522 case ixgbe_mac_82599_vf:
7523 case ixgbe_mac_X540_vf:
7531 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7532 struct rte_eth_dcb_info *dcb_info)
7534 struct ixgbe_dcb_config *dcb_config =
7535 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7536 struct ixgbe_dcb_tc_config *tc;
7537 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7541 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7542 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7544 dcb_info->nb_tcs = 1;
7546 tc_queue = &dcb_info->tc_queue;
7547 nb_tcs = dcb_info->nb_tcs;
7549 if (dcb_config->vt_mode) { /* vt is enabled*/
7550 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7551 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7552 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7553 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7554 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7555 for (j = 0; j < nb_tcs; j++) {
7556 tc_queue->tc_rxq[0][j].base = j;
7557 tc_queue->tc_rxq[0][j].nb_queue = 1;
7558 tc_queue->tc_txq[0][j].base = j;
7559 tc_queue->tc_txq[0][j].nb_queue = 1;
7562 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7563 for (j = 0; j < nb_tcs; j++) {
7564 tc_queue->tc_rxq[i][j].base =
7566 tc_queue->tc_rxq[i][j].nb_queue = 1;
7567 tc_queue->tc_txq[i][j].base =
7569 tc_queue->tc_txq[i][j].nb_queue = 1;
7573 } else { /* vt is disabled*/
7574 struct rte_eth_dcb_rx_conf *rx_conf =
7575 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7576 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7577 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7578 if (dcb_info->nb_tcs == ETH_4_TCS) {
7579 for (i = 0; i < dcb_info->nb_tcs; i++) {
7580 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7581 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7583 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7584 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7585 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7586 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7587 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7588 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7589 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7590 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7591 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7592 for (i = 0; i < dcb_info->nb_tcs; i++) {
7593 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7594 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7596 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7597 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7598 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7599 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7600 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7601 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7602 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7603 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7604 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7605 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7606 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7607 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7608 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7609 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7610 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7611 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7614 for (i = 0; i < dcb_info->nb_tcs; i++) {
7615 tc = &dcb_config->tc_config[i];
7616 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7621 /* Update e-tag ether type */
7623 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7624 uint16_t ether_type)
7626 uint32_t etag_etype;
7628 if (hw->mac.type != ixgbe_mac_X550 &&
7629 hw->mac.type != ixgbe_mac_X550EM_x &&
7630 hw->mac.type != ixgbe_mac_X550EM_a) {
7634 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7635 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7636 etag_etype |= ether_type;
7637 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7638 IXGBE_WRITE_FLUSH(hw);
7643 /* Config l2 tunnel ether type */
7645 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7646 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7649 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7650 struct ixgbe_l2_tn_info *l2_tn_info =
7651 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7653 if (l2_tunnel == NULL)
7656 switch (l2_tunnel->l2_tunnel_type) {
7657 case RTE_L2_TUNNEL_TYPE_E_TAG:
7658 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7659 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7662 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7670 /* Enable e-tag tunnel */
7672 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7674 uint32_t etag_etype;
7676 if (hw->mac.type != ixgbe_mac_X550 &&
7677 hw->mac.type != ixgbe_mac_X550EM_x &&
7678 hw->mac.type != ixgbe_mac_X550EM_a) {
7682 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7683 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7684 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7685 IXGBE_WRITE_FLUSH(hw);
7690 /* Enable l2 tunnel */
7692 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7693 enum rte_eth_tunnel_type l2_tunnel_type)
7696 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7697 struct ixgbe_l2_tn_info *l2_tn_info =
7698 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7700 switch (l2_tunnel_type) {
7701 case RTE_L2_TUNNEL_TYPE_E_TAG:
7702 l2_tn_info->e_tag_en = TRUE;
7703 ret = ixgbe_e_tag_enable(hw);
7706 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7714 /* Disable e-tag tunnel */
7716 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7718 uint32_t etag_etype;
7720 if (hw->mac.type != ixgbe_mac_X550 &&
7721 hw->mac.type != ixgbe_mac_X550EM_x &&
7722 hw->mac.type != ixgbe_mac_X550EM_a) {
7726 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7727 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7728 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7729 IXGBE_WRITE_FLUSH(hw);
7734 /* Disable l2 tunnel */
7736 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7737 enum rte_eth_tunnel_type l2_tunnel_type)
7740 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7741 struct ixgbe_l2_tn_info *l2_tn_info =
7742 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7744 switch (l2_tunnel_type) {
7745 case RTE_L2_TUNNEL_TYPE_E_TAG:
7746 l2_tn_info->e_tag_en = FALSE;
7747 ret = ixgbe_e_tag_disable(hw);
7750 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7759 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7760 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7763 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7764 uint32_t i, rar_entries;
7765 uint32_t rar_low, rar_high;
7767 if (hw->mac.type != ixgbe_mac_X550 &&
7768 hw->mac.type != ixgbe_mac_X550EM_x &&
7769 hw->mac.type != ixgbe_mac_X550EM_a) {
7773 rar_entries = ixgbe_get_num_rx_addrs(hw);
7775 for (i = 1; i < rar_entries; i++) {
7776 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7777 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7778 if ((rar_high & IXGBE_RAH_AV) &&
7779 (rar_high & IXGBE_RAH_ADTYPE) &&
7780 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7781 l2_tunnel->tunnel_id)) {
7782 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7783 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7785 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7795 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7796 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7799 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7800 uint32_t i, rar_entries;
7801 uint32_t rar_low, rar_high;
7803 if (hw->mac.type != ixgbe_mac_X550 &&
7804 hw->mac.type != ixgbe_mac_X550EM_x &&
7805 hw->mac.type != ixgbe_mac_X550EM_a) {
7809 /* One entry for one tunnel. Try to remove potential existing entry. */
7810 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7812 rar_entries = ixgbe_get_num_rx_addrs(hw);
7814 for (i = 1; i < rar_entries; i++) {
7815 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7816 if (rar_high & IXGBE_RAH_AV) {
7819 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7820 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7821 rar_low = l2_tunnel->tunnel_id;
7823 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7824 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7830 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7831 " Please remove a rule before adding a new one.");
7835 static inline struct ixgbe_l2_tn_filter *
7836 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7837 struct ixgbe_l2_tn_key *key)
7841 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7845 return l2_tn_info->hash_map[ret];
7849 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7850 struct ixgbe_l2_tn_filter *l2_tn_filter)
7854 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7855 &l2_tn_filter->key);
7859 "Failed to insert L2 tunnel filter"
7860 " to hash table %d!",
7865 l2_tn_info->hash_map[ret] = l2_tn_filter;
7867 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7873 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7874 struct ixgbe_l2_tn_key *key)
7877 struct ixgbe_l2_tn_filter *l2_tn_filter;
7879 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7883 "No such L2 tunnel filter to delete %d!",
7888 l2_tn_filter = l2_tn_info->hash_map[ret];
7889 l2_tn_info->hash_map[ret] = NULL;
7891 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7892 rte_free(l2_tn_filter);
7897 /* Add l2 tunnel filter */
7899 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7900 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7904 struct ixgbe_l2_tn_info *l2_tn_info =
7905 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7906 struct ixgbe_l2_tn_key key;
7907 struct ixgbe_l2_tn_filter *node;
7910 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7911 key.tn_id = l2_tunnel->tunnel_id;
7913 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7917 "The L2 tunnel filter already exists!");
7921 node = rte_zmalloc("ixgbe_l2_tn",
7922 sizeof(struct ixgbe_l2_tn_filter),
7927 rte_memcpy(&node->key,
7929 sizeof(struct ixgbe_l2_tn_key));
7930 node->pool = l2_tunnel->pool;
7931 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7938 switch (l2_tunnel->l2_tunnel_type) {
7939 case RTE_L2_TUNNEL_TYPE_E_TAG:
7940 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7943 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7948 if ((!restore) && (ret < 0))
7949 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7954 /* Delete l2 tunnel filter */
7956 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7957 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7960 struct ixgbe_l2_tn_info *l2_tn_info =
7961 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7962 struct ixgbe_l2_tn_key key;
7964 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7965 key.tn_id = l2_tunnel->tunnel_id;
7966 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7970 switch (l2_tunnel->l2_tunnel_type) {
7971 case RTE_L2_TUNNEL_TYPE_E_TAG:
7972 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7975 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7984 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7985 * @dev: pointer to rte_eth_dev structure
7986 * @filter_op:operation will be taken.
7987 * @arg: a pointer to specific structure corresponding to the filter_op
7990 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7991 enum rte_filter_op filter_op,
7996 if (filter_op == RTE_ETH_FILTER_NOP)
8000 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8005 switch (filter_op) {
8006 case RTE_ETH_FILTER_ADD:
8007 ret = ixgbe_dev_l2_tunnel_filter_add
8009 (struct rte_eth_l2_tunnel_conf *)arg,
8012 case RTE_ETH_FILTER_DELETE:
8013 ret = ixgbe_dev_l2_tunnel_filter_del
8015 (struct rte_eth_l2_tunnel_conf *)arg);
8018 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8026 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8030 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8032 if (hw->mac.type != ixgbe_mac_X550 &&
8033 hw->mac.type != ixgbe_mac_X550EM_x &&
8034 hw->mac.type != ixgbe_mac_X550EM_a) {
8038 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8039 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8041 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8042 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8047 /* Enable l2 tunnel forwarding */
8049 ixgbe_dev_l2_tunnel_forwarding_enable
8050 (struct rte_eth_dev *dev,
8051 enum rte_eth_tunnel_type l2_tunnel_type)
8053 struct ixgbe_l2_tn_info *l2_tn_info =
8054 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8057 switch (l2_tunnel_type) {
8058 case RTE_L2_TUNNEL_TYPE_E_TAG:
8059 l2_tn_info->e_tag_fwd_en = TRUE;
8060 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8063 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8071 /* Disable l2 tunnel forwarding */
8073 ixgbe_dev_l2_tunnel_forwarding_disable
8074 (struct rte_eth_dev *dev,
8075 enum rte_eth_tunnel_type l2_tunnel_type)
8077 struct ixgbe_l2_tn_info *l2_tn_info =
8078 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8081 switch (l2_tunnel_type) {
8082 case RTE_L2_TUNNEL_TYPE_E_TAG:
8083 l2_tn_info->e_tag_fwd_en = FALSE;
8084 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8087 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8096 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8097 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8100 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8102 uint32_t vmtir, vmvir;
8103 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8105 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8107 "VF id %u should be less than %u",
8113 if (hw->mac.type != ixgbe_mac_X550 &&
8114 hw->mac.type != ixgbe_mac_X550EM_x &&
8115 hw->mac.type != ixgbe_mac_X550EM_a) {
8120 vmtir = l2_tunnel->tunnel_id;
8124 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8126 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8127 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8129 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8130 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8135 /* Enable l2 tunnel tag insertion */
8137 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8138 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8142 switch (l2_tunnel->l2_tunnel_type) {
8143 case RTE_L2_TUNNEL_TYPE_E_TAG:
8144 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8147 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8155 /* Disable l2 tunnel tag insertion */
8157 ixgbe_dev_l2_tunnel_insertion_disable
8158 (struct rte_eth_dev *dev,
8159 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8163 switch (l2_tunnel->l2_tunnel_type) {
8164 case RTE_L2_TUNNEL_TYPE_E_TAG:
8165 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8168 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8177 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8182 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8184 if (hw->mac.type != ixgbe_mac_X550 &&
8185 hw->mac.type != ixgbe_mac_X550EM_x &&
8186 hw->mac.type != ixgbe_mac_X550EM_a) {
8190 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8192 qde |= IXGBE_QDE_STRIP_TAG;
8194 qde &= ~IXGBE_QDE_STRIP_TAG;
8195 qde &= ~IXGBE_QDE_READ;
8196 qde |= IXGBE_QDE_WRITE;
8197 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8202 /* Enable l2 tunnel tag stripping */
8204 ixgbe_dev_l2_tunnel_stripping_enable
8205 (struct rte_eth_dev *dev,
8206 enum rte_eth_tunnel_type l2_tunnel_type)
8210 switch (l2_tunnel_type) {
8211 case RTE_L2_TUNNEL_TYPE_E_TAG:
8212 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8215 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8223 /* Disable l2 tunnel tag stripping */
8225 ixgbe_dev_l2_tunnel_stripping_disable
8226 (struct rte_eth_dev *dev,
8227 enum rte_eth_tunnel_type l2_tunnel_type)
8231 switch (l2_tunnel_type) {
8232 case RTE_L2_TUNNEL_TYPE_E_TAG:
8233 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8236 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8244 /* Enable/disable l2 tunnel offload functions */
8246 ixgbe_dev_l2_tunnel_offload_set
8247 (struct rte_eth_dev *dev,
8248 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8254 if (l2_tunnel == NULL)
8258 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8260 ret = ixgbe_dev_l2_tunnel_enable(
8262 l2_tunnel->l2_tunnel_type);
8264 ret = ixgbe_dev_l2_tunnel_disable(
8266 l2_tunnel->l2_tunnel_type);
8269 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8271 ret = ixgbe_dev_l2_tunnel_insertion_enable(
8275 ret = ixgbe_dev_l2_tunnel_insertion_disable(
8280 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8282 ret = ixgbe_dev_l2_tunnel_stripping_enable(
8284 l2_tunnel->l2_tunnel_type);
8286 ret = ixgbe_dev_l2_tunnel_stripping_disable(
8288 l2_tunnel->l2_tunnel_type);
8291 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8293 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8295 l2_tunnel->l2_tunnel_type);
8297 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8299 l2_tunnel->l2_tunnel_type);
8306 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8309 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8310 IXGBE_WRITE_FLUSH(hw);
8315 /* There's only one register for VxLAN UDP port.
8316 * So, we cannot add several ports. Will update it.
8319 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8323 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8327 return ixgbe_update_vxlan_port(hw, port);
8330 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8331 * UDP port, it must have a value.
8332 * So, will reset it to the original value 0.
8335 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8340 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8342 if (cur_port != port) {
8343 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8347 return ixgbe_update_vxlan_port(hw, 0);
8350 /* Add UDP tunneling port */
8352 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8353 struct rte_eth_udp_tunnel *udp_tunnel)
8356 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8358 if (hw->mac.type != ixgbe_mac_X550 &&
8359 hw->mac.type != ixgbe_mac_X550EM_x &&
8360 hw->mac.type != ixgbe_mac_X550EM_a) {
8364 if (udp_tunnel == NULL)
8367 switch (udp_tunnel->prot_type) {
8368 case RTE_TUNNEL_TYPE_VXLAN:
8369 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8372 case RTE_TUNNEL_TYPE_GENEVE:
8373 case RTE_TUNNEL_TYPE_TEREDO:
8374 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8379 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8387 /* Remove UDP tunneling port */
8389 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8390 struct rte_eth_udp_tunnel *udp_tunnel)
8393 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8395 if (hw->mac.type != ixgbe_mac_X550 &&
8396 hw->mac.type != ixgbe_mac_X550EM_x &&
8397 hw->mac.type != ixgbe_mac_X550EM_a) {
8401 if (udp_tunnel == NULL)
8404 switch (udp_tunnel->prot_type) {
8405 case RTE_TUNNEL_TYPE_VXLAN:
8406 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8408 case RTE_TUNNEL_TYPE_GENEVE:
8409 case RTE_TUNNEL_TYPE_TEREDO:
8410 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8414 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8423 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8425 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8428 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8432 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8444 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8446 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8449 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8453 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8465 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8467 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8469 int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8471 switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8475 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8487 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8489 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8492 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8496 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8507 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8509 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8512 /* peek the message first */
8513 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8515 /* PF reset VF event */
8516 if (in_msg == IXGBE_PF_CONTROL_MSG) {
8517 /* dummy mbx read to ack pf */
8518 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8520 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8526 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8529 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8530 struct ixgbe_interrupt *intr =
8531 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8532 ixgbevf_intr_disable(dev);
8534 /* read-on-clear nic registers here */
8535 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8538 /* only one misc vector supported - mailbox */
8539 eicr &= IXGBE_VTEICR_MASK;
8540 if (eicr == IXGBE_MISC_VEC_ID)
8541 intr->flags |= IXGBE_FLAG_MAILBOX;
8547 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8549 struct ixgbe_interrupt *intr =
8550 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8552 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8553 ixgbevf_mbx_process(dev);
8554 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8557 ixgbevf_intr_enable(dev);
8563 ixgbevf_dev_interrupt_handler(void *param)
8565 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8567 ixgbevf_dev_interrupt_get_status(dev);
8568 ixgbevf_dev_interrupt_action(dev);
8572 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8573 * @hw: pointer to hardware structure
8575 * Stops the transmit data path and waits for the HW to internally empty
8576 * the Tx security block
8578 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8580 #define IXGBE_MAX_SECTX_POLL 40
8585 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8586 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8587 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8588 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8589 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8590 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8592 /* Use interrupt-safe sleep just in case */
8596 /* For informational purposes only */
8597 if (i >= IXGBE_MAX_SECTX_POLL)
8598 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8599 "path fully disabled. Continuing with init.");
8601 return IXGBE_SUCCESS;
8605 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8606 * @hw: pointer to hardware structure
8608 * Enables the transmit data path.
8610 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8614 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8615 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8616 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8617 IXGBE_WRITE_FLUSH(hw);
8619 return IXGBE_SUCCESS;
8622 /* restore n-tuple filter */
8624 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8626 struct ixgbe_filter_info *filter_info =
8627 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8628 struct ixgbe_5tuple_filter *node;
8630 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8631 ixgbe_inject_5tuple_filter(dev, node);
8635 /* restore ethernet type filter */
8637 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8639 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8640 struct ixgbe_filter_info *filter_info =
8641 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8644 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8645 if (filter_info->ethertype_mask & (1 << i)) {
8646 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8647 filter_info->ethertype_filters[i].etqf);
8648 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8649 filter_info->ethertype_filters[i].etqs);
8650 IXGBE_WRITE_FLUSH(hw);
8655 /* restore SYN filter */
8657 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8659 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8660 struct ixgbe_filter_info *filter_info =
8661 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8664 synqf = filter_info->syn_info;
8666 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8667 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8668 IXGBE_WRITE_FLUSH(hw);
8672 /* restore L2 tunnel filter */
8674 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8676 struct ixgbe_l2_tn_info *l2_tn_info =
8677 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8678 struct ixgbe_l2_tn_filter *node;
8679 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8681 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8682 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8683 l2_tn_conf.tunnel_id = node->key.tn_id;
8684 l2_tn_conf.pool = node->pool;
8685 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8689 /* restore rss filter */
8691 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8693 struct ixgbe_filter_info *filter_info =
8694 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8696 if (filter_info->rss_info.conf.queue_num)
8697 ixgbe_config_rss_filter(dev,
8698 &filter_info->rss_info, TRUE);
8702 ixgbe_filter_restore(struct rte_eth_dev *dev)
8704 ixgbe_ntuple_filter_restore(dev);
8705 ixgbe_ethertype_filter_restore(dev);
8706 ixgbe_syn_filter_restore(dev);
8707 ixgbe_fdir_filter_restore(dev);
8708 ixgbe_l2_tn_filter_restore(dev);
8709 ixgbe_rss_filter_restore(dev);
8715 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8717 struct ixgbe_l2_tn_info *l2_tn_info =
8718 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8719 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8721 if (l2_tn_info->e_tag_en)
8722 (void)ixgbe_e_tag_enable(hw);
8724 if (l2_tn_info->e_tag_fwd_en)
8725 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8727 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8730 /* remove all the n-tuple filters */
8732 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8734 struct ixgbe_filter_info *filter_info =
8735 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8736 struct ixgbe_5tuple_filter *p_5tuple;
8738 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8739 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8742 /* remove all the ether type filters */
8744 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8746 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8747 struct ixgbe_filter_info *filter_info =
8748 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8751 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8752 if (filter_info->ethertype_mask & (1 << i) &&
8753 !filter_info->ethertype_filters[i].conf) {
8754 (void)ixgbe_ethertype_filter_remove(filter_info,
8756 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8757 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8758 IXGBE_WRITE_FLUSH(hw);
8763 /* remove the SYN filter */
8765 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8767 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8768 struct ixgbe_filter_info *filter_info =
8769 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8771 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8772 filter_info->syn_info = 0;
8774 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8775 IXGBE_WRITE_FLUSH(hw);
8779 /* remove all the L2 tunnel filters */
8781 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8783 struct ixgbe_l2_tn_info *l2_tn_info =
8784 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8785 struct ixgbe_l2_tn_filter *l2_tn_filter;
8786 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8789 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8790 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8791 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8792 l2_tn_conf.pool = l2_tn_filter->pool;
8793 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8801 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8802 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8803 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8804 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8805 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8806 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8807 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8808 IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8810 RTE_INIT(ixgbe_init_log)
8812 ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8813 if (ixgbe_logtype_init >= 0)
8814 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8815 ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8816 if (ixgbe_logtype_driver >= 0)
8817 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);