drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63 #include <rte_hash_crc.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "base/ixgbe_api.h"
  67 #include "base/ixgbe_vf.h"
  68 #include "base/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71 #include "ixgbe_rxtx.h"
  72 #include "base/ixgbe_type.h"
  73 #include "base/ixgbe_phy.h"
  74 #include "ixgbe_regs.h"
  75
  76 #include "rte_pmd_ixgbe.h"
  77
  78 /*
  79  * High threshold controlling when to start sending XOFF frames. Must be at
  80  * least 8 bytes less than receive packet buffer size. This value is in units
  81  * of 1024 bytes.
  82  */
  83 #define IXGBE_FC_HI    0x80
  84
  85 /*
  86  * Low threshold controlling when to start sending XON frames. This value is
  87  * in units of 1024 bytes.
  88  */
  89 #define IXGBE_FC_LO    0x40
  90
  91 /* Default minimum inter-interrupt interval for EITR configuration */
  92 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  93
  94 /* Timer value included in XOFF frames. */
  95 #define IXGBE_FC_PAUSE 0x680
  96
  97 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  98 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  99 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
 100
 101 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 102 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 103 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 104
 105 /*
 106  *  Default values for RX/TX configuration
 107  */
 108 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 109 #define IXGBE_DEFAULT_RX_PTHRESH      8
 110 #define IXGBE_DEFAULT_RX_HTHRESH      8
 111 #define IXGBE_DEFAULT_RX_WTHRESH      0
 112
 113 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 114 #define IXGBE_DEFAULT_TX_PTHRESH      32
 115 #define IXGBE_DEFAULT_TX_HTHRESH      0
 116 #define IXGBE_DEFAULT_TX_WTHRESH      0
 117 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 118
 119 /* Bit shift and mask */
 120 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 121 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 122 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 123 #define IXGBE_8_BIT_MASK   UINT8_MAX
 124
 125 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 126
 127 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 128
 129 #define IXGBE_HKEY_MAX_INDEX 10
 130
 131 /* Additional timesync values. */
 132 #define NSEC_PER_SEC             1000000000L
 133 #define IXGBE_INCVAL_10GB        0x66666666
 134 #define IXGBE_INCVAL_1GB         0x40000000
 135 #define IXGBE_INCVAL_100         0x50000000
 136 #define IXGBE_INCVAL_SHIFT_10GB  28
 137 #define IXGBE_INCVAL_SHIFT_1GB   24
 138 #define IXGBE_INCVAL_SHIFT_100   21
 139 #define IXGBE_INCVAL_SHIFT_82599 7
 140 #define IXGBE_INCPER_SHIFT_82599 24
 141
 142 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 143
 144 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 145 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 146 #define DEFAULT_ETAG_ETYPE                     0x893f
 147 #define IXGBE_ETAG_ETYPE                       0x00005084
 148 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 149 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 150 #define IXGBE_RAH_ADTYPE                       0x40000000
 151 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 152 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 153 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 154 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 155 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 156 #define IXGBE_VTEICR_MASK                      0x07
 157
 158 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 159 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 160
 161 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 162 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 163 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 164 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 165 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 166 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 167 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 168 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 172 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 178 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 179                                 int wait_to_complete);
 180 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_stats *stats);
 182 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_xstat *xstats, unsigned n);
 184 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 185                                   struct rte_eth_xstat *xstats, unsigned n);
 186 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 187 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 188 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 189         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 190 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 192 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 193                                              uint16_t queue_id,
 194                                              uint8_t stat_idx,
 195                                              uint8_t is_rx);
 196 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 197                                  size_t fw_size);
 198 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 199                                struct rte_eth_dev_info *dev_info);
 200 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 201 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 202                                  struct rte_eth_dev_info *dev_info);
 203 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 204
 205 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 206                 uint16_t vlan_id, int on);
 207 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 208                                enum rte_vlan_type vlan_type,
 209                                uint16_t tpid_id);
 210 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 211                 uint16_t queue, bool on);
 212 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 213                 int on);
 214 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 215 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 216 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 217 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 218 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 219
 220 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 221 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 222 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 223                                struct rte_eth_fc_conf *fc_conf);
 224 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 225                                struct rte_eth_fc_conf *fc_conf);
 226 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 227                 struct rte_eth_pfc_conf *pfc_conf);
 228 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 229                         struct rte_eth_rss_reta_entry64 *reta_conf,
 230                         uint16_t reta_size);
 231 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 232                         struct rte_eth_rss_reta_entry64 *reta_conf,
 233                         uint16_t reta_size);
 234 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 235 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 236 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 237 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 238 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 239 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 240                                       struct rte_intr_handle *handle);
 241 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 242                 void *param);
 243 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 244 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 245                 uint32_t index, uint32_t pool);
 246 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 247 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 248                                            struct ether_addr *mac_addr);
 249 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 250 static bool is_device_supported(struct rte_eth_dev *dev,
 251                                 struct eth_driver *drv);
 252
 253 /* For Virtual Function support */
 254 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 255 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 256 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 257 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 258 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 259 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 260 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 261 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 262 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 263                 struct rte_eth_stats *stats);
 264 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 265 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 266                 uint16_t vlan_id, int on);
 267 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 268                 uint16_t queue, int on);
 269 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 270 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 271 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 272                                             uint16_t queue_id);
 273 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 274                                              uint16_t queue_id);
 275 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 276                                  uint8_t queue, uint8_t msix_vector);
 277 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 278 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 279 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 280
 281 /* For Eth VMDQ APIs support */
 282 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 283                 ether_addr * mac_addr, uint8_t on);
 284 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 285 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 286                 struct rte_eth_mirror_conf *mirror_conf,
 287                 uint8_t rule_id, uint8_t on);
 288 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 289                 uint8_t rule_id);
 290 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 291                                           uint16_t queue_id);
 292 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 293                                            uint16_t queue_id);
 294 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 295                                uint8_t queue, uint8_t msix_vector);
 296 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 297
 298 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 299                 uint16_t queue_idx, uint16_t tx_rate);
 300
 301 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 302                                  struct ether_addr *mac_addr,
 303                                  uint32_t index, uint32_t pool);
 304 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 305 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 306                                              struct ether_addr *mac_addr);
 307 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 308                         struct rte_eth_syn_filter *filter);
 309 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 310                         enum rte_filter_op filter_op,
 311                         void *arg);
 312 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 313                         struct ixgbe_5tuple_filter *filter);
 314 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 315                         struct ixgbe_5tuple_filter *filter);
 316 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 317                                 enum rte_filter_op filter_op,
 318                                 void *arg);
 319 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 320                         struct rte_eth_ntuple_filter *filter);
 321 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 322                                 enum rte_filter_op filter_op,
 323                                 void *arg);
 324 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 325                         struct rte_eth_ethertype_filter *filter);
 326 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 327                      enum rte_filter_type filter_type,
 328                      enum rte_filter_op filter_op,
 329                      void *arg);
 330 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 331
 332 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 333                                       struct ether_addr *mc_addr_set,
 334                                       uint32_t nb_mc_addr);
 335 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 336                                    struct rte_eth_dcb_info *dcb_info);
 337
 338 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 339 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 340                             struct rte_dev_reg_info *regs);
 341 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 342 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 343                                 struct rte_dev_eeprom_info *eeprom);
 344 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 345                                 struct rte_dev_eeprom_info *eeprom);
 346
 347 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 348 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 349                                 struct rte_dev_reg_info *regs);
 350
 351 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 352 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 354                                             struct timespec *timestamp,
 355                                             uint32_t flags);
 356 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 357                                             struct timespec *timestamp);
 358 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 359 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 360                                    struct timespec *timestamp);
 361 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 362                                    const struct timespec *timestamp);
 363 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 364                                           void *param);
 365
 366 static int ixgbe_dev_l2_tunnel_eth_type_conf
 367         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 368 static int ixgbe_dev_l2_tunnel_offload_set
 369         (struct rte_eth_dev *dev,
 370          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 371          uint32_t mask,
 372          uint8_t en);
 373 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 374                                              enum rte_filter_op filter_op,
 375                                              void *arg);
 376
 377 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 380                                          struct rte_eth_udp_tunnel *udp_tunnel);
 381 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 382 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 383
 384 /*
 385  * Define VF Stats MACRO for Non "cleared on read" register
 386  */
 387 #define UPDATE_VF_STAT(reg, last, cur)                          \
 388 {                                                               \
 389         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 390         cur += (latest - last) & UINT_MAX;                      \
 391         last = latest;                                          \
 392 }
 393
 394 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 395 {                                                                \
 396         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 397         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 398         u64 latest = ((new_msb << 32) | new_lsb);                \
 399         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 400         last = latest;                                           \
 401 }
 402
 403 #define IXGBE_SET_HWSTRIP(h, q) do {\
 404                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 405                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 406                 (h)->bitmap[idx] |= 1 << bit;\
 407         } while (0)
 408
 409 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 410                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 411                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 412                 (h)->bitmap[idx] &= ~(1 << bit);\
 413         } while (0)
 414
 415 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 416                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 417                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 418                 (r) = (h)->bitmap[idx] >> bit & 1;\
 419         } while (0)
 420
 421 /*
 422  * The set of PCI devices this driver supports
 423  */
 424 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 478 #ifdef RTE_NIC_BYPASS
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 480 #endif
 481         { .vendor_id = 0, /* sentinel */ },
 482 };
 483
 484 /*
 485  * The set of PCI devices this driver supports (for 82599 VF)
 486  */
 487 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 498         { .vendor_id = 0, /* sentinel */ },
 499 };
 500
 501 static const struct rte_eth_desc_lim rx_desc_lim = {
 502         .nb_max = IXGBE_MAX_RING_DESC,
 503         .nb_min = IXGBE_MIN_RING_DESC,
 504         .nb_align = IXGBE_RXD_ALIGN,
 505 };
 506
 507 static const struct rte_eth_desc_lim tx_desc_lim = {
 508         .nb_max = IXGBE_MAX_RING_DESC,
 509         .nb_min = IXGBE_MIN_RING_DESC,
 510         .nb_align = IXGBE_TXD_ALIGN,
 511         .nb_seg_max = IXGBE_TX_MAX_SEG,
 512         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 513 };
 514
 515 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 516         .dev_configure        = ixgbe_dev_configure,
 517         .dev_start            = ixgbe_dev_start,
 518         .dev_stop             = ixgbe_dev_stop,
 519         .dev_set_link_up    = ixgbe_dev_set_link_up,
 520         .dev_set_link_down  = ixgbe_dev_set_link_down,
 521         .dev_close            = ixgbe_dev_close,
 522         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 523         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 524         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 525         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 526         .link_update          = ixgbe_dev_link_update,
 527         .stats_get            = ixgbe_dev_stats_get,
 528         .xstats_get           = ixgbe_dev_xstats_get,
 529         .stats_reset          = ixgbe_dev_stats_reset,
 530         .xstats_reset         = ixgbe_dev_xstats_reset,
 531         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 532         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 533         .fw_version_get       = ixgbe_fw_version_get,
 534         .dev_infos_get        = ixgbe_dev_info_get,
 535         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 536         .mtu_set              = ixgbe_dev_mtu_set,
 537         .vlan_filter_set      = ixgbe_vlan_filter_set,
 538         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 539         .vlan_offload_set     = ixgbe_vlan_offload_set,
 540         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 541         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 542         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 543         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 544         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 545         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 546         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 547         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 548         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 549         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 550         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 551         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 552         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 553         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 554         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 555         .dev_led_on           = ixgbe_dev_led_on,
 556         .dev_led_off          = ixgbe_dev_led_off,
 557         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 558         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 559         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 560         .mac_addr_add         = ixgbe_add_rar,
 561         .mac_addr_remove      = ixgbe_remove_rar,
 562         .mac_addr_set         = ixgbe_set_default_mac_addr,
 563         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 564         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 565         .mirror_rule_set      = ixgbe_mirror_rule_set,
 566         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 567         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 568         .reta_update          = ixgbe_dev_rss_reta_update,
 569         .reta_query           = ixgbe_dev_rss_reta_query,
 570 #ifdef RTE_NIC_BYPASS
 571         .bypass_init          = ixgbe_bypass_init,
 572         .bypass_state_set     = ixgbe_bypass_state_store,
 573         .bypass_state_show    = ixgbe_bypass_state_show,
 574         .bypass_event_set     = ixgbe_bypass_event_store,
 575         .bypass_event_show    = ixgbe_bypass_event_show,
 576         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 577         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 578         .bypass_ver_show      = ixgbe_bypass_ver_show,
 579         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 580 #endif /* RTE_NIC_BYPASS */
 581         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 582         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 583         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 584         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 585         .rxq_info_get         = ixgbe_rxq_info_get,
 586         .txq_info_get         = ixgbe_txq_info_get,
 587         .timesync_enable      = ixgbe_timesync_enable,
 588         .timesync_disable     = ixgbe_timesync_disable,
 589         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 590         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 591         .get_reg              = ixgbe_get_regs,
 592         .get_eeprom_length    = ixgbe_get_eeprom_length,
 593         .get_eeprom           = ixgbe_get_eeprom,
 594         .set_eeprom           = ixgbe_set_eeprom,
 595         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 596         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 597         .timesync_read_time   = ixgbe_timesync_read_time,
 598         .timesync_write_time  = ixgbe_timesync_write_time,
 599         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 600         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 601         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 602         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 603 };
 604
 605 /*
 606  * dev_ops for virtual function, bare necessities for basic vf
 607  * operation have been implemented
 608  */
 609 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 610         .dev_configure        = ixgbevf_dev_configure,
 611         .dev_start            = ixgbevf_dev_start,
 612         .dev_stop             = ixgbevf_dev_stop,
 613         .link_update          = ixgbe_dev_link_update,
 614         .stats_get            = ixgbevf_dev_stats_get,
 615         .xstats_get           = ixgbevf_dev_xstats_get,
 616         .stats_reset          = ixgbevf_dev_stats_reset,
 617         .xstats_reset         = ixgbevf_dev_stats_reset,
 618         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 619         .dev_close            = ixgbevf_dev_close,
 620         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 621         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 622         .dev_infos_get        = ixgbevf_dev_info_get,
 623         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 624         .mtu_set              = ixgbevf_dev_set_mtu,
 625         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 626         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 627         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 628         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 629         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 630         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 631         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 632         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 633         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 634         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 635         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 636         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 637         .mac_addr_add         = ixgbevf_add_mac_addr,
 638         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 639         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 640         .rxq_info_get         = ixgbe_rxq_info_get,
 641         .txq_info_get         = ixgbe_txq_info_get,
 642         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 643         .get_reg              = ixgbevf_get_regs,
 644         .reta_update          = ixgbe_dev_rss_reta_update,
 645         .reta_query           = ixgbe_dev_rss_reta_query,
 646         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 647         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 648 };
 649
 650 /* store statistics names and its offset in stats structure */
 651 struct rte_ixgbe_xstats_name_off {
 652         char name[RTE_ETH_XSTATS_NAME_SIZE];
 653         unsigned offset;
 654 };
 655
 656 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 657         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 658         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 659         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 660         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 661         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 662         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 663         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 664         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 665         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 666         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 667         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 668         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 669         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 670         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 671         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 672                 prc1023)},
 673         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 674                 prc1522)},
 675         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 676         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 677         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 678         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 679         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 680         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 681         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 682         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 683         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 684         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 685         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 686         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 687         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 688         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 689         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 690         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 691         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 692                 ptc1023)},
 693         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 694                 ptc1522)},
 695         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 696         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 697         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 698         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 699
 700         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 701                 fdirustat_add)},
 702         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 703                 fdirustat_remove)},
 704         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 705                 fdirfstat_fadd)},
 706         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 707                 fdirfstat_fremove)},
 708         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 709                 fdirmatch)},
 710         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 711                 fdirmiss)},
 712
 713         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 714         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 715         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 716                 fclast)},
 717         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 718         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 719         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 720         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 721         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 722                 fcoe_noddp)},
 723         {"rx_fcoe_no_direct_data_placement_ext_buff",
 724                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 725
 726         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 727                 lxontxc)},
 728         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 729                 lxonrxc)},
 730         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 731                 lxofftxc)},
 732         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 733                 lxoffrxc)},
 734         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 735 };
 736
 737 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 738                            sizeof(rte_ixgbe_stats_strings[0]))
 739
 740 /* MACsec statistics */
 741 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 742         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 743                 out_pkts_untagged)},
 744         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 745                 out_pkts_encrypted)},
 746         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 747                 out_pkts_protected)},
 748         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 749                 out_octets_encrypted)},
 750         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 751                 out_octets_protected)},
 752         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_untagged)},
 754         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 755                 in_pkts_badtag)},
 756         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 757                 in_pkts_nosci)},
 758         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 759                 in_pkts_unknownsci)},
 760         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 761                 in_octets_decrypted)},
 762         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 763                 in_octets_validated)},
 764         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 765                 in_pkts_unchecked)},
 766         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 767                 in_pkts_delayed)},
 768         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 769                 in_pkts_late)},
 770         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 771                 in_pkts_ok)},
 772         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 773                 in_pkts_invalid)},
 774         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 775                 in_pkts_notvalid)},
 776         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 777                 in_pkts_unusedsa)},
 778         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 779                 in_pkts_notusingsa)},
 780 };
 781
 782 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 783                            sizeof(rte_ixgbe_macsec_strings[0]))
 784
 785 /* Per-queue statistics */
 786 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 787         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 788         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 789         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 790         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 791 };
 792
 793 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 794                            sizeof(rte_ixgbe_rxq_strings[0]))
 795 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 796
 797 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 798         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 799         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 800         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 801                 pxon2offc)},
 802 };
 803
 804 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 805                            sizeof(rte_ixgbe_txq_strings[0]))
 806 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 807
 808 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 809         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 810 };
 811
 812 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 813                 sizeof(rte_ixgbevf_stats_strings[0]))
 814
 815 /**
 816  * Atomically reads the link status information from global
 817  * structure rte_eth_dev.
 818  *
 819  * @param dev
 820  *   - Pointer to the structure rte_eth_dev to read from.
 821  *   - Pointer to the buffer to be saved with the link status.
 822  *
 823  * @return
 824  *   - On success, zero.
 825  *   - On failure, negative value.
 826  */
 827 static inline int
 828 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 829                                 struct rte_eth_link *link)
 830 {
 831         struct rte_eth_link *dst = link;
 832         struct rte_eth_link *src = &(dev->data->dev_link);
 833
 834         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 835                                         *(uint64_t *)src) == 0)
 836                 return -1;
 837
 838         return 0;
 839 }
 840
 841 /**
 842  * Atomically writes the link status information into global
 843  * structure rte_eth_dev.
 844  *
 845  * @param dev
 846  *   - Pointer to the structure rte_eth_dev to read from.
 847  *   - Pointer to the buffer to be saved with the link status.
 848  *
 849  * @return
 850  *   - On success, zero.
 851  *   - On failure, negative value.
 852  */
 853 static inline int
 854 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 855                                 struct rte_eth_link *link)
 856 {
 857         struct rte_eth_link *dst = &(dev->data->dev_link);
 858         struct rte_eth_link *src = link;
 859
 860         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 861                                         *(uint64_t *)src) == 0)
 862                 return -1;
 863
 864         return 0;
 865 }
 866
 867 /*
 868  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 869  */
 870 static inline int
 871 ixgbe_is_sfp(struct ixgbe_hw *hw)
 872 {
 873         switch (hw->phy.type) {
 874         case ixgbe_phy_sfp_avago:
 875         case ixgbe_phy_sfp_ftl:
 876         case ixgbe_phy_sfp_intel:
 877         case ixgbe_phy_sfp_unknown:
 878         case ixgbe_phy_sfp_passive_tyco:
 879         case ixgbe_phy_sfp_passive_unknown:
 880                 return 1;
 881         default:
 882                 return 0;
 883         }
 884 }
 885
 886 static inline int32_t
 887 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 888 {
 889         uint32_t ctrl_ext;
 890         int32_t status;
 891
 892         status = ixgbe_reset_hw(hw);
 893
 894         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 895         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 896         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 897         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 898         IXGBE_WRITE_FLUSH(hw);
 899
 900         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 901                 status = IXGBE_SUCCESS;
 902         return status;
 903 }
 904
 905 static inline void
 906 ixgbe_enable_intr(struct rte_eth_dev *dev)
 907 {
 908         struct ixgbe_interrupt *intr =
 909                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 910         struct ixgbe_hw *hw =
 911                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 912
 913         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 914         IXGBE_WRITE_FLUSH(hw);
 915 }
 916
 917 /*
 918  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 919  */
 920 static void
 921 ixgbe_disable_intr(struct ixgbe_hw *hw)
 922 {
 923         PMD_INIT_FUNC_TRACE();
 924
 925         if (hw->mac.type == ixgbe_mac_82598EB) {
 926                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 927         } else {
 928                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 929                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 930                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 931         }
 932         IXGBE_WRITE_FLUSH(hw);
 933 }
 934
 935 /*
 936  * This function resets queue statistics mapping registers.
 937  * From Niantic datasheet, Initialization of Statistics section:
 938  * "...if software requires the queue counters, the RQSMR and TQSM registers
 939  * must be re-programmed following a device reset.
 940  */
 941 static void
 942 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 943 {
 944         uint32_t i;
 945
 946         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 947                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 948                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 949         }
 950 }
 951
 952
 953 static int
 954 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 955                                   uint16_t queue_id,
 956                                   uint8_t stat_idx,
 957                                   uint8_t is_rx)
 958 {
 959 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 960 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 961 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 962
 963         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 964         struct ixgbe_stat_mapping_registers *stat_mappings =
 965                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 966         uint32_t qsmr_mask = 0;
 967         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 968         uint32_t q_map;
 969         uint8_t n, offset;
 970
 971         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 972                 (hw->mac.type != ixgbe_mac_X540) &&
 973                 (hw->mac.type != ixgbe_mac_X550) &&
 974                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 975                 (hw->mac.type != ixgbe_mac_X550EM_a))
 976                 return -ENOSYS;
 977
 978         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 979                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 980                      queue_id, stat_idx);
 981
 982         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 983         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 984                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 985                 return -EIO;
 986         }
 987         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 988
 989         /* Now clear any previous stat_idx set */
 990         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 991         if (!is_rx)
 992                 stat_mappings->tqsm[n] &= ~clearing_mask;
 993         else
 994                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 995
 996         q_map = (uint32_t)stat_idx;
 997         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 998         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 999         if (!is_rx)
1000                 stat_mappings->tqsm[n] |= qsmr_mask;
1001         else
1002                 stat_mappings->rqsmr[n] |= qsmr_mask;
1003
1004         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1005                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1006                      queue_id, stat_idx);
1007         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1008                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1009
1010         /* Now write the mapping in the appropriate register */
1011         if (is_rx) {
1012                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1013                              stat_mappings->rqsmr[n], n);
1014                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1015         } else {
1016                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1017                              stat_mappings->tqsm[n], n);
1018                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1019         }
1020         return 0;
1021 }
1022
1023 static void
1024 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1025 {
1026         struct ixgbe_stat_mapping_registers *stat_mappings =
1027                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1028         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1029         int i;
1030
1031         /* write whatever was in stat mapping table to the NIC */
1032         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1033                 /* rx */
1034                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1035
1036                 /* tx */
1037                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1038         }
1039 }
1040
1041 static void
1042 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1043 {
1044         uint8_t i;
1045         struct ixgbe_dcb_tc_config *tc;
1046         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1047
1048         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1049         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1050         for (i = 0; i < dcb_max_tc; i++) {
1051                 tc = &dcb_config->tc_config[i];
1052                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1053                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1054                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1055                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1056                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1057                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1058                 tc->pfc = ixgbe_dcb_pfc_disabled;
1059         }
1060
1061         /* Initialize default user to priority mapping, UPx->TC0 */
1062         tc = &dcb_config->tc_config[0];
1063         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1064         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1065         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1066                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1067                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1068         }
1069         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1070         dcb_config->pfc_mode_enable = false;
1071         dcb_config->vt_mode = true;
1072         dcb_config->round_robin_enable = false;
1073         /* support all DCB capabilities in 82599 */
1074         dcb_config->support.capabilities = 0xFF;
1075
1076         /*we only support 4 Tcs for X540, X550 */
1077         if (hw->mac.type == ixgbe_mac_X540 ||
1078                 hw->mac.type == ixgbe_mac_X550 ||
1079                 hw->mac.type == ixgbe_mac_X550EM_x ||
1080                 hw->mac.type == ixgbe_mac_X550EM_a) {
1081                 dcb_config->num_tcs.pg_tcs = 4;
1082                 dcb_config->num_tcs.pfc_tcs = 4;
1083         }
1084 }
1085
1086 /*
1087  * Ensure that all locks are released before first NVM or PHY access
1088  */
1089 static void
1090 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1091 {
1092         uint16_t mask;
1093
1094         /*
1095          * Phy lock should not fail in this early stage. If this is the case,
1096          * it is due to an improper exit of the application.
1097          * So force the release of the faulty lock. Release of common lock
1098          * is done automatically by swfw_sync function.
1099          */
1100         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1101         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1102                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1103         }
1104         ixgbe_release_swfw_semaphore(hw, mask);
1105
1106         /*
1107          * These ones are more tricky since they are common to all ports; but
1108          * swfw_sync retries last long enough (1s) to be almost sure that if
1109          * lock can not be taken it is due to an improper lock of the
1110          * semaphore.
1111          */
1112         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1113         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1114                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1115         }
1116         ixgbe_release_swfw_semaphore(hw, mask);
1117 }
1118
1119 /*
1120  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1121  * It returns 0 on success.
1122  */
1123 static int
1124 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1125 {
1126         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1127         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1128         struct ixgbe_hw *hw =
1129                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1130         struct ixgbe_vfta *shadow_vfta =
1131                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1132         struct ixgbe_hwstrip *hwstrip =
1133                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1134         struct ixgbe_dcb_config *dcb_config =
1135                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1136         struct ixgbe_filter_info *filter_info =
1137                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1138         struct ixgbe_bw_conf *bw_conf =
1139                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1140         uint32_t ctrl_ext;
1141         uint16_t csum;
1142         int diag, i;
1143
1144         PMD_INIT_FUNC_TRACE();
1145
1146         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1147         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1148         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1149         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1150
1151         /*
1152          * For secondary processes, we don't initialise any further as primary
1153          * has already done this work. Only check we don't need a different
1154          * RX and TX function.
1155          */
1156         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1157                 struct ixgbe_tx_queue *txq;
1158                 /* TX queue function in primary, set by last queue initialized
1159                  * Tx queue may not initialized by primary process
1160                  */
1161                 if (eth_dev->data->tx_queues) {
1162                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1163                         ixgbe_set_tx_function(eth_dev, txq);
1164                 } else {
1165                         /* Use default TX function if we get here */
1166                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1167                                      "Using default TX function.");
1168                 }
1169
1170                 ixgbe_set_rx_function(eth_dev);
1171
1172                 return 0;
1173         }
1174
1175         rte_eth_copy_pci_info(eth_dev, pci_dev);
1176         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1177
1178         /* Vendor and Device ID need to be set before init of shared code */
1179         hw->device_id = pci_dev->id.device_id;
1180         hw->vendor_id = pci_dev->id.vendor_id;
1181         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1182         hw->allow_unsupported_sfp = 1;
1183
1184         /* Initialize the shared code (base driver) */
1185 #ifdef RTE_NIC_BYPASS
1186         diag = ixgbe_bypass_init_shared_code(hw);
1187 #else
1188         diag = ixgbe_init_shared_code(hw);
1189 #endif /* RTE_NIC_BYPASS */
1190
1191         if (diag != IXGBE_SUCCESS) {
1192                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1193                 return -EIO;
1194         }
1195
1196         /* pick up the PCI bus settings for reporting later */
1197         ixgbe_get_bus_info(hw);
1198
1199         /* Unlock any pending hardware semaphore */
1200         ixgbe_swfw_lock_reset(hw);
1201
1202         /* Initialize DCB configuration*/
1203         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1204         ixgbe_dcb_init(hw, dcb_config);
1205         /* Get Hardware Flow Control setting */
1206         hw->fc.requested_mode = ixgbe_fc_full;
1207         hw->fc.current_mode = ixgbe_fc_full;
1208         hw->fc.pause_time = IXGBE_FC_PAUSE;
1209         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1210                 hw->fc.low_water[i] = IXGBE_FC_LO;
1211                 hw->fc.high_water[i] = IXGBE_FC_HI;
1212         }
1213         hw->fc.send_xon = 1;
1214
1215         /* Make sure we have a good EEPROM before we read from it */
1216         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1217         if (diag != IXGBE_SUCCESS) {
1218                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1219                 return -EIO;
1220         }
1221
1222 #ifdef RTE_NIC_BYPASS
1223         diag = ixgbe_bypass_init_hw(hw);
1224 #else
1225         diag = ixgbe_init_hw(hw);
1226 #endif /* RTE_NIC_BYPASS */
1227
1228         /*
1229          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1230          * is called too soon after the kernel driver unbinding/binding occurs.
1231          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1232          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1233          * also called. See ixgbe_identify_phy_82599(). The reason for the
1234          * failure is not known, and only occuts when virtualisation features
1235          * are disabled in the bios. A delay of 100ms  was found to be enough by
1236          * trial-and-error, and is doubled to be safe.
1237          */
1238         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1239                 rte_delay_ms(200);
1240                 diag = ixgbe_init_hw(hw);
1241         }
1242
1243         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1244                 diag = IXGBE_SUCCESS;
1245
1246         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1247                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1248                              "LOM.  Please be aware there may be issues associated "
1249                              "with your hardware.");
1250                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1251                              "please contact your Intel or hardware representative "
1252                              "who provided you with this hardware.");
1253         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1254                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1255         if (diag) {
1256                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1257                 return -EIO;
1258         }
1259
1260         /* Reset the hw statistics */
1261         ixgbe_dev_stats_reset(eth_dev);
1262
1263         /* disable interrupt */
1264         ixgbe_disable_intr(hw);
1265
1266         /* reset mappings for queue statistics hw counters*/
1267         ixgbe_reset_qstat_mappings(hw);
1268
1269         /* Allocate memory for storing MAC addresses */
1270         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1271                                                hw->mac.num_rar_entries, 0);
1272         if (eth_dev->data->mac_addrs == NULL) {
1273                 PMD_INIT_LOG(ERR,
1274                              "Failed to allocate %u bytes needed to store "
1275                              "MAC addresses",
1276                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1277                 return -ENOMEM;
1278         }
1279         /* Copy the permanent MAC address */
1280         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1281                         &eth_dev->data->mac_addrs[0]);
1282
1283         /* Allocate memory for storing hash filter MAC addresses */
1284         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1285                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1286         if (eth_dev->data->hash_mac_addrs == NULL) {
1287                 PMD_INIT_LOG(ERR,
1288                              "Failed to allocate %d bytes needed to store MAC addresses",
1289                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1290                 return -ENOMEM;
1291         }
1292
1293         /* initialize the vfta */
1294         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1295
1296         /* initialize the hw strip bitmap*/
1297         memset(hwstrip, 0, sizeof(*hwstrip));
1298
1299         /* initialize PF if max_vfs not zero */
1300         ixgbe_pf_host_init(eth_dev);
1301
1302         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1303         /* let hardware know driver is loaded */
1304         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1305         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1306         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1307         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1308         IXGBE_WRITE_FLUSH(hw);
1309
1310         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1311                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1312                              (int) hw->mac.type, (int) hw->phy.type,
1313                              (int) hw->phy.sfp_type);
1314         else
1315                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1316                              (int) hw->mac.type, (int) hw->phy.type);
1317
1318         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1319                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1320                      pci_dev->id.device_id);
1321
1322         rte_intr_callback_register(intr_handle,
1323                                    ixgbe_dev_interrupt_handler, eth_dev);
1324
1325         /* enable uio/vfio intr/eventfd mapping */
1326         rte_intr_enable(intr_handle);
1327
1328         /* enable support intr */
1329         ixgbe_enable_intr(eth_dev);
1330
1331         /* initialize filter info */
1332         memset(filter_info, 0,
1333                sizeof(struct ixgbe_filter_info));
1334
1335         /* initialize 5tuple filter list */
1336         TAILQ_INIT(&filter_info->fivetuple_list);
1337
1338         /* initialize flow director filter list & hash */
1339         ixgbe_fdir_filter_init(eth_dev);
1340
1341         /* initialize l2 tunnel filter list & hash */
1342         ixgbe_l2_tn_filter_init(eth_dev);
1343
1344         TAILQ_INIT(&filter_ntuple_list);
1345         TAILQ_INIT(&filter_ethertype_list);
1346         TAILQ_INIT(&filter_syn_list);
1347         TAILQ_INIT(&filter_fdir_list);
1348         TAILQ_INIT(&filter_l2_tunnel_list);
1349         TAILQ_INIT(&ixgbe_flow_list);
1350
1351         /* initialize bandwidth configuration info */
1352         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1353
1354         return 0;
1355 }
1356
1357 static int
1358 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1359 {
1360         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1361         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1362         struct ixgbe_hw *hw;
1363
1364         PMD_INIT_FUNC_TRACE();
1365
1366         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1367                 return -EPERM;
1368
1369         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1370
1371         if (hw->adapter_stopped == 0)
1372                 ixgbe_dev_close(eth_dev);
1373
1374         eth_dev->dev_ops = NULL;
1375         eth_dev->rx_pkt_burst = NULL;
1376         eth_dev->tx_pkt_burst = NULL;
1377
1378         /* Unlock any pending hardware semaphore */
1379         ixgbe_swfw_lock_reset(hw);
1380
1381         /* disable uio intr before callback unregister */
1382         rte_intr_disable(intr_handle);
1383         rte_intr_callback_unregister(intr_handle,
1384                                      ixgbe_dev_interrupt_handler, eth_dev);
1385
1386         /* uninitialize PF if max_vfs not zero */
1387         ixgbe_pf_host_uninit(eth_dev);
1388
1389         rte_free(eth_dev->data->mac_addrs);
1390         eth_dev->data->mac_addrs = NULL;
1391
1392         rte_free(eth_dev->data->hash_mac_addrs);
1393         eth_dev->data->hash_mac_addrs = NULL;
1394
1395         /* remove all the fdir filters & hash */
1396         ixgbe_fdir_filter_uninit(eth_dev);
1397
1398         /* remove all the L2 tunnel filters & hash */
1399         ixgbe_l2_tn_filter_uninit(eth_dev);
1400
1401         /* Remove all ntuple filters of the device */
1402         ixgbe_ntuple_filter_uninit(eth_dev);
1403
1404         /* clear all the filters list */
1405         ixgbe_filterlist_flush();
1406
1407         return 0;
1408 }
1409
1410 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1411 {
1412         struct ixgbe_filter_info *filter_info =
1413                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1414         struct ixgbe_5tuple_filter *p_5tuple;
1415
1416         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1417                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1418                              p_5tuple,
1419                              entries);
1420                 rte_free(p_5tuple);
1421         }
1422         memset(filter_info->fivetuple_mask, 0,
1423                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1424
1425         return 0;
1426 }
1427
1428 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1429 {
1430         struct ixgbe_hw_fdir_info *fdir_info =
1431                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1432         struct ixgbe_fdir_filter *fdir_filter;
1433
1434                 if (fdir_info->hash_map)
1435                 rte_free(fdir_info->hash_map);
1436         if (fdir_info->hash_handle)
1437                 rte_hash_free(fdir_info->hash_handle);
1438
1439         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1440                 TAILQ_REMOVE(&fdir_info->fdir_list,
1441                              fdir_filter,
1442                              entries);
1443                 rte_free(fdir_filter);
1444         }
1445
1446         return 0;
1447 }
1448
1449 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1450 {
1451         struct ixgbe_l2_tn_info *l2_tn_info =
1452                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1453         struct ixgbe_l2_tn_filter *l2_tn_filter;
1454
1455         if (l2_tn_info->hash_map)
1456                 rte_free(l2_tn_info->hash_map);
1457         if (l2_tn_info->hash_handle)
1458                 rte_hash_free(l2_tn_info->hash_handle);
1459
1460         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1461                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1462                              l2_tn_filter,
1463                              entries);
1464                 rte_free(l2_tn_filter);
1465         }
1466
1467         return 0;
1468 }
1469
1470 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1471 {
1472         struct ixgbe_hw_fdir_info *fdir_info =
1473                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1474         char fdir_hash_name[RTE_HASH_NAMESIZE];
1475         struct rte_hash_parameters fdir_hash_params = {
1476                 .name = fdir_hash_name,
1477                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1478                 .key_len = sizeof(union ixgbe_atr_input),
1479                 .hash_func = rte_hash_crc,
1480                 .hash_func_init_val = 0,
1481                 .socket_id = rte_socket_id(),
1482         };
1483
1484         TAILQ_INIT(&fdir_info->fdir_list);
1485         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1486                  "fdir_%s", eth_dev->data->name);
1487         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1488         if (!fdir_info->hash_handle) {
1489                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1490                 return -EINVAL;
1491         }
1492         fdir_info->hash_map = rte_zmalloc("ixgbe",
1493                                           sizeof(struct ixgbe_fdir_filter *) *
1494                                           IXGBE_MAX_FDIR_FILTER_NUM,
1495                                           0);
1496         if (!fdir_info->hash_map) {
1497                 PMD_INIT_LOG(ERR,
1498                              "Failed to allocate memory for fdir hash map!");
1499                 return -ENOMEM;
1500         }
1501         fdir_info->mask_added = FALSE;
1502
1503         return 0;
1504 }
1505
1506 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1507 {
1508         struct ixgbe_l2_tn_info *l2_tn_info =
1509                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1510         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1511         struct rte_hash_parameters l2_tn_hash_params = {
1512                 .name = l2_tn_hash_name,
1513                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1514                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1515                 .hash_func = rte_hash_crc,
1516                 .hash_func_init_val = 0,
1517                 .socket_id = rte_socket_id(),
1518         };
1519
1520         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1521         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1522                  "l2_tn_%s", eth_dev->data->name);
1523         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1524         if (!l2_tn_info->hash_handle) {
1525                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1526                 return -EINVAL;
1527         }
1528         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1529                                    sizeof(struct ixgbe_l2_tn_filter *) *
1530                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1531                                    0);
1532         if (!l2_tn_info->hash_map) {
1533                 PMD_INIT_LOG(ERR,
1534                         "Failed to allocate memory for L2 TN hash map!");
1535                 return -ENOMEM;
1536         }
1537         l2_tn_info->e_tag_en = FALSE;
1538         l2_tn_info->e_tag_fwd_en = FALSE;
1539         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1540
1541         return 0;
1542 }
1543 /*
1544  * Negotiate mailbox API version with the PF.
1545  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1546  * Then we try to negotiate starting with the most recent one.
1547  * If all negotiation attempts fail, then we will proceed with
1548  * the default one (ixgbe_mbox_api_10).
1549  */
1550 static void
1551 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1552 {
1553         int32_t i;
1554
1555         /* start with highest supported, proceed down */
1556         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1557                 ixgbe_mbox_api_12,
1558                 ixgbe_mbox_api_11,
1559                 ixgbe_mbox_api_10,
1560         };
1561
1562         for (i = 0;
1563                         i != RTE_DIM(sup_ver) &&
1564                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1565                         i++)
1566                 ;
1567 }
1568
1569 static void
1570 generate_random_mac_addr(struct ether_addr *mac_addr)
1571 {
1572         uint64_t random;
1573
1574         /* Set Organizationally Unique Identifier (OUI) prefix. */
1575         mac_addr->addr_bytes[0] = 0x00;
1576         mac_addr->addr_bytes[1] = 0x09;
1577         mac_addr->addr_bytes[2] = 0xC0;
1578         /* Force indication of locally assigned MAC address. */
1579         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1580         /* Generate the last 3 bytes of the MAC address with a random number. */
1581         random = rte_rand();
1582         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1583 }
1584
1585 /*
1586  * Virtual Function device init
1587  */
1588 static int
1589 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1590 {
1591         int diag;
1592         uint32_t tc, tcs;
1593         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1594         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1595         struct ixgbe_hw *hw =
1596                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1597         struct ixgbe_vfta *shadow_vfta =
1598                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1599         struct ixgbe_hwstrip *hwstrip =
1600                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1601         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1602
1603         PMD_INIT_FUNC_TRACE();
1604
1605         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1606         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1607         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1608
1609         /* for secondary processes, we don't initialise any further as primary
1610          * has already done this work. Only check we don't need a different
1611          * RX function
1612          */
1613         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1614                 struct ixgbe_tx_queue *txq;
1615                 /* TX queue function in primary, set by last queue initialized
1616                  * Tx queue may not initialized by primary process
1617                  */
1618                 if (eth_dev->data->tx_queues) {
1619                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1620                         ixgbe_set_tx_function(eth_dev, txq);
1621                 } else {
1622                         /* Use default TX function if we get here */
1623                         PMD_INIT_LOG(NOTICE,
1624                                      "No TX queues configured yet. Using default TX function.");
1625                 }
1626
1627                 ixgbe_set_rx_function(eth_dev);
1628
1629                 return 0;
1630         }
1631
1632         rte_eth_copy_pci_info(eth_dev, pci_dev);
1633         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1634
1635         hw->device_id = pci_dev->id.device_id;
1636         hw->vendor_id = pci_dev->id.vendor_id;
1637         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1638
1639         /* initialize the vfta */
1640         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1641
1642         /* initialize the hw strip bitmap*/
1643         memset(hwstrip, 0, sizeof(*hwstrip));
1644
1645         /* Initialize the shared code (base driver) */
1646         diag = ixgbe_init_shared_code(hw);
1647         if (diag != IXGBE_SUCCESS) {
1648                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1649                 return -EIO;
1650         }
1651
1652         /* init_mailbox_params */
1653         hw->mbx.ops.init_params(hw);
1654
1655         /* Reset the hw statistics */
1656         ixgbevf_dev_stats_reset(eth_dev);
1657
1658         /* Disable the interrupts for VF */
1659         ixgbevf_intr_disable(hw);
1660
1661         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1662         diag = hw->mac.ops.reset_hw(hw);
1663
1664         /*
1665          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1666          * the underlying PF driver has not assigned a MAC address to the VF.
1667          * In this case, assign a random MAC address.
1668          */
1669         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1670                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1671                 return diag;
1672         }
1673
1674         /* negotiate mailbox API version to use with the PF. */
1675         ixgbevf_negotiate_api(hw);
1676
1677         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1678         ixgbevf_get_queues(hw, &tcs, &tc);
1679
1680         /* Allocate memory for storing MAC addresses */
1681         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1682                                                hw->mac.num_rar_entries, 0);
1683         if (eth_dev->data->mac_addrs == NULL) {
1684                 PMD_INIT_LOG(ERR,
1685                              "Failed to allocate %u bytes needed to store "
1686                              "MAC addresses",
1687                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1688                 return -ENOMEM;
1689         }
1690
1691         /* Generate a random MAC address, if none was assigned by PF. */
1692         if (is_zero_ether_addr(perm_addr)) {
1693                 generate_random_mac_addr(perm_addr);
1694                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1695                 if (diag) {
1696                         rte_free(eth_dev->data->mac_addrs);
1697                         eth_dev->data->mac_addrs = NULL;
1698                         return diag;
1699                 }
1700                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1701                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1702                              "%02x:%02x:%02x:%02x:%02x:%02x",
1703                              perm_addr->addr_bytes[0],
1704                              perm_addr->addr_bytes[1],
1705                              perm_addr->addr_bytes[2],
1706                              perm_addr->addr_bytes[3],
1707                              perm_addr->addr_bytes[4],
1708                              perm_addr->addr_bytes[5]);
1709         }
1710
1711         /* Copy the permanent MAC address */
1712         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1713
1714         /* reset the hardware with the new settings */
1715         diag = hw->mac.ops.start_hw(hw);
1716         switch (diag) {
1717         case  0:
1718                 break;
1719
1720         default:
1721                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1722                 return -EIO;
1723         }
1724
1725         rte_intr_callback_register(intr_handle,
1726                                    ixgbevf_dev_interrupt_handler, eth_dev);
1727         rte_intr_enable(intr_handle);
1728         ixgbevf_intr_enable(hw);
1729
1730         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1731                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1732                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1733
1734         return 0;
1735 }
1736
1737 /* Virtual Function device uninit */
1738
1739 static int
1740 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1741 {
1742         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1743         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1744         struct ixgbe_hw *hw;
1745
1746         PMD_INIT_FUNC_TRACE();
1747
1748         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1749                 return -EPERM;
1750
1751         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1752
1753         if (hw->adapter_stopped == 0)
1754                 ixgbevf_dev_close(eth_dev);
1755
1756         eth_dev->dev_ops = NULL;
1757         eth_dev->rx_pkt_burst = NULL;
1758         eth_dev->tx_pkt_burst = NULL;
1759
1760         /* Disable the interrupts for VF */
1761         ixgbevf_intr_disable(hw);
1762
1763         rte_free(eth_dev->data->mac_addrs);
1764         eth_dev->data->mac_addrs = NULL;
1765
1766         rte_intr_disable(intr_handle);
1767         rte_intr_callback_unregister(intr_handle,
1768                                      ixgbevf_dev_interrupt_handler, eth_dev);
1769
1770         return 0;
1771 }
1772
1773 static struct eth_driver rte_ixgbe_pmd = {
1774         .pci_drv = {
1775                 .id_table = pci_id_ixgbe_map,
1776                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1777                 .probe = rte_eth_dev_pci_probe,
1778                 .remove = rte_eth_dev_pci_remove,
1779         },
1780         .eth_dev_init = eth_ixgbe_dev_init,
1781         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1782         .dev_private_size = sizeof(struct ixgbe_adapter),
1783 };
1784
1785 /*
1786  * virtual function driver struct
1787  */
1788 static struct eth_driver rte_ixgbevf_pmd = {
1789         .pci_drv = {
1790                 .id_table = pci_id_ixgbevf_map,
1791                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1792                 .probe = rte_eth_dev_pci_probe,
1793                 .remove = rte_eth_dev_pci_remove,
1794         },
1795         .eth_dev_init = eth_ixgbevf_dev_init,
1796         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1797         .dev_private_size = sizeof(struct ixgbe_adapter),
1798 };
1799
1800 static int
1801 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1802 {
1803         struct ixgbe_hw *hw =
1804                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1805         struct ixgbe_vfta *shadow_vfta =
1806                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1807         uint32_t vfta;
1808         uint32_t vid_idx;
1809         uint32_t vid_bit;
1810
1811         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1812         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1813         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1814         if (on)
1815                 vfta |= vid_bit;
1816         else
1817                 vfta &= ~vid_bit;
1818         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1819
1820         /* update local VFTA copy */
1821         shadow_vfta->vfta[vid_idx] = vfta;
1822
1823         return 0;
1824 }
1825
1826 static void
1827 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1828 {
1829         if (on)
1830                 ixgbe_vlan_hw_strip_enable(dev, queue);
1831         else
1832                 ixgbe_vlan_hw_strip_disable(dev, queue);
1833 }
1834
1835 static int
1836 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1837                     enum rte_vlan_type vlan_type,
1838                     uint16_t tpid)
1839 {
1840         struct ixgbe_hw *hw =
1841                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1842         int ret = 0;
1843         uint32_t reg;
1844         uint32_t qinq;
1845
1846         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1847         qinq &= IXGBE_DMATXCTL_GDV;
1848
1849         switch (vlan_type) {
1850         case ETH_VLAN_TYPE_INNER:
1851                 if (qinq) {
1852                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1853                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1854                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1855                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1856                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1857                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1858                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1859                 } else {
1860                         ret = -ENOTSUP;
1861                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1862                                     " by single VLAN");
1863                 }
1864                 break;
1865         case ETH_VLAN_TYPE_OUTER:
1866                 if (qinq) {
1867                         /* Only the high 16-bits is valid */
1868                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1869                                         IXGBE_EXVET_VET_EXT_SHIFT);
1870                 } else {
1871                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1872                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1873                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1874                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1875                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1876                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1877                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1878                 }
1879
1880                 break;
1881         default:
1882                 ret = -EINVAL;
1883                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1884                 break;
1885         }
1886
1887         return ret;
1888 }
1889
1890 void
1891 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1892 {
1893         struct ixgbe_hw *hw =
1894                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1895         uint32_t vlnctrl;
1896
1897         PMD_INIT_FUNC_TRACE();
1898
1899         /* Filter Table Disable */
1900         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1901         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1902
1903         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1904 }
1905
1906 void
1907 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1908 {
1909         struct ixgbe_hw *hw =
1910                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1911         struct ixgbe_vfta *shadow_vfta =
1912                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1913         uint32_t vlnctrl;
1914         uint16_t i;
1915
1916         PMD_INIT_FUNC_TRACE();
1917
1918         /* Filter Table Enable */
1919         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1920         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1921         vlnctrl |= IXGBE_VLNCTRL_VFE;
1922
1923         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1924
1925         /* write whatever is in local vfta copy */
1926         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1927                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1928 }
1929
1930 static void
1931 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1932 {
1933         struct ixgbe_hwstrip *hwstrip =
1934                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1935         struct ixgbe_rx_queue *rxq;
1936
1937         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1938                 return;
1939
1940         if (on)
1941                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1942         else
1943                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1944
1945         if (queue >= dev->data->nb_rx_queues)
1946                 return;
1947
1948         rxq = dev->data->rx_queues[queue];
1949
1950         if (on)
1951                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1952         else
1953                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1954 }
1955
1956 static void
1957 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1958 {
1959         struct ixgbe_hw *hw =
1960                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1961         uint32_t ctrl;
1962
1963         PMD_INIT_FUNC_TRACE();
1964
1965         if (hw->mac.type == ixgbe_mac_82598EB) {
1966                 /* No queue level support */
1967                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1968                 return;
1969         }
1970
1971         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1972         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1973         ctrl &= ~IXGBE_RXDCTL_VME;
1974         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1975
1976         /* record those setting for HW strip per queue */
1977         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1978 }
1979
1980 static void
1981 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1982 {
1983         struct ixgbe_hw *hw =
1984                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1985         uint32_t ctrl;
1986
1987         PMD_INIT_FUNC_TRACE();
1988
1989         if (hw->mac.type == ixgbe_mac_82598EB) {
1990                 /* No queue level supported */
1991                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1992                 return;
1993         }
1994
1995         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1996         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1997         ctrl |= IXGBE_RXDCTL_VME;
1998         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1999
2000         /* record those setting for HW strip per queue */
2001         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2002 }
2003
2004 void
2005 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2006 {
2007         struct ixgbe_hw *hw =
2008                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2009         uint32_t ctrl;
2010         uint16_t i;
2011         struct ixgbe_rx_queue *rxq;
2012
2013         PMD_INIT_FUNC_TRACE();
2014
2015         if (hw->mac.type == ixgbe_mac_82598EB) {
2016                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2017                 ctrl &= ~IXGBE_VLNCTRL_VME;
2018                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2019         } else {
2020                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2021                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2022                         rxq = dev->data->rx_queues[i];
2023                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2024                         ctrl &= ~IXGBE_RXDCTL_VME;
2025                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2026
2027                         /* record those setting for HW strip per queue */
2028                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2029                 }
2030         }
2031 }
2032
2033 void
2034 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2035 {
2036         struct ixgbe_hw *hw =
2037                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2038         uint32_t ctrl;
2039         uint16_t i;
2040         struct ixgbe_rx_queue *rxq;
2041
2042         PMD_INIT_FUNC_TRACE();
2043
2044         if (hw->mac.type == ixgbe_mac_82598EB) {
2045                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2046                 ctrl |= IXGBE_VLNCTRL_VME;
2047                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2048         } else {
2049                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2050                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2051                         rxq = dev->data->rx_queues[i];
2052                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2053                         ctrl |= IXGBE_RXDCTL_VME;
2054                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2055
2056                         /* record those setting for HW strip per queue */
2057                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2058                 }
2059         }
2060 }
2061
2062 static void
2063 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2064 {
2065         struct ixgbe_hw *hw =
2066                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2067         uint32_t ctrl;
2068
2069         PMD_INIT_FUNC_TRACE();
2070
2071         /* DMATXCTRL: Geric Double VLAN Disable */
2072         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2073         ctrl &= ~IXGBE_DMATXCTL_GDV;
2074         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2075
2076         /* CTRL_EXT: Global Double VLAN Disable */
2077         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2078         ctrl &= ~IXGBE_EXTENDED_VLAN;
2079         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2080
2081 }
2082
2083 static void
2084 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2085 {
2086         struct ixgbe_hw *hw =
2087                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2088         uint32_t ctrl;
2089
2090         PMD_INIT_FUNC_TRACE();
2091
2092         /* DMATXCTRL: Geric Double VLAN Enable */
2093         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2094         ctrl |= IXGBE_DMATXCTL_GDV;
2095         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2096
2097         /* CTRL_EXT: Global Double VLAN Enable */
2098         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2099         ctrl |= IXGBE_EXTENDED_VLAN;
2100         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2101
2102         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2103         if (hw->mac.type == ixgbe_mac_X550 ||
2104             hw->mac.type == ixgbe_mac_X550EM_x ||
2105             hw->mac.type == ixgbe_mac_X550EM_a) {
2106                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2107                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2108                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2109         }
2110
2111         /*
2112          * VET EXT field in the EXVET register = 0x8100 by default
2113          * So no need to change. Same to VT field of DMATXCTL register
2114          */
2115 }
2116
2117 static void
2118 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2119 {
2120         if (mask & ETH_VLAN_STRIP_MASK) {
2121                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2122                         ixgbe_vlan_hw_strip_enable_all(dev);
2123                 else
2124                         ixgbe_vlan_hw_strip_disable_all(dev);
2125         }
2126
2127         if (mask & ETH_VLAN_FILTER_MASK) {
2128                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2129                         ixgbe_vlan_hw_filter_enable(dev);
2130                 else
2131                         ixgbe_vlan_hw_filter_disable(dev);
2132         }
2133
2134         if (mask & ETH_VLAN_EXTEND_MASK) {
2135                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2136                         ixgbe_vlan_hw_extend_enable(dev);
2137                 else
2138                         ixgbe_vlan_hw_extend_disable(dev);
2139         }
2140 }
2141
2142 static void
2143 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2144 {
2145         struct ixgbe_hw *hw =
2146                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2147         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2148         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2149
2150         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2151         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2152 }
2153
2154 static int
2155 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2156 {
2157         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2158
2159         switch (nb_rx_q) {
2160         case 1:
2161         case 2:
2162                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2163                 break;
2164         case 4:
2165                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2166                 break;
2167         default:
2168                 return -EINVAL;
2169         }
2170
2171         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2172         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2173
2174         return 0;
2175 }
2176
2177 static int
2178 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2179 {
2180         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2181         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2182         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2183         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2184
2185         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2186                 /* check multi-queue mode */
2187                 switch (dev_conf->rxmode.mq_mode) {
2188                 case ETH_MQ_RX_VMDQ_DCB:
2189                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2190                         break;
2191                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2192                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2193                         PMD_INIT_LOG(ERR, "SRIOV active,"
2194                                         " unsupported mq_mode rx %d.",
2195                                         dev_conf->rxmode.mq_mode);
2196                         return -EINVAL;
2197                 case ETH_MQ_RX_RSS:
2198                 case ETH_MQ_RX_VMDQ_RSS:
2199                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2200                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2201                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2202                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2203                                                 " invalid queue number"
2204                                                 " for VMDQ RSS, allowed"
2205                                                 " value are 1, 2 or 4.");
2206                                         return -EINVAL;
2207                                 }
2208                         break;
2209                 case ETH_MQ_RX_VMDQ_ONLY:
2210                 case ETH_MQ_RX_NONE:
2211                         /* if nothing mq mode configure, use default scheme */
2212                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2213                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2214                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2215                         break;
2216                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2217                         /* SRIOV only works in VMDq enable mode */
2218                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2219                                         " wrong mq_mode rx %d.",
2220                                         dev_conf->rxmode.mq_mode);
2221                         return -EINVAL;
2222                 }
2223
2224                 switch (dev_conf->txmode.mq_mode) {
2225                 case ETH_MQ_TX_VMDQ_DCB:
2226                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2227                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2228                         break;
2229                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2230                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2231                         break;
2232                 }
2233
2234                 /* check valid queue number */
2235                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2236                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2237                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2238                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2239                                         " must be less than or equal to %d.",
2240                                         nb_rx_q, nb_tx_q,
2241                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2242                         return -EINVAL;
2243                 }
2244         } else {
2245                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2246                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2247                                           " not supported.");
2248                         return -EINVAL;
2249                 }
2250                 /* check configuration for vmdb+dcb mode */
2251                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2252                         const struct rte_eth_vmdq_dcb_conf *conf;
2253
2254                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2255                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2256                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2257                                 return -EINVAL;
2258                         }
2259                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2260                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2261                                conf->nb_queue_pools == ETH_32_POOLS)) {
2262                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2263                                                 " nb_queue_pools must be %d or %d.",
2264                                                 ETH_16_POOLS, ETH_32_POOLS);
2265                                 return -EINVAL;
2266                         }
2267                 }
2268                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2269                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2270
2271                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2272                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2273                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2274                                 return -EINVAL;
2275                         }
2276                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2277                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2278                                conf->nb_queue_pools == ETH_32_POOLS)) {
2279                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2280                                                 " nb_queue_pools != %d and"
2281                                                 " nb_queue_pools != %d.",
2282                                                 ETH_16_POOLS, ETH_32_POOLS);
2283                                 return -EINVAL;
2284                         }
2285                 }
2286
2287                 /* For DCB mode check our configuration before we go further */
2288                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2289                         const struct rte_eth_dcb_rx_conf *conf;
2290
2291                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2292                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2293                                                  IXGBE_DCB_NB_QUEUES);
2294                                 return -EINVAL;
2295                         }
2296                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2297                         if (!(conf->nb_tcs == ETH_4_TCS ||
2298                                conf->nb_tcs == ETH_8_TCS)) {
2299                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2300                                                 " and nb_tcs != %d.",
2301                                                 ETH_4_TCS, ETH_8_TCS);
2302                                 return -EINVAL;
2303                         }
2304                 }
2305
2306                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2307                         const struct rte_eth_dcb_tx_conf *conf;
2308
2309                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2310                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2311                                                  IXGBE_DCB_NB_QUEUES);
2312                                 return -EINVAL;
2313                         }
2314                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2315                         if (!(conf->nb_tcs == ETH_4_TCS ||
2316                                conf->nb_tcs == ETH_8_TCS)) {
2317                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2318                                                 " and nb_tcs != %d.",
2319                                                 ETH_4_TCS, ETH_8_TCS);
2320                                 return -EINVAL;
2321                         }
2322                 }
2323
2324                 /*
2325                  * When DCB/VT is off, maximum number of queues changes,
2326                  * except for 82598EB, which remains constant.
2327                  */
2328                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2329                                 hw->mac.type != ixgbe_mac_82598EB) {
2330                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2331                                 PMD_INIT_LOG(ERR,
2332                                              "Neither VT nor DCB are enabled, "
2333                                              "nb_tx_q > %d.",
2334                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2335                                 return -EINVAL;
2336                         }
2337                 }
2338         }
2339         return 0;
2340 }
2341
2342 static int
2343 ixgbe_dev_configure(struct rte_eth_dev *dev)
2344 {
2345         struct ixgbe_interrupt *intr =
2346                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2347         struct ixgbe_adapter *adapter =
2348                 (struct ixgbe_adapter *)dev->data->dev_private;
2349         int ret;
2350
2351         PMD_INIT_FUNC_TRACE();
2352         /* multipe queue mode checking */
2353         ret  = ixgbe_check_mq_mode(dev);
2354         if (ret != 0) {
2355                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2356                             ret);
2357                 return ret;
2358         }
2359
2360         /* set flag to update link status after init */
2361         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2362
2363         /*
2364          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2365          * allocation or vector Rx preconditions we will reset it.
2366          */
2367         adapter->rx_bulk_alloc_allowed = true;
2368         adapter->rx_vec_allowed = true;
2369
2370         return 0;
2371 }
2372
2373 static void
2374 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2375 {
2376         struct ixgbe_hw *hw =
2377                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2378         struct ixgbe_interrupt *intr =
2379                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2380         uint32_t gpie;
2381
2382         /* only set up it on X550EM_X */
2383         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2384                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2385                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2386                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2387                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2388                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2389         }
2390 }
2391
2392 /*
2393  * Configure device link speed and setup link.
2394  * It returns 0 on success.
2395  */
2396 static int
2397 ixgbe_dev_start(struct rte_eth_dev *dev)
2398 {
2399         struct ixgbe_hw *hw =
2400                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2401         struct ixgbe_vf_info *vfinfo =
2402                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2403         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2404         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2405         uint32_t intr_vector = 0;
2406         int err, link_up = 0, negotiate = 0;
2407         uint32_t speed = 0;
2408         int mask = 0;
2409         int status;
2410         uint16_t vf, idx;
2411         uint32_t *link_speeds;
2412
2413         PMD_INIT_FUNC_TRACE();
2414
2415         /* IXGBE devices don't support:
2416         *    - half duplex (checked afterwards for valid speeds)
2417         *    - fixed speed: TODO implement
2418         */
2419         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2420                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2421                              dev->data->port_id);
2422                 return -EINVAL;
2423         }
2424
2425         /* disable uio/vfio intr/eventfd mapping */
2426         rte_intr_disable(intr_handle);
2427
2428         /* stop adapter */
2429         hw->adapter_stopped = 0;
2430         ixgbe_stop_adapter(hw);
2431
2432         /* reinitialize adapter
2433          * this calls reset and start
2434          */
2435         status = ixgbe_pf_reset_hw(hw);
2436         if (status != 0)
2437                 return -1;
2438         hw->mac.ops.start_hw(hw);
2439         hw->mac.get_link_status = true;
2440
2441         /* configure PF module if SRIOV enabled */
2442         ixgbe_pf_host_configure(dev);
2443
2444         ixgbe_dev_phy_intr_setup(dev);
2445
2446         /* check and configure queue intr-vector mapping */
2447         if ((rte_intr_cap_multiple(intr_handle) ||
2448              !RTE_ETH_DEV_SRIOV(dev).active) &&
2449             dev->data->dev_conf.intr_conf.rxq != 0) {
2450                 intr_vector = dev->data->nb_rx_queues;
2451                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2452                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2453                                         IXGBE_MAX_INTR_QUEUE_NUM);
2454                         return -ENOTSUP;
2455                 }
2456                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2457                         return -1;
2458         }
2459
2460         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2461                 intr_handle->intr_vec =
2462                         rte_zmalloc("intr_vec",
2463                                     dev->data->nb_rx_queues * sizeof(int), 0);
2464                 if (intr_handle->intr_vec == NULL) {
2465                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2466                                      " intr_vec", dev->data->nb_rx_queues);
2467                         return -ENOMEM;
2468                 }
2469         }
2470
2471         /* confiugre msix for sleep until rx interrupt */
2472         ixgbe_configure_msix(dev);
2473
2474         /* initialize transmission unit */
2475         ixgbe_dev_tx_init(dev);
2476
2477         /* This can fail when allocating mbufs for descriptor rings */
2478         err = ixgbe_dev_rx_init(dev);
2479         if (err) {
2480                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2481                 goto error;
2482         }
2483
2484     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2485                 ETH_VLAN_EXTEND_MASK;
2486         ixgbe_vlan_offload_set(dev, mask);
2487
2488         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2489                 /* Enable vlan filtering for VMDq */
2490                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2491         }
2492
2493         /* Configure DCB hw */
2494         ixgbe_configure_dcb(dev);
2495
2496         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2497                 err = ixgbe_fdir_configure(dev);
2498                 if (err)
2499                         goto error;
2500         }
2501
2502         /* Restore vf rate limit */
2503         if (vfinfo != NULL) {
2504                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2505                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2506                                 if (vfinfo[vf].tx_rate[idx] != 0)
2507                                         rte_pmd_ixgbe_set_vf_rate_limit(
2508                                                 dev->data->port_id, vf,
2509                                                 vfinfo[vf].tx_rate[idx],
2510                                                 1 << idx);
2511         }
2512
2513         ixgbe_restore_statistics_mapping(dev);
2514
2515         err = ixgbe_dev_rxtx_start(dev);
2516         if (err < 0) {
2517                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2518                 goto error;
2519         }
2520
2521         /* Skip link setup if loopback mode is enabled for 82599. */
2522         if (hw->mac.type == ixgbe_mac_82599EB &&
2523                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2524                 goto skip_link_setup;
2525
2526         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2527                 err = hw->mac.ops.setup_sfp(hw);
2528                 if (err)
2529                         goto error;
2530         }
2531
2532         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2533                 /* Turn on the copper */
2534                 ixgbe_set_phy_power(hw, true);
2535         } else {
2536                 /* Turn on the laser */
2537                 ixgbe_enable_tx_laser(hw);
2538         }
2539
2540         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2541         if (err)
2542                 goto error;
2543         dev->data->dev_link.link_status = link_up;
2544
2545         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2546         if (err)
2547                 goto error;
2548
2549         link_speeds = &dev->data->dev_conf.link_speeds;
2550         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2551                         ETH_LINK_SPEED_10G)) {
2552                 PMD_INIT_LOG(ERR, "Invalid link setting");
2553                 goto error;
2554         }
2555
2556         speed = 0x0;
2557         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2558                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2559                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2560                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2561         } else {
2562                 if (*link_speeds & ETH_LINK_SPEED_10G)
2563                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2564                 if (*link_speeds & ETH_LINK_SPEED_1G)
2565                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2566                 if (*link_speeds & ETH_LINK_SPEED_100M)
2567                         speed |= IXGBE_LINK_SPEED_100_FULL;
2568         }
2569
2570         err = ixgbe_setup_link(hw, speed, link_up);
2571         if (err)
2572                 goto error;
2573
2574 skip_link_setup:
2575
2576         if (rte_intr_allow_others(intr_handle)) {
2577                 /* check if lsc interrupt is enabled */
2578                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2579                         ixgbe_dev_lsc_interrupt_setup(dev);
2580                 ixgbe_dev_macsec_interrupt_setup(dev);
2581         } else {
2582                 rte_intr_callback_unregister(intr_handle,
2583                                              ixgbe_dev_interrupt_handler, dev);
2584                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2585                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2586                                      " no intr multiplex");
2587         }
2588
2589         /* check if rxq interrupt is enabled */
2590         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2591             rte_intr_dp_is_en(intr_handle))
2592                 ixgbe_dev_rxq_interrupt_setup(dev);
2593
2594         /* enable uio/vfio intr/eventfd mapping */
2595         rte_intr_enable(intr_handle);
2596
2597         /* resume enabled intr since hw reset */
2598         ixgbe_enable_intr(dev);
2599         ixgbe_l2_tunnel_conf(dev);
2600         ixgbe_filter_restore(dev);
2601
2602         return 0;
2603
2604 error:
2605         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2606         ixgbe_dev_clear_queues(dev);
2607         return -EIO;
2608 }
2609
2610 /*
2611  * Stop device: disable rx and tx functions to allow for reconfiguring.
2612  */
2613 static void
2614 ixgbe_dev_stop(struct rte_eth_dev *dev)
2615 {
2616         struct rte_eth_link link;
2617         struct ixgbe_hw *hw =
2618                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2619         struct ixgbe_vf_info *vfinfo =
2620                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2621         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2622         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2623         int vf;
2624
2625         PMD_INIT_FUNC_TRACE();
2626
2627         /* disable interrupts */
2628         ixgbe_disable_intr(hw);
2629
2630         /* reset the NIC */
2631         ixgbe_pf_reset_hw(hw);
2632         hw->adapter_stopped = 0;
2633
2634         /* stop adapter */
2635         ixgbe_stop_adapter(hw);
2636
2637         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2638                 vfinfo[vf].clear_to_send = false;
2639
2640         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2641                 /* Turn off the copper */
2642                 ixgbe_set_phy_power(hw, false);
2643         } else {
2644                 /* Turn off the laser */
2645                 ixgbe_disable_tx_laser(hw);
2646         }
2647
2648         ixgbe_dev_clear_queues(dev);
2649
2650         /* Clear stored conf */
2651         dev->data->scattered_rx = 0;
2652         dev->data->lro = 0;
2653
2654         /* Clear recorded link status */
2655         memset(&link, 0, sizeof(link));
2656         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2657
2658         if (!rte_intr_allow_others(intr_handle))
2659                 /* resume to the default handler */
2660                 rte_intr_callback_register(intr_handle,
2661                                            ixgbe_dev_interrupt_handler,
2662                                            (void *)dev);
2663
2664         /* Clean datapath event and queue/vec mapping */
2665         rte_intr_efd_disable(intr_handle);
2666         if (intr_handle->intr_vec != NULL) {
2667                 rte_free(intr_handle->intr_vec);
2668                 intr_handle->intr_vec = NULL;
2669         }
2670 }
2671
2672 /*
2673  * Set device link up: enable tx.
2674  */
2675 static int
2676 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2677 {
2678         struct ixgbe_hw *hw =
2679                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2680         if (hw->mac.type == ixgbe_mac_82599EB) {
2681 #ifdef RTE_NIC_BYPASS
2682                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2683                         /* Not suported in bypass mode */
2684                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2685                                      "by device id 0x%x", hw->device_id);
2686                         return -ENOTSUP;
2687                 }
2688 #endif
2689         }
2690
2691         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2692                 /* Turn on the copper */
2693                 ixgbe_set_phy_power(hw, true);
2694         } else {
2695                 /* Turn on the laser */
2696                 ixgbe_enable_tx_laser(hw);
2697         }
2698
2699         return 0;
2700 }
2701
2702 /*
2703  * Set device link down: disable tx.
2704  */
2705 static int
2706 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2707 {
2708         struct ixgbe_hw *hw =
2709                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2710         if (hw->mac.type == ixgbe_mac_82599EB) {
2711 #ifdef RTE_NIC_BYPASS
2712                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2713                         /* Not suported in bypass mode */
2714                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2715                                      "by device id 0x%x", hw->device_id);
2716                         return -ENOTSUP;
2717                 }
2718 #endif
2719         }
2720
2721         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2722                 /* Turn off the copper */
2723                 ixgbe_set_phy_power(hw, false);
2724         } else {
2725                 /* Turn off the laser */
2726                 ixgbe_disable_tx_laser(hw);
2727         }
2728
2729         return 0;
2730 }
2731
2732 /*
2733  * Reest and stop device.
2734  */
2735 static void
2736 ixgbe_dev_close(struct rte_eth_dev *dev)
2737 {
2738         struct ixgbe_hw *hw =
2739                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2740
2741         PMD_INIT_FUNC_TRACE();
2742
2743         ixgbe_pf_reset_hw(hw);
2744
2745         ixgbe_dev_stop(dev);
2746         hw->adapter_stopped = 1;
2747
2748         ixgbe_dev_free_queues(dev);
2749
2750         ixgbe_disable_pcie_master(hw);
2751
2752         /* reprogram the RAR[0] in case user changed it. */
2753         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2754 }
2755
2756 static void
2757 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2758                            struct ixgbe_hw_stats *hw_stats,
2759                            struct ixgbe_macsec_stats *macsec_stats,
2760                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2761                            uint64_t *total_qprc, uint64_t *total_qprdc)
2762 {
2763         uint32_t bprc, lxon, lxoff, total;
2764         uint32_t delta_gprc = 0;
2765         unsigned i;
2766         /* Workaround for RX byte count not including CRC bytes when CRC
2767          * strip is enabled. CRC bytes are removed from counters when crc_strip
2768          * is disabled.
2769          */
2770         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2771                         IXGBE_HLREG0_RXCRCSTRP);
2772
2773         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2774         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2775         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2776         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2777
2778         for (i = 0; i < 8; i++) {
2779                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2780
2781                 /* global total per queue */
2782                 hw_stats->mpc[i] += mp;
2783                 /* Running comprehensive total for stats display */
2784                 *total_missed_rx += hw_stats->mpc[i];
2785                 if (hw->mac.type == ixgbe_mac_82598EB) {
2786                         hw_stats->rnbc[i] +=
2787                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2788                         hw_stats->pxonrxc[i] +=
2789                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2790                         hw_stats->pxoffrxc[i] +=
2791                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2792                 } else {
2793                         hw_stats->pxonrxc[i] +=
2794                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2795                         hw_stats->pxoffrxc[i] +=
2796                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2797                         hw_stats->pxon2offc[i] +=
2798                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2799                 }
2800                 hw_stats->pxontxc[i] +=
2801                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2802                 hw_stats->pxofftxc[i] +=
2803                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2804         }
2805         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2806                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2807                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2808                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2809
2810                 delta_gprc += delta_qprc;
2811
2812                 hw_stats->qprc[i] += delta_qprc;
2813                 hw_stats->qptc[i] += delta_qptc;
2814
2815                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2816                 hw_stats->qbrc[i] +=
2817                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2818                 if (crc_strip == 0)
2819                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2820
2821                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2822                 hw_stats->qbtc[i] +=
2823                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2824
2825                 hw_stats->qprdc[i] += delta_qprdc;
2826                 *total_qprdc += hw_stats->qprdc[i];
2827
2828                 *total_qprc += hw_stats->qprc[i];
2829                 *total_qbrc += hw_stats->qbrc[i];
2830         }
2831         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2832         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2833         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2834
2835         /*
2836          * An errata states that gprc actually counts good + missed packets:
2837          * Workaround to set gprc to summated queue packet receives
2838          */
2839         hw_stats->gprc = *total_qprc;
2840
2841         if (hw->mac.type != ixgbe_mac_82598EB) {
2842                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2843                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2844                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2845                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2846                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2847                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2848                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2849                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2850         } else {
2851                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2852                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2853                 /* 82598 only has a counter in the high register */
2854                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2855                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2856                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2857         }
2858         uint64_t old_tpr = hw_stats->tpr;
2859
2860         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2861         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2862
2863         if (crc_strip == 0)
2864                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2865
2866         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2867         hw_stats->gptc += delta_gptc;
2868         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2869         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2870
2871         /*
2872          * Workaround: mprc hardware is incorrectly counting
2873          * broadcasts, so for now we subtract those.
2874          */
2875         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2876         hw_stats->bprc += bprc;
2877         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2878         if (hw->mac.type == ixgbe_mac_82598EB)
2879                 hw_stats->mprc -= bprc;
2880
2881         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2882         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2883         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2884         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2885         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2886         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2887
2888         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2889         hw_stats->lxontxc += lxon;
2890         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2891         hw_stats->lxofftxc += lxoff;
2892         total = lxon + lxoff;
2893
2894         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2895         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2896         hw_stats->gptc -= total;
2897         hw_stats->mptc -= total;
2898         hw_stats->ptc64 -= total;
2899         hw_stats->gotc -= total * ETHER_MIN_LEN;
2900
2901         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2902         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2903         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2904         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2905         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2906         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2907         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2908         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2909         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2910         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2911         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2912         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2913         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2914         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2915         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2916         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2917         /* Only read FCOE on 82599 */
2918         if (hw->mac.type != ixgbe_mac_82598EB) {
2919                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2920                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2921                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2922                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2923                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2924         }
2925
2926         /* Flow Director Stats registers */
2927         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2928         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2929
2930         /* MACsec Stats registers */
2931         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2932         macsec_stats->out_pkts_encrypted +=
2933                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2934         macsec_stats->out_pkts_protected +=
2935                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2936         macsec_stats->out_octets_encrypted +=
2937                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2938         macsec_stats->out_octets_protected +=
2939                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2940         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2941         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2942         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2943         macsec_stats->in_pkts_unknownsci +=
2944                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2945         macsec_stats->in_octets_decrypted +=
2946                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2947         macsec_stats->in_octets_validated +=
2948                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2949         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2950         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2951         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2952         for (i = 0; i < 2; i++) {
2953                 macsec_stats->in_pkts_ok +=
2954                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2955                 macsec_stats->in_pkts_invalid +=
2956                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2957                 macsec_stats->in_pkts_notvalid +=
2958                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2959         }
2960         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2961         macsec_stats->in_pkts_notusingsa +=
2962                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2963 }
2964
2965 /*
2966  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2967  */
2968 static void
2969 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2970 {
2971         struct ixgbe_hw *hw =
2972                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2973         struct ixgbe_hw_stats *hw_stats =
2974                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2975         struct ixgbe_macsec_stats *macsec_stats =
2976                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2977                                 dev->data->dev_private);
2978         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2979         unsigned i;
2980
2981         total_missed_rx = 0;
2982         total_qbrc = 0;
2983         total_qprc = 0;
2984         total_qprdc = 0;
2985
2986         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2987                         &total_qbrc, &total_qprc, &total_qprdc);
2988
2989         if (stats == NULL)
2990                 return;
2991
2992         /* Fill out the rte_eth_stats statistics structure */
2993         stats->ipackets = total_qprc;
2994         stats->ibytes = total_qbrc;
2995         stats->opackets = hw_stats->gptc;
2996         stats->obytes = hw_stats->gotc;
2997
2998         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2999                 stats->q_ipackets[i] = hw_stats->qprc[i];
3000                 stats->q_opackets[i] = hw_stats->qptc[i];
3001                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3002                 stats->q_obytes[i] = hw_stats->qbtc[i];
3003                 stats->q_errors[i] = hw_stats->qprdc[i];
3004         }
3005
3006         /* Rx Errors */
3007         stats->imissed  = total_missed_rx;
3008         stats->ierrors  = hw_stats->crcerrs +
3009                           hw_stats->mspdc +
3010                           hw_stats->rlec +
3011                           hw_stats->ruc +
3012                           hw_stats->roc +
3013                           hw_stats->illerrc +
3014                           hw_stats->errbc +
3015                           hw_stats->rfc +
3016                           hw_stats->fccrc +
3017                           hw_stats->fclast;
3018
3019         /* Tx Errors */
3020         stats->oerrors  = 0;
3021 }
3022
3023 static void
3024 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3025 {
3026         struct ixgbe_hw_stats *stats =
3027                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3028
3029         /* HW registers are cleared on read */
3030         ixgbe_dev_stats_get(dev, NULL);
3031
3032         /* Reset software totals */
3033         memset(stats, 0, sizeof(*stats));
3034 }
3035
3036 /* This function calculates the number of xstats based on the current config */
3037 static unsigned
3038 ixgbe_xstats_calc_num(void) {
3039         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3040                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3041                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3042 }
3043
3044 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3045         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
3046 {
3047         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3048         unsigned stat, i, count;
3049
3050         if (xstats_names != NULL) {
3051                 count = 0;
3052
3053                 /* Note: limit >= cnt_stats checked upstream
3054                  * in rte_eth_xstats_names()
3055                  */
3056
3057                 /* Extended stats from ixgbe_hw_stats */
3058                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3059                         snprintf(xstats_names[count].name,
3060                                 sizeof(xstats_names[count].name),
3061                                 "%s",
3062                                 rte_ixgbe_stats_strings[i].name);
3063                         count++;
3064                 }
3065
3066                 /* MACsec Stats */
3067                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3068                         snprintf(xstats_names[count].name,
3069                                 sizeof(xstats_names[count].name),
3070                                 "%s",
3071                                 rte_ixgbe_macsec_strings[i].name);
3072                         count++;
3073                 }
3074
3075                 /* RX Priority Stats */
3076                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3077                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3078                                 snprintf(xstats_names[count].name,
3079                                         sizeof(xstats_names[count].name),
3080                                         "rx_priority%u_%s", i,
3081                                         rte_ixgbe_rxq_strings[stat].name);
3082                                 count++;
3083                         }
3084                 }
3085
3086                 /* TX Priority Stats */
3087                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3088                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3089                                 snprintf(xstats_names[count].name,
3090                                         sizeof(xstats_names[count].name),
3091                                         "tx_priority%u_%s", i,
3092                                         rte_ixgbe_txq_strings[stat].name);
3093                                 count++;
3094                         }
3095                 }
3096         }
3097         return cnt_stats;
3098 }
3099
3100 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3101         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3102 {
3103         unsigned i;
3104
3105         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3106                 return -ENOMEM;
3107
3108         if (xstats_names != NULL)
3109                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3110                         snprintf(xstats_names[i].name,
3111                                 sizeof(xstats_names[i].name),
3112                                 "%s", rte_ixgbevf_stats_strings[i].name);
3113         return IXGBEVF_NB_XSTATS;
3114 }
3115
3116 static int
3117 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3118                                          unsigned n)
3119 {
3120         struct ixgbe_hw *hw =
3121                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3122         struct ixgbe_hw_stats *hw_stats =
3123                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3124         struct ixgbe_macsec_stats *macsec_stats =
3125                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3126                                 dev->data->dev_private);
3127         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3128         unsigned i, stat, count = 0;
3129
3130         count = ixgbe_xstats_calc_num();
3131
3132         if (n < count)
3133                 return count;
3134
3135         total_missed_rx = 0;
3136         total_qbrc = 0;
3137         total_qprc = 0;
3138         total_qprdc = 0;
3139
3140         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3141                         &total_qbrc, &total_qprc, &total_qprdc);
3142
3143         /* If this is a reset xstats is NULL, and we have cleared the
3144          * registers by reading them.
3145          */
3146         if (!xstats)
3147                 return 0;
3148
3149         /* Extended stats from ixgbe_hw_stats */
3150         count = 0;
3151         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3152                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3153                                 rte_ixgbe_stats_strings[i].offset);
3154                 xstats[count].id = count;
3155                 count++;
3156         }
3157
3158         /* MACsec Stats */
3159         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3160                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3161                                 rte_ixgbe_macsec_strings[i].offset);
3162                 xstats[count].id = count;
3163                 count++;
3164         }
3165
3166         /* RX Priority Stats */
3167         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3168                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3169                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3170                                         rte_ixgbe_rxq_strings[stat].offset +
3171                                         (sizeof(uint64_t) * i));
3172                         xstats[count].id = count;
3173                         count++;
3174                 }
3175         }
3176
3177         /* TX Priority Stats */
3178         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3179                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3180                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3181                                         rte_ixgbe_txq_strings[stat].offset +
3182                                         (sizeof(uint64_t) * i));
3183                         xstats[count].id = count;
3184                         count++;
3185                 }
3186         }
3187         return count;
3188 }
3189
3190 static void
3191 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3192 {
3193         struct ixgbe_hw_stats *stats =
3194                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3195         struct ixgbe_macsec_stats *macsec_stats =
3196                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3197                                 dev->data->dev_private);
3198
3199         unsigned count = ixgbe_xstats_calc_num();
3200
3201         /* HW registers are cleared on read */
3202         ixgbe_dev_xstats_get(dev, NULL, count);
3203
3204         /* Reset software totals */
3205         memset(stats, 0, sizeof(*stats));
3206         memset(macsec_stats, 0, sizeof(*macsec_stats));
3207 }
3208
3209 static void
3210 ixgbevf_update_stats(struct rte_eth_dev *dev)
3211 {
3212         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3213         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3214                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3215
3216         /* Good Rx packet, include VF loopback */
3217         UPDATE_VF_STAT(IXGBE_VFGPRC,
3218             hw_stats->last_vfgprc, hw_stats->vfgprc);
3219
3220         /* Good Rx octets, include VF loopback */
3221         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3222             hw_stats->last_vfgorc, hw_stats->vfgorc);
3223
3224         /* Good Tx packet, include VF loopback */
3225         UPDATE_VF_STAT(IXGBE_VFGPTC,
3226             hw_stats->last_vfgptc, hw_stats->vfgptc);
3227
3228         /* Good Tx octets, include VF loopback */
3229         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3230             hw_stats->last_vfgotc, hw_stats->vfgotc);
3231
3232         /* Rx Multicst Packet */
3233         UPDATE_VF_STAT(IXGBE_VFMPRC,
3234             hw_stats->last_vfmprc, hw_stats->vfmprc);
3235 }
3236
3237 static int
3238 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3239                        unsigned n)
3240 {
3241         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3242                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3243         unsigned i;
3244
3245         if (n < IXGBEVF_NB_XSTATS)
3246                 return IXGBEVF_NB_XSTATS;
3247
3248         ixgbevf_update_stats(dev);
3249
3250         if (!xstats)
3251                 return 0;
3252
3253         /* Extended stats */
3254         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3255                 xstats[i].id = i;
3256                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3257                         rte_ixgbevf_stats_strings[i].offset);
3258         }
3259
3260         return IXGBEVF_NB_XSTATS;
3261 }
3262
3263 static void
3264 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3265 {
3266         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3267                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3268
3269         ixgbevf_update_stats(dev);
3270
3271         if (stats == NULL)
3272                 return;
3273
3274         stats->ipackets = hw_stats->vfgprc;
3275         stats->ibytes = hw_stats->vfgorc;
3276         stats->opackets = hw_stats->vfgptc;
3277         stats->obytes = hw_stats->vfgotc;
3278 }
3279
3280 static void
3281 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3282 {
3283         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3284                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3285
3286         /* Sync HW register to the last stats */
3287         ixgbevf_dev_stats_get(dev, NULL);
3288
3289         /* reset HW current stats*/
3290         hw_stats->vfgprc = 0;
3291         hw_stats->vfgorc = 0;
3292         hw_stats->vfgptc = 0;
3293         hw_stats->vfgotc = 0;
3294 }
3295
3296 static int
3297 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3298 {
3299         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3300         u16 eeprom_verh, eeprom_verl;
3301         u32 etrack_id;
3302         int ret;
3303
3304         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3305         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3306
3307         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3308         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3309
3310         ret += 1; /* add the size of '\0' */
3311         if (fw_size < (u32)ret)
3312                 return ret;
3313         else
3314                 return 0;
3315 }
3316
3317 static void
3318 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3319 {
3320         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3321         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3322         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3323
3324         dev_info->pci_dev = pci_dev;
3325         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3326         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3327         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3328                 /*
3329                  * When DCB/VT is off, maximum number of queues changes,
3330                  * except for 82598EB, which remains constant.
3331                  */
3332                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3333                                 hw->mac.type != ixgbe_mac_82598EB)
3334                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3335         }
3336         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3337         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3338         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3339         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3340         dev_info->max_vfs = pci_dev->max_vfs;
3341         if (hw->mac.type == ixgbe_mac_82598EB)
3342                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3343         else
3344                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3345         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3346         dev_info->rx_offload_capa =
3347                 DEV_RX_OFFLOAD_VLAN_STRIP |
3348                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3349                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3350                 DEV_RX_OFFLOAD_TCP_CKSUM;
3351
3352         /*
3353          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3354          * mode.
3355          */
3356         if ((hw->mac.type == ixgbe_mac_82599EB ||
3357              hw->mac.type == ixgbe_mac_X540) &&
3358             !RTE_ETH_DEV_SRIOV(dev).active)
3359                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3360
3361         if (hw->mac.type == ixgbe_mac_82599EB ||
3362             hw->mac.type == ixgbe_mac_X540)
3363                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3364
3365         if (hw->mac.type == ixgbe_mac_X550 ||
3366             hw->mac.type == ixgbe_mac_X550EM_x ||
3367             hw->mac.type == ixgbe_mac_X550EM_a)
3368                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3369
3370         dev_info->tx_offload_capa =
3371                 DEV_TX_OFFLOAD_VLAN_INSERT |
3372                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3373                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3374                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3375                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3376                 DEV_TX_OFFLOAD_TCP_TSO;
3377
3378         if (hw->mac.type == ixgbe_mac_82599EB ||
3379             hw->mac.type == ixgbe_mac_X540)
3380                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3381
3382         if (hw->mac.type == ixgbe_mac_X550 ||
3383             hw->mac.type == ixgbe_mac_X550EM_x ||
3384             hw->mac.type == ixgbe_mac_X550EM_a)
3385                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3386
3387         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3388                 .rx_thresh = {
3389                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3390                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3391                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3392                 },
3393                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3394                 .rx_drop_en = 0,
3395         };
3396
3397         dev_info->default_txconf = (struct rte_eth_txconf) {
3398                 .tx_thresh = {
3399                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3400                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3401                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3402                 },
3403                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3404                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3405                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3406                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3407         };
3408
3409         dev_info->rx_desc_lim = rx_desc_lim;
3410         dev_info->tx_desc_lim = tx_desc_lim;
3411
3412         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3413         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3414         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3415
3416         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3417         if (hw->mac.type == ixgbe_mac_X540 ||
3418             hw->mac.type == ixgbe_mac_X540_vf ||
3419             hw->mac.type == ixgbe_mac_X550 ||
3420             hw->mac.type == ixgbe_mac_X550_vf) {
3421                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3422         }
3423 }
3424
3425 static const uint32_t *
3426 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3427 {
3428         static const uint32_t ptypes[] = {
3429                 /* For non-vec functions,
3430                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3431                  * for vec functions,
3432                  * refers to _recv_raw_pkts_vec().
3433                  */
3434                 RTE_PTYPE_L2_ETHER,
3435                 RTE_PTYPE_L3_IPV4,
3436                 RTE_PTYPE_L3_IPV4_EXT,
3437                 RTE_PTYPE_L3_IPV6,
3438                 RTE_PTYPE_L3_IPV6_EXT,
3439                 RTE_PTYPE_L4_SCTP,
3440                 RTE_PTYPE_L4_TCP,
3441                 RTE_PTYPE_L4_UDP,
3442                 RTE_PTYPE_TUNNEL_IP,
3443                 RTE_PTYPE_INNER_L3_IPV6,
3444                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3445                 RTE_PTYPE_INNER_L4_TCP,
3446                 RTE_PTYPE_INNER_L4_UDP,
3447                 RTE_PTYPE_UNKNOWN
3448         };
3449
3450         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3451             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3452             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3453             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3454                 return ptypes;
3455         return NULL;
3456 }
3457
3458 static void
3459 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3460                      struct rte_eth_dev_info *dev_info)
3461 {
3462         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3463         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3464
3465         dev_info->pci_dev = pci_dev;
3466         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3467         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3468         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3469         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3470         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3471         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3472         dev_info->max_vfs = pci_dev->max_vfs;
3473         if (hw->mac.type == ixgbe_mac_82598EB)
3474                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3475         else
3476                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3477         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3478                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3479                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3480                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3481         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3482                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3483                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3484                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3485                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3486                                 DEV_TX_OFFLOAD_TCP_TSO;
3487
3488         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3489                 .rx_thresh = {
3490                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3491                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3492                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3493                 },
3494                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3495                 .rx_drop_en = 0,
3496         };
3497
3498         dev_info->default_txconf = (struct rte_eth_txconf) {
3499                 .tx_thresh = {
3500                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3501                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3502                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3503                 },
3504                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3505                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3506                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3507                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3508         };
3509
3510         dev_info->rx_desc_lim = rx_desc_lim;
3511         dev_info->tx_desc_lim = tx_desc_lim;
3512 }
3513
3514 /* return 0 means link status changed, -1 means not changed */
3515 static int
3516 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3517 {
3518         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3519         struct rte_eth_link link, old;
3520         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3521         int link_up;
3522         int diag;
3523
3524         link.link_status = ETH_LINK_DOWN;
3525         link.link_speed = 0;
3526         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3527         memset(&old, 0, sizeof(old));
3528         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3529
3530         hw->mac.get_link_status = true;
3531
3532         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3533         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3534                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3535         else
3536                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3537
3538         if (diag != 0) {
3539                 link.link_speed = ETH_SPEED_NUM_100M;
3540                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3541                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3542                 if (link.link_status == old.link_status)
3543                         return -1;
3544                 return 0;
3545         }
3546
3547         if (link_up == 0) {
3548                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3549                 if (link.link_status == old.link_status)
3550                         return -1;
3551                 return 0;
3552         }
3553         link.link_status = ETH_LINK_UP;
3554         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3555
3556         switch (link_speed) {
3557         default:
3558         case IXGBE_LINK_SPEED_UNKNOWN:
3559                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3560                 link.link_speed = ETH_SPEED_NUM_100M;
3561                 break;
3562
3563         case IXGBE_LINK_SPEED_100_FULL:
3564                 link.link_speed = ETH_SPEED_NUM_100M;
3565                 break;
3566
3567         case IXGBE_LINK_SPEED_1GB_FULL:
3568                 link.link_speed = ETH_SPEED_NUM_1G;
3569                 break;
3570
3571         case IXGBE_LINK_SPEED_10GB_FULL:
3572                 link.link_speed = ETH_SPEED_NUM_10G;
3573                 break;
3574         }
3575         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3576
3577         if (link.link_status == old.link_status)
3578                 return -1;
3579
3580         return 0;
3581 }
3582
3583 static void
3584 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3585 {
3586         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3587         uint32_t fctrl;
3588
3589         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3590         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3591         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3592 }
3593
3594 static void
3595 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3596 {
3597         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3598         uint32_t fctrl;
3599
3600         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3601         fctrl &= (~IXGBE_FCTRL_UPE);
3602         if (dev->data->all_multicast == 1)
3603                 fctrl |= IXGBE_FCTRL_MPE;
3604         else
3605                 fctrl &= (~IXGBE_FCTRL_MPE);
3606         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3607 }
3608
3609 static void
3610 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3611 {
3612         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3613         uint32_t fctrl;
3614
3615         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3616         fctrl |= IXGBE_FCTRL_MPE;
3617         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3618 }
3619
3620 static void
3621 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3622 {
3623         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3624         uint32_t fctrl;
3625
3626         if (dev->data->promiscuous == 1)
3627                 return; /* must remain in all_multicast mode */
3628
3629         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3630         fctrl &= (~IXGBE_FCTRL_MPE);
3631         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3632 }
3633
3634 /**
3635  * It clears the interrupt causes and enables the interrupt.
3636  * It will be called once only during nic initialized.
3637  *
3638  * @param dev
3639  *  Pointer to struct rte_eth_dev.
3640  *
3641  * @return
3642  *  - On success, zero.
3643  *  - On failure, a negative value.
3644  */
3645 static int
3646 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3647 {
3648         struct ixgbe_interrupt *intr =
3649                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3650
3651         ixgbe_dev_link_status_print(dev);
3652         intr->mask |= IXGBE_EICR_LSC;
3653
3654         return 0;
3655 }
3656
3657 /**
3658  * It clears the interrupt causes and enables the interrupt.
3659  * It will be called once only during nic initialized.
3660  *
3661  * @param dev
3662  *  Pointer to struct rte_eth_dev.
3663  *
3664  * @return
3665  *  - On success, zero.
3666  *  - On failure, a negative value.
3667  */
3668 static int
3669 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3670 {
3671         struct ixgbe_interrupt *intr =
3672                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3673
3674         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3675
3676         return 0;
3677 }
3678
3679 /**
3680  * It clears the interrupt causes and enables the interrupt.
3681  * It will be called once only during nic initialized.
3682  *
3683  * @param dev
3684  *  Pointer to struct rte_eth_dev.
3685  *
3686  * @return
3687  *  - On success, zero.
3688  *  - On failure, a negative value.
3689  */
3690 static int
3691 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3692 {
3693         struct ixgbe_interrupt *intr =
3694                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3695
3696         intr->mask |= IXGBE_EICR_LINKSEC;
3697
3698         return 0;
3699 }
3700
3701 /*
3702  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3703  *
3704  * @param dev
3705  *  Pointer to struct rte_eth_dev.
3706  *
3707  * @return
3708  *  - On success, zero.
3709  *  - On failure, a negative value.
3710  */
3711 static int
3712 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3713 {
3714         uint32_t eicr;
3715         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3716         struct ixgbe_interrupt *intr =
3717                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3718
3719         /* clear all cause mask */
3720         ixgbe_disable_intr(hw);
3721
3722         /* read-on-clear nic registers here */
3723         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3724         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3725
3726         intr->flags = 0;
3727
3728         /* set flag for async link update */
3729         if (eicr & IXGBE_EICR_LSC)
3730                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3731
3732         if (eicr & IXGBE_EICR_MAILBOX)
3733                 intr->flags |= IXGBE_FLAG_MAILBOX;
3734
3735         if (eicr & IXGBE_EICR_LINKSEC)
3736                 intr->flags |= IXGBE_FLAG_MACSEC;
3737
3738         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3739             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3740             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3741                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3742
3743         return 0;
3744 }
3745
3746 /**
3747  * It gets and then prints the link status.
3748  *
3749  * @param dev
3750  *  Pointer to struct rte_eth_dev.
3751  *
3752  * @return
3753  *  - On success, zero.
3754  *  - On failure, a negative value.
3755  */
3756 static void
3757 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3758 {
3759         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3760         struct rte_eth_link link;
3761
3762         memset(&link, 0, sizeof(link));
3763         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3764         if (link.link_status) {
3765                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3766                                         (int)(dev->data->port_id),
3767                                         (unsigned)link.link_speed,
3768                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3769                                         "full-duplex" : "half-duplex");
3770         } else {
3771                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3772                                 (int)(dev->data->port_id));
3773         }
3774         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3775                                 pci_dev->addr.domain,
3776                                 pci_dev->addr.bus,
3777                                 pci_dev->addr.devid,
3778                                 pci_dev->addr.function);
3779 }
3780
3781 /*
3782  * It executes link_update after knowing an interrupt occurred.
3783  *
3784  * @param dev
3785  *  Pointer to struct rte_eth_dev.
3786  *
3787  * @return
3788  *  - On success, zero.
3789  *  - On failure, a negative value.
3790  */
3791 static int
3792 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3793                            struct rte_intr_handle *intr_handle)
3794 {
3795         struct ixgbe_interrupt *intr =
3796                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3797         int64_t timeout;
3798         struct rte_eth_link link;
3799         struct ixgbe_hw *hw =
3800                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3801
3802         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3803
3804         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3805                 ixgbe_pf_mbx_process(dev);
3806                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3807         }
3808
3809         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3810                 ixgbe_handle_lasi(hw);
3811                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3812         }
3813
3814         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3815                 /* get the link status before link update, for predicting later */
3816                 memset(&link, 0, sizeof(link));
3817                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3818
3819                 ixgbe_dev_link_update(dev, 0);
3820
3821                 /* likely to up */
3822                 if (!link.link_status)
3823                         /* handle it 1 sec later, wait it being stable */
3824                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3825                 /* likely to down */
3826                 else
3827                         /* handle it 4 sec later, wait it being stable */
3828                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3829
3830                 ixgbe_dev_link_status_print(dev);
3831                 intr->mask_original = intr->mask;
3832                 /* only disable lsc interrupt */
3833                 intr->mask &= ~IXGBE_EIMS_LSC;
3834                 if (rte_eal_alarm_set(timeout * 1000,
3835                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3836                         PMD_DRV_LOG(ERR, "Error setting alarm");
3837                 else
3838                         intr->mask = intr->mask_original;
3839         }
3840
3841         PMD_DRV_LOG(DEBUG, "enable intr immediately");
3842         ixgbe_enable_intr(dev);
3843         rte_intr_enable(intr_handle);
3844
3845         return 0;
3846 }
3847
3848 /**
3849  * Interrupt handler which shall be registered for alarm callback for delayed
3850  * handling specific interrupt to wait for the stable nic state. As the
3851  * NIC interrupt state is not stable for ixgbe after link is just down,
3852  * it needs to wait 4 seconds to get the stable status.
3853  *
3854  * @param handle
3855  *  Pointer to interrupt handle.
3856  * @param param
3857  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3858  *
3859  * @return
3860  *  void
3861  */
3862 static void
3863 ixgbe_dev_interrupt_delayed_handler(void *param)
3864 {
3865         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3866         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3867         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3868         struct ixgbe_interrupt *intr =
3869                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3870         struct ixgbe_hw *hw =
3871                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3872         uint32_t eicr;
3873
3874         ixgbe_disable_intr(hw);
3875
3876         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3877         if (eicr & IXGBE_EICR_MAILBOX)
3878                 ixgbe_pf_mbx_process(dev);
3879
3880         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3881                 ixgbe_handle_lasi(hw);
3882                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3883         }
3884
3885         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3886                 ixgbe_dev_link_update(dev, 0);
3887                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3888                 ixgbe_dev_link_status_print(dev);
3889                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3890         }
3891
3892         if (intr->flags & IXGBE_FLAG_MACSEC) {
3893                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3894                                               NULL);
3895                 intr->flags &= ~IXGBE_FLAG_MACSEC;
3896         }
3897
3898         /* restore original mask */
3899         intr->mask = intr->mask_original;
3900         intr->mask_original = 0;
3901
3902         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3903         ixgbe_enable_intr(dev);
3904         rte_intr_enable(intr_handle);
3905 }
3906
3907 /**
3908  * Interrupt handler triggered by NIC  for handling
3909  * specific interrupt.
3910  *
3911  * @param handle
3912  *  Pointer to interrupt handle.
3913  * @param param
3914  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3915  *
3916  * @return
3917  *  void
3918  */
3919 static void
3920 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3921                             void *param)
3922 {
3923         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3924
3925         ixgbe_dev_interrupt_get_status(dev);
3926         ixgbe_dev_interrupt_action(dev, handle);
3927 }
3928
3929 static int
3930 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3931 {
3932         struct ixgbe_hw *hw;
3933
3934         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3935         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3936 }
3937
3938 static int
3939 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3940 {
3941         struct ixgbe_hw *hw;
3942
3943         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3944         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3945 }
3946
3947 static int
3948 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3949 {
3950         struct ixgbe_hw *hw;
3951         uint32_t mflcn_reg;
3952         uint32_t fccfg_reg;
3953         int rx_pause;
3954         int tx_pause;
3955
3956         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3957
3958         fc_conf->pause_time = hw->fc.pause_time;
3959         fc_conf->high_water = hw->fc.high_water[0];
3960         fc_conf->low_water = hw->fc.low_water[0];
3961         fc_conf->send_xon = hw->fc.send_xon;
3962         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3963
3964         /*
3965          * Return rx_pause status according to actual setting of
3966          * MFLCN register.
3967          */
3968         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3969         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3970                 rx_pause = 1;
3971         else
3972                 rx_pause = 0;
3973
3974         /*
3975          * Return tx_pause status according to actual setting of
3976          * FCCFG register.
3977          */
3978         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3979         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3980                 tx_pause = 1;
3981         else
3982                 tx_pause = 0;
3983
3984         if (rx_pause && tx_pause)
3985                 fc_conf->mode = RTE_FC_FULL;
3986         else if (rx_pause)
3987                 fc_conf->mode = RTE_FC_RX_PAUSE;
3988         else if (tx_pause)
3989                 fc_conf->mode = RTE_FC_TX_PAUSE;
3990         else
3991                 fc_conf->mode = RTE_FC_NONE;
3992
3993         return 0;
3994 }
3995
3996 static int
3997 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3998 {
3999         struct ixgbe_hw *hw;
4000         int err;
4001         uint32_t rx_buf_size;
4002         uint32_t max_high_water;
4003         uint32_t mflcn;
4004         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4005                 ixgbe_fc_none,
4006                 ixgbe_fc_rx_pause,
4007                 ixgbe_fc_tx_pause,
4008                 ixgbe_fc_full
4009         };
4010
4011         PMD_INIT_FUNC_TRACE();
4012
4013         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4014         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4015         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4016
4017         /*
4018          * At least reserve one Ethernet frame for watermark
4019          * high_water/low_water in kilo bytes for ixgbe
4020          */
4021         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4022         if ((fc_conf->high_water > max_high_water) ||
4023                 (fc_conf->high_water < fc_conf->low_water)) {
4024                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4025                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4026                 return -EINVAL;
4027         }
4028
4029         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4030         hw->fc.pause_time     = fc_conf->pause_time;
4031         hw->fc.high_water[0]  = fc_conf->high_water;
4032         hw->fc.low_water[0]   = fc_conf->low_water;
4033         hw->fc.send_xon       = fc_conf->send_xon;
4034         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4035
4036         err = ixgbe_fc_enable(hw);
4037
4038         /* Not negotiated is not an error case */
4039         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4040
4041                 /* check if we want to forward MAC frames - driver doesn't have native
4042                  * capability to do that, so we'll write the registers ourselves */
4043
4044                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4045
4046                 /* set or clear MFLCN.PMCF bit depending on configuration */
4047                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4048                         mflcn |= IXGBE_MFLCN_PMCF;
4049                 else
4050                         mflcn &= ~IXGBE_MFLCN_PMCF;
4051
4052                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4053                 IXGBE_WRITE_FLUSH(hw);
4054
4055                 return 0;
4056         }
4057
4058         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4059         return -EIO;
4060 }
4061
4062 /**
4063  *  ixgbe_pfc_enable_generic - Enable flow control
4064  *  @hw: pointer to hardware structure
4065  *  @tc_num: traffic class number
4066  *  Enable flow control according to the current settings.
4067  */
4068 static int
4069 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4070 {
4071         int ret_val = 0;
4072         uint32_t mflcn_reg, fccfg_reg;
4073         uint32_t reg;
4074         uint32_t fcrtl, fcrth;
4075         uint8_t i;
4076         uint8_t nb_rx_en;
4077
4078         /* Validate the water mark configuration */
4079         if (!hw->fc.pause_time) {
4080                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4081                 goto out;
4082         }
4083
4084         /* Low water mark of zero causes XOFF floods */
4085         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4086                  /* High/Low water can not be 0 */
4087                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4088                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4089                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4090                         goto out;
4091                 }
4092
4093                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4094                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4095                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4096                         goto out;
4097                 }
4098         }
4099         /* Negotiate the fc mode to use */
4100         ixgbe_fc_autoneg(hw);
4101
4102         /* Disable any previous flow control settings */
4103         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4104         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4105
4106         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4107         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4108
4109         switch (hw->fc.current_mode) {
4110         case ixgbe_fc_none:
4111                 /*
4112                  * If the count of enabled RX Priority Flow control >1,
4113                  * and the TX pause can not be disabled
4114                  */
4115                 nb_rx_en = 0;
4116                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4117                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4118                         if (reg & IXGBE_FCRTH_FCEN)
4119                                 nb_rx_en++;
4120                 }
4121                 if (nb_rx_en > 1)
4122                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4123                 break;
4124         case ixgbe_fc_rx_pause:
4125                 /*
4126                  * Rx Flow control is enabled and Tx Flow control is
4127                  * disabled by software override. Since there really
4128                  * isn't a way to advertise that we are capable of RX
4129                  * Pause ONLY, we will advertise that we support both
4130                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4131                  * disable the adapter's ability to send PAUSE frames.
4132                  */
4133                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4134                 /*
4135                  * If the count of enabled RX Priority Flow control >1,
4136                  * and the TX pause can not be disabled
4137                  */
4138                 nb_rx_en = 0;
4139                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4140                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4141                         if (reg & IXGBE_FCRTH_FCEN)
4142                                 nb_rx_en++;
4143                 }
4144                 if (nb_rx_en > 1)
4145                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4146                 break;
4147         case ixgbe_fc_tx_pause:
4148                 /*
4149                  * Tx Flow control is enabled, and Rx Flow control is
4150                  * disabled by software override.
4151                  */
4152                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4153                 break;
4154         case ixgbe_fc_full:
4155                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4156                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4157                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4158                 break;
4159         default:
4160                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4161                 ret_val = IXGBE_ERR_CONFIG;
4162                 goto out;
4163         }
4164
4165         /* Set 802.3x based flow control settings. */
4166         mflcn_reg |= IXGBE_MFLCN_DPF;
4167         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4168         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4169
4170         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4171         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4172                 hw->fc.high_water[tc_num]) {
4173                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4174                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4175                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4176         } else {
4177                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4178                 /*
4179                  * In order to prevent Tx hangs when the internal Tx
4180                  * switch is enabled we must set the high water mark
4181                  * to the maximum FCRTH value.  This allows the Tx
4182                  * switch to function even under heavy Rx workloads.
4183                  */
4184                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4185         }
4186         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4187
4188         /* Configure pause time (2 TCs per register) */
4189         reg = hw->fc.pause_time * 0x00010001;
4190         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4191                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4192
4193         /* Configure flow control refresh threshold value */
4194         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4195
4196 out:
4197         return ret_val;
4198 }
4199
4200 static int
4201 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4202 {
4203         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4204         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4205
4206         if (hw->mac.type != ixgbe_mac_82598EB) {
4207                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4208         }
4209         return ret_val;
4210 }
4211
4212 static int
4213 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4214 {
4215         int err;
4216         uint32_t rx_buf_size;
4217         uint32_t max_high_water;
4218         uint8_t tc_num;
4219         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4220         struct ixgbe_hw *hw =
4221                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4222         struct ixgbe_dcb_config *dcb_config =
4223                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4224
4225         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4226                 ixgbe_fc_none,
4227                 ixgbe_fc_rx_pause,
4228                 ixgbe_fc_tx_pause,
4229                 ixgbe_fc_full
4230         };
4231
4232         PMD_INIT_FUNC_TRACE();
4233
4234         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4235         tc_num = map[pfc_conf->priority];
4236         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4237         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4238         /*
4239          * At least reserve one Ethernet frame for watermark
4240          * high_water/low_water in kilo bytes for ixgbe
4241          */
4242         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4243         if ((pfc_conf->fc.high_water > max_high_water) ||
4244             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4245                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4246                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4247                 return -EINVAL;
4248         }
4249
4250         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4251         hw->fc.pause_time = pfc_conf->fc.pause_time;
4252         hw->fc.send_xon = pfc_conf->fc.send_xon;
4253         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4254         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4255
4256         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4257
4258         /* Not negotiated is not an error case */
4259         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4260                 return 0;
4261
4262         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4263         return -EIO;
4264 }
4265
4266 static int
4267 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4268                           struct rte_eth_rss_reta_entry64 *reta_conf,
4269                           uint16_t reta_size)
4270 {
4271         uint16_t i, sp_reta_size;
4272         uint8_t j, mask;
4273         uint32_t reta, r;
4274         uint16_t idx, shift;
4275         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4276         uint32_t reta_reg;
4277
4278         PMD_INIT_FUNC_TRACE();
4279
4280         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4281                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4282                         "NIC.");
4283                 return -ENOTSUP;
4284         }
4285
4286         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4287         if (reta_size != sp_reta_size) {
4288                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4289                         "(%d) doesn't match the number hardware can supported "
4290                         "(%d)", reta_size, sp_reta_size);
4291                 return -EINVAL;
4292         }
4293
4294         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4295                 idx = i / RTE_RETA_GROUP_SIZE;
4296                 shift = i % RTE_RETA_GROUP_SIZE;
4297                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4298                                                 IXGBE_4_BIT_MASK);
4299                 if (!mask)
4300                         continue;
4301                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4302                 if (mask == IXGBE_4_BIT_MASK)
4303                         r = 0;
4304                 else
4305                         r = IXGBE_READ_REG(hw, reta_reg);
4306                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4307                         if (mask & (0x1 << j))
4308                                 reta |= reta_conf[idx].reta[shift + j] <<
4309                                                         (CHAR_BIT * j);
4310                         else
4311                                 reta |= r & (IXGBE_8_BIT_MASK <<
4312                                                 (CHAR_BIT * j));
4313                 }
4314                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4315         }
4316
4317         return 0;
4318 }
4319
4320 static int
4321 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4322                          struct rte_eth_rss_reta_entry64 *reta_conf,
4323                          uint16_t reta_size)
4324 {
4325         uint16_t i, sp_reta_size;
4326         uint8_t j, mask;
4327         uint32_t reta;
4328         uint16_t idx, shift;
4329         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4330         uint32_t reta_reg;
4331
4332         PMD_INIT_FUNC_TRACE();
4333         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4334         if (reta_size != sp_reta_size) {
4335                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4336                         "(%d) doesn't match the number hardware can supported "
4337                         "(%d)", reta_size, sp_reta_size);
4338                 return -EINVAL;
4339         }
4340
4341         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4342                 idx = i / RTE_RETA_GROUP_SIZE;
4343                 shift = i % RTE_RETA_GROUP_SIZE;
4344                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4345                                                 IXGBE_4_BIT_MASK);
4346                 if (!mask)
4347                         continue;
4348
4349                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4350                 reta = IXGBE_READ_REG(hw, reta_reg);
4351                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4352                         if (mask & (0x1 << j))
4353                                 reta_conf[idx].reta[shift + j] =
4354                                         ((reta >> (CHAR_BIT * j)) &
4355                                                 IXGBE_8_BIT_MASK);
4356                 }
4357         }
4358
4359         return 0;
4360 }
4361
4362 static void
4363 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4364                                 uint32_t index, uint32_t pool)
4365 {
4366         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4367         uint32_t enable_addr = 1;
4368
4369         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4370 }
4371
4372 static void
4373 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4374 {
4375         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4376
4377         ixgbe_clear_rar(hw, index);
4378 }
4379
4380 static void
4381 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4382 {
4383         ixgbe_remove_rar(dev, 0);
4384
4385         ixgbe_add_rar(dev, addr, 0, 0);
4386 }
4387
4388 static bool
4389 is_device_supported(struct rte_eth_dev *dev, struct eth_driver *drv)
4390 {
4391         if (strcmp(dev->driver->pci_drv.driver.name,
4392                    drv->pci_drv.driver.name))
4393                 return false;
4394
4395         return true;
4396 }
4397
4398 int
4399 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4400                 struct ether_addr *mac_addr)
4401 {
4402         struct ixgbe_hw *hw;
4403         struct ixgbe_vf_info *vfinfo;
4404         int rar_entry;
4405         uint8_t *new_mac = (uint8_t *)(mac_addr);
4406         struct rte_eth_dev *dev;
4407         struct rte_pci_device *pci_dev;
4408
4409         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4410
4411         dev = &rte_eth_devices[port];
4412         pci_dev = IXGBE_DEV_TO_PCI(dev);
4413
4414         if (!is_device_supported(dev, &rte_ixgbe_pmd))
4415                 return -ENOTSUP;
4416
4417         if (vf >= pci_dev->max_vfs)
4418                 return -EINVAL;
4419
4420         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4421         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4422         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4423
4424         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4425                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4426                                 ETHER_ADDR_LEN);
4427                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4428                                 IXGBE_RAH_AV);
4429         }
4430         return -EINVAL;
4431 }
4432
4433 static int
4434 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4435 {
4436         uint32_t hlreg0;
4437         uint32_t maxfrs;
4438         struct ixgbe_hw *hw;
4439         struct rte_eth_dev_info dev_info;
4440         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4441
4442         ixgbe_dev_info_get(dev, &dev_info);
4443
4444         /* check that mtu is within the allowed range */
4445         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4446                 return -EINVAL;
4447
4448         /* refuse mtu that requires the support of scattered packets when this
4449          * feature has not been enabled before.
4450          */
4451         if (!dev->data->scattered_rx &&
4452             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4453              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4454                 return -EINVAL;
4455
4456         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4457         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4458
4459         /* switch to jumbo mode if needed */
4460         if (frame_size > ETHER_MAX_LEN) {
4461                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4462                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4463         } else {
4464                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4465                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4466         }
4467         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4468
4469         /* update max frame size */
4470         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4471
4472         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4473         maxfrs &= 0x0000FFFF;
4474         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4475         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4476
4477         return 0;
4478 }
4479
4480 /*
4481  * Virtual Function operations
4482  */
4483 static void
4484 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4485 {
4486         PMD_INIT_FUNC_TRACE();
4487
4488         /* Clear interrupt mask to stop from interrupts being generated */
4489         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4490
4491         IXGBE_WRITE_FLUSH(hw);
4492 }
4493
4494 static void
4495 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4496 {
4497         PMD_INIT_FUNC_TRACE();
4498
4499         /* VF enable interrupt autoclean */
4500         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4501         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4502         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4503
4504         IXGBE_WRITE_FLUSH(hw);
4505 }
4506
4507 static int
4508 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4509 {
4510         struct rte_eth_conf *conf = &dev->data->dev_conf;
4511         struct ixgbe_adapter *adapter =
4512                         (struct ixgbe_adapter *)dev->data->dev_private;
4513
4514         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4515                      dev->data->port_id);
4516
4517         /*
4518          * VF has no ability to enable/disable HW CRC
4519          * Keep the persistent behavior the same as Host PF
4520          */
4521 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4522         if (!conf->rxmode.hw_strip_crc) {
4523                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4524                 conf->rxmode.hw_strip_crc = 1;
4525         }
4526 #else
4527         if (conf->rxmode.hw_strip_crc) {
4528                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4529                 conf->rxmode.hw_strip_crc = 0;
4530         }
4531 #endif
4532
4533         /*
4534          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4535          * allocation or vector Rx preconditions we will reset it.
4536          */
4537         adapter->rx_bulk_alloc_allowed = true;
4538         adapter->rx_vec_allowed = true;
4539
4540         return 0;
4541 }
4542
4543 static int
4544 ixgbevf_dev_start(struct rte_eth_dev *dev)
4545 {
4546         struct ixgbe_hw *hw =
4547                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4548         uint32_t intr_vector = 0;
4549         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4550         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4551
4552         int err, mask = 0;
4553
4554         PMD_INIT_FUNC_TRACE();
4555
4556         hw->mac.ops.reset_hw(hw);
4557         hw->mac.get_link_status = true;
4558
4559         /* negotiate mailbox API version to use with the PF. */
4560         ixgbevf_negotiate_api(hw);
4561
4562         ixgbevf_dev_tx_init(dev);
4563
4564         /* This can fail when allocating mbufs for descriptor rings */
4565         err = ixgbevf_dev_rx_init(dev);
4566         if (err) {
4567                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4568                 ixgbe_dev_clear_queues(dev);
4569                 return err;
4570         }
4571
4572         /* Set vfta */
4573         ixgbevf_set_vfta_all(dev, 1);
4574
4575         /* Set HW strip */
4576         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4577                 ETH_VLAN_EXTEND_MASK;
4578         ixgbevf_vlan_offload_set(dev, mask);
4579
4580         ixgbevf_dev_rxtx_start(dev);
4581
4582         /* check and configure queue intr-vector mapping */
4583         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4584                 intr_vector = dev->data->nb_rx_queues;
4585                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4586                         return -1;
4587         }
4588
4589         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4590                 intr_handle->intr_vec =
4591                         rte_zmalloc("intr_vec",
4592                                     dev->data->nb_rx_queues * sizeof(int), 0);
4593                 if (intr_handle->intr_vec == NULL) {
4594                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4595                                      " intr_vec", dev->data->nb_rx_queues);
4596                         return -ENOMEM;
4597                 }
4598         }
4599         ixgbevf_configure_msix(dev);
4600
4601         rte_intr_enable(intr_handle);
4602
4603         /* Re-enable interrupt for VF */
4604         ixgbevf_intr_enable(hw);
4605
4606         return 0;
4607 }
4608
4609 static void
4610 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4611 {
4612         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4613         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4614         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4615
4616         PMD_INIT_FUNC_TRACE();
4617
4618         ixgbevf_intr_disable(hw);
4619
4620         hw->adapter_stopped = 1;
4621         ixgbe_stop_adapter(hw);
4622
4623         /*
4624           * Clear what we set, but we still keep shadow_vfta to
4625           * restore after device starts
4626           */
4627         ixgbevf_set_vfta_all(dev, 0);
4628
4629         /* Clear stored conf */
4630         dev->data->scattered_rx = 0;
4631
4632         ixgbe_dev_clear_queues(dev);
4633
4634         /* Clean datapath event and queue/vec mapping */
4635         rte_intr_efd_disable(intr_handle);
4636         if (intr_handle->intr_vec != NULL) {
4637                 rte_free(intr_handle->intr_vec);
4638                 intr_handle->intr_vec = NULL;
4639         }
4640 }
4641
4642 static void
4643 ixgbevf_dev_close(struct rte_eth_dev *dev)
4644 {
4645         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4646
4647         PMD_INIT_FUNC_TRACE();
4648
4649         ixgbe_reset_hw(hw);
4650
4651         ixgbevf_dev_stop(dev);
4652
4653         ixgbe_dev_free_queues(dev);
4654
4655         /**
4656          * Remove the VF MAC address ro ensure
4657          * that the VF traffic goes to the PF
4658          * after stop, close and detach of the VF
4659          **/
4660         ixgbevf_remove_mac_addr(dev, 0);
4661 }
4662
4663 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4664 {
4665         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4666         struct ixgbe_vfta *shadow_vfta =
4667                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4668         int i = 0, j = 0, vfta = 0, mask = 1;
4669
4670         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4671                 vfta = shadow_vfta->vfta[i];
4672                 if (vfta) {
4673                         mask = 1;
4674                         for (j = 0; j < 32; j++) {
4675                                 if (vfta & mask)
4676                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4677                                                        on, false);
4678                                 mask <<= 1;
4679                         }
4680                 }
4681         }
4682
4683 }
4684
4685 static int
4686 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4687 {
4688         struct ixgbe_hw *hw =
4689                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4690         struct ixgbe_vfta *shadow_vfta =
4691                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4692         uint32_t vid_idx = 0;
4693         uint32_t vid_bit = 0;
4694         int ret = 0;
4695
4696         PMD_INIT_FUNC_TRACE();
4697
4698         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4699         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4700         if (ret) {
4701                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4702                 return ret;
4703         }
4704         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4705         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4706
4707         /* Save what we set and retore it after device reset */
4708         if (on)
4709                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4710         else
4711                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4712
4713         return 0;
4714 }
4715
4716 static void
4717 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4718 {
4719         struct ixgbe_hw *hw =
4720                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4721         uint32_t ctrl;
4722
4723         PMD_INIT_FUNC_TRACE();
4724
4725         if (queue >= hw->mac.max_rx_queues)
4726                 return;
4727
4728         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4729         if (on)
4730                 ctrl |= IXGBE_RXDCTL_VME;
4731         else
4732                 ctrl &= ~IXGBE_RXDCTL_VME;
4733         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4734
4735         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4736 }
4737
4738 static void
4739 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4740 {
4741         struct ixgbe_hw *hw =
4742                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4743         uint16_t i;
4744         int on = 0;
4745
4746         /* VF function only support hw strip feature, others are not support */
4747         if (mask & ETH_VLAN_STRIP_MASK) {
4748                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4749
4750                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4751                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4752         }
4753 }
4754
4755 static int
4756 ixgbe_vt_check(struct ixgbe_hw *hw)
4757 {
4758         uint32_t reg_val;
4759
4760         /* if Virtualization Technology is enabled */
4761         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4762         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4763                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
4764                 return -1;
4765         }
4766
4767         return 0;
4768 }
4769
4770 static uint32_t
4771 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4772 {
4773         uint32_t vector = 0;
4774
4775         switch (hw->mac.mc_filter_type) {
4776         case 0:   /* use bits [47:36] of the address */
4777                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4778                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4779                 break;
4780         case 1:   /* use bits [46:35] of the address */
4781                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4782                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4783                 break;
4784         case 2:   /* use bits [45:34] of the address */
4785                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4786                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4787                 break;
4788         case 3:   /* use bits [43:32] of the address */
4789                 vector = ((uc_addr->addr_bytes[4]) |
4790                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4791                 break;
4792         default:  /* Invalid mc_filter_type */
4793                 break;
4794         }
4795
4796         /* vector can only be 12-bits or boundary will be exceeded */
4797         vector &= 0xFFF;
4798         return vector;
4799 }
4800
4801 static int
4802 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4803                         uint8_t on)
4804 {
4805         uint32_t vector;
4806         uint32_t uta_idx;
4807         uint32_t reg_val;
4808         uint32_t uta_shift;
4809         uint32_t rc;
4810         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4811         const uint32_t ixgbe_uta_bit_shift = 5;
4812         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4813         const uint32_t bit1 = 0x1;
4814
4815         struct ixgbe_hw *hw =
4816                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4817         struct ixgbe_uta_info *uta_info =
4818                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4819
4820         /* The UTA table only exists on 82599 hardware and newer */
4821         if (hw->mac.type < ixgbe_mac_82599EB)
4822                 return -ENOTSUP;
4823
4824         vector = ixgbe_uta_vector(hw, mac_addr);
4825         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4826         uta_shift = vector & ixgbe_uta_bit_mask;
4827
4828         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4829         if (rc == on)
4830                 return 0;
4831
4832         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4833         if (on) {
4834                 uta_info->uta_in_use++;
4835                 reg_val |= (bit1 << uta_shift);
4836                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4837         } else {
4838                 uta_info->uta_in_use--;
4839                 reg_val &= ~(bit1 << uta_shift);
4840                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4841         }
4842
4843         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4844
4845         if (uta_info->uta_in_use > 0)
4846                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4847                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4848         else
4849                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4850
4851         return 0;
4852 }
4853
4854 static int
4855 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4856 {
4857         int i;
4858         struct ixgbe_hw *hw =
4859                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4860         struct ixgbe_uta_info *uta_info =
4861                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4862
4863         /* The UTA table only exists on 82599 hardware and newer */
4864         if (hw->mac.type < ixgbe_mac_82599EB)
4865                 return -ENOTSUP;
4866
4867         if (on) {
4868                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4869                         uta_info->uta_shadow[i] = ~0;
4870                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4871                 }
4872         } else {
4873                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4874                         uta_info->uta_shadow[i] = 0;
4875                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4876                 }
4877         }
4878         return 0;
4879
4880 }
4881
4882 uint32_t
4883 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4884 {
4885         uint32_t new_val = orig_val;
4886
4887         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4888                 new_val |= IXGBE_VMOLR_AUPE;
4889         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4890                 new_val |= IXGBE_VMOLR_ROMPE;
4891         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4892                 new_val |= IXGBE_VMOLR_ROPE;
4893         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4894                 new_val |= IXGBE_VMOLR_BAM;
4895         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4896                 new_val |= IXGBE_VMOLR_MPE;
4897
4898         return new_val;
4899 }
4900
4901 int
4902 rte_pmd_ixgbe_ping_vf(uint8_t port, uint16_t vf)
4903 {
4904         struct ixgbe_hw *hw;
4905         struct ixgbe_vf_info *vfinfo;
4906         struct rte_eth_dev *dev;
4907         struct rte_pci_device *pci_dev;
4908         uint32_t ctrl;
4909
4910         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4911
4912         dev = &rte_eth_devices[port];
4913         pci_dev = IXGBE_DEV_TO_PCI(dev);
4914
4915         if (!is_device_supported(dev, &rte_ixgbe_pmd))
4916                 return -ENOTSUP;
4917
4918         if (vf >= pci_dev->max_vfs)
4919                 return -EINVAL;
4920
4921         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4922         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4923
4924         ctrl = IXGBE_PF_CONTROL_MSG;
4925         if (vfinfo[vf].clear_to_send)
4926                 ctrl |= IXGBE_VT_MSGTYPE_CTS;
4927
4928         ixgbe_write_mbx(hw, &ctrl, 1, vf);
4929
4930         return 0;
4931 }
4932
4933 int
4934 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4935 {
4936         struct ixgbe_hw *hw;
4937         struct ixgbe_mac_info *mac;
4938         struct rte_eth_dev *dev;
4939         struct rte_pci_device *pci_dev;
4940
4941         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4942
4943         dev = &rte_eth_devices[port];
4944         pci_dev = IXGBE_DEV_TO_PCI(dev);
4945
4946         if (!is_device_supported(dev, &rte_ixgbe_pmd))
4947                 return -ENOTSUP;
4948
4949         if (vf >= pci_dev->max_vfs)
4950                 return -EINVAL;
4951
4952         if (on > 1)
4953                 return -EINVAL;
4954
4955         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4956         mac = &hw->mac;
4957
4958         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4959
4960         return 0;
4961 }
4962
4963 int
4964 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4965 {
4966         struct ixgbe_hw *hw;
4967         struct ixgbe_mac_info *mac;
4968         struct rte_eth_dev *dev;
4969         struct rte_pci_device *pci_dev;
4970
4971         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4972
4973         dev = &rte_eth_devices[port];
4974         pci_dev = IXGBE_DEV_TO_PCI(dev);
4975
4976         if (!is_device_supported(dev, &rte_ixgbe_pmd))
4977                 return -ENOTSUP;
4978
4979         if (vf >= pci_dev->max_vfs)
4980                 return -EINVAL;
4981
4982         if (on > 1)
4983                 return -EINVAL;
4984
4985         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4986         mac = &hw->mac;
4987         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4988
4989         return 0;
4990 }
4991
4992 int
4993 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4994 {
4995         struct ixgbe_hw *hw;
4996         uint32_t ctrl;
4997         struct rte_eth_dev *dev;
4998         struct rte_pci_device *pci_dev;
4999
5000         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5001
5002         dev = &rte_eth_devices[port];
5003         pci_dev = IXGBE_DEV_TO_PCI(dev);
5004
5005         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5006                 return -ENOTSUP;
5007
5008         if (vf >= pci_dev->max_vfs)
5009                 return -EINVAL;
5010
5011         if (vlan_id > ETHER_MAX_VLAN_ID)
5012                 return -EINVAL;
5013
5014         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5015         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
5016         if (vlan_id) {
5017                 ctrl = vlan_id;
5018                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
5019         } else {
5020                 ctrl = 0;
5021         }
5022
5023         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
5024
5025         return 0;
5026 }
5027
5028 int
5029 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
5030 {
5031         struct ixgbe_hw *hw;
5032         uint32_t ctrl;
5033         struct rte_eth_dev *dev;
5034
5035         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5036
5037         dev = &rte_eth_devices[port];
5038
5039         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5040                 return -ENOTSUP;
5041
5042         if (on > 1)
5043                 return -EINVAL;
5044
5045         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5046         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5047         /* enable or disable VMDQ loopback */
5048         if (on)
5049                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
5050         else
5051                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5052
5053         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
5054
5055         return 0;
5056 }
5057
5058 int
5059 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
5060 {
5061         struct ixgbe_hw *hw;
5062         uint32_t reg_value;
5063         int i;
5064         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
5065         struct rte_eth_dev *dev;
5066
5067         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5068
5069         dev = &rte_eth_devices[port];
5070
5071         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5072                 return -ENOTSUP;
5073
5074         if (on > 1)
5075                 return -EINVAL;
5076
5077         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5078         for (i = 0; i <= num_queues; i++) {
5079                 reg_value = IXGBE_QDE_WRITE |
5080                                 (i << IXGBE_QDE_IDX_SHIFT) |
5081                                 (on & IXGBE_QDE_ENABLE);
5082                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
5083         }
5084
5085         return 0;
5086 }
5087
5088 int
5089 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
5090 {
5091         struct ixgbe_hw *hw;
5092         uint32_t reg_value;
5093         struct rte_eth_dev *dev;
5094         struct rte_pci_device *pci_dev;
5095
5096         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5097
5098         dev = &rte_eth_devices[port];
5099         pci_dev = IXGBE_DEV_TO_PCI(dev);
5100
5101         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5102                 return -ENOTSUP;
5103
5104         /* only support VF's 0 to 63 */
5105         if ((vf >= pci_dev->max_vfs) || (vf > 63))
5106                 return -EINVAL;
5107
5108         if (on > 1)
5109                 return -EINVAL;
5110
5111         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5112         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
5113         if (on)
5114                 reg_value |= IXGBE_SRRCTL_DROP_EN;
5115         else
5116                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
5117
5118         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
5119
5120         return 0;
5121 }
5122
5123 int
5124 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
5125 {
5126         struct rte_eth_dev *dev;
5127         struct rte_pci_device *pci_dev;
5128         struct ixgbe_hw *hw;
5129         uint16_t queues_per_pool;
5130         uint32_t q;
5131
5132         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5133
5134         dev = &rte_eth_devices[port];
5135         pci_dev = IXGBE_DEV_TO_PCI(dev);
5136         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5137
5138         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5139                 return -ENOTSUP;
5140
5141         if (vf >= pci_dev->max_vfs)
5142                 return -EINVAL;
5143
5144         if (on > 1)
5145                 return -EINVAL;
5146
5147         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5148
5149         /* The PF has 128 queue pairs and in SRIOV configuration
5150          * those queues will be assigned to VF's, so RXDCTL
5151          * registers will be dealing with queues which will be
5152          * assigned to VF's.
5153          * Let's say we have SRIOV configured with 31 VF's then the
5154          * first 124 queues 0-123 will be allocated to VF's and only
5155          * the last 4 queues 123-127 will be assigned to the PF.
5156          */
5157         if (hw->mac.type == ixgbe_mac_82598EB)
5158                 queues_per_pool = (uint16_t)hw->mac.max_rx_queues /
5159                                   ETH_16_POOLS;
5160         else
5161                 queues_per_pool = (uint16_t)hw->mac.max_rx_queues /
5162                                   ETH_64_POOLS;
5163
5164         for (q = 0; q < queues_per_pool; q++)
5165                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5166                                 q + vf * queues_per_pool, on);
5167         return 0;
5168 }
5169
5170 int
5171 rte_pmd_ixgbe_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mask, uint8_t on)
5172 {
5173         int val = 0;
5174         struct rte_eth_dev *dev;
5175         struct rte_pci_device *pci_dev;
5176         struct ixgbe_hw *hw;
5177         uint32_t vmolr;
5178
5179         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5180
5181         dev = &rte_eth_devices[port];
5182         pci_dev = IXGBE_DEV_TO_PCI(dev);
5183
5184         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5185                 return -ENOTSUP;
5186
5187         if (vf >= pci_dev->max_vfs)
5188                 return -EINVAL;
5189
5190         if (on > 1)
5191                 return -EINVAL;
5192
5193         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5194         vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
5195
5196         if (hw->mac.type == ixgbe_mac_82598EB) {
5197                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
5198                              " on 82599 hardware and newer");
5199                 return -ENOTSUP;
5200         }
5201         if (ixgbe_vt_check(hw) < 0)
5202                 return -ENOTSUP;
5203
5204         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
5205
5206         if (on)
5207                 vmolr |= val;
5208         else
5209                 vmolr &= ~val;
5210
5211         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
5212
5213         return 0;
5214 }
5215
5216 int
5217 rte_pmd_ixgbe_set_vf_rx(uint8_t port, uint16_t vf, uint8_t on)
5218 {
5219         struct rte_eth_dev *dev;
5220         struct rte_pci_device *pci_dev;
5221         uint32_t reg, addr;
5222         uint32_t val;
5223         const uint8_t bit1 = 0x1;
5224         struct ixgbe_hw *hw;
5225
5226         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5227
5228         dev = &rte_eth_devices[port];
5229         pci_dev = IXGBE_DEV_TO_PCI(dev);
5230
5231         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5232                 return -ENOTSUP;
5233
5234         if (vf >= pci_dev->max_vfs)
5235                 return -EINVAL;
5236
5237         if (on > 1)
5238                 return -EINVAL;
5239
5240         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5241
5242         if (ixgbe_vt_check(hw) < 0)
5243                 return -ENOTSUP;
5244
5245         /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
5246         if (vf >= 32) {
5247                 addr = IXGBE_VFRE(1);
5248                 val = bit1 << (vf - 32);
5249         } else {
5250                 addr = IXGBE_VFRE(0);
5251                 val = bit1 << vf;
5252         }
5253
5254         reg = IXGBE_READ_REG(hw, addr);
5255
5256         if (on)
5257                 reg |= val;
5258         else
5259                 reg &= ~val;
5260
5261         IXGBE_WRITE_REG(hw, addr, reg);
5262
5263         return 0;
5264 }
5265
5266 int
5267 rte_pmd_ixgbe_set_vf_tx(uint8_t port, uint16_t vf, uint8_t on)
5268 {
5269         struct rte_eth_dev *dev;
5270         struct rte_pci_device *pci_dev;
5271         uint32_t reg, addr;
5272         uint32_t val;
5273         const uint8_t bit1 = 0x1;
5274
5275         struct ixgbe_hw *hw;
5276
5277         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5278
5279         dev = &rte_eth_devices[port];
5280         pci_dev = IXGBE_DEV_TO_PCI(dev);
5281
5282         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5283                 return -ENOTSUP;
5284
5285         if (vf >= pci_dev->max_vfs)
5286                 return -EINVAL;
5287
5288         if (on > 1)
5289                 return -EINVAL;
5290
5291         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5292         if (ixgbe_vt_check(hw) < 0)
5293                 return -ENOTSUP;
5294
5295         /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
5296         if (vf >= 32) {
5297                 addr = IXGBE_VFTE(1);
5298                 val = bit1 << (vf - 32);
5299         } else {
5300                 addr = IXGBE_VFTE(0);
5301                 val = bit1 << vf;
5302         }
5303
5304         reg = IXGBE_READ_REG(hw, addr);
5305
5306         if (on)
5307                 reg |= val;
5308         else
5309                 reg &= ~val;
5310
5311         IXGBE_WRITE_REG(hw, addr, reg);
5312
5313         return 0;
5314 }
5315
5316 int
5317 rte_pmd_ixgbe_set_vf_vlan_filter(uint8_t port, uint16_t vlan,
5318                         uint64_t vf_mask, uint8_t vlan_on)
5319 {
5320         struct rte_eth_dev *dev;
5321         int ret = 0;
5322         uint16_t vf_idx;
5323         struct ixgbe_hw *hw;
5324
5325         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5326
5327         dev = &rte_eth_devices[port];
5328
5329         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5330                 return -ENOTSUP;
5331
5332         if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
5333                 return -EINVAL;
5334
5335         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5336         if (ixgbe_vt_check(hw) < 0)
5337                 return -ENOTSUP;
5338
5339         for (vf_idx = 0; vf_idx < 64; vf_idx++) {
5340                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
5341                         ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
5342                                                    vlan_on, false);
5343                         if (ret < 0)
5344                                 return ret;
5345                 }
5346         }
5347
5348         return ret;
5349 }
5350
5351 int rte_pmd_ixgbe_set_vf_rate_limit(uint8_t port, uint16_t vf,
5352         uint16_t tx_rate, uint64_t q_msk)
5353 {
5354         struct rte_eth_dev *dev;
5355         struct ixgbe_hw *hw;
5356         struct ixgbe_vf_info *vfinfo;
5357         struct rte_eth_link link;
5358         uint8_t  nb_q_per_pool;
5359         uint32_t queue_stride;
5360         uint32_t queue_idx, idx = 0, vf_idx;
5361         uint32_t queue_end;
5362         uint16_t total_rate = 0;
5363         struct rte_pci_device *pci_dev;
5364
5365         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5366
5367         dev = &rte_eth_devices[port];
5368         pci_dev = IXGBE_DEV_TO_PCI(dev);
5369         rte_eth_link_get_nowait(port, &link);
5370
5371         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5372                 return -ENOTSUP;
5373
5374         if (vf >= pci_dev->max_vfs)
5375                 return -EINVAL;
5376
5377         if (tx_rate > link.link_speed)
5378                 return -EINVAL;
5379
5380         if (q_msk == 0)
5381                 return 0;
5382
5383         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5384         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5385         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5386         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5387         queue_idx = vf * queue_stride;
5388         queue_end = queue_idx + nb_q_per_pool - 1;
5389         if (queue_end >= hw->mac.max_tx_queues)
5390                 return -EINVAL;
5391
5392         if (vfinfo) {
5393                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5394                         if (vf_idx == vf)
5395                                 continue;
5396                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5397                                 idx++)
5398                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5399                 }
5400         } else {
5401                 return -EINVAL;
5402         }
5403
5404         /* Store tx_rate for this vf. */
5405         for (idx = 0; idx < nb_q_per_pool; idx++) {
5406                 if (((uint64_t)0x1 << idx) & q_msk) {
5407                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5408                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5409                         total_rate += tx_rate;
5410                 }
5411         }
5412
5413         if (total_rate > dev->data->dev_link.link_speed) {
5414                 /* Reset stored TX rate of the VF if it causes exceed
5415                  * link speed.
5416                  */
5417                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5418                 return -EINVAL;
5419         }
5420
5421         /* Set RTTBCNRC of each queue/pool for vf X  */
5422         for (; queue_idx <= queue_end; queue_idx++) {
5423                 if (0x1 & q_msk)
5424                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5425                 q_msk = q_msk >> 1;
5426         }
5427
5428         return 0;
5429 }
5430
5431 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5432 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5433 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5434 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5435 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5436         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5437         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5438
5439 static int
5440 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5441                         struct rte_eth_mirror_conf *mirror_conf,
5442                         uint8_t rule_id, uint8_t on)
5443 {
5444         uint32_t mr_ctl, vlvf;
5445         uint32_t mp_lsb = 0;
5446         uint32_t mv_msb = 0;
5447         uint32_t mv_lsb = 0;
5448         uint32_t mp_msb = 0;
5449         uint8_t i = 0;
5450         int reg_index = 0;
5451         uint64_t vlan_mask = 0;
5452
5453         const uint8_t pool_mask_offset = 32;
5454         const uint8_t vlan_mask_offset = 32;
5455         const uint8_t dst_pool_offset = 8;
5456         const uint8_t rule_mr_offset  = 4;
5457         const uint8_t mirror_rule_mask = 0x0F;
5458
5459         struct ixgbe_mirror_info *mr_info =
5460                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5461         struct ixgbe_hw *hw =
5462                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5463         uint8_t mirror_type = 0;
5464
5465         if (ixgbe_vt_check(hw) < 0)
5466                 return -ENOTSUP;
5467
5468         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5469                 return -EINVAL;
5470
5471         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5472                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5473                         mirror_conf->rule_type);
5474                 return -EINVAL;
5475         }
5476
5477         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5478                 mirror_type |= IXGBE_MRCTL_VLME;
5479                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5480                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5481                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5482                                 /* search vlan id related pool vlan filter index */
5483                                 reg_index = ixgbe_find_vlvf_slot(hw,
5484                                                  mirror_conf->vlan.vlan_id[i],
5485                                                  false);
5486                                 if (reg_index < 0)
5487                                         return -EINVAL;
5488                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5489                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5490                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5491                                       mirror_conf->vlan.vlan_id[i]))
5492                                         vlan_mask |= (1ULL << reg_index);
5493                                 else
5494                                         return -EINVAL;
5495                         }
5496                 }
5497
5498                 if (on) {
5499                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5500                         mv_msb = vlan_mask >> vlan_mask_offset;
5501
5502                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5503                                                 mirror_conf->vlan.vlan_mask;
5504                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5505                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5506                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5507                                                 mirror_conf->vlan.vlan_id[i];
5508                         }
5509                 } else {
5510                         mv_lsb = 0;
5511                         mv_msb = 0;
5512                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5513                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5514                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5515                 }
5516         }
5517
5518         /*
5519          * if enable pool mirror, write related pool mask register,if disable
5520          * pool mirror, clear PFMRVM register
5521          */
5522         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5523                 mirror_type |= IXGBE_MRCTL_VPME;
5524                 if (on) {
5525                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5526                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5527                         mr_info->mr_conf[rule_id].pool_mask =
5528                                         mirror_conf->pool_mask;
5529
5530                 } else {
5531                         mp_lsb = 0;
5532                         mp_msb = 0;
5533                         mr_info->mr_conf[rule_id].pool_mask = 0;
5534                 }
5535         }
5536         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5537                 mirror_type |= IXGBE_MRCTL_UPME;
5538         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5539                 mirror_type |= IXGBE_MRCTL_DPME;
5540
5541         /* read  mirror control register and recalculate it */
5542         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5543
5544         if (on) {
5545                 mr_ctl |= mirror_type;
5546                 mr_ctl &= mirror_rule_mask;
5547                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5548         } else
5549                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5550
5551         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5552         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5553
5554         /* write mirrror control  register */
5555         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5556
5557         /* write pool mirrror control  register */
5558         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5559                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5560                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5561                                 mp_msb);
5562         }
5563         /* write VLAN mirrror control  register */
5564         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5565                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5566                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5567                                 mv_msb);
5568         }
5569
5570         return 0;
5571 }
5572
5573 static int
5574 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5575 {
5576         int mr_ctl = 0;
5577         uint32_t lsb_val = 0;
5578         uint32_t msb_val = 0;
5579         const uint8_t rule_mr_offset = 4;
5580
5581         struct ixgbe_hw *hw =
5582                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5583         struct ixgbe_mirror_info *mr_info =
5584                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5585
5586         if (ixgbe_vt_check(hw) < 0)
5587                 return -ENOTSUP;
5588
5589         memset(&mr_info->mr_conf[rule_id], 0,
5590                 sizeof(struct rte_eth_mirror_conf));
5591
5592         /* clear PFVMCTL register */
5593         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5594
5595         /* clear pool mask register */
5596         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5597         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5598
5599         /* clear vlan mask register */
5600         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5601         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5602
5603         return 0;
5604 }
5605
5606 static int
5607 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5608 {
5609         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5610         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5611         uint32_t mask;
5612         struct ixgbe_hw *hw =
5613                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5614
5615         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5616         mask |= (1 << IXGBE_MISC_VEC_ID);
5617         RTE_SET_USED(queue_id);
5618         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5619
5620         rte_intr_enable(intr_handle);
5621
5622         return 0;
5623 }
5624
5625 static int
5626 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5627 {
5628         uint32_t mask;
5629         struct ixgbe_hw *hw =
5630                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5631
5632         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5633         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5634         RTE_SET_USED(queue_id);
5635         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5636
5637         return 0;
5638 }
5639
5640 static int
5641 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5642 {
5643         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5644         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5645         uint32_t mask;
5646         struct ixgbe_hw *hw =
5647                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5648         struct ixgbe_interrupt *intr =
5649                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5650
5651         if (queue_id < 16) {
5652                 ixgbe_disable_intr(hw);
5653                 intr->mask |= (1 << queue_id);
5654                 ixgbe_enable_intr(dev);
5655         } else if (queue_id < 32) {
5656                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5657                 mask &= (1 << queue_id);
5658                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5659         } else if (queue_id < 64) {
5660                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5661                 mask &= (1 << (queue_id - 32));
5662                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5663         }
5664         rte_intr_enable(intr_handle);
5665
5666         return 0;
5667 }
5668
5669 static int
5670 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5671 {
5672         uint32_t mask;
5673         struct ixgbe_hw *hw =
5674                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5675         struct ixgbe_interrupt *intr =
5676                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5677
5678         if (queue_id < 16) {
5679                 ixgbe_disable_intr(hw);
5680                 intr->mask &= ~(1 << queue_id);
5681                 ixgbe_enable_intr(dev);
5682         } else if (queue_id < 32) {
5683                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5684                 mask &= ~(1 << queue_id);
5685                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5686         } else if (queue_id < 64) {
5687                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5688                 mask &= ~(1 << (queue_id - 32));
5689                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5690         }
5691
5692         return 0;
5693 }
5694
5695 static void
5696 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5697                      uint8_t queue, uint8_t msix_vector)
5698 {
5699         uint32_t tmp, idx;
5700
5701         if (direction == -1) {
5702                 /* other causes */
5703                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5704                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5705                 tmp &= ~0xFF;
5706                 tmp |= msix_vector;
5707                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5708         } else {
5709                 /* rx or tx cause */
5710                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5711                 idx = ((16 * (queue & 1)) + (8 * direction));
5712                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5713                 tmp &= ~(0xFF << idx);
5714                 tmp |= (msix_vector << idx);
5715                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5716         }
5717 }
5718
5719 /**
5720  * set the IVAR registers, mapping interrupt causes to vectors
5721  * @param hw
5722  *  pointer to ixgbe_hw struct
5723  * @direction
5724  *  0 for Rx, 1 for Tx, -1 for other causes
5725  * @queue
5726  *  queue to map the corresponding interrupt to
5727  * @msix_vector
5728  *  the vector to map to the corresponding queue
5729  */
5730 static void
5731 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5732                    uint8_t queue, uint8_t msix_vector)
5733 {
5734         uint32_t tmp, idx;
5735
5736         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5737         if (hw->mac.type == ixgbe_mac_82598EB) {
5738                 if (direction == -1)
5739                         direction = 0;
5740                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5741                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5742                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5743                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5744                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5745         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5746                         (hw->mac.type == ixgbe_mac_X540)) {
5747                 if (direction == -1) {
5748                         /* other causes */
5749                         idx = ((queue & 1) * 8);
5750                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5751                         tmp &= ~(0xFF << idx);
5752                         tmp |= (msix_vector << idx);
5753                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5754                 } else {
5755                         /* rx or tx causes */
5756                         idx = ((16 * (queue & 1)) + (8 * direction));
5757                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5758                         tmp &= ~(0xFF << idx);
5759                         tmp |= (msix_vector << idx);
5760                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5761                 }
5762         }
5763 }
5764
5765 static void
5766 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5767 {
5768         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5769         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5770         struct ixgbe_hw *hw =
5771                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5772         uint32_t q_idx;
5773         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5774
5775         /* Configure VF other cause ivar */
5776         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5777
5778         /* won't configure msix register if no mapping is done
5779          * between intr vector and event fd.
5780          */
5781         if (!rte_intr_dp_is_en(intr_handle))
5782                 return;
5783
5784         /* Configure all RX queues of VF */
5785         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5786                 /* Force all queue use vector 0,
5787                  * as IXGBE_VF_MAXMSIVECOTR = 1
5788                  */
5789                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5790                 intr_handle->intr_vec[q_idx] = vector_idx;
5791         }
5792 }
5793
5794 /**
5795  * Sets up the hardware to properly generate MSI-X interrupts
5796  * @hw
5797  *  board private structure
5798  */
5799 static void
5800 ixgbe_configure_msix(struct rte_eth_dev *dev)
5801 {
5802         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5803         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5804         struct ixgbe_hw *hw =
5805                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5806         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5807         uint32_t vec = IXGBE_MISC_VEC_ID;
5808         uint32_t mask;
5809         uint32_t gpie;
5810
5811         /* won't configure msix register if no mapping is done
5812          * between intr vector and event fd
5813          */
5814         if (!rte_intr_dp_is_en(intr_handle))
5815                 return;
5816
5817         if (rte_intr_allow_others(intr_handle))
5818                 vec = base = IXGBE_RX_VEC_START;
5819
5820         /* setup GPIE for MSI-x mode */
5821         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5822         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5823                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5824         /* auto clearing and auto setting corresponding bits in EIMS
5825          * when MSI-X interrupt is triggered
5826          */
5827         if (hw->mac.type == ixgbe_mac_82598EB) {
5828                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5829         } else {
5830                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5831                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5832         }
5833         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5834
5835         /* Populate the IVAR table and set the ITR values to the
5836          * corresponding register.
5837          */
5838         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5839              queue_id++) {
5840                 /* by default, 1:1 mapping */
5841                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5842                 intr_handle->intr_vec[queue_id] = vec;
5843                 if (vec < base + intr_handle->nb_efd - 1)
5844                         vec++;
5845         }
5846
5847         switch (hw->mac.type) {
5848         case ixgbe_mac_82598EB:
5849                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5850                                    IXGBE_MISC_VEC_ID);
5851                 break;
5852         case ixgbe_mac_82599EB:
5853         case ixgbe_mac_X540:
5854                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5855                 break;
5856         default:
5857                 break;
5858         }
5859         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5860                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5861
5862         /* set up to autoclear timer, and the vectors */
5863         mask = IXGBE_EIMS_ENABLE_MASK;
5864         mask &= ~(IXGBE_EIMS_OTHER |
5865                   IXGBE_EIMS_MAILBOX |
5866                   IXGBE_EIMS_LSC);
5867
5868         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5869 }
5870
5871 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5872         uint16_t queue_idx, uint16_t tx_rate)
5873 {
5874         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5875         uint32_t rf_dec, rf_int;
5876         uint32_t bcnrc_val;
5877         uint16_t link_speed = dev->data->dev_link.link_speed;
5878
5879         if (queue_idx >= hw->mac.max_tx_queues)
5880                 return -EINVAL;
5881
5882         if (tx_rate != 0) {
5883                 /* Calculate the rate factor values to set */
5884                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5885                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5886                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5887
5888                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5889                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5890                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5891                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5892         } else {
5893                 bcnrc_val = 0;
5894         }
5895
5896         /*
5897          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5898          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5899          * set as 0x4.
5900          */
5901         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5902                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5903                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5904                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5905                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5906         else
5907                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5908                         IXGBE_MMW_SIZE_DEFAULT);
5909
5910         /* Set RTTBCNRC of queue X */
5911         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5912         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5913         IXGBE_WRITE_FLUSH(hw);
5914
5915         return 0;
5916 }
5917
5918 static void
5919 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5920                      __attribute__((unused)) uint32_t index,
5921                      __attribute__((unused)) uint32_t pool)
5922 {
5923         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5924         int diag;
5925
5926         /*
5927          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5928          * operation. Trap this case to avoid exhausting the [very limited]
5929          * set of PF resources used to store VF MAC addresses.
5930          */
5931         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5932                 return;
5933         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5934         if (diag == 0)
5935                 return;
5936         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5937 }
5938
5939 static void
5940 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5941 {
5942         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5943         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5944         struct ether_addr *mac_addr;
5945         uint32_t i;
5946         int diag;
5947
5948         /*
5949          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5950          * not support the deletion of a given MAC address.
5951          * Instead, it imposes to delete all MAC addresses, then to add again
5952          * all MAC addresses with the exception of the one to be deleted.
5953          */
5954         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5955
5956         /*
5957          * Add again all MAC addresses, with the exception of the deleted one
5958          * and of the permanent MAC address.
5959          */
5960         for (i = 0, mac_addr = dev->data->mac_addrs;
5961              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5962                 /* Skip the deleted MAC address */
5963                 if (i == index)
5964                         continue;
5965                 /* Skip NULL MAC addresses */
5966                 if (is_zero_ether_addr(mac_addr))
5967                         continue;
5968                 /* Skip the permanent MAC address */
5969                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5970                         continue;
5971                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5972                 if (diag != 0)
5973                         PMD_DRV_LOG(ERR,
5974                                     "Adding again MAC address "
5975                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5976                                     "diag=%d",
5977                                     mac_addr->addr_bytes[0],
5978                                     mac_addr->addr_bytes[1],
5979                                     mac_addr->addr_bytes[2],
5980                                     mac_addr->addr_bytes[3],
5981                                     mac_addr->addr_bytes[4],
5982                                     mac_addr->addr_bytes[5],
5983                                     diag);
5984         }
5985 }
5986
5987 static void
5988 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5989 {
5990         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5991
5992         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5993 }
5994
5995 int
5996 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5997                         struct rte_eth_syn_filter *filter,
5998                         bool add)
5999 {
6000         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6001         struct ixgbe_filter_info *filter_info =
6002                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6003         uint32_t syn_info;
6004         uint32_t synqf;
6005
6006         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6007                 return -EINVAL;
6008
6009         syn_info = filter_info->syn_info;
6010
6011         if (add) {
6012                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6013                         return -EINVAL;
6014                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6015                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6016
6017                 if (filter->hig_pri)
6018                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6019                 else
6020                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6021         } else {
6022                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6023                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6024                         return -ENOENT;
6025                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6026         }
6027
6028         filter_info->syn_info = synqf;
6029         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6030         IXGBE_WRITE_FLUSH(hw);
6031         return 0;
6032 }
6033
6034 static int
6035 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6036                         struct rte_eth_syn_filter *filter)
6037 {
6038         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6039         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6040
6041         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6042                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6043                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6044                 return 0;
6045         }
6046         return -ENOENT;
6047 }
6048
6049 static int
6050 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6051                         enum rte_filter_op filter_op,
6052                         void *arg)
6053 {
6054         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6055         int ret;
6056
6057         MAC_TYPE_FILTER_SUP(hw->mac.type);
6058
6059         if (filter_op == RTE_ETH_FILTER_NOP)
6060                 return 0;
6061
6062         if (arg == NULL) {
6063                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6064                             filter_op);
6065                 return -EINVAL;
6066         }
6067
6068         switch (filter_op) {
6069         case RTE_ETH_FILTER_ADD:
6070                 ret = ixgbe_syn_filter_set(dev,
6071                                 (struct rte_eth_syn_filter *)arg,
6072                                 TRUE);
6073                 break;
6074         case RTE_ETH_FILTER_DELETE:
6075                 ret = ixgbe_syn_filter_set(dev,
6076                                 (struct rte_eth_syn_filter *)arg,
6077                                 FALSE);
6078                 break;
6079         case RTE_ETH_FILTER_GET:
6080                 ret = ixgbe_syn_filter_get(dev,
6081                                 (struct rte_eth_syn_filter *)arg);
6082                 break;
6083         default:
6084                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6085                 ret = -EINVAL;
6086                 break;
6087         }
6088
6089         return ret;
6090 }
6091
6092
6093 static inline enum ixgbe_5tuple_protocol
6094 convert_protocol_type(uint8_t protocol_value)
6095 {
6096         if (protocol_value == IPPROTO_TCP)
6097                 return IXGBE_FILTER_PROTOCOL_TCP;
6098         else if (protocol_value == IPPROTO_UDP)
6099                 return IXGBE_FILTER_PROTOCOL_UDP;
6100         else if (protocol_value == IPPROTO_SCTP)
6101                 return IXGBE_FILTER_PROTOCOL_SCTP;
6102         else
6103                 return IXGBE_FILTER_PROTOCOL_NONE;
6104 }
6105
6106 /* inject a 5-tuple filter to HW */
6107 static inline void
6108 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6109                            struct ixgbe_5tuple_filter *filter)
6110 {
6111         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6112         int i;
6113         uint32_t ftqf, sdpqf;
6114         uint32_t l34timir = 0;
6115         uint8_t mask = 0xff;
6116
6117         i = filter->index;
6118
6119         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6120                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6121         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6122
6123         ftqf = (uint32_t)(filter->filter_info.proto &
6124                 IXGBE_FTQF_PROTOCOL_MASK);
6125         ftqf |= (uint32_t)((filter->filter_info.priority &
6126                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6127         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6128                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6129         if (filter->filter_info.dst_ip_mask == 0)
6130                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6131         if (filter->filter_info.src_port_mask == 0)
6132                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6133         if (filter->filter_info.dst_port_mask == 0)
6134                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6135         if (filter->filter_info.proto_mask == 0)
6136                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6137         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6138         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6139         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6140
6141         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6142         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6143         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6144         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6145
6146         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6147         l34timir |= (uint32_t)(filter->queue <<
6148                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6149         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6150 }
6151
6152 /*
6153  * add a 5tuple filter
6154  *
6155  * @param
6156  * dev: Pointer to struct rte_eth_dev.
6157  * index: the index the filter allocates.
6158  * filter: ponter to the filter that will be added.
6159  * rx_queue: the queue id the filter assigned to.
6160  *
6161  * @return
6162  *    - On success, zero.
6163  *    - On failure, a negative value.
6164  */
6165 static int
6166 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6167                         struct ixgbe_5tuple_filter *filter)
6168 {
6169         struct ixgbe_filter_info *filter_info =
6170                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6171         int i, idx, shift;
6172
6173         /*
6174          * look for an unused 5tuple filter index,
6175          * and insert the filter to list.
6176          */
6177         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6178                 idx = i / (sizeof(uint32_t) * NBBY);
6179                 shift = i % (sizeof(uint32_t) * NBBY);
6180                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6181                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6182                         filter->index = i;
6183                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6184                                           filter,
6185                                           entries);
6186                         break;
6187                 }
6188         }
6189         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6190                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6191                 return -ENOSYS;
6192         }
6193
6194         ixgbe_inject_5tuple_filter(dev, filter);
6195
6196         return 0;
6197 }
6198
6199 /*
6200  * remove a 5tuple filter
6201  *
6202  * @param
6203  * dev: Pointer to struct rte_eth_dev.
6204  * filter: the pointer of the filter will be removed.
6205  */
6206 static void
6207 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6208                         struct ixgbe_5tuple_filter *filter)
6209 {
6210         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6211         struct ixgbe_filter_info *filter_info =
6212                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6213         uint16_t index = filter->index;
6214
6215         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6216                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6217         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6218         rte_free(filter);
6219
6220         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6221         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6222         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6223         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6224         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6225 }
6226
6227 static int
6228 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6229 {
6230         struct ixgbe_hw *hw;
6231         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6232
6233         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6234
6235         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6236                 return -EINVAL;
6237
6238         /* refuse mtu that requires the support of scattered packets when this
6239          * feature has not been enabled before.
6240          */
6241         if (!dev->data->scattered_rx &&
6242             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6243              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6244                 return -EINVAL;
6245
6246         /*
6247          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6248          * request of the version 2.0 of the mailbox API.
6249          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6250          * of the mailbox API.
6251          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6252          * prior to 3.11.33 which contains the following change:
6253          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6254          */
6255         ixgbevf_rlpml_set_vf(hw, max_frame);
6256
6257         /* update max frame size */
6258         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6259         return 0;
6260 }
6261
6262 static inline struct ixgbe_5tuple_filter *
6263 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6264                         struct ixgbe_5tuple_filter_info *key)
6265 {
6266         struct ixgbe_5tuple_filter *it;
6267
6268         TAILQ_FOREACH(it, filter_list, entries) {
6269                 if (memcmp(key, &it->filter_info,
6270                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6271                         return it;
6272                 }
6273         }
6274         return NULL;
6275 }
6276
6277 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6278 static inline int
6279 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6280                         struct ixgbe_5tuple_filter_info *filter_info)
6281 {
6282         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6283                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6284                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6285                 return -EINVAL;
6286
6287         switch (filter->dst_ip_mask) {
6288         case UINT32_MAX:
6289                 filter_info->dst_ip_mask = 0;
6290                 filter_info->dst_ip = filter->dst_ip;
6291                 break;
6292         case 0:
6293                 filter_info->dst_ip_mask = 1;
6294                 break;
6295         default:
6296                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6297                 return -EINVAL;
6298         }
6299
6300         switch (filter->src_ip_mask) {
6301         case UINT32_MAX:
6302                 filter_info->src_ip_mask = 0;
6303                 filter_info->src_ip = filter->src_ip;
6304                 break;
6305         case 0:
6306                 filter_info->src_ip_mask = 1;
6307                 break;
6308         default:
6309                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6310                 return -EINVAL;
6311         }
6312
6313         switch (filter->dst_port_mask) {
6314         case UINT16_MAX:
6315                 filter_info->dst_port_mask = 0;
6316                 filter_info->dst_port = filter->dst_port;
6317                 break;
6318         case 0:
6319                 filter_info->dst_port_mask = 1;
6320                 break;
6321         default:
6322                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6323                 return -EINVAL;
6324         }
6325
6326         switch (filter->src_port_mask) {
6327         case UINT16_MAX:
6328                 filter_info->src_port_mask = 0;
6329                 filter_info->src_port = filter->src_port;
6330                 break;
6331         case 0:
6332                 filter_info->src_port_mask = 1;
6333                 break;
6334         default:
6335                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6336                 return -EINVAL;
6337         }
6338
6339         switch (filter->proto_mask) {
6340         case UINT8_MAX:
6341                 filter_info->proto_mask = 0;
6342                 filter_info->proto =
6343                         convert_protocol_type(filter->proto);
6344                 break;
6345         case 0:
6346                 filter_info->proto_mask = 1;
6347                 break;
6348         default:
6349                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6350                 return -EINVAL;
6351         }
6352
6353         filter_info->priority = (uint8_t)filter->priority;
6354         return 0;
6355 }
6356
6357 /*
6358  * add or delete a ntuple filter
6359  *
6360  * @param
6361  * dev: Pointer to struct rte_eth_dev.
6362  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6363  * add: if true, add filter, if false, remove filter
6364  *
6365  * @return
6366  *    - On success, zero.
6367  *    - On failure, a negative value.
6368  */
6369 int
6370 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6371                         struct rte_eth_ntuple_filter *ntuple_filter,
6372                         bool add)
6373 {
6374         struct ixgbe_filter_info *filter_info =
6375                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6376         struct ixgbe_5tuple_filter_info filter_5tuple;
6377         struct ixgbe_5tuple_filter *filter;
6378         int ret;
6379
6380         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6381                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6382                 return -EINVAL;
6383         }
6384
6385         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6386         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6387         if (ret < 0)
6388                 return ret;
6389
6390         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6391                                          &filter_5tuple);
6392         if (filter != NULL && add) {
6393                 PMD_DRV_LOG(ERR, "filter exists.");
6394                 return -EEXIST;
6395         }
6396         if (filter == NULL && !add) {
6397                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6398                 return -ENOENT;
6399         }
6400
6401         if (add) {
6402                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6403                                 sizeof(struct ixgbe_5tuple_filter), 0);
6404                 if (filter == NULL)
6405                         return -ENOMEM;
6406                 (void)rte_memcpy(&filter->filter_info,
6407                                  &filter_5tuple,
6408                                  sizeof(struct ixgbe_5tuple_filter_info));
6409                 filter->queue = ntuple_filter->queue;
6410                 ret = ixgbe_add_5tuple_filter(dev, filter);
6411                 if (ret < 0) {
6412                         rte_free(filter);
6413                         return ret;
6414                 }
6415         } else
6416                 ixgbe_remove_5tuple_filter(dev, filter);
6417
6418         return 0;
6419 }
6420
6421 /*
6422  * get a ntuple filter
6423  *
6424  * @param
6425  * dev: Pointer to struct rte_eth_dev.
6426  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6427  *
6428  * @return
6429  *    - On success, zero.
6430  *    - On failure, a negative value.
6431  */
6432 static int
6433 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6434                         struct rte_eth_ntuple_filter *ntuple_filter)
6435 {
6436         struct ixgbe_filter_info *filter_info =
6437                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6438         struct ixgbe_5tuple_filter_info filter_5tuple;
6439         struct ixgbe_5tuple_filter *filter;
6440         int ret;
6441
6442         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6443                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6444                 return -EINVAL;
6445         }
6446
6447         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6448         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6449         if (ret < 0)
6450                 return ret;
6451
6452         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6453                                          &filter_5tuple);
6454         if (filter == NULL) {
6455                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6456                 return -ENOENT;
6457         }
6458         ntuple_filter->queue = filter->queue;
6459         return 0;
6460 }
6461
6462 /*
6463  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6464  * @dev: pointer to rte_eth_dev structure
6465  * @filter_op:operation will be taken.
6466  * @arg: a pointer to specific structure corresponding to the filter_op
6467  *
6468  * @return
6469  *    - On success, zero.
6470  *    - On failure, a negative value.
6471  */
6472 static int
6473 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6474                                 enum rte_filter_op filter_op,
6475                                 void *arg)
6476 {
6477         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6478         int ret;
6479
6480         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6481
6482         if (filter_op == RTE_ETH_FILTER_NOP)
6483                 return 0;
6484
6485         if (arg == NULL) {
6486                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6487                             filter_op);
6488                 return -EINVAL;
6489         }
6490
6491         switch (filter_op) {
6492         case RTE_ETH_FILTER_ADD:
6493                 ret = ixgbe_add_del_ntuple_filter(dev,
6494                         (struct rte_eth_ntuple_filter *)arg,
6495                         TRUE);
6496                 break;
6497         case RTE_ETH_FILTER_DELETE:
6498                 ret = ixgbe_add_del_ntuple_filter(dev,
6499                         (struct rte_eth_ntuple_filter *)arg,
6500                         FALSE);
6501                 break;
6502         case RTE_ETH_FILTER_GET:
6503                 ret = ixgbe_get_ntuple_filter(dev,
6504                         (struct rte_eth_ntuple_filter *)arg);
6505                 break;
6506         default:
6507                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6508                 ret = -EINVAL;
6509                 break;
6510         }
6511         return ret;
6512 }
6513
6514 int
6515 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6516                         struct rte_eth_ethertype_filter *filter,
6517                         bool add)
6518 {
6519         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6520         struct ixgbe_filter_info *filter_info =
6521                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6522         uint32_t etqf = 0;
6523         uint32_t etqs = 0;
6524         int ret;
6525         struct ixgbe_ethertype_filter ethertype_filter;
6526
6527         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6528                 return -EINVAL;
6529
6530         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6531                 filter->ether_type == ETHER_TYPE_IPv6) {
6532                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6533                         " ethertype filter.", filter->ether_type);
6534                 return -EINVAL;
6535         }
6536
6537         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6538                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6539                 return -EINVAL;
6540         }
6541         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6542                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6543                 return -EINVAL;
6544         }
6545
6546         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6547         if (ret >= 0 && add) {
6548                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6549                             filter->ether_type);
6550                 return -EEXIST;
6551         }
6552         if (ret < 0 && !add) {
6553                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6554                             filter->ether_type);
6555                 return -ENOENT;
6556         }
6557
6558         if (add) {
6559                 etqf = IXGBE_ETQF_FILTER_EN;
6560                 etqf |= (uint32_t)filter->ether_type;
6561                 etqs |= (uint32_t)((filter->queue <<
6562                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6563                                     IXGBE_ETQS_RX_QUEUE);
6564                 etqs |= IXGBE_ETQS_QUEUE_EN;
6565
6566                 ethertype_filter.ethertype = filter->ether_type;
6567                 ethertype_filter.etqf = etqf;
6568                 ethertype_filter.etqs = etqs;
6569                 ethertype_filter.conf = FALSE;
6570                 ret = ixgbe_ethertype_filter_insert(filter_info,
6571                                                     &ethertype_filter);
6572                 if (ret < 0) {
6573                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6574                         return -ENOSPC;
6575                 }
6576         } else {
6577                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6578                 if (ret < 0)
6579                         return -ENOSYS;
6580         }
6581         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6582         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6583         IXGBE_WRITE_FLUSH(hw);
6584
6585         return 0;
6586 }
6587
6588 static int
6589 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6590                         struct rte_eth_ethertype_filter *filter)
6591 {
6592         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6593         struct ixgbe_filter_info *filter_info =
6594                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6595         uint32_t etqf, etqs;
6596         int ret;
6597
6598         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6599         if (ret < 0) {
6600                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6601                             filter->ether_type);
6602                 return -ENOENT;
6603         }
6604
6605         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6606         if (etqf & IXGBE_ETQF_FILTER_EN) {
6607                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6608                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6609                 filter->flags = 0;
6610                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6611                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6612                 return 0;
6613         }
6614         return -ENOENT;
6615 }
6616
6617 /*
6618  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6619  * @dev: pointer to rte_eth_dev structure
6620  * @filter_op:operation will be taken.
6621  * @arg: a pointer to specific structure corresponding to the filter_op
6622  */
6623 static int
6624 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6625                                 enum rte_filter_op filter_op,
6626                                 void *arg)
6627 {
6628         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6629         int ret;
6630
6631         MAC_TYPE_FILTER_SUP(hw->mac.type);
6632
6633         if (filter_op == RTE_ETH_FILTER_NOP)
6634                 return 0;
6635
6636         if (arg == NULL) {
6637                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6638                             filter_op);
6639                 return -EINVAL;
6640         }
6641
6642         switch (filter_op) {
6643         case RTE_ETH_FILTER_ADD:
6644                 ret = ixgbe_add_del_ethertype_filter(dev,
6645                         (struct rte_eth_ethertype_filter *)arg,
6646                         TRUE);
6647                 break;
6648         case RTE_ETH_FILTER_DELETE:
6649                 ret = ixgbe_add_del_ethertype_filter(dev,
6650                         (struct rte_eth_ethertype_filter *)arg,
6651                         FALSE);
6652                 break;
6653         case RTE_ETH_FILTER_GET:
6654                 ret = ixgbe_get_ethertype_filter(dev,
6655                         (struct rte_eth_ethertype_filter *)arg);
6656                 break;
6657         default:
6658                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6659                 ret = -EINVAL;
6660                 break;
6661         }
6662         return ret;
6663 }
6664
6665 static int
6666 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6667                      enum rte_filter_type filter_type,
6668                      enum rte_filter_op filter_op,
6669                      void *arg)
6670 {
6671         int ret = 0;
6672
6673         switch (filter_type) {
6674         case RTE_ETH_FILTER_NTUPLE:
6675                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6676                 break;
6677         case RTE_ETH_FILTER_ETHERTYPE:
6678                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6679                 break;
6680         case RTE_ETH_FILTER_SYN:
6681                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6682                 break;
6683         case RTE_ETH_FILTER_FDIR:
6684                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6685                 break;
6686         case RTE_ETH_FILTER_L2_TUNNEL:
6687                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6688                 break;
6689         case RTE_ETH_FILTER_GENERIC:
6690                 if (filter_op != RTE_ETH_FILTER_GET)
6691                         return -EINVAL;
6692                 *(const void **)arg = &ixgbe_flow_ops;
6693                 break;
6694         default:
6695                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6696                                                         filter_type);
6697                 ret = -EINVAL;
6698                 break;
6699         }
6700
6701         return ret;
6702 }
6703
6704 static u8 *
6705 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6706                         u8 **mc_addr_ptr, u32 *vmdq)
6707 {
6708         u8 *mc_addr;
6709
6710         *vmdq = 0;
6711         mc_addr = *mc_addr_ptr;
6712         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6713         return mc_addr;
6714 }
6715
6716 static int
6717 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6718                           struct ether_addr *mc_addr_set,
6719                           uint32_t nb_mc_addr)
6720 {
6721         struct ixgbe_hw *hw;
6722         u8 *mc_addr_list;
6723
6724         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6725         mc_addr_list = (u8 *)mc_addr_set;
6726         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6727                                          ixgbe_dev_addr_list_itr, TRUE);
6728 }
6729
6730 static uint64_t
6731 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6732 {
6733         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6734         uint64_t systime_cycles;
6735
6736         switch (hw->mac.type) {
6737         case ixgbe_mac_X550:
6738         case ixgbe_mac_X550EM_x:
6739         case ixgbe_mac_X550EM_a:
6740                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6741                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6742                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6743                                 * NSEC_PER_SEC;
6744                 break;
6745         default:
6746                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6747                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6748                                 << 32;
6749         }
6750
6751         return systime_cycles;
6752 }
6753
6754 static uint64_t
6755 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6756 {
6757         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6758         uint64_t rx_tstamp_cycles;
6759
6760         switch (hw->mac.type) {
6761         case ixgbe_mac_X550:
6762         case ixgbe_mac_X550EM_x:
6763         case ixgbe_mac_X550EM_a:
6764                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6765                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6766                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6767                                 * NSEC_PER_SEC;
6768                 break;
6769         default:
6770                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6771                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6772                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6773                                 << 32;
6774         }
6775
6776         return rx_tstamp_cycles;
6777 }
6778
6779 static uint64_t
6780 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6781 {
6782         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6783         uint64_t tx_tstamp_cycles;
6784
6785         switch (hw->mac.type) {
6786         case ixgbe_mac_X550:
6787         case ixgbe_mac_X550EM_x:
6788         case ixgbe_mac_X550EM_a:
6789                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6790                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6791                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6792                                 * NSEC_PER_SEC;
6793                 break;
6794         default:
6795                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6796                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6797                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6798                                 << 32;
6799         }
6800
6801         return tx_tstamp_cycles;
6802 }
6803
6804 static void
6805 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6806 {
6807         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6808         struct ixgbe_adapter *adapter =
6809                 (struct ixgbe_adapter *)dev->data->dev_private;
6810         struct rte_eth_link link;
6811         uint32_t incval = 0;
6812         uint32_t shift = 0;
6813
6814         /* Get current link speed. */
6815         memset(&link, 0, sizeof(link));
6816         ixgbe_dev_link_update(dev, 1);
6817         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6818
6819         switch (link.link_speed) {
6820         case ETH_SPEED_NUM_100M:
6821                 incval = IXGBE_INCVAL_100;
6822                 shift = IXGBE_INCVAL_SHIFT_100;
6823                 break;
6824         case ETH_SPEED_NUM_1G:
6825                 incval = IXGBE_INCVAL_1GB;
6826                 shift = IXGBE_INCVAL_SHIFT_1GB;
6827                 break;
6828         case ETH_SPEED_NUM_10G:
6829         default:
6830                 incval = IXGBE_INCVAL_10GB;
6831                 shift = IXGBE_INCVAL_SHIFT_10GB;
6832                 break;
6833         }
6834
6835         switch (hw->mac.type) {
6836         case ixgbe_mac_X550:
6837         case ixgbe_mac_X550EM_x:
6838         case ixgbe_mac_X550EM_a:
6839                 /* Independent of link speed. */
6840                 incval = 1;
6841                 /* Cycles read will be interpreted as ns. */
6842                 shift = 0;
6843                 /* Fall-through */
6844         case ixgbe_mac_X540:
6845                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6846                 break;
6847         case ixgbe_mac_82599EB:
6848                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6849                 shift -= IXGBE_INCVAL_SHIFT_82599;
6850                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6851                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6852                 break;
6853         default:
6854                 /* Not supported. */
6855                 return;
6856         }
6857
6858         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6859         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6860         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6861
6862         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6863         adapter->systime_tc.cc_shift = shift;
6864         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6865
6866         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6867         adapter->rx_tstamp_tc.cc_shift = shift;
6868         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6869
6870         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6871         adapter->tx_tstamp_tc.cc_shift = shift;
6872         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6873 }
6874
6875 static int
6876 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6877 {
6878         struct ixgbe_adapter *adapter =
6879                         (struct ixgbe_adapter *)dev->data->dev_private;
6880
6881         adapter->systime_tc.nsec += delta;
6882         adapter->rx_tstamp_tc.nsec += delta;
6883         adapter->tx_tstamp_tc.nsec += delta;
6884
6885         return 0;
6886 }
6887
6888 static int
6889 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6890 {
6891         uint64_t ns;
6892         struct ixgbe_adapter *adapter =
6893                         (struct ixgbe_adapter *)dev->data->dev_private;
6894
6895         ns = rte_timespec_to_ns(ts);
6896         /* Set the timecounters to a new value. */
6897         adapter->systime_tc.nsec = ns;
6898         adapter->rx_tstamp_tc.nsec = ns;
6899         adapter->tx_tstamp_tc.nsec = ns;
6900
6901         return 0;
6902 }
6903
6904 static int
6905 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6906 {
6907         uint64_t ns, systime_cycles;
6908         struct ixgbe_adapter *adapter =
6909                         (struct ixgbe_adapter *)dev->data->dev_private;
6910
6911         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6912         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6913         *ts = rte_ns_to_timespec(ns);
6914
6915         return 0;
6916 }
6917
6918 static int
6919 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6920 {
6921         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6922         uint32_t tsync_ctl;
6923         uint32_t tsauxc;
6924
6925         /* Stop the timesync system time. */
6926         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6927         /* Reset the timesync system time value. */
6928         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6929         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6930
6931         /* Enable system time for platforms where it isn't on by default. */
6932         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6933         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6934         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6935
6936         ixgbe_start_timecounters(dev);
6937
6938         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6939         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6940                         (ETHER_TYPE_1588 |
6941                          IXGBE_ETQF_FILTER_EN |
6942                          IXGBE_ETQF_1588));
6943
6944         /* Enable timestamping of received PTP packets. */
6945         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6946         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6947         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6948
6949         /* Enable timestamping of transmitted PTP packets. */
6950         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6951         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6952         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6953
6954         IXGBE_WRITE_FLUSH(hw);
6955
6956         return 0;
6957 }
6958
6959 static int
6960 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6961 {
6962         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6963         uint32_t tsync_ctl;
6964
6965         /* Disable timestamping of transmitted PTP packets. */
6966         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6967         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6968         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6969
6970         /* Disable timestamping of received PTP packets. */
6971         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6972         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6973         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6974
6975         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6976         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6977
6978         /* Stop incrementating the System Time registers. */
6979         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6980
6981         return 0;
6982 }
6983
6984 static int
6985 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6986                                  struct timespec *timestamp,
6987                                  uint32_t flags __rte_unused)
6988 {
6989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6990         struct ixgbe_adapter *adapter =
6991                 (struct ixgbe_adapter *)dev->data->dev_private;
6992         uint32_t tsync_rxctl;
6993         uint64_t rx_tstamp_cycles;
6994         uint64_t ns;
6995
6996         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6997         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6998                 return -EINVAL;
6999
7000         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7001         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7002         *timestamp = rte_ns_to_timespec(ns);
7003
7004         return  0;
7005 }
7006
7007 static int
7008 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7009                                  struct timespec *timestamp)
7010 {
7011         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7012         struct ixgbe_adapter *adapter =
7013                 (struct ixgbe_adapter *)dev->data->dev_private;
7014         uint32_t tsync_txctl;
7015         uint64_t tx_tstamp_cycles;
7016         uint64_t ns;
7017
7018         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7019         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7020                 return -EINVAL;
7021
7022         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7023         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7024         *timestamp = rte_ns_to_timespec(ns);
7025
7026         return 0;
7027 }
7028
7029 static int
7030 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7031 {
7032         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7033         int count = 0;
7034         int g_ind = 0;
7035         const struct reg_info *reg_group;
7036         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7037                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7038
7039         while ((reg_group = reg_set[g_ind++]))
7040                 count += ixgbe_regs_group_count(reg_group);
7041
7042         return count;
7043 }
7044
7045 static int
7046 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7047 {
7048         int count = 0;
7049         int g_ind = 0;
7050         const struct reg_info *reg_group;
7051
7052         while ((reg_group = ixgbevf_regs[g_ind++]))
7053                 count += ixgbe_regs_group_count(reg_group);
7054
7055         return count;
7056 }
7057
7058 static int
7059 ixgbe_get_regs(struct rte_eth_dev *dev,
7060               struct rte_dev_reg_info *regs)
7061 {
7062         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7063         uint32_t *data = regs->data;
7064         int g_ind = 0;
7065         int count = 0;
7066         const struct reg_info *reg_group;
7067         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7068                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7069
7070         if (data == NULL) {
7071                 regs->length = ixgbe_get_reg_length(dev);
7072                 regs->width = sizeof(uint32_t);
7073                 return 0;
7074         }
7075
7076         /* Support only full register dump */
7077         if ((regs->length == 0) ||
7078             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7079                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7080                         hw->device_id;
7081                 while ((reg_group = reg_set[g_ind++]))
7082                         count += ixgbe_read_regs_group(dev, &data[count],
7083                                 reg_group);
7084                 return 0;
7085         }
7086
7087         return -ENOTSUP;
7088 }
7089
7090 static int
7091 ixgbevf_get_regs(struct rte_eth_dev *dev,
7092                 struct rte_dev_reg_info *regs)
7093 {
7094         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7095         uint32_t *data = regs->data;
7096         int g_ind = 0;
7097         int count = 0;
7098         const struct reg_info *reg_group;
7099
7100         if (data == NULL) {
7101                 regs->length = ixgbevf_get_reg_length(dev);
7102                 regs->width = sizeof(uint32_t);
7103                 return 0;
7104         }
7105
7106         /* Support only full register dump */
7107         if ((regs->length == 0) ||
7108             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7109                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7110                         hw->device_id;
7111                 while ((reg_group = ixgbevf_regs[g_ind++]))
7112                         count += ixgbe_read_regs_group(dev, &data[count],
7113                                                       reg_group);
7114                 return 0;
7115         }
7116
7117         return -ENOTSUP;
7118 }
7119
7120 static int
7121 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7122 {
7123         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7124
7125         /* Return unit is byte count */
7126         return hw->eeprom.word_size * 2;
7127 }
7128
7129 static int
7130 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7131                 struct rte_dev_eeprom_info *in_eeprom)
7132 {
7133         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7134         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7135         uint16_t *data = in_eeprom->data;
7136         int first, length;
7137
7138         first = in_eeprom->offset >> 1;
7139         length = in_eeprom->length >> 1;
7140         if ((first > hw->eeprom.word_size) ||
7141             ((first + length) > hw->eeprom.word_size))
7142                 return -EINVAL;
7143
7144         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7145
7146         return eeprom->ops.read_buffer(hw, first, length, data);
7147 }
7148
7149 static int
7150 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7151                 struct rte_dev_eeprom_info *in_eeprom)
7152 {
7153         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7154         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7155         uint16_t *data = in_eeprom->data;
7156         int first, length;
7157
7158         first = in_eeprom->offset >> 1;
7159         length = in_eeprom->length >> 1;
7160         if ((first > hw->eeprom.word_size) ||
7161             ((first + length) > hw->eeprom.word_size))
7162                 return -EINVAL;
7163
7164         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7165
7166         return eeprom->ops.write_buffer(hw,  first, length, data);
7167 }
7168
7169 uint16_t
7170 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7171         switch (mac_type) {
7172         case ixgbe_mac_X550:
7173         case ixgbe_mac_X550EM_x:
7174         case ixgbe_mac_X550EM_a:
7175                 return ETH_RSS_RETA_SIZE_512;
7176         case ixgbe_mac_X550_vf:
7177         case ixgbe_mac_X550EM_x_vf:
7178         case ixgbe_mac_X550EM_a_vf:
7179                 return ETH_RSS_RETA_SIZE_64;
7180         default:
7181                 return ETH_RSS_RETA_SIZE_128;
7182         }
7183 }
7184
7185 uint32_t
7186 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7187         switch (mac_type) {
7188         case ixgbe_mac_X550:
7189         case ixgbe_mac_X550EM_x:
7190         case ixgbe_mac_X550EM_a:
7191                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7192                         return IXGBE_RETA(reta_idx >> 2);
7193                 else
7194                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7195         case ixgbe_mac_X550_vf:
7196         case ixgbe_mac_X550EM_x_vf:
7197         case ixgbe_mac_X550EM_a_vf:
7198                 return IXGBE_VFRETA(reta_idx >> 2);
7199         default:
7200                 return IXGBE_RETA(reta_idx >> 2);
7201         }
7202 }
7203
7204 uint32_t
7205 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7206         switch (mac_type) {
7207         case ixgbe_mac_X550_vf:
7208         case ixgbe_mac_X550EM_x_vf:
7209         case ixgbe_mac_X550EM_a_vf:
7210                 return IXGBE_VFMRQC;
7211         default:
7212                 return IXGBE_MRQC;
7213         }
7214 }
7215
7216 uint32_t
7217 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7218         switch (mac_type) {
7219         case ixgbe_mac_X550_vf:
7220         case ixgbe_mac_X550EM_x_vf:
7221         case ixgbe_mac_X550EM_a_vf:
7222                 return IXGBE_VFRSSRK(i);
7223         default:
7224                 return IXGBE_RSSRK(i);
7225         }
7226 }
7227
7228 bool
7229 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7230         switch (mac_type) {
7231         case ixgbe_mac_82599_vf:
7232         case ixgbe_mac_X540_vf:
7233                 return 0;
7234         default:
7235                 return 1;
7236         }
7237 }
7238
7239 static int
7240 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7241                         struct rte_eth_dcb_info *dcb_info)
7242 {
7243         struct ixgbe_dcb_config *dcb_config =
7244                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7245         struct ixgbe_dcb_tc_config *tc;
7246         uint8_t i, j;
7247
7248         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7249                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7250         else
7251                 dcb_info->nb_tcs = 1;
7252
7253         if (dcb_config->vt_mode) { /* vt is enabled*/
7254                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7255                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7256                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7257                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7258                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7259                         for (j = 0; j < dcb_info->nb_tcs; j++) {
7260                                 dcb_info->tc_queue.tc_rxq[i][j].base =
7261                                                 i * dcb_info->nb_tcs + j;
7262                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7263                                 dcb_info->tc_queue.tc_txq[i][j].base =
7264                                                 i * dcb_info->nb_tcs + j;
7265                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7266                         }
7267                 }
7268         } else { /* vt is disabled*/
7269                 struct rte_eth_dcb_rx_conf *rx_conf =
7270                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7271                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7272                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7273                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7274                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7275                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7276                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7277                         }
7278                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7279                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7280                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7281                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7282                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7283                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7284                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7285                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7286                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7287                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7288                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7289                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7290                         }
7291                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7292                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7293                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7294                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7295                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7296                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7297                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7298                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7299                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7300                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7301                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7302                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7303                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7304                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7305                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7306                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7307                 }
7308         }
7309         for (i = 0; i < dcb_info->nb_tcs; i++) {
7310                 tc = &dcb_config->tc_config[i];
7311                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7312         }
7313         return 0;
7314 }
7315
7316 /* Update e-tag ether type */
7317 static int
7318 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7319                             uint16_t ether_type)
7320 {
7321         uint32_t etag_etype;
7322
7323         if (hw->mac.type != ixgbe_mac_X550 &&
7324             hw->mac.type != ixgbe_mac_X550EM_x &&
7325             hw->mac.type != ixgbe_mac_X550EM_a) {
7326                 return -ENOTSUP;
7327         }
7328
7329         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7330         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7331         etag_etype |= ether_type;
7332         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7333         IXGBE_WRITE_FLUSH(hw);
7334
7335         return 0;
7336 }
7337
7338 /* Config l2 tunnel ether type */
7339 static int
7340 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7341                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7342 {
7343         int ret = 0;
7344         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7345         struct ixgbe_l2_tn_info *l2_tn_info =
7346                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7347
7348         if (l2_tunnel == NULL)
7349                 return -EINVAL;
7350
7351         switch (l2_tunnel->l2_tunnel_type) {
7352         case RTE_L2_TUNNEL_TYPE_E_TAG:
7353                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7354                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7355                 break;
7356         default:
7357                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7358                 ret = -EINVAL;
7359                 break;
7360         }
7361
7362         return ret;
7363 }
7364
7365 /* Enable e-tag tunnel */
7366 static int
7367 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7368 {
7369         uint32_t etag_etype;
7370
7371         if (hw->mac.type != ixgbe_mac_X550 &&
7372             hw->mac.type != ixgbe_mac_X550EM_x &&
7373             hw->mac.type != ixgbe_mac_X550EM_a) {
7374                 return -ENOTSUP;
7375         }
7376
7377         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7378         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7379         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7380         IXGBE_WRITE_FLUSH(hw);
7381
7382         return 0;
7383 }
7384
7385 /* Enable l2 tunnel */
7386 static int
7387 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7388                            enum rte_eth_tunnel_type l2_tunnel_type)
7389 {
7390         int ret = 0;
7391         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7392         struct ixgbe_l2_tn_info *l2_tn_info =
7393                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7394
7395         switch (l2_tunnel_type) {
7396         case RTE_L2_TUNNEL_TYPE_E_TAG:
7397                 l2_tn_info->e_tag_en = TRUE;
7398                 ret = ixgbe_e_tag_enable(hw);
7399                 break;
7400         default:
7401                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7402                 ret = -EINVAL;
7403                 break;
7404         }
7405
7406         return ret;
7407 }
7408
7409 /* Disable e-tag tunnel */
7410 static int
7411 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7412 {
7413         uint32_t etag_etype;
7414
7415         if (hw->mac.type != ixgbe_mac_X550 &&
7416             hw->mac.type != ixgbe_mac_X550EM_x &&
7417             hw->mac.type != ixgbe_mac_X550EM_a) {
7418                 return -ENOTSUP;
7419         }
7420
7421         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7422         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7423         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7424         IXGBE_WRITE_FLUSH(hw);
7425
7426         return 0;
7427 }
7428
7429 /* Disable l2 tunnel */
7430 static int
7431 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7432                             enum rte_eth_tunnel_type l2_tunnel_type)
7433 {
7434         int ret = 0;
7435         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7436         struct ixgbe_l2_tn_info *l2_tn_info =
7437                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7438
7439         switch (l2_tunnel_type) {
7440         case RTE_L2_TUNNEL_TYPE_E_TAG:
7441                 l2_tn_info->e_tag_en = FALSE;
7442                 ret = ixgbe_e_tag_disable(hw);
7443                 break;
7444         default:
7445                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7446                 ret = -EINVAL;
7447                 break;
7448         }
7449
7450         return ret;
7451 }
7452
7453 static int
7454 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7455                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7456 {
7457         int ret = 0;
7458         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7459         uint32_t i, rar_entries;
7460         uint32_t rar_low, rar_high;
7461
7462         if (hw->mac.type != ixgbe_mac_X550 &&
7463             hw->mac.type != ixgbe_mac_X550EM_x &&
7464             hw->mac.type != ixgbe_mac_X550EM_a) {
7465                 return -ENOTSUP;
7466         }
7467
7468         rar_entries = ixgbe_get_num_rx_addrs(hw);
7469
7470         for (i = 1; i < rar_entries; i++) {
7471                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7472                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7473                 if ((rar_high & IXGBE_RAH_AV) &&
7474                     (rar_high & IXGBE_RAH_ADTYPE) &&
7475                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7476                      l2_tunnel->tunnel_id)) {
7477                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7478                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7479
7480                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7481
7482                         return ret;
7483                 }
7484         }
7485
7486         return ret;
7487 }
7488
7489 static int
7490 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7491                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7492 {
7493         int ret = 0;
7494         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7495         uint32_t i, rar_entries;
7496         uint32_t rar_low, rar_high;
7497
7498         if (hw->mac.type != ixgbe_mac_X550 &&
7499             hw->mac.type != ixgbe_mac_X550EM_x &&
7500             hw->mac.type != ixgbe_mac_X550EM_a) {
7501                 return -ENOTSUP;
7502         }
7503
7504         /* One entry for one tunnel. Try to remove potential existing entry. */
7505         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7506
7507         rar_entries = ixgbe_get_num_rx_addrs(hw);
7508
7509         for (i = 1; i < rar_entries; i++) {
7510                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7511                 if (rar_high & IXGBE_RAH_AV) {
7512                         continue;
7513                 } else {
7514                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7515                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7516                         rar_low = l2_tunnel->tunnel_id;
7517
7518                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7519                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7520
7521                         return ret;
7522                 }
7523         }
7524
7525         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7526                      " Please remove a rule before adding a new one.");
7527         return -EINVAL;
7528 }
7529
7530 static inline struct ixgbe_l2_tn_filter *
7531 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7532                           struct ixgbe_l2_tn_key *key)
7533 {
7534         int ret;
7535
7536         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7537         if (ret < 0)
7538                 return NULL;
7539
7540         return l2_tn_info->hash_map[ret];
7541 }
7542
7543 static inline int
7544 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7545                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7546 {
7547         int ret;
7548
7549         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7550                                &l2_tn_filter->key);
7551
7552         if (ret < 0) {
7553                 PMD_DRV_LOG(ERR,
7554                             "Failed to insert L2 tunnel filter"
7555                             " to hash table %d!",
7556                             ret);
7557                 return ret;
7558         }
7559
7560         l2_tn_info->hash_map[ret] = l2_tn_filter;
7561
7562         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7563
7564         return 0;
7565 }
7566
7567 static inline int
7568 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7569                           struct ixgbe_l2_tn_key *key)
7570 {
7571         int ret;
7572         struct ixgbe_l2_tn_filter *l2_tn_filter;
7573
7574         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7575
7576         if (ret < 0) {
7577                 PMD_DRV_LOG(ERR,
7578                             "No such L2 tunnel filter to delete %d!",
7579                             ret);
7580                 return ret;
7581         }
7582
7583         l2_tn_filter = l2_tn_info->hash_map[ret];
7584         l2_tn_info->hash_map[ret] = NULL;
7585
7586         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7587         rte_free(l2_tn_filter);
7588
7589         return 0;
7590 }
7591
7592 /* Add l2 tunnel filter */
7593 int
7594 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7595                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7596                                bool restore)
7597 {
7598         int ret;
7599         struct ixgbe_l2_tn_info *l2_tn_info =
7600                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7601         struct ixgbe_l2_tn_key key;
7602         struct ixgbe_l2_tn_filter *node;
7603
7604         if (!restore) {
7605                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7606                 key.tn_id = l2_tunnel->tunnel_id;
7607
7608                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7609
7610                 if (node) {
7611                         PMD_DRV_LOG(ERR,
7612                                     "The L2 tunnel filter already exists!");
7613                         return -EINVAL;
7614                 }
7615
7616                 node = rte_zmalloc("ixgbe_l2_tn",
7617                                    sizeof(struct ixgbe_l2_tn_filter),
7618                                    0);
7619                 if (!node)
7620                         return -ENOMEM;
7621
7622                 (void)rte_memcpy(&node->key,
7623                                  &key,
7624                                  sizeof(struct ixgbe_l2_tn_key));
7625                 node->pool = l2_tunnel->pool;
7626                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7627                 if (ret < 0) {
7628                         rte_free(node);
7629                         return ret;
7630                 }
7631         }
7632
7633         switch (l2_tunnel->l2_tunnel_type) {
7634         case RTE_L2_TUNNEL_TYPE_E_TAG:
7635                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7636                 break;
7637         default:
7638                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7639                 ret = -EINVAL;
7640                 break;
7641         }
7642
7643         if ((!restore) && (ret < 0))
7644                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7645
7646         return ret;
7647 }
7648
7649 /* Delete l2 tunnel filter */
7650 int
7651 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7652                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7653 {
7654         int ret;
7655         struct ixgbe_l2_tn_info *l2_tn_info =
7656                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7657         struct ixgbe_l2_tn_key key;
7658
7659         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7660         key.tn_id = l2_tunnel->tunnel_id;
7661         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7662         if (ret < 0)
7663                 return ret;
7664
7665         switch (l2_tunnel->l2_tunnel_type) {
7666         case RTE_L2_TUNNEL_TYPE_E_TAG:
7667                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7668                 break;
7669         default:
7670                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7671                 ret = -EINVAL;
7672                 break;
7673         }
7674
7675         return ret;
7676 }
7677
7678 /**
7679  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7680  * @dev: pointer to rte_eth_dev structure
7681  * @filter_op:operation will be taken.
7682  * @arg: a pointer to specific structure corresponding to the filter_op
7683  */
7684 static int
7685 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7686                                   enum rte_filter_op filter_op,
7687                                   void *arg)
7688 {
7689         int ret;
7690
7691         if (filter_op == RTE_ETH_FILTER_NOP)
7692                 return 0;
7693
7694         if (arg == NULL) {
7695                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7696                             filter_op);
7697                 return -EINVAL;
7698         }
7699
7700         switch (filter_op) {
7701         case RTE_ETH_FILTER_ADD:
7702                 ret = ixgbe_dev_l2_tunnel_filter_add
7703                         (dev,
7704                          (struct rte_eth_l2_tunnel_conf *)arg,
7705                          FALSE);
7706                 break;
7707         case RTE_ETH_FILTER_DELETE:
7708                 ret = ixgbe_dev_l2_tunnel_filter_del
7709                         (dev,
7710                          (struct rte_eth_l2_tunnel_conf *)arg);
7711                 break;
7712         default:
7713                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7714                 ret = -EINVAL;
7715                 break;
7716         }
7717         return ret;
7718 }
7719
7720 static int
7721 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7722 {
7723         int ret = 0;
7724         uint32_t ctrl;
7725         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7726
7727         if (hw->mac.type != ixgbe_mac_X550 &&
7728             hw->mac.type != ixgbe_mac_X550EM_x &&
7729             hw->mac.type != ixgbe_mac_X550EM_a) {
7730                 return -ENOTSUP;
7731         }
7732
7733         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7734         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7735         if (en)
7736                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7737         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7738
7739         return ret;
7740 }
7741
7742 /* Enable l2 tunnel forwarding */
7743 static int
7744 ixgbe_dev_l2_tunnel_forwarding_enable
7745         (struct rte_eth_dev *dev,
7746          enum rte_eth_tunnel_type l2_tunnel_type)
7747 {
7748         struct ixgbe_l2_tn_info *l2_tn_info =
7749                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7750         int ret = 0;
7751
7752         switch (l2_tunnel_type) {
7753         case RTE_L2_TUNNEL_TYPE_E_TAG:
7754                 l2_tn_info->e_tag_fwd_en = TRUE;
7755                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7756                 break;
7757         default:
7758                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7759                 ret = -EINVAL;
7760                 break;
7761         }
7762
7763         return ret;
7764 }
7765
7766 /* Disable l2 tunnel forwarding */
7767 static int
7768 ixgbe_dev_l2_tunnel_forwarding_disable
7769         (struct rte_eth_dev *dev,
7770          enum rte_eth_tunnel_type l2_tunnel_type)
7771 {
7772         struct ixgbe_l2_tn_info *l2_tn_info =
7773                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7774         int ret = 0;
7775
7776         switch (l2_tunnel_type) {
7777         case RTE_L2_TUNNEL_TYPE_E_TAG:
7778                 l2_tn_info->e_tag_fwd_en = FALSE;
7779                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7780                 break;
7781         default:
7782                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7783                 ret = -EINVAL;
7784                 break;
7785         }
7786
7787         return ret;
7788 }
7789
7790 static int
7791 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7792                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7793                              bool en)
7794 {
7795         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7796         int ret = 0;
7797         uint32_t vmtir, vmvir;
7798         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7799
7800         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7801                 PMD_DRV_LOG(ERR,
7802                             "VF id %u should be less than %u",
7803                             l2_tunnel->vf_id,
7804                             pci_dev->max_vfs);
7805                 return -EINVAL;
7806         }
7807
7808         if (hw->mac.type != ixgbe_mac_X550 &&
7809             hw->mac.type != ixgbe_mac_X550EM_x &&
7810             hw->mac.type != ixgbe_mac_X550EM_a) {
7811                 return -ENOTSUP;
7812         }
7813
7814         if (en)
7815                 vmtir = l2_tunnel->tunnel_id;
7816         else
7817                 vmtir = 0;
7818
7819         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7820
7821         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7822         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7823         if (en)
7824                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7825         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7826
7827         return ret;
7828 }
7829
7830 /* Enable l2 tunnel tag insertion */
7831 static int
7832 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7833                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7834 {
7835         int ret = 0;
7836
7837         switch (l2_tunnel->l2_tunnel_type) {
7838         case RTE_L2_TUNNEL_TYPE_E_TAG:
7839                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7840                 break;
7841         default:
7842                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7843                 ret = -EINVAL;
7844                 break;
7845         }
7846
7847         return ret;
7848 }
7849
7850 /* Disable l2 tunnel tag insertion */
7851 static int
7852 ixgbe_dev_l2_tunnel_insertion_disable
7853         (struct rte_eth_dev *dev,
7854          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7855 {
7856         int ret = 0;
7857
7858         switch (l2_tunnel->l2_tunnel_type) {
7859         case RTE_L2_TUNNEL_TYPE_E_TAG:
7860                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7861                 break;
7862         default:
7863                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7864                 ret = -EINVAL;
7865                 break;
7866         }
7867
7868         return ret;
7869 }
7870
7871 static int
7872 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7873                              bool en)
7874 {
7875         int ret = 0;
7876         uint32_t qde;
7877         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7878
7879         if (hw->mac.type != ixgbe_mac_X550 &&
7880             hw->mac.type != ixgbe_mac_X550EM_x &&
7881             hw->mac.type != ixgbe_mac_X550EM_a) {
7882                 return -ENOTSUP;
7883         }
7884
7885         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7886         if (en)
7887                 qde |= IXGBE_QDE_STRIP_TAG;
7888         else
7889                 qde &= ~IXGBE_QDE_STRIP_TAG;
7890         qde &= ~IXGBE_QDE_READ;
7891         qde |= IXGBE_QDE_WRITE;
7892         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7893
7894         return ret;
7895 }
7896
7897 /* Enable l2 tunnel tag stripping */
7898 static int
7899 ixgbe_dev_l2_tunnel_stripping_enable
7900         (struct rte_eth_dev *dev,
7901          enum rte_eth_tunnel_type l2_tunnel_type)
7902 {
7903         int ret = 0;
7904
7905         switch (l2_tunnel_type) {
7906         case RTE_L2_TUNNEL_TYPE_E_TAG:
7907                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7908                 break;
7909         default:
7910                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7911                 ret = -EINVAL;
7912                 break;
7913         }
7914
7915         return ret;
7916 }
7917
7918 /* Disable l2 tunnel tag stripping */
7919 static int
7920 ixgbe_dev_l2_tunnel_stripping_disable
7921         (struct rte_eth_dev *dev,
7922          enum rte_eth_tunnel_type l2_tunnel_type)
7923 {
7924         int ret = 0;
7925
7926         switch (l2_tunnel_type) {
7927         case RTE_L2_TUNNEL_TYPE_E_TAG:
7928                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7929                 break;
7930         default:
7931                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7932                 ret = -EINVAL;
7933                 break;
7934         }
7935
7936         return ret;
7937 }
7938
7939 /* Enable/disable l2 tunnel offload functions */
7940 static int
7941 ixgbe_dev_l2_tunnel_offload_set
7942         (struct rte_eth_dev *dev,
7943          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7944          uint32_t mask,
7945          uint8_t en)
7946 {
7947         int ret = 0;
7948
7949         if (l2_tunnel == NULL)
7950                 return -EINVAL;
7951
7952         ret = -EINVAL;
7953         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7954                 if (en)
7955                         ret = ixgbe_dev_l2_tunnel_enable(
7956                                 dev,
7957                                 l2_tunnel->l2_tunnel_type);
7958                 else
7959                         ret = ixgbe_dev_l2_tunnel_disable(
7960                                 dev,
7961                                 l2_tunnel->l2_tunnel_type);
7962         }
7963
7964         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7965                 if (en)
7966                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7967                                 dev,
7968                                 l2_tunnel);
7969                 else
7970                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7971                                 dev,
7972                                 l2_tunnel);
7973         }
7974
7975         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7976                 if (en)
7977                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7978                                 dev,
7979                                 l2_tunnel->l2_tunnel_type);
7980                 else
7981                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7982                                 dev,
7983                                 l2_tunnel->l2_tunnel_type);
7984         }
7985
7986         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7987                 if (en)
7988                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7989                                 dev,
7990                                 l2_tunnel->l2_tunnel_type);
7991                 else
7992                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7993                                 dev,
7994                                 l2_tunnel->l2_tunnel_type);
7995         }
7996
7997         return ret;
7998 }
7999
8000 static int
8001 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8002                         uint16_t port)
8003 {
8004         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8005         IXGBE_WRITE_FLUSH(hw);
8006
8007         return 0;
8008 }
8009
8010 /* There's only one register for VxLAN UDP port.
8011  * So, we cannot add several ports. Will update it.
8012  */
8013 static int
8014 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8015                      uint16_t port)
8016 {
8017         if (port == 0) {
8018                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8019                 return -EINVAL;
8020         }
8021
8022         return ixgbe_update_vxlan_port(hw, port);
8023 }
8024
8025 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8026  * UDP port, it must have a value.
8027  * So, will reset it to the original value 0.
8028  */
8029 static int
8030 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8031                      uint16_t port)
8032 {
8033         uint16_t cur_port;
8034
8035         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8036
8037         if (cur_port != port) {
8038                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8039                 return -EINVAL;
8040         }
8041
8042         return ixgbe_update_vxlan_port(hw, 0);
8043 }
8044
8045 /* Add UDP tunneling port */
8046 static int
8047 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8048                               struct rte_eth_udp_tunnel *udp_tunnel)
8049 {
8050         int ret = 0;
8051         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8052
8053         if (hw->mac.type != ixgbe_mac_X550 &&
8054             hw->mac.type != ixgbe_mac_X550EM_x &&
8055             hw->mac.type != ixgbe_mac_X550EM_a) {
8056                 return -ENOTSUP;
8057         }
8058
8059         if (udp_tunnel == NULL)
8060                 return -EINVAL;
8061
8062         switch (udp_tunnel->prot_type) {
8063         case RTE_TUNNEL_TYPE_VXLAN:
8064                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8065                 break;
8066
8067         case RTE_TUNNEL_TYPE_GENEVE:
8068         case RTE_TUNNEL_TYPE_TEREDO:
8069                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8070                 ret = -EINVAL;
8071                 break;
8072
8073         default:
8074                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8075                 ret = -EINVAL;
8076                 break;
8077         }
8078
8079         return ret;
8080 }
8081
8082 /* Remove UDP tunneling port */
8083 static int
8084 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8085                               struct rte_eth_udp_tunnel *udp_tunnel)
8086 {
8087         int ret = 0;
8088         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8089
8090         if (hw->mac.type != ixgbe_mac_X550 &&
8091             hw->mac.type != ixgbe_mac_X550EM_x &&
8092             hw->mac.type != ixgbe_mac_X550EM_a) {
8093                 return -ENOTSUP;
8094         }
8095
8096         if (udp_tunnel == NULL)
8097                 return -EINVAL;
8098
8099         switch (udp_tunnel->prot_type) {
8100         case RTE_TUNNEL_TYPE_VXLAN:
8101                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8102                 break;
8103         case RTE_TUNNEL_TYPE_GENEVE:
8104         case RTE_TUNNEL_TYPE_TEREDO:
8105                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8106                 ret = -EINVAL;
8107                 break;
8108         default:
8109                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8110                 ret = -EINVAL;
8111                 break;
8112         }
8113
8114         return ret;
8115 }
8116
8117 static void
8118 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8119 {
8120         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8121
8122         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8123 }
8124
8125 static void
8126 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8127 {
8128         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8129
8130         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8131 }
8132
8133 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8134 {
8135         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8136         u32 in_msg = 0;
8137
8138         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8139                 return;
8140
8141         /* PF reset VF event */
8142         if (in_msg == IXGBE_PF_CONTROL_MSG)
8143                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
8144 }
8145
8146 static int
8147 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8148 {
8149         uint32_t eicr;
8150         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8151         struct ixgbe_interrupt *intr =
8152                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8153         ixgbevf_intr_disable(hw);
8154
8155         /* read-on-clear nic registers here */
8156         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8157         intr->flags = 0;
8158
8159         /* only one misc vector supported - mailbox */
8160         eicr &= IXGBE_VTEICR_MASK;
8161         if (eicr == IXGBE_MISC_VEC_ID)
8162                 intr->flags |= IXGBE_FLAG_MAILBOX;
8163
8164         return 0;
8165 }
8166
8167 static int
8168 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8169 {
8170         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8171         struct ixgbe_interrupt *intr =
8172                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8173
8174         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8175                 ixgbevf_mbx_process(dev);
8176                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8177         }
8178
8179         ixgbevf_intr_enable(hw);
8180
8181         return 0;
8182 }
8183
8184 static void
8185 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
8186                               void *param)
8187 {
8188         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8189
8190         ixgbevf_dev_interrupt_get_status(dev);
8191         ixgbevf_dev_interrupt_action(dev);
8192 }
8193
8194 /**
8195  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8196  *  @hw: pointer to hardware structure
8197  *
8198  *  Stops the transmit data path and waits for the HW to internally empty
8199  *  the Tx security block
8200  **/
8201 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8202 {
8203 #define IXGBE_MAX_SECTX_POLL 40
8204
8205         int i;
8206         int sectxreg;
8207
8208         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8209         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8210         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8211         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8212                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8213                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8214                         break;
8215                 /* Use interrupt-safe sleep just in case */
8216                 usec_delay(1000);
8217         }
8218
8219         /* For informational purposes only */
8220         if (i >= IXGBE_MAX_SECTX_POLL)
8221                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8222                          "path fully disabled.  Continuing with init.");
8223
8224         return IXGBE_SUCCESS;
8225 }
8226
8227 /**
8228  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8229  *  @hw: pointer to hardware structure
8230  *
8231  *  Enables the transmit data path.
8232  **/
8233 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8234 {
8235         uint32_t sectxreg;
8236
8237         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8238         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8239         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8240         IXGBE_WRITE_FLUSH(hw);
8241
8242         return IXGBE_SUCCESS;
8243 }
8244
8245 int
8246 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
8247 {
8248         struct ixgbe_hw *hw;
8249         struct rte_eth_dev *dev;
8250         uint32_t ctrl;
8251
8252         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8253
8254         dev = &rte_eth_devices[port];
8255
8256         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8257                 return -ENOTSUP;
8258
8259         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8260
8261         /* Stop the data paths */
8262         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8263                 return -ENOTSUP;
8264         /*
8265          * Workaround:
8266          * As no ixgbe_disable_sec_rx_path equivalent is
8267          * implemented for tx in the base code, and we are
8268          * not allowed to modify the base code in DPDK, so
8269          * just call the hand-written one directly for now.
8270          * The hardware support has been checked by
8271          * ixgbe_disable_sec_rx_path().
8272          */
8273         ixgbe_disable_sec_tx_path_generic(hw);
8274
8275         /* Enable Ethernet CRC (required by MACsec offload) */
8276         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8277         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8278         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8279
8280         /* Enable the TX and RX crypto engines */
8281         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8282         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8283         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8284
8285         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8286         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8287         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8288
8289         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8290         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8291         ctrl |= 0x3;
8292         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8293
8294         /* Enable SA lookup */
8295         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8296         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8297         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8298                      IXGBE_LSECTXCTRL_AUTH;
8299         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8300         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8301         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8302         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8303
8304         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8305         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8306         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8307         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8308         if (rp)
8309                 ctrl |= IXGBE_LSECRXCTRL_RP;
8310         else
8311                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8312         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8313
8314         /* Start the data paths */
8315         ixgbe_enable_sec_rx_path(hw);
8316         /*
8317          * Workaround:
8318          * As no ixgbe_enable_sec_rx_path equivalent is
8319          * implemented for tx in the base code, and we are
8320          * not allowed to modify the base code in DPDK, so
8321          * just call the hand-written one directly for now.
8322          */
8323         ixgbe_enable_sec_tx_path_generic(hw);
8324
8325         return 0;
8326 }
8327
8328 int
8329 rte_pmd_ixgbe_macsec_disable(uint8_t port)
8330 {
8331         struct ixgbe_hw *hw;
8332         struct rte_eth_dev *dev;
8333         uint32_t ctrl;
8334
8335         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8336
8337         dev = &rte_eth_devices[port];
8338
8339         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8340                 return -ENOTSUP;
8341
8342         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8343
8344         /* Stop the data paths */
8345         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8346                 return -ENOTSUP;
8347         /*
8348          * Workaround:
8349          * As no ixgbe_disable_sec_rx_path equivalent is
8350          * implemented for tx in the base code, and we are
8351          * not allowed to modify the base code in DPDK, so
8352          * just call the hand-written one directly for now.
8353          * The hardware support has been checked by
8354          * ixgbe_disable_sec_rx_path().
8355          */
8356         ixgbe_disable_sec_tx_path_generic(hw);
8357
8358         /* Disable the TX and RX crypto engines */
8359         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8360         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8361         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8362
8363         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8364         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8365         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8366
8367         /* Disable SA lookup */
8368         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8369         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8370         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8371         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8372
8373         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8374         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8375         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8376         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8377
8378         /* Start the data paths */
8379         ixgbe_enable_sec_rx_path(hw);
8380         /*
8381          * Workaround:
8382          * As no ixgbe_enable_sec_rx_path equivalent is
8383          * implemented for tx in the base code, and we are
8384          * not allowed to modify the base code in DPDK, so
8385          * just call the hand-written one directly for now.
8386          */
8387         ixgbe_enable_sec_tx_path_generic(hw);
8388
8389         return 0;
8390 }
8391
8392 int
8393 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
8394 {
8395         struct ixgbe_hw *hw;
8396         struct rte_eth_dev *dev;
8397         uint32_t ctrl;
8398
8399         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8400
8401         dev = &rte_eth_devices[port];
8402
8403         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8404                 return -ENOTSUP;
8405
8406         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8407
8408         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8409         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
8410
8411         ctrl = mac[4] | (mac[5] << 8);
8412         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
8413
8414         return 0;
8415 }
8416
8417 int
8418 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
8419 {
8420         struct ixgbe_hw *hw;
8421         struct rte_eth_dev *dev;
8422         uint32_t ctrl;
8423
8424         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8425
8426         dev = &rte_eth_devices[port];
8427
8428         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8429                 return -ENOTSUP;
8430
8431         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8432
8433         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8434         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
8435
8436         pi = rte_cpu_to_be_16(pi);
8437         ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
8438         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
8439
8440         return 0;
8441 }
8442
8443 int
8444 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8445                                  uint32_t pn, uint8_t *key)
8446 {
8447         struct ixgbe_hw *hw;
8448         struct rte_eth_dev *dev;
8449         uint32_t ctrl, i;
8450
8451         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8452
8453         dev = &rte_eth_devices[port];
8454
8455         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8456                 return -ENOTSUP;
8457
8458         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8459
8460         if (idx != 0 && idx != 1)
8461                 return -EINVAL;
8462
8463         if (an >= 4)
8464                 return -EINVAL;
8465
8466         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8467
8468         /* Set the PN and key */
8469         pn = rte_cpu_to_be_32(pn);
8470         if (idx == 0) {
8471                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8472
8473                 for (i = 0; i < 4; i++) {
8474                         ctrl = (key[i * 4 + 0] <<  0) |
8475                                (key[i * 4 + 1] <<  8) |
8476                                (key[i * 4 + 2] << 16) |
8477                                (key[i * 4 + 3] << 24);
8478                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8479                 }
8480         } else {
8481                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8482
8483                 for (i = 0; i < 4; i++) {
8484                         ctrl = (key[i * 4 + 0] <<  0) |
8485                                (key[i * 4 + 1] <<  8) |
8486                                (key[i * 4 + 2] << 16) |
8487                                (key[i * 4 + 3] << 24);
8488                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8489                 }
8490         }
8491
8492         /* Set AN and select the SA */
8493         ctrl = (an << idx * 2) | (idx << 4);
8494         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8495
8496         return 0;
8497 }
8498
8499 int
8500 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8501                                  uint32_t pn, uint8_t *key)
8502 {
8503         struct ixgbe_hw *hw;
8504         struct rte_eth_dev *dev;
8505         uint32_t ctrl, i;
8506
8507         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8508
8509         dev = &rte_eth_devices[port];
8510
8511         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8512                 return -ENOTSUP;
8513
8514         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8515
8516         if (idx != 0 && idx != 1)
8517                 return -EINVAL;
8518
8519         if (an >= 4)
8520                 return -EINVAL;
8521
8522         /* Set the PN */
8523         pn = rte_cpu_to_be_32(pn);
8524         IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8525
8526         /* Set the key */
8527         for (i = 0; i < 4; i++) {
8528                 ctrl = (key[i * 4 + 0] <<  0) |
8529                        (key[i * 4 + 1] <<  8) |
8530                        (key[i * 4 + 2] << 16) |
8531                        (key[i * 4 + 3] << 24);
8532                 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8533         }
8534
8535         /* Set the AN and validate the SA */
8536         ctrl = an | (1 << 2);
8537         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8538
8539         return 0;
8540 }
8541
8542 /* restore n-tuple filter */
8543 static inline void
8544 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8545 {
8546         struct ixgbe_filter_info *filter_info =
8547                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8548         struct ixgbe_5tuple_filter *node;
8549
8550         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8551                 ixgbe_inject_5tuple_filter(dev, node);
8552         }
8553 }
8554
8555 /* restore ethernet type filter */
8556 static inline void
8557 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8558 {
8559         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8560         struct ixgbe_filter_info *filter_info =
8561                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8562         int i;
8563
8564         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8565                 if (filter_info->ethertype_mask & (1 << i)) {
8566                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8567                                         filter_info->ethertype_filters[i].etqf);
8568                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8569                                         filter_info->ethertype_filters[i].etqs);
8570                         IXGBE_WRITE_FLUSH(hw);
8571                 }
8572         }
8573 }
8574
8575 /* restore SYN filter */
8576 static inline void
8577 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8578 {
8579         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8580         struct ixgbe_filter_info *filter_info =
8581                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8582         uint32_t synqf;
8583
8584         synqf = filter_info->syn_info;
8585
8586         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8587                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8588                 IXGBE_WRITE_FLUSH(hw);
8589         }
8590 }
8591
8592 /* restore L2 tunnel filter */
8593 static inline void
8594 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8595 {
8596         struct ixgbe_l2_tn_info *l2_tn_info =
8597                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8598         struct ixgbe_l2_tn_filter *node;
8599         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8600
8601         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8602                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8603                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8604                 l2_tn_conf.pool           = node->pool;
8605                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8606         }
8607 }
8608
8609 static int
8610 ixgbe_filter_restore(struct rte_eth_dev *dev)
8611 {
8612         ixgbe_ntuple_filter_restore(dev);
8613         ixgbe_ethertype_filter_restore(dev);
8614         ixgbe_syn_filter_restore(dev);
8615         ixgbe_fdir_filter_restore(dev);
8616         ixgbe_l2_tn_filter_restore(dev);
8617
8618         return 0;
8619 }
8620
8621 static void
8622 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8623 {
8624         struct ixgbe_l2_tn_info *l2_tn_info =
8625                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8626         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8627
8628         if (l2_tn_info->e_tag_en)
8629                 (void)ixgbe_e_tag_enable(hw);
8630
8631         if (l2_tn_info->e_tag_fwd_en)
8632                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8633
8634         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8635 }
8636
8637 /* remove all the n-tuple filters */
8638 void
8639 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8640 {
8641         struct ixgbe_filter_info *filter_info =
8642                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8643         struct ixgbe_5tuple_filter *p_5tuple;
8644
8645         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8646                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8647 }
8648
8649 /* remove all the ether type filters */
8650 void
8651 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8652 {
8653         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8654         struct ixgbe_filter_info *filter_info =
8655                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8656         int i;
8657
8658         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8659                 if (filter_info->ethertype_mask & (1 << i) &&
8660                     !filter_info->ethertype_filters[i].conf) {
8661                         (void)ixgbe_ethertype_filter_remove(filter_info,
8662                                                             (uint8_t)i);
8663                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8664                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8665                         IXGBE_WRITE_FLUSH(hw);
8666                 }
8667         }
8668 }
8669
8670 /* remove the SYN filter */
8671 void
8672 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8673 {
8674         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8675         struct ixgbe_filter_info *filter_info =
8676                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8677
8678         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8679                 filter_info->syn_info = 0;
8680
8681                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8682                 IXGBE_WRITE_FLUSH(hw);
8683         }
8684 }
8685
8686 /* remove all the L2 tunnel filters */
8687 int
8688 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8689 {
8690         struct ixgbe_l2_tn_info *l2_tn_info =
8691                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8692         struct ixgbe_l2_tn_filter *l2_tn_filter;
8693         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8694         int ret = 0;
8695
8696         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8697                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8698                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8699                 l2_tn_conf.pool           = l2_tn_filter->pool;
8700                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8701                 if (ret < 0)
8702                         return ret;
8703         }
8704
8705         return 0;
8706 }
8707
8708 int
8709 rte_pmd_ixgbe_set_tc_bw_alloc(uint8_t port,
8710                               uint8_t tc_num,
8711                               uint8_t *bw_weight)
8712 {
8713         struct rte_eth_dev *dev;
8714         struct ixgbe_dcb_config *dcb_config;
8715         struct ixgbe_dcb_tc_config *tc;
8716         struct rte_eth_conf *eth_conf;
8717         struct ixgbe_bw_conf *bw_conf;
8718         uint8_t i;
8719         uint8_t nb_tcs;
8720         uint16_t sum;
8721
8722         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8723
8724         dev = &rte_eth_devices[port];
8725
8726         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8727                 return -ENOTSUP;
8728
8729         if (tc_num > IXGBE_DCB_MAX_TRAFFIC_CLASS) {
8730                 PMD_DRV_LOG(ERR, "TCs should be no more than %d.",
8731                             IXGBE_DCB_MAX_TRAFFIC_CLASS);
8732                 return -EINVAL;
8733         }
8734
8735         dcb_config = IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
8736         bw_conf = IXGBE_DEV_PRIVATE_TO_BW_CONF(dev->data->dev_private);
8737         eth_conf = &dev->data->dev_conf;
8738
8739         if (eth_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
8740                 nb_tcs = eth_conf->tx_adv_conf.dcb_tx_conf.nb_tcs;
8741         } else if (eth_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
8742                 if (eth_conf->tx_adv_conf.vmdq_dcb_tx_conf.nb_queue_pools ==
8743                     ETH_32_POOLS)
8744                         nb_tcs = ETH_4_TCS;
8745                 else
8746                         nb_tcs = ETH_8_TCS;
8747         } else {
8748                 nb_tcs = 1;
8749         }
8750
8751         if (nb_tcs != tc_num) {
8752                 PMD_DRV_LOG(ERR,
8753                             "Weight should be set for all %d enabled TCs.",
8754                             nb_tcs);
8755                 return -EINVAL;
8756         }
8757
8758         sum = 0;
8759         for (i = 0; i < nb_tcs; i++)
8760                 sum += bw_weight[i];
8761         if (sum != 100) {
8762                 PMD_DRV_LOG(ERR,
8763                             "The summary of the TC weight should be 100.");
8764                 return -EINVAL;
8765         }
8766
8767         for (i = 0; i < nb_tcs; i++) {
8768                 tc = &dcb_config->tc_config[i];
8769                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = bw_weight[i];
8770         }
8771         for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
8772                 tc = &dcb_config->tc_config[i];
8773                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
8774         }
8775
8776         bw_conf->tc_num = nb_tcs;
8777
8778         return 0;
8779 }
8780
8781 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
8782 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8783 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8784 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
8785 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8786 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");