4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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14 * notice, this list of conditions and the following disclaimer in
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
64 #include "ixgbe_logs.h"
65 #include "base/ixgbe_api.h"
66 #include "base/ixgbe_vf.h"
67 #include "base/ixgbe_common.h"
68 #include "ixgbe_ethdev.h"
69 #include "ixgbe_bypass.h"
70 #include "ixgbe_rxtx.h"
71 #include "base/ixgbe_type.h"
72 #include "base/ixgbe_phy.h"
73 #include "ixgbe_regs.h"
76 * High threshold controlling when to start sending XOFF frames. Must be at
77 * least 8 bytes less than receive packet buffer size. This value is in units
80 #define IXGBE_FC_HI 0x80
83 * Low threshold controlling when to start sending XON frames. This value is
84 * in units of 1024 bytes.
86 #define IXGBE_FC_LO 0x40
88 /* Default minimum inter-interrupt interval for EITR configuration */
89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
91 /* Timer value included in XOFF frames. */
92 #define IXGBE_FC_PAUSE 0x680
94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
95 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
96 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
98 #define IXGBE_MMW_SIZE_DEFAULT 0x4
99 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
100 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
103 * Default values for RX/TX configuration
105 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
106 #define IXGBE_DEFAULT_RX_PTHRESH 8
107 #define IXGBE_DEFAULT_RX_HTHRESH 8
108 #define IXGBE_DEFAULT_RX_WTHRESH 0
110 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
111 #define IXGBE_DEFAULT_TX_PTHRESH 32
112 #define IXGBE_DEFAULT_TX_HTHRESH 0
113 #define IXGBE_DEFAULT_TX_WTHRESH 0
114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
116 /* Bit shift and mask */
117 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
118 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
119 #define IXGBE_8_BIT_WIDTH CHAR_BIT
120 #define IXGBE_8_BIT_MASK UINT8_MAX
122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
126 #define IXGBE_HKEY_MAX_INDEX 10
128 /* Additional timesync values. */
129 #define IXGBE_TIMINCA_16NS_SHIFT 24
130 #define IXGBE_TIMINCA_INCVALUE 16000000
131 #define IXGBE_TIMINCA_INIT ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
132 | IXGBE_TIMINCA_INCVALUE)
134 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
135 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
136 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
137 static int ixgbe_dev_start(struct rte_eth_dev *dev);
138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
139 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
140 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
142 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
143 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
144 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
145 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
146 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
147 int wait_to_complete);
148 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
149 struct rte_eth_stats *stats);
150 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
151 struct rte_eth_xstats *xstats, unsigned n);
152 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
153 struct rte_eth_xstats *xstats, unsigned n);
154 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
155 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
156 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
160 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
161 struct rte_eth_dev_info *dev_info);
162 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
163 struct rte_eth_dev_info *dev_info);
164 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
166 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
167 uint16_t vlan_id, int on);
168 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
169 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
170 uint16_t queue, bool on);
171 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
173 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
174 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
175 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
176 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
177 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
179 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
180 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
181 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
182 struct rte_eth_fc_conf *fc_conf);
183 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
184 struct rte_eth_fc_conf *fc_conf);
185 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
186 struct rte_eth_pfc_conf *pfc_conf);
187 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
188 struct rte_eth_rss_reta_entry64 *reta_conf,
190 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
191 struct rte_eth_rss_reta_entry64 *reta_conf,
193 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
194 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
195 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
196 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
197 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
198 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
200 static void ixgbe_dev_interrupt_delayed_handler(void *param);
201 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
202 uint32_t index, uint32_t pool);
203 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
204 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
205 struct ether_addr *mac_addr);
206 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
208 /* For Virtual Function support */
209 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
210 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
211 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
212 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
213 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
214 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
215 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
216 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
217 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
218 struct rte_eth_stats *stats);
219 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
220 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
221 uint16_t vlan_id, int on);
222 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
223 uint16_t queue, int on);
224 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
225 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
226 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
228 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
230 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
231 uint8_t queue, uint8_t msix_vector);
232 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
234 /* For Eth VMDQ APIs support */
235 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
236 ether_addr* mac_addr,uint8_t on);
237 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
238 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
239 uint16_t rx_mask, uint8_t on);
240 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
241 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
242 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
243 uint64_t pool_mask,uint8_t vlan_on);
244 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
245 struct rte_eth_mirror_conf *mirror_conf,
246 uint8_t rule_id, uint8_t on);
247 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
249 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
251 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
253 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
254 uint8_t queue, uint8_t msix_vector);
255 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
257 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
258 uint16_t queue_idx, uint16_t tx_rate);
259 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
260 uint16_t tx_rate, uint64_t q_msk);
262 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
263 struct ether_addr *mac_addr,
264 uint32_t index, uint32_t pool);
265 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
266 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
267 struct ether_addr *mac_addr);
268 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
269 struct rte_eth_syn_filter *filter,
271 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
272 struct rte_eth_syn_filter *filter);
273 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
274 enum rte_filter_op filter_op,
276 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
277 struct ixgbe_5tuple_filter *filter);
278 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
279 struct ixgbe_5tuple_filter *filter);
280 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
281 struct rte_eth_ntuple_filter *filter,
283 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
284 enum rte_filter_op filter_op,
286 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
287 struct rte_eth_ntuple_filter *filter);
288 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
289 struct rte_eth_ethertype_filter *filter,
291 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
292 enum rte_filter_op filter_op,
294 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
295 struct rte_eth_ethertype_filter *filter);
296 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
297 enum rte_filter_type filter_type,
298 enum rte_filter_op filter_op,
300 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
302 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
303 struct ether_addr *mc_addr_set,
304 uint32_t nb_mc_addr);
305 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
306 struct rte_eth_dcb_info *dcb_info);
308 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
309 static int ixgbe_get_regs(struct rte_eth_dev *dev,
310 struct rte_dev_reg_info *regs);
311 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
312 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
313 struct rte_dev_eeprom_info *eeprom);
314 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
315 struct rte_dev_eeprom_info *eeprom);
317 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
318 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
319 struct rte_dev_reg_info *regs);
321 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
322 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
323 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
324 struct timespec *timestamp,
326 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
327 struct timespec *timestamp);
330 * Define VF Stats MACRO for Non "cleared on read" register
332 #define UPDATE_VF_STAT(reg, last, cur) \
334 uint32_t latest = IXGBE_READ_REG(hw, reg); \
335 cur += (latest - last) & UINT_MAX; \
339 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
341 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
342 u64 new_msb = IXGBE_READ_REG(hw, msb); \
343 u64 latest = ((new_msb << 32) | new_lsb); \
344 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
348 #define IXGBE_SET_HWSTRIP(h, q) do{\
349 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
350 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
351 (h)->bitmap[idx] |= 1 << bit;\
354 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
355 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
356 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
357 (h)->bitmap[idx] &= ~(1 << bit);\
360 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
361 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
362 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
363 (r) = (h)->bitmap[idx] >> bit & 1;\
367 * The set of PCI devices this driver supports
369 static const struct rte_pci_id pci_id_ixgbe_map[] = {
371 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
372 #include "rte_pci_dev_ids.h"
374 { .vendor_id = 0, /* sentinel */ },
379 * The set of PCI devices this driver supports (for 82599 VF)
381 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
383 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
384 #include "rte_pci_dev_ids.h"
385 { .vendor_id = 0, /* sentinel */ },
389 static const struct rte_eth_desc_lim rx_desc_lim = {
390 .nb_max = IXGBE_MAX_RING_DESC,
391 .nb_min = IXGBE_MIN_RING_DESC,
392 .nb_align = IXGBE_RXD_ALIGN,
395 static const struct rte_eth_desc_lim tx_desc_lim = {
396 .nb_max = IXGBE_MAX_RING_DESC,
397 .nb_min = IXGBE_MIN_RING_DESC,
398 .nb_align = IXGBE_TXD_ALIGN,
401 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
402 .dev_configure = ixgbe_dev_configure,
403 .dev_start = ixgbe_dev_start,
404 .dev_stop = ixgbe_dev_stop,
405 .dev_set_link_up = ixgbe_dev_set_link_up,
406 .dev_set_link_down = ixgbe_dev_set_link_down,
407 .dev_close = ixgbe_dev_close,
408 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
409 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
410 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
411 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
412 .link_update = ixgbe_dev_link_update,
413 .stats_get = ixgbe_dev_stats_get,
414 .xstats_get = ixgbe_dev_xstats_get,
415 .stats_reset = ixgbe_dev_stats_reset,
416 .xstats_reset = ixgbe_dev_xstats_reset,
417 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
418 .dev_infos_get = ixgbe_dev_info_get,
419 .mtu_set = ixgbe_dev_mtu_set,
420 .vlan_filter_set = ixgbe_vlan_filter_set,
421 .vlan_tpid_set = ixgbe_vlan_tpid_set,
422 .vlan_offload_set = ixgbe_vlan_offload_set,
423 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
424 .rx_queue_start = ixgbe_dev_rx_queue_start,
425 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
426 .tx_queue_start = ixgbe_dev_tx_queue_start,
427 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
428 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
429 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
430 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
431 .rx_queue_release = ixgbe_dev_rx_queue_release,
432 .rx_queue_count = ixgbe_dev_rx_queue_count,
433 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
434 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
435 .tx_queue_release = ixgbe_dev_tx_queue_release,
436 .dev_led_on = ixgbe_dev_led_on,
437 .dev_led_off = ixgbe_dev_led_off,
438 .flow_ctrl_get = ixgbe_flow_ctrl_get,
439 .flow_ctrl_set = ixgbe_flow_ctrl_set,
440 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
441 .mac_addr_add = ixgbe_add_rar,
442 .mac_addr_remove = ixgbe_remove_rar,
443 .mac_addr_set = ixgbe_set_default_mac_addr,
444 .uc_hash_table_set = ixgbe_uc_hash_table_set,
445 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
446 .mirror_rule_set = ixgbe_mirror_rule_set,
447 .mirror_rule_reset = ixgbe_mirror_rule_reset,
448 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
449 .set_vf_rx = ixgbe_set_pool_rx,
450 .set_vf_tx = ixgbe_set_pool_tx,
451 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
452 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
453 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
454 .reta_update = ixgbe_dev_rss_reta_update,
455 .reta_query = ixgbe_dev_rss_reta_query,
456 #ifdef RTE_NIC_BYPASS
457 .bypass_init = ixgbe_bypass_init,
458 .bypass_state_set = ixgbe_bypass_state_store,
459 .bypass_state_show = ixgbe_bypass_state_show,
460 .bypass_event_set = ixgbe_bypass_event_store,
461 .bypass_event_show = ixgbe_bypass_event_show,
462 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
463 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
464 .bypass_ver_show = ixgbe_bypass_ver_show,
465 .bypass_wd_reset = ixgbe_bypass_wd_reset,
466 #endif /* RTE_NIC_BYPASS */
467 .rss_hash_update = ixgbe_dev_rss_hash_update,
468 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
469 .filter_ctrl = ixgbe_dev_filter_ctrl,
470 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
471 .rxq_info_get = ixgbe_rxq_info_get,
472 .txq_info_get = ixgbe_txq_info_get,
473 .timesync_enable = ixgbe_timesync_enable,
474 .timesync_disable = ixgbe_timesync_disable,
475 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
476 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
477 .get_reg_length = ixgbe_get_reg_length,
478 .get_reg = ixgbe_get_regs,
479 .get_eeprom_length = ixgbe_get_eeprom_length,
480 .get_eeprom = ixgbe_get_eeprom,
481 .set_eeprom = ixgbe_set_eeprom,
482 .get_dcb_info = ixgbe_dev_get_dcb_info,
486 * dev_ops for virtual function, bare necessities for basic vf
487 * operation have been implemented
489 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
490 .dev_configure = ixgbevf_dev_configure,
491 .dev_start = ixgbevf_dev_start,
492 .dev_stop = ixgbevf_dev_stop,
493 .link_update = ixgbe_dev_link_update,
494 .stats_get = ixgbevf_dev_stats_get,
495 .xstats_get = ixgbevf_dev_xstats_get,
496 .stats_reset = ixgbevf_dev_stats_reset,
497 .xstats_reset = ixgbevf_dev_stats_reset,
498 .dev_close = ixgbevf_dev_close,
499 .dev_infos_get = ixgbevf_dev_info_get,
500 .mtu_set = ixgbevf_dev_set_mtu,
501 .vlan_filter_set = ixgbevf_vlan_filter_set,
502 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
503 .vlan_offload_set = ixgbevf_vlan_offload_set,
504 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
505 .rx_queue_release = ixgbe_dev_rx_queue_release,
506 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
507 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
508 .tx_queue_release = ixgbe_dev_tx_queue_release,
509 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
510 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
511 .mac_addr_add = ixgbevf_add_mac_addr,
512 .mac_addr_remove = ixgbevf_remove_mac_addr,
513 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
514 .rxq_info_get = ixgbe_rxq_info_get,
515 .txq_info_get = ixgbe_txq_info_get,
516 .mac_addr_set = ixgbevf_set_default_mac_addr,
517 .get_reg_length = ixgbevf_get_reg_length,
518 .get_reg = ixgbevf_get_regs,
519 .reta_update = ixgbe_dev_rss_reta_update,
520 .reta_query = ixgbe_dev_rss_reta_query,
521 .rss_hash_update = ixgbe_dev_rss_hash_update,
522 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
525 /* store statistics names and its offset in stats structure */
526 struct rte_ixgbe_xstats_name_off {
527 char name[RTE_ETH_XSTATS_NAME_SIZE];
531 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
532 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
533 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
534 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
535 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
536 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
537 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
538 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
539 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
540 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
541 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
542 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
543 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
544 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
545 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
546 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
548 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
550 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
551 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
552 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
553 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
554 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
555 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
556 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
557 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
558 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
559 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
560 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
561 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
562 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
563 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
564 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
565 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
566 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
568 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
570 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
571 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
572 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
573 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
575 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
577 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
579 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
581 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
583 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
585 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
588 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
589 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
590 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
592 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
593 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
594 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
595 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
596 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
598 {"rx_fcoe_no_direct_data_placement_ext_buff",
599 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
601 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
603 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
605 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
607 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
609 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
612 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
613 sizeof(rte_ixgbe_stats_strings[0]))
615 /* Per-queue statistics */
616 #define IXBGE_NB_8_PER_Q_STATS (8 * 7)
617 #define IXBGE_NB_16_PER_Q_STATS (16 * 5)
618 #define IXGBE_NB_Q_STATS (IXBGE_NB_8_PER_Q_STATS + IXBGE_NB_16_PER_Q_STATS)
620 #define IXGBE_NB_XSTATS (IXGBE_NB_HW_STATS + IXGBE_NB_Q_STATS)
622 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
623 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
626 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
627 sizeof(rte_ixgbevf_stats_strings[0]))
630 * Atomically reads the link status information from global
631 * structure rte_eth_dev.
634 * - Pointer to the structure rte_eth_dev to read from.
635 * - Pointer to the buffer to be saved with the link status.
638 * - On success, zero.
639 * - On failure, negative value.
642 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
643 struct rte_eth_link *link)
645 struct rte_eth_link *dst = link;
646 struct rte_eth_link *src = &(dev->data->dev_link);
648 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
649 *(uint64_t *)src) == 0)
656 * Atomically writes the link status information into global
657 * structure rte_eth_dev.
660 * - Pointer to the structure rte_eth_dev to read from.
661 * - Pointer to the buffer to be saved with the link status.
664 * - On success, zero.
665 * - On failure, negative value.
668 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
669 struct rte_eth_link *link)
671 struct rte_eth_link *dst = &(dev->data->dev_link);
672 struct rte_eth_link *src = link;
674 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
675 *(uint64_t *)src) == 0)
682 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
685 ixgbe_is_sfp(struct ixgbe_hw *hw)
687 switch (hw->phy.type) {
688 case ixgbe_phy_sfp_avago:
689 case ixgbe_phy_sfp_ftl:
690 case ixgbe_phy_sfp_intel:
691 case ixgbe_phy_sfp_unknown:
692 case ixgbe_phy_sfp_passive_tyco:
693 case ixgbe_phy_sfp_passive_unknown:
700 static inline int32_t
701 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
706 status = ixgbe_reset_hw(hw);
708 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
709 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
710 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
711 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
712 IXGBE_WRITE_FLUSH(hw);
718 ixgbe_enable_intr(struct rte_eth_dev *dev)
720 struct ixgbe_interrupt *intr =
721 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
722 struct ixgbe_hw *hw =
723 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
725 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
726 IXGBE_WRITE_FLUSH(hw);
730 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
733 ixgbe_disable_intr(struct ixgbe_hw *hw)
735 PMD_INIT_FUNC_TRACE();
737 if (hw->mac.type == ixgbe_mac_82598EB) {
738 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
740 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
741 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
742 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
744 IXGBE_WRITE_FLUSH(hw);
748 * This function resets queue statistics mapping registers.
749 * From Niantic datasheet, Initialization of Statistics section:
750 * "...if software requires the queue counters, the RQSMR and TQSM registers
751 * must be re-programmed following a device reset.
754 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
758 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
759 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
760 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
766 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
771 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
772 #define NB_QMAP_FIELDS_PER_QSM_REG 4
773 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
775 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
776 struct ixgbe_stat_mapping_registers *stat_mappings =
777 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
778 uint32_t qsmr_mask = 0;
779 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
783 if ((hw->mac.type != ixgbe_mac_82599EB) &&
784 (hw->mac.type != ixgbe_mac_X540) &&
785 (hw->mac.type != ixgbe_mac_X550) &&
786 (hw->mac.type != ixgbe_mac_X550EM_x))
789 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
790 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
793 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
794 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
795 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
798 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
800 /* Now clear any previous stat_idx set */
801 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
803 stat_mappings->tqsm[n] &= ~clearing_mask;
805 stat_mappings->rqsmr[n] &= ~clearing_mask;
807 q_map = (uint32_t)stat_idx;
808 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
809 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
811 stat_mappings->tqsm[n] |= qsmr_mask;
813 stat_mappings->rqsmr[n] |= qsmr_mask;
815 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
816 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
818 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
819 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
821 /* Now write the mapping in the appropriate register */
823 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
824 stat_mappings->rqsmr[n], n);
825 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
828 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
829 stat_mappings->tqsm[n], n);
830 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
836 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
838 struct ixgbe_stat_mapping_registers *stat_mappings =
839 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
840 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
843 /* write whatever was in stat mapping table to the NIC */
844 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
846 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
849 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
854 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
857 struct ixgbe_dcb_tc_config *tc;
858 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
860 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
861 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
862 for (i = 0; i < dcb_max_tc; i++) {
863 tc = &dcb_config->tc_config[i];
864 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
865 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
866 (uint8_t)(100/dcb_max_tc + (i & 1));
867 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
868 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
869 (uint8_t)(100/dcb_max_tc + (i & 1));
870 tc->pfc = ixgbe_dcb_pfc_disabled;
873 /* Initialize default user to priority mapping, UPx->TC0 */
874 tc = &dcb_config->tc_config[0];
875 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
876 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
877 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
878 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
879 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
881 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
882 dcb_config->pfc_mode_enable = false;
883 dcb_config->vt_mode = true;
884 dcb_config->round_robin_enable = false;
885 /* support all DCB capabilities in 82599 */
886 dcb_config->support.capabilities = 0xFF;
888 /*we only support 4 Tcs for X540, X550 */
889 if (hw->mac.type == ixgbe_mac_X540 ||
890 hw->mac.type == ixgbe_mac_X550 ||
891 hw->mac.type == ixgbe_mac_X550EM_x) {
892 dcb_config->num_tcs.pg_tcs = 4;
893 dcb_config->num_tcs.pfc_tcs = 4;
898 * Ensure that all locks are released before first NVM or PHY access
901 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
906 * Phy lock should not fail in this early stage. If this is the case,
907 * it is due to an improper exit of the application.
908 * So force the release of the faulty lock. Release of common lock
909 * is done automatically by swfw_sync function.
911 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
912 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
913 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
915 ixgbe_release_swfw_semaphore(hw, mask);
918 * These ones are more tricky since they are common to all ports; but
919 * swfw_sync retries last long enough (1s) to be almost sure that if
920 * lock can not be taken it is due to an improper lock of the
923 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
924 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
925 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
927 ixgbe_release_swfw_semaphore(hw, mask);
931 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
932 * It returns 0 on success.
935 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
937 struct rte_pci_device *pci_dev;
938 struct ixgbe_hw *hw =
939 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
940 struct ixgbe_vfta * shadow_vfta =
941 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
942 struct ixgbe_hwstrip *hwstrip =
943 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
944 struct ixgbe_dcb_config *dcb_config =
945 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
946 struct ixgbe_filter_info *filter_info =
947 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
952 PMD_INIT_FUNC_TRACE();
954 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
955 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
956 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
959 * For secondary processes, we don't initialise any further as primary
960 * has already done this work. Only check we don't need a different
961 * RX and TX function.
963 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
964 struct ixgbe_tx_queue *txq;
965 /* TX queue function in primary, set by last queue initialized
966 * Tx queue may not initialized by primary process */
967 if (eth_dev->data->tx_queues) {
968 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
969 ixgbe_set_tx_function(eth_dev, txq);
971 /* Use default TX function if we get here */
972 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
973 "Using default TX function.");
976 ixgbe_set_rx_function(eth_dev);
980 pci_dev = eth_dev->pci_dev;
982 rte_eth_copy_pci_info(eth_dev, pci_dev);
984 /* Vendor and Device ID need to be set before init of shared code */
985 hw->device_id = pci_dev->id.device_id;
986 hw->vendor_id = pci_dev->id.vendor_id;
987 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
988 hw->allow_unsupported_sfp = 1;
990 /* Initialize the shared code (base driver) */
991 #ifdef RTE_NIC_BYPASS
992 diag = ixgbe_bypass_init_shared_code(hw);
994 diag = ixgbe_init_shared_code(hw);
995 #endif /* RTE_NIC_BYPASS */
997 if (diag != IXGBE_SUCCESS) {
998 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1002 /* pick up the PCI bus settings for reporting later */
1003 ixgbe_get_bus_info(hw);
1005 /* Unlock any pending hardware semaphore */
1006 ixgbe_swfw_lock_reset(hw);
1008 /* Initialize DCB configuration*/
1009 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1010 ixgbe_dcb_init(hw,dcb_config);
1011 /* Get Hardware Flow Control setting */
1012 hw->fc.requested_mode = ixgbe_fc_full;
1013 hw->fc.current_mode = ixgbe_fc_full;
1014 hw->fc.pause_time = IXGBE_FC_PAUSE;
1015 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1016 hw->fc.low_water[i] = IXGBE_FC_LO;
1017 hw->fc.high_water[i] = IXGBE_FC_HI;
1019 hw->fc.send_xon = 1;
1021 /* Make sure we have a good EEPROM before we read from it */
1022 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1023 if (diag != IXGBE_SUCCESS) {
1024 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1028 #ifdef RTE_NIC_BYPASS
1029 diag = ixgbe_bypass_init_hw(hw);
1031 diag = ixgbe_init_hw(hw);
1032 #endif /* RTE_NIC_BYPASS */
1035 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1036 * is called too soon after the kernel driver unbinding/binding occurs.
1037 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1038 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1039 * also called. See ixgbe_identify_phy_82599(). The reason for the
1040 * failure is not known, and only occuts when virtualisation features
1041 * are disabled in the bios. A delay of 100ms was found to be enough by
1042 * trial-and-error, and is doubled to be safe.
1044 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1046 diag = ixgbe_init_hw(hw);
1049 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1050 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1051 "LOM. Please be aware there may be issues associated "
1052 "with your hardware.");
1053 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1054 "please contact your Intel or hardware representative "
1055 "who provided you with this hardware.");
1056 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1057 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1059 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1063 /* Reset the hw statistics */
1064 ixgbe_dev_stats_reset(eth_dev);
1066 /* disable interrupt */
1067 ixgbe_disable_intr(hw);
1069 /* reset mappings for queue statistics hw counters*/
1070 ixgbe_reset_qstat_mappings(hw);
1072 /* Allocate memory for storing MAC addresses */
1073 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1074 hw->mac.num_rar_entries, 0);
1075 if (eth_dev->data->mac_addrs == NULL) {
1077 "Failed to allocate %u bytes needed to store "
1079 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1082 /* Copy the permanent MAC address */
1083 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1084 ð_dev->data->mac_addrs[0]);
1086 /* Allocate memory for storing hash filter MAC addresses */
1087 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1088 IXGBE_VMDQ_NUM_UC_MAC, 0);
1089 if (eth_dev->data->hash_mac_addrs == NULL) {
1091 "Failed to allocate %d bytes needed to store MAC addresses",
1092 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1096 /* initialize the vfta */
1097 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1099 /* initialize the hw strip bitmap*/
1100 memset(hwstrip, 0, sizeof(*hwstrip));
1102 /* initialize PF if max_vfs not zero */
1103 ixgbe_pf_host_init(eth_dev);
1105 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1106 /* let hardware know driver is loaded */
1107 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1108 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1109 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1110 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1111 IXGBE_WRITE_FLUSH(hw);
1113 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1114 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1115 (int) hw->mac.type, (int) hw->phy.type,
1116 (int) hw->phy.sfp_type);
1118 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1119 (int) hw->mac.type, (int) hw->phy.type);
1121 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1122 eth_dev->data->port_id, pci_dev->id.vendor_id,
1123 pci_dev->id.device_id);
1125 rte_intr_callback_register(&pci_dev->intr_handle,
1126 ixgbe_dev_interrupt_handler,
1129 /* enable uio/vfio intr/eventfd mapping */
1130 rte_intr_enable(&pci_dev->intr_handle);
1132 /* enable support intr */
1133 ixgbe_enable_intr(eth_dev);
1135 /* initialize 5tuple filter list */
1136 TAILQ_INIT(&filter_info->fivetuple_list);
1137 memset(filter_info->fivetuple_mask, 0,
1138 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1144 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1146 struct rte_pci_device *pci_dev;
1147 struct ixgbe_hw *hw;
1149 PMD_INIT_FUNC_TRACE();
1151 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1154 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1155 pci_dev = eth_dev->pci_dev;
1157 if (hw->adapter_stopped == 0)
1158 ixgbe_dev_close(eth_dev);
1160 eth_dev->dev_ops = NULL;
1161 eth_dev->rx_pkt_burst = NULL;
1162 eth_dev->tx_pkt_burst = NULL;
1164 /* Unlock any pending hardware semaphore */
1165 ixgbe_swfw_lock_reset(hw);
1167 /* disable uio intr before callback unregister */
1168 rte_intr_disable(&(pci_dev->intr_handle));
1169 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1170 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1172 /* uninitialize PF if max_vfs not zero */
1173 ixgbe_pf_host_uninit(eth_dev);
1175 rte_free(eth_dev->data->mac_addrs);
1176 eth_dev->data->mac_addrs = NULL;
1178 rte_free(eth_dev->data->hash_mac_addrs);
1179 eth_dev->data->hash_mac_addrs = NULL;
1185 * Negotiate mailbox API version with the PF.
1186 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1187 * Then we try to negotiate starting with the most recent one.
1188 * If all negotiation attempts fail, then we will proceed with
1189 * the default one (ixgbe_mbox_api_10).
1192 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1196 /* start with highest supported, proceed down */
1197 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1203 i != RTE_DIM(sup_ver) &&
1204 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1210 generate_random_mac_addr(struct ether_addr *mac_addr)
1214 /* Set Organizationally Unique Identifier (OUI) prefix. */
1215 mac_addr->addr_bytes[0] = 0x00;
1216 mac_addr->addr_bytes[1] = 0x09;
1217 mac_addr->addr_bytes[2] = 0xC0;
1218 /* Force indication of locally assigned MAC address. */
1219 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1220 /* Generate the last 3 bytes of the MAC address with a random number. */
1221 random = rte_rand();
1222 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1226 * Virtual Function device init
1229 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1233 struct rte_pci_device *pci_dev;
1234 struct ixgbe_hw *hw =
1235 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1236 struct ixgbe_vfta * shadow_vfta =
1237 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1238 struct ixgbe_hwstrip *hwstrip =
1239 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1240 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1242 PMD_INIT_FUNC_TRACE();
1244 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1245 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1246 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1248 /* for secondary processes, we don't initialise any further as primary
1249 * has already done this work. Only check we don't need a different
1251 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1252 if (eth_dev->data->scattered_rx)
1253 eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1257 pci_dev = eth_dev->pci_dev;
1259 rte_eth_copy_pci_info(eth_dev, pci_dev);
1261 hw->device_id = pci_dev->id.device_id;
1262 hw->vendor_id = pci_dev->id.vendor_id;
1263 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1265 /* initialize the vfta */
1266 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1268 /* initialize the hw strip bitmap*/
1269 memset(hwstrip, 0, sizeof(*hwstrip));
1271 /* Initialize the shared code (base driver) */
1272 diag = ixgbe_init_shared_code(hw);
1273 if (diag != IXGBE_SUCCESS) {
1274 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1278 /* init_mailbox_params */
1279 hw->mbx.ops.init_params(hw);
1281 /* Reset the hw statistics */
1282 ixgbevf_dev_stats_reset(eth_dev);
1284 /* Disable the interrupts for VF */
1285 ixgbevf_intr_disable(hw);
1287 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1288 diag = hw->mac.ops.reset_hw(hw);
1291 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1292 * the underlying PF driver has not assigned a MAC address to the VF.
1293 * In this case, assign a random MAC address.
1295 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1296 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1300 /* negotiate mailbox API version to use with the PF. */
1301 ixgbevf_negotiate_api(hw);
1303 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1304 ixgbevf_get_queues(hw, &tcs, &tc);
1306 /* Allocate memory for storing MAC addresses */
1307 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1308 hw->mac.num_rar_entries, 0);
1309 if (eth_dev->data->mac_addrs == NULL) {
1311 "Failed to allocate %u bytes needed to store "
1313 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1317 /* Generate a random MAC address, if none was assigned by PF. */
1318 if (is_zero_ether_addr(perm_addr)) {
1319 generate_random_mac_addr(perm_addr);
1320 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1322 rte_free(eth_dev->data->mac_addrs);
1323 eth_dev->data->mac_addrs = NULL;
1326 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1327 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1328 "%02x:%02x:%02x:%02x:%02x:%02x",
1329 perm_addr->addr_bytes[0],
1330 perm_addr->addr_bytes[1],
1331 perm_addr->addr_bytes[2],
1332 perm_addr->addr_bytes[3],
1333 perm_addr->addr_bytes[4],
1334 perm_addr->addr_bytes[5]);
1337 /* Copy the permanent MAC address */
1338 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1340 /* reset the hardware with the new settings */
1341 diag = hw->mac.ops.start_hw(hw);
1347 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1351 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1352 eth_dev->data->port_id, pci_dev->id.vendor_id,
1353 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1358 /* Virtual Function device uninit */
1361 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1363 struct ixgbe_hw *hw;
1366 PMD_INIT_FUNC_TRACE();
1368 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1371 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1373 if (hw->adapter_stopped == 0)
1374 ixgbevf_dev_close(eth_dev);
1376 eth_dev->dev_ops = NULL;
1377 eth_dev->rx_pkt_burst = NULL;
1378 eth_dev->tx_pkt_burst = NULL;
1380 /* Disable the interrupts for VF */
1381 ixgbevf_intr_disable(hw);
1383 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1384 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1385 eth_dev->data->rx_queues[i] = NULL;
1387 eth_dev->data->nb_rx_queues = 0;
1389 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1390 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1391 eth_dev->data->tx_queues[i] = NULL;
1393 eth_dev->data->nb_tx_queues = 0;
1395 rte_free(eth_dev->data->mac_addrs);
1396 eth_dev->data->mac_addrs = NULL;
1401 static struct eth_driver rte_ixgbe_pmd = {
1403 .name = "rte_ixgbe_pmd",
1404 .id_table = pci_id_ixgbe_map,
1405 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1406 RTE_PCI_DRV_DETACHABLE,
1408 .eth_dev_init = eth_ixgbe_dev_init,
1409 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1410 .dev_private_size = sizeof(struct ixgbe_adapter),
1414 * virtual function driver struct
1416 static struct eth_driver rte_ixgbevf_pmd = {
1418 .name = "rte_ixgbevf_pmd",
1419 .id_table = pci_id_ixgbevf_map,
1420 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1422 .eth_dev_init = eth_ixgbevf_dev_init,
1423 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1424 .dev_private_size = sizeof(struct ixgbe_adapter),
1428 * Driver initialization routine.
1429 * Invoked once at EAL init time.
1430 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1433 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1435 PMD_INIT_FUNC_TRACE();
1437 rte_eth_driver_register(&rte_ixgbe_pmd);
1442 * VF Driver initialization routine.
1443 * Invoked one at EAL init time.
1444 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1447 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1449 PMD_INIT_FUNC_TRACE();
1451 rte_eth_driver_register(&rte_ixgbevf_pmd);
1456 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1458 struct ixgbe_hw *hw =
1459 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1460 struct ixgbe_vfta * shadow_vfta =
1461 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1466 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1467 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1468 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1473 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1475 /* update local VFTA copy */
1476 shadow_vfta->vfta[vid_idx] = vfta;
1482 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1485 ixgbe_vlan_hw_strip_enable(dev, queue);
1487 ixgbe_vlan_hw_strip_disable(dev, queue);
1491 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1493 struct ixgbe_hw *hw =
1494 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1496 /* Only the high 16-bits is valid */
1497 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1501 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1503 struct ixgbe_hw *hw =
1504 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1507 PMD_INIT_FUNC_TRACE();
1509 /* Filter Table Disable */
1510 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1511 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1513 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1517 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1519 struct ixgbe_hw *hw =
1520 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1521 struct ixgbe_vfta * shadow_vfta =
1522 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1526 PMD_INIT_FUNC_TRACE();
1528 /* Filter Table Enable */
1529 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1530 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1531 vlnctrl |= IXGBE_VLNCTRL_VFE;
1533 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1535 /* write whatever is in local vfta copy */
1536 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1537 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1541 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1543 struct ixgbe_hwstrip *hwstrip =
1544 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1546 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1550 IXGBE_SET_HWSTRIP(hwstrip, queue);
1552 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1556 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1558 struct ixgbe_hw *hw =
1559 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1562 PMD_INIT_FUNC_TRACE();
1564 if (hw->mac.type == ixgbe_mac_82598EB) {
1565 /* No queue level support */
1566 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1570 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1571 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1572 ctrl &= ~IXGBE_RXDCTL_VME;
1573 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1575 /* record those setting for HW strip per queue */
1576 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1580 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1582 struct ixgbe_hw *hw =
1583 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1586 PMD_INIT_FUNC_TRACE();
1588 if (hw->mac.type == ixgbe_mac_82598EB) {
1589 /* No queue level supported */
1590 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1594 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1595 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1596 ctrl |= IXGBE_RXDCTL_VME;
1597 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1599 /* record those setting for HW strip per queue */
1600 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1604 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1606 struct ixgbe_hw *hw =
1607 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1611 PMD_INIT_FUNC_TRACE();
1613 if (hw->mac.type == ixgbe_mac_82598EB) {
1614 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1615 ctrl &= ~IXGBE_VLNCTRL_VME;
1616 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1619 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1620 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1621 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1622 ctrl &= ~IXGBE_RXDCTL_VME;
1623 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1625 /* record those setting for HW strip per queue */
1626 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1632 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1634 struct ixgbe_hw *hw =
1635 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1639 PMD_INIT_FUNC_TRACE();
1641 if (hw->mac.type == ixgbe_mac_82598EB) {
1642 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1643 ctrl |= IXGBE_VLNCTRL_VME;
1644 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1647 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1648 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1649 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1650 ctrl |= IXGBE_RXDCTL_VME;
1651 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1653 /* record those setting for HW strip per queue */
1654 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1660 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1662 struct ixgbe_hw *hw =
1663 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1666 PMD_INIT_FUNC_TRACE();
1668 /* DMATXCTRL: Geric Double VLAN Disable */
1669 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1670 ctrl &= ~IXGBE_DMATXCTL_GDV;
1671 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1673 /* CTRL_EXT: Global Double VLAN Disable */
1674 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1675 ctrl &= ~IXGBE_EXTENDED_VLAN;
1676 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1681 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1683 struct ixgbe_hw *hw =
1684 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1687 PMD_INIT_FUNC_TRACE();
1689 /* DMATXCTRL: Geric Double VLAN Enable */
1690 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1691 ctrl |= IXGBE_DMATXCTL_GDV;
1692 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1694 /* CTRL_EXT: Global Double VLAN Enable */
1695 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1696 ctrl |= IXGBE_EXTENDED_VLAN;
1697 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1700 * VET EXT field in the EXVET register = 0x8100 by default
1701 * So no need to change. Same to VT field of DMATXCTL register
1706 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1708 if(mask & ETH_VLAN_STRIP_MASK){
1709 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1710 ixgbe_vlan_hw_strip_enable_all(dev);
1712 ixgbe_vlan_hw_strip_disable_all(dev);
1715 if(mask & ETH_VLAN_FILTER_MASK){
1716 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1717 ixgbe_vlan_hw_filter_enable(dev);
1719 ixgbe_vlan_hw_filter_disable(dev);
1722 if(mask & ETH_VLAN_EXTEND_MASK){
1723 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1724 ixgbe_vlan_hw_extend_enable(dev);
1726 ixgbe_vlan_hw_extend_disable(dev);
1731 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1733 struct ixgbe_hw *hw =
1734 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1735 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1736 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1737 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1738 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1742 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1747 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1750 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1756 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1757 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1763 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1765 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1766 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1767 uint16_t nb_tx_q = dev->data->nb_rx_queues;
1769 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1770 /* check multi-queue mode */
1771 switch (dev_conf->rxmode.mq_mode) {
1772 case ETH_MQ_RX_VMDQ_DCB:
1773 case ETH_MQ_RX_VMDQ_DCB_RSS:
1774 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1775 PMD_INIT_LOG(ERR, "SRIOV active,"
1776 " unsupported mq_mode rx %d.",
1777 dev_conf->rxmode.mq_mode);
1780 case ETH_MQ_RX_VMDQ_RSS:
1781 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1782 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1783 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1784 PMD_INIT_LOG(ERR, "SRIOV is active,"
1785 " invalid queue number"
1786 " for VMDQ RSS, allowed"
1787 " value are 1, 2 or 4.");
1791 case ETH_MQ_RX_VMDQ_ONLY:
1792 case ETH_MQ_RX_NONE:
1793 /* if nothing mq mode configure, use default scheme */
1794 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1795 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1796 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1798 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1799 /* SRIOV only works in VMDq enable mode */
1800 PMD_INIT_LOG(ERR, "SRIOV is active,"
1801 " wrong mq_mode rx %d.",
1802 dev_conf->rxmode.mq_mode);
1806 switch (dev_conf->txmode.mq_mode) {
1807 case ETH_MQ_TX_VMDQ_DCB:
1808 /* DCB VMDQ in SRIOV mode, not implement yet */
1809 PMD_INIT_LOG(ERR, "SRIOV is active,"
1810 " unsupported VMDQ mq_mode tx %d.",
1811 dev_conf->txmode.mq_mode);
1813 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1814 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1818 /* check valid queue number */
1819 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1820 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1821 PMD_INIT_LOG(ERR, "SRIOV is active,"
1822 " queue number must less equal to %d.",
1823 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1827 /* check configuration for vmdb+dcb mode */
1828 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1829 const struct rte_eth_vmdq_dcb_conf *conf;
1831 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1832 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1833 IXGBE_VMDQ_DCB_NB_QUEUES);
1836 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1837 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1838 conf->nb_queue_pools == ETH_32_POOLS)) {
1839 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1840 " nb_queue_pools must be %d or %d.",
1841 ETH_16_POOLS, ETH_32_POOLS);
1845 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1846 const struct rte_eth_vmdq_dcb_tx_conf *conf;
1848 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1849 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1850 IXGBE_VMDQ_DCB_NB_QUEUES);
1853 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1854 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1855 conf->nb_queue_pools == ETH_32_POOLS)) {
1856 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1857 " nb_queue_pools != %d and"
1858 " nb_queue_pools != %d.",
1859 ETH_16_POOLS, ETH_32_POOLS);
1864 /* For DCB mode check our configuration before we go further */
1865 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1866 const struct rte_eth_dcb_rx_conf *conf;
1868 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1869 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1870 IXGBE_DCB_NB_QUEUES);
1873 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1874 if (!(conf->nb_tcs == ETH_4_TCS ||
1875 conf->nb_tcs == ETH_8_TCS)) {
1876 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1877 " and nb_tcs != %d.",
1878 ETH_4_TCS, ETH_8_TCS);
1883 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1884 const struct rte_eth_dcb_tx_conf *conf;
1886 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1887 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1888 IXGBE_DCB_NB_QUEUES);
1891 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1892 if (!(conf->nb_tcs == ETH_4_TCS ||
1893 conf->nb_tcs == ETH_8_TCS)) {
1894 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1895 " and nb_tcs != %d.",
1896 ETH_4_TCS, ETH_8_TCS);
1905 ixgbe_dev_configure(struct rte_eth_dev *dev)
1907 struct ixgbe_interrupt *intr =
1908 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1909 struct ixgbe_adapter *adapter =
1910 (struct ixgbe_adapter *)dev->data->dev_private;
1913 PMD_INIT_FUNC_TRACE();
1914 /* multipe queue mode checking */
1915 ret = ixgbe_check_mq_mode(dev);
1917 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
1922 /* set flag to update link status after init */
1923 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1926 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1927 * allocation or vector Rx preconditions we will reset it.
1929 adapter->rx_bulk_alloc_allowed = true;
1930 adapter->rx_vec_allowed = true;
1936 * Configure device link speed and setup link.
1937 * It returns 0 on success.
1940 ixgbe_dev_start(struct rte_eth_dev *dev)
1942 struct ixgbe_hw *hw =
1943 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1944 struct ixgbe_vf_info *vfinfo =
1945 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1946 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1947 uint32_t intr_vector = 0;
1948 int err, link_up = 0, negotiate = 0;
1954 PMD_INIT_FUNC_TRACE();
1956 /* IXGBE devices don't support half duplex */
1957 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1958 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1959 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1960 dev->data->dev_conf.link_duplex,
1961 dev->data->port_id);
1966 hw->adapter_stopped = 0;
1967 ixgbe_stop_adapter(hw);
1969 /* reinitialize adapter
1970 * this calls reset and start */
1971 status = ixgbe_pf_reset_hw(hw);
1974 hw->mac.ops.start_hw(hw);
1975 hw->mac.get_link_status = true;
1977 /* configure PF module if SRIOV enabled */
1978 ixgbe_pf_host_configure(dev);
1980 /* check and configure queue intr-vector mapping */
1981 if ((rte_intr_cap_multiple(intr_handle) ||
1982 !RTE_ETH_DEV_SRIOV(dev).active) &&
1983 dev->data->dev_conf.intr_conf.rxq != 0) {
1984 intr_vector = dev->data->nb_rx_queues;
1985 if (rte_intr_efd_enable(intr_handle, intr_vector))
1989 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1990 intr_handle->intr_vec =
1991 rte_zmalloc("intr_vec",
1992 dev->data->nb_rx_queues * sizeof(int), 0);
1993 if (intr_handle->intr_vec == NULL) {
1994 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1995 " intr_vec\n", dev->data->nb_rx_queues);
2000 /* confiugre msix for sleep until rx interrupt */
2001 ixgbe_configure_msix(dev);
2003 /* initialize transmission unit */
2004 ixgbe_dev_tx_init(dev);
2006 /* This can fail when allocating mbufs for descriptor rings */
2007 err = ixgbe_dev_rx_init(dev);
2009 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2013 err = ixgbe_dev_rxtx_start(dev);
2015 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2019 /* Skip link setup if loopback mode is enabled for 82599. */
2020 if (hw->mac.type == ixgbe_mac_82599EB &&
2021 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2022 goto skip_link_setup;
2024 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2025 err = hw->mac.ops.setup_sfp(hw);
2030 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2031 /* Turn on the copper */
2032 ixgbe_set_phy_power(hw, true);
2034 /* Turn on the laser */
2035 ixgbe_enable_tx_laser(hw);
2038 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2041 dev->data->dev_link.link_status = link_up;
2043 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2047 switch(dev->data->dev_conf.link_speed) {
2048 case ETH_LINK_SPEED_AUTONEG:
2049 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2050 IXGBE_LINK_SPEED_82599_AUTONEG :
2051 IXGBE_LINK_SPEED_82598_AUTONEG;
2053 case ETH_LINK_SPEED_100:
2055 * Invalid for 82598 but error will be detected by
2056 * ixgbe_setup_link()
2058 speed = IXGBE_LINK_SPEED_100_FULL;
2060 case ETH_LINK_SPEED_1000:
2061 speed = IXGBE_LINK_SPEED_1GB_FULL;
2063 case ETH_LINK_SPEED_10000:
2064 speed = IXGBE_LINK_SPEED_10GB_FULL;
2067 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2068 dev->data->dev_conf.link_speed,
2069 dev->data->port_id);
2073 err = ixgbe_setup_link(hw, speed, link_up);
2079 if (rte_intr_allow_others(intr_handle)) {
2080 /* check if lsc interrupt is enabled */
2081 if (dev->data->dev_conf.intr_conf.lsc != 0)
2082 ixgbe_dev_lsc_interrupt_setup(dev);
2084 rte_intr_callback_unregister(intr_handle,
2085 ixgbe_dev_interrupt_handler,
2087 if (dev->data->dev_conf.intr_conf.lsc != 0)
2088 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2089 " no intr multiplex\n");
2092 /* check if rxq interrupt is enabled */
2093 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2094 rte_intr_dp_is_en(intr_handle))
2095 ixgbe_dev_rxq_interrupt_setup(dev);
2097 /* enable uio/vfio intr/eventfd mapping */
2098 rte_intr_enable(intr_handle);
2100 /* resume enabled intr since hw reset */
2101 ixgbe_enable_intr(dev);
2103 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2104 ETH_VLAN_EXTEND_MASK;
2105 ixgbe_vlan_offload_set(dev, mask);
2107 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2108 /* Enable vlan filtering for VMDq */
2109 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2112 /* Configure DCB hw */
2113 ixgbe_configure_dcb(dev);
2115 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2116 err = ixgbe_fdir_configure(dev);
2121 /* Restore vf rate limit */
2122 if (vfinfo != NULL) {
2123 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2124 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2125 if (vfinfo[vf].tx_rate[idx] != 0)
2126 ixgbe_set_vf_rate_limit(dev, vf,
2127 vfinfo[vf].tx_rate[idx],
2131 ixgbe_restore_statistics_mapping(dev);
2136 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2137 ixgbe_dev_clear_queues(dev);
2142 * Stop device: disable rx and tx functions to allow for reconfiguring.
2145 ixgbe_dev_stop(struct rte_eth_dev *dev)
2147 struct rte_eth_link link;
2148 struct ixgbe_hw *hw =
2149 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150 struct ixgbe_vf_info *vfinfo =
2151 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2152 struct ixgbe_filter_info *filter_info =
2153 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2154 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2155 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2158 PMD_INIT_FUNC_TRACE();
2160 /* disable interrupts */
2161 ixgbe_disable_intr(hw);
2163 /* disable intr eventfd mapping */
2164 rte_intr_disable(intr_handle);
2167 ixgbe_pf_reset_hw(hw);
2168 hw->adapter_stopped = 0;
2171 ixgbe_stop_adapter(hw);
2173 for (vf = 0; vfinfo != NULL &&
2174 vf < dev->pci_dev->max_vfs; vf++)
2175 vfinfo[vf].clear_to_send = false;
2177 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2178 /* Turn off the copper */
2179 ixgbe_set_phy_power(hw, false);
2181 /* Turn off the laser */
2182 ixgbe_disable_tx_laser(hw);
2185 ixgbe_dev_clear_queues(dev);
2187 /* Clear stored conf */
2188 dev->data->scattered_rx = 0;
2191 /* Clear recorded link status */
2192 memset(&link, 0, sizeof(link));
2193 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2195 /* Remove all ntuple filters of the device */
2196 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2197 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2198 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2199 TAILQ_REMOVE(&filter_info->fivetuple_list,
2203 memset(filter_info->fivetuple_mask, 0,
2204 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2206 if (!rte_intr_allow_others(intr_handle))
2207 /* resume to the default handler */
2208 rte_intr_callback_register(intr_handle,
2209 ixgbe_dev_interrupt_handler,
2212 /* Clean datapath event and queue/vec mapping */
2213 rte_intr_efd_disable(intr_handle);
2214 if (intr_handle->intr_vec != NULL) {
2215 rte_free(intr_handle->intr_vec);
2216 intr_handle->intr_vec = NULL;
2221 * Set device link up: enable tx.
2224 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2226 struct ixgbe_hw *hw =
2227 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2228 if (hw->mac.type == ixgbe_mac_82599EB) {
2229 #ifdef RTE_NIC_BYPASS
2230 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2231 /* Not suported in bypass mode */
2232 PMD_INIT_LOG(ERR, "Set link up is not supported "
2233 "by device id 0x%x", hw->device_id);
2239 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2240 /* Turn on the copper */
2241 ixgbe_set_phy_power(hw, true);
2243 /* Turn on the laser */
2244 ixgbe_enable_tx_laser(hw);
2251 * Set device link down: disable tx.
2254 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2256 struct ixgbe_hw *hw =
2257 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2258 if (hw->mac.type == ixgbe_mac_82599EB) {
2259 #ifdef RTE_NIC_BYPASS
2260 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2261 /* Not suported in bypass mode */
2262 PMD_INIT_LOG(ERR, "Set link down is not supported "
2263 "by device id 0x%x", hw->device_id);
2269 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2270 /* Turn off the copper */
2271 ixgbe_set_phy_power(hw, false);
2273 /* Turn off the laser */
2274 ixgbe_disable_tx_laser(hw);
2281 * Reest and stop device.
2284 ixgbe_dev_close(struct rte_eth_dev *dev)
2286 struct ixgbe_hw *hw =
2287 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2289 PMD_INIT_FUNC_TRACE();
2291 ixgbe_pf_reset_hw(hw);
2293 ixgbe_dev_stop(dev);
2294 hw->adapter_stopped = 1;
2296 ixgbe_dev_free_queues(dev);
2298 ixgbe_disable_pcie_master(hw);
2300 /* reprogram the RAR[0] in case user changed it. */
2301 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2305 ixgbe_read_stats_registers(struct ixgbe_hw *hw, struct ixgbe_hw_stats
2306 *hw_stats, uint64_t *total_missed_rx,
2307 uint64_t *total_qbrc, uint64_t *total_qprc,
2308 uint64_t *total_qprdc)
2310 uint32_t bprc, lxon, lxoff, total;
2313 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2314 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2315 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2316 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2318 for (i = 0; i < 8; i++) {
2320 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2321 /* global total per queue */
2322 hw_stats->mpc[i] += mp;
2323 /* Running comprehensive total for stats display */
2324 *total_missed_rx += hw_stats->mpc[i];
2325 if (hw->mac.type == ixgbe_mac_82598EB) {
2326 hw_stats->rnbc[i] +=
2327 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2328 hw_stats->pxonrxc[i] +=
2329 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2330 hw_stats->pxoffrxc[i] +=
2331 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2333 hw_stats->pxonrxc[i] +=
2334 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2335 hw_stats->pxoffrxc[i] +=
2336 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2337 hw_stats->pxon2offc[i] +=
2338 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2340 hw_stats->pxontxc[i] +=
2341 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2342 hw_stats->pxofftxc[i] +=
2343 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2345 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2346 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2347 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2348 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2349 hw_stats->qbrc[i] +=
2350 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2351 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2352 hw_stats->qbtc[i] +=
2353 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2354 *total_qprdc += hw_stats->qprdc[i] +=
2355 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2357 *total_qprc += hw_stats->qprc[i];
2358 *total_qbrc += hw_stats->qbrc[i];
2360 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2361 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2362 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2364 /* Note that gprc counts missed packets */
2365 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2367 if (hw->mac.type != ixgbe_mac_82598EB) {
2368 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2369 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2370 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2371 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2372 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2373 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2374 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2375 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2377 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2378 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2379 /* 82598 only has a counter in the high register */
2380 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2381 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2382 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2386 * Workaround: mprc hardware is incorrectly counting
2387 * broadcasts, so for now we subtract those.
2389 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2390 hw_stats->bprc += bprc;
2391 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2392 if (hw->mac.type == ixgbe_mac_82598EB)
2393 hw_stats->mprc -= bprc;
2395 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2396 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2397 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2398 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2399 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2400 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2402 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2403 hw_stats->lxontxc += lxon;
2404 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2405 hw_stats->lxofftxc += lxoff;
2406 total = lxon + lxoff;
2408 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2409 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2410 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2411 hw_stats->gptc -= total;
2412 hw_stats->mptc -= total;
2413 hw_stats->ptc64 -= total;
2414 hw_stats->gotc -= total * ETHER_MIN_LEN;
2416 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2417 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2418 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2419 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2420 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2421 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2422 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2423 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2424 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2425 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2426 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2427 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2428 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2429 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2430 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2431 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2432 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2433 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2434 /* Only read FCOE on 82599 */
2435 if (hw->mac.type != ixgbe_mac_82598EB) {
2436 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2437 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2438 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2439 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2440 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2443 /* Flow Director Stats registers */
2444 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2445 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2449 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2452 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2454 struct ixgbe_hw *hw =
2455 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2456 struct ixgbe_hw_stats *hw_stats =
2457 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2458 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2461 total_missed_rx = 0;
2466 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2467 &total_qprc, &total_qprdc);
2472 /* Fill out the rte_eth_stats statistics structure */
2473 stats->ipackets = total_qprc;
2474 stats->ibytes = total_qbrc;
2475 stats->opackets = hw_stats->gptc;
2476 stats->obytes = hw_stats->gotc;
2478 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2479 stats->q_ipackets[i] = hw_stats->qprc[i];
2480 stats->q_opackets[i] = hw_stats->qptc[i];
2481 stats->q_ibytes[i] = hw_stats->qbrc[i];
2482 stats->q_obytes[i] = hw_stats->qbtc[i];
2483 stats->q_errors[i] = hw_stats->qprdc[i];
2487 stats->ierrors = hw_stats->crcerrs +
2504 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2506 struct ixgbe_hw_stats *stats =
2507 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2509 /* HW registers are cleared on read */
2510 ixgbe_dev_stats_get(dev, NULL);
2512 /* Reset software totals */
2513 memset(stats, 0, sizeof(*stats));
2517 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2520 struct ixgbe_hw *hw =
2521 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2522 struct ixgbe_hw_stats *hw_stats =
2523 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2524 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2525 unsigned i, count = IXGBE_NB_XSTATS;
2530 total_missed_rx = 0;
2535 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2536 &total_qprc, &total_qprdc);
2538 /* If this is a reset xstats is NULL, and we have cleared the
2539 * registers by reading them.
2544 /* Extended stats from ixgbe_hw_stats */
2546 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2547 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2548 rte_ixgbe_stats_strings[i].name);
2549 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2550 rte_ixgbe_stats_strings[i].offset);
2554 /* Per-Q stats, with 8 queues available */
2555 for (i = 0; i < 8; i++) {
2556 snprintf(xstats[count].name, sizeof(xstats[count].name),
2557 "rx_q%u_mbuf_allocation_errors", i);
2558 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2559 offsetof(struct ixgbe_hw_stats, rnbc[i]));
2562 snprintf(xstats[count].name, sizeof(xstats[count].name),
2563 "rx_q%u_missed_packets", i);
2564 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2565 offsetof(struct ixgbe_hw_stats, mpc[i]));
2568 snprintf(xstats[count].name, sizeof(xstats[count].name),
2569 "rx_q%u_xon_priority_packets", i);
2570 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2571 offsetof(struct ixgbe_hw_stats, pxonrxc[i]));
2574 snprintf(xstats[count].name, sizeof(xstats[count].name),
2575 "tx_q%u_xon_priority_packets", i);
2576 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2577 offsetof(struct ixgbe_hw_stats, pxontxc[i]));
2580 snprintf(xstats[count].name, sizeof(xstats[count].name),
2581 "rx_q%u_xoff_priority_packets", i);
2582 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2583 offsetof(struct ixgbe_hw_stats, pxoffrxc[i]));
2586 snprintf(xstats[count].name, sizeof(xstats[count].name),
2587 "tx_q%u_xoff_priority_packets", i);
2588 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2589 offsetof(struct ixgbe_hw_stats, pxofftxc[i]));
2592 snprintf(xstats[count].name, sizeof(xstats[count].name),
2593 "xx_q%u_xon_to_xoff_priority_packets", i);
2594 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2595 offsetof(struct ixgbe_hw_stats, pxon2offc[i]));
2599 for (i = 0; i < 16; i++) {
2600 snprintf(xstats[count].name, sizeof(xstats[count].name),
2601 "rx_q%u_packets", i);
2602 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2603 offsetof(struct ixgbe_hw_stats, qprc[i]));
2606 snprintf(xstats[count].name, sizeof(xstats[count].name),
2608 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2609 offsetof(struct ixgbe_hw_stats, qbrc[i]));
2612 snprintf(xstats[count].name, sizeof(xstats[count].name),
2613 "tx_q%u_packets", i);
2614 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2615 offsetof(struct ixgbe_hw_stats, qptc[i]));
2618 snprintf(xstats[count].name, sizeof(xstats[count].name),
2620 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2621 offsetof(struct ixgbe_hw_stats, qbtc[i]));
2624 snprintf(xstats[count].name, sizeof(xstats[count].name),
2625 "rx_q%u_dropped", i);
2626 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2627 offsetof(struct ixgbe_hw_stats, qprdc[i]));
2635 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2637 struct ixgbe_hw_stats *stats =
2638 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2640 /* HW registers are cleared on read */
2641 ixgbe_dev_xstats_get(dev, NULL, IXGBE_NB_XSTATS);
2643 /* Reset software totals */
2644 memset(stats, 0, sizeof(*stats));
2648 ixgbevf_update_stats(struct rte_eth_dev *dev)
2650 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2651 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2652 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2654 /* Good Rx packet, include VF loopback */
2655 UPDATE_VF_STAT(IXGBE_VFGPRC,
2656 hw_stats->last_vfgprc, hw_stats->vfgprc);
2658 /* Good Rx octets, include VF loopback */
2659 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2660 hw_stats->last_vfgorc, hw_stats->vfgorc);
2662 /* Good Tx packet, include VF loopback */
2663 UPDATE_VF_STAT(IXGBE_VFGPTC,
2664 hw_stats->last_vfgptc, hw_stats->vfgptc);
2666 /* Good Tx octets, include VF loopback */
2667 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2668 hw_stats->last_vfgotc, hw_stats->vfgotc);
2670 /* Rx Multicst Packet */
2671 UPDATE_VF_STAT(IXGBE_VFMPRC,
2672 hw_stats->last_vfmprc, hw_stats->vfmprc);
2676 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2679 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2680 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2683 if (n < IXGBEVF_NB_XSTATS)
2684 return IXGBEVF_NB_XSTATS;
2686 ixgbevf_update_stats(dev);
2691 /* Extended stats */
2692 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2693 snprintf(xstats[i].name, sizeof(xstats[i].name),
2694 "%s", rte_ixgbevf_stats_strings[i].name);
2695 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2696 rte_ixgbevf_stats_strings[i].offset);
2699 return IXGBEVF_NB_XSTATS;
2703 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2705 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2706 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2708 ixgbevf_update_stats(dev);
2713 stats->ipackets = hw_stats->vfgprc;
2714 stats->ibytes = hw_stats->vfgorc;
2715 stats->opackets = hw_stats->vfgptc;
2716 stats->obytes = hw_stats->vfgotc;
2717 stats->imcasts = hw_stats->vfmprc;
2718 /* stats->imcasts should be removed as imcasts is deprecated */
2722 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2724 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2725 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2727 /* Sync HW register to the last stats */
2728 ixgbevf_dev_stats_get(dev, NULL);
2730 /* reset HW current stats*/
2731 hw_stats->vfgprc = 0;
2732 hw_stats->vfgorc = 0;
2733 hw_stats->vfgptc = 0;
2734 hw_stats->vfgotc = 0;
2735 hw_stats->vfmprc = 0;
2740 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2742 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2744 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2745 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2746 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2747 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2748 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2749 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2750 dev_info->max_vfs = dev->pci_dev->max_vfs;
2751 if (hw->mac.type == ixgbe_mac_82598EB)
2752 dev_info->max_vmdq_pools = ETH_16_POOLS;
2754 dev_info->max_vmdq_pools = ETH_64_POOLS;
2755 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2756 dev_info->rx_offload_capa =
2757 DEV_RX_OFFLOAD_VLAN_STRIP |
2758 DEV_RX_OFFLOAD_IPV4_CKSUM |
2759 DEV_RX_OFFLOAD_UDP_CKSUM |
2760 DEV_RX_OFFLOAD_TCP_CKSUM;
2763 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2766 if ((hw->mac.type == ixgbe_mac_82599EB ||
2767 hw->mac.type == ixgbe_mac_X540) &&
2768 !RTE_ETH_DEV_SRIOV(dev).active)
2769 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2771 dev_info->tx_offload_capa =
2772 DEV_TX_OFFLOAD_VLAN_INSERT |
2773 DEV_TX_OFFLOAD_IPV4_CKSUM |
2774 DEV_TX_OFFLOAD_UDP_CKSUM |
2775 DEV_TX_OFFLOAD_TCP_CKSUM |
2776 DEV_TX_OFFLOAD_SCTP_CKSUM |
2777 DEV_TX_OFFLOAD_TCP_TSO;
2779 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2781 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2782 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2783 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2785 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2789 dev_info->default_txconf = (struct rte_eth_txconf) {
2791 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2792 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2793 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2795 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2796 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2797 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2798 ETH_TXQ_FLAGS_NOOFFLOADS,
2801 dev_info->rx_desc_lim = rx_desc_lim;
2802 dev_info->tx_desc_lim = tx_desc_lim;
2804 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2805 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2806 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2810 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2811 struct rte_eth_dev_info *dev_info)
2813 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2815 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2816 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2817 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2818 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2819 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2820 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2821 dev_info->max_vfs = dev->pci_dev->max_vfs;
2822 if (hw->mac.type == ixgbe_mac_82598EB)
2823 dev_info->max_vmdq_pools = ETH_16_POOLS;
2825 dev_info->max_vmdq_pools = ETH_64_POOLS;
2826 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2827 DEV_RX_OFFLOAD_IPV4_CKSUM |
2828 DEV_RX_OFFLOAD_UDP_CKSUM |
2829 DEV_RX_OFFLOAD_TCP_CKSUM;
2830 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2831 DEV_TX_OFFLOAD_IPV4_CKSUM |
2832 DEV_TX_OFFLOAD_UDP_CKSUM |
2833 DEV_TX_OFFLOAD_TCP_CKSUM |
2834 DEV_TX_OFFLOAD_SCTP_CKSUM |
2835 DEV_TX_OFFLOAD_TCP_TSO;
2837 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2839 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2840 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2841 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2843 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2847 dev_info->default_txconf = (struct rte_eth_txconf) {
2849 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2850 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2851 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2853 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2854 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2855 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2856 ETH_TXQ_FLAGS_NOOFFLOADS,
2859 dev_info->rx_desc_lim = rx_desc_lim;
2860 dev_info->tx_desc_lim = tx_desc_lim;
2863 /* return 0 means link status changed, -1 means not changed */
2865 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2867 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2868 struct rte_eth_link link, old;
2869 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2873 link.link_status = 0;
2874 link.link_speed = 0;
2875 link.link_duplex = 0;
2876 memset(&old, 0, sizeof(old));
2877 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2879 hw->mac.get_link_status = true;
2881 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2882 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2883 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2885 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2888 link.link_speed = ETH_LINK_SPEED_100;
2889 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2890 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2891 if (link.link_status == old.link_status)
2897 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2898 if (link.link_status == old.link_status)
2902 link.link_status = 1;
2903 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2905 switch (link_speed) {
2907 case IXGBE_LINK_SPEED_UNKNOWN:
2908 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2909 link.link_speed = ETH_LINK_SPEED_100;
2912 case IXGBE_LINK_SPEED_100_FULL:
2913 link.link_speed = ETH_LINK_SPEED_100;
2916 case IXGBE_LINK_SPEED_1GB_FULL:
2917 link.link_speed = ETH_LINK_SPEED_1000;
2920 case IXGBE_LINK_SPEED_10GB_FULL:
2921 link.link_speed = ETH_LINK_SPEED_10000;
2924 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2926 if (link.link_status == old.link_status)
2933 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2935 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2938 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2939 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2940 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2944 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2946 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2949 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2950 fctrl &= (~IXGBE_FCTRL_UPE);
2951 if (dev->data->all_multicast == 1)
2952 fctrl |= IXGBE_FCTRL_MPE;
2954 fctrl &= (~IXGBE_FCTRL_MPE);
2955 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2959 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2961 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2964 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2965 fctrl |= IXGBE_FCTRL_MPE;
2966 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2970 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2972 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2975 if (dev->data->promiscuous == 1)
2976 return; /* must remain in all_multicast mode */
2978 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2979 fctrl &= (~IXGBE_FCTRL_MPE);
2980 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2984 * It clears the interrupt causes and enables the interrupt.
2985 * It will be called once only during nic initialized.
2988 * Pointer to struct rte_eth_dev.
2991 * - On success, zero.
2992 * - On failure, a negative value.
2995 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2997 struct ixgbe_interrupt *intr =
2998 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3000 ixgbe_dev_link_status_print(dev);
3001 intr->mask |= IXGBE_EICR_LSC;
3007 * It clears the interrupt causes and enables the interrupt.
3008 * It will be called once only during nic initialized.
3011 * Pointer to struct rte_eth_dev.
3014 * - On success, zero.
3015 * - On failure, a negative value.
3018 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3020 struct ixgbe_interrupt *intr =
3021 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3023 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3029 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3032 * Pointer to struct rte_eth_dev.
3035 * - On success, zero.
3036 * - On failure, a negative value.
3039 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3042 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3043 struct ixgbe_interrupt *intr =
3044 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3046 /* clear all cause mask */
3047 ixgbe_disable_intr(hw);
3049 /* read-on-clear nic registers here */
3050 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3051 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3055 /* set flag for async link update */
3056 if (eicr & IXGBE_EICR_LSC)
3057 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3059 if (eicr & IXGBE_EICR_MAILBOX)
3060 intr->flags |= IXGBE_FLAG_MAILBOX;
3066 * It gets and then prints the link status.
3069 * Pointer to struct rte_eth_dev.
3072 * - On success, zero.
3073 * - On failure, a negative value.
3076 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3078 struct rte_eth_link link;
3080 memset(&link, 0, sizeof(link));
3081 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3082 if (link.link_status) {
3083 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3084 (int)(dev->data->port_id),
3085 (unsigned)link.link_speed,
3086 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3087 "full-duplex" : "half-duplex");
3089 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3090 (int)(dev->data->port_id));
3092 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3093 dev->pci_dev->addr.domain,
3094 dev->pci_dev->addr.bus,
3095 dev->pci_dev->addr.devid,
3096 dev->pci_dev->addr.function);
3100 * It executes link_update after knowing an interrupt occurred.
3103 * Pointer to struct rte_eth_dev.
3106 * - On success, zero.
3107 * - On failure, a negative value.
3110 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3112 struct ixgbe_interrupt *intr =
3113 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3115 struct rte_eth_link link;
3116 int intr_enable_delay = false;
3118 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3120 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3121 ixgbe_pf_mbx_process(dev);
3122 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3125 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3126 /* get the link status before link update, for predicting later */
3127 memset(&link, 0, sizeof(link));
3128 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3130 ixgbe_dev_link_update(dev, 0);
3133 if (!link.link_status)
3134 /* handle it 1 sec later, wait it being stable */
3135 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3136 /* likely to down */
3138 /* handle it 4 sec later, wait it being stable */
3139 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3141 ixgbe_dev_link_status_print(dev);
3143 intr_enable_delay = true;
3146 if (intr_enable_delay) {
3147 if (rte_eal_alarm_set(timeout * 1000,
3148 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3149 PMD_DRV_LOG(ERR, "Error setting alarm");
3151 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3152 ixgbe_enable_intr(dev);
3153 rte_intr_enable(&(dev->pci_dev->intr_handle));
3161 * Interrupt handler which shall be registered for alarm callback for delayed
3162 * handling specific interrupt to wait for the stable nic state. As the
3163 * NIC interrupt state is not stable for ixgbe after link is just down,
3164 * it needs to wait 4 seconds to get the stable status.
3167 * Pointer to interrupt handle.
3169 * The address of parameter (struct rte_eth_dev *) regsitered before.
3175 ixgbe_dev_interrupt_delayed_handler(void *param)
3177 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3178 struct ixgbe_interrupt *intr =
3179 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3180 struct ixgbe_hw *hw =
3181 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3184 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3185 if (eicr & IXGBE_EICR_MAILBOX)
3186 ixgbe_pf_mbx_process(dev);
3188 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3189 ixgbe_dev_link_update(dev, 0);
3190 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3191 ixgbe_dev_link_status_print(dev);
3192 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3195 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3196 ixgbe_enable_intr(dev);
3197 rte_intr_enable(&(dev->pci_dev->intr_handle));
3201 * Interrupt handler triggered by NIC for handling
3202 * specific interrupt.
3205 * Pointer to interrupt handle.
3207 * The address of parameter (struct rte_eth_dev *) regsitered before.
3213 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3216 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3218 ixgbe_dev_interrupt_get_status(dev);
3219 ixgbe_dev_interrupt_action(dev);
3223 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3225 struct ixgbe_hw *hw;
3227 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3228 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3232 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3234 struct ixgbe_hw *hw;
3236 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3237 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3241 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3243 struct ixgbe_hw *hw;
3249 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3251 fc_conf->pause_time = hw->fc.pause_time;
3252 fc_conf->high_water = hw->fc.high_water[0];
3253 fc_conf->low_water = hw->fc.low_water[0];
3254 fc_conf->send_xon = hw->fc.send_xon;
3255 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3258 * Return rx_pause status according to actual setting of
3261 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3262 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3268 * Return tx_pause status according to actual setting of
3271 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3272 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3277 if (rx_pause && tx_pause)
3278 fc_conf->mode = RTE_FC_FULL;
3280 fc_conf->mode = RTE_FC_RX_PAUSE;
3282 fc_conf->mode = RTE_FC_TX_PAUSE;
3284 fc_conf->mode = RTE_FC_NONE;
3290 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3292 struct ixgbe_hw *hw;
3294 uint32_t rx_buf_size;
3295 uint32_t max_high_water;
3297 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3304 PMD_INIT_FUNC_TRACE();
3306 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3307 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3308 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3311 * At least reserve one Ethernet frame for watermark
3312 * high_water/low_water in kilo bytes for ixgbe
3314 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3315 if ((fc_conf->high_water > max_high_water) ||
3316 (fc_conf->high_water < fc_conf->low_water)) {
3317 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3318 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3322 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3323 hw->fc.pause_time = fc_conf->pause_time;
3324 hw->fc.high_water[0] = fc_conf->high_water;
3325 hw->fc.low_water[0] = fc_conf->low_water;
3326 hw->fc.send_xon = fc_conf->send_xon;
3327 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3329 err = ixgbe_fc_enable(hw);
3331 /* Not negotiated is not an error case */
3332 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3334 /* check if we want to forward MAC frames - driver doesn't have native
3335 * capability to do that, so we'll write the registers ourselves */
3337 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3339 /* set or clear MFLCN.PMCF bit depending on configuration */
3340 if (fc_conf->mac_ctrl_frame_fwd != 0)
3341 mflcn |= IXGBE_MFLCN_PMCF;
3343 mflcn &= ~IXGBE_MFLCN_PMCF;
3345 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3346 IXGBE_WRITE_FLUSH(hw);
3351 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3356 * ixgbe_pfc_enable_generic - Enable flow control
3357 * @hw: pointer to hardware structure
3358 * @tc_num: traffic class number
3359 * Enable flow control according to the current settings.
3362 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3365 uint32_t mflcn_reg, fccfg_reg;
3367 uint32_t fcrtl, fcrth;
3371 /* Validate the water mark configuration */
3372 if (!hw->fc.pause_time) {
3373 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3377 /* Low water mark of zero causes XOFF floods */
3378 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3379 /* High/Low water can not be 0 */
3380 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
3381 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3382 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3386 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3387 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3388 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3392 /* Negotiate the fc mode to use */
3393 ixgbe_fc_autoneg(hw);
3395 /* Disable any previous flow control settings */
3396 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3397 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3399 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3400 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3402 switch (hw->fc.current_mode) {
3405 * If the count of enabled RX Priority Flow control >1,
3406 * and the TX pause can not be disabled
3409 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3410 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3411 if (reg & IXGBE_FCRTH_FCEN)
3415 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3417 case ixgbe_fc_rx_pause:
3419 * Rx Flow control is enabled and Tx Flow control is
3420 * disabled by software override. Since there really
3421 * isn't a way to advertise that we are capable of RX
3422 * Pause ONLY, we will advertise that we support both
3423 * symmetric and asymmetric Rx PAUSE. Later, we will
3424 * disable the adapter's ability to send PAUSE frames.
3426 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3428 * If the count of enabled RX Priority Flow control >1,
3429 * and the TX pause can not be disabled
3432 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3433 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3434 if (reg & IXGBE_FCRTH_FCEN)
3438 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3440 case ixgbe_fc_tx_pause:
3442 * Tx Flow control is enabled, and Rx Flow control is
3443 * disabled by software override.
3445 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3448 /* Flow control (both Rx and Tx) is enabled by SW override. */
3449 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3450 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3453 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3454 ret_val = IXGBE_ERR_CONFIG;
3459 /* Set 802.3x based flow control settings. */
3460 mflcn_reg |= IXGBE_MFLCN_DPF;
3461 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3462 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3464 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3465 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3466 hw->fc.high_water[tc_num]) {
3467 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3468 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3469 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3471 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3473 * In order to prevent Tx hangs when the internal Tx
3474 * switch is enabled we must set the high water mark
3475 * to the maximum FCRTH value. This allows the Tx
3476 * switch to function even under heavy Rx workloads.
3478 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3480 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3482 /* Configure pause time (2 TCs per register) */
3483 reg = hw->fc.pause_time * 0x00010001;
3484 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3485 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3487 /* Configure flow control refresh threshold value */
3488 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3495 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3497 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3498 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3500 if(hw->mac.type != ixgbe_mac_82598EB) {
3501 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3507 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3510 uint32_t rx_buf_size;
3511 uint32_t max_high_water;
3513 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3514 struct ixgbe_hw *hw =
3515 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3516 struct ixgbe_dcb_config *dcb_config =
3517 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3519 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3526 PMD_INIT_FUNC_TRACE();
3528 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3529 tc_num = map[pfc_conf->priority];
3530 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3531 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3533 * At least reserve one Ethernet frame for watermark
3534 * high_water/low_water in kilo bytes for ixgbe
3536 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3537 if ((pfc_conf->fc.high_water > max_high_water) ||
3538 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3539 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3540 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3544 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3545 hw->fc.pause_time = pfc_conf->fc.pause_time;
3546 hw->fc.send_xon = pfc_conf->fc.send_xon;
3547 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
3548 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3550 err = ixgbe_dcb_pfc_enable(dev,tc_num);
3552 /* Not negotiated is not an error case */
3553 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3556 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3561 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3562 struct rte_eth_rss_reta_entry64 *reta_conf,
3567 uint16_t idx, shift;
3568 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3569 uint16_t sp_reta_size;
3572 PMD_INIT_FUNC_TRACE();
3574 if (!ixgbe_rss_update_sp(hw->mac.type)) {
3575 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3580 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3581 if (reta_size != sp_reta_size) {
3582 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3583 "(%d) doesn't match the number hardware can supported "
3584 "(%d)\n", reta_size, sp_reta_size);
3588 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3589 idx = i / RTE_RETA_GROUP_SIZE;
3590 shift = i % RTE_RETA_GROUP_SIZE;
3591 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3595 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3596 if (mask == IXGBE_4_BIT_MASK)
3599 r = IXGBE_READ_REG(hw, reta_reg);
3600 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3601 if (mask & (0x1 << j))
3602 reta |= reta_conf[idx].reta[shift + j] <<
3605 reta |= r & (IXGBE_8_BIT_MASK <<
3608 IXGBE_WRITE_REG(hw, reta_reg, reta);
3615 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3616 struct rte_eth_rss_reta_entry64 *reta_conf,
3621 uint16_t idx, shift;
3622 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3623 uint16_t sp_reta_size;
3626 PMD_INIT_FUNC_TRACE();
3627 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3628 if (reta_size != sp_reta_size) {
3629 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3630 "(%d) doesn't match the number hardware can supported "
3631 "(%d)\n", reta_size, sp_reta_size);
3635 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3636 idx = i / RTE_RETA_GROUP_SIZE;
3637 shift = i % RTE_RETA_GROUP_SIZE;
3638 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3643 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3644 reta = IXGBE_READ_REG(hw, reta_reg);
3645 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3646 if (mask & (0x1 << j))
3647 reta_conf[idx].reta[shift + j] =
3648 ((reta >> (CHAR_BIT * j)) &
3657 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3658 uint32_t index, uint32_t pool)
3660 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3661 uint32_t enable_addr = 1;
3663 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3667 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3669 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3671 ixgbe_clear_rar(hw, index);
3675 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3677 ixgbe_remove_rar(dev, 0);
3679 ixgbe_add_rar(dev, addr, 0, 0);
3683 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3687 struct ixgbe_hw *hw;
3688 struct rte_eth_dev_info dev_info;
3689 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3691 ixgbe_dev_info_get(dev, &dev_info);
3693 /* check that mtu is within the allowed range */
3694 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3697 /* refuse mtu that requires the support of scattered packets when this
3698 * feature has not been enabled before. */
3699 if (!dev->data->scattered_rx &&
3700 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3701 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3704 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3705 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3707 /* switch to jumbo mode if needed */
3708 if (frame_size > ETHER_MAX_LEN) {
3709 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3710 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3712 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3713 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3715 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3717 /* update max frame size */
3718 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3720 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3721 maxfrs &= 0x0000FFFF;
3722 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3723 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3729 * Virtual Function operations
3732 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3734 PMD_INIT_FUNC_TRACE();
3736 /* Clear interrupt mask to stop from interrupts being generated */
3737 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3739 IXGBE_WRITE_FLUSH(hw);
3743 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3745 PMD_INIT_FUNC_TRACE();
3747 /* VF enable interrupt autoclean */
3748 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3749 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3750 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3752 IXGBE_WRITE_FLUSH(hw);
3756 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3758 struct rte_eth_conf* conf = &dev->data->dev_conf;
3759 struct ixgbe_adapter *adapter =
3760 (struct ixgbe_adapter *)dev->data->dev_private;
3762 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3763 dev->data->port_id);
3766 * VF has no ability to enable/disable HW CRC
3767 * Keep the persistent behavior the same as Host PF
3769 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3770 if (!conf->rxmode.hw_strip_crc) {
3771 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3772 conf->rxmode.hw_strip_crc = 1;
3775 if (conf->rxmode.hw_strip_crc) {
3776 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3777 conf->rxmode.hw_strip_crc = 0;
3782 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3783 * allocation or vector Rx preconditions we will reset it.
3785 adapter->rx_bulk_alloc_allowed = true;
3786 adapter->rx_vec_allowed = true;
3792 ixgbevf_dev_start(struct rte_eth_dev *dev)
3794 struct ixgbe_hw *hw =
3795 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3796 uint32_t intr_vector = 0;
3797 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3801 PMD_INIT_FUNC_TRACE();
3803 hw->mac.ops.reset_hw(hw);
3804 hw->mac.get_link_status = true;
3806 /* negotiate mailbox API version to use with the PF. */
3807 ixgbevf_negotiate_api(hw);
3809 ixgbevf_dev_tx_init(dev);
3811 /* This can fail when allocating mbufs for descriptor rings */
3812 err = ixgbevf_dev_rx_init(dev);
3814 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3815 ixgbe_dev_clear_queues(dev);
3820 ixgbevf_set_vfta_all(dev,1);
3823 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3824 ETH_VLAN_EXTEND_MASK;
3825 ixgbevf_vlan_offload_set(dev, mask);
3827 ixgbevf_dev_rxtx_start(dev);
3829 /* check and configure queue intr-vector mapping */
3830 if (dev->data->dev_conf.intr_conf.rxq != 0) {
3831 intr_vector = dev->data->nb_rx_queues;
3832 if (rte_intr_efd_enable(intr_handle, intr_vector))
3836 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3837 intr_handle->intr_vec =
3838 rte_zmalloc("intr_vec",
3839 dev->data->nb_rx_queues * sizeof(int), 0);
3840 if (intr_handle->intr_vec == NULL) {
3841 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3842 " intr_vec\n", dev->data->nb_rx_queues);
3846 ixgbevf_configure_msix(dev);
3848 rte_intr_enable(intr_handle);
3850 /* Re-enable interrupt for VF */
3851 ixgbevf_intr_enable(hw);
3857 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3859 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3860 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3862 PMD_INIT_FUNC_TRACE();
3864 hw->adapter_stopped = 1;
3865 ixgbe_stop_adapter(hw);
3868 * Clear what we set, but we still keep shadow_vfta to
3869 * restore after device starts
3871 ixgbevf_set_vfta_all(dev,0);
3873 /* Clear stored conf */
3874 dev->data->scattered_rx = 0;
3876 ixgbe_dev_clear_queues(dev);
3878 /* disable intr eventfd mapping */
3879 rte_intr_disable(intr_handle);
3881 /* Clean datapath event and queue/vec mapping */
3882 rte_intr_efd_disable(intr_handle);
3883 if (intr_handle->intr_vec != NULL) {
3884 rte_free(intr_handle->intr_vec);
3885 intr_handle->intr_vec = NULL;
3890 ixgbevf_dev_close(struct rte_eth_dev *dev)
3892 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3894 PMD_INIT_FUNC_TRACE();
3898 ixgbevf_dev_stop(dev);
3900 ixgbe_dev_free_queues(dev);
3902 /* reprogram the RAR[0] in case user changed it. */
3903 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3906 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3908 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3909 struct ixgbe_vfta * shadow_vfta =
3910 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3911 int i = 0, j = 0, vfta = 0, mask = 1;
3913 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3914 vfta = shadow_vfta->vfta[i];
3917 for (j = 0; j < 32; j++){
3919 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3928 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3930 struct ixgbe_hw *hw =
3931 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3932 struct ixgbe_vfta * shadow_vfta =
3933 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3934 uint32_t vid_idx = 0;
3935 uint32_t vid_bit = 0;
3938 PMD_INIT_FUNC_TRACE();
3940 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3941 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3943 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3946 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3947 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3949 /* Save what we set and retore it after device reset */
3951 shadow_vfta->vfta[vid_idx] |= vid_bit;
3953 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3959 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3961 struct ixgbe_hw *hw =
3962 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3965 PMD_INIT_FUNC_TRACE();
3967 if(queue >= hw->mac.max_rx_queues)
3970 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3972 ctrl |= IXGBE_RXDCTL_VME;
3974 ctrl &= ~IXGBE_RXDCTL_VME;
3975 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3977 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3981 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3983 struct ixgbe_hw *hw =
3984 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3988 /* VF function only support hw strip feature, others are not support */
3989 if(mask & ETH_VLAN_STRIP_MASK){
3990 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3992 for(i=0; i < hw->mac.max_rx_queues; i++)
3993 ixgbevf_vlan_strip_queue_set(dev,i,on);
3998 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4002 /* we only need to do this if VMDq is enabled */
4003 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4004 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4005 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4013 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4015 uint32_t vector = 0;
4016 switch (hw->mac.mc_filter_type) {
4017 case 0: /* use bits [47:36] of the address */
4018 vector = ((uc_addr->addr_bytes[4] >> 4) |
4019 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4021 case 1: /* use bits [46:35] of the address */
4022 vector = ((uc_addr->addr_bytes[4] >> 3) |
4023 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4025 case 2: /* use bits [45:34] of the address */
4026 vector = ((uc_addr->addr_bytes[4] >> 2) |
4027 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4029 case 3: /* use bits [43:32] of the address */
4030 vector = ((uc_addr->addr_bytes[4]) |
4031 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4033 default: /* Invalid mc_filter_type */
4037 /* vector can only be 12-bits or boundary will be exceeded */
4043 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4051 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4052 const uint32_t ixgbe_uta_bit_shift = 5;
4053 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4054 const uint32_t bit1 = 0x1;
4056 struct ixgbe_hw *hw =
4057 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4058 struct ixgbe_uta_info *uta_info =
4059 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4061 /* The UTA table only exists on 82599 hardware and newer */
4062 if (hw->mac.type < ixgbe_mac_82599EB)
4065 vector = ixgbe_uta_vector(hw,mac_addr);
4066 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4067 uta_shift = vector & ixgbe_uta_bit_mask;
4069 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4073 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4075 uta_info->uta_in_use++;
4076 reg_val |= (bit1 << uta_shift);
4077 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4079 uta_info->uta_in_use--;
4080 reg_val &= ~(bit1 << uta_shift);
4081 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4084 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4086 if (uta_info->uta_in_use > 0)
4087 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4088 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4090 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4096 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4099 struct ixgbe_hw *hw =
4100 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4101 struct ixgbe_uta_info *uta_info =
4102 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4104 /* The UTA table only exists on 82599 hardware and newer */
4105 if (hw->mac.type < ixgbe_mac_82599EB)
4109 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4110 uta_info->uta_shadow[i] = ~0;
4111 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4114 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4115 uta_info->uta_shadow[i] = 0;
4116 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4124 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4126 uint32_t new_val = orig_val;
4128 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4129 new_val |= IXGBE_VMOLR_AUPE;
4130 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4131 new_val |= IXGBE_VMOLR_ROMPE;
4132 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4133 new_val |= IXGBE_VMOLR_ROPE;
4134 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4135 new_val |= IXGBE_VMOLR_BAM;
4136 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4137 new_val |= IXGBE_VMOLR_MPE;
4143 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4144 uint16_t rx_mask, uint8_t on)
4148 struct ixgbe_hw *hw =
4149 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4150 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4152 if (hw->mac.type == ixgbe_mac_82598EB) {
4153 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4154 " on 82599 hardware and newer");
4157 if (ixgbe_vmdq_mode_check(hw) < 0)
4160 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4167 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4173 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4177 const uint8_t bit1 = 0x1;
4179 struct ixgbe_hw *hw =
4180 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4182 if (ixgbe_vmdq_mode_check(hw) < 0)
4185 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4186 reg = IXGBE_READ_REG(hw, addr);
4194 IXGBE_WRITE_REG(hw, addr,reg);
4200 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4204 const uint8_t bit1 = 0x1;
4206 struct ixgbe_hw *hw =
4207 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4209 if (ixgbe_vmdq_mode_check(hw) < 0)
4212 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4213 reg = IXGBE_READ_REG(hw, addr);
4221 IXGBE_WRITE_REG(hw, addr,reg);
4227 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4228 uint64_t pool_mask, uint8_t vlan_on)
4232 struct ixgbe_hw *hw =
4233 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4235 if (ixgbe_vmdq_mode_check(hw) < 0)
4237 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4238 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4239 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4247 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
4248 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
4249 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
4250 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
4251 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4252 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4253 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4256 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4257 struct rte_eth_mirror_conf *mirror_conf,
4258 uint8_t rule_id, uint8_t on)
4260 uint32_t mr_ctl,vlvf;
4261 uint32_t mp_lsb = 0;
4262 uint32_t mv_msb = 0;
4263 uint32_t mv_lsb = 0;
4264 uint32_t mp_msb = 0;
4267 uint64_t vlan_mask = 0;
4269 const uint8_t pool_mask_offset = 32;
4270 const uint8_t vlan_mask_offset = 32;
4271 const uint8_t dst_pool_offset = 8;
4272 const uint8_t rule_mr_offset = 4;
4273 const uint8_t mirror_rule_mask= 0x0F;
4275 struct ixgbe_mirror_info *mr_info =
4276 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4277 struct ixgbe_hw *hw =
4278 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4279 uint8_t mirror_type = 0;
4281 if (ixgbe_vmdq_mode_check(hw) < 0)
4284 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4287 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4288 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4289 mirror_conf->rule_type);
4293 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4294 mirror_type |= IXGBE_MRCTL_VLME;
4295 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4296 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4297 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4298 /* search vlan id related pool vlan filter index */
4299 reg_index = ixgbe_find_vlvf_slot(hw,
4300 mirror_conf->vlan.vlan_id[i]);
4303 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4304 if ((vlvf & IXGBE_VLVF_VIEN) &&
4305 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4306 mirror_conf->vlan.vlan_id[i]))
4307 vlan_mask |= (1ULL << reg_index);
4314 mv_lsb = vlan_mask & 0xFFFFFFFF;
4315 mv_msb = vlan_mask >> vlan_mask_offset;
4317 mr_info->mr_conf[rule_id].vlan.vlan_mask =
4318 mirror_conf->vlan.vlan_mask;
4319 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4320 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
4321 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4322 mirror_conf->vlan.vlan_id[i];
4327 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4328 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4329 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4334 * if enable pool mirror, write related pool mask register,if disable
4335 * pool mirror, clear PFMRVM register
4337 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4338 mirror_type |= IXGBE_MRCTL_VPME;
4340 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4341 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4342 mr_info->mr_conf[rule_id].pool_mask =
4343 mirror_conf->pool_mask;
4348 mr_info->mr_conf[rule_id].pool_mask = 0;
4351 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4352 mirror_type |= IXGBE_MRCTL_UPME;
4353 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4354 mirror_type |= IXGBE_MRCTL_DPME;
4356 /* read mirror control register and recalculate it */
4357 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4360 mr_ctl |= mirror_type;
4361 mr_ctl &= mirror_rule_mask;
4362 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4364 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4366 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4367 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4369 /* write mirrror control register */
4370 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4372 /* write pool mirrror control register */
4373 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4374 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4375 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4378 /* write VLAN mirrror control register */
4379 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4380 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4381 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4389 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4392 uint32_t lsb_val = 0;
4393 uint32_t msb_val = 0;
4394 const uint8_t rule_mr_offset = 4;
4396 struct ixgbe_hw *hw =
4397 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4398 struct ixgbe_mirror_info *mr_info =
4399 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4401 if (ixgbe_vmdq_mode_check(hw) < 0)
4404 memset(&mr_info->mr_conf[rule_id], 0,
4405 sizeof(struct rte_eth_mirror_conf));
4407 /* clear PFVMCTL register */
4408 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4410 /* clear pool mask register */
4411 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4412 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4414 /* clear vlan mask register */
4415 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4416 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4422 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4425 struct ixgbe_hw *hw =
4426 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4428 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4429 mask |= (1 << IXGBE_MISC_VEC_ID);
4430 RTE_SET_USED(queue_id);
4431 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4433 rte_intr_enable(&dev->pci_dev->intr_handle);
4439 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4442 struct ixgbe_hw *hw =
4443 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4445 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4446 mask &= ~(1 << IXGBE_MISC_VEC_ID);
4447 RTE_SET_USED(queue_id);
4448 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4454 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4457 struct ixgbe_hw *hw =
4458 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4459 struct ixgbe_interrupt *intr =
4460 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4462 if (queue_id < 16) {
4463 ixgbe_disable_intr(hw);
4464 intr->mask |= (1 << queue_id);
4465 ixgbe_enable_intr(dev);
4466 } else if (queue_id < 32) {
4467 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4468 mask &= (1 << queue_id);
4469 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4470 } else if (queue_id < 64) {
4471 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4472 mask &= (1 << (queue_id - 32));
4473 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4475 rte_intr_enable(&dev->pci_dev->intr_handle);
4481 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4484 struct ixgbe_hw *hw =
4485 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4486 struct ixgbe_interrupt *intr =
4487 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4489 if (queue_id < 16) {
4490 ixgbe_disable_intr(hw);
4491 intr->mask &= ~(1 << queue_id);
4492 ixgbe_enable_intr(dev);
4493 } else if (queue_id < 32) {
4494 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4495 mask &= ~(1 << queue_id);
4496 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4497 } else if (queue_id < 64) {
4498 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4499 mask &= ~(1 << (queue_id - 32));
4500 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4507 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4508 uint8_t queue, uint8_t msix_vector)
4512 if (direction == -1) {
4514 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4515 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4518 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4520 /* rx or tx cause */
4521 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4522 idx = ((16 * (queue & 1)) + (8 * direction));
4523 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4524 tmp &= ~(0xFF << idx);
4525 tmp |= (msix_vector << idx);
4526 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4531 * set the IVAR registers, mapping interrupt causes to vectors
4533 * pointer to ixgbe_hw struct
4535 * 0 for Rx, 1 for Tx, -1 for other causes
4537 * queue to map the corresponding interrupt to
4539 * the vector to map to the corresponding queue
4542 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4543 uint8_t queue, uint8_t msix_vector)
4547 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4548 if (hw->mac.type == ixgbe_mac_82598EB) {
4549 if (direction == -1)
4551 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4552 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4553 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4554 tmp |= (msix_vector << (8 * (queue & 0x3)));
4555 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4556 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4557 (hw->mac.type == ixgbe_mac_X540)) {
4558 if (direction == -1) {
4560 idx = ((queue & 1) * 8);
4561 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4562 tmp &= ~(0xFF << idx);
4563 tmp |= (msix_vector << idx);
4564 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4566 /* rx or tx causes */
4567 idx = ((16 * (queue & 1)) + (8 * direction));
4568 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4569 tmp &= ~(0xFF << idx);
4570 tmp |= (msix_vector << idx);
4571 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4577 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4579 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4580 struct ixgbe_hw *hw =
4581 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4583 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4585 /* won't configure msix register if no mapping is done
4586 * between intr vector and event fd.
4588 if (!rte_intr_dp_is_en(intr_handle))
4591 /* Configure all RX queues of VF */
4592 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4593 /* Force all queue use vector 0,
4594 * as IXGBE_VF_MAXMSIVECOTR = 1
4596 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4597 intr_handle->intr_vec[q_idx] = vector_idx;
4600 /* Configure VF other cause ivar */
4601 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4605 * Sets up the hardware to properly generate MSI-X interrupts
4607 * board private structure
4610 ixgbe_configure_msix(struct rte_eth_dev *dev)
4612 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4613 struct ixgbe_hw *hw =
4614 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4615 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4616 uint32_t vec = IXGBE_MISC_VEC_ID;
4620 /* won't configure msix register if no mapping is done
4621 * between intr vector and event fd
4623 if (!rte_intr_dp_is_en(intr_handle))
4626 if (rte_intr_allow_others(intr_handle))
4627 vec = base = IXGBE_RX_VEC_START;
4629 /* setup GPIE for MSI-x mode */
4630 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4631 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4632 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4633 /* auto clearing and auto setting corresponding bits in EIMS
4634 * when MSI-X interrupt is triggered
4636 if (hw->mac.type == ixgbe_mac_82598EB) {
4637 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4639 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4640 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4642 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4644 /* Populate the IVAR table and set the ITR values to the
4645 * corresponding register.
4647 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4649 /* by default, 1:1 mapping */
4650 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4651 intr_handle->intr_vec[queue_id] = vec;
4652 if (vec < base + intr_handle->nb_efd - 1)
4656 switch (hw->mac.type) {
4657 case ixgbe_mac_82598EB:
4658 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4661 case ixgbe_mac_82599EB:
4662 case ixgbe_mac_X540:
4663 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4668 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4669 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4671 /* set up to autoclear timer, and the vectors */
4672 mask = IXGBE_EIMS_ENABLE_MASK;
4673 mask &= ~(IXGBE_EIMS_OTHER |
4674 IXGBE_EIMS_MAILBOX |
4677 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4680 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4681 uint16_t queue_idx, uint16_t tx_rate)
4683 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4684 uint32_t rf_dec, rf_int;
4686 uint16_t link_speed = dev->data->dev_link.link_speed;
4688 if (queue_idx >= hw->mac.max_tx_queues)
4692 /* Calculate the rate factor values to set */
4693 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4694 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4695 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4697 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4698 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4699 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4700 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4706 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4707 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4710 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4711 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4712 IXGBE_MAX_JUMBO_FRAME_SIZE))
4713 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4714 IXGBE_MMW_SIZE_JUMBO_FRAME);
4716 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4717 IXGBE_MMW_SIZE_DEFAULT);
4719 /* Set RTTBCNRC of queue X */
4720 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4721 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4722 IXGBE_WRITE_FLUSH(hw);
4727 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4728 uint16_t tx_rate, uint64_t q_msk)
4730 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4731 struct ixgbe_vf_info *vfinfo =
4732 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4733 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4734 uint32_t queue_stride =
4735 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4736 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4737 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4738 uint16_t total_rate = 0;
4740 if (queue_end >= hw->mac.max_tx_queues)
4743 if (vfinfo != NULL) {
4744 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4747 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4749 total_rate += vfinfo[vf_idx].tx_rate[idx];
4754 /* Store tx_rate for this vf. */
4755 for (idx = 0; idx < nb_q_per_pool; idx++) {
4756 if (((uint64_t)0x1 << idx) & q_msk) {
4757 if (vfinfo[vf].tx_rate[idx] != tx_rate)
4758 vfinfo[vf].tx_rate[idx] = tx_rate;
4759 total_rate += tx_rate;
4763 if (total_rate > dev->data->dev_link.link_speed) {
4765 * Reset stored TX rate of the VF if it causes exceed
4768 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4772 /* Set RTTBCNRC of each queue/pool for vf X */
4773 for (; queue_idx <= queue_end; queue_idx++) {
4775 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4783 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4784 __attribute__((unused)) uint32_t index,
4785 __attribute__((unused)) uint32_t pool)
4787 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4791 * On a 82599 VF, adding again the same MAC addr is not an idempotent
4792 * operation. Trap this case to avoid exhausting the [very limited]
4793 * set of PF resources used to store VF MAC addresses.
4795 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4797 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4800 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4804 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4806 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4807 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4808 struct ether_addr *mac_addr;
4813 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4814 * not support the deletion of a given MAC address.
4815 * Instead, it imposes to delete all MAC addresses, then to add again
4816 * all MAC addresses with the exception of the one to be deleted.
4818 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4821 * Add again all MAC addresses, with the exception of the deleted one
4822 * and of the permanent MAC address.
4824 for (i = 0, mac_addr = dev->data->mac_addrs;
4825 i < hw->mac.num_rar_entries; i++, mac_addr++) {
4826 /* Skip the deleted MAC address */
4829 /* Skip NULL MAC addresses */
4830 if (is_zero_ether_addr(mac_addr))
4832 /* Skip the permanent MAC address */
4833 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4835 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4838 "Adding again MAC address "
4839 "%02x:%02x:%02x:%02x:%02x:%02x failed "
4841 mac_addr->addr_bytes[0],
4842 mac_addr->addr_bytes[1],
4843 mac_addr->addr_bytes[2],
4844 mac_addr->addr_bytes[3],
4845 mac_addr->addr_bytes[4],
4846 mac_addr->addr_bytes[5],
4852 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4854 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4856 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4859 #define MAC_TYPE_FILTER_SUP(type) do {\
4860 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4861 (type) != ixgbe_mac_X550)\
4866 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4867 struct rte_eth_syn_filter *filter,
4870 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4873 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4876 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4879 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4881 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4882 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4884 if (filter->hig_pri)
4885 synqf |= IXGBE_SYN_FILTER_SYNQFP;
4887 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4889 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4891 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4893 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4894 IXGBE_WRITE_FLUSH(hw);
4899 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4900 struct rte_eth_syn_filter *filter)
4902 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4903 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4905 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4906 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4907 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4914 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4915 enum rte_filter_op filter_op,
4918 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4921 MAC_TYPE_FILTER_SUP(hw->mac.type);
4923 if (filter_op == RTE_ETH_FILTER_NOP)
4927 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4932 switch (filter_op) {
4933 case RTE_ETH_FILTER_ADD:
4934 ret = ixgbe_syn_filter_set(dev,
4935 (struct rte_eth_syn_filter *)arg,
4938 case RTE_ETH_FILTER_DELETE:
4939 ret = ixgbe_syn_filter_set(dev,
4940 (struct rte_eth_syn_filter *)arg,
4943 case RTE_ETH_FILTER_GET:
4944 ret = ixgbe_syn_filter_get(dev,
4945 (struct rte_eth_syn_filter *)arg);
4948 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
4957 static inline enum ixgbe_5tuple_protocol
4958 convert_protocol_type(uint8_t protocol_value)
4960 if (protocol_value == IPPROTO_TCP)
4961 return IXGBE_FILTER_PROTOCOL_TCP;
4962 else if (protocol_value == IPPROTO_UDP)
4963 return IXGBE_FILTER_PROTOCOL_UDP;
4964 else if (protocol_value == IPPROTO_SCTP)
4965 return IXGBE_FILTER_PROTOCOL_SCTP;
4967 return IXGBE_FILTER_PROTOCOL_NONE;
4971 * add a 5tuple filter
4974 * dev: Pointer to struct rte_eth_dev.
4975 * index: the index the filter allocates.
4976 * filter: ponter to the filter that will be added.
4977 * rx_queue: the queue id the filter assigned to.
4980 * - On success, zero.
4981 * - On failure, a negative value.
4984 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
4985 struct ixgbe_5tuple_filter *filter)
4987 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4988 struct ixgbe_filter_info *filter_info =
4989 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4991 uint32_t ftqf, sdpqf;
4992 uint32_t l34timir = 0;
4993 uint8_t mask = 0xff;
4996 * look for an unused 5tuple filter index,
4997 * and insert the filter to list.
4999 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5000 idx = i / (sizeof(uint32_t) * NBBY);
5001 shift = i % (sizeof(uint32_t) * NBBY);
5002 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5003 filter_info->fivetuple_mask[idx] |= 1 << shift;
5005 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5011 if (i >= IXGBE_MAX_FTQF_FILTERS) {
5012 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5016 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5017 IXGBE_SDPQF_DSTPORT_SHIFT);
5018 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5020 ftqf = (uint32_t)(filter->filter_info.proto &
5021 IXGBE_FTQF_PROTOCOL_MASK);
5022 ftqf |= (uint32_t)((filter->filter_info.priority &
5023 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5024 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5025 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5026 if (filter->filter_info.dst_ip_mask == 0)
5027 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5028 if (filter->filter_info.src_port_mask == 0)
5029 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5030 if (filter->filter_info.dst_port_mask == 0)
5031 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5032 if (filter->filter_info.proto_mask == 0)
5033 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5034 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5035 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5036 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5038 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5039 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5040 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5041 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5043 l34timir |= IXGBE_L34T_IMIR_RESERVE;
5044 l34timir |= (uint32_t)(filter->queue <<
5045 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5046 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5051 * remove a 5tuple filter
5054 * dev: Pointer to struct rte_eth_dev.
5055 * filter: the pointer of the filter will be removed.
5058 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5059 struct ixgbe_5tuple_filter *filter)
5061 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5062 struct ixgbe_filter_info *filter_info =
5063 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5064 uint16_t index = filter->index;
5066 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5067 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5068 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5071 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5072 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5073 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5074 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5075 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5079 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5081 struct ixgbe_hw *hw;
5082 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5084 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5086 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5089 /* refuse mtu that requires the support of scattered packets when this
5090 * feature has not been enabled before. */
5091 if (!dev->data->scattered_rx &&
5092 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5093 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5097 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5098 * request of the version 2.0 of the mailbox API.
5099 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5100 * of the mailbox API.
5101 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5102 * prior to 3.11.33 which contains the following change:
5103 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5105 ixgbevf_rlpml_set_vf(hw, max_frame);
5107 /* update max frame size */
5108 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5112 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
5113 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5117 static inline struct ixgbe_5tuple_filter *
5118 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5119 struct ixgbe_5tuple_filter_info *key)
5121 struct ixgbe_5tuple_filter *it;
5123 TAILQ_FOREACH(it, filter_list, entries) {
5124 if (memcmp(key, &it->filter_info,
5125 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5132 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5134 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5135 struct ixgbe_5tuple_filter_info *filter_info)
5137 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5138 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5139 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5142 switch (filter->dst_ip_mask) {
5144 filter_info->dst_ip_mask = 0;
5145 filter_info->dst_ip = filter->dst_ip;
5148 filter_info->dst_ip_mask = 1;
5151 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5155 switch (filter->src_ip_mask) {
5157 filter_info->src_ip_mask = 0;
5158 filter_info->src_ip = filter->src_ip;
5161 filter_info->src_ip_mask = 1;
5164 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5168 switch (filter->dst_port_mask) {
5170 filter_info->dst_port_mask = 0;
5171 filter_info->dst_port = filter->dst_port;
5174 filter_info->dst_port_mask = 1;
5177 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5181 switch (filter->src_port_mask) {
5183 filter_info->src_port_mask = 0;
5184 filter_info->src_port = filter->src_port;
5187 filter_info->src_port_mask = 1;
5190 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5194 switch (filter->proto_mask) {
5196 filter_info->proto_mask = 0;
5197 filter_info->proto =
5198 convert_protocol_type(filter->proto);
5201 filter_info->proto_mask = 1;
5204 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5208 filter_info->priority = (uint8_t)filter->priority;
5213 * add or delete a ntuple filter
5216 * dev: Pointer to struct rte_eth_dev.
5217 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5218 * add: if true, add filter, if false, remove filter
5221 * - On success, zero.
5222 * - On failure, a negative value.
5225 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5226 struct rte_eth_ntuple_filter *ntuple_filter,
5229 struct ixgbe_filter_info *filter_info =
5230 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5231 struct ixgbe_5tuple_filter_info filter_5tuple;
5232 struct ixgbe_5tuple_filter *filter;
5235 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5236 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5240 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5241 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5245 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5247 if (filter != NULL && add) {
5248 PMD_DRV_LOG(ERR, "filter exists.");
5251 if (filter == NULL && !add) {
5252 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5257 filter = rte_zmalloc("ixgbe_5tuple_filter",
5258 sizeof(struct ixgbe_5tuple_filter), 0);
5261 (void)rte_memcpy(&filter->filter_info,
5263 sizeof(struct ixgbe_5tuple_filter_info));
5264 filter->queue = ntuple_filter->queue;
5265 ret = ixgbe_add_5tuple_filter(dev, filter);
5271 ixgbe_remove_5tuple_filter(dev, filter);
5277 * get a ntuple filter
5280 * dev: Pointer to struct rte_eth_dev.
5281 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5284 * - On success, zero.
5285 * - On failure, a negative value.
5288 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5289 struct rte_eth_ntuple_filter *ntuple_filter)
5291 struct ixgbe_filter_info *filter_info =
5292 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5293 struct ixgbe_5tuple_filter_info filter_5tuple;
5294 struct ixgbe_5tuple_filter *filter;
5297 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5298 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5302 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5303 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5307 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5309 if (filter == NULL) {
5310 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5313 ntuple_filter->queue = filter->queue;
5318 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5319 * @dev: pointer to rte_eth_dev structure
5320 * @filter_op:operation will be taken.
5321 * @arg: a pointer to specific structure corresponding to the filter_op
5324 * - On success, zero.
5325 * - On failure, a negative value.
5328 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5329 enum rte_filter_op filter_op,
5332 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5335 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5337 if (filter_op == RTE_ETH_FILTER_NOP)
5341 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5346 switch (filter_op) {
5347 case RTE_ETH_FILTER_ADD:
5348 ret = ixgbe_add_del_ntuple_filter(dev,
5349 (struct rte_eth_ntuple_filter *)arg,
5352 case RTE_ETH_FILTER_DELETE:
5353 ret = ixgbe_add_del_ntuple_filter(dev,
5354 (struct rte_eth_ntuple_filter *)arg,
5357 case RTE_ETH_FILTER_GET:
5358 ret = ixgbe_get_ntuple_filter(dev,
5359 (struct rte_eth_ntuple_filter *)arg);
5362 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5370 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5375 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5376 if (filter_info->ethertype_filters[i] == ethertype &&
5377 (filter_info->ethertype_mask & (1 << i)))
5384 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5389 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5390 if (!(filter_info->ethertype_mask & (1 << i))) {
5391 filter_info->ethertype_mask |= 1 << i;
5392 filter_info->ethertype_filters[i] = ethertype;
5400 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5403 if (idx >= IXGBE_MAX_ETQF_FILTERS)
5405 filter_info->ethertype_mask &= ~(1 << idx);
5406 filter_info->ethertype_filters[idx] = 0;
5411 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5412 struct rte_eth_ethertype_filter *filter,
5415 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5416 struct ixgbe_filter_info *filter_info =
5417 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5422 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5425 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5426 filter->ether_type == ETHER_TYPE_IPv6) {
5427 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5428 " ethertype filter.", filter->ether_type);
5432 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5433 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5436 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5437 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5441 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5442 if (ret >= 0 && add) {
5443 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5444 filter->ether_type);
5447 if (ret < 0 && !add) {
5448 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5449 filter->ether_type);
5454 ret = ixgbe_ethertype_filter_insert(filter_info,
5455 filter->ether_type);
5457 PMD_DRV_LOG(ERR, "ethertype filters are full.");
5460 etqf = IXGBE_ETQF_FILTER_EN;
5461 etqf |= (uint32_t)filter->ether_type;
5462 etqs |= (uint32_t)((filter->queue <<
5463 IXGBE_ETQS_RX_QUEUE_SHIFT) &
5464 IXGBE_ETQS_RX_QUEUE);
5465 etqs |= IXGBE_ETQS_QUEUE_EN;
5467 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5471 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5472 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5473 IXGBE_WRITE_FLUSH(hw);
5479 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5480 struct rte_eth_ethertype_filter *filter)
5482 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5483 struct ixgbe_filter_info *filter_info =
5484 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5485 uint32_t etqf, etqs;
5488 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5490 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5491 filter->ether_type);
5495 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5496 if (etqf & IXGBE_ETQF_FILTER_EN) {
5497 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5498 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5500 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5501 IXGBE_ETQS_RX_QUEUE_SHIFT;
5508 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5509 * @dev: pointer to rte_eth_dev structure
5510 * @filter_op:operation will be taken.
5511 * @arg: a pointer to specific structure corresponding to the filter_op
5514 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5515 enum rte_filter_op filter_op,
5518 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5521 MAC_TYPE_FILTER_SUP(hw->mac.type);
5523 if (filter_op == RTE_ETH_FILTER_NOP)
5527 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5532 switch (filter_op) {
5533 case RTE_ETH_FILTER_ADD:
5534 ret = ixgbe_add_del_ethertype_filter(dev,
5535 (struct rte_eth_ethertype_filter *)arg,
5538 case RTE_ETH_FILTER_DELETE:
5539 ret = ixgbe_add_del_ethertype_filter(dev,
5540 (struct rte_eth_ethertype_filter *)arg,
5543 case RTE_ETH_FILTER_GET:
5544 ret = ixgbe_get_ethertype_filter(dev,
5545 (struct rte_eth_ethertype_filter *)arg);
5548 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5556 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5557 enum rte_filter_type filter_type,
5558 enum rte_filter_op filter_op,
5563 switch (filter_type) {
5564 case RTE_ETH_FILTER_NTUPLE:
5565 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5567 case RTE_ETH_FILTER_ETHERTYPE:
5568 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5570 case RTE_ETH_FILTER_SYN:
5571 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5573 case RTE_ETH_FILTER_FDIR:
5574 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5577 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5586 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5587 u8 **mc_addr_ptr, u32 *vmdq)
5592 mc_addr = *mc_addr_ptr;
5593 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5598 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5599 struct ether_addr *mc_addr_set,
5600 uint32_t nb_mc_addr)
5602 struct ixgbe_hw *hw;
5605 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5606 mc_addr_list = (u8 *)mc_addr_set;
5607 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5608 ixgbe_dev_addr_list_itr, TRUE);
5612 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5614 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5618 /* Enable system time for platforms where it isn't on by default. */
5619 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5620 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5621 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5623 /* Start incrementing the register used to timestamp PTP packets. */
5624 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
5626 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5627 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5629 IXGBE_ETQF_FILTER_EN |
5632 /* Enable timestamping of received PTP packets. */
5633 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5634 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5635 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5637 /* Enable timestamping of transmitted PTP packets. */
5638 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5639 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5640 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5646 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5648 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5651 /* Disable timestamping of transmitted PTP packets. */
5652 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5653 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5654 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5656 /* Disable timestamping of received PTP packets. */
5657 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5658 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5659 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5661 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5662 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5664 /* Stop incrementating the System Time registers. */
5665 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5671 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5672 struct timespec *timestamp,
5673 uint32_t flags __rte_unused)
5675 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5676 uint32_t tsync_rxctl;
5680 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5681 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5684 rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5685 rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
5687 timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
5688 timestamp->tv_nsec = 0;
5694 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5695 struct timespec *timestamp)
5697 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5698 uint32_t tsync_txctl;
5702 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5703 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5706 tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5707 tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
5709 timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
5710 timestamp->tv_nsec = 0;
5716 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5718 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5721 const struct reg_info *reg_group;
5722 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5723 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5725 while ((reg_group = reg_set[g_ind++]))
5726 count += ixgbe_regs_group_count(reg_group);
5732 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5736 const struct reg_info *reg_group;
5738 while ((reg_group = ixgbevf_regs[g_ind++]))
5739 count += ixgbe_regs_group_count(reg_group);
5745 ixgbe_get_regs(struct rte_eth_dev *dev,
5746 struct rte_dev_reg_info *regs)
5748 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5749 uint32_t *data = regs->data;
5752 const struct reg_info *reg_group;
5753 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5754 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5756 /* Support only full register dump */
5757 if ((regs->length == 0) ||
5758 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
5759 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5761 while ((reg_group = reg_set[g_ind++]))
5762 count += ixgbe_read_regs_group(dev, &data[count],
5771 ixgbevf_get_regs(struct rte_eth_dev *dev,
5772 struct rte_dev_reg_info *regs)
5774 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5775 uint32_t *data = regs->data;
5778 const struct reg_info *reg_group;
5780 /* Support only full register dump */
5781 if ((regs->length == 0) ||
5782 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
5783 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5785 while ((reg_group = ixgbevf_regs[g_ind++]))
5786 count += ixgbe_read_regs_group(dev, &data[count],
5795 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
5797 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5799 /* Return unit is byte count */
5800 return hw->eeprom.word_size * 2;
5804 ixgbe_get_eeprom(struct rte_eth_dev *dev,
5805 struct rte_dev_eeprom_info *in_eeprom)
5807 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5808 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5809 uint16_t *data = in_eeprom->data;
5812 first = in_eeprom->offset >> 1;
5813 length = in_eeprom->length >> 1;
5814 if ((first > hw->eeprom.word_size) ||
5815 ((first + length) > hw->eeprom.word_size))
5818 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5820 return eeprom->ops.read_buffer(hw, first, length, data);
5824 ixgbe_set_eeprom(struct rte_eth_dev *dev,
5825 struct rte_dev_eeprom_info *in_eeprom)
5827 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5828 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5829 uint16_t *data = in_eeprom->data;
5832 first = in_eeprom->offset >> 1;
5833 length = in_eeprom->length >> 1;
5834 if ((first > hw->eeprom.word_size) ||
5835 ((first + length) > hw->eeprom.word_size))
5838 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5840 return eeprom->ops.write_buffer(hw, first, length, data);
5844 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
5846 case ixgbe_mac_X550:
5847 case ixgbe_mac_X550EM_x:
5848 return ETH_RSS_RETA_SIZE_512;
5849 case ixgbe_mac_X550_vf:
5850 case ixgbe_mac_X550EM_x_vf:
5851 return ETH_RSS_RETA_SIZE_64;
5853 return ETH_RSS_RETA_SIZE_128;
5858 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
5860 case ixgbe_mac_X550:
5861 case ixgbe_mac_X550EM_x:
5862 if (reta_idx < ETH_RSS_RETA_SIZE_128)
5863 return IXGBE_RETA(reta_idx >> 2);
5865 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
5866 case ixgbe_mac_X550_vf:
5867 case ixgbe_mac_X550EM_x_vf:
5868 return IXGBE_VFRETA(reta_idx >> 2);
5870 return IXGBE_RETA(reta_idx >> 2);
5875 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
5877 case ixgbe_mac_X550_vf:
5878 case ixgbe_mac_X550EM_x_vf:
5879 return IXGBE_VFMRQC;
5886 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
5888 case ixgbe_mac_X550_vf:
5889 case ixgbe_mac_X550EM_x_vf:
5890 return IXGBE_VFRSSRK(i);
5892 return IXGBE_RSSRK(i);
5897 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
5899 case ixgbe_mac_82599_vf:
5900 case ixgbe_mac_X540_vf:
5908 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
5909 struct rte_eth_dcb_info *dcb_info)
5911 struct ixgbe_dcb_config *dcb_config =
5912 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
5913 struct ixgbe_dcb_tc_config *tc;
5916 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
5917 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
5919 dcb_info->nb_tcs = 1;
5921 if (dcb_config->vt_mode) { /* vt is enabled*/
5922 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
5923 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
5924 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
5925 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
5926 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
5927 for (j = 0; j < dcb_info->nb_tcs; j++) {
5928 dcb_info->tc_queue.tc_rxq[i][j].base =
5929 i * dcb_info->nb_tcs + j;
5930 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
5931 dcb_info->tc_queue.tc_txq[i][j].base =
5932 i * dcb_info->nb_tcs + j;
5933 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
5936 } else { /* vt is disabled*/
5937 struct rte_eth_dcb_rx_conf *rx_conf =
5938 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
5939 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
5940 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
5941 if (dcb_info->nb_tcs == ETH_4_TCS) {
5942 for (i = 0; i < dcb_info->nb_tcs; i++) {
5943 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
5944 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
5946 dcb_info->tc_queue.tc_txq[0][0].base = 0;
5947 dcb_info->tc_queue.tc_txq[0][1].base = 64;
5948 dcb_info->tc_queue.tc_txq[0][2].base = 96;
5949 dcb_info->tc_queue.tc_txq[0][3].base = 112;
5950 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
5951 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
5952 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
5953 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
5954 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
5955 for (i = 0; i < dcb_info->nb_tcs; i++) {
5956 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
5957 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
5959 dcb_info->tc_queue.tc_txq[0][0].base = 0;
5960 dcb_info->tc_queue.tc_txq[0][1].base = 32;
5961 dcb_info->tc_queue.tc_txq[0][2].base = 64;
5962 dcb_info->tc_queue.tc_txq[0][3].base = 80;
5963 dcb_info->tc_queue.tc_txq[0][4].base = 96;
5964 dcb_info->tc_queue.tc_txq[0][5].base = 104;
5965 dcb_info->tc_queue.tc_txq[0][6].base = 112;
5966 dcb_info->tc_queue.tc_txq[0][7].base = 120;
5967 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
5968 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
5969 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
5970 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
5971 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
5972 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
5973 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
5974 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
5977 for (i = 0; i < dcb_info->nb_tcs; i++) {
5978 tc = &dcb_config->tc_config[i];
5979 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
5984 static struct rte_driver rte_ixgbe_driver = {
5986 .init = rte_ixgbe_pmd_init,
5989 static struct rte_driver rte_ixgbevf_driver = {
5991 .init = rte_ixgbevf_pmd_init,
5994 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
5995 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);