4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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19 * from this software without specific prior written permission.
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34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
64 #include "ixgbe_logs.h"
65 #include "base/ixgbe_api.h"
66 #include "base/ixgbe_vf.h"
67 #include "base/ixgbe_common.h"
68 #include "ixgbe_ethdev.h"
69 #include "ixgbe_bypass.h"
70 #include "ixgbe_rxtx.h"
71 #include "base/ixgbe_type.h"
72 #include "base/ixgbe_phy.h"
73 #include "ixgbe_regs.h"
76 * High threshold controlling when to start sending XOFF frames. Must be at
77 * least 8 bytes less than receive packet buffer size. This value is in units
80 #define IXGBE_FC_HI 0x80
83 * Low threshold controlling when to start sending XON frames. This value is
84 * in units of 1024 bytes.
86 #define IXGBE_FC_LO 0x40
88 /* Default minimum inter-interrupt interval for EITR configuration */
89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
91 /* Timer value included in XOFF frames. */
92 #define IXGBE_FC_PAUSE 0x680
94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
95 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
96 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
98 #define IXGBE_MMW_SIZE_DEFAULT 0x4
99 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
100 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
103 * Default values for RX/TX configuration
105 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
106 #define IXGBE_DEFAULT_RX_PTHRESH 8
107 #define IXGBE_DEFAULT_RX_HTHRESH 8
108 #define IXGBE_DEFAULT_RX_WTHRESH 0
110 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
111 #define IXGBE_DEFAULT_TX_PTHRESH 32
112 #define IXGBE_DEFAULT_TX_HTHRESH 0
113 #define IXGBE_DEFAULT_TX_WTHRESH 0
114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
116 /* Bit shift and mask */
117 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
118 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
119 #define IXGBE_8_BIT_WIDTH CHAR_BIT
120 #define IXGBE_8_BIT_MASK UINT8_MAX
122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
126 #define IXGBE_HKEY_MAX_INDEX 10
128 /* Additional timesync values. */
129 #define NSEC_PER_SEC 1000000000L
130 #define IXGBE_INCVAL_10GB 0x66666666
131 #define IXGBE_INCVAL_1GB 0x40000000
132 #define IXGBE_INCVAL_100 0x50000000
133 #define IXGBE_INCVAL_SHIFT_10GB 28
134 #define IXGBE_INCVAL_SHIFT_1GB 24
135 #define IXGBE_INCVAL_SHIFT_100 21
136 #define IXGBE_INCVAL_SHIFT_82599 7
137 #define IXGBE_INCPER_SHIFT_82599 24
139 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
141 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
143 #define DEFAULT_ETAG_ETYPE 0x893f
144 #define IXGBE_ETAG_ETYPE 0x00005084
145 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
146 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
147 #define IXGBE_RAH_ADTYPE 0x40000000
148 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
149 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
152 #define IXGBE_QDE_STRIP_TAG 0x00000004
154 enum ixgbevf_xcast_modes {
155 IXGBEVF_XCAST_MODE_NONE = 0,
156 IXGBEVF_XCAST_MODE_MULTI,
157 IXGBEVF_XCAST_MODE_ALLMULTI,
160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
162 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
163 static int ixgbe_dev_start(struct rte_eth_dev *dev);
164 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
165 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
166 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
167 static void ixgbe_dev_close(struct rte_eth_dev *dev);
168 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
169 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
170 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
171 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
172 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
173 int wait_to_complete);
174 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
175 struct rte_eth_stats *stats);
176 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
177 struct rte_eth_xstats *xstats, unsigned n);
178 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
179 struct rte_eth_xstats *xstats, unsigned n);
180 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
181 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
182 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
186 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
187 struct rte_eth_dev_info *dev_info);
188 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
189 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
190 struct rte_eth_dev_info *dev_info);
191 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
193 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
194 uint16_t vlan_id, int on);
195 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
196 enum rte_vlan_type vlan_type,
198 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
199 uint16_t queue, bool on);
200 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
202 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
203 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
204 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
205 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
206 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
208 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
209 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
210 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
211 struct rte_eth_fc_conf *fc_conf);
212 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
213 struct rte_eth_fc_conf *fc_conf);
214 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
215 struct rte_eth_pfc_conf *pfc_conf);
216 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
217 struct rte_eth_rss_reta_entry64 *reta_conf,
219 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
220 struct rte_eth_rss_reta_entry64 *reta_conf,
222 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
223 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
224 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
225 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
226 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
227 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
229 static void ixgbe_dev_interrupt_delayed_handler(void *param);
230 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
231 uint32_t index, uint32_t pool);
232 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
233 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
234 struct ether_addr *mac_addr);
235 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
237 /* For Virtual Function support */
238 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
239 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
240 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
241 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
242 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
243 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
244 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
245 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
246 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
247 struct rte_eth_stats *stats);
248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
250 uint16_t vlan_id, int on);
251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
252 uint16_t queue, int on);
253 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
254 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
255 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
257 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
259 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
260 uint8_t queue, uint8_t msix_vector);
261 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
262 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
263 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
265 /* For Eth VMDQ APIs support */
266 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
267 ether_addr* mac_addr,uint8_t on);
268 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
269 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
270 uint16_t rx_mask, uint8_t on);
271 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
272 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
273 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
274 uint64_t pool_mask,uint8_t vlan_on);
275 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
276 struct rte_eth_mirror_conf *mirror_conf,
277 uint8_t rule_id, uint8_t on);
278 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
280 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
282 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
284 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
285 uint8_t queue, uint8_t msix_vector);
286 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
288 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
289 uint16_t queue_idx, uint16_t tx_rate);
290 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
291 uint16_t tx_rate, uint64_t q_msk);
293 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
294 struct ether_addr *mac_addr,
295 uint32_t index, uint32_t pool);
296 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
297 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
298 struct ether_addr *mac_addr);
299 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
300 struct rte_eth_syn_filter *filter,
302 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
303 struct rte_eth_syn_filter *filter);
304 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
305 enum rte_filter_op filter_op,
307 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
308 struct ixgbe_5tuple_filter *filter);
309 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
310 struct ixgbe_5tuple_filter *filter);
311 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
312 struct rte_eth_ntuple_filter *filter,
314 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
315 enum rte_filter_op filter_op,
317 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
318 struct rte_eth_ntuple_filter *filter);
319 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
320 struct rte_eth_ethertype_filter *filter,
322 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
323 enum rte_filter_op filter_op,
325 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
326 struct rte_eth_ethertype_filter *filter);
327 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
328 enum rte_filter_type filter_type,
329 enum rte_filter_op filter_op,
331 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
333 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
334 struct ether_addr *mc_addr_set,
335 uint32_t nb_mc_addr);
336 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
337 struct rte_eth_dcb_info *dcb_info);
339 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
340 static int ixgbe_get_regs(struct rte_eth_dev *dev,
341 struct rte_dev_reg_info *regs);
342 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
343 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
344 struct rte_dev_eeprom_info *eeprom);
345 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
346 struct rte_dev_eeprom_info *eeprom);
348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
350 struct rte_dev_reg_info *regs);
352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
355 struct timespec *timestamp,
357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
358 struct timespec *timestamp);
359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
361 struct timespec *timestamp);
362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
363 const struct timespec *timestamp);
365 static int ixgbe_dev_l2_tunnel_eth_type_conf
366 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
367 static int ixgbe_dev_l2_tunnel_offload_set
368 (struct rte_eth_dev *dev,
369 struct rte_eth_l2_tunnel_conf *l2_tunnel,
372 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
373 enum rte_filter_op filter_op,
376 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
377 struct rte_eth_udp_tunnel *udp_tunnel);
378 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
379 struct rte_eth_udp_tunnel *udp_tunnel);
382 * Define VF Stats MACRO for Non "cleared on read" register
384 #define UPDATE_VF_STAT(reg, last, cur) \
386 uint32_t latest = IXGBE_READ_REG(hw, reg); \
387 cur += (latest - last) & UINT_MAX; \
391 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
393 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
394 u64 new_msb = IXGBE_READ_REG(hw, msb); \
395 u64 latest = ((new_msb << 32) | new_lsb); \
396 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
400 #define IXGBE_SET_HWSTRIP(h, q) do{\
401 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
402 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
403 (h)->bitmap[idx] |= 1 << bit;\
406 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
407 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
408 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
409 (h)->bitmap[idx] &= ~(1 << bit);\
412 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
413 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
414 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
415 (r) = (h)->bitmap[idx] >> bit & 1;\
419 * The set of PCI devices this driver supports
421 static const struct rte_pci_id pci_id_ixgbe_map[] = {
423 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
424 #include "rte_pci_dev_ids.h"
426 { .vendor_id = 0, /* sentinel */ },
431 * The set of PCI devices this driver supports (for 82599 VF)
433 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
435 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
436 #include "rte_pci_dev_ids.h"
437 { .vendor_id = 0, /* sentinel */ },
441 static const struct rte_eth_desc_lim rx_desc_lim = {
442 .nb_max = IXGBE_MAX_RING_DESC,
443 .nb_min = IXGBE_MIN_RING_DESC,
444 .nb_align = IXGBE_RXD_ALIGN,
447 static const struct rte_eth_desc_lim tx_desc_lim = {
448 .nb_max = IXGBE_MAX_RING_DESC,
449 .nb_min = IXGBE_MIN_RING_DESC,
450 .nb_align = IXGBE_TXD_ALIGN,
453 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
454 .dev_configure = ixgbe_dev_configure,
455 .dev_start = ixgbe_dev_start,
456 .dev_stop = ixgbe_dev_stop,
457 .dev_set_link_up = ixgbe_dev_set_link_up,
458 .dev_set_link_down = ixgbe_dev_set_link_down,
459 .dev_close = ixgbe_dev_close,
460 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
461 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
462 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
463 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
464 .link_update = ixgbe_dev_link_update,
465 .stats_get = ixgbe_dev_stats_get,
466 .xstats_get = ixgbe_dev_xstats_get,
467 .stats_reset = ixgbe_dev_stats_reset,
468 .xstats_reset = ixgbe_dev_xstats_reset,
469 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
470 .dev_infos_get = ixgbe_dev_info_get,
471 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
472 .mtu_set = ixgbe_dev_mtu_set,
473 .vlan_filter_set = ixgbe_vlan_filter_set,
474 .vlan_tpid_set = ixgbe_vlan_tpid_set,
475 .vlan_offload_set = ixgbe_vlan_offload_set,
476 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
477 .rx_queue_start = ixgbe_dev_rx_queue_start,
478 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
479 .tx_queue_start = ixgbe_dev_tx_queue_start,
480 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
481 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
482 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
483 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
484 .rx_queue_release = ixgbe_dev_rx_queue_release,
485 .rx_queue_count = ixgbe_dev_rx_queue_count,
486 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
487 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
488 .tx_queue_release = ixgbe_dev_tx_queue_release,
489 .dev_led_on = ixgbe_dev_led_on,
490 .dev_led_off = ixgbe_dev_led_off,
491 .flow_ctrl_get = ixgbe_flow_ctrl_get,
492 .flow_ctrl_set = ixgbe_flow_ctrl_set,
493 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
494 .mac_addr_add = ixgbe_add_rar,
495 .mac_addr_remove = ixgbe_remove_rar,
496 .mac_addr_set = ixgbe_set_default_mac_addr,
497 .uc_hash_table_set = ixgbe_uc_hash_table_set,
498 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
499 .mirror_rule_set = ixgbe_mirror_rule_set,
500 .mirror_rule_reset = ixgbe_mirror_rule_reset,
501 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
502 .set_vf_rx = ixgbe_set_pool_rx,
503 .set_vf_tx = ixgbe_set_pool_tx,
504 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
505 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
506 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
507 .reta_update = ixgbe_dev_rss_reta_update,
508 .reta_query = ixgbe_dev_rss_reta_query,
509 #ifdef RTE_NIC_BYPASS
510 .bypass_init = ixgbe_bypass_init,
511 .bypass_state_set = ixgbe_bypass_state_store,
512 .bypass_state_show = ixgbe_bypass_state_show,
513 .bypass_event_set = ixgbe_bypass_event_store,
514 .bypass_event_show = ixgbe_bypass_event_show,
515 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
516 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
517 .bypass_ver_show = ixgbe_bypass_ver_show,
518 .bypass_wd_reset = ixgbe_bypass_wd_reset,
519 #endif /* RTE_NIC_BYPASS */
520 .rss_hash_update = ixgbe_dev_rss_hash_update,
521 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
522 .filter_ctrl = ixgbe_dev_filter_ctrl,
523 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
524 .rxq_info_get = ixgbe_rxq_info_get,
525 .txq_info_get = ixgbe_txq_info_get,
526 .timesync_enable = ixgbe_timesync_enable,
527 .timesync_disable = ixgbe_timesync_disable,
528 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
529 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
530 .get_reg_length = ixgbe_get_reg_length,
531 .get_reg = ixgbe_get_regs,
532 .get_eeprom_length = ixgbe_get_eeprom_length,
533 .get_eeprom = ixgbe_get_eeprom,
534 .set_eeprom = ixgbe_set_eeprom,
535 .get_dcb_info = ixgbe_dev_get_dcb_info,
536 .timesync_adjust_time = ixgbe_timesync_adjust_time,
537 .timesync_read_time = ixgbe_timesync_read_time,
538 .timesync_write_time = ixgbe_timesync_write_time,
539 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
540 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
541 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
542 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
546 * dev_ops for virtual function, bare necessities for basic vf
547 * operation have been implemented
549 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
550 .dev_configure = ixgbevf_dev_configure,
551 .dev_start = ixgbevf_dev_start,
552 .dev_stop = ixgbevf_dev_stop,
553 .link_update = ixgbe_dev_link_update,
554 .stats_get = ixgbevf_dev_stats_get,
555 .xstats_get = ixgbevf_dev_xstats_get,
556 .stats_reset = ixgbevf_dev_stats_reset,
557 .xstats_reset = ixgbevf_dev_stats_reset,
558 .dev_close = ixgbevf_dev_close,
559 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
560 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
561 .dev_infos_get = ixgbevf_dev_info_get,
562 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
563 .mtu_set = ixgbevf_dev_set_mtu,
564 .vlan_filter_set = ixgbevf_vlan_filter_set,
565 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
566 .vlan_offload_set = ixgbevf_vlan_offload_set,
567 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
568 .rx_queue_release = ixgbe_dev_rx_queue_release,
569 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
570 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
571 .tx_queue_release = ixgbe_dev_tx_queue_release,
572 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
573 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
574 .mac_addr_add = ixgbevf_add_mac_addr,
575 .mac_addr_remove = ixgbevf_remove_mac_addr,
576 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
577 .rxq_info_get = ixgbe_rxq_info_get,
578 .txq_info_get = ixgbe_txq_info_get,
579 .mac_addr_set = ixgbevf_set_default_mac_addr,
580 .get_reg_length = ixgbevf_get_reg_length,
581 .get_reg = ixgbevf_get_regs,
582 .reta_update = ixgbe_dev_rss_reta_update,
583 .reta_query = ixgbe_dev_rss_reta_query,
584 .rss_hash_update = ixgbe_dev_rss_hash_update,
585 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
588 /* store statistics names and its offset in stats structure */
589 struct rte_ixgbe_xstats_name_off {
590 char name[RTE_ETH_XSTATS_NAME_SIZE];
594 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
595 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
596 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
597 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
598 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
599 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
600 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
601 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
602 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
603 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
604 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
605 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
606 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
607 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
608 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
609 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
611 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
613 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
614 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
615 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
616 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
617 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
618 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
619 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
620 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
621 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
622 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
623 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
624 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
625 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
626 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
627 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
628 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
629 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
631 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
633 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
634 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
635 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
636 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
638 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
640 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
642 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
644 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
646 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
648 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
651 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
652 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
653 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
655 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
656 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
657 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
658 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
659 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
661 {"rx_fcoe_no_direct_data_placement_ext_buff",
662 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
664 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
666 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
668 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
670 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
672 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
675 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
676 sizeof(rte_ixgbe_stats_strings[0]))
678 /* Per-queue statistics */
679 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
680 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
681 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
682 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
683 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
686 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
687 sizeof(rte_ixgbe_rxq_strings[0]))
689 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
690 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
691 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
692 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
696 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
697 sizeof(rte_ixgbe_txq_strings[0]))
699 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
700 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
703 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
704 sizeof(rte_ixgbevf_stats_strings[0]))
707 * Atomically reads the link status information from global
708 * structure rte_eth_dev.
711 * - Pointer to the structure rte_eth_dev to read from.
712 * - Pointer to the buffer to be saved with the link status.
715 * - On success, zero.
716 * - On failure, negative value.
719 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
720 struct rte_eth_link *link)
722 struct rte_eth_link *dst = link;
723 struct rte_eth_link *src = &(dev->data->dev_link);
725 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
726 *(uint64_t *)src) == 0)
733 * Atomically writes the link status information into global
734 * structure rte_eth_dev.
737 * - Pointer to the structure rte_eth_dev to read from.
738 * - Pointer to the buffer to be saved with the link status.
741 * - On success, zero.
742 * - On failure, negative value.
745 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
746 struct rte_eth_link *link)
748 struct rte_eth_link *dst = &(dev->data->dev_link);
749 struct rte_eth_link *src = link;
751 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
752 *(uint64_t *)src) == 0)
759 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
762 ixgbe_is_sfp(struct ixgbe_hw *hw)
764 switch (hw->phy.type) {
765 case ixgbe_phy_sfp_avago:
766 case ixgbe_phy_sfp_ftl:
767 case ixgbe_phy_sfp_intel:
768 case ixgbe_phy_sfp_unknown:
769 case ixgbe_phy_sfp_passive_tyco:
770 case ixgbe_phy_sfp_passive_unknown:
777 static inline int32_t
778 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
783 status = ixgbe_reset_hw(hw);
785 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
786 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
787 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
788 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
789 IXGBE_WRITE_FLUSH(hw);
795 ixgbe_enable_intr(struct rte_eth_dev *dev)
797 struct ixgbe_interrupt *intr =
798 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
799 struct ixgbe_hw *hw =
800 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
802 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
803 IXGBE_WRITE_FLUSH(hw);
807 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
810 ixgbe_disable_intr(struct ixgbe_hw *hw)
812 PMD_INIT_FUNC_TRACE();
814 if (hw->mac.type == ixgbe_mac_82598EB) {
815 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
817 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
818 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
819 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
821 IXGBE_WRITE_FLUSH(hw);
825 * This function resets queue statistics mapping registers.
826 * From Niantic datasheet, Initialization of Statistics section:
827 * "...if software requires the queue counters, the RQSMR and TQSM registers
828 * must be re-programmed following a device reset.
831 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
835 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
836 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
837 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
843 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
848 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
849 #define NB_QMAP_FIELDS_PER_QSM_REG 4
850 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
852 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
853 struct ixgbe_stat_mapping_registers *stat_mappings =
854 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
855 uint32_t qsmr_mask = 0;
856 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
860 if ((hw->mac.type != ixgbe_mac_82599EB) &&
861 (hw->mac.type != ixgbe_mac_X540) &&
862 (hw->mac.type != ixgbe_mac_X550) &&
863 (hw->mac.type != ixgbe_mac_X550EM_x) &&
864 (hw->mac.type != ixgbe_mac_X550EM_a))
867 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
868 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
871 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
872 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
873 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
876 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
878 /* Now clear any previous stat_idx set */
879 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
881 stat_mappings->tqsm[n] &= ~clearing_mask;
883 stat_mappings->rqsmr[n] &= ~clearing_mask;
885 q_map = (uint32_t)stat_idx;
886 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
887 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
889 stat_mappings->tqsm[n] |= qsmr_mask;
891 stat_mappings->rqsmr[n] |= qsmr_mask;
893 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
894 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
896 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
897 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
899 /* Now write the mapping in the appropriate register */
901 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
902 stat_mappings->rqsmr[n], n);
903 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
906 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
907 stat_mappings->tqsm[n], n);
908 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
914 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
916 struct ixgbe_stat_mapping_registers *stat_mappings =
917 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
918 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
921 /* write whatever was in stat mapping table to the NIC */
922 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
924 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
927 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
932 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
935 struct ixgbe_dcb_tc_config *tc;
936 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
938 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
939 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
940 for (i = 0; i < dcb_max_tc; i++) {
941 tc = &dcb_config->tc_config[i];
942 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
943 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
944 (uint8_t)(100/dcb_max_tc + (i & 1));
945 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
946 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
947 (uint8_t)(100/dcb_max_tc + (i & 1));
948 tc->pfc = ixgbe_dcb_pfc_disabled;
951 /* Initialize default user to priority mapping, UPx->TC0 */
952 tc = &dcb_config->tc_config[0];
953 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
954 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
955 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
956 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
957 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
959 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
960 dcb_config->pfc_mode_enable = false;
961 dcb_config->vt_mode = true;
962 dcb_config->round_robin_enable = false;
963 /* support all DCB capabilities in 82599 */
964 dcb_config->support.capabilities = 0xFF;
966 /*we only support 4 Tcs for X540, X550 */
967 if (hw->mac.type == ixgbe_mac_X540 ||
968 hw->mac.type == ixgbe_mac_X550 ||
969 hw->mac.type == ixgbe_mac_X550EM_x ||
970 hw->mac.type == ixgbe_mac_X550EM_a) {
971 dcb_config->num_tcs.pg_tcs = 4;
972 dcb_config->num_tcs.pfc_tcs = 4;
977 * Ensure that all locks are released before first NVM or PHY access
980 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
985 * Phy lock should not fail in this early stage. If this is the case,
986 * it is due to an improper exit of the application.
987 * So force the release of the faulty lock. Release of common lock
988 * is done automatically by swfw_sync function.
990 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
991 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
992 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
994 ixgbe_release_swfw_semaphore(hw, mask);
997 * These ones are more tricky since they are common to all ports; but
998 * swfw_sync retries last long enough (1s) to be almost sure that if
999 * lock can not be taken it is due to an improper lock of the
1002 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1003 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1004 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1006 ixgbe_release_swfw_semaphore(hw, mask);
1010 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1011 * It returns 0 on success.
1014 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1016 struct rte_pci_device *pci_dev;
1017 struct ixgbe_hw *hw =
1018 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1019 struct ixgbe_vfta * shadow_vfta =
1020 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1021 struct ixgbe_hwstrip *hwstrip =
1022 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1023 struct ixgbe_dcb_config *dcb_config =
1024 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1025 struct ixgbe_filter_info *filter_info =
1026 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1031 PMD_INIT_FUNC_TRACE();
1033 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1034 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1035 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1038 * For secondary processes, we don't initialise any further as primary
1039 * has already done this work. Only check we don't need a different
1040 * RX and TX function.
1042 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1043 struct ixgbe_tx_queue *txq;
1044 /* TX queue function in primary, set by last queue initialized
1045 * Tx queue may not initialized by primary process */
1046 if (eth_dev->data->tx_queues) {
1047 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1048 ixgbe_set_tx_function(eth_dev, txq);
1050 /* Use default TX function if we get here */
1051 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1052 "Using default TX function.");
1055 ixgbe_set_rx_function(eth_dev);
1059 pci_dev = eth_dev->pci_dev;
1061 rte_eth_copy_pci_info(eth_dev, pci_dev);
1063 /* Vendor and Device ID need to be set before init of shared code */
1064 hw->device_id = pci_dev->id.device_id;
1065 hw->vendor_id = pci_dev->id.vendor_id;
1066 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1067 hw->allow_unsupported_sfp = 1;
1069 /* Initialize the shared code (base driver) */
1070 #ifdef RTE_NIC_BYPASS
1071 diag = ixgbe_bypass_init_shared_code(hw);
1073 diag = ixgbe_init_shared_code(hw);
1074 #endif /* RTE_NIC_BYPASS */
1076 if (diag != IXGBE_SUCCESS) {
1077 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1081 /* pick up the PCI bus settings for reporting later */
1082 ixgbe_get_bus_info(hw);
1084 /* Unlock any pending hardware semaphore */
1085 ixgbe_swfw_lock_reset(hw);
1087 /* Initialize DCB configuration*/
1088 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1089 ixgbe_dcb_init(hw,dcb_config);
1090 /* Get Hardware Flow Control setting */
1091 hw->fc.requested_mode = ixgbe_fc_full;
1092 hw->fc.current_mode = ixgbe_fc_full;
1093 hw->fc.pause_time = IXGBE_FC_PAUSE;
1094 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1095 hw->fc.low_water[i] = IXGBE_FC_LO;
1096 hw->fc.high_water[i] = IXGBE_FC_HI;
1098 hw->fc.send_xon = 1;
1100 /* Make sure we have a good EEPROM before we read from it */
1101 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1102 if (diag != IXGBE_SUCCESS) {
1103 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1107 #ifdef RTE_NIC_BYPASS
1108 diag = ixgbe_bypass_init_hw(hw);
1110 diag = ixgbe_init_hw(hw);
1111 #endif /* RTE_NIC_BYPASS */
1114 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1115 * is called too soon after the kernel driver unbinding/binding occurs.
1116 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1117 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1118 * also called. See ixgbe_identify_phy_82599(). The reason for the
1119 * failure is not known, and only occuts when virtualisation features
1120 * are disabled in the bios. A delay of 100ms was found to be enough by
1121 * trial-and-error, and is doubled to be safe.
1123 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1125 diag = ixgbe_init_hw(hw);
1128 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1129 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1130 "LOM. Please be aware there may be issues associated "
1131 "with your hardware.");
1132 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1133 "please contact your Intel or hardware representative "
1134 "who provided you with this hardware.");
1135 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1136 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1138 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1142 /* Reset the hw statistics */
1143 ixgbe_dev_stats_reset(eth_dev);
1145 /* disable interrupt */
1146 ixgbe_disable_intr(hw);
1148 /* reset mappings for queue statistics hw counters*/
1149 ixgbe_reset_qstat_mappings(hw);
1151 /* Allocate memory for storing MAC addresses */
1152 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1153 hw->mac.num_rar_entries, 0);
1154 if (eth_dev->data->mac_addrs == NULL) {
1156 "Failed to allocate %u bytes needed to store "
1158 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1161 /* Copy the permanent MAC address */
1162 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1163 ð_dev->data->mac_addrs[0]);
1165 /* Allocate memory for storing hash filter MAC addresses */
1166 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1167 IXGBE_VMDQ_NUM_UC_MAC, 0);
1168 if (eth_dev->data->hash_mac_addrs == NULL) {
1170 "Failed to allocate %d bytes needed to store MAC addresses",
1171 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1175 /* initialize the vfta */
1176 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1178 /* initialize the hw strip bitmap*/
1179 memset(hwstrip, 0, sizeof(*hwstrip));
1181 /* initialize PF if max_vfs not zero */
1182 ixgbe_pf_host_init(eth_dev);
1184 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1185 /* let hardware know driver is loaded */
1186 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1187 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1188 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1189 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1190 IXGBE_WRITE_FLUSH(hw);
1192 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1193 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1194 (int) hw->mac.type, (int) hw->phy.type,
1195 (int) hw->phy.sfp_type);
1197 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1198 (int) hw->mac.type, (int) hw->phy.type);
1200 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1201 eth_dev->data->port_id, pci_dev->id.vendor_id,
1202 pci_dev->id.device_id);
1204 rte_intr_callback_register(&pci_dev->intr_handle,
1205 ixgbe_dev_interrupt_handler,
1208 /* enable uio/vfio intr/eventfd mapping */
1209 rte_intr_enable(&pci_dev->intr_handle);
1211 /* enable support intr */
1212 ixgbe_enable_intr(eth_dev);
1214 /* initialize 5tuple filter list */
1215 TAILQ_INIT(&filter_info->fivetuple_list);
1216 memset(filter_info->fivetuple_mask, 0,
1217 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1223 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1225 struct rte_pci_device *pci_dev;
1226 struct ixgbe_hw *hw;
1228 PMD_INIT_FUNC_TRACE();
1230 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1233 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1234 pci_dev = eth_dev->pci_dev;
1236 if (hw->adapter_stopped == 0)
1237 ixgbe_dev_close(eth_dev);
1239 eth_dev->dev_ops = NULL;
1240 eth_dev->rx_pkt_burst = NULL;
1241 eth_dev->tx_pkt_burst = NULL;
1243 /* Unlock any pending hardware semaphore */
1244 ixgbe_swfw_lock_reset(hw);
1246 /* disable uio intr before callback unregister */
1247 rte_intr_disable(&(pci_dev->intr_handle));
1248 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1249 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1251 /* uninitialize PF if max_vfs not zero */
1252 ixgbe_pf_host_uninit(eth_dev);
1254 rte_free(eth_dev->data->mac_addrs);
1255 eth_dev->data->mac_addrs = NULL;
1257 rte_free(eth_dev->data->hash_mac_addrs);
1258 eth_dev->data->hash_mac_addrs = NULL;
1264 * Negotiate mailbox API version with the PF.
1265 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1266 * Then we try to negotiate starting with the most recent one.
1267 * If all negotiation attempts fail, then we will proceed with
1268 * the default one (ixgbe_mbox_api_10).
1271 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1275 /* start with highest supported, proceed down */
1276 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1283 i != RTE_DIM(sup_ver) &&
1284 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1290 generate_random_mac_addr(struct ether_addr *mac_addr)
1294 /* Set Organizationally Unique Identifier (OUI) prefix. */
1295 mac_addr->addr_bytes[0] = 0x00;
1296 mac_addr->addr_bytes[1] = 0x09;
1297 mac_addr->addr_bytes[2] = 0xC0;
1298 /* Force indication of locally assigned MAC address. */
1299 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1300 /* Generate the last 3 bytes of the MAC address with a random number. */
1301 random = rte_rand();
1302 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1306 * Virtual Function device init
1309 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1313 struct rte_pci_device *pci_dev;
1314 struct ixgbe_hw *hw =
1315 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1316 struct ixgbe_vfta * shadow_vfta =
1317 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1318 struct ixgbe_hwstrip *hwstrip =
1319 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1320 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1322 PMD_INIT_FUNC_TRACE();
1324 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1325 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1326 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1328 /* for secondary processes, we don't initialise any further as primary
1329 * has already done this work. Only check we don't need a different
1331 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1332 struct ixgbe_tx_queue *txq;
1333 /* TX queue function in primary, set by last queue initialized
1334 * Tx queue may not initialized by primary process
1336 if (eth_dev->data->tx_queues) {
1337 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1338 ixgbe_set_tx_function(eth_dev, txq);
1340 /* Use default TX function if we get here */
1341 PMD_INIT_LOG(NOTICE,
1342 "No TX queues configured yet. Using default TX function.");
1345 ixgbe_set_rx_function(eth_dev);
1350 pci_dev = eth_dev->pci_dev;
1352 rte_eth_copy_pci_info(eth_dev, pci_dev);
1354 hw->device_id = pci_dev->id.device_id;
1355 hw->vendor_id = pci_dev->id.vendor_id;
1356 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1358 /* initialize the vfta */
1359 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1361 /* initialize the hw strip bitmap*/
1362 memset(hwstrip, 0, sizeof(*hwstrip));
1364 /* Initialize the shared code (base driver) */
1365 diag = ixgbe_init_shared_code(hw);
1366 if (diag != IXGBE_SUCCESS) {
1367 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1371 /* init_mailbox_params */
1372 hw->mbx.ops.init_params(hw);
1374 /* Reset the hw statistics */
1375 ixgbevf_dev_stats_reset(eth_dev);
1377 /* Disable the interrupts for VF */
1378 ixgbevf_intr_disable(hw);
1380 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1381 diag = hw->mac.ops.reset_hw(hw);
1384 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1385 * the underlying PF driver has not assigned a MAC address to the VF.
1386 * In this case, assign a random MAC address.
1388 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1389 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1393 /* negotiate mailbox API version to use with the PF. */
1394 ixgbevf_negotiate_api(hw);
1396 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1397 ixgbevf_get_queues(hw, &tcs, &tc);
1399 /* Allocate memory for storing MAC addresses */
1400 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1401 hw->mac.num_rar_entries, 0);
1402 if (eth_dev->data->mac_addrs == NULL) {
1404 "Failed to allocate %u bytes needed to store "
1406 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1410 /* Generate a random MAC address, if none was assigned by PF. */
1411 if (is_zero_ether_addr(perm_addr)) {
1412 generate_random_mac_addr(perm_addr);
1413 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1415 rte_free(eth_dev->data->mac_addrs);
1416 eth_dev->data->mac_addrs = NULL;
1419 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1420 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1421 "%02x:%02x:%02x:%02x:%02x:%02x",
1422 perm_addr->addr_bytes[0],
1423 perm_addr->addr_bytes[1],
1424 perm_addr->addr_bytes[2],
1425 perm_addr->addr_bytes[3],
1426 perm_addr->addr_bytes[4],
1427 perm_addr->addr_bytes[5]);
1430 /* Copy the permanent MAC address */
1431 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1433 /* reset the hardware with the new settings */
1434 diag = hw->mac.ops.start_hw(hw);
1440 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1444 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1445 eth_dev->data->port_id, pci_dev->id.vendor_id,
1446 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1451 /* Virtual Function device uninit */
1454 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1456 struct ixgbe_hw *hw;
1458 PMD_INIT_FUNC_TRACE();
1460 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1463 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1465 if (hw->adapter_stopped == 0)
1466 ixgbevf_dev_close(eth_dev);
1468 eth_dev->dev_ops = NULL;
1469 eth_dev->rx_pkt_burst = NULL;
1470 eth_dev->tx_pkt_burst = NULL;
1472 /* Disable the interrupts for VF */
1473 ixgbevf_intr_disable(hw);
1475 rte_free(eth_dev->data->mac_addrs);
1476 eth_dev->data->mac_addrs = NULL;
1481 static struct eth_driver rte_ixgbe_pmd = {
1483 .name = "rte_ixgbe_pmd",
1484 .id_table = pci_id_ixgbe_map,
1485 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1486 RTE_PCI_DRV_DETACHABLE,
1488 .eth_dev_init = eth_ixgbe_dev_init,
1489 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1490 .dev_private_size = sizeof(struct ixgbe_adapter),
1494 * virtual function driver struct
1496 static struct eth_driver rte_ixgbevf_pmd = {
1498 .name = "rte_ixgbevf_pmd",
1499 .id_table = pci_id_ixgbevf_map,
1500 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1502 .eth_dev_init = eth_ixgbevf_dev_init,
1503 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1504 .dev_private_size = sizeof(struct ixgbe_adapter),
1508 * Driver initialization routine.
1509 * Invoked once at EAL init time.
1510 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1513 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1515 PMD_INIT_FUNC_TRACE();
1517 rte_eth_driver_register(&rte_ixgbe_pmd);
1522 * VF Driver initialization routine.
1523 * Invoked one at EAL init time.
1524 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1527 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1529 PMD_INIT_FUNC_TRACE();
1531 rte_eth_driver_register(&rte_ixgbevf_pmd);
1536 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1538 struct ixgbe_hw *hw =
1539 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1540 struct ixgbe_vfta * shadow_vfta =
1541 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1546 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1547 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1548 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1553 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1555 /* update local VFTA copy */
1556 shadow_vfta->vfta[vid_idx] = vfta;
1562 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1565 ixgbe_vlan_hw_strip_enable(dev, queue);
1567 ixgbe_vlan_hw_strip_disable(dev, queue);
1571 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1572 enum rte_vlan_type vlan_type,
1575 struct ixgbe_hw *hw =
1576 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1579 switch (vlan_type) {
1580 case ETH_VLAN_TYPE_INNER:
1581 /* Only the high 16-bits is valid */
1582 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1586 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1594 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1596 struct ixgbe_hw *hw =
1597 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1600 PMD_INIT_FUNC_TRACE();
1602 /* Filter Table Disable */
1603 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1604 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1606 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1610 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1612 struct ixgbe_hw *hw =
1613 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1614 struct ixgbe_vfta * shadow_vfta =
1615 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1619 PMD_INIT_FUNC_TRACE();
1621 /* Filter Table Enable */
1622 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1623 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1624 vlnctrl |= IXGBE_VLNCTRL_VFE;
1626 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1628 /* write whatever is in local vfta copy */
1629 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1630 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1634 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1636 struct ixgbe_hwstrip *hwstrip =
1637 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1639 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1643 IXGBE_SET_HWSTRIP(hwstrip, queue);
1645 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1649 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1651 struct ixgbe_hw *hw =
1652 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1655 PMD_INIT_FUNC_TRACE();
1657 if (hw->mac.type == ixgbe_mac_82598EB) {
1658 /* No queue level support */
1659 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1663 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1664 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1665 ctrl &= ~IXGBE_RXDCTL_VME;
1666 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1668 /* record those setting for HW strip per queue */
1669 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1673 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1675 struct ixgbe_hw *hw =
1676 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1679 PMD_INIT_FUNC_TRACE();
1681 if (hw->mac.type == ixgbe_mac_82598EB) {
1682 /* No queue level supported */
1683 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1687 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1688 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1689 ctrl |= IXGBE_RXDCTL_VME;
1690 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1692 /* record those setting for HW strip per queue */
1693 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1697 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1699 struct ixgbe_hw *hw =
1700 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1704 PMD_INIT_FUNC_TRACE();
1706 if (hw->mac.type == ixgbe_mac_82598EB) {
1707 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1708 ctrl &= ~IXGBE_VLNCTRL_VME;
1709 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1712 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1713 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1714 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1715 ctrl &= ~IXGBE_RXDCTL_VME;
1716 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1718 /* record those setting for HW strip per queue */
1719 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1725 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1727 struct ixgbe_hw *hw =
1728 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1732 PMD_INIT_FUNC_TRACE();
1734 if (hw->mac.type == ixgbe_mac_82598EB) {
1735 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1736 ctrl |= IXGBE_VLNCTRL_VME;
1737 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1740 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1741 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1742 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1743 ctrl |= IXGBE_RXDCTL_VME;
1744 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1746 /* record those setting for HW strip per queue */
1747 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1753 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1755 struct ixgbe_hw *hw =
1756 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1759 PMD_INIT_FUNC_TRACE();
1761 /* DMATXCTRL: Geric Double VLAN Disable */
1762 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1763 ctrl &= ~IXGBE_DMATXCTL_GDV;
1764 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1766 /* CTRL_EXT: Global Double VLAN Disable */
1767 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1768 ctrl &= ~IXGBE_EXTENDED_VLAN;
1769 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1774 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1776 struct ixgbe_hw *hw =
1777 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1780 PMD_INIT_FUNC_TRACE();
1782 /* DMATXCTRL: Geric Double VLAN Enable */
1783 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1784 ctrl |= IXGBE_DMATXCTL_GDV;
1785 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1787 /* CTRL_EXT: Global Double VLAN Enable */
1788 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1789 ctrl |= IXGBE_EXTENDED_VLAN;
1790 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1792 /* Clear pooling mode of PFVTCTL. It's required by X550. */
1793 if (hw->mac.type == ixgbe_mac_X550 ||
1794 hw->mac.type == ixgbe_mac_X550EM_x) {
1795 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1796 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1797 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1801 * VET EXT field in the EXVET register = 0x8100 by default
1802 * So no need to change. Same to VT field of DMATXCTL register
1807 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1809 if (mask & ETH_VLAN_STRIP_MASK) {
1810 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1811 ixgbe_vlan_hw_strip_enable_all(dev);
1813 ixgbe_vlan_hw_strip_disable_all(dev);
1816 if (mask & ETH_VLAN_FILTER_MASK) {
1817 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1818 ixgbe_vlan_hw_filter_enable(dev);
1820 ixgbe_vlan_hw_filter_disable(dev);
1823 if (mask & ETH_VLAN_EXTEND_MASK) {
1824 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1825 ixgbe_vlan_hw_extend_enable(dev);
1827 ixgbe_vlan_hw_extend_disable(dev);
1832 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1834 struct ixgbe_hw *hw =
1835 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1836 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1837 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1838 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1839 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1843 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1848 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1851 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1857 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1858 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1864 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1866 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1867 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1868 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1870 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1871 /* check multi-queue mode */
1872 switch (dev_conf->rxmode.mq_mode) {
1873 case ETH_MQ_RX_VMDQ_DCB:
1874 case ETH_MQ_RX_VMDQ_DCB_RSS:
1875 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1876 PMD_INIT_LOG(ERR, "SRIOV active,"
1877 " unsupported mq_mode rx %d.",
1878 dev_conf->rxmode.mq_mode);
1881 case ETH_MQ_RX_VMDQ_RSS:
1882 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1883 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1884 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1885 PMD_INIT_LOG(ERR, "SRIOV is active,"
1886 " invalid queue number"
1887 " for VMDQ RSS, allowed"
1888 " value are 1, 2 or 4.");
1892 case ETH_MQ_RX_VMDQ_ONLY:
1893 case ETH_MQ_RX_NONE:
1894 /* if nothing mq mode configure, use default scheme */
1895 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1896 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1897 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1899 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1900 /* SRIOV only works in VMDq enable mode */
1901 PMD_INIT_LOG(ERR, "SRIOV is active,"
1902 " wrong mq_mode rx %d.",
1903 dev_conf->rxmode.mq_mode);
1907 switch (dev_conf->txmode.mq_mode) {
1908 case ETH_MQ_TX_VMDQ_DCB:
1909 /* DCB VMDQ in SRIOV mode, not implement yet */
1910 PMD_INIT_LOG(ERR, "SRIOV is active,"
1911 " unsupported VMDQ mq_mode tx %d.",
1912 dev_conf->txmode.mq_mode);
1914 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1915 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1919 /* check valid queue number */
1920 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1921 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1922 PMD_INIT_LOG(ERR, "SRIOV is active,"
1923 " nb_rx_q=%d nb_tx_q=%d queue number"
1924 " must be less than or equal to %d.",
1926 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1930 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1931 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1935 /* check configuration for vmdb+dcb mode */
1936 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1937 const struct rte_eth_vmdq_dcb_conf *conf;
1939 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1940 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1941 IXGBE_VMDQ_DCB_NB_QUEUES);
1944 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1945 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1946 conf->nb_queue_pools == ETH_32_POOLS)) {
1947 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1948 " nb_queue_pools must be %d or %d.",
1949 ETH_16_POOLS, ETH_32_POOLS);
1953 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1954 const struct rte_eth_vmdq_dcb_tx_conf *conf;
1956 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1957 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1958 IXGBE_VMDQ_DCB_NB_QUEUES);
1961 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1962 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1963 conf->nb_queue_pools == ETH_32_POOLS)) {
1964 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1965 " nb_queue_pools != %d and"
1966 " nb_queue_pools != %d.",
1967 ETH_16_POOLS, ETH_32_POOLS);
1972 /* For DCB mode check our configuration before we go further */
1973 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1974 const struct rte_eth_dcb_rx_conf *conf;
1976 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1977 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1978 IXGBE_DCB_NB_QUEUES);
1981 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1982 if (!(conf->nb_tcs == ETH_4_TCS ||
1983 conf->nb_tcs == ETH_8_TCS)) {
1984 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1985 " and nb_tcs != %d.",
1986 ETH_4_TCS, ETH_8_TCS);
1991 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1992 const struct rte_eth_dcb_tx_conf *conf;
1994 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1995 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1996 IXGBE_DCB_NB_QUEUES);
1999 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2000 if (!(conf->nb_tcs == ETH_4_TCS ||
2001 conf->nb_tcs == ETH_8_TCS)) {
2002 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2003 " and nb_tcs != %d.",
2004 ETH_4_TCS, ETH_8_TCS);
2013 ixgbe_dev_configure(struct rte_eth_dev *dev)
2015 struct ixgbe_interrupt *intr =
2016 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2017 struct ixgbe_adapter *adapter =
2018 (struct ixgbe_adapter *)dev->data->dev_private;
2021 PMD_INIT_FUNC_TRACE();
2022 /* multipe queue mode checking */
2023 ret = ixgbe_check_mq_mode(dev);
2025 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2030 /* set flag to update link status after init */
2031 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2034 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2035 * allocation or vector Rx preconditions we will reset it.
2037 adapter->rx_bulk_alloc_allowed = true;
2038 adapter->rx_vec_allowed = true;
2044 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2046 struct ixgbe_hw *hw =
2047 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2048 struct ixgbe_interrupt *intr =
2049 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2052 /* only set up it on X550EM_X */
2053 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2054 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2055 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2056 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2057 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2058 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2063 * Configure device link speed and setup link.
2064 * It returns 0 on success.
2067 ixgbe_dev_start(struct rte_eth_dev *dev)
2069 struct ixgbe_hw *hw =
2070 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2071 struct ixgbe_vf_info *vfinfo =
2072 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2073 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2074 uint32_t intr_vector = 0;
2075 int err, link_up = 0, negotiate = 0;
2081 PMD_INIT_FUNC_TRACE();
2083 /* IXGBE devices don't support half duplex */
2084 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
2085 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
2086 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
2087 dev->data->dev_conf.link_duplex,
2088 dev->data->port_id);
2092 /* disable uio/vfio intr/eventfd mapping */
2093 rte_intr_disable(intr_handle);
2096 hw->adapter_stopped = 0;
2097 ixgbe_stop_adapter(hw);
2099 /* reinitialize adapter
2100 * this calls reset and start */
2101 status = ixgbe_pf_reset_hw(hw);
2104 hw->mac.ops.start_hw(hw);
2105 hw->mac.get_link_status = true;
2107 /* configure PF module if SRIOV enabled */
2108 ixgbe_pf_host_configure(dev);
2110 ixgbe_dev_phy_intr_setup(dev);
2112 /* check and configure queue intr-vector mapping */
2113 if ((rte_intr_cap_multiple(intr_handle) ||
2114 !RTE_ETH_DEV_SRIOV(dev).active) &&
2115 dev->data->dev_conf.intr_conf.rxq != 0) {
2116 intr_vector = dev->data->nb_rx_queues;
2117 if (rte_intr_efd_enable(intr_handle, intr_vector))
2121 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2122 intr_handle->intr_vec =
2123 rte_zmalloc("intr_vec",
2124 dev->data->nb_rx_queues * sizeof(int), 0);
2125 if (intr_handle->intr_vec == NULL) {
2126 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2127 " intr_vec\n", dev->data->nb_rx_queues);
2132 /* confiugre msix for sleep until rx interrupt */
2133 ixgbe_configure_msix(dev);
2135 /* initialize transmission unit */
2136 ixgbe_dev_tx_init(dev);
2138 /* This can fail when allocating mbufs for descriptor rings */
2139 err = ixgbe_dev_rx_init(dev);
2141 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2145 err = ixgbe_dev_rxtx_start(dev);
2147 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2151 /* Skip link setup if loopback mode is enabled for 82599. */
2152 if (hw->mac.type == ixgbe_mac_82599EB &&
2153 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2154 goto skip_link_setup;
2156 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2157 err = hw->mac.ops.setup_sfp(hw);
2162 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2163 /* Turn on the copper */
2164 ixgbe_set_phy_power(hw, true);
2166 /* Turn on the laser */
2167 ixgbe_enable_tx_laser(hw);
2170 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2173 dev->data->dev_link.link_status = link_up;
2175 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2179 switch(dev->data->dev_conf.link_speed) {
2180 case ETH_LINK_SPEED_AUTONEG:
2181 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2182 IXGBE_LINK_SPEED_82599_AUTONEG :
2183 IXGBE_LINK_SPEED_82598_AUTONEG;
2185 case ETH_LINK_SPEED_100:
2187 * Invalid for 82598 but error will be detected by
2188 * ixgbe_setup_link()
2190 speed = IXGBE_LINK_SPEED_100_FULL;
2192 case ETH_LINK_SPEED_1000:
2193 speed = IXGBE_LINK_SPEED_1GB_FULL;
2195 case ETH_LINK_SPEED_10000:
2196 speed = IXGBE_LINK_SPEED_10GB_FULL;
2199 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2200 dev->data->dev_conf.link_speed,
2201 dev->data->port_id);
2205 err = ixgbe_setup_link(hw, speed, link_up);
2211 if (rte_intr_allow_others(intr_handle)) {
2212 /* check if lsc interrupt is enabled */
2213 if (dev->data->dev_conf.intr_conf.lsc != 0)
2214 ixgbe_dev_lsc_interrupt_setup(dev);
2216 rte_intr_callback_unregister(intr_handle,
2217 ixgbe_dev_interrupt_handler,
2219 if (dev->data->dev_conf.intr_conf.lsc != 0)
2220 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2221 " no intr multiplex\n");
2224 /* check if rxq interrupt is enabled */
2225 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2226 rte_intr_dp_is_en(intr_handle))
2227 ixgbe_dev_rxq_interrupt_setup(dev);
2229 /* enable uio/vfio intr/eventfd mapping */
2230 rte_intr_enable(intr_handle);
2232 /* resume enabled intr since hw reset */
2233 ixgbe_enable_intr(dev);
2235 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2236 ETH_VLAN_EXTEND_MASK;
2237 ixgbe_vlan_offload_set(dev, mask);
2239 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2240 /* Enable vlan filtering for VMDq */
2241 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2244 /* Configure DCB hw */
2245 ixgbe_configure_dcb(dev);
2247 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2248 err = ixgbe_fdir_configure(dev);
2253 /* Restore vf rate limit */
2254 if (vfinfo != NULL) {
2255 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2256 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2257 if (vfinfo[vf].tx_rate[idx] != 0)
2258 ixgbe_set_vf_rate_limit(dev, vf,
2259 vfinfo[vf].tx_rate[idx],
2263 ixgbe_restore_statistics_mapping(dev);
2268 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2269 ixgbe_dev_clear_queues(dev);
2274 * Stop device: disable rx and tx functions to allow for reconfiguring.
2277 ixgbe_dev_stop(struct rte_eth_dev *dev)
2279 struct rte_eth_link link;
2280 struct ixgbe_hw *hw =
2281 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2282 struct ixgbe_vf_info *vfinfo =
2283 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2284 struct ixgbe_filter_info *filter_info =
2285 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2286 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2287 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2290 PMD_INIT_FUNC_TRACE();
2292 /* disable interrupts */
2293 ixgbe_disable_intr(hw);
2296 ixgbe_pf_reset_hw(hw);
2297 hw->adapter_stopped = 0;
2300 ixgbe_stop_adapter(hw);
2302 for (vf = 0; vfinfo != NULL &&
2303 vf < dev->pci_dev->max_vfs; vf++)
2304 vfinfo[vf].clear_to_send = false;
2306 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2307 /* Turn off the copper */
2308 ixgbe_set_phy_power(hw, false);
2310 /* Turn off the laser */
2311 ixgbe_disable_tx_laser(hw);
2314 ixgbe_dev_clear_queues(dev);
2316 /* Clear stored conf */
2317 dev->data->scattered_rx = 0;
2320 /* Clear recorded link status */
2321 memset(&link, 0, sizeof(link));
2322 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2324 /* Remove all ntuple filters of the device */
2325 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2326 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2327 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2328 TAILQ_REMOVE(&filter_info->fivetuple_list,
2332 memset(filter_info->fivetuple_mask, 0,
2333 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2335 if (!rte_intr_allow_others(intr_handle))
2336 /* resume to the default handler */
2337 rte_intr_callback_register(intr_handle,
2338 ixgbe_dev_interrupt_handler,
2341 /* Clean datapath event and queue/vec mapping */
2342 rte_intr_efd_disable(intr_handle);
2343 if (intr_handle->intr_vec != NULL) {
2344 rte_free(intr_handle->intr_vec);
2345 intr_handle->intr_vec = NULL;
2350 * Set device link up: enable tx.
2353 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2355 struct ixgbe_hw *hw =
2356 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2357 if (hw->mac.type == ixgbe_mac_82599EB) {
2358 #ifdef RTE_NIC_BYPASS
2359 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2360 /* Not suported in bypass mode */
2361 PMD_INIT_LOG(ERR, "Set link up is not supported "
2362 "by device id 0x%x", hw->device_id);
2368 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2369 /* Turn on the copper */
2370 ixgbe_set_phy_power(hw, true);
2372 /* Turn on the laser */
2373 ixgbe_enable_tx_laser(hw);
2380 * Set device link down: disable tx.
2383 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2385 struct ixgbe_hw *hw =
2386 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2387 if (hw->mac.type == ixgbe_mac_82599EB) {
2388 #ifdef RTE_NIC_BYPASS
2389 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2390 /* Not suported in bypass mode */
2391 PMD_INIT_LOG(ERR, "Set link down is not supported "
2392 "by device id 0x%x", hw->device_id);
2398 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2399 /* Turn off the copper */
2400 ixgbe_set_phy_power(hw, false);
2402 /* Turn off the laser */
2403 ixgbe_disable_tx_laser(hw);
2410 * Reest and stop device.
2413 ixgbe_dev_close(struct rte_eth_dev *dev)
2415 struct ixgbe_hw *hw =
2416 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2418 PMD_INIT_FUNC_TRACE();
2420 ixgbe_pf_reset_hw(hw);
2422 ixgbe_dev_stop(dev);
2423 hw->adapter_stopped = 1;
2425 ixgbe_dev_free_queues(dev);
2427 ixgbe_disable_pcie_master(hw);
2429 /* reprogram the RAR[0] in case user changed it. */
2430 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2434 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2435 struct ixgbe_hw_stats *hw_stats,
2436 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2437 uint64_t *total_qprc, uint64_t *total_qprdc)
2439 uint32_t bprc, lxon, lxoff, total;
2440 uint32_t delta_gprc = 0;
2442 /* Workaround for RX byte count not including CRC bytes when CRC
2443 + * strip is enabled. CRC bytes are removed from counters when crc_strip
2446 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2447 IXGBE_HLREG0_RXCRCSTRP);
2449 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2450 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2451 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2452 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2454 for (i = 0; i < 8; i++) {
2456 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2457 /* global total per queue */
2458 hw_stats->mpc[i] += mp;
2459 /* Running comprehensive total for stats display */
2460 *total_missed_rx += hw_stats->mpc[i];
2461 if (hw->mac.type == ixgbe_mac_82598EB) {
2462 hw_stats->rnbc[i] +=
2463 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2464 hw_stats->pxonrxc[i] +=
2465 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2466 hw_stats->pxoffrxc[i] +=
2467 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2469 hw_stats->pxonrxc[i] +=
2470 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2471 hw_stats->pxoffrxc[i] +=
2472 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2473 hw_stats->pxon2offc[i] +=
2474 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2476 hw_stats->pxontxc[i] +=
2477 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2478 hw_stats->pxofftxc[i] +=
2479 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2481 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2482 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2483 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2484 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2486 delta_gprc += delta_qprc;
2488 hw_stats->qprc[i] += delta_qprc;
2489 hw_stats->qptc[i] += delta_qptc;
2491 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2492 hw_stats->qbrc[i] +=
2493 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2495 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2497 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2498 hw_stats->qbtc[i] +=
2499 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2501 hw_stats->qprdc[i] += delta_qprdc;
2502 *total_qprdc += hw_stats->qprdc[i];
2504 *total_qprc += hw_stats->qprc[i];
2505 *total_qbrc += hw_stats->qbrc[i];
2507 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2508 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2509 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2512 * An errata states that gprc actually counts good + missed packets:
2513 * Workaround to set gprc to summated queue packet receives
2515 hw_stats->gprc = *total_qprc;
2517 if (hw->mac.type != ixgbe_mac_82598EB) {
2518 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2519 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2520 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2521 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2522 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2523 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2524 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2525 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2527 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2528 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2529 /* 82598 only has a counter in the high register */
2530 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2531 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2532 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2534 uint64_t old_tpr = hw_stats->tpr;
2536 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2537 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2540 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2542 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2543 hw_stats->gptc += delta_gptc;
2544 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2545 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2548 * Workaround: mprc hardware is incorrectly counting
2549 * broadcasts, so for now we subtract those.
2551 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2552 hw_stats->bprc += bprc;
2553 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2554 if (hw->mac.type == ixgbe_mac_82598EB)
2555 hw_stats->mprc -= bprc;
2557 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2558 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2559 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2560 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2561 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2562 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2564 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2565 hw_stats->lxontxc += lxon;
2566 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2567 hw_stats->lxofftxc += lxoff;
2568 total = lxon + lxoff;
2570 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2571 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2572 hw_stats->gptc -= total;
2573 hw_stats->mptc -= total;
2574 hw_stats->ptc64 -= total;
2575 hw_stats->gotc -= total * ETHER_MIN_LEN;
2577 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2578 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2579 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2580 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2581 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2582 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2583 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2584 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2585 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2586 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2587 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2588 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2589 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2590 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2591 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2592 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2593 /* Only read FCOE on 82599 */
2594 if (hw->mac.type != ixgbe_mac_82598EB) {
2595 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2596 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2597 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2598 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2599 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2602 /* Flow Director Stats registers */
2603 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2604 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2608 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2611 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2613 struct ixgbe_hw *hw =
2614 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2615 struct ixgbe_hw_stats *hw_stats =
2616 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2617 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2620 total_missed_rx = 0;
2625 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2626 &total_qprc, &total_qprdc);
2631 /* Fill out the rte_eth_stats statistics structure */
2632 stats->ipackets = total_qprc;
2633 stats->ibytes = total_qbrc;
2634 stats->opackets = hw_stats->gptc;
2635 stats->obytes = hw_stats->gotc;
2637 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2638 stats->q_ipackets[i] = hw_stats->qprc[i];
2639 stats->q_opackets[i] = hw_stats->qptc[i];
2640 stats->q_ibytes[i] = hw_stats->qbrc[i];
2641 stats->q_obytes[i] = hw_stats->qbtc[i];
2642 stats->q_errors[i] = hw_stats->qprdc[i];
2646 stats->imissed = total_missed_rx;
2647 stats->ierrors = hw_stats->crcerrs +
2663 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2665 struct ixgbe_hw_stats *stats =
2666 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2668 /* HW registers are cleared on read */
2669 ixgbe_dev_stats_get(dev, NULL);
2671 /* Reset software totals */
2672 memset(stats, 0, sizeof(*stats));
2675 /* This function calculates the number of xstats based on the current config */
2677 ixgbe_xstats_calc_num(void) {
2678 return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2679 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2683 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2686 struct ixgbe_hw *hw =
2687 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2688 struct ixgbe_hw_stats *hw_stats =
2689 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2690 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2691 unsigned i, stat, count = 0;
2693 count = ixgbe_xstats_calc_num();
2698 total_missed_rx = 0;
2703 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2704 &total_qprc, &total_qprdc);
2706 /* If this is a reset xstats is NULL, and we have cleared the
2707 * registers by reading them.
2712 /* Extended stats from ixgbe_hw_stats */
2714 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2715 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2716 rte_ixgbe_stats_strings[i].name);
2717 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2718 rte_ixgbe_stats_strings[i].offset);
2722 /* RX Priority Stats */
2723 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2724 for (i = 0; i < 8; i++) {
2725 snprintf(xstats[count].name, sizeof(xstats[count].name),
2726 "rx_priority%u_%s", i,
2727 rte_ixgbe_rxq_strings[stat].name);
2728 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2729 rte_ixgbe_rxq_strings[stat].offset +
2730 (sizeof(uint64_t) * i));
2735 /* TX Priority Stats */
2736 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2737 for (i = 0; i < 8; i++) {
2738 snprintf(xstats[count].name, sizeof(xstats[count].name),
2739 "tx_priority%u_%s", i,
2740 rte_ixgbe_txq_strings[stat].name);
2741 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2742 rte_ixgbe_txq_strings[stat].offset +
2743 (sizeof(uint64_t) * i));
2752 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2754 struct ixgbe_hw_stats *stats =
2755 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2757 unsigned count = ixgbe_xstats_calc_num();
2759 /* HW registers are cleared on read */
2760 ixgbe_dev_xstats_get(dev, NULL, count);
2762 /* Reset software totals */
2763 memset(stats, 0, sizeof(*stats));
2767 ixgbevf_update_stats(struct rte_eth_dev *dev)
2769 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2770 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2771 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2773 /* Good Rx packet, include VF loopback */
2774 UPDATE_VF_STAT(IXGBE_VFGPRC,
2775 hw_stats->last_vfgprc, hw_stats->vfgprc);
2777 /* Good Rx octets, include VF loopback */
2778 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2779 hw_stats->last_vfgorc, hw_stats->vfgorc);
2781 /* Good Tx packet, include VF loopback */
2782 UPDATE_VF_STAT(IXGBE_VFGPTC,
2783 hw_stats->last_vfgptc, hw_stats->vfgptc);
2785 /* Good Tx octets, include VF loopback */
2786 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2787 hw_stats->last_vfgotc, hw_stats->vfgotc);
2789 /* Rx Multicst Packet */
2790 UPDATE_VF_STAT(IXGBE_VFMPRC,
2791 hw_stats->last_vfmprc, hw_stats->vfmprc);
2795 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2798 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2799 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2802 if (n < IXGBEVF_NB_XSTATS)
2803 return IXGBEVF_NB_XSTATS;
2805 ixgbevf_update_stats(dev);
2810 /* Extended stats */
2811 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2812 snprintf(xstats[i].name, sizeof(xstats[i].name),
2813 "%s", rte_ixgbevf_stats_strings[i].name);
2814 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2815 rte_ixgbevf_stats_strings[i].offset);
2818 return IXGBEVF_NB_XSTATS;
2822 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2824 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2825 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2827 ixgbevf_update_stats(dev);
2832 stats->ipackets = hw_stats->vfgprc;
2833 stats->ibytes = hw_stats->vfgorc;
2834 stats->opackets = hw_stats->vfgptc;
2835 stats->obytes = hw_stats->vfgotc;
2836 stats->imcasts = hw_stats->vfmprc;
2837 /* stats->imcasts should be removed as imcasts is deprecated */
2841 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2843 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2844 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2846 /* Sync HW register to the last stats */
2847 ixgbevf_dev_stats_get(dev, NULL);
2849 /* reset HW current stats*/
2850 hw_stats->vfgprc = 0;
2851 hw_stats->vfgorc = 0;
2852 hw_stats->vfgptc = 0;
2853 hw_stats->vfgotc = 0;
2854 hw_stats->vfmprc = 0;
2859 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2861 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2863 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2864 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2865 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2866 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2867 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2868 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2869 dev_info->max_vfs = dev->pci_dev->max_vfs;
2870 if (hw->mac.type == ixgbe_mac_82598EB)
2871 dev_info->max_vmdq_pools = ETH_16_POOLS;
2873 dev_info->max_vmdq_pools = ETH_64_POOLS;
2874 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2875 dev_info->rx_offload_capa =
2876 DEV_RX_OFFLOAD_VLAN_STRIP |
2877 DEV_RX_OFFLOAD_IPV4_CKSUM |
2878 DEV_RX_OFFLOAD_UDP_CKSUM |
2879 DEV_RX_OFFLOAD_TCP_CKSUM;
2882 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2885 if ((hw->mac.type == ixgbe_mac_82599EB ||
2886 hw->mac.type == ixgbe_mac_X540) &&
2887 !RTE_ETH_DEV_SRIOV(dev).active)
2888 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2890 if (hw->mac.type == ixgbe_mac_X550 ||
2891 hw->mac.type == ixgbe_mac_X550EM_x)
2892 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2894 dev_info->tx_offload_capa =
2895 DEV_TX_OFFLOAD_VLAN_INSERT |
2896 DEV_TX_OFFLOAD_IPV4_CKSUM |
2897 DEV_TX_OFFLOAD_UDP_CKSUM |
2898 DEV_TX_OFFLOAD_TCP_CKSUM |
2899 DEV_TX_OFFLOAD_SCTP_CKSUM |
2900 DEV_TX_OFFLOAD_TCP_TSO;
2902 if (hw->mac.type == ixgbe_mac_X550 ||
2903 hw->mac.type == ixgbe_mac_X550EM_x)
2904 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2906 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2908 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2909 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2910 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2912 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2916 dev_info->default_txconf = (struct rte_eth_txconf) {
2918 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2919 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2920 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2922 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2923 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2924 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2925 ETH_TXQ_FLAGS_NOOFFLOADS,
2928 dev_info->rx_desc_lim = rx_desc_lim;
2929 dev_info->tx_desc_lim = tx_desc_lim;
2931 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2932 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2933 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2936 static const uint32_t *
2937 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2939 static const uint32_t ptypes[] = {
2940 /* For non-vec functions,
2941 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
2942 * for vec functions,
2943 * refers to _recv_raw_pkts_vec().
2947 RTE_PTYPE_L3_IPV4_EXT,
2949 RTE_PTYPE_L3_IPV6_EXT,
2953 RTE_PTYPE_TUNNEL_IP,
2954 RTE_PTYPE_INNER_L3_IPV6,
2955 RTE_PTYPE_INNER_L3_IPV6_EXT,
2956 RTE_PTYPE_INNER_L4_TCP,
2957 RTE_PTYPE_INNER_L4_UDP,
2961 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
2962 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
2963 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
2964 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
2970 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2971 struct rte_eth_dev_info *dev_info)
2973 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2975 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2976 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2977 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2978 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2979 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2980 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2981 dev_info->max_vfs = dev->pci_dev->max_vfs;
2982 if (hw->mac.type == ixgbe_mac_82598EB)
2983 dev_info->max_vmdq_pools = ETH_16_POOLS;
2985 dev_info->max_vmdq_pools = ETH_64_POOLS;
2986 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2987 DEV_RX_OFFLOAD_IPV4_CKSUM |
2988 DEV_RX_OFFLOAD_UDP_CKSUM |
2989 DEV_RX_OFFLOAD_TCP_CKSUM;
2990 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2991 DEV_TX_OFFLOAD_IPV4_CKSUM |
2992 DEV_TX_OFFLOAD_UDP_CKSUM |
2993 DEV_TX_OFFLOAD_TCP_CKSUM |
2994 DEV_TX_OFFLOAD_SCTP_CKSUM |
2995 DEV_TX_OFFLOAD_TCP_TSO;
2997 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2999 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3000 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3001 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3003 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3007 dev_info->default_txconf = (struct rte_eth_txconf) {
3009 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3010 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3011 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3013 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3014 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3015 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3016 ETH_TXQ_FLAGS_NOOFFLOADS,
3019 dev_info->rx_desc_lim = rx_desc_lim;
3020 dev_info->tx_desc_lim = tx_desc_lim;
3023 /* return 0 means link status changed, -1 means not changed */
3025 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3027 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3028 struct rte_eth_link link, old;
3029 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3033 link.link_status = 0;
3034 link.link_speed = 0;
3035 link.link_duplex = 0;
3036 memset(&old, 0, sizeof(old));
3037 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3039 hw->mac.get_link_status = true;
3041 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3042 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3043 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3045 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3048 link.link_speed = ETH_LINK_SPEED_100;
3049 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3050 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3051 if (link.link_status == old.link_status)
3057 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3058 if (link.link_status == old.link_status)
3062 link.link_status = 1;
3063 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3065 switch (link_speed) {
3067 case IXGBE_LINK_SPEED_UNKNOWN:
3068 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3069 link.link_speed = ETH_LINK_SPEED_100;
3072 case IXGBE_LINK_SPEED_100_FULL:
3073 link.link_speed = ETH_LINK_SPEED_100;
3076 case IXGBE_LINK_SPEED_1GB_FULL:
3077 link.link_speed = ETH_LINK_SPEED_1000;
3080 case IXGBE_LINK_SPEED_10GB_FULL:
3081 link.link_speed = ETH_LINK_SPEED_10000;
3084 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3086 if (link.link_status == old.link_status)
3093 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3095 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3098 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3099 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3100 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3104 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3106 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3109 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3110 fctrl &= (~IXGBE_FCTRL_UPE);
3111 if (dev->data->all_multicast == 1)
3112 fctrl |= IXGBE_FCTRL_MPE;
3114 fctrl &= (~IXGBE_FCTRL_MPE);
3115 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3119 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3121 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3124 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3125 fctrl |= IXGBE_FCTRL_MPE;
3126 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3130 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3132 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3135 if (dev->data->promiscuous == 1)
3136 return; /* must remain in all_multicast mode */
3138 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3139 fctrl &= (~IXGBE_FCTRL_MPE);
3140 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3144 * It clears the interrupt causes and enables the interrupt.
3145 * It will be called once only during nic initialized.
3148 * Pointer to struct rte_eth_dev.
3151 * - On success, zero.
3152 * - On failure, a negative value.
3155 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3157 struct ixgbe_interrupt *intr =
3158 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3160 ixgbe_dev_link_status_print(dev);
3161 intr->mask |= IXGBE_EICR_LSC;
3167 * It clears the interrupt causes and enables the interrupt.
3168 * It will be called once only during nic initialized.
3171 * Pointer to struct rte_eth_dev.
3174 * - On success, zero.
3175 * - On failure, a negative value.
3178 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3180 struct ixgbe_interrupt *intr =
3181 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3183 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3189 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3192 * Pointer to struct rte_eth_dev.
3195 * - On success, zero.
3196 * - On failure, a negative value.
3199 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3202 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3203 struct ixgbe_interrupt *intr =
3204 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3206 /* clear all cause mask */
3207 ixgbe_disable_intr(hw);
3209 /* read-on-clear nic registers here */
3210 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3211 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3215 /* set flag for async link update */
3216 if (eicr & IXGBE_EICR_LSC)
3217 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3219 if (eicr & IXGBE_EICR_MAILBOX)
3220 intr->flags |= IXGBE_FLAG_MAILBOX;
3222 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3223 hw->phy.type == ixgbe_phy_x550em_ext_t &&
3224 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3225 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3231 * It gets and then prints the link status.
3234 * Pointer to struct rte_eth_dev.
3237 * - On success, zero.
3238 * - On failure, a negative value.
3241 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3243 struct rte_eth_link link;
3245 memset(&link, 0, sizeof(link));
3246 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3247 if (link.link_status) {
3248 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3249 (int)(dev->data->port_id),
3250 (unsigned)link.link_speed,
3251 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3252 "full-duplex" : "half-duplex");
3254 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3255 (int)(dev->data->port_id));
3257 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3258 dev->pci_dev->addr.domain,
3259 dev->pci_dev->addr.bus,
3260 dev->pci_dev->addr.devid,
3261 dev->pci_dev->addr.function);
3265 * It executes link_update after knowing an interrupt occurred.
3268 * Pointer to struct rte_eth_dev.
3271 * - On success, zero.
3272 * - On failure, a negative value.
3275 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3277 struct ixgbe_interrupt *intr =
3278 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3280 struct rte_eth_link link;
3281 int intr_enable_delay = false;
3282 struct ixgbe_hw *hw =
3283 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3285 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3287 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3288 ixgbe_pf_mbx_process(dev);
3289 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3292 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3293 ixgbe_handle_lasi(hw);
3294 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3297 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3298 /* get the link status before link update, for predicting later */
3299 memset(&link, 0, sizeof(link));
3300 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3302 ixgbe_dev_link_update(dev, 0);
3305 if (!link.link_status)
3306 /* handle it 1 sec later, wait it being stable */
3307 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3308 /* likely to down */
3310 /* handle it 4 sec later, wait it being stable */
3311 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3313 ixgbe_dev_link_status_print(dev);
3315 intr_enable_delay = true;
3318 if (intr_enable_delay) {
3319 if (rte_eal_alarm_set(timeout * 1000,
3320 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3321 PMD_DRV_LOG(ERR, "Error setting alarm");
3323 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3324 ixgbe_enable_intr(dev);
3325 rte_intr_enable(&(dev->pci_dev->intr_handle));
3333 * Interrupt handler which shall be registered for alarm callback for delayed
3334 * handling specific interrupt to wait for the stable nic state. As the
3335 * NIC interrupt state is not stable for ixgbe after link is just down,
3336 * it needs to wait 4 seconds to get the stable status.
3339 * Pointer to interrupt handle.
3341 * The address of parameter (struct rte_eth_dev *) regsitered before.
3347 ixgbe_dev_interrupt_delayed_handler(void *param)
3349 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3350 struct ixgbe_interrupt *intr =
3351 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3352 struct ixgbe_hw *hw =
3353 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3356 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3357 if (eicr & IXGBE_EICR_MAILBOX)
3358 ixgbe_pf_mbx_process(dev);
3360 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3361 ixgbe_handle_lasi(hw);
3362 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3365 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3366 ixgbe_dev_link_update(dev, 0);
3367 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3368 ixgbe_dev_link_status_print(dev);
3369 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3372 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3373 ixgbe_enable_intr(dev);
3374 rte_intr_enable(&(dev->pci_dev->intr_handle));
3378 * Interrupt handler triggered by NIC for handling
3379 * specific interrupt.
3382 * Pointer to interrupt handle.
3384 * The address of parameter (struct rte_eth_dev *) regsitered before.
3390 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3393 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3395 ixgbe_dev_interrupt_get_status(dev);
3396 ixgbe_dev_interrupt_action(dev);
3400 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3402 struct ixgbe_hw *hw;
3404 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3405 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3409 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3411 struct ixgbe_hw *hw;
3413 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3414 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3418 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3420 struct ixgbe_hw *hw;
3426 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3428 fc_conf->pause_time = hw->fc.pause_time;
3429 fc_conf->high_water = hw->fc.high_water[0];
3430 fc_conf->low_water = hw->fc.low_water[0];
3431 fc_conf->send_xon = hw->fc.send_xon;
3432 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3435 * Return rx_pause status according to actual setting of
3438 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3439 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3445 * Return tx_pause status according to actual setting of
3448 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3449 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3454 if (rx_pause && tx_pause)
3455 fc_conf->mode = RTE_FC_FULL;
3457 fc_conf->mode = RTE_FC_RX_PAUSE;
3459 fc_conf->mode = RTE_FC_TX_PAUSE;
3461 fc_conf->mode = RTE_FC_NONE;
3467 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3469 struct ixgbe_hw *hw;
3471 uint32_t rx_buf_size;
3472 uint32_t max_high_water;
3474 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3481 PMD_INIT_FUNC_TRACE();
3483 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3484 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3485 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3488 * At least reserve one Ethernet frame for watermark
3489 * high_water/low_water in kilo bytes for ixgbe
3491 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3492 if ((fc_conf->high_water > max_high_water) ||
3493 (fc_conf->high_water < fc_conf->low_water)) {
3494 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3495 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3499 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3500 hw->fc.pause_time = fc_conf->pause_time;
3501 hw->fc.high_water[0] = fc_conf->high_water;
3502 hw->fc.low_water[0] = fc_conf->low_water;
3503 hw->fc.send_xon = fc_conf->send_xon;
3504 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3506 err = ixgbe_fc_enable(hw);
3508 /* Not negotiated is not an error case */
3509 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3511 /* check if we want to forward MAC frames - driver doesn't have native
3512 * capability to do that, so we'll write the registers ourselves */
3514 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3516 /* set or clear MFLCN.PMCF bit depending on configuration */
3517 if (fc_conf->mac_ctrl_frame_fwd != 0)
3518 mflcn |= IXGBE_MFLCN_PMCF;
3520 mflcn &= ~IXGBE_MFLCN_PMCF;
3522 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3523 IXGBE_WRITE_FLUSH(hw);
3528 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3533 * ixgbe_pfc_enable_generic - Enable flow control
3534 * @hw: pointer to hardware structure
3535 * @tc_num: traffic class number
3536 * Enable flow control according to the current settings.
3539 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3542 uint32_t mflcn_reg, fccfg_reg;
3544 uint32_t fcrtl, fcrth;
3548 /* Validate the water mark configuration */
3549 if (!hw->fc.pause_time) {
3550 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3554 /* Low water mark of zero causes XOFF floods */
3555 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3556 /* High/Low water can not be 0 */
3557 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3558 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3559 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3563 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3564 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3565 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3569 /* Negotiate the fc mode to use */
3570 ixgbe_fc_autoneg(hw);
3572 /* Disable any previous flow control settings */
3573 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3574 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3576 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3577 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3579 switch (hw->fc.current_mode) {
3582 * If the count of enabled RX Priority Flow control >1,
3583 * and the TX pause can not be disabled
3586 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3587 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3588 if (reg & IXGBE_FCRTH_FCEN)
3592 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3594 case ixgbe_fc_rx_pause:
3596 * Rx Flow control is enabled and Tx Flow control is
3597 * disabled by software override. Since there really
3598 * isn't a way to advertise that we are capable of RX
3599 * Pause ONLY, we will advertise that we support both
3600 * symmetric and asymmetric Rx PAUSE. Later, we will
3601 * disable the adapter's ability to send PAUSE frames.
3603 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3605 * If the count of enabled RX Priority Flow control >1,
3606 * and the TX pause can not be disabled
3609 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3610 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3611 if (reg & IXGBE_FCRTH_FCEN)
3615 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3617 case ixgbe_fc_tx_pause:
3619 * Tx Flow control is enabled, and Rx Flow control is
3620 * disabled by software override.
3622 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3625 /* Flow control (both Rx and Tx) is enabled by SW override. */
3626 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3627 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3630 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3631 ret_val = IXGBE_ERR_CONFIG;
3636 /* Set 802.3x based flow control settings. */
3637 mflcn_reg |= IXGBE_MFLCN_DPF;
3638 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3639 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3641 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3642 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3643 hw->fc.high_water[tc_num]) {
3644 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3645 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3646 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3648 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3650 * In order to prevent Tx hangs when the internal Tx
3651 * switch is enabled we must set the high water mark
3652 * to the maximum FCRTH value. This allows the Tx
3653 * switch to function even under heavy Rx workloads.
3655 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3657 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3659 /* Configure pause time (2 TCs per register) */
3660 reg = hw->fc.pause_time * 0x00010001;
3661 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3662 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3664 /* Configure flow control refresh threshold value */
3665 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3672 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3674 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3675 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3677 if (hw->mac.type != ixgbe_mac_82598EB) {
3678 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3684 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3687 uint32_t rx_buf_size;
3688 uint32_t max_high_water;
3690 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3691 struct ixgbe_hw *hw =
3692 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3693 struct ixgbe_dcb_config *dcb_config =
3694 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3696 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3703 PMD_INIT_FUNC_TRACE();
3705 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3706 tc_num = map[pfc_conf->priority];
3707 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3708 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3710 * At least reserve one Ethernet frame for watermark
3711 * high_water/low_water in kilo bytes for ixgbe
3713 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3714 if ((pfc_conf->fc.high_water > max_high_water) ||
3715 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3716 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3717 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3721 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3722 hw->fc.pause_time = pfc_conf->fc.pause_time;
3723 hw->fc.send_xon = pfc_conf->fc.send_xon;
3724 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
3725 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3727 err = ixgbe_dcb_pfc_enable(dev,tc_num);
3729 /* Not negotiated is not an error case */
3730 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3733 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3738 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3739 struct rte_eth_rss_reta_entry64 *reta_conf,
3742 uint16_t i, sp_reta_size;
3745 uint16_t idx, shift;
3746 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3749 PMD_INIT_FUNC_TRACE();
3751 if (!ixgbe_rss_update_sp(hw->mac.type)) {
3752 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3757 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3758 if (reta_size != sp_reta_size) {
3759 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3760 "(%d) doesn't match the number hardware can supported "
3761 "(%d)\n", reta_size, sp_reta_size);
3765 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3766 idx = i / RTE_RETA_GROUP_SIZE;
3767 shift = i % RTE_RETA_GROUP_SIZE;
3768 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3772 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3773 if (mask == IXGBE_4_BIT_MASK)
3776 r = IXGBE_READ_REG(hw, reta_reg);
3777 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3778 if (mask & (0x1 << j))
3779 reta |= reta_conf[idx].reta[shift + j] <<
3782 reta |= r & (IXGBE_8_BIT_MASK <<
3785 IXGBE_WRITE_REG(hw, reta_reg, reta);
3792 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3793 struct rte_eth_rss_reta_entry64 *reta_conf,
3796 uint16_t i, sp_reta_size;
3799 uint16_t idx, shift;
3800 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3803 PMD_INIT_FUNC_TRACE();
3804 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3805 if (reta_size != sp_reta_size) {
3806 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3807 "(%d) doesn't match the number hardware can supported "
3808 "(%d)\n", reta_size, sp_reta_size);
3812 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3813 idx = i / RTE_RETA_GROUP_SIZE;
3814 shift = i % RTE_RETA_GROUP_SIZE;
3815 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3820 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3821 reta = IXGBE_READ_REG(hw, reta_reg);
3822 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3823 if (mask & (0x1 << j))
3824 reta_conf[idx].reta[shift + j] =
3825 ((reta >> (CHAR_BIT * j)) &
3834 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3835 uint32_t index, uint32_t pool)
3837 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3838 uint32_t enable_addr = 1;
3840 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3844 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3846 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3848 ixgbe_clear_rar(hw, index);
3852 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3854 ixgbe_remove_rar(dev, 0);
3856 ixgbe_add_rar(dev, addr, 0, 0);
3860 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3864 struct ixgbe_hw *hw;
3865 struct rte_eth_dev_info dev_info;
3866 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3868 ixgbe_dev_info_get(dev, &dev_info);
3870 /* check that mtu is within the allowed range */
3871 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3874 /* refuse mtu that requires the support of scattered packets when this
3875 * feature has not been enabled before. */
3876 if (!dev->data->scattered_rx &&
3877 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3878 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3881 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3882 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3884 /* switch to jumbo mode if needed */
3885 if (frame_size > ETHER_MAX_LEN) {
3886 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3887 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3889 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3890 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3892 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3894 /* update max frame size */
3895 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3897 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3898 maxfrs &= 0x0000FFFF;
3899 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3900 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3906 * Virtual Function operations
3909 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3911 PMD_INIT_FUNC_TRACE();
3913 /* Clear interrupt mask to stop from interrupts being generated */
3914 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3916 IXGBE_WRITE_FLUSH(hw);
3920 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3922 PMD_INIT_FUNC_TRACE();
3924 /* VF enable interrupt autoclean */
3925 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3926 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3927 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3929 IXGBE_WRITE_FLUSH(hw);
3933 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3935 struct rte_eth_conf* conf = &dev->data->dev_conf;
3936 struct ixgbe_adapter *adapter =
3937 (struct ixgbe_adapter *)dev->data->dev_private;
3939 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3940 dev->data->port_id);
3943 * VF has no ability to enable/disable HW CRC
3944 * Keep the persistent behavior the same as Host PF
3946 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3947 if (!conf->rxmode.hw_strip_crc) {
3948 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3949 conf->rxmode.hw_strip_crc = 1;
3952 if (conf->rxmode.hw_strip_crc) {
3953 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3954 conf->rxmode.hw_strip_crc = 0;
3959 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3960 * allocation or vector Rx preconditions we will reset it.
3962 adapter->rx_bulk_alloc_allowed = true;
3963 adapter->rx_vec_allowed = true;
3969 ixgbevf_dev_start(struct rte_eth_dev *dev)
3971 struct ixgbe_hw *hw =
3972 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3973 uint32_t intr_vector = 0;
3974 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3978 PMD_INIT_FUNC_TRACE();
3980 hw->mac.ops.reset_hw(hw);
3981 hw->mac.get_link_status = true;
3983 /* negotiate mailbox API version to use with the PF. */
3984 ixgbevf_negotiate_api(hw);
3986 ixgbevf_dev_tx_init(dev);
3988 /* This can fail when allocating mbufs for descriptor rings */
3989 err = ixgbevf_dev_rx_init(dev);
3991 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3992 ixgbe_dev_clear_queues(dev);
3997 ixgbevf_set_vfta_all(dev,1);
4000 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
4001 ETH_VLAN_EXTEND_MASK;
4002 ixgbevf_vlan_offload_set(dev, mask);
4004 ixgbevf_dev_rxtx_start(dev);
4006 /* check and configure queue intr-vector mapping */
4007 if (dev->data->dev_conf.intr_conf.rxq != 0) {
4008 intr_vector = dev->data->nb_rx_queues;
4009 if (rte_intr_efd_enable(intr_handle, intr_vector))
4013 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4014 intr_handle->intr_vec =
4015 rte_zmalloc("intr_vec",
4016 dev->data->nb_rx_queues * sizeof(int), 0);
4017 if (intr_handle->intr_vec == NULL) {
4018 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4019 " intr_vec\n", dev->data->nb_rx_queues);
4023 ixgbevf_configure_msix(dev);
4025 rte_intr_enable(intr_handle);
4027 /* Re-enable interrupt for VF */
4028 ixgbevf_intr_enable(hw);
4034 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4036 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4037 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4039 PMD_INIT_FUNC_TRACE();
4041 hw->adapter_stopped = 1;
4042 ixgbe_stop_adapter(hw);
4045 * Clear what we set, but we still keep shadow_vfta to
4046 * restore after device starts
4048 ixgbevf_set_vfta_all(dev,0);
4050 /* Clear stored conf */
4051 dev->data->scattered_rx = 0;
4053 ixgbe_dev_clear_queues(dev);
4055 /* Clean datapath event and queue/vec mapping */
4056 rte_intr_efd_disable(intr_handle);
4057 if (intr_handle->intr_vec != NULL) {
4058 rte_free(intr_handle->intr_vec);
4059 intr_handle->intr_vec = NULL;
4064 ixgbevf_dev_close(struct rte_eth_dev *dev)
4066 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4068 PMD_INIT_FUNC_TRACE();
4072 ixgbevf_dev_stop(dev);
4074 ixgbe_dev_free_queues(dev);
4077 * Remove the VF MAC address ro ensure
4078 * that the VF traffic goes to the PF
4079 * after stop, close and detach of the VF
4081 ixgbevf_remove_mac_addr(dev, 0);
4084 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4086 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4087 struct ixgbe_vfta * shadow_vfta =
4088 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4089 int i = 0, j = 0, vfta = 0, mask = 1;
4091 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
4092 vfta = shadow_vfta->vfta[i];
4095 for (j = 0; j < 32; j++){
4097 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4106 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4108 struct ixgbe_hw *hw =
4109 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4110 struct ixgbe_vfta * shadow_vfta =
4111 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4112 uint32_t vid_idx = 0;
4113 uint32_t vid_bit = 0;
4116 PMD_INIT_FUNC_TRACE();
4118 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4119 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4121 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4124 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4125 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4127 /* Save what we set and retore it after device reset */
4129 shadow_vfta->vfta[vid_idx] |= vid_bit;
4131 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4137 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4139 struct ixgbe_hw *hw =
4140 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4143 PMD_INIT_FUNC_TRACE();
4145 if (queue >= hw->mac.max_rx_queues)
4148 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4150 ctrl |= IXGBE_RXDCTL_VME;
4152 ctrl &= ~IXGBE_RXDCTL_VME;
4153 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4155 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4159 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4161 struct ixgbe_hw *hw =
4162 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4166 /* VF function only support hw strip feature, others are not support */
4167 if (mask & ETH_VLAN_STRIP_MASK) {
4168 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4170 for (i = 0; i < hw->mac.max_rx_queues; i++)
4171 ixgbevf_vlan_strip_queue_set(dev,i,on);
4176 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4180 /* we only need to do this if VMDq is enabled */
4181 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4182 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4183 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4191 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4193 uint32_t vector = 0;
4194 switch (hw->mac.mc_filter_type) {
4195 case 0: /* use bits [47:36] of the address */
4196 vector = ((uc_addr->addr_bytes[4] >> 4) |
4197 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4199 case 1: /* use bits [46:35] of the address */
4200 vector = ((uc_addr->addr_bytes[4] >> 3) |
4201 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4203 case 2: /* use bits [45:34] of the address */
4204 vector = ((uc_addr->addr_bytes[4] >> 2) |
4205 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4207 case 3: /* use bits [43:32] of the address */
4208 vector = ((uc_addr->addr_bytes[4]) |
4209 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4211 default: /* Invalid mc_filter_type */
4215 /* vector can only be 12-bits or boundary will be exceeded */
4221 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4229 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4230 const uint32_t ixgbe_uta_bit_shift = 5;
4231 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4232 const uint32_t bit1 = 0x1;
4234 struct ixgbe_hw *hw =
4235 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4236 struct ixgbe_uta_info *uta_info =
4237 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4239 /* The UTA table only exists on 82599 hardware and newer */
4240 if (hw->mac.type < ixgbe_mac_82599EB)
4243 vector = ixgbe_uta_vector(hw,mac_addr);
4244 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4245 uta_shift = vector & ixgbe_uta_bit_mask;
4247 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4251 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4253 uta_info->uta_in_use++;
4254 reg_val |= (bit1 << uta_shift);
4255 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4257 uta_info->uta_in_use--;
4258 reg_val &= ~(bit1 << uta_shift);
4259 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4262 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4264 if (uta_info->uta_in_use > 0)
4265 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4266 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4268 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4274 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4277 struct ixgbe_hw *hw =
4278 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4279 struct ixgbe_uta_info *uta_info =
4280 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4282 /* The UTA table only exists on 82599 hardware and newer */
4283 if (hw->mac.type < ixgbe_mac_82599EB)
4287 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4288 uta_info->uta_shadow[i] = ~0;
4289 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4292 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4293 uta_info->uta_shadow[i] = 0;
4294 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4302 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4304 uint32_t new_val = orig_val;
4306 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4307 new_val |= IXGBE_VMOLR_AUPE;
4308 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4309 new_val |= IXGBE_VMOLR_ROMPE;
4310 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4311 new_val |= IXGBE_VMOLR_ROPE;
4312 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4313 new_val |= IXGBE_VMOLR_BAM;
4314 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4315 new_val |= IXGBE_VMOLR_MPE;
4321 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4322 uint16_t rx_mask, uint8_t on)
4326 struct ixgbe_hw *hw =
4327 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4328 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4330 if (hw->mac.type == ixgbe_mac_82598EB) {
4331 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4332 " on 82599 hardware and newer");
4335 if (ixgbe_vmdq_mode_check(hw) < 0)
4338 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4345 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4351 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4355 const uint8_t bit1 = 0x1;
4357 struct ixgbe_hw *hw =
4358 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4360 if (ixgbe_vmdq_mode_check(hw) < 0)
4363 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4364 reg = IXGBE_READ_REG(hw, addr);
4372 IXGBE_WRITE_REG(hw, addr,reg);
4378 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4382 const uint8_t bit1 = 0x1;
4384 struct ixgbe_hw *hw =
4385 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4387 if (ixgbe_vmdq_mode_check(hw) < 0)
4390 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4391 reg = IXGBE_READ_REG(hw, addr);
4399 IXGBE_WRITE_REG(hw, addr,reg);
4405 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4406 uint64_t pool_mask, uint8_t vlan_on)
4410 struct ixgbe_hw *hw =
4411 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4413 if (ixgbe_vmdq_mode_check(hw) < 0)
4415 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4416 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4417 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4425 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
4426 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
4427 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
4428 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
4429 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4430 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4431 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4434 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4435 struct rte_eth_mirror_conf *mirror_conf,
4436 uint8_t rule_id, uint8_t on)
4438 uint32_t mr_ctl,vlvf;
4439 uint32_t mp_lsb = 0;
4440 uint32_t mv_msb = 0;
4441 uint32_t mv_lsb = 0;
4442 uint32_t mp_msb = 0;
4445 uint64_t vlan_mask = 0;
4447 const uint8_t pool_mask_offset = 32;
4448 const uint8_t vlan_mask_offset = 32;
4449 const uint8_t dst_pool_offset = 8;
4450 const uint8_t rule_mr_offset = 4;
4451 const uint8_t mirror_rule_mask= 0x0F;
4453 struct ixgbe_mirror_info *mr_info =
4454 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4455 struct ixgbe_hw *hw =
4456 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4457 uint8_t mirror_type = 0;
4459 if (ixgbe_vmdq_mode_check(hw) < 0)
4462 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4465 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4466 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4467 mirror_conf->rule_type);
4471 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4472 mirror_type |= IXGBE_MRCTL_VLME;
4473 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4474 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4475 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4476 /* search vlan id related pool vlan filter index */
4477 reg_index = ixgbe_find_vlvf_slot(hw,
4478 mirror_conf->vlan.vlan_id[i]);
4481 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4482 if ((vlvf & IXGBE_VLVF_VIEN) &&
4483 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4484 mirror_conf->vlan.vlan_id[i]))
4485 vlan_mask |= (1ULL << reg_index);
4492 mv_lsb = vlan_mask & 0xFFFFFFFF;
4493 mv_msb = vlan_mask >> vlan_mask_offset;
4495 mr_info->mr_conf[rule_id].vlan.vlan_mask =
4496 mirror_conf->vlan.vlan_mask;
4497 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4498 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4499 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4500 mirror_conf->vlan.vlan_id[i];
4505 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4506 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4507 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4512 * if enable pool mirror, write related pool mask register,if disable
4513 * pool mirror, clear PFMRVM register
4515 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4516 mirror_type |= IXGBE_MRCTL_VPME;
4518 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4519 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4520 mr_info->mr_conf[rule_id].pool_mask =
4521 mirror_conf->pool_mask;
4526 mr_info->mr_conf[rule_id].pool_mask = 0;
4529 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4530 mirror_type |= IXGBE_MRCTL_UPME;
4531 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4532 mirror_type |= IXGBE_MRCTL_DPME;
4534 /* read mirror control register and recalculate it */
4535 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4538 mr_ctl |= mirror_type;
4539 mr_ctl &= mirror_rule_mask;
4540 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4542 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4544 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4545 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4547 /* write mirrror control register */
4548 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4550 /* write pool mirrror control register */
4551 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4552 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4553 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4556 /* write VLAN mirrror control register */
4557 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4558 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4559 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4567 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4570 uint32_t lsb_val = 0;
4571 uint32_t msb_val = 0;
4572 const uint8_t rule_mr_offset = 4;
4574 struct ixgbe_hw *hw =
4575 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4576 struct ixgbe_mirror_info *mr_info =
4577 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4579 if (ixgbe_vmdq_mode_check(hw) < 0)
4582 memset(&mr_info->mr_conf[rule_id], 0,
4583 sizeof(struct rte_eth_mirror_conf));
4585 /* clear PFVMCTL register */
4586 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4588 /* clear pool mask register */
4589 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4590 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4592 /* clear vlan mask register */
4593 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4594 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4600 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4603 struct ixgbe_hw *hw =
4604 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4606 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4607 mask |= (1 << IXGBE_MISC_VEC_ID);
4608 RTE_SET_USED(queue_id);
4609 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4611 rte_intr_enable(&dev->pci_dev->intr_handle);
4617 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4620 struct ixgbe_hw *hw =
4621 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4623 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4624 mask &= ~(1 << IXGBE_MISC_VEC_ID);
4625 RTE_SET_USED(queue_id);
4626 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4632 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4635 struct ixgbe_hw *hw =
4636 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4637 struct ixgbe_interrupt *intr =
4638 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4640 if (queue_id < 16) {
4641 ixgbe_disable_intr(hw);
4642 intr->mask |= (1 << queue_id);
4643 ixgbe_enable_intr(dev);
4644 } else if (queue_id < 32) {
4645 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4646 mask &= (1 << queue_id);
4647 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4648 } else if (queue_id < 64) {
4649 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4650 mask &= (1 << (queue_id - 32));
4651 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4653 rte_intr_enable(&dev->pci_dev->intr_handle);
4659 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4662 struct ixgbe_hw *hw =
4663 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4664 struct ixgbe_interrupt *intr =
4665 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4667 if (queue_id < 16) {
4668 ixgbe_disable_intr(hw);
4669 intr->mask &= ~(1 << queue_id);
4670 ixgbe_enable_intr(dev);
4671 } else if (queue_id < 32) {
4672 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4673 mask &= ~(1 << queue_id);
4674 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4675 } else if (queue_id < 64) {
4676 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4677 mask &= ~(1 << (queue_id - 32));
4678 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4685 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4686 uint8_t queue, uint8_t msix_vector)
4690 if (direction == -1) {
4692 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4693 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4696 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4698 /* rx or tx cause */
4699 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4700 idx = ((16 * (queue & 1)) + (8 * direction));
4701 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4702 tmp &= ~(0xFF << idx);
4703 tmp |= (msix_vector << idx);
4704 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4709 * set the IVAR registers, mapping interrupt causes to vectors
4711 * pointer to ixgbe_hw struct
4713 * 0 for Rx, 1 for Tx, -1 for other causes
4715 * queue to map the corresponding interrupt to
4717 * the vector to map to the corresponding queue
4720 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4721 uint8_t queue, uint8_t msix_vector)
4725 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4726 if (hw->mac.type == ixgbe_mac_82598EB) {
4727 if (direction == -1)
4729 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4730 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4731 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4732 tmp |= (msix_vector << (8 * (queue & 0x3)));
4733 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4734 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4735 (hw->mac.type == ixgbe_mac_X540)) {
4736 if (direction == -1) {
4738 idx = ((queue & 1) * 8);
4739 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4740 tmp &= ~(0xFF << idx);
4741 tmp |= (msix_vector << idx);
4742 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4744 /* rx or tx causes */
4745 idx = ((16 * (queue & 1)) + (8 * direction));
4746 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4747 tmp &= ~(0xFF << idx);
4748 tmp |= (msix_vector << idx);
4749 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4755 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4757 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4758 struct ixgbe_hw *hw =
4759 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4761 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4763 /* won't configure msix register if no mapping is done
4764 * between intr vector and event fd.
4766 if (!rte_intr_dp_is_en(intr_handle))
4769 /* Configure all RX queues of VF */
4770 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4771 /* Force all queue use vector 0,
4772 * as IXGBE_VF_MAXMSIVECOTR = 1
4774 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4775 intr_handle->intr_vec[q_idx] = vector_idx;
4778 /* Configure VF other cause ivar */
4779 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4783 * Sets up the hardware to properly generate MSI-X interrupts
4785 * board private structure
4788 ixgbe_configure_msix(struct rte_eth_dev *dev)
4790 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4791 struct ixgbe_hw *hw =
4792 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4793 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4794 uint32_t vec = IXGBE_MISC_VEC_ID;
4798 /* won't configure msix register if no mapping is done
4799 * between intr vector and event fd
4801 if (!rte_intr_dp_is_en(intr_handle))
4804 if (rte_intr_allow_others(intr_handle))
4805 vec = base = IXGBE_RX_VEC_START;
4807 /* setup GPIE for MSI-x mode */
4808 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4809 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4810 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4811 /* auto clearing and auto setting corresponding bits in EIMS
4812 * when MSI-X interrupt is triggered
4814 if (hw->mac.type == ixgbe_mac_82598EB) {
4815 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4817 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4818 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4820 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4822 /* Populate the IVAR table and set the ITR values to the
4823 * corresponding register.
4825 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4827 /* by default, 1:1 mapping */
4828 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4829 intr_handle->intr_vec[queue_id] = vec;
4830 if (vec < base + intr_handle->nb_efd - 1)
4834 switch (hw->mac.type) {
4835 case ixgbe_mac_82598EB:
4836 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4839 case ixgbe_mac_82599EB:
4840 case ixgbe_mac_X540:
4841 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4846 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4847 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4849 /* set up to autoclear timer, and the vectors */
4850 mask = IXGBE_EIMS_ENABLE_MASK;
4851 mask &= ~(IXGBE_EIMS_OTHER |
4852 IXGBE_EIMS_MAILBOX |
4855 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4858 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4859 uint16_t queue_idx, uint16_t tx_rate)
4861 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4862 uint32_t rf_dec, rf_int;
4864 uint16_t link_speed = dev->data->dev_link.link_speed;
4866 if (queue_idx >= hw->mac.max_tx_queues)
4870 /* Calculate the rate factor values to set */
4871 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4872 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4873 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4875 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4876 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4877 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4878 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4884 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4885 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4888 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4889 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4890 IXGBE_MAX_JUMBO_FRAME_SIZE))
4891 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4892 IXGBE_MMW_SIZE_JUMBO_FRAME);
4894 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4895 IXGBE_MMW_SIZE_DEFAULT);
4897 /* Set RTTBCNRC of queue X */
4898 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4899 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4900 IXGBE_WRITE_FLUSH(hw);
4905 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4906 uint16_t tx_rate, uint64_t q_msk)
4908 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4909 struct ixgbe_vf_info *vfinfo =
4910 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4911 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4912 uint32_t queue_stride =
4913 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4914 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4915 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4916 uint16_t total_rate = 0;
4918 if (queue_end >= hw->mac.max_tx_queues)
4921 if (vfinfo != NULL) {
4922 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4925 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4927 total_rate += vfinfo[vf_idx].tx_rate[idx];
4932 /* Store tx_rate for this vf. */
4933 for (idx = 0; idx < nb_q_per_pool; idx++) {
4934 if (((uint64_t)0x1 << idx) & q_msk) {
4935 if (vfinfo[vf].tx_rate[idx] != tx_rate)
4936 vfinfo[vf].tx_rate[idx] = tx_rate;
4937 total_rate += tx_rate;
4941 if (total_rate > dev->data->dev_link.link_speed) {
4943 * Reset stored TX rate of the VF if it causes exceed
4946 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4950 /* Set RTTBCNRC of each queue/pool for vf X */
4951 for (; queue_idx <= queue_end; queue_idx++) {
4953 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4961 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4962 __attribute__((unused)) uint32_t index,
4963 __attribute__((unused)) uint32_t pool)
4965 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4969 * On a 82599 VF, adding again the same MAC addr is not an idempotent
4970 * operation. Trap this case to avoid exhausting the [very limited]
4971 * set of PF resources used to store VF MAC addresses.
4973 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4975 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4978 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4982 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4984 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4985 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4986 struct ether_addr *mac_addr;
4991 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4992 * not support the deletion of a given MAC address.
4993 * Instead, it imposes to delete all MAC addresses, then to add again
4994 * all MAC addresses with the exception of the one to be deleted.
4996 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4999 * Add again all MAC addresses, with the exception of the deleted one
5000 * and of the permanent MAC address.
5002 for (i = 0, mac_addr = dev->data->mac_addrs;
5003 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5004 /* Skip the deleted MAC address */
5007 /* Skip NULL MAC addresses */
5008 if (is_zero_ether_addr(mac_addr))
5010 /* Skip the permanent MAC address */
5011 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5013 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5016 "Adding again MAC address "
5017 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5019 mac_addr->addr_bytes[0],
5020 mac_addr->addr_bytes[1],
5021 mac_addr->addr_bytes[2],
5022 mac_addr->addr_bytes[3],
5023 mac_addr->addr_bytes[4],
5024 mac_addr->addr_bytes[5],
5030 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5032 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5034 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5037 #define MAC_TYPE_FILTER_SUP(type) do {\
5038 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5039 (type) != ixgbe_mac_X550)\
5044 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5045 struct rte_eth_syn_filter *filter,
5048 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5051 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5054 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5057 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5059 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5060 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5062 if (filter->hig_pri)
5063 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5065 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5067 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5069 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5071 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5072 IXGBE_WRITE_FLUSH(hw);
5077 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5078 struct rte_eth_syn_filter *filter)
5080 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5081 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5083 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5084 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5085 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5092 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5093 enum rte_filter_op filter_op,
5096 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5099 MAC_TYPE_FILTER_SUP(hw->mac.type);
5101 if (filter_op == RTE_ETH_FILTER_NOP)
5105 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5110 switch (filter_op) {
5111 case RTE_ETH_FILTER_ADD:
5112 ret = ixgbe_syn_filter_set(dev,
5113 (struct rte_eth_syn_filter *)arg,
5116 case RTE_ETH_FILTER_DELETE:
5117 ret = ixgbe_syn_filter_set(dev,
5118 (struct rte_eth_syn_filter *)arg,
5121 case RTE_ETH_FILTER_GET:
5122 ret = ixgbe_syn_filter_get(dev,
5123 (struct rte_eth_syn_filter *)arg);
5126 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5135 static inline enum ixgbe_5tuple_protocol
5136 convert_protocol_type(uint8_t protocol_value)
5138 if (protocol_value == IPPROTO_TCP)
5139 return IXGBE_FILTER_PROTOCOL_TCP;
5140 else if (protocol_value == IPPROTO_UDP)
5141 return IXGBE_FILTER_PROTOCOL_UDP;
5142 else if (protocol_value == IPPROTO_SCTP)
5143 return IXGBE_FILTER_PROTOCOL_SCTP;
5145 return IXGBE_FILTER_PROTOCOL_NONE;
5149 * add a 5tuple filter
5152 * dev: Pointer to struct rte_eth_dev.
5153 * index: the index the filter allocates.
5154 * filter: ponter to the filter that will be added.
5155 * rx_queue: the queue id the filter assigned to.
5158 * - On success, zero.
5159 * - On failure, a negative value.
5162 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5163 struct ixgbe_5tuple_filter *filter)
5165 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5166 struct ixgbe_filter_info *filter_info =
5167 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5169 uint32_t ftqf, sdpqf;
5170 uint32_t l34timir = 0;
5171 uint8_t mask = 0xff;
5174 * look for an unused 5tuple filter index,
5175 * and insert the filter to list.
5177 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5178 idx = i / (sizeof(uint32_t) * NBBY);
5179 shift = i % (sizeof(uint32_t) * NBBY);
5180 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5181 filter_info->fivetuple_mask[idx] |= 1 << shift;
5183 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5189 if (i >= IXGBE_MAX_FTQF_FILTERS) {
5190 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5194 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5195 IXGBE_SDPQF_DSTPORT_SHIFT);
5196 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5198 ftqf = (uint32_t)(filter->filter_info.proto &
5199 IXGBE_FTQF_PROTOCOL_MASK);
5200 ftqf |= (uint32_t)((filter->filter_info.priority &
5201 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5202 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5203 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5204 if (filter->filter_info.dst_ip_mask == 0)
5205 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5206 if (filter->filter_info.src_port_mask == 0)
5207 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5208 if (filter->filter_info.dst_port_mask == 0)
5209 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5210 if (filter->filter_info.proto_mask == 0)
5211 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5212 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5213 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5214 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5216 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5217 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5218 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5219 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5221 l34timir |= IXGBE_L34T_IMIR_RESERVE;
5222 l34timir |= (uint32_t)(filter->queue <<
5223 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5224 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5229 * remove a 5tuple filter
5232 * dev: Pointer to struct rte_eth_dev.
5233 * filter: the pointer of the filter will be removed.
5236 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5237 struct ixgbe_5tuple_filter *filter)
5239 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5240 struct ixgbe_filter_info *filter_info =
5241 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5242 uint16_t index = filter->index;
5244 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5245 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5246 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5249 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5250 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5251 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5252 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5253 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5257 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5259 struct ixgbe_hw *hw;
5260 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5262 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5264 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5267 /* refuse mtu that requires the support of scattered packets when this
5268 * feature has not been enabled before. */
5269 if (!dev->data->scattered_rx &&
5270 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5271 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5275 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5276 * request of the version 2.0 of the mailbox API.
5277 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5278 * of the mailbox API.
5279 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5280 * prior to 3.11.33 which contains the following change:
5281 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5283 ixgbevf_rlpml_set_vf(hw, max_frame);
5285 /* update max frame size */
5286 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5290 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
5291 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5295 static inline struct ixgbe_5tuple_filter *
5296 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5297 struct ixgbe_5tuple_filter_info *key)
5299 struct ixgbe_5tuple_filter *it;
5301 TAILQ_FOREACH(it, filter_list, entries) {
5302 if (memcmp(key, &it->filter_info,
5303 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5310 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5312 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5313 struct ixgbe_5tuple_filter_info *filter_info)
5315 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5316 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5317 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5320 switch (filter->dst_ip_mask) {
5322 filter_info->dst_ip_mask = 0;
5323 filter_info->dst_ip = filter->dst_ip;
5326 filter_info->dst_ip_mask = 1;
5329 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5333 switch (filter->src_ip_mask) {
5335 filter_info->src_ip_mask = 0;
5336 filter_info->src_ip = filter->src_ip;
5339 filter_info->src_ip_mask = 1;
5342 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5346 switch (filter->dst_port_mask) {
5348 filter_info->dst_port_mask = 0;
5349 filter_info->dst_port = filter->dst_port;
5352 filter_info->dst_port_mask = 1;
5355 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5359 switch (filter->src_port_mask) {
5361 filter_info->src_port_mask = 0;
5362 filter_info->src_port = filter->src_port;
5365 filter_info->src_port_mask = 1;
5368 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5372 switch (filter->proto_mask) {
5374 filter_info->proto_mask = 0;
5375 filter_info->proto =
5376 convert_protocol_type(filter->proto);
5379 filter_info->proto_mask = 1;
5382 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5386 filter_info->priority = (uint8_t)filter->priority;
5391 * add or delete a ntuple filter
5394 * dev: Pointer to struct rte_eth_dev.
5395 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5396 * add: if true, add filter, if false, remove filter
5399 * - On success, zero.
5400 * - On failure, a negative value.
5403 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5404 struct rte_eth_ntuple_filter *ntuple_filter,
5407 struct ixgbe_filter_info *filter_info =
5408 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5409 struct ixgbe_5tuple_filter_info filter_5tuple;
5410 struct ixgbe_5tuple_filter *filter;
5413 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5414 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5418 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5419 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5423 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5425 if (filter != NULL && add) {
5426 PMD_DRV_LOG(ERR, "filter exists.");
5429 if (filter == NULL && !add) {
5430 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5435 filter = rte_zmalloc("ixgbe_5tuple_filter",
5436 sizeof(struct ixgbe_5tuple_filter), 0);
5439 (void)rte_memcpy(&filter->filter_info,
5441 sizeof(struct ixgbe_5tuple_filter_info));
5442 filter->queue = ntuple_filter->queue;
5443 ret = ixgbe_add_5tuple_filter(dev, filter);
5449 ixgbe_remove_5tuple_filter(dev, filter);
5455 * get a ntuple filter
5458 * dev: Pointer to struct rte_eth_dev.
5459 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5462 * - On success, zero.
5463 * - On failure, a negative value.
5466 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5467 struct rte_eth_ntuple_filter *ntuple_filter)
5469 struct ixgbe_filter_info *filter_info =
5470 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5471 struct ixgbe_5tuple_filter_info filter_5tuple;
5472 struct ixgbe_5tuple_filter *filter;
5475 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5476 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5480 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5481 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5485 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5487 if (filter == NULL) {
5488 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5491 ntuple_filter->queue = filter->queue;
5496 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5497 * @dev: pointer to rte_eth_dev structure
5498 * @filter_op:operation will be taken.
5499 * @arg: a pointer to specific structure corresponding to the filter_op
5502 * - On success, zero.
5503 * - On failure, a negative value.
5506 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5507 enum rte_filter_op filter_op,
5510 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5513 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5515 if (filter_op == RTE_ETH_FILTER_NOP)
5519 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5524 switch (filter_op) {
5525 case RTE_ETH_FILTER_ADD:
5526 ret = ixgbe_add_del_ntuple_filter(dev,
5527 (struct rte_eth_ntuple_filter *)arg,
5530 case RTE_ETH_FILTER_DELETE:
5531 ret = ixgbe_add_del_ntuple_filter(dev,
5532 (struct rte_eth_ntuple_filter *)arg,
5535 case RTE_ETH_FILTER_GET:
5536 ret = ixgbe_get_ntuple_filter(dev,
5537 (struct rte_eth_ntuple_filter *)arg);
5540 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5548 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5553 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5554 if (filter_info->ethertype_filters[i] == ethertype &&
5555 (filter_info->ethertype_mask & (1 << i)))
5562 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5567 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5568 if (!(filter_info->ethertype_mask & (1 << i))) {
5569 filter_info->ethertype_mask |= 1 << i;
5570 filter_info->ethertype_filters[i] = ethertype;
5578 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5581 if (idx >= IXGBE_MAX_ETQF_FILTERS)
5583 filter_info->ethertype_mask &= ~(1 << idx);
5584 filter_info->ethertype_filters[idx] = 0;
5589 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5590 struct rte_eth_ethertype_filter *filter,
5593 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5594 struct ixgbe_filter_info *filter_info =
5595 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5600 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5603 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5604 filter->ether_type == ETHER_TYPE_IPv6) {
5605 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5606 " ethertype filter.", filter->ether_type);
5610 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5611 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5614 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5615 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5619 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5620 if (ret >= 0 && add) {
5621 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5622 filter->ether_type);
5625 if (ret < 0 && !add) {
5626 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5627 filter->ether_type);
5632 ret = ixgbe_ethertype_filter_insert(filter_info,
5633 filter->ether_type);
5635 PMD_DRV_LOG(ERR, "ethertype filters are full.");
5638 etqf = IXGBE_ETQF_FILTER_EN;
5639 etqf |= (uint32_t)filter->ether_type;
5640 etqs |= (uint32_t)((filter->queue <<
5641 IXGBE_ETQS_RX_QUEUE_SHIFT) &
5642 IXGBE_ETQS_RX_QUEUE);
5643 etqs |= IXGBE_ETQS_QUEUE_EN;
5645 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5649 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5650 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5651 IXGBE_WRITE_FLUSH(hw);
5657 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5658 struct rte_eth_ethertype_filter *filter)
5660 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5661 struct ixgbe_filter_info *filter_info =
5662 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5663 uint32_t etqf, etqs;
5666 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5668 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5669 filter->ether_type);
5673 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5674 if (etqf & IXGBE_ETQF_FILTER_EN) {
5675 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5676 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5678 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5679 IXGBE_ETQS_RX_QUEUE_SHIFT;
5686 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5687 * @dev: pointer to rte_eth_dev structure
5688 * @filter_op:operation will be taken.
5689 * @arg: a pointer to specific structure corresponding to the filter_op
5692 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5693 enum rte_filter_op filter_op,
5696 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5699 MAC_TYPE_FILTER_SUP(hw->mac.type);
5701 if (filter_op == RTE_ETH_FILTER_NOP)
5705 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5710 switch (filter_op) {
5711 case RTE_ETH_FILTER_ADD:
5712 ret = ixgbe_add_del_ethertype_filter(dev,
5713 (struct rte_eth_ethertype_filter *)arg,
5716 case RTE_ETH_FILTER_DELETE:
5717 ret = ixgbe_add_del_ethertype_filter(dev,
5718 (struct rte_eth_ethertype_filter *)arg,
5721 case RTE_ETH_FILTER_GET:
5722 ret = ixgbe_get_ethertype_filter(dev,
5723 (struct rte_eth_ethertype_filter *)arg);
5726 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5734 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5735 enum rte_filter_type filter_type,
5736 enum rte_filter_op filter_op,
5741 switch (filter_type) {
5742 case RTE_ETH_FILTER_NTUPLE:
5743 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5745 case RTE_ETH_FILTER_ETHERTYPE:
5746 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5748 case RTE_ETH_FILTER_SYN:
5749 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5751 case RTE_ETH_FILTER_FDIR:
5752 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5754 case RTE_ETH_FILTER_L2_TUNNEL:
5755 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5758 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5767 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5768 u8 **mc_addr_ptr, u32 *vmdq)
5773 mc_addr = *mc_addr_ptr;
5774 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5779 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5780 struct ether_addr *mc_addr_set,
5781 uint32_t nb_mc_addr)
5783 struct ixgbe_hw *hw;
5786 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5787 mc_addr_list = (u8 *)mc_addr_set;
5788 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5789 ixgbe_dev_addr_list_itr, TRUE);
5793 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5795 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5796 uint64_t systime_cycles;
5798 switch (hw->mac.type) {
5799 case ixgbe_mac_X550:
5800 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5801 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5802 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5806 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5807 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5811 return systime_cycles;
5815 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5817 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5818 uint64_t rx_tstamp_cycles;
5820 switch (hw->mac.type) {
5821 case ixgbe_mac_X550:
5822 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5823 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5824 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5828 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5829 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5830 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5834 return rx_tstamp_cycles;
5838 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5840 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5841 uint64_t tx_tstamp_cycles;
5843 switch (hw->mac.type) {
5844 case ixgbe_mac_X550:
5845 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5846 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5847 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5851 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5852 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5853 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5857 return tx_tstamp_cycles;
5861 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5863 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5864 struct ixgbe_adapter *adapter =
5865 (struct ixgbe_adapter *)dev->data->dev_private;
5866 struct rte_eth_link link;
5867 uint32_t incval = 0;
5870 /* Get current link speed. */
5871 memset(&link, 0, sizeof(link));
5872 ixgbe_dev_link_update(dev, 1);
5873 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5875 switch (link.link_speed) {
5876 case ETH_LINK_SPEED_100:
5877 incval = IXGBE_INCVAL_100;
5878 shift = IXGBE_INCVAL_SHIFT_100;
5880 case ETH_LINK_SPEED_1000:
5881 incval = IXGBE_INCVAL_1GB;
5882 shift = IXGBE_INCVAL_SHIFT_1GB;
5884 case ETH_LINK_SPEED_10000:
5886 incval = IXGBE_INCVAL_10GB;
5887 shift = IXGBE_INCVAL_SHIFT_10GB;
5891 switch (hw->mac.type) {
5892 case ixgbe_mac_X550:
5893 /* Independent of link speed. */
5895 /* Cycles read will be interpreted as ns. */
5898 case ixgbe_mac_X540:
5899 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5901 case ixgbe_mac_82599EB:
5902 incval >>= IXGBE_INCVAL_SHIFT_82599;
5903 shift -= IXGBE_INCVAL_SHIFT_82599;
5904 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5905 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5908 /* Not supported. */
5912 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5913 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5914 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5916 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5917 adapter->systime_tc.cc_shift = shift;
5918 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5920 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5921 adapter->rx_tstamp_tc.cc_shift = shift;
5922 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5924 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5925 adapter->tx_tstamp_tc.cc_shift = shift;
5926 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5930 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5932 struct ixgbe_adapter *adapter =
5933 (struct ixgbe_adapter *)dev->data->dev_private;
5935 adapter->systime_tc.nsec += delta;
5936 adapter->rx_tstamp_tc.nsec += delta;
5937 adapter->tx_tstamp_tc.nsec += delta;
5943 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5946 struct ixgbe_adapter *adapter =
5947 (struct ixgbe_adapter *)dev->data->dev_private;
5949 ns = rte_timespec_to_ns(ts);
5950 /* Set the timecounters to a new value. */
5951 adapter->systime_tc.nsec = ns;
5952 adapter->rx_tstamp_tc.nsec = ns;
5953 adapter->tx_tstamp_tc.nsec = ns;
5959 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5961 uint64_t ns, systime_cycles;
5962 struct ixgbe_adapter *adapter =
5963 (struct ixgbe_adapter *)dev->data->dev_private;
5965 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
5966 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5967 *ts = rte_ns_to_timespec(ns);
5973 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5975 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5979 /* Stop the timesync system time. */
5980 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
5981 /* Reset the timesync system time value. */
5982 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
5983 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
5985 /* Enable system time for platforms where it isn't on by default. */
5986 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5987 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5988 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5990 ixgbe_start_timecounters(dev);
5992 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5993 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5995 IXGBE_ETQF_FILTER_EN |
5998 /* Enable timestamping of received PTP packets. */
5999 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6000 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6001 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6003 /* Enable timestamping of transmitted PTP packets. */
6004 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6005 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6006 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6008 IXGBE_WRITE_FLUSH(hw);
6014 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6016 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6019 /* Disable timestamping of transmitted PTP packets. */
6020 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6021 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6022 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6024 /* Disable timestamping of received PTP packets. */
6025 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6026 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6027 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6029 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6030 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6032 /* Stop incrementating the System Time registers. */
6033 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6039 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6040 struct timespec *timestamp,
6041 uint32_t flags __rte_unused)
6043 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6044 struct ixgbe_adapter *adapter =
6045 (struct ixgbe_adapter *)dev->data->dev_private;
6046 uint32_t tsync_rxctl;
6047 uint64_t rx_tstamp_cycles;
6050 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6051 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6054 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6055 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6056 *timestamp = rte_ns_to_timespec(ns);
6062 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6063 struct timespec *timestamp)
6065 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6066 struct ixgbe_adapter *adapter =
6067 (struct ixgbe_adapter *)dev->data->dev_private;
6068 uint32_t tsync_txctl;
6069 uint64_t tx_tstamp_cycles;
6072 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6073 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6076 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6077 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6078 *timestamp = rte_ns_to_timespec(ns);
6084 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6086 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6089 const struct reg_info *reg_group;
6090 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6091 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6093 while ((reg_group = reg_set[g_ind++]))
6094 count += ixgbe_regs_group_count(reg_group);
6100 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6104 const struct reg_info *reg_group;
6106 while ((reg_group = ixgbevf_regs[g_ind++]))
6107 count += ixgbe_regs_group_count(reg_group);
6113 ixgbe_get_regs(struct rte_eth_dev *dev,
6114 struct rte_dev_reg_info *regs)
6116 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6117 uint32_t *data = regs->data;
6120 const struct reg_info *reg_group;
6121 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6122 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6124 /* Support only full register dump */
6125 if ((regs->length == 0) ||
6126 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6127 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6129 while ((reg_group = reg_set[g_ind++]))
6130 count += ixgbe_read_regs_group(dev, &data[count],
6139 ixgbevf_get_regs(struct rte_eth_dev *dev,
6140 struct rte_dev_reg_info *regs)
6142 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6143 uint32_t *data = regs->data;
6146 const struct reg_info *reg_group;
6148 /* Support only full register dump */
6149 if ((regs->length == 0) ||
6150 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6151 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6153 while ((reg_group = ixgbevf_regs[g_ind++]))
6154 count += ixgbe_read_regs_group(dev, &data[count],
6163 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6165 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6167 /* Return unit is byte count */
6168 return hw->eeprom.word_size * 2;
6172 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6173 struct rte_dev_eeprom_info *in_eeprom)
6175 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6176 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6177 uint16_t *data = in_eeprom->data;
6180 first = in_eeprom->offset >> 1;
6181 length = in_eeprom->length >> 1;
6182 if ((first > hw->eeprom.word_size) ||
6183 ((first + length) > hw->eeprom.word_size))
6186 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6188 return eeprom->ops.read_buffer(hw, first, length, data);
6192 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6193 struct rte_dev_eeprom_info *in_eeprom)
6195 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6196 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6197 uint16_t *data = in_eeprom->data;
6200 first = in_eeprom->offset >> 1;
6201 length = in_eeprom->length >> 1;
6202 if ((first > hw->eeprom.word_size) ||
6203 ((first + length) > hw->eeprom.word_size))
6206 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6208 return eeprom->ops.write_buffer(hw, first, length, data);
6212 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6214 case ixgbe_mac_X550:
6215 case ixgbe_mac_X550EM_x:
6216 case ixgbe_mac_X550EM_a:
6217 return ETH_RSS_RETA_SIZE_512;
6218 case ixgbe_mac_X550_vf:
6219 case ixgbe_mac_X550EM_x_vf:
6220 case ixgbe_mac_X550EM_a_vf:
6221 return ETH_RSS_RETA_SIZE_64;
6223 return ETH_RSS_RETA_SIZE_128;
6228 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6230 case ixgbe_mac_X550:
6231 case ixgbe_mac_X550EM_x:
6232 case ixgbe_mac_X550EM_a:
6233 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6234 return IXGBE_RETA(reta_idx >> 2);
6236 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6237 case ixgbe_mac_X550_vf:
6238 case ixgbe_mac_X550EM_x_vf:
6239 case ixgbe_mac_X550EM_a_vf:
6240 return IXGBE_VFRETA(reta_idx >> 2);
6242 return IXGBE_RETA(reta_idx >> 2);
6247 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6249 case ixgbe_mac_X550_vf:
6250 case ixgbe_mac_X550EM_x_vf:
6251 case ixgbe_mac_X550EM_a_vf:
6252 return IXGBE_VFMRQC;
6259 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6261 case ixgbe_mac_X550_vf:
6262 case ixgbe_mac_X550EM_x_vf:
6263 case ixgbe_mac_X550EM_a_vf:
6264 return IXGBE_VFRSSRK(i);
6266 return IXGBE_RSSRK(i);
6271 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6273 case ixgbe_mac_82599_vf:
6274 case ixgbe_mac_X540_vf:
6282 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6283 struct rte_eth_dcb_info *dcb_info)
6285 struct ixgbe_dcb_config *dcb_config =
6286 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6287 struct ixgbe_dcb_tc_config *tc;
6290 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6291 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6293 dcb_info->nb_tcs = 1;
6295 if (dcb_config->vt_mode) { /* vt is enabled*/
6296 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6297 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6298 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6299 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6300 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6301 for (j = 0; j < dcb_info->nb_tcs; j++) {
6302 dcb_info->tc_queue.tc_rxq[i][j].base =
6303 i * dcb_info->nb_tcs + j;
6304 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6305 dcb_info->tc_queue.tc_txq[i][j].base =
6306 i * dcb_info->nb_tcs + j;
6307 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6310 } else { /* vt is disabled*/
6311 struct rte_eth_dcb_rx_conf *rx_conf =
6312 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6313 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6314 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6315 if (dcb_info->nb_tcs == ETH_4_TCS) {
6316 for (i = 0; i < dcb_info->nb_tcs; i++) {
6317 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6318 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6320 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6321 dcb_info->tc_queue.tc_txq[0][1].base = 64;
6322 dcb_info->tc_queue.tc_txq[0][2].base = 96;
6323 dcb_info->tc_queue.tc_txq[0][3].base = 112;
6324 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6325 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6326 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6327 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6328 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6329 for (i = 0; i < dcb_info->nb_tcs; i++) {
6330 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6331 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6333 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6334 dcb_info->tc_queue.tc_txq[0][1].base = 32;
6335 dcb_info->tc_queue.tc_txq[0][2].base = 64;
6336 dcb_info->tc_queue.tc_txq[0][3].base = 80;
6337 dcb_info->tc_queue.tc_txq[0][4].base = 96;
6338 dcb_info->tc_queue.tc_txq[0][5].base = 104;
6339 dcb_info->tc_queue.tc_txq[0][6].base = 112;
6340 dcb_info->tc_queue.tc_txq[0][7].base = 120;
6341 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6342 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6343 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6344 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6345 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6346 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6347 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6348 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6351 for (i = 0; i < dcb_info->nb_tcs; i++) {
6352 tc = &dcb_config->tc_config[i];
6353 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6358 /* Update e-tag ether type */
6360 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6361 uint16_t ether_type)
6363 uint32_t etag_etype;
6365 if (hw->mac.type != ixgbe_mac_X550 &&
6366 hw->mac.type != ixgbe_mac_X550EM_x) {
6370 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6371 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6372 etag_etype |= ether_type;
6373 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6374 IXGBE_WRITE_FLUSH(hw);
6379 /* Config l2 tunnel ether type */
6381 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6382 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6385 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6387 if (l2_tunnel == NULL)
6390 switch (l2_tunnel->l2_tunnel_type) {
6391 case RTE_L2_TUNNEL_TYPE_E_TAG:
6392 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6395 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6403 /* Enable e-tag tunnel */
6405 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6407 uint32_t etag_etype;
6409 if (hw->mac.type != ixgbe_mac_X550 &&
6410 hw->mac.type != ixgbe_mac_X550EM_x) {
6414 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6415 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6416 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6417 IXGBE_WRITE_FLUSH(hw);
6422 /* Enable l2 tunnel */
6424 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6425 enum rte_eth_tunnel_type l2_tunnel_type)
6428 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6430 switch (l2_tunnel_type) {
6431 case RTE_L2_TUNNEL_TYPE_E_TAG:
6432 ret = ixgbe_e_tag_enable(hw);
6435 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6443 /* Disable e-tag tunnel */
6445 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6447 uint32_t etag_etype;
6449 if (hw->mac.type != ixgbe_mac_X550 &&
6450 hw->mac.type != ixgbe_mac_X550EM_x) {
6454 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6455 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6456 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6457 IXGBE_WRITE_FLUSH(hw);
6462 /* Disable l2 tunnel */
6464 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6465 enum rte_eth_tunnel_type l2_tunnel_type)
6468 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6470 switch (l2_tunnel_type) {
6471 case RTE_L2_TUNNEL_TYPE_E_TAG:
6472 ret = ixgbe_e_tag_disable(hw);
6475 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6484 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6485 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6488 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6489 uint32_t i, rar_entries;
6490 uint32_t rar_low, rar_high;
6492 if (hw->mac.type != ixgbe_mac_X550 &&
6493 hw->mac.type != ixgbe_mac_X550EM_x) {
6497 rar_entries = ixgbe_get_num_rx_addrs(hw);
6499 for (i = 1; i < rar_entries; i++) {
6500 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6501 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6502 if ((rar_high & IXGBE_RAH_AV) &&
6503 (rar_high & IXGBE_RAH_ADTYPE) &&
6504 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6505 l2_tunnel->tunnel_id)) {
6506 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6507 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6509 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6519 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6520 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6523 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6524 uint32_t i, rar_entries;
6525 uint32_t rar_low, rar_high;
6527 if (hw->mac.type != ixgbe_mac_X550 &&
6528 hw->mac.type != ixgbe_mac_X550EM_x) {
6532 /* One entry for one tunnel. Try to remove potential existing entry. */
6533 ixgbe_e_tag_filter_del(dev, l2_tunnel);
6535 rar_entries = ixgbe_get_num_rx_addrs(hw);
6537 for (i = 1; i < rar_entries; i++) {
6538 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6539 if (rar_high & IXGBE_RAH_AV) {
6542 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6543 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6544 rar_low = l2_tunnel->tunnel_id;
6546 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6547 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6553 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6554 " Please remove a rule before adding a new one.");
6558 /* Add l2 tunnel filter */
6560 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6561 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6565 switch (l2_tunnel->l2_tunnel_type) {
6566 case RTE_L2_TUNNEL_TYPE_E_TAG:
6567 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6570 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6578 /* Delete l2 tunnel filter */
6580 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6581 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6585 switch (l2_tunnel->l2_tunnel_type) {
6586 case RTE_L2_TUNNEL_TYPE_E_TAG:
6587 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6590 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6599 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6600 * @dev: pointer to rte_eth_dev structure
6601 * @filter_op:operation will be taken.
6602 * @arg: a pointer to specific structure corresponding to the filter_op
6605 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6606 enum rte_filter_op filter_op,
6611 if (filter_op == RTE_ETH_FILTER_NOP)
6615 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6620 switch (filter_op) {
6621 case RTE_ETH_FILTER_ADD:
6622 ret = ixgbe_dev_l2_tunnel_filter_add
6624 (struct rte_eth_l2_tunnel_conf *)arg);
6626 case RTE_ETH_FILTER_DELETE:
6627 ret = ixgbe_dev_l2_tunnel_filter_del
6629 (struct rte_eth_l2_tunnel_conf *)arg);
6632 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6640 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6644 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6646 if (hw->mac.type != ixgbe_mac_X550 &&
6647 hw->mac.type != ixgbe_mac_X550EM_x) {
6651 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6652 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6654 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6655 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6660 /* Enable l2 tunnel forwarding */
6662 ixgbe_dev_l2_tunnel_forwarding_enable
6663 (struct rte_eth_dev *dev,
6664 enum rte_eth_tunnel_type l2_tunnel_type)
6668 switch (l2_tunnel_type) {
6669 case RTE_L2_TUNNEL_TYPE_E_TAG:
6670 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6673 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6681 /* Disable l2 tunnel forwarding */
6683 ixgbe_dev_l2_tunnel_forwarding_disable
6684 (struct rte_eth_dev *dev,
6685 enum rte_eth_tunnel_type l2_tunnel_type)
6689 switch (l2_tunnel_type) {
6690 case RTE_L2_TUNNEL_TYPE_E_TAG:
6691 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6694 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6703 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6704 struct rte_eth_l2_tunnel_conf *l2_tunnel,
6708 uint32_t vmtir, vmvir;
6709 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6711 if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6713 "VF id %u should be less than %u",
6715 dev->pci_dev->max_vfs);
6719 if (hw->mac.type != ixgbe_mac_X550 &&
6720 hw->mac.type != ixgbe_mac_X550EM_x) {
6725 vmtir = l2_tunnel->tunnel_id;
6729 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6731 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6732 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6734 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6735 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6740 /* Enable l2 tunnel tag insertion */
6742 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6743 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6747 switch (l2_tunnel->l2_tunnel_type) {
6748 case RTE_L2_TUNNEL_TYPE_E_TAG:
6749 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6752 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6760 /* Disable l2 tunnel tag insertion */
6762 ixgbe_dev_l2_tunnel_insertion_disable
6763 (struct rte_eth_dev *dev,
6764 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6768 switch (l2_tunnel->l2_tunnel_type) {
6769 case RTE_L2_TUNNEL_TYPE_E_TAG:
6770 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6773 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6782 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6787 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6789 if (hw->mac.type != ixgbe_mac_X550 &&
6790 hw->mac.type != ixgbe_mac_X550EM_x) {
6794 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6796 qde |= IXGBE_QDE_STRIP_TAG;
6798 qde &= ~IXGBE_QDE_STRIP_TAG;
6799 qde &= ~IXGBE_QDE_READ;
6800 qde |= IXGBE_QDE_WRITE;
6801 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6806 /* Enable l2 tunnel tag stripping */
6808 ixgbe_dev_l2_tunnel_stripping_enable
6809 (struct rte_eth_dev *dev,
6810 enum rte_eth_tunnel_type l2_tunnel_type)
6814 switch (l2_tunnel_type) {
6815 case RTE_L2_TUNNEL_TYPE_E_TAG:
6816 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6819 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6827 /* Disable l2 tunnel tag stripping */
6829 ixgbe_dev_l2_tunnel_stripping_disable
6830 (struct rte_eth_dev *dev,
6831 enum rte_eth_tunnel_type l2_tunnel_type)
6835 switch (l2_tunnel_type) {
6836 case RTE_L2_TUNNEL_TYPE_E_TAG:
6837 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6840 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6848 /* Enable/disable l2 tunnel offload functions */
6850 ixgbe_dev_l2_tunnel_offload_set
6851 (struct rte_eth_dev *dev,
6852 struct rte_eth_l2_tunnel_conf *l2_tunnel,
6858 if (l2_tunnel == NULL)
6862 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
6864 ret = ixgbe_dev_l2_tunnel_enable(
6866 l2_tunnel->l2_tunnel_type);
6868 ret = ixgbe_dev_l2_tunnel_disable(
6870 l2_tunnel->l2_tunnel_type);
6873 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
6875 ret = ixgbe_dev_l2_tunnel_insertion_enable(
6879 ret = ixgbe_dev_l2_tunnel_insertion_disable(
6884 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
6886 ret = ixgbe_dev_l2_tunnel_stripping_enable(
6888 l2_tunnel->l2_tunnel_type);
6890 ret = ixgbe_dev_l2_tunnel_stripping_disable(
6892 l2_tunnel->l2_tunnel_type);
6895 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
6897 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
6899 l2_tunnel->l2_tunnel_type);
6901 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
6903 l2_tunnel->l2_tunnel_type);
6910 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
6913 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
6914 IXGBE_WRITE_FLUSH(hw);
6919 /* There's only one register for VxLAN UDP port.
6920 * So, we cannot add several ports. Will update it.
6923 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
6927 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
6931 return ixgbe_update_vxlan_port(hw, port);
6934 /* We cannot delete the VxLAN port. For there's a register for VxLAN
6935 * UDP port, it must have a value.
6936 * So, will reset it to the original value 0.
6939 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
6944 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
6946 if (cur_port != port) {
6947 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
6951 return ixgbe_update_vxlan_port(hw, 0);
6954 /* Add UDP tunneling port */
6956 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6957 struct rte_eth_udp_tunnel *udp_tunnel)
6960 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6962 if (hw->mac.type != ixgbe_mac_X550 &&
6963 hw->mac.type != ixgbe_mac_X550EM_x) {
6967 if (udp_tunnel == NULL)
6970 switch (udp_tunnel->prot_type) {
6971 case RTE_TUNNEL_TYPE_VXLAN:
6972 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
6975 case RTE_TUNNEL_TYPE_GENEVE:
6976 case RTE_TUNNEL_TYPE_TEREDO:
6977 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6982 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6990 /* Remove UDP tunneling port */
6992 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6993 struct rte_eth_udp_tunnel *udp_tunnel)
6996 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6998 if (hw->mac.type != ixgbe_mac_X550 &&
6999 hw->mac.type != ixgbe_mac_X550EM_x) {
7003 if (udp_tunnel == NULL)
7006 switch (udp_tunnel->prot_type) {
7007 case RTE_TUNNEL_TYPE_VXLAN:
7008 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7010 case RTE_TUNNEL_TYPE_GENEVE:
7011 case RTE_TUNNEL_TYPE_TEREDO:
7012 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7016 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7024 /* ixgbevf_update_xcast_mode - Update Multicast mode
7025 * @hw: pointer to the HW structure
7026 * @netdev: pointer to net device structure
7027 * @xcast_mode: new multicast mode
7029 * Updates the Multicast Mode of VF.
7031 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
7034 struct ixgbe_mbx_info *mbx = &hw->mbx;
7038 switch (hw->api_version) {
7039 case ixgbe_mbox_api_12:
7045 msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7046 msgbuf[1] = xcast_mode;
7048 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7052 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7056 msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7057 if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7064 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7066 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7068 ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7072 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7074 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7076 ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7079 static struct rte_driver rte_ixgbe_driver = {
7081 .init = rte_ixgbe_pmd_init,
7084 static struct rte_driver rte_ixgbevf_driver = {
7086 .init = rte_ixgbevf_pmd_init,
7089 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
7090 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);