drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 #include "rte_pmd_ixgbe.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  97 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  98 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  99
 100 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 101 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 102 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 103
 104 /*
 105  *  Default values for RX/TX configuration
 106  */
 107 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_RX_PTHRESH      8
 109 #define IXGBE_DEFAULT_RX_HTHRESH      8
 110 #define IXGBE_DEFAULT_RX_WTHRESH      0
 111
 112 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 113 #define IXGBE_DEFAULT_TX_PTHRESH      32
 114 #define IXGBE_DEFAULT_TX_HTHRESH      0
 115 #define IXGBE_DEFAULT_TX_WTHRESH      0
 116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 117
 118 /* Bit shift and mask */
 119 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 120 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 121 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 122 #define IXGBE_8_BIT_MASK   UINT8_MAX
 123
 124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 125
 126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 127
 128 #define IXGBE_HKEY_MAX_INDEX 10
 129
 130 /* Additional timesync values. */
 131 #define NSEC_PER_SEC             1000000000L
 132 #define IXGBE_INCVAL_10GB        0x66666666
 133 #define IXGBE_INCVAL_1GB         0x40000000
 134 #define IXGBE_INCVAL_100         0x50000000
 135 #define IXGBE_INCVAL_SHIFT_10GB  28
 136 #define IXGBE_INCVAL_SHIFT_1GB   24
 137 #define IXGBE_INCVAL_SHIFT_100   21
 138 #define IXGBE_INCVAL_SHIFT_82599 7
 139 #define IXGBE_INCPER_SHIFT_82599 24
 140
 141 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 142
 143 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 145 #define DEFAULT_ETAG_ETYPE                     0x893f
 146 #define IXGBE_ETAG_ETYPE                       0x00005084
 147 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 148 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 149 #define IXGBE_RAH_ADTYPE                       0x40000000
 150 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 151 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 154 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 155 #define IXGBE_VTEICR_MASK                      0x07
 156
 157 enum ixgbevf_xcast_modes {
 158         IXGBEVF_XCAST_MODE_NONE = 0,
 159         IXGBEVF_XCAST_MODE_MULTI,
 160         IXGBEVF_XCAST_MODE_ALLMULTI,
 161 };
 162
 163 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 164 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 165
 166 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 167 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 168 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 172 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 178 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 179                                 int wait_to_complete);
 180 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_stats *stats);
 182 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_xstat *xstats, unsigned n);
 184 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 185                                   struct rte_eth_xstat *xstats, unsigned n);
 186 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 187 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 188 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 189         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 190 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 192 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 193                                              uint16_t queue_id,
 194                                              uint8_t stat_idx,
 195                                              uint8_t is_rx);
 196 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 197                                struct rte_eth_dev_info *dev_info);
 198 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 199 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 200                                  struct rte_eth_dev_info *dev_info);
 201 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 202
 203 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 204                 uint16_t vlan_id, int on);
 205 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 206                                enum rte_vlan_type vlan_type,
 207                                uint16_t tpid_id);
 208 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 209                 uint16_t queue, bool on);
 210 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 211                 int on);
 212 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 213 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 214 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 215 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 216 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 217
 218 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 220 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 221                                struct rte_eth_fc_conf *fc_conf);
 222 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 223                                struct rte_eth_fc_conf *fc_conf);
 224 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 225                 struct rte_eth_pfc_conf *pfc_conf);
 226 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 227                         struct rte_eth_rss_reta_entry64 *reta_conf,
 228                         uint16_t reta_size);
 229 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 230                         struct rte_eth_rss_reta_entry64 *reta_conf,
 231                         uint16_t reta_size);
 232 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 233 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 234 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 235 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 236 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 237                                       struct rte_intr_handle *handle);
 238 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 239                 void *param);
 240 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 241 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 242                 uint32_t index, uint32_t pool);
 243 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 244 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 245                                            struct ether_addr *mac_addr);
 246 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 247
 248 /* For Virtual Function support */
 249 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 250 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 251 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 252 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 253 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 256 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 257 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 258                 struct rte_eth_stats *stats);
 259 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 260 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 261                 uint16_t vlan_id, int on);
 262 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 263                 uint16_t queue, int on);
 264 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 265 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 266 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 267                                             uint16_t queue_id);
 268 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 269                                              uint16_t queue_id);
 270 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 271                                  uint8_t queue, uint8_t msix_vector);
 272 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 273 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 274 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 275
 276 /* For Eth VMDQ APIs support */
 277 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 278                 ether_addr * mac_addr, uint8_t on);
 279 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 280 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 281                 uint16_t rx_mask, uint8_t on);
 282 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 283 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 284 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 285                 uint64_t pool_mask, uint8_t vlan_on);
 286 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 287                 struct rte_eth_mirror_conf *mirror_conf,
 288                 uint8_t rule_id, uint8_t on);
 289 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 290                 uint8_t rule_id);
 291 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 292                                           uint16_t queue_id);
 293 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 294                                            uint16_t queue_id);
 295 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 296                                uint8_t queue, uint8_t msix_vector);
 297 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 298
 299 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 300                 uint16_t queue_idx, uint16_t tx_rate);
 301 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 302                 uint16_t tx_rate, uint64_t q_msk);
 303
 304 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 305                                  struct ether_addr *mac_addr,
 306                                  uint32_t index, uint32_t pool);
 307 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 308 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 309                                              struct ether_addr *mac_addr);
 310 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 311                         struct rte_eth_syn_filter *filter,
 312                         bool add);
 313 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 314                         struct rte_eth_syn_filter *filter);
 315 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 316                         enum rte_filter_op filter_op,
 317                         void *arg);
 318 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 319                         struct ixgbe_5tuple_filter *filter);
 320 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 321                         struct ixgbe_5tuple_filter *filter);
 322 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 323                         struct rte_eth_ntuple_filter *filter,
 324                         bool add);
 325 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 326                                 enum rte_filter_op filter_op,
 327                                 void *arg);
 328 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 329                         struct rte_eth_ntuple_filter *filter);
 330 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 331                         struct rte_eth_ethertype_filter *filter,
 332                         bool add);
 333 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 334                                 enum rte_filter_op filter_op,
 335                                 void *arg);
 336 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 337                         struct rte_eth_ethertype_filter *filter);
 338 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 339                      enum rte_filter_type filter_type,
 340                      enum rte_filter_op filter_op,
 341                      void *arg);
 342 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 343
 344 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 345                                       struct ether_addr *mc_addr_set,
 346                                       uint32_t nb_mc_addr);
 347 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 348                                    struct rte_eth_dcb_info *dcb_info);
 349
 350 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 351 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 352                             struct rte_dev_reg_info *regs);
 353 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 354 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 355                                 struct rte_dev_eeprom_info *eeprom);
 356 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 357                                 struct rte_dev_eeprom_info *eeprom);
 358
 359 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 360 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 361                                 struct rte_dev_reg_info *regs);
 362
 363 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 364 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 365 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 366                                             struct timespec *timestamp,
 367                                             uint32_t flags);
 368 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 369                                             struct timespec *timestamp);
 370 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 371 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 372                                    struct timespec *timestamp);
 373 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 374                                    const struct timespec *timestamp);
 375 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 376                                           void *param);
 377
 378 static int ixgbe_dev_l2_tunnel_eth_type_conf
 379         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 380 static int ixgbe_dev_l2_tunnel_offload_set
 381         (struct rte_eth_dev *dev,
 382          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 383          uint32_t mask,
 384          uint8_t en);
 385 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 386                                              enum rte_filter_op filter_op,
 387                                              void *arg);
 388
 389 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 390                                          struct rte_eth_udp_tunnel *udp_tunnel);
 391 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 392                                          struct rte_eth_udp_tunnel *udp_tunnel);
 393
 394 /*
 395  * Define VF Stats MACRO for Non "cleared on read" register
 396  */
 397 #define UPDATE_VF_STAT(reg, last, cur)                          \
 398 {                                                               \
 399         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 400         cur += (latest - last) & UINT_MAX;                      \
 401         last = latest;                                          \
 402 }
 403
 404 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 405 {                                                                \
 406         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 407         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 408         u64 latest = ((new_msb << 32) | new_lsb);                \
 409         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 410         last = latest;                                           \
 411 }
 412
 413 #define IXGBE_SET_HWSTRIP(h, q) do {\
 414                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 415                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 416                 (h)->bitmap[idx] |= 1 << bit;\
 417         } while (0)
 418
 419 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 420                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 421                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 422                 (h)->bitmap[idx] &= ~(1 << bit);\
 423         } while (0)
 424
 425 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 426                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 427                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 428                 (r) = (h)->bitmap[idx] >> bit & 1;\
 429         } while (0)
 430
 431 /*
 432  * The set of PCI devices this driver supports
 433  */
 434 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 488 #ifdef RTE_NIC_BYPASS
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 490 #endif
 491         { .vendor_id = 0, /* sentinel */ },
 492 };
 493
 494 /*
 495  * The set of PCI devices this driver supports (for 82599 VF)
 496  */
 497 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 505         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 506         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 507         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 508         { .vendor_id = 0, /* sentinel */ },
 509 };
 510
 511 static const struct rte_eth_desc_lim rx_desc_lim = {
 512         .nb_max = IXGBE_MAX_RING_DESC,
 513         .nb_min = IXGBE_MIN_RING_DESC,
 514         .nb_align = IXGBE_RXD_ALIGN,
 515 };
 516
 517 static const struct rte_eth_desc_lim tx_desc_lim = {
 518         .nb_max = IXGBE_MAX_RING_DESC,
 519         .nb_min = IXGBE_MIN_RING_DESC,
 520         .nb_align = IXGBE_TXD_ALIGN,
 521 };
 522
 523 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 524         .dev_configure        = ixgbe_dev_configure,
 525         .dev_start            = ixgbe_dev_start,
 526         .dev_stop             = ixgbe_dev_stop,
 527         .dev_set_link_up    = ixgbe_dev_set_link_up,
 528         .dev_set_link_down  = ixgbe_dev_set_link_down,
 529         .dev_close            = ixgbe_dev_close,
 530         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 531         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 532         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 533         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 534         .link_update          = ixgbe_dev_link_update,
 535         .stats_get            = ixgbe_dev_stats_get,
 536         .xstats_get           = ixgbe_dev_xstats_get,
 537         .stats_reset          = ixgbe_dev_stats_reset,
 538         .xstats_reset         = ixgbe_dev_xstats_reset,
 539         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 540         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 541         .dev_infos_get        = ixgbe_dev_info_get,
 542         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 543         .mtu_set              = ixgbe_dev_mtu_set,
 544         .vlan_filter_set      = ixgbe_vlan_filter_set,
 545         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 546         .vlan_offload_set     = ixgbe_vlan_offload_set,
 547         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 548         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 549         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 550         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 551         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 552         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 553         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 554         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 555         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 556         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 557         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 558         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 559         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 560         .dev_led_on           = ixgbe_dev_led_on,
 561         .dev_led_off          = ixgbe_dev_led_off,
 562         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 563         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 564         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 565         .mac_addr_add         = ixgbe_add_rar,
 566         .mac_addr_remove      = ixgbe_remove_rar,
 567         .mac_addr_set         = ixgbe_set_default_mac_addr,
 568         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 569         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 570         .mirror_rule_set      = ixgbe_mirror_rule_set,
 571         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 572         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 573         .set_vf_rx            = ixgbe_set_pool_rx,
 574         .set_vf_tx            = ixgbe_set_pool_tx,
 575         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 576         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 577         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 578         .reta_update          = ixgbe_dev_rss_reta_update,
 579         .reta_query           = ixgbe_dev_rss_reta_query,
 580 #ifdef RTE_NIC_BYPASS
 581         .bypass_init          = ixgbe_bypass_init,
 582         .bypass_state_set     = ixgbe_bypass_state_store,
 583         .bypass_state_show    = ixgbe_bypass_state_show,
 584         .bypass_event_set     = ixgbe_bypass_event_store,
 585         .bypass_event_show    = ixgbe_bypass_event_show,
 586         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 587         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 588         .bypass_ver_show      = ixgbe_bypass_ver_show,
 589         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 590 #endif /* RTE_NIC_BYPASS */
 591         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 592         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 593         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 594         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 595         .rxq_info_get         = ixgbe_rxq_info_get,
 596         .txq_info_get         = ixgbe_txq_info_get,
 597         .timesync_enable      = ixgbe_timesync_enable,
 598         .timesync_disable     = ixgbe_timesync_disable,
 599         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 600         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 601         .get_reg              = ixgbe_get_regs,
 602         .get_eeprom_length    = ixgbe_get_eeprom_length,
 603         .get_eeprom           = ixgbe_get_eeprom,
 604         .set_eeprom           = ixgbe_set_eeprom,
 605         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 606         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 607         .timesync_read_time   = ixgbe_timesync_read_time,
 608         .timesync_write_time  = ixgbe_timesync_write_time,
 609         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 610         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 611         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 612         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 613 };
 614
 615 /*
 616  * dev_ops for virtual function, bare necessities for basic vf
 617  * operation have been implemented
 618  */
 619 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 620         .dev_configure        = ixgbevf_dev_configure,
 621         .dev_start            = ixgbevf_dev_start,
 622         .dev_stop             = ixgbevf_dev_stop,
 623         .link_update          = ixgbe_dev_link_update,
 624         .stats_get            = ixgbevf_dev_stats_get,
 625         .xstats_get           = ixgbevf_dev_xstats_get,
 626         .stats_reset          = ixgbevf_dev_stats_reset,
 627         .xstats_reset         = ixgbevf_dev_stats_reset,
 628         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 629         .dev_close            = ixgbevf_dev_close,
 630         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 631         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 632         .dev_infos_get        = ixgbevf_dev_info_get,
 633         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 634         .mtu_set              = ixgbevf_dev_set_mtu,
 635         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 636         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 637         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 638         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 639         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 640         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 641         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 642         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 643         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 644         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 645         .mac_addr_add         = ixgbevf_add_mac_addr,
 646         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 647         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 648         .rxq_info_get         = ixgbe_rxq_info_get,
 649         .txq_info_get         = ixgbe_txq_info_get,
 650         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 651         .get_reg              = ixgbevf_get_regs,
 652         .reta_update          = ixgbe_dev_rss_reta_update,
 653         .reta_query           = ixgbe_dev_rss_reta_query,
 654         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 655         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 656 };
 657
 658 /* store statistics names and its offset in stats structure */
 659 struct rte_ixgbe_xstats_name_off {
 660         char name[RTE_ETH_XSTATS_NAME_SIZE];
 661         unsigned offset;
 662 };
 663
 664 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 665         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 666         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 667         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 668         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 669         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 670         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 671         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 672         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 673         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 674         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 675         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 676         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 677         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 678         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 679         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 680                 prc1023)},
 681         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 682                 prc1522)},
 683         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 684         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 685         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 686         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 687         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 688         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 689         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 690         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 691         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 692         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 693         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 694         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 695         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 696         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 697         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 698         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 699         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 700                 ptc1023)},
 701         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 702                 ptc1522)},
 703         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 704         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 705         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 706         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 707
 708         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 709                 fdirustat_add)},
 710         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 711                 fdirustat_remove)},
 712         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 713                 fdirfstat_fadd)},
 714         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 715                 fdirfstat_fremove)},
 716         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 717                 fdirmatch)},
 718         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 719                 fdirmiss)},
 720
 721         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 722         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 723         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 724                 fclast)},
 725         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 726         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 727         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 728         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 729         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 730                 fcoe_noddp)},
 731         {"rx_fcoe_no_direct_data_placement_ext_buff",
 732                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 733
 734         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 735                 lxontxc)},
 736         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 737                 lxonrxc)},
 738         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 739                 lxofftxc)},
 740         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 741                 lxoffrxc)},
 742         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 743 };
 744
 745 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 746                            sizeof(rte_ixgbe_stats_strings[0]))
 747
 748 /* Per-queue statistics */
 749 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 750         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 751         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 752         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 753         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 754 };
 755
 756 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 757                            sizeof(rte_ixgbe_rxq_strings[0]))
 758 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 759
 760 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 761         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 762         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 763         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 764                 pxon2offc)},
 765 };
 766
 767 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 768                            sizeof(rte_ixgbe_txq_strings[0]))
 769 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 770
 771 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 772         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 773 };
 774
 775 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 776                 sizeof(rte_ixgbevf_stats_strings[0]))
 777
 778 /**
 779  * Atomically reads the link status information from global
 780  * structure rte_eth_dev.
 781  *
 782  * @param dev
 783  *   - Pointer to the structure rte_eth_dev to read from.
 784  *   - Pointer to the buffer to be saved with the link status.
 785  *
 786  * @return
 787  *   - On success, zero.
 788  *   - On failure, negative value.
 789  */
 790 static inline int
 791 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 792                                 struct rte_eth_link *link)
 793 {
 794         struct rte_eth_link *dst = link;
 795         struct rte_eth_link *src = &(dev->data->dev_link);
 796
 797         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 798                                         *(uint64_t *)src) == 0)
 799                 return -1;
 800
 801         return 0;
 802 }
 803
 804 /**
 805  * Atomically writes the link status information into global
 806  * structure rte_eth_dev.
 807  *
 808  * @param dev
 809  *   - Pointer to the structure rte_eth_dev to read from.
 810  *   - Pointer to the buffer to be saved with the link status.
 811  *
 812  * @return
 813  *   - On success, zero.
 814  *   - On failure, negative value.
 815  */
 816 static inline int
 817 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 818                                 struct rte_eth_link *link)
 819 {
 820         struct rte_eth_link *dst = &(dev->data->dev_link);
 821         struct rte_eth_link *src = link;
 822
 823         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 824                                         *(uint64_t *)src) == 0)
 825                 return -1;
 826
 827         return 0;
 828 }
 829
 830 /*
 831  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 832  */
 833 static inline int
 834 ixgbe_is_sfp(struct ixgbe_hw *hw)
 835 {
 836         switch (hw->phy.type) {
 837         case ixgbe_phy_sfp_avago:
 838         case ixgbe_phy_sfp_ftl:
 839         case ixgbe_phy_sfp_intel:
 840         case ixgbe_phy_sfp_unknown:
 841         case ixgbe_phy_sfp_passive_tyco:
 842         case ixgbe_phy_sfp_passive_unknown:
 843                 return 1;
 844         default:
 845                 return 0;
 846         }
 847 }
 848
 849 static inline int32_t
 850 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 851 {
 852         uint32_t ctrl_ext;
 853         int32_t status;
 854
 855         status = ixgbe_reset_hw(hw);
 856
 857         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 858         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 859         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 860         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 861         IXGBE_WRITE_FLUSH(hw);
 862
 863         return status;
 864 }
 865
 866 static inline void
 867 ixgbe_enable_intr(struct rte_eth_dev *dev)
 868 {
 869         struct ixgbe_interrupt *intr =
 870                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 871         struct ixgbe_hw *hw =
 872                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 873
 874         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 875         IXGBE_WRITE_FLUSH(hw);
 876 }
 877
 878 /*
 879  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 880  */
 881 static void
 882 ixgbe_disable_intr(struct ixgbe_hw *hw)
 883 {
 884         PMD_INIT_FUNC_TRACE();
 885
 886         if (hw->mac.type == ixgbe_mac_82598EB) {
 887                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 888         } else {
 889                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 890                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 891                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 892         }
 893         IXGBE_WRITE_FLUSH(hw);
 894 }
 895
 896 /*
 897  * This function resets queue statistics mapping registers.
 898  * From Niantic datasheet, Initialization of Statistics section:
 899  * "...if software requires the queue counters, the RQSMR and TQSM registers
 900  * must be re-programmed following a device reset.
 901  */
 902 static void
 903 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 904 {
 905         uint32_t i;
 906
 907         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 908                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 909                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 910         }
 911 }
 912
 913
 914 static int
 915 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 916                                   uint16_t queue_id,
 917                                   uint8_t stat_idx,
 918                                   uint8_t is_rx)
 919 {
 920 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 921 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 922 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 923
 924         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 925         struct ixgbe_stat_mapping_registers *stat_mappings =
 926                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 927         uint32_t qsmr_mask = 0;
 928         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 929         uint32_t q_map;
 930         uint8_t n, offset;
 931
 932         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 933                 (hw->mac.type != ixgbe_mac_X540) &&
 934                 (hw->mac.type != ixgbe_mac_X550) &&
 935                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 936                 (hw->mac.type != ixgbe_mac_X550EM_a))
 937                 return -ENOSYS;
 938
 939         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 940                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 941                      queue_id, stat_idx);
 942
 943         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 944         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 945                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 946                 return -EIO;
 947         }
 948         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 949
 950         /* Now clear any previous stat_idx set */
 951         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 952         if (!is_rx)
 953                 stat_mappings->tqsm[n] &= ~clearing_mask;
 954         else
 955                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 956
 957         q_map = (uint32_t)stat_idx;
 958         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 959         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 960         if (!is_rx)
 961                 stat_mappings->tqsm[n] |= qsmr_mask;
 962         else
 963                 stat_mappings->rqsmr[n] |= qsmr_mask;
 964
 965         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 966                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 967                      queue_id, stat_idx);
 968         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 969                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 970
 971         /* Now write the mapping in the appropriate register */
 972         if (is_rx) {
 973                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 974                              stat_mappings->rqsmr[n], n);
 975                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 976         } else {
 977                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 978                              stat_mappings->tqsm[n], n);
 979                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 980         }
 981         return 0;
 982 }
 983
 984 static void
 985 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 986 {
 987         struct ixgbe_stat_mapping_registers *stat_mappings =
 988                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 990         int i;
 991
 992         /* write whatever was in stat mapping table to the NIC */
 993         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 994                 /* rx */
 995                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 996
 997                 /* tx */
 998                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 999         }
1000 }
1001
1002 static void
1003 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1004 {
1005         uint8_t i;
1006         struct ixgbe_dcb_tc_config *tc;
1007         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1008
1009         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1010         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1011         for (i = 0; i < dcb_max_tc; i++) {
1012                 tc = &dcb_config->tc_config[i];
1013                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1014                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1015                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1016                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1017                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1018                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1019                 tc->pfc = ixgbe_dcb_pfc_disabled;
1020         }
1021
1022         /* Initialize default user to priority mapping, UPx->TC0 */
1023         tc = &dcb_config->tc_config[0];
1024         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1025         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1026         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1027                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1028                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1029         }
1030         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1031         dcb_config->pfc_mode_enable = false;
1032         dcb_config->vt_mode = true;
1033         dcb_config->round_robin_enable = false;
1034         /* support all DCB capabilities in 82599 */
1035         dcb_config->support.capabilities = 0xFF;
1036
1037         /*we only support 4 Tcs for X540, X550 */
1038         if (hw->mac.type == ixgbe_mac_X540 ||
1039                 hw->mac.type == ixgbe_mac_X550 ||
1040                 hw->mac.type == ixgbe_mac_X550EM_x ||
1041                 hw->mac.type == ixgbe_mac_X550EM_a) {
1042                 dcb_config->num_tcs.pg_tcs = 4;
1043                 dcb_config->num_tcs.pfc_tcs = 4;
1044         }
1045 }
1046
1047 /*
1048  * Ensure that all locks are released before first NVM or PHY access
1049  */
1050 static void
1051 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1052 {
1053         uint16_t mask;
1054
1055         /*
1056          * Phy lock should not fail in this early stage. If this is the case,
1057          * it is due to an improper exit of the application.
1058          * So force the release of the faulty lock. Release of common lock
1059          * is done automatically by swfw_sync function.
1060          */
1061         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1062         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1063                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1064         }
1065         ixgbe_release_swfw_semaphore(hw, mask);
1066
1067         /*
1068          * These ones are more tricky since they are common to all ports; but
1069          * swfw_sync retries last long enough (1s) to be almost sure that if
1070          * lock can not be taken it is due to an improper lock of the
1071          * semaphore.
1072          */
1073         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1074         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1075                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1076         }
1077         ixgbe_release_swfw_semaphore(hw, mask);
1078 }
1079
1080 /*
1081  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1082  * It returns 0 on success.
1083  */
1084 static int
1085 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1086 {
1087         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1088         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1089         struct ixgbe_hw *hw =
1090                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1091         struct ixgbe_vfta *shadow_vfta =
1092                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1093         struct ixgbe_hwstrip *hwstrip =
1094                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1095         struct ixgbe_dcb_config *dcb_config =
1096                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1097         struct ixgbe_filter_info *filter_info =
1098                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1099         uint32_t ctrl_ext;
1100         uint16_t csum;
1101         int diag, i;
1102
1103         PMD_INIT_FUNC_TRACE();
1104
1105         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1106         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1107         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1108
1109         /*
1110          * For secondary processes, we don't initialise any further as primary
1111          * has already done this work. Only check we don't need a different
1112          * RX and TX function.
1113          */
1114         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1115                 struct ixgbe_tx_queue *txq;
1116                 /* TX queue function in primary, set by last queue initialized
1117                  * Tx queue may not initialized by primary process
1118                  */
1119                 if (eth_dev->data->tx_queues) {
1120                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1121                         ixgbe_set_tx_function(eth_dev, txq);
1122                 } else {
1123                         /* Use default TX function if we get here */
1124                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1125                                      "Using default TX function.");
1126                 }
1127
1128                 ixgbe_set_rx_function(eth_dev);
1129
1130                 return 0;
1131         }
1132
1133         rte_eth_copy_pci_info(eth_dev, pci_dev);
1134
1135         /* Vendor and Device ID need to be set before init of shared code */
1136         hw->device_id = pci_dev->id.device_id;
1137         hw->vendor_id = pci_dev->id.vendor_id;
1138         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1139         hw->allow_unsupported_sfp = 1;
1140
1141         /* Initialize the shared code (base driver) */
1142 #ifdef RTE_NIC_BYPASS
1143         diag = ixgbe_bypass_init_shared_code(hw);
1144 #else
1145         diag = ixgbe_init_shared_code(hw);
1146 #endif /* RTE_NIC_BYPASS */
1147
1148         if (diag != IXGBE_SUCCESS) {
1149                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1150                 return -EIO;
1151         }
1152
1153         /* pick up the PCI bus settings for reporting later */
1154         ixgbe_get_bus_info(hw);
1155
1156         /* Unlock any pending hardware semaphore */
1157         ixgbe_swfw_lock_reset(hw);
1158
1159         /* Initialize DCB configuration*/
1160         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1161         ixgbe_dcb_init(hw, dcb_config);
1162         /* Get Hardware Flow Control setting */
1163         hw->fc.requested_mode = ixgbe_fc_full;
1164         hw->fc.current_mode = ixgbe_fc_full;
1165         hw->fc.pause_time = IXGBE_FC_PAUSE;
1166         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1167                 hw->fc.low_water[i] = IXGBE_FC_LO;
1168                 hw->fc.high_water[i] = IXGBE_FC_HI;
1169         }
1170         hw->fc.send_xon = 1;
1171
1172         /* Make sure we have a good EEPROM before we read from it */
1173         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1174         if (diag != IXGBE_SUCCESS) {
1175                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1176                 return -EIO;
1177         }
1178
1179 #ifdef RTE_NIC_BYPASS
1180         diag = ixgbe_bypass_init_hw(hw);
1181 #else
1182         diag = ixgbe_init_hw(hw);
1183 #endif /* RTE_NIC_BYPASS */
1184
1185         /*
1186          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1187          * is called too soon after the kernel driver unbinding/binding occurs.
1188          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1189          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1190          * also called. See ixgbe_identify_phy_82599(). The reason for the
1191          * failure is not known, and only occuts when virtualisation features
1192          * are disabled in the bios. A delay of 100ms  was found to be enough by
1193          * trial-and-error, and is doubled to be safe.
1194          */
1195         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1196                 rte_delay_ms(200);
1197                 diag = ixgbe_init_hw(hw);
1198         }
1199
1200         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1201                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1202                              "LOM.  Please be aware there may be issues associated "
1203                              "with your hardware.");
1204                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1205                              "please contact your Intel or hardware representative "
1206                              "who provided you with this hardware.");
1207         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1208                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1209         if (diag) {
1210                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1211                 return -EIO;
1212         }
1213
1214         /* Reset the hw statistics */
1215         ixgbe_dev_stats_reset(eth_dev);
1216
1217         /* disable interrupt */
1218         ixgbe_disable_intr(hw);
1219
1220         /* reset mappings for queue statistics hw counters*/
1221         ixgbe_reset_qstat_mappings(hw);
1222
1223         /* Allocate memory for storing MAC addresses */
1224         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1225                                                hw->mac.num_rar_entries, 0);
1226         if (eth_dev->data->mac_addrs == NULL) {
1227                 PMD_INIT_LOG(ERR,
1228                              "Failed to allocate %u bytes needed to store "
1229                              "MAC addresses",
1230                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1231                 return -ENOMEM;
1232         }
1233         /* Copy the permanent MAC address */
1234         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1235                         &eth_dev->data->mac_addrs[0]);
1236
1237         /* Allocate memory for storing hash filter MAC addresses */
1238         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1239                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1240         if (eth_dev->data->hash_mac_addrs == NULL) {
1241                 PMD_INIT_LOG(ERR,
1242                              "Failed to allocate %d bytes needed to store MAC addresses",
1243                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1244                 return -ENOMEM;
1245         }
1246
1247         /* initialize the vfta */
1248         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1249
1250         /* initialize the hw strip bitmap*/
1251         memset(hwstrip, 0, sizeof(*hwstrip));
1252
1253         /* initialize PF if max_vfs not zero */
1254         ixgbe_pf_host_init(eth_dev);
1255
1256         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1257         /* let hardware know driver is loaded */
1258         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1259         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1260         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1261         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1262         IXGBE_WRITE_FLUSH(hw);
1263
1264         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1265                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1266                              (int) hw->mac.type, (int) hw->phy.type,
1267                              (int) hw->phy.sfp_type);
1268         else
1269                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1270                              (int) hw->mac.type, (int) hw->phy.type);
1271
1272         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1273                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1274                      pci_dev->id.device_id);
1275
1276         rte_intr_callback_register(intr_handle,
1277                                    ixgbe_dev_interrupt_handler, eth_dev);
1278
1279         /* enable uio/vfio intr/eventfd mapping */
1280         rte_intr_enable(intr_handle);
1281
1282         /* enable support intr */
1283         ixgbe_enable_intr(eth_dev);
1284
1285         /* initialize 5tuple filter list */
1286         TAILQ_INIT(&filter_info->fivetuple_list);
1287         memset(filter_info->fivetuple_mask, 0,
1288                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1289
1290         return 0;
1291 }
1292
1293 static int
1294 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1295 {
1296         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1297         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1298         struct ixgbe_hw *hw;
1299
1300         PMD_INIT_FUNC_TRACE();
1301
1302         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1303                 return -EPERM;
1304
1305         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1306
1307         if (hw->adapter_stopped == 0)
1308                 ixgbe_dev_close(eth_dev);
1309
1310         eth_dev->dev_ops = NULL;
1311         eth_dev->rx_pkt_burst = NULL;
1312         eth_dev->tx_pkt_burst = NULL;
1313
1314         /* Unlock any pending hardware semaphore */
1315         ixgbe_swfw_lock_reset(hw);
1316
1317         /* disable uio intr before callback unregister */
1318         rte_intr_disable(intr_handle);
1319         rte_intr_callback_unregister(intr_handle,
1320                                      ixgbe_dev_interrupt_handler, eth_dev);
1321
1322         /* uninitialize PF if max_vfs not zero */
1323         ixgbe_pf_host_uninit(eth_dev);
1324
1325         rte_free(eth_dev->data->mac_addrs);
1326         eth_dev->data->mac_addrs = NULL;
1327
1328         rte_free(eth_dev->data->hash_mac_addrs);
1329         eth_dev->data->hash_mac_addrs = NULL;
1330
1331         return 0;
1332 }
1333
1334 /*
1335  * Negotiate mailbox API version with the PF.
1336  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1337  * Then we try to negotiate starting with the most recent one.
1338  * If all negotiation attempts fail, then we will proceed with
1339  * the default one (ixgbe_mbox_api_10).
1340  */
1341 static void
1342 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1343 {
1344         int32_t i;
1345
1346         /* start with highest supported, proceed down */
1347         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1348                 ixgbe_mbox_api_12,
1349                 ixgbe_mbox_api_11,
1350                 ixgbe_mbox_api_10,
1351         };
1352
1353         for (i = 0;
1354                         i != RTE_DIM(sup_ver) &&
1355                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1356                         i++)
1357                 ;
1358 }
1359
1360 static void
1361 generate_random_mac_addr(struct ether_addr *mac_addr)
1362 {
1363         uint64_t random;
1364
1365         /* Set Organizationally Unique Identifier (OUI) prefix. */
1366         mac_addr->addr_bytes[0] = 0x00;
1367         mac_addr->addr_bytes[1] = 0x09;
1368         mac_addr->addr_bytes[2] = 0xC0;
1369         /* Force indication of locally assigned MAC address. */
1370         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1371         /* Generate the last 3 bytes of the MAC address with a random number. */
1372         random = rte_rand();
1373         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1374 }
1375
1376 /*
1377  * Virtual Function device init
1378  */
1379 static int
1380 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1381 {
1382         int diag;
1383         uint32_t tc, tcs;
1384         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1385         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1386         struct ixgbe_hw *hw =
1387                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1388         struct ixgbe_vfta *shadow_vfta =
1389                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1390         struct ixgbe_hwstrip *hwstrip =
1391                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1392         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1393
1394         PMD_INIT_FUNC_TRACE();
1395
1396         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1397         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1398         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1399
1400         /* for secondary processes, we don't initialise any further as primary
1401          * has already done this work. Only check we don't need a different
1402          * RX function
1403          */
1404         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1405                 struct ixgbe_tx_queue *txq;
1406                 /* TX queue function in primary, set by last queue initialized
1407                  * Tx queue may not initialized by primary process
1408                  */
1409                 if (eth_dev->data->tx_queues) {
1410                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1411                         ixgbe_set_tx_function(eth_dev, txq);
1412                 } else {
1413                         /* Use default TX function if we get here */
1414                         PMD_INIT_LOG(NOTICE,
1415                                      "No TX queues configured yet. Using default TX function.");
1416                 }
1417
1418                 ixgbe_set_rx_function(eth_dev);
1419
1420                 return 0;
1421         }
1422
1423         rte_eth_copy_pci_info(eth_dev, pci_dev);
1424
1425         hw->device_id = pci_dev->id.device_id;
1426         hw->vendor_id = pci_dev->id.vendor_id;
1427         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1428
1429         /* initialize the vfta */
1430         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1431
1432         /* initialize the hw strip bitmap*/
1433         memset(hwstrip, 0, sizeof(*hwstrip));
1434
1435         /* Initialize the shared code (base driver) */
1436         diag = ixgbe_init_shared_code(hw);
1437         if (diag != IXGBE_SUCCESS) {
1438                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1439                 return -EIO;
1440         }
1441
1442         /* init_mailbox_params */
1443         hw->mbx.ops.init_params(hw);
1444
1445         /* Reset the hw statistics */
1446         ixgbevf_dev_stats_reset(eth_dev);
1447
1448         /* Disable the interrupts for VF */
1449         ixgbevf_intr_disable(hw);
1450
1451         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1452         diag = hw->mac.ops.reset_hw(hw);
1453
1454         /*
1455          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1456          * the underlying PF driver has not assigned a MAC address to the VF.
1457          * In this case, assign a random MAC address.
1458          */
1459         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1460                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1461                 return diag;
1462         }
1463
1464         /* negotiate mailbox API version to use with the PF. */
1465         ixgbevf_negotiate_api(hw);
1466
1467         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1468         ixgbevf_get_queues(hw, &tcs, &tc);
1469
1470         /* Allocate memory for storing MAC addresses */
1471         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1472                                                hw->mac.num_rar_entries, 0);
1473         if (eth_dev->data->mac_addrs == NULL) {
1474                 PMD_INIT_LOG(ERR,
1475                              "Failed to allocate %u bytes needed to store "
1476                              "MAC addresses",
1477                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1478                 return -ENOMEM;
1479         }
1480
1481         /* Generate a random MAC address, if none was assigned by PF. */
1482         if (is_zero_ether_addr(perm_addr)) {
1483                 generate_random_mac_addr(perm_addr);
1484                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1485                 if (diag) {
1486                         rte_free(eth_dev->data->mac_addrs);
1487                         eth_dev->data->mac_addrs = NULL;
1488                         return diag;
1489                 }
1490                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1491                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1492                              "%02x:%02x:%02x:%02x:%02x:%02x",
1493                              perm_addr->addr_bytes[0],
1494                              perm_addr->addr_bytes[1],
1495                              perm_addr->addr_bytes[2],
1496                              perm_addr->addr_bytes[3],
1497                              perm_addr->addr_bytes[4],
1498                              perm_addr->addr_bytes[5]);
1499         }
1500
1501         /* Copy the permanent MAC address */
1502         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1503
1504         /* reset the hardware with the new settings */
1505         diag = hw->mac.ops.start_hw(hw);
1506         switch (diag) {
1507         case  0:
1508                 break;
1509
1510         default:
1511                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1512                 return -EIO;
1513         }
1514
1515         rte_intr_callback_register(intr_handle,
1516                                    ixgbevf_dev_interrupt_handler, eth_dev);
1517         rte_intr_enable(intr_handle);
1518         ixgbevf_intr_enable(hw);
1519
1520         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1521                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1522                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1523
1524         return 0;
1525 }
1526
1527 /* Virtual Function device uninit */
1528
1529 static int
1530 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1531 {
1532         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1533         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1534         struct ixgbe_hw *hw;
1535
1536         PMD_INIT_FUNC_TRACE();
1537
1538         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1539                 return -EPERM;
1540
1541         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1542
1543         if (hw->adapter_stopped == 0)
1544                 ixgbevf_dev_close(eth_dev);
1545
1546         eth_dev->dev_ops = NULL;
1547         eth_dev->rx_pkt_burst = NULL;
1548         eth_dev->tx_pkt_burst = NULL;
1549
1550         /* Disable the interrupts for VF */
1551         ixgbevf_intr_disable(hw);
1552
1553         rte_free(eth_dev->data->mac_addrs);
1554         eth_dev->data->mac_addrs = NULL;
1555
1556         rte_intr_disable(intr_handle);
1557         rte_intr_callback_unregister(intr_handle,
1558                                      ixgbevf_dev_interrupt_handler, eth_dev);
1559
1560         return 0;
1561 }
1562
1563 static struct eth_driver rte_ixgbe_pmd = {
1564         .pci_drv = {
1565                 .id_table = pci_id_ixgbe_map,
1566                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1567                         RTE_PCI_DRV_DETACHABLE,
1568                 .probe = rte_eth_dev_pci_probe,
1569                 .remove = rte_eth_dev_pci_remove,
1570         },
1571         .eth_dev_init = eth_ixgbe_dev_init,
1572         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1573         .dev_private_size = sizeof(struct ixgbe_adapter),
1574 };
1575
1576 /*
1577  * virtual function driver struct
1578  */
1579 static struct eth_driver rte_ixgbevf_pmd = {
1580         .pci_drv = {
1581                 .id_table = pci_id_ixgbevf_map,
1582                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1583                 .probe = rte_eth_dev_pci_probe,
1584                 .remove = rte_eth_dev_pci_remove,
1585         },
1586         .eth_dev_init = eth_ixgbevf_dev_init,
1587         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1588         .dev_private_size = sizeof(struct ixgbe_adapter),
1589 };
1590
1591 static int
1592 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1593 {
1594         struct ixgbe_hw *hw =
1595                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1596         struct ixgbe_vfta *shadow_vfta =
1597                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1598         uint32_t vfta;
1599         uint32_t vid_idx;
1600         uint32_t vid_bit;
1601
1602         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1603         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1604         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1605         if (on)
1606                 vfta |= vid_bit;
1607         else
1608                 vfta &= ~vid_bit;
1609         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1610
1611         /* update local VFTA copy */
1612         shadow_vfta->vfta[vid_idx] = vfta;
1613
1614         return 0;
1615 }
1616
1617 static void
1618 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1619 {
1620         if (on)
1621                 ixgbe_vlan_hw_strip_enable(dev, queue);
1622         else
1623                 ixgbe_vlan_hw_strip_disable(dev, queue);
1624 }
1625
1626 static int
1627 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1628                     enum rte_vlan_type vlan_type,
1629                     uint16_t tpid)
1630 {
1631         struct ixgbe_hw *hw =
1632                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1633         int ret = 0;
1634         uint32_t reg;
1635         uint32_t qinq;
1636
1637         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1638         qinq &= IXGBE_DMATXCTL_GDV;
1639
1640         switch (vlan_type) {
1641         case ETH_VLAN_TYPE_INNER:
1642                 if (qinq) {
1643                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1644                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1645                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1646                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1647                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1648                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1649                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1650                 } else {
1651                         ret = -ENOTSUP;
1652                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1653                                     " by single VLAN");
1654                 }
1655                 break;
1656         case ETH_VLAN_TYPE_OUTER:
1657                 if (qinq) {
1658                         /* Only the high 16-bits is valid */
1659                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1660                                         IXGBE_EXVET_VET_EXT_SHIFT);
1661                 } else {
1662                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1663                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1664                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1665                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1666                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1667                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1668                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1669                 }
1670
1671                 break;
1672         default:
1673                 ret = -EINVAL;
1674                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1675                 break;
1676         }
1677
1678         return ret;
1679 }
1680
1681 void
1682 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1683 {
1684         struct ixgbe_hw *hw =
1685                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1686         uint32_t vlnctrl;
1687
1688         PMD_INIT_FUNC_TRACE();
1689
1690         /* Filter Table Disable */
1691         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1692         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1693
1694         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1695 }
1696
1697 void
1698 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1699 {
1700         struct ixgbe_hw *hw =
1701                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1702         struct ixgbe_vfta *shadow_vfta =
1703                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1704         uint32_t vlnctrl;
1705         uint16_t i;
1706
1707         PMD_INIT_FUNC_TRACE();
1708
1709         /* Filter Table Enable */
1710         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1711         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1712         vlnctrl |= IXGBE_VLNCTRL_VFE;
1713
1714         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1715
1716         /* write whatever is in local vfta copy */
1717         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1718                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1719 }
1720
1721 static void
1722 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1723 {
1724         struct ixgbe_hwstrip *hwstrip =
1725                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1726         struct ixgbe_rx_queue *rxq;
1727
1728         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1729                 return;
1730
1731         if (on)
1732                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1733         else
1734                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1735
1736         if (queue >= dev->data->nb_rx_queues)
1737                 return;
1738
1739         rxq = dev->data->rx_queues[queue];
1740
1741         if (on)
1742                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1743         else
1744                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1745 }
1746
1747 static void
1748 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1749 {
1750         struct ixgbe_hw *hw =
1751                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1752         uint32_t ctrl;
1753
1754         PMD_INIT_FUNC_TRACE();
1755
1756         if (hw->mac.type == ixgbe_mac_82598EB) {
1757                 /* No queue level support */
1758                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1759                 return;
1760         }
1761
1762         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1763         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1764         ctrl &= ~IXGBE_RXDCTL_VME;
1765         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1766
1767         /* record those setting for HW strip per queue */
1768         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1769 }
1770
1771 static void
1772 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1773 {
1774         struct ixgbe_hw *hw =
1775                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1776         uint32_t ctrl;
1777
1778         PMD_INIT_FUNC_TRACE();
1779
1780         if (hw->mac.type == ixgbe_mac_82598EB) {
1781                 /* No queue level supported */
1782                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1783                 return;
1784         }
1785
1786         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1787         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1788         ctrl |= IXGBE_RXDCTL_VME;
1789         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1790
1791         /* record those setting for HW strip per queue */
1792         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1793 }
1794
1795 void
1796 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1797 {
1798         struct ixgbe_hw *hw =
1799                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1800         uint32_t ctrl;
1801         uint16_t i;
1802         struct ixgbe_rx_queue *rxq;
1803
1804         PMD_INIT_FUNC_TRACE();
1805
1806         if (hw->mac.type == ixgbe_mac_82598EB) {
1807                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1808                 ctrl &= ~IXGBE_VLNCTRL_VME;
1809                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1810         } else {
1811                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1812                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1813                         rxq = dev->data->rx_queues[i];
1814                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1815                         ctrl &= ~IXGBE_RXDCTL_VME;
1816                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1817
1818                         /* record those setting for HW strip per queue */
1819                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1820                 }
1821         }
1822 }
1823
1824 void
1825 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1826 {
1827         struct ixgbe_hw *hw =
1828                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1829         uint32_t ctrl;
1830         uint16_t i;
1831         struct ixgbe_rx_queue *rxq;
1832
1833         PMD_INIT_FUNC_TRACE();
1834
1835         if (hw->mac.type == ixgbe_mac_82598EB) {
1836                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1837                 ctrl |= IXGBE_VLNCTRL_VME;
1838                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1839         } else {
1840                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1841                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1842                         rxq = dev->data->rx_queues[i];
1843                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1844                         ctrl |= IXGBE_RXDCTL_VME;
1845                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1846
1847                         /* record those setting for HW strip per queue */
1848                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1849                 }
1850         }
1851 }
1852
1853 static void
1854 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1855 {
1856         struct ixgbe_hw *hw =
1857                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1858         uint32_t ctrl;
1859
1860         PMD_INIT_FUNC_TRACE();
1861
1862         /* DMATXCTRL: Geric Double VLAN Disable */
1863         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1864         ctrl &= ~IXGBE_DMATXCTL_GDV;
1865         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1866
1867         /* CTRL_EXT: Global Double VLAN Disable */
1868         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1869         ctrl &= ~IXGBE_EXTENDED_VLAN;
1870         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1871
1872 }
1873
1874 static void
1875 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1876 {
1877         struct ixgbe_hw *hw =
1878                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1879         uint32_t ctrl;
1880
1881         PMD_INIT_FUNC_TRACE();
1882
1883         /* DMATXCTRL: Geric Double VLAN Enable */
1884         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1885         ctrl |= IXGBE_DMATXCTL_GDV;
1886         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1887
1888         /* CTRL_EXT: Global Double VLAN Enable */
1889         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1890         ctrl |= IXGBE_EXTENDED_VLAN;
1891         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1892
1893         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1894         if (hw->mac.type == ixgbe_mac_X550 ||
1895             hw->mac.type == ixgbe_mac_X550EM_x ||
1896             hw->mac.type == ixgbe_mac_X550EM_a) {
1897                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1898                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1899                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1900         }
1901
1902         /*
1903          * VET EXT field in the EXVET register = 0x8100 by default
1904          * So no need to change. Same to VT field of DMATXCTL register
1905          */
1906 }
1907
1908 static void
1909 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1910 {
1911         if (mask & ETH_VLAN_STRIP_MASK) {
1912                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1913                         ixgbe_vlan_hw_strip_enable_all(dev);
1914                 else
1915                         ixgbe_vlan_hw_strip_disable_all(dev);
1916         }
1917
1918         if (mask & ETH_VLAN_FILTER_MASK) {
1919                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1920                         ixgbe_vlan_hw_filter_enable(dev);
1921                 else
1922                         ixgbe_vlan_hw_filter_disable(dev);
1923         }
1924
1925         if (mask & ETH_VLAN_EXTEND_MASK) {
1926                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1927                         ixgbe_vlan_hw_extend_enable(dev);
1928                 else
1929                         ixgbe_vlan_hw_extend_disable(dev);
1930         }
1931 }
1932
1933 static void
1934 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1935 {
1936         struct ixgbe_hw *hw =
1937                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1939         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1940
1941         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1942         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1943 }
1944
1945 static int
1946 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1947 {
1948         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
1949
1950         switch (nb_rx_q) {
1951         case 1:
1952         case 2:
1953                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1954                 break;
1955         case 4:
1956                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1957                 break;
1958         default:
1959                 return -EINVAL;
1960         }
1961
1962         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1963         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
1964
1965         return 0;
1966 }
1967
1968 static int
1969 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1970 {
1971         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1972         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1973         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1974         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1975
1976         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1977                 /* check multi-queue mode */
1978                 switch (dev_conf->rxmode.mq_mode) {
1979                 case ETH_MQ_RX_VMDQ_DCB:
1980                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1981                         break;
1982                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1983                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1984                         PMD_INIT_LOG(ERR, "SRIOV active,"
1985                                         " unsupported mq_mode rx %d.",
1986                                         dev_conf->rxmode.mq_mode);
1987                         return -EINVAL;
1988                 case ETH_MQ_RX_RSS:
1989                 case ETH_MQ_RX_VMDQ_RSS:
1990                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1991                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1992                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1993                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1994                                                 " invalid queue number"
1995                                                 " for VMDQ RSS, allowed"
1996                                                 " value are 1, 2 or 4.");
1997                                         return -EINVAL;
1998                                 }
1999                         break;
2000                 case ETH_MQ_RX_VMDQ_ONLY:
2001                 case ETH_MQ_RX_NONE:
2002                         /* if nothing mq mode configure, use default scheme */
2003                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2004                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2005                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2006                         break;
2007                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2008                         /* SRIOV only works in VMDq enable mode */
2009                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2010                                         " wrong mq_mode rx %d.",
2011                                         dev_conf->rxmode.mq_mode);
2012                         return -EINVAL;
2013                 }
2014
2015                 switch (dev_conf->txmode.mq_mode) {
2016                 case ETH_MQ_TX_VMDQ_DCB:
2017                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2018                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2019                         break;
2020                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2021                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2022                         break;
2023                 }
2024
2025                 /* check valid queue number */
2026                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2027                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2028                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2029                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2030                                         " must be less than or equal to %d.",
2031                                         nb_rx_q, nb_tx_q,
2032                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2033                         return -EINVAL;
2034                 }
2035         } else {
2036                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2037                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2038                                           " not supported.");
2039                         return -EINVAL;
2040                 }
2041                 /* check configuration for vmdb+dcb mode */
2042                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2043                         const struct rte_eth_vmdq_dcb_conf *conf;
2044
2045                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2046                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2047                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2048                                 return -EINVAL;
2049                         }
2050                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2051                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2052                                conf->nb_queue_pools == ETH_32_POOLS)) {
2053                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2054                                                 " nb_queue_pools must be %d or %d.",
2055                                                 ETH_16_POOLS, ETH_32_POOLS);
2056                                 return -EINVAL;
2057                         }
2058                 }
2059                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2060                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2061
2062                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2063                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2064                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2065                                 return -EINVAL;
2066                         }
2067                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2068                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2069                                conf->nb_queue_pools == ETH_32_POOLS)) {
2070                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2071                                                 " nb_queue_pools != %d and"
2072                                                 " nb_queue_pools != %d.",
2073                                                 ETH_16_POOLS, ETH_32_POOLS);
2074                                 return -EINVAL;
2075                         }
2076                 }
2077
2078                 /* For DCB mode check our configuration before we go further */
2079                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2080                         const struct rte_eth_dcb_rx_conf *conf;
2081
2082                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2083                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2084                                                  IXGBE_DCB_NB_QUEUES);
2085                                 return -EINVAL;
2086                         }
2087                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2088                         if (!(conf->nb_tcs == ETH_4_TCS ||
2089                                conf->nb_tcs == ETH_8_TCS)) {
2090                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2091                                                 " and nb_tcs != %d.",
2092                                                 ETH_4_TCS, ETH_8_TCS);
2093                                 return -EINVAL;
2094                         }
2095                 }
2096
2097                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2098                         const struct rte_eth_dcb_tx_conf *conf;
2099
2100                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2101                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2102                                                  IXGBE_DCB_NB_QUEUES);
2103                                 return -EINVAL;
2104                         }
2105                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2106                         if (!(conf->nb_tcs == ETH_4_TCS ||
2107                                conf->nb_tcs == ETH_8_TCS)) {
2108                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2109                                                 " and nb_tcs != %d.",
2110                                                 ETH_4_TCS, ETH_8_TCS);
2111                                 return -EINVAL;
2112                         }
2113                 }
2114
2115                 /*
2116                  * When DCB/VT is off, maximum number of queues changes,
2117                  * except for 82598EB, which remains constant.
2118                  */
2119                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2120                                 hw->mac.type != ixgbe_mac_82598EB) {
2121                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2122                                 PMD_INIT_LOG(ERR,
2123                                              "Neither VT nor DCB are enabled, "
2124                                              "nb_tx_q > %d.",
2125                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2126                                 return -EINVAL;
2127                         }
2128                 }
2129         }
2130         return 0;
2131 }
2132
2133 static int
2134 ixgbe_dev_configure(struct rte_eth_dev *dev)
2135 {
2136         struct ixgbe_interrupt *intr =
2137                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2138         struct ixgbe_adapter *adapter =
2139                 (struct ixgbe_adapter *)dev->data->dev_private;
2140         int ret;
2141
2142         PMD_INIT_FUNC_TRACE();
2143         /* multipe queue mode checking */
2144         ret  = ixgbe_check_mq_mode(dev);
2145         if (ret != 0) {
2146                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2147                             ret);
2148                 return ret;
2149         }
2150
2151         /* set flag to update link status after init */
2152         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2153
2154         /*
2155          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2156          * allocation or vector Rx preconditions we will reset it.
2157          */
2158         adapter->rx_bulk_alloc_allowed = true;
2159         adapter->rx_vec_allowed = true;
2160
2161         return 0;
2162 }
2163
2164 static void
2165 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2166 {
2167         struct ixgbe_hw *hw =
2168                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2169         struct ixgbe_interrupt *intr =
2170                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2171         uint32_t gpie;
2172
2173         /* only set up it on X550EM_X */
2174         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2175                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2176                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2177                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2178                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2179                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2180         }
2181 }
2182
2183 /*
2184  * Configure device link speed and setup link.
2185  * It returns 0 on success.
2186  */
2187 static int
2188 ixgbe_dev_start(struct rte_eth_dev *dev)
2189 {
2190         struct ixgbe_hw *hw =
2191                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2192         struct ixgbe_vf_info *vfinfo =
2193                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2194         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2195         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2196         uint32_t intr_vector = 0;
2197         int err, link_up = 0, negotiate = 0;
2198         uint32_t speed = 0;
2199         int mask = 0;
2200         int status;
2201         uint16_t vf, idx;
2202         uint32_t *link_speeds;
2203
2204         PMD_INIT_FUNC_TRACE();
2205
2206         /* IXGBE devices don't support:
2207         *    - half duplex (checked afterwards for valid speeds)
2208         *    - fixed speed: TODO implement
2209         */
2210         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2211                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2212                              dev->data->port_id);
2213                 return -EINVAL;
2214         }
2215
2216         /* disable uio/vfio intr/eventfd mapping */
2217         rte_intr_disable(intr_handle);
2218
2219         /* stop adapter */
2220         hw->adapter_stopped = 0;
2221         ixgbe_stop_adapter(hw);
2222
2223         /* reinitialize adapter
2224          * this calls reset and start
2225          */
2226         status = ixgbe_pf_reset_hw(hw);
2227         if (status != 0)
2228                 return -1;
2229         hw->mac.ops.start_hw(hw);
2230         hw->mac.get_link_status = true;
2231
2232         /* configure PF module if SRIOV enabled */
2233         ixgbe_pf_host_configure(dev);
2234
2235         ixgbe_dev_phy_intr_setup(dev);
2236
2237         /* check and configure queue intr-vector mapping */
2238         if ((rte_intr_cap_multiple(intr_handle) ||
2239              !RTE_ETH_DEV_SRIOV(dev).active) &&
2240             dev->data->dev_conf.intr_conf.rxq != 0) {
2241                 intr_vector = dev->data->nb_rx_queues;
2242                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2243                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2244                                         IXGBE_MAX_INTR_QUEUE_NUM);
2245                         return -ENOTSUP;
2246                 }
2247                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2248                         return -1;
2249         }
2250
2251         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2252                 intr_handle->intr_vec =
2253                         rte_zmalloc("intr_vec",
2254                                     dev->data->nb_rx_queues * sizeof(int), 0);
2255                 if (intr_handle->intr_vec == NULL) {
2256                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2257                                      " intr_vec\n", dev->data->nb_rx_queues);
2258                         return -ENOMEM;
2259                 }
2260         }
2261
2262         /* confiugre msix for sleep until rx interrupt */
2263         ixgbe_configure_msix(dev);
2264
2265         /* initialize transmission unit */
2266         ixgbe_dev_tx_init(dev);
2267
2268         /* This can fail when allocating mbufs for descriptor rings */
2269         err = ixgbe_dev_rx_init(dev);
2270         if (err) {
2271                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2272                 goto error;
2273         }
2274
2275     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2276                 ETH_VLAN_EXTEND_MASK;
2277         ixgbe_vlan_offload_set(dev, mask);
2278
2279         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2280                 /* Enable vlan filtering for VMDq */
2281                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2282         }
2283
2284         /* Configure DCB hw */
2285         ixgbe_configure_dcb(dev);
2286
2287         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2288                 err = ixgbe_fdir_configure(dev);
2289                 if (err)
2290                         goto error;
2291         }
2292
2293         /* Restore vf rate limit */
2294         if (vfinfo != NULL) {
2295                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2296                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2297                                 if (vfinfo[vf].tx_rate[idx] != 0)
2298                                         ixgbe_set_vf_rate_limit(dev, vf,
2299                                                 vfinfo[vf].tx_rate[idx],
2300                                                 1 << idx);
2301         }
2302
2303         ixgbe_restore_statistics_mapping(dev);
2304
2305         err = ixgbe_dev_rxtx_start(dev);
2306         if (err < 0) {
2307                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2308                 goto error;
2309         }
2310
2311         /* Skip link setup if loopback mode is enabled for 82599. */
2312         if (hw->mac.type == ixgbe_mac_82599EB &&
2313                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2314                 goto skip_link_setup;
2315
2316         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2317                 err = hw->mac.ops.setup_sfp(hw);
2318                 if (err)
2319                         goto error;
2320         }
2321
2322         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2323                 /* Turn on the copper */
2324                 ixgbe_set_phy_power(hw, true);
2325         } else {
2326                 /* Turn on the laser */
2327                 ixgbe_enable_tx_laser(hw);
2328         }
2329
2330         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2331         if (err)
2332                 goto error;
2333         dev->data->dev_link.link_status = link_up;
2334
2335         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2336         if (err)
2337                 goto error;
2338
2339         link_speeds = &dev->data->dev_conf.link_speeds;
2340         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2341                         ETH_LINK_SPEED_10G)) {
2342                 PMD_INIT_LOG(ERR, "Invalid link setting");
2343                 goto error;
2344         }
2345
2346         speed = 0x0;
2347         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2348                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2349                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2350                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2351         } else {
2352                 if (*link_speeds & ETH_LINK_SPEED_10G)
2353                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2354                 if (*link_speeds & ETH_LINK_SPEED_1G)
2355                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2356                 if (*link_speeds & ETH_LINK_SPEED_100M)
2357                         speed |= IXGBE_LINK_SPEED_100_FULL;
2358         }
2359
2360         err = ixgbe_setup_link(hw, speed, link_up);
2361         if (err)
2362                 goto error;
2363
2364 skip_link_setup:
2365
2366         if (rte_intr_allow_others(intr_handle)) {
2367                 /* check if lsc interrupt is enabled */
2368                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2369                         ixgbe_dev_lsc_interrupt_setup(dev);
2370         } else {
2371                 rte_intr_callback_unregister(intr_handle,
2372                                              ixgbe_dev_interrupt_handler, dev);
2373                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2374                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2375                                      " no intr multiplex\n");
2376         }
2377
2378         /* check if rxq interrupt is enabled */
2379         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2380             rte_intr_dp_is_en(intr_handle))
2381                 ixgbe_dev_rxq_interrupt_setup(dev);
2382
2383         /* enable uio/vfio intr/eventfd mapping */
2384         rte_intr_enable(intr_handle);
2385
2386         /* resume enabled intr since hw reset */
2387         ixgbe_enable_intr(dev);
2388
2389         return 0;
2390
2391 error:
2392         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2393         ixgbe_dev_clear_queues(dev);
2394         return -EIO;
2395 }
2396
2397 /*
2398  * Stop device: disable rx and tx functions to allow for reconfiguring.
2399  */
2400 static void
2401 ixgbe_dev_stop(struct rte_eth_dev *dev)
2402 {
2403         struct rte_eth_link link;
2404         struct ixgbe_hw *hw =
2405                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2406         struct ixgbe_vf_info *vfinfo =
2407                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2408         struct ixgbe_filter_info *filter_info =
2409                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2410         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2411         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2412         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2413         int vf;
2414
2415         PMD_INIT_FUNC_TRACE();
2416
2417         /* disable interrupts */
2418         ixgbe_disable_intr(hw);
2419
2420         /* reset the NIC */
2421         ixgbe_pf_reset_hw(hw);
2422         hw->adapter_stopped = 0;
2423
2424         /* stop adapter */
2425         ixgbe_stop_adapter(hw);
2426
2427         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2428                 vfinfo[vf].clear_to_send = false;
2429
2430         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2431                 /* Turn off the copper */
2432                 ixgbe_set_phy_power(hw, false);
2433         } else {
2434                 /* Turn off the laser */
2435                 ixgbe_disable_tx_laser(hw);
2436         }
2437
2438         ixgbe_dev_clear_queues(dev);
2439
2440         /* Clear stored conf */
2441         dev->data->scattered_rx = 0;
2442         dev->data->lro = 0;
2443
2444         /* Clear recorded link status */
2445         memset(&link, 0, sizeof(link));
2446         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2447
2448         /* Remove all ntuple filters of the device */
2449         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2450              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2451                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2452                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2453                              p_5tuple, entries);
2454                 rte_free(p_5tuple);
2455         }
2456         memset(filter_info->fivetuple_mask, 0,
2457                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2458
2459         if (!rte_intr_allow_others(intr_handle))
2460                 /* resume to the default handler */
2461                 rte_intr_callback_register(intr_handle,
2462                                            ixgbe_dev_interrupt_handler,
2463                                            (void *)dev);
2464
2465         /* Clean datapath event and queue/vec mapping */
2466         rte_intr_efd_disable(intr_handle);
2467         if (intr_handle->intr_vec != NULL) {
2468                 rte_free(intr_handle->intr_vec);
2469                 intr_handle->intr_vec = NULL;
2470         }
2471 }
2472
2473 /*
2474  * Set device link up: enable tx.
2475  */
2476 static int
2477 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2478 {
2479         struct ixgbe_hw *hw =
2480                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2481         if (hw->mac.type == ixgbe_mac_82599EB) {
2482 #ifdef RTE_NIC_BYPASS
2483                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2484                         /* Not suported in bypass mode */
2485                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2486                                      "by device id 0x%x", hw->device_id);
2487                         return -ENOTSUP;
2488                 }
2489 #endif
2490         }
2491
2492         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2493                 /* Turn on the copper */
2494                 ixgbe_set_phy_power(hw, true);
2495         } else {
2496                 /* Turn on the laser */
2497                 ixgbe_enable_tx_laser(hw);
2498         }
2499
2500         return 0;
2501 }
2502
2503 /*
2504  * Set device link down: disable tx.
2505  */
2506 static int
2507 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2508 {
2509         struct ixgbe_hw *hw =
2510                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2511         if (hw->mac.type == ixgbe_mac_82599EB) {
2512 #ifdef RTE_NIC_BYPASS
2513                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2514                         /* Not suported in bypass mode */
2515                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2516                                      "by device id 0x%x", hw->device_id);
2517                         return -ENOTSUP;
2518                 }
2519 #endif
2520         }
2521
2522         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2523                 /* Turn off the copper */
2524                 ixgbe_set_phy_power(hw, false);
2525         } else {
2526                 /* Turn off the laser */
2527                 ixgbe_disable_tx_laser(hw);
2528         }
2529
2530         return 0;
2531 }
2532
2533 /*
2534  * Reest and stop device.
2535  */
2536 static void
2537 ixgbe_dev_close(struct rte_eth_dev *dev)
2538 {
2539         struct ixgbe_hw *hw =
2540                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541
2542         PMD_INIT_FUNC_TRACE();
2543
2544         ixgbe_pf_reset_hw(hw);
2545
2546         ixgbe_dev_stop(dev);
2547         hw->adapter_stopped = 1;
2548
2549         ixgbe_dev_free_queues(dev);
2550
2551         ixgbe_disable_pcie_master(hw);
2552
2553         /* reprogram the RAR[0] in case user changed it. */
2554         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2555 }
2556
2557 static void
2558 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2559                            struct ixgbe_hw_stats *hw_stats,
2560                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2561                            uint64_t *total_qprc, uint64_t *total_qprdc)
2562 {
2563         uint32_t bprc, lxon, lxoff, total;
2564         uint32_t delta_gprc = 0;
2565         unsigned i;
2566         /* Workaround for RX byte count not including CRC bytes when CRC
2567 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2568          * is disabled.
2569 +        */
2570         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2571                         IXGBE_HLREG0_RXCRCSTRP);
2572
2573         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2574         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2575         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2576         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2577
2578         for (i = 0; i < 8; i++) {
2579                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2580
2581                 /* global total per queue */
2582                 hw_stats->mpc[i] += mp;
2583                 /* Running comprehensive total for stats display */
2584                 *total_missed_rx += hw_stats->mpc[i];
2585                 if (hw->mac.type == ixgbe_mac_82598EB) {
2586                         hw_stats->rnbc[i] +=
2587                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2588                         hw_stats->pxonrxc[i] +=
2589                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2590                         hw_stats->pxoffrxc[i] +=
2591                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2592                 } else {
2593                         hw_stats->pxonrxc[i] +=
2594                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2595                         hw_stats->pxoffrxc[i] +=
2596                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2597                         hw_stats->pxon2offc[i] +=
2598                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2599                 }
2600                 hw_stats->pxontxc[i] +=
2601                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2602                 hw_stats->pxofftxc[i] +=
2603                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2604         }
2605         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2606                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2607                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2608                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2609
2610                 delta_gprc += delta_qprc;
2611
2612                 hw_stats->qprc[i] += delta_qprc;
2613                 hw_stats->qptc[i] += delta_qptc;
2614
2615                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2616                 hw_stats->qbrc[i] +=
2617                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2618                 if (crc_strip == 0)
2619                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2620
2621                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2622                 hw_stats->qbtc[i] +=
2623                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2624
2625                 hw_stats->qprdc[i] += delta_qprdc;
2626                 *total_qprdc += hw_stats->qprdc[i];
2627
2628                 *total_qprc += hw_stats->qprc[i];
2629                 *total_qbrc += hw_stats->qbrc[i];
2630         }
2631         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2632         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2633         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2634
2635         /*
2636          * An errata states that gprc actually counts good + missed packets:
2637          * Workaround to set gprc to summated queue packet receives
2638          */
2639         hw_stats->gprc = *total_qprc;
2640
2641         if (hw->mac.type != ixgbe_mac_82598EB) {
2642                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2643                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2644                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2645                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2646                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2647                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2648                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2649                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2650         } else {
2651                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2652                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2653                 /* 82598 only has a counter in the high register */
2654                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2655                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2656                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2657         }
2658         uint64_t old_tpr = hw_stats->tpr;
2659
2660         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2661         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2662
2663         if (crc_strip == 0)
2664                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2665
2666         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2667         hw_stats->gptc += delta_gptc;
2668         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2669         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2670
2671         /*
2672          * Workaround: mprc hardware is incorrectly counting
2673          * broadcasts, so for now we subtract those.
2674          */
2675         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2676         hw_stats->bprc += bprc;
2677         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2678         if (hw->mac.type == ixgbe_mac_82598EB)
2679                 hw_stats->mprc -= bprc;
2680
2681         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2682         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2683         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2684         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2685         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2686         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2687
2688         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2689         hw_stats->lxontxc += lxon;
2690         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2691         hw_stats->lxofftxc += lxoff;
2692         total = lxon + lxoff;
2693
2694         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2695         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2696         hw_stats->gptc -= total;
2697         hw_stats->mptc -= total;
2698         hw_stats->ptc64 -= total;
2699         hw_stats->gotc -= total * ETHER_MIN_LEN;
2700
2701         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2702         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2703         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2704         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2705         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2706         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2707         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2708         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2709         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2710         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2711         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2712         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2713         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2714         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2715         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2716         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2717         /* Only read FCOE on 82599 */
2718         if (hw->mac.type != ixgbe_mac_82598EB) {
2719                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2720                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2721                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2722                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2723                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2724         }
2725
2726         /* Flow Director Stats registers */
2727         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2728         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2729 }
2730
2731 /*
2732  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2733  */
2734 static void
2735 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2736 {
2737         struct ixgbe_hw *hw =
2738                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2739         struct ixgbe_hw_stats *hw_stats =
2740                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2741         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2742         unsigned i;
2743
2744         total_missed_rx = 0;
2745         total_qbrc = 0;
2746         total_qprc = 0;
2747         total_qprdc = 0;
2748
2749         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2750                         &total_qprc, &total_qprdc);
2751
2752         if (stats == NULL)
2753                 return;
2754
2755         /* Fill out the rte_eth_stats statistics structure */
2756         stats->ipackets = total_qprc;
2757         stats->ibytes = total_qbrc;
2758         stats->opackets = hw_stats->gptc;
2759         stats->obytes = hw_stats->gotc;
2760
2761         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2762                 stats->q_ipackets[i] = hw_stats->qprc[i];
2763                 stats->q_opackets[i] = hw_stats->qptc[i];
2764                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2765                 stats->q_obytes[i] = hw_stats->qbtc[i];
2766                 stats->q_errors[i] = hw_stats->qprdc[i];
2767         }
2768
2769         /* Rx Errors */
2770         stats->imissed  = total_missed_rx;
2771         stats->ierrors  = hw_stats->crcerrs +
2772                           hw_stats->mspdc +
2773                           hw_stats->rlec +
2774                           hw_stats->ruc +
2775                           hw_stats->roc +
2776                           hw_stats->illerrc +
2777                           hw_stats->errbc +
2778                           hw_stats->rfc +
2779                           hw_stats->fccrc +
2780                           hw_stats->fclast;
2781
2782         /* Tx Errors */
2783         stats->oerrors  = 0;
2784 }
2785
2786 static void
2787 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2788 {
2789         struct ixgbe_hw_stats *stats =
2790                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2791
2792         /* HW registers are cleared on read */
2793         ixgbe_dev_stats_get(dev, NULL);
2794
2795         /* Reset software totals */
2796         memset(stats, 0, sizeof(*stats));
2797 }
2798
2799 /* This function calculates the number of xstats based on the current config */
2800 static unsigned
2801 ixgbe_xstats_calc_num(void) {
2802         return IXGBE_NB_HW_STATS +
2803                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2804                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2805 }
2806
2807 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2808         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2809 {
2810         const unsigned cnt_stats = ixgbe_xstats_calc_num();
2811         unsigned stat, i, count;
2812
2813         if (xstats_names != NULL) {
2814                 count = 0;
2815
2816                 /* Note: limit >= cnt_stats checked upstream
2817                  * in rte_eth_xstats_names()
2818                  */
2819
2820                 /* Extended stats from ixgbe_hw_stats */
2821                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2822                         snprintf(xstats_names[count].name,
2823                                 sizeof(xstats_names[count].name),
2824                                 "%s",
2825                                 rte_ixgbe_stats_strings[i].name);
2826                         count++;
2827                 }
2828
2829                 /* RX Priority Stats */
2830                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2831                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2832                                 snprintf(xstats_names[count].name,
2833                                         sizeof(xstats_names[count].name),
2834                                         "rx_priority%u_%s", i,
2835                                         rte_ixgbe_rxq_strings[stat].name);
2836                                 count++;
2837                         }
2838                 }
2839
2840                 /* TX Priority Stats */
2841                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2842                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2843                                 snprintf(xstats_names[count].name,
2844                                         sizeof(xstats_names[count].name),
2845                                         "tx_priority%u_%s", i,
2846                                         rte_ixgbe_txq_strings[stat].name);
2847                                 count++;
2848                         }
2849                 }
2850         }
2851         return cnt_stats;
2852 }
2853
2854 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2855         struct rte_eth_xstat_name *xstats_names, unsigned limit)
2856 {
2857         unsigned i;
2858
2859         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2860                 return -ENOMEM;
2861
2862         if (xstats_names != NULL)
2863                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2864                         snprintf(xstats_names[i].name,
2865                                 sizeof(xstats_names[i].name),
2866                                 "%s", rte_ixgbevf_stats_strings[i].name);
2867         return IXGBEVF_NB_XSTATS;
2868 }
2869
2870 static int
2871 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2872                                          unsigned n)
2873 {
2874         struct ixgbe_hw *hw =
2875                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876         struct ixgbe_hw_stats *hw_stats =
2877                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2878         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2879         unsigned i, stat, count = 0;
2880
2881         count = ixgbe_xstats_calc_num();
2882
2883         if (n < count)
2884                 return count;
2885
2886         total_missed_rx = 0;
2887         total_qbrc = 0;
2888         total_qprc = 0;
2889         total_qprdc = 0;
2890
2891         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2892                                    &total_qprc, &total_qprdc);
2893
2894         /* If this is a reset xstats is NULL, and we have cleared the
2895          * registers by reading them.
2896          */
2897         if (!xstats)
2898                 return 0;
2899
2900         /* Extended stats from ixgbe_hw_stats */
2901         count = 0;
2902         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2903                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2904                                 rte_ixgbe_stats_strings[i].offset);
2905                 xstats[count].id = count;
2906                 count++;
2907         }
2908
2909         /* RX Priority Stats */
2910         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2911                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2912                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2913                                         rte_ixgbe_rxq_strings[stat].offset +
2914                                         (sizeof(uint64_t) * i));
2915                         xstats[count].id = count;
2916                         count++;
2917                 }
2918         }
2919
2920         /* TX Priority Stats */
2921         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2922                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2923                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2924                                         rte_ixgbe_txq_strings[stat].offset +
2925                                         (sizeof(uint64_t) * i));
2926                         xstats[count].id = count;
2927                         count++;
2928                 }
2929         }
2930         return count;
2931 }
2932
2933 static void
2934 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2935 {
2936         struct ixgbe_hw_stats *stats =
2937                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2938
2939         unsigned count = ixgbe_xstats_calc_num();
2940
2941         /* HW registers are cleared on read */
2942         ixgbe_dev_xstats_get(dev, NULL, count);
2943
2944         /* Reset software totals */
2945         memset(stats, 0, sizeof(*stats));
2946 }
2947
2948 static void
2949 ixgbevf_update_stats(struct rte_eth_dev *dev)
2950 {
2951         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2952         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2953                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2954
2955         /* Good Rx packet, include VF loopback */
2956         UPDATE_VF_STAT(IXGBE_VFGPRC,
2957             hw_stats->last_vfgprc, hw_stats->vfgprc);
2958
2959         /* Good Rx octets, include VF loopback */
2960         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2961             hw_stats->last_vfgorc, hw_stats->vfgorc);
2962
2963         /* Good Tx packet, include VF loopback */
2964         UPDATE_VF_STAT(IXGBE_VFGPTC,
2965             hw_stats->last_vfgptc, hw_stats->vfgptc);
2966
2967         /* Good Tx octets, include VF loopback */
2968         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2969             hw_stats->last_vfgotc, hw_stats->vfgotc);
2970
2971         /* Rx Multicst Packet */
2972         UPDATE_VF_STAT(IXGBE_VFMPRC,
2973             hw_stats->last_vfmprc, hw_stats->vfmprc);
2974 }
2975
2976 static int
2977 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2978                        unsigned n)
2979 {
2980         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2981                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2982         unsigned i;
2983
2984         if (n < IXGBEVF_NB_XSTATS)
2985                 return IXGBEVF_NB_XSTATS;
2986
2987         ixgbevf_update_stats(dev);
2988
2989         if (!xstats)
2990                 return 0;
2991
2992         /* Extended stats */
2993         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2994                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2995                         rte_ixgbevf_stats_strings[i].offset);
2996         }
2997
2998         return IXGBEVF_NB_XSTATS;
2999 }
3000
3001 static void
3002 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3003 {
3004         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3005                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3006
3007         ixgbevf_update_stats(dev);
3008
3009         if (stats == NULL)
3010                 return;
3011
3012         stats->ipackets = hw_stats->vfgprc;
3013         stats->ibytes = hw_stats->vfgorc;
3014         stats->opackets = hw_stats->vfgptc;
3015         stats->obytes = hw_stats->vfgotc;
3016 }
3017
3018 static void
3019 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3020 {
3021         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3022                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3023
3024         /* Sync HW register to the last stats */
3025         ixgbevf_dev_stats_get(dev, NULL);
3026
3027         /* reset HW current stats*/
3028         hw_stats->vfgprc = 0;
3029         hw_stats->vfgorc = 0;
3030         hw_stats->vfgptc = 0;
3031         hw_stats->vfgotc = 0;
3032 }
3033
3034 static void
3035 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3036 {
3037         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3038         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3039         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3040
3041         dev_info->pci_dev = pci_dev;
3042         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3043         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3044         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3045                 /*
3046                  * When DCB/VT is off, maximum number of queues changes,
3047                  * except for 82598EB, which remains constant.
3048                  */
3049                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3050                                 hw->mac.type != ixgbe_mac_82598EB)
3051                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3052         }
3053         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3054         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3055         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3056         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3057         dev_info->max_vfs = pci_dev->max_vfs;
3058         if (hw->mac.type == ixgbe_mac_82598EB)
3059                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3060         else
3061                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3062         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3063         dev_info->rx_offload_capa =
3064                 DEV_RX_OFFLOAD_VLAN_STRIP |
3065                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3066                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3067                 DEV_RX_OFFLOAD_TCP_CKSUM;
3068
3069         /*
3070          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3071          * mode.
3072          */
3073         if ((hw->mac.type == ixgbe_mac_82599EB ||
3074              hw->mac.type == ixgbe_mac_X540) &&
3075             !RTE_ETH_DEV_SRIOV(dev).active)
3076                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3077
3078         if (hw->mac.type == ixgbe_mac_X550 ||
3079             hw->mac.type == ixgbe_mac_X550EM_x ||
3080             hw->mac.type == ixgbe_mac_X550EM_a)
3081                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3082
3083         dev_info->tx_offload_capa =
3084                 DEV_TX_OFFLOAD_VLAN_INSERT |
3085                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3086                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3087                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3088                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3089                 DEV_TX_OFFLOAD_TCP_TSO;
3090
3091         if (hw->mac.type == ixgbe_mac_X550 ||
3092             hw->mac.type == ixgbe_mac_X550EM_x ||
3093             hw->mac.type == ixgbe_mac_X550EM_a)
3094                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3095
3096         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3097                 .rx_thresh = {
3098                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3099                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3100                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3101                 },
3102                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3103                 .rx_drop_en = 0,
3104         };
3105
3106         dev_info->default_txconf = (struct rte_eth_txconf) {
3107                 .tx_thresh = {
3108                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3109                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3110                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3111                 },
3112                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3113                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3114                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3115                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3116         };
3117
3118         dev_info->rx_desc_lim = rx_desc_lim;
3119         dev_info->tx_desc_lim = tx_desc_lim;
3120
3121         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3122         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3123         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3124
3125         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3126         if (hw->mac.type == ixgbe_mac_X540 ||
3127             hw->mac.type == ixgbe_mac_X540_vf ||
3128             hw->mac.type == ixgbe_mac_X550 ||
3129             hw->mac.type == ixgbe_mac_X550_vf) {
3130                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3131         }
3132 }
3133
3134 static const uint32_t *
3135 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3136 {
3137         static const uint32_t ptypes[] = {
3138                 /* For non-vec functions,
3139                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3140                  * for vec functions,
3141                  * refers to _recv_raw_pkts_vec().
3142                  */
3143                 RTE_PTYPE_L2_ETHER,
3144                 RTE_PTYPE_L3_IPV4,
3145                 RTE_PTYPE_L3_IPV4_EXT,
3146                 RTE_PTYPE_L3_IPV6,
3147                 RTE_PTYPE_L3_IPV6_EXT,
3148                 RTE_PTYPE_L4_SCTP,
3149                 RTE_PTYPE_L4_TCP,
3150                 RTE_PTYPE_L4_UDP,
3151                 RTE_PTYPE_TUNNEL_IP,
3152                 RTE_PTYPE_INNER_L3_IPV6,
3153                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3154                 RTE_PTYPE_INNER_L4_TCP,
3155                 RTE_PTYPE_INNER_L4_UDP,
3156                 RTE_PTYPE_UNKNOWN
3157         };
3158
3159         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3160             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3161             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3162             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3163                 return ptypes;
3164         return NULL;
3165 }
3166
3167 static void
3168 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3169                      struct rte_eth_dev_info *dev_info)
3170 {
3171         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3172         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3173
3174         dev_info->pci_dev = pci_dev;
3175         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3176         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3177         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3178         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3179         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3180         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3181         dev_info->max_vfs = pci_dev->max_vfs;
3182         if (hw->mac.type == ixgbe_mac_82598EB)
3183                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3184         else
3185                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3186         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3187                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3188                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3189                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3190         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3191                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3192                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3193                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3194                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3195                                 DEV_TX_OFFLOAD_TCP_TSO;
3196
3197         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3198                 .rx_thresh = {
3199                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3200                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3201                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3202                 },
3203                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3204                 .rx_drop_en = 0,
3205         };
3206
3207         dev_info->default_txconf = (struct rte_eth_txconf) {
3208                 .tx_thresh = {
3209                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3210                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3211                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3212                 },
3213                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3214                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3215                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3216                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3217         };
3218
3219         dev_info->rx_desc_lim = rx_desc_lim;
3220         dev_info->tx_desc_lim = tx_desc_lim;
3221 }
3222
3223 /* return 0 means link status changed, -1 means not changed */
3224 static int
3225 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3226 {
3227         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3228         struct rte_eth_link link, old;
3229         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3230         int link_up;
3231         int diag;
3232
3233         link.link_status = ETH_LINK_DOWN;
3234         link.link_speed = 0;
3235         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3236         memset(&old, 0, sizeof(old));
3237         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3238
3239         hw->mac.get_link_status = true;
3240
3241         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3242         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3243                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3244         else
3245                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3246
3247         if (diag != 0) {
3248                 link.link_speed = ETH_SPEED_NUM_100M;
3249                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3250                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3251                 if (link.link_status == old.link_status)
3252                         return -1;
3253                 return 0;
3254         }
3255
3256         if (link_up == 0) {
3257                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3258                 if (link.link_status == old.link_status)
3259                         return -1;
3260                 return 0;
3261         }
3262         link.link_status = ETH_LINK_UP;
3263         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3264
3265         switch (link_speed) {
3266         default:
3267         case IXGBE_LINK_SPEED_UNKNOWN:
3268                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3269                 link.link_speed = ETH_SPEED_NUM_100M;
3270                 break;
3271
3272         case IXGBE_LINK_SPEED_100_FULL:
3273                 link.link_speed = ETH_SPEED_NUM_100M;
3274                 break;
3275
3276         case IXGBE_LINK_SPEED_1GB_FULL:
3277                 link.link_speed = ETH_SPEED_NUM_1G;
3278                 break;
3279
3280         case IXGBE_LINK_SPEED_10GB_FULL:
3281                 link.link_speed = ETH_SPEED_NUM_10G;
3282                 break;
3283         }
3284         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3285
3286         if (link.link_status == old.link_status)
3287                 return -1;
3288
3289         return 0;
3290 }
3291
3292 static void
3293 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3294 {
3295         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3296         uint32_t fctrl;
3297
3298         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3299         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3300         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3301 }
3302
3303 static void
3304 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3305 {
3306         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3307         uint32_t fctrl;
3308
3309         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3310         fctrl &= (~IXGBE_FCTRL_UPE);
3311         if (dev->data->all_multicast == 1)
3312                 fctrl |= IXGBE_FCTRL_MPE;
3313         else
3314                 fctrl &= (~IXGBE_FCTRL_MPE);
3315         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3316 }
3317
3318 static void
3319 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3320 {
3321         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3322         uint32_t fctrl;
3323
3324         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3325         fctrl |= IXGBE_FCTRL_MPE;
3326         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3327 }
3328
3329 static void
3330 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3331 {
3332         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3333         uint32_t fctrl;
3334
3335         if (dev->data->promiscuous == 1)
3336                 return; /* must remain in all_multicast mode */
3337
3338         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3339         fctrl &= (~IXGBE_FCTRL_MPE);
3340         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3341 }
3342
3343 /**
3344  * It clears the interrupt causes and enables the interrupt.
3345  * It will be called once only during nic initialized.
3346  *
3347  * @param dev
3348  *  Pointer to struct rte_eth_dev.
3349  *
3350  * @return
3351  *  - On success, zero.
3352  *  - On failure, a negative value.
3353  */
3354 static int
3355 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3356 {
3357         struct ixgbe_interrupt *intr =
3358                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3359
3360         ixgbe_dev_link_status_print(dev);
3361         intr->mask |= IXGBE_EICR_LSC;
3362
3363         return 0;
3364 }
3365
3366 /**
3367  * It clears the interrupt causes and enables the interrupt.
3368  * It will be called once only during nic initialized.
3369  *
3370  * @param dev
3371  *  Pointer to struct rte_eth_dev.
3372  *
3373  * @return
3374  *  - On success, zero.
3375  *  - On failure, a negative value.
3376  */
3377 static int
3378 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3379 {
3380         struct ixgbe_interrupt *intr =
3381                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3382
3383         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3384
3385         return 0;
3386 }
3387
3388 /*
3389  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3390  *
3391  * @param dev
3392  *  Pointer to struct rte_eth_dev.
3393  *
3394  * @return
3395  *  - On success, zero.
3396  *  - On failure, a negative value.
3397  */
3398 static int
3399 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3400 {
3401         uint32_t eicr;
3402         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3403         struct ixgbe_interrupt *intr =
3404                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3405
3406         /* clear all cause mask */
3407         ixgbe_disable_intr(hw);
3408
3409         /* read-on-clear nic registers here */
3410         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3411         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3412
3413         intr->flags = 0;
3414
3415         /* set flag for async link update */
3416         if (eicr & IXGBE_EICR_LSC)
3417                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3418
3419         if (eicr & IXGBE_EICR_MAILBOX)
3420                 intr->flags |= IXGBE_FLAG_MAILBOX;
3421
3422         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3423             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3424             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3425                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3426
3427         return 0;
3428 }
3429
3430 /**
3431  * It gets and then prints the link status.
3432  *
3433  * @param dev
3434  *  Pointer to struct rte_eth_dev.
3435  *
3436  * @return
3437  *  - On success, zero.
3438  *  - On failure, a negative value.
3439  */
3440 static void
3441 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3442 {
3443         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3444         struct rte_eth_link link;
3445
3446         memset(&link, 0, sizeof(link));
3447         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3448         if (link.link_status) {
3449                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3450                                         (int)(dev->data->port_id),
3451                                         (unsigned)link.link_speed,
3452                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3453                                         "full-duplex" : "half-duplex");
3454         } else {
3455                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3456                                 (int)(dev->data->port_id));
3457         }
3458         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3459                                 pci_dev->addr.domain,
3460                                 pci_dev->addr.bus,
3461                                 pci_dev->addr.devid,
3462                                 pci_dev->addr.function);
3463 }
3464
3465 /*
3466  * It executes link_update after knowing an interrupt occurred.
3467  *
3468  * @param dev
3469  *  Pointer to struct rte_eth_dev.
3470  *
3471  * @return
3472  *  - On success, zero.
3473  *  - On failure, a negative value.
3474  */
3475 static int
3476 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3477                            struct rte_intr_handle *intr_handle)
3478 {
3479         struct ixgbe_interrupt *intr =
3480                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3481         int64_t timeout;
3482         struct rte_eth_link link;
3483         int intr_enable_delay = false;
3484         struct ixgbe_hw *hw =
3485                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3486
3487         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3488
3489         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3490                 ixgbe_pf_mbx_process(dev);
3491                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3492         }
3493
3494         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3495                 ixgbe_handle_lasi(hw);
3496                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3497         }
3498
3499         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3500                 /* get the link status before link update, for predicting later */
3501                 memset(&link, 0, sizeof(link));
3502                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3503
3504                 ixgbe_dev_link_update(dev, 0);
3505
3506                 /* likely to up */
3507                 if (!link.link_status)
3508                         /* handle it 1 sec later, wait it being stable */
3509                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3510                 /* likely to down */
3511                 else
3512                         /* handle it 4 sec later, wait it being stable */
3513                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3514
3515                 ixgbe_dev_link_status_print(dev);
3516
3517                 intr_enable_delay = true;
3518         }
3519
3520         if (intr_enable_delay) {
3521                 if (rte_eal_alarm_set(timeout * 1000,
3522                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3523                         PMD_DRV_LOG(ERR, "Error setting alarm");
3524         } else {
3525                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3526                 ixgbe_enable_intr(dev);
3527                 rte_intr_enable(intr_handle);
3528         }
3529
3530
3531         return 0;
3532 }
3533
3534 /**
3535  * Interrupt handler which shall be registered for alarm callback for delayed
3536  * handling specific interrupt to wait for the stable nic state. As the
3537  * NIC interrupt state is not stable for ixgbe after link is just down,
3538  * it needs to wait 4 seconds to get the stable status.
3539  *
3540  * @param handle
3541  *  Pointer to interrupt handle.
3542  * @param param
3543  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3544  *
3545  * @return
3546  *  void
3547  */
3548 static void
3549 ixgbe_dev_interrupt_delayed_handler(void *param)
3550 {
3551         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3552         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3553         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3554         struct ixgbe_interrupt *intr =
3555                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3556         struct ixgbe_hw *hw =
3557                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3558         uint32_t eicr;
3559
3560         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3561         if (eicr & IXGBE_EICR_MAILBOX)
3562                 ixgbe_pf_mbx_process(dev);
3563
3564         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3565                 ixgbe_handle_lasi(hw);
3566                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3567         }
3568
3569         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3570                 ixgbe_dev_link_update(dev, 0);
3571                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3572                 ixgbe_dev_link_status_print(dev);
3573                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3574         }
3575
3576         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3577         ixgbe_enable_intr(dev);
3578         rte_intr_enable(intr_handle);
3579 }
3580
3581 /**
3582  * Interrupt handler triggered by NIC  for handling
3583  * specific interrupt.
3584  *
3585  * @param handle
3586  *  Pointer to interrupt handle.
3587  * @param param
3588  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3589  *
3590  * @return
3591  *  void
3592  */
3593 static void
3594 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3595                             void *param)
3596 {
3597         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3598
3599         ixgbe_dev_interrupt_get_status(dev);
3600         ixgbe_dev_interrupt_action(dev, handle);
3601 }
3602
3603 static int
3604 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3605 {
3606         struct ixgbe_hw *hw;
3607
3608         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3609         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3610 }
3611
3612 static int
3613 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3614 {
3615         struct ixgbe_hw *hw;
3616
3617         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3618         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3619 }
3620
3621 static int
3622 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3623 {
3624         struct ixgbe_hw *hw;
3625         uint32_t mflcn_reg;
3626         uint32_t fccfg_reg;
3627         int rx_pause;
3628         int tx_pause;
3629
3630         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3631
3632         fc_conf->pause_time = hw->fc.pause_time;
3633         fc_conf->high_water = hw->fc.high_water[0];
3634         fc_conf->low_water = hw->fc.low_water[0];
3635         fc_conf->send_xon = hw->fc.send_xon;
3636         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3637
3638         /*
3639          * Return rx_pause status according to actual setting of
3640          * MFLCN register.
3641          */
3642         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3643         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3644                 rx_pause = 1;
3645         else
3646                 rx_pause = 0;
3647
3648         /*
3649          * Return tx_pause status according to actual setting of
3650          * FCCFG register.
3651          */
3652         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3653         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3654                 tx_pause = 1;
3655         else
3656                 tx_pause = 0;
3657
3658         if (rx_pause && tx_pause)
3659                 fc_conf->mode = RTE_FC_FULL;
3660         else if (rx_pause)
3661                 fc_conf->mode = RTE_FC_RX_PAUSE;
3662         else if (tx_pause)
3663                 fc_conf->mode = RTE_FC_TX_PAUSE;
3664         else
3665                 fc_conf->mode = RTE_FC_NONE;
3666
3667         return 0;
3668 }
3669
3670 static int
3671 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3672 {
3673         struct ixgbe_hw *hw;
3674         int err;
3675         uint32_t rx_buf_size;
3676         uint32_t max_high_water;
3677         uint32_t mflcn;
3678         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3679                 ixgbe_fc_none,
3680                 ixgbe_fc_rx_pause,
3681                 ixgbe_fc_tx_pause,
3682                 ixgbe_fc_full
3683         };
3684
3685         PMD_INIT_FUNC_TRACE();
3686
3687         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3688         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3689         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3690
3691         /*
3692          * At least reserve one Ethernet frame for watermark
3693          * high_water/low_water in kilo bytes for ixgbe
3694          */
3695         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3696         if ((fc_conf->high_water > max_high_water) ||
3697                 (fc_conf->high_water < fc_conf->low_water)) {
3698                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3699                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3700                 return -EINVAL;
3701         }
3702
3703         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3704         hw->fc.pause_time     = fc_conf->pause_time;
3705         hw->fc.high_water[0]  = fc_conf->high_water;
3706         hw->fc.low_water[0]   = fc_conf->low_water;
3707         hw->fc.send_xon       = fc_conf->send_xon;
3708         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3709
3710         err = ixgbe_fc_enable(hw);
3711
3712         /* Not negotiated is not an error case */
3713         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3714
3715                 /* check if we want to forward MAC frames - driver doesn't have native
3716                  * capability to do that, so we'll write the registers ourselves */
3717
3718                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3719
3720                 /* set or clear MFLCN.PMCF bit depending on configuration */
3721                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3722                         mflcn |= IXGBE_MFLCN_PMCF;
3723                 else
3724                         mflcn &= ~IXGBE_MFLCN_PMCF;
3725
3726                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3727                 IXGBE_WRITE_FLUSH(hw);
3728
3729                 return 0;
3730         }
3731
3732         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3733         return -EIO;
3734 }
3735
3736 /**
3737  *  ixgbe_pfc_enable_generic - Enable flow control
3738  *  @hw: pointer to hardware structure
3739  *  @tc_num: traffic class number
3740  *  Enable flow control according to the current settings.
3741  */
3742 static int
3743 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3744 {
3745         int ret_val = 0;
3746         uint32_t mflcn_reg, fccfg_reg;
3747         uint32_t reg;
3748         uint32_t fcrtl, fcrth;
3749         uint8_t i;
3750         uint8_t nb_rx_en;
3751
3752         /* Validate the water mark configuration */
3753         if (!hw->fc.pause_time) {
3754                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3755                 goto out;
3756         }
3757
3758         /* Low water mark of zero causes XOFF floods */
3759         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3760                  /* High/Low water can not be 0 */
3761                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3762                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3763                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3764                         goto out;
3765                 }
3766
3767                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3768                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3769                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3770                         goto out;
3771                 }
3772         }
3773         /* Negotiate the fc mode to use */
3774         ixgbe_fc_autoneg(hw);
3775
3776         /* Disable any previous flow control settings */
3777         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3778         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3779
3780         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3781         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3782
3783         switch (hw->fc.current_mode) {
3784         case ixgbe_fc_none:
3785                 /*
3786                  * If the count of enabled RX Priority Flow control >1,
3787                  * and the TX pause can not be disabled
3788                  */
3789                 nb_rx_en = 0;
3790                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3791                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3792                         if (reg & IXGBE_FCRTH_FCEN)
3793                                 nb_rx_en++;
3794                 }
3795                 if (nb_rx_en > 1)
3796                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3797                 break;
3798         case ixgbe_fc_rx_pause:
3799                 /*
3800                  * Rx Flow control is enabled and Tx Flow control is
3801                  * disabled by software override. Since there really
3802                  * isn't a way to advertise that we are capable of RX
3803                  * Pause ONLY, we will advertise that we support both
3804                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3805                  * disable the adapter's ability to send PAUSE frames.
3806                  */
3807                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3808                 /*
3809                  * If the count of enabled RX Priority Flow control >1,
3810                  * and the TX pause can not be disabled
3811                  */
3812                 nb_rx_en = 0;
3813                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3814                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3815                         if (reg & IXGBE_FCRTH_FCEN)
3816                                 nb_rx_en++;
3817                 }
3818                 if (nb_rx_en > 1)
3819                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3820                 break;
3821         case ixgbe_fc_tx_pause:
3822                 /*
3823                  * Tx Flow control is enabled, and Rx Flow control is
3824                  * disabled by software override.
3825                  */
3826                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3827                 break;
3828         case ixgbe_fc_full:
3829                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3830                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3831                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3832                 break;
3833         default:
3834                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3835                 ret_val = IXGBE_ERR_CONFIG;
3836                 goto out;
3837         }
3838
3839         /* Set 802.3x based flow control settings. */
3840         mflcn_reg |= IXGBE_MFLCN_DPF;
3841         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3842         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3843
3844         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3845         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3846                 hw->fc.high_water[tc_num]) {
3847                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3848                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3849                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3850         } else {
3851                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3852                 /*
3853                  * In order to prevent Tx hangs when the internal Tx
3854                  * switch is enabled we must set the high water mark
3855                  * to the maximum FCRTH value.  This allows the Tx
3856                  * switch to function even under heavy Rx workloads.
3857                  */
3858                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3859         }
3860         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3861
3862         /* Configure pause time (2 TCs per register) */
3863         reg = hw->fc.pause_time * 0x00010001;
3864         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3865                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3866
3867         /* Configure flow control refresh threshold value */
3868         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3869
3870 out:
3871         return ret_val;
3872 }
3873
3874 static int
3875 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
3876 {
3877         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3878         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3879
3880         if (hw->mac.type != ixgbe_mac_82598EB) {
3881                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
3882         }
3883         return ret_val;
3884 }
3885
3886 static int
3887 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3888 {
3889         int err;
3890         uint32_t rx_buf_size;
3891         uint32_t max_high_water;
3892         uint8_t tc_num;
3893         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3894         struct ixgbe_hw *hw =
3895                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3896         struct ixgbe_dcb_config *dcb_config =
3897                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3898
3899         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3900                 ixgbe_fc_none,
3901                 ixgbe_fc_rx_pause,
3902                 ixgbe_fc_tx_pause,
3903                 ixgbe_fc_full
3904         };
3905
3906         PMD_INIT_FUNC_TRACE();
3907
3908         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3909         tc_num = map[pfc_conf->priority];
3910         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3911         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3912         /*
3913          * At least reserve one Ethernet frame for watermark
3914          * high_water/low_water in kilo bytes for ixgbe
3915          */
3916         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3917         if ((pfc_conf->fc.high_water > max_high_water) ||
3918             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3919                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3920                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3921                 return -EINVAL;
3922         }
3923
3924         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3925         hw->fc.pause_time = pfc_conf->fc.pause_time;
3926         hw->fc.send_xon = pfc_conf->fc.send_xon;
3927         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3928         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3929
3930         err = ixgbe_dcb_pfc_enable(dev, tc_num);
3931
3932         /* Not negotiated is not an error case */
3933         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3934                 return 0;
3935
3936         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3937         return -EIO;
3938 }
3939
3940 static int
3941 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3942                           struct rte_eth_rss_reta_entry64 *reta_conf,
3943                           uint16_t reta_size)
3944 {
3945         uint16_t i, sp_reta_size;
3946         uint8_t j, mask;
3947         uint32_t reta, r;
3948         uint16_t idx, shift;
3949         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3950         uint32_t reta_reg;
3951
3952         PMD_INIT_FUNC_TRACE();
3953
3954         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3955                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3956                         "NIC.");
3957                 return -ENOTSUP;
3958         }
3959
3960         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3961         if (reta_size != sp_reta_size) {
3962                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3963                         "(%d) doesn't match the number hardware can supported "
3964                         "(%d)\n", reta_size, sp_reta_size);
3965                 return -EINVAL;
3966         }
3967
3968         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3969                 idx = i / RTE_RETA_GROUP_SIZE;
3970                 shift = i % RTE_RETA_GROUP_SIZE;
3971                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3972                                                 IXGBE_4_BIT_MASK);
3973                 if (!mask)
3974                         continue;
3975                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3976                 if (mask == IXGBE_4_BIT_MASK)
3977                         r = 0;
3978                 else
3979                         r = IXGBE_READ_REG(hw, reta_reg);
3980                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3981                         if (mask & (0x1 << j))
3982                                 reta |= reta_conf[idx].reta[shift + j] <<
3983                                                         (CHAR_BIT * j);
3984                         else
3985                                 reta |= r & (IXGBE_8_BIT_MASK <<
3986                                                 (CHAR_BIT * j));
3987                 }
3988                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3989         }
3990
3991         return 0;
3992 }
3993
3994 static int
3995 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3996                          struct rte_eth_rss_reta_entry64 *reta_conf,
3997                          uint16_t reta_size)
3998 {
3999         uint16_t i, sp_reta_size;
4000         uint8_t j, mask;
4001         uint32_t reta;
4002         uint16_t idx, shift;
4003         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4004         uint32_t reta_reg;
4005
4006         PMD_INIT_FUNC_TRACE();
4007         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4008         if (reta_size != sp_reta_size) {
4009                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4010                         "(%d) doesn't match the number hardware can supported "
4011                         "(%d)\n", reta_size, sp_reta_size);
4012                 return -EINVAL;
4013         }
4014
4015         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4016                 idx = i / RTE_RETA_GROUP_SIZE;
4017                 shift = i % RTE_RETA_GROUP_SIZE;
4018                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4019                                                 IXGBE_4_BIT_MASK);
4020                 if (!mask)
4021                         continue;
4022
4023                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4024                 reta = IXGBE_READ_REG(hw, reta_reg);
4025                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4026                         if (mask & (0x1 << j))
4027                                 reta_conf[idx].reta[shift + j] =
4028                                         ((reta >> (CHAR_BIT * j)) &
4029                                                 IXGBE_8_BIT_MASK);
4030                 }
4031         }
4032
4033         return 0;
4034 }
4035
4036 static void
4037 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4038                                 uint32_t index, uint32_t pool)
4039 {
4040         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4041         uint32_t enable_addr = 1;
4042
4043         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4044 }
4045
4046 static void
4047 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4048 {
4049         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4050
4051         ixgbe_clear_rar(hw, index);
4052 }
4053
4054 static void
4055 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4056 {
4057         ixgbe_remove_rar(dev, 0);
4058
4059         ixgbe_add_rar(dev, addr, 0, 0);
4060 }
4061
4062 int
4063 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4064                 struct ether_addr *mac_addr)
4065 {
4066         struct ixgbe_hw *hw;
4067         struct ixgbe_vf_info *vfinfo;
4068         int rar_entry;
4069         uint8_t *new_mac = (uint8_t *)(mac_addr);
4070         struct rte_eth_dev *dev;
4071         struct rte_eth_dev_info dev_info;
4072
4073         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4074
4075         dev = &rte_eth_devices[port];
4076         rte_eth_dev_info_get(port, &dev_info);
4077
4078         if (vf >= dev_info.max_vfs)
4079                 return -EINVAL;
4080
4081         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4082         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4083         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4084
4085         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4086                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4087                                 ETHER_ADDR_LEN);
4088                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4089                                 IXGBE_RAH_AV);
4090         }
4091         return -EINVAL;
4092 }
4093
4094 static int
4095 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4096 {
4097         uint32_t hlreg0;
4098         uint32_t maxfrs;
4099         struct ixgbe_hw *hw;
4100         struct rte_eth_dev_info dev_info;
4101         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4102
4103         ixgbe_dev_info_get(dev, &dev_info);
4104
4105         /* check that mtu is within the allowed range */
4106         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4107                 return -EINVAL;
4108
4109         /* refuse mtu that requires the support of scattered packets when this
4110          * feature has not been enabled before.
4111          */
4112         if (!dev->data->scattered_rx &&
4113             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4114              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4115                 return -EINVAL;
4116
4117         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4118         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4119
4120         /* switch to jumbo mode if needed */
4121         if (frame_size > ETHER_MAX_LEN) {
4122                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4123                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4124         } else {
4125                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4126                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4127         }
4128         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4129
4130         /* update max frame size */
4131         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4132
4133         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4134         maxfrs &= 0x0000FFFF;
4135         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4136         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4137
4138         return 0;
4139 }
4140
4141 /*
4142  * Virtual Function operations
4143  */
4144 static void
4145 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4146 {
4147         PMD_INIT_FUNC_TRACE();
4148
4149         /* Clear interrupt mask to stop from interrupts being generated */
4150         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4151
4152         IXGBE_WRITE_FLUSH(hw);
4153 }
4154
4155 static void
4156 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4157 {
4158         PMD_INIT_FUNC_TRACE();
4159
4160         /* VF enable interrupt autoclean */
4161         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4162         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4163         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4164
4165         IXGBE_WRITE_FLUSH(hw);
4166 }
4167
4168 static int
4169 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4170 {
4171         struct rte_eth_conf *conf = &dev->data->dev_conf;
4172         struct ixgbe_adapter *adapter =
4173                         (struct ixgbe_adapter *)dev->data->dev_private;
4174
4175         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4176                      dev->data->port_id);
4177
4178         /*
4179          * VF has no ability to enable/disable HW CRC
4180          * Keep the persistent behavior the same as Host PF
4181          */
4182 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4183         if (!conf->rxmode.hw_strip_crc) {
4184                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4185                 conf->rxmode.hw_strip_crc = 1;
4186         }
4187 #else
4188         if (conf->rxmode.hw_strip_crc) {
4189                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4190                 conf->rxmode.hw_strip_crc = 0;
4191         }
4192 #endif
4193
4194         /*
4195          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4196          * allocation or vector Rx preconditions we will reset it.
4197          */
4198         adapter->rx_bulk_alloc_allowed = true;
4199         adapter->rx_vec_allowed = true;
4200
4201         return 0;
4202 }
4203
4204 static int
4205 ixgbevf_dev_start(struct rte_eth_dev *dev)
4206 {
4207         struct ixgbe_hw *hw =
4208                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4209         uint32_t intr_vector = 0;
4210         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4211         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4212
4213         int err, mask = 0;
4214
4215         PMD_INIT_FUNC_TRACE();
4216
4217         hw->mac.ops.reset_hw(hw);
4218         hw->mac.get_link_status = true;
4219
4220         /* negotiate mailbox API version to use with the PF. */
4221         ixgbevf_negotiate_api(hw);
4222
4223         ixgbevf_dev_tx_init(dev);
4224
4225         /* This can fail when allocating mbufs for descriptor rings */
4226         err = ixgbevf_dev_rx_init(dev);
4227         if (err) {
4228                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4229                 ixgbe_dev_clear_queues(dev);
4230                 return err;
4231         }
4232
4233         /* Set vfta */
4234         ixgbevf_set_vfta_all(dev, 1);
4235
4236         /* Set HW strip */
4237         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4238                 ETH_VLAN_EXTEND_MASK;
4239         ixgbevf_vlan_offload_set(dev, mask);
4240
4241         ixgbevf_dev_rxtx_start(dev);
4242
4243         /* check and configure queue intr-vector mapping */
4244         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4245                 intr_vector = dev->data->nb_rx_queues;
4246                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4247                         return -1;
4248         }
4249
4250         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4251                 intr_handle->intr_vec =
4252                         rte_zmalloc("intr_vec",
4253                                     dev->data->nb_rx_queues * sizeof(int), 0);
4254                 if (intr_handle->intr_vec == NULL) {
4255                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4256                                      " intr_vec\n", dev->data->nb_rx_queues);
4257                         return -ENOMEM;
4258                 }
4259         }
4260         ixgbevf_configure_msix(dev);
4261
4262         rte_intr_enable(intr_handle);
4263
4264         /* Re-enable interrupt for VF */
4265         ixgbevf_intr_enable(hw);
4266
4267         return 0;
4268 }
4269
4270 static void
4271 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4272 {
4273         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4274         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4275         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4276
4277         PMD_INIT_FUNC_TRACE();
4278
4279         ixgbevf_intr_disable(hw);
4280
4281         hw->adapter_stopped = 1;
4282         ixgbe_stop_adapter(hw);
4283
4284         /*
4285           * Clear what we set, but we still keep shadow_vfta to
4286           * restore after device starts
4287           */
4288         ixgbevf_set_vfta_all(dev, 0);
4289
4290         /* Clear stored conf */
4291         dev->data->scattered_rx = 0;
4292
4293         ixgbe_dev_clear_queues(dev);
4294
4295         /* Clean datapath event and queue/vec mapping */
4296         rte_intr_efd_disable(intr_handle);
4297         if (intr_handle->intr_vec != NULL) {
4298                 rte_free(intr_handle->intr_vec);
4299                 intr_handle->intr_vec = NULL;
4300         }
4301 }
4302
4303 static void
4304 ixgbevf_dev_close(struct rte_eth_dev *dev)
4305 {
4306         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4307
4308         PMD_INIT_FUNC_TRACE();
4309
4310         ixgbe_reset_hw(hw);
4311
4312         ixgbevf_dev_stop(dev);
4313
4314         ixgbe_dev_free_queues(dev);
4315
4316         /**
4317          * Remove the VF MAC address ro ensure
4318          * that the VF traffic goes to the PF
4319          * after stop, close and detach of the VF
4320          **/
4321         ixgbevf_remove_mac_addr(dev, 0);
4322 }
4323
4324 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4325 {
4326         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4327         struct ixgbe_vfta *shadow_vfta =
4328                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4329         int i = 0, j = 0, vfta = 0, mask = 1;
4330
4331         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4332                 vfta = shadow_vfta->vfta[i];
4333                 if (vfta) {
4334                         mask = 1;
4335                         for (j = 0; j < 32; j++) {
4336                                 if (vfta & mask)
4337                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4338                                                        on, false);
4339                                 mask <<= 1;
4340                         }
4341                 }
4342         }
4343
4344 }
4345
4346 static int
4347 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4348 {
4349         struct ixgbe_hw *hw =
4350                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4351         struct ixgbe_vfta *shadow_vfta =
4352                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4353         uint32_t vid_idx = 0;
4354         uint32_t vid_bit = 0;
4355         int ret = 0;
4356
4357         PMD_INIT_FUNC_TRACE();
4358
4359         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4360         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4361         if (ret) {
4362                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4363                 return ret;
4364         }
4365         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4366         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4367
4368         /* Save what we set and retore it after device reset */
4369         if (on)
4370                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4371         else
4372                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4373
4374         return 0;
4375 }
4376
4377 static void
4378 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4379 {
4380         struct ixgbe_hw *hw =
4381                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4382         uint32_t ctrl;
4383
4384         PMD_INIT_FUNC_TRACE();
4385
4386         if (queue >= hw->mac.max_rx_queues)
4387                 return;
4388
4389         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4390         if (on)
4391                 ctrl |= IXGBE_RXDCTL_VME;
4392         else
4393                 ctrl &= ~IXGBE_RXDCTL_VME;
4394         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4395
4396         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4397 }
4398
4399 static void
4400 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4401 {
4402         struct ixgbe_hw *hw =
4403                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4404         uint16_t i;
4405         int on = 0;
4406
4407         /* VF function only support hw strip feature, others are not support */
4408         if (mask & ETH_VLAN_STRIP_MASK) {
4409                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4410
4411                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4412                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4413         }
4414 }
4415
4416 static int
4417 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4418 {
4419         uint32_t reg_val;
4420
4421         /* we only need to do this if VMDq is enabled */
4422         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4423         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4424                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4425                 return -1;
4426         }
4427
4428         return 0;
4429 }
4430
4431 static uint32_t
4432 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4433 {
4434         uint32_t vector = 0;
4435
4436         switch (hw->mac.mc_filter_type) {
4437         case 0:   /* use bits [47:36] of the address */
4438                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4439                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4440                 break;
4441         case 1:   /* use bits [46:35] of the address */
4442                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4443                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4444                 break;
4445         case 2:   /* use bits [45:34] of the address */
4446                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4447                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4448                 break;
4449         case 3:   /* use bits [43:32] of the address */
4450                 vector = ((uc_addr->addr_bytes[4]) |
4451                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4452                 break;
4453         default:  /* Invalid mc_filter_type */
4454                 break;
4455         }
4456
4457         /* vector can only be 12-bits or boundary will be exceeded */
4458         vector &= 0xFFF;
4459         return vector;
4460 }
4461
4462 static int
4463 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4464                         uint8_t on)
4465 {
4466         uint32_t vector;
4467         uint32_t uta_idx;
4468         uint32_t reg_val;
4469         uint32_t uta_shift;
4470         uint32_t rc;
4471         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4472         const uint32_t ixgbe_uta_bit_shift = 5;
4473         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4474         const uint32_t bit1 = 0x1;
4475
4476         struct ixgbe_hw *hw =
4477                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4478         struct ixgbe_uta_info *uta_info =
4479                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4480
4481         /* The UTA table only exists on 82599 hardware and newer */
4482         if (hw->mac.type < ixgbe_mac_82599EB)
4483                 return -ENOTSUP;
4484
4485         vector = ixgbe_uta_vector(hw, mac_addr);
4486         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4487         uta_shift = vector & ixgbe_uta_bit_mask;
4488
4489         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4490         if (rc == on)
4491                 return 0;
4492
4493         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4494         if (on) {
4495                 uta_info->uta_in_use++;
4496                 reg_val |= (bit1 << uta_shift);
4497                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4498         } else {
4499                 uta_info->uta_in_use--;
4500                 reg_val &= ~(bit1 << uta_shift);
4501                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4502         }
4503
4504         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4505
4506         if (uta_info->uta_in_use > 0)
4507                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4508                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4509         else
4510                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4511
4512         return 0;
4513 }
4514
4515 static int
4516 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4517 {
4518         int i;
4519         struct ixgbe_hw *hw =
4520                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4521         struct ixgbe_uta_info *uta_info =
4522                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4523
4524         /* The UTA table only exists on 82599 hardware and newer */
4525         if (hw->mac.type < ixgbe_mac_82599EB)
4526                 return -ENOTSUP;
4527
4528         if (on) {
4529                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4530                         uta_info->uta_shadow[i] = ~0;
4531                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4532                 }
4533         } else {
4534                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4535                         uta_info->uta_shadow[i] = 0;
4536                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4537                 }
4538         }
4539         return 0;
4540
4541 }
4542
4543 uint32_t
4544 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4545 {
4546         uint32_t new_val = orig_val;
4547
4548         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4549                 new_val |= IXGBE_VMOLR_AUPE;
4550         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4551                 new_val |= IXGBE_VMOLR_ROMPE;
4552         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4553                 new_val |= IXGBE_VMOLR_ROPE;
4554         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4555                 new_val |= IXGBE_VMOLR_BAM;
4556         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4557                 new_val |= IXGBE_VMOLR_MPE;
4558
4559         return new_val;
4560 }
4561
4562 static int
4563 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4564                                uint16_t rx_mask, uint8_t on)
4565 {
4566         int val = 0;
4567
4568         struct ixgbe_hw *hw =
4569                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4570         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4571
4572         if (hw->mac.type == ixgbe_mac_82598EB) {
4573                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4574                              " on 82599 hardware and newer");
4575                 return -ENOTSUP;
4576         }
4577         if (ixgbe_vmdq_mode_check(hw) < 0)
4578                 return -ENOTSUP;
4579
4580         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4581
4582         if (on)
4583                 vmolr |= val;
4584         else
4585                 vmolr &= ~val;
4586
4587         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4588
4589         return 0;
4590 }
4591
4592 static int
4593 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4594 {
4595         uint32_t reg, addr;
4596         uint32_t val;
4597         const uint8_t bit1 = 0x1;
4598
4599         struct ixgbe_hw *hw =
4600                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4601
4602         if (ixgbe_vmdq_mode_check(hw) < 0)
4603                 return -ENOTSUP;
4604
4605         if (pool >= ETH_64_POOLS)
4606                 return -EINVAL;
4607
4608         /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4609         if (pool >= 32) {
4610                 addr = IXGBE_VFRE(1);
4611                 val = bit1 << (pool - 32);
4612         } else {
4613                 addr = IXGBE_VFRE(0);
4614                 val = bit1 << pool;
4615         }
4616
4617         reg = IXGBE_READ_REG(hw, addr);
4618
4619         if (on)
4620                 reg |= val;
4621         else
4622                 reg &= ~val;
4623
4624         IXGBE_WRITE_REG(hw, addr, reg);
4625
4626         return 0;
4627 }
4628
4629 static int
4630 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4631 {
4632         uint32_t reg, addr;
4633         uint32_t val;
4634         const uint8_t bit1 = 0x1;
4635
4636         struct ixgbe_hw *hw =
4637                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4638
4639         if (ixgbe_vmdq_mode_check(hw) < 0)
4640                 return -ENOTSUP;
4641
4642         if (pool >= ETH_64_POOLS)
4643                 return -EINVAL;
4644
4645         /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4646         if (pool >= 32) {
4647                 addr = IXGBE_VFTE(1);
4648                 val = bit1 << (pool - 32);
4649         } else {
4650                 addr = IXGBE_VFTE(0);
4651                 val = bit1 << pool;
4652         }
4653
4654         reg = IXGBE_READ_REG(hw, addr);
4655
4656         if (on)
4657                 reg |= val;
4658         else
4659                 reg &= ~val;
4660
4661         IXGBE_WRITE_REG(hw, addr, reg);
4662
4663         return 0;
4664 }
4665
4666 static int
4667 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4668                         uint64_t pool_mask, uint8_t vlan_on)
4669 {
4670         int ret = 0;
4671         uint16_t pool_idx;
4672         struct ixgbe_hw *hw =
4673                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4674
4675         if (ixgbe_vmdq_mode_check(hw) < 0)
4676                 return -ENOTSUP;
4677         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4678                 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4679                         ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx,
4680                                                    vlan_on, false);
4681                         if (ret < 0)
4682                                 return ret;
4683                 }
4684         }
4685
4686         return ret;
4687 }
4688
4689 int
4690 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4691 {
4692         struct ixgbe_hw *hw;
4693         struct ixgbe_mac_info *mac;
4694         struct rte_eth_dev *dev;
4695         struct rte_eth_dev_info dev_info;
4696
4697         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4698
4699         dev = &rte_eth_devices[port];
4700         rte_eth_dev_info_get(port, &dev_info);
4701
4702         if (vf >= dev_info.max_vfs)
4703                 return -EINVAL;
4704
4705         if (on > 1)
4706                 return -EINVAL;
4707
4708         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4709         mac = &hw->mac;
4710
4711         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4712
4713         return 0;
4714 }
4715
4716 int
4717 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4718 {
4719         struct ixgbe_hw *hw;
4720         struct ixgbe_mac_info *mac;
4721         struct rte_eth_dev *dev;
4722         struct rte_eth_dev_info dev_info;
4723
4724         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4725
4726         dev = &rte_eth_devices[port];
4727         rte_eth_dev_info_get(port, &dev_info);
4728
4729         if (vf >= dev_info.max_vfs)
4730                 return -EINVAL;
4731
4732         if (on > 1)
4733                 return -EINVAL;
4734
4735         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4736         mac = &hw->mac;
4737         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4738
4739         return 0;
4740 }
4741
4742 int
4743 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4744 {
4745         struct ixgbe_hw *hw;
4746         uint32_t ctrl;
4747         struct rte_eth_dev *dev;
4748         struct rte_eth_dev_info dev_info;
4749
4750         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4751
4752         dev = &rte_eth_devices[port];
4753         rte_eth_dev_info_get(port, &dev_info);
4754
4755         if (vf >= dev_info.max_vfs)
4756                 return -EINVAL;
4757
4758         if (vlan_id > 4095)
4759                 return -EINVAL;
4760
4761         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4762         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4763         if (vlan_id) {
4764                 ctrl = vlan_id;
4765                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4766         } else {
4767                 ctrl = 0;
4768         }
4769
4770         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4771
4772         return 0;
4773 }
4774
4775 int
4776 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4777 {
4778         struct ixgbe_hw *hw;
4779         uint32_t ctrl;
4780         struct rte_eth_dev *dev;
4781
4782         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4783
4784         dev = &rte_eth_devices[port];
4785
4786         if (on > 1)
4787                 return -EINVAL;
4788
4789         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4790         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4791         /* enable or disable VMDQ loopback */
4792         if (on)
4793                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
4794         else
4795                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4796
4797         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
4798
4799         return 0;
4800 }
4801
4802 int
4803 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
4804 {
4805         struct ixgbe_hw *hw;
4806         uint32_t reg_value;
4807         int i;
4808         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
4809         struct rte_eth_dev *dev;
4810
4811         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4812
4813         dev = &rte_eth_devices[port];
4814
4815         if (on > 1)
4816                 return -EINVAL;
4817
4818         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4819         for (i = 0; i <= num_queues; i++) {
4820                 reg_value = IXGBE_QDE_WRITE |
4821                                 (i << IXGBE_QDE_IDX_SHIFT) |
4822                                 (on & IXGBE_QDE_ENABLE);
4823                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
4824         }
4825
4826         return 0;
4827 }
4828
4829 int
4830 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
4831 {
4832         struct ixgbe_hw *hw;
4833         uint32_t reg_value;
4834         struct rte_eth_dev *dev;
4835         struct rte_eth_dev_info dev_info;
4836
4837         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4838
4839         dev = &rte_eth_devices[port];
4840         rte_eth_dev_info_get(port, &dev_info);
4841
4842         /* only support VF's 0 to 63 */
4843         if ((vf >= dev_info.max_vfs) || (vf > 63))
4844                 return -EINVAL;
4845
4846         if (on > 1)
4847                 return -EINVAL;
4848
4849         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4850         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
4851         if (on)
4852                 reg_value |= IXGBE_SRRCTL_DROP_EN;
4853         else
4854                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
4855
4856         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
4857
4858         return 0;
4859 }
4860
4861 int
4862 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
4863 {
4864         struct rte_eth_dev *dev;
4865         struct rte_eth_dev_info dev_info;
4866         uint16_t queues_per_pool;
4867         uint32_t q;
4868
4869         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4870
4871         dev = &rte_eth_devices[port];
4872         rte_eth_dev_info_get(port, &dev_info);
4873
4874         if (vf >= dev_info.max_vfs)
4875                 return -EINVAL;
4876
4877         if (on > 1)
4878                 return -EINVAL;
4879
4880         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
4881
4882         /* The PF has 128 queue pairs and in SRIOV configuration
4883          * those queues will be assigned to VF's, so RXDCTL
4884          * registers will be dealing with queues which will be
4885          * assigned to VF's.
4886          * Let's say we have SRIOV configured with 31 VF's then the
4887          * first 124 queues 0-123 will be allocated to VF's and only
4888          * the last 4 queues 123-127 will be assigned to the PF.
4889          */
4890
4891         queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
4892
4893         for (q = 0; q < queues_per_pool; q++)
4894                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
4895                                 q + vf * queues_per_pool, on);
4896         return 0;
4897 }
4898
4899 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4900 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4901 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4902 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4903 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4904         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4905         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4906
4907 static int
4908 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4909                         struct rte_eth_mirror_conf *mirror_conf,
4910                         uint8_t rule_id, uint8_t on)
4911 {
4912         uint32_t mr_ctl, vlvf;
4913         uint32_t mp_lsb = 0;
4914         uint32_t mv_msb = 0;
4915         uint32_t mv_lsb = 0;
4916         uint32_t mp_msb = 0;
4917         uint8_t i = 0;
4918         int reg_index = 0;
4919         uint64_t vlan_mask = 0;
4920
4921         const uint8_t pool_mask_offset = 32;
4922         const uint8_t vlan_mask_offset = 32;
4923         const uint8_t dst_pool_offset = 8;
4924         const uint8_t rule_mr_offset  = 4;
4925         const uint8_t mirror_rule_mask = 0x0F;
4926
4927         struct ixgbe_mirror_info *mr_info =
4928                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4929         struct ixgbe_hw *hw =
4930                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4931         uint8_t mirror_type = 0;
4932
4933         if (ixgbe_vmdq_mode_check(hw) < 0)
4934                 return -ENOTSUP;
4935
4936         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4937                 return -EINVAL;
4938
4939         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4940                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4941                         mirror_conf->rule_type);
4942                 return -EINVAL;
4943         }
4944
4945         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4946                 mirror_type |= IXGBE_MRCTL_VLME;
4947                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4948                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
4949                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4950                                 /* search vlan id related pool vlan filter index */
4951                                 reg_index = ixgbe_find_vlvf_slot(hw,
4952                                                  mirror_conf->vlan.vlan_id[i],
4953                                                  false);
4954                                 if (reg_index < 0)
4955                                         return -EINVAL;
4956                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4957                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4958                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4959                                       mirror_conf->vlan.vlan_id[i]))
4960                                         vlan_mask |= (1ULL << reg_index);
4961                                 else
4962                                         return -EINVAL;
4963                         }
4964                 }
4965
4966                 if (on) {
4967                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4968                         mv_msb = vlan_mask >> vlan_mask_offset;
4969
4970                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4971                                                 mirror_conf->vlan.vlan_mask;
4972                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4973                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4974                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4975                                                 mirror_conf->vlan.vlan_id[i];
4976                         }
4977                 } else {
4978                         mv_lsb = 0;
4979                         mv_msb = 0;
4980                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4981                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4982                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4983                 }
4984         }
4985
4986         /*
4987          * if enable pool mirror, write related pool mask register,if disable
4988          * pool mirror, clear PFMRVM register
4989          */
4990         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4991                 mirror_type |= IXGBE_MRCTL_VPME;
4992                 if (on) {
4993                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4994                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4995                         mr_info->mr_conf[rule_id].pool_mask =
4996                                         mirror_conf->pool_mask;
4997
4998                 } else {
4999                         mp_lsb = 0;
5000                         mp_msb = 0;
5001                         mr_info->mr_conf[rule_id].pool_mask = 0;
5002                 }
5003         }
5004         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5005                 mirror_type |= IXGBE_MRCTL_UPME;
5006         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5007                 mirror_type |= IXGBE_MRCTL_DPME;
5008
5009         /* read  mirror control register and recalculate it */
5010         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5011
5012         if (on) {
5013                 mr_ctl |= mirror_type;
5014                 mr_ctl &= mirror_rule_mask;
5015                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5016         } else
5017                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5018
5019         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5020         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5021
5022         /* write mirrror control  register */
5023         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5024
5025         /* write pool mirrror control  register */
5026         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5027                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5028                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5029                                 mp_msb);
5030         }
5031         /* write VLAN mirrror control  register */
5032         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5033                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5034                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5035                                 mv_msb);
5036         }
5037
5038         return 0;
5039 }
5040
5041 static int
5042 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5043 {
5044         int mr_ctl = 0;
5045         uint32_t lsb_val = 0;
5046         uint32_t msb_val = 0;
5047         const uint8_t rule_mr_offset = 4;
5048
5049         struct ixgbe_hw *hw =
5050                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5051         struct ixgbe_mirror_info *mr_info =
5052                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5053
5054         if (ixgbe_vmdq_mode_check(hw) < 0)
5055                 return -ENOTSUP;
5056
5057         memset(&mr_info->mr_conf[rule_id], 0,
5058                 sizeof(struct rte_eth_mirror_conf));
5059
5060         /* clear PFVMCTL register */
5061         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5062
5063         /* clear pool mask register */
5064         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5065         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5066
5067         /* clear vlan mask register */
5068         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5069         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5070
5071         return 0;
5072 }
5073
5074 static int
5075 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5076 {
5077         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5078         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5079         uint32_t mask;
5080         struct ixgbe_hw *hw =
5081                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5082
5083         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5084         mask |= (1 << IXGBE_MISC_VEC_ID);
5085         RTE_SET_USED(queue_id);
5086         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5087
5088         rte_intr_enable(intr_handle);
5089
5090         return 0;
5091 }
5092
5093 static int
5094 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5095 {
5096         uint32_t mask;
5097         struct ixgbe_hw *hw =
5098                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5099
5100         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5101         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5102         RTE_SET_USED(queue_id);
5103         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5104
5105         return 0;
5106 }
5107
5108 static int
5109 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5110 {
5111         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5112         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5113         uint32_t mask;
5114         struct ixgbe_hw *hw =
5115                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5116         struct ixgbe_interrupt *intr =
5117                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5118
5119         if (queue_id < 16) {
5120                 ixgbe_disable_intr(hw);
5121                 intr->mask |= (1 << queue_id);
5122                 ixgbe_enable_intr(dev);
5123         } else if (queue_id < 32) {
5124                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5125                 mask &= (1 << queue_id);
5126                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5127         } else if (queue_id < 64) {
5128                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5129                 mask &= (1 << (queue_id - 32));
5130                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5131         }
5132         rte_intr_enable(intr_handle);
5133
5134         return 0;
5135 }
5136
5137 static int
5138 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5139 {
5140         uint32_t mask;
5141         struct ixgbe_hw *hw =
5142                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5143         struct ixgbe_interrupt *intr =
5144                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5145
5146         if (queue_id < 16) {
5147                 ixgbe_disable_intr(hw);
5148                 intr->mask &= ~(1 << queue_id);
5149                 ixgbe_enable_intr(dev);
5150         } else if (queue_id < 32) {
5151                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5152                 mask &= ~(1 << queue_id);
5153                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5154         } else if (queue_id < 64) {
5155                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5156                 mask &= ~(1 << (queue_id - 32));
5157                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5158         }
5159
5160         return 0;
5161 }
5162
5163 static void
5164 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5165                      uint8_t queue, uint8_t msix_vector)
5166 {
5167         uint32_t tmp, idx;
5168
5169         if (direction == -1) {
5170                 /* other causes */
5171                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5172                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5173                 tmp &= ~0xFF;
5174                 tmp |= msix_vector;
5175                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5176         } else {
5177                 /* rx or tx cause */
5178                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5179                 idx = ((16 * (queue & 1)) + (8 * direction));
5180                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5181                 tmp &= ~(0xFF << idx);
5182                 tmp |= (msix_vector << idx);
5183                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5184         }
5185 }
5186
5187 /**
5188  * set the IVAR registers, mapping interrupt causes to vectors
5189  * @param hw
5190  *  pointer to ixgbe_hw struct
5191  * @direction
5192  *  0 for Rx, 1 for Tx, -1 for other causes
5193  * @queue
5194  *  queue to map the corresponding interrupt to
5195  * @msix_vector
5196  *  the vector to map to the corresponding queue
5197  */
5198 static void
5199 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5200                    uint8_t queue, uint8_t msix_vector)
5201 {
5202         uint32_t tmp, idx;
5203
5204         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5205         if (hw->mac.type == ixgbe_mac_82598EB) {
5206                 if (direction == -1)
5207                         direction = 0;
5208                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5209                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5210                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5211                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5212                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5213         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5214                         (hw->mac.type == ixgbe_mac_X540)) {
5215                 if (direction == -1) {
5216                         /* other causes */
5217                         idx = ((queue & 1) * 8);
5218                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5219                         tmp &= ~(0xFF << idx);
5220                         tmp |= (msix_vector << idx);
5221                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5222                 } else {
5223                         /* rx or tx causes */
5224                         idx = ((16 * (queue & 1)) + (8 * direction));
5225                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5226                         tmp &= ~(0xFF << idx);
5227                         tmp |= (msix_vector << idx);
5228                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5229                 }
5230         }
5231 }
5232
5233 static void
5234 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5235 {
5236         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5237         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5238         struct ixgbe_hw *hw =
5239                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5240         uint32_t q_idx;
5241         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5242
5243         /* Configure VF other cause ivar */
5244         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5245
5246         /* won't configure msix register if no mapping is done
5247          * between intr vector and event fd.
5248          */
5249         if (!rte_intr_dp_is_en(intr_handle))
5250                 return;
5251
5252         /* Configure all RX queues of VF */
5253         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5254                 /* Force all queue use vector 0,
5255                  * as IXGBE_VF_MAXMSIVECOTR = 1
5256                  */
5257                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5258                 intr_handle->intr_vec[q_idx] = vector_idx;
5259         }
5260 }
5261
5262 /**
5263  * Sets up the hardware to properly generate MSI-X interrupts
5264  * @hw
5265  *  board private structure
5266  */
5267 static void
5268 ixgbe_configure_msix(struct rte_eth_dev *dev)
5269 {
5270         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5271         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5272         struct ixgbe_hw *hw =
5273                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5274         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5275         uint32_t vec = IXGBE_MISC_VEC_ID;
5276         uint32_t mask;
5277         uint32_t gpie;
5278
5279         /* won't configure msix register if no mapping is done
5280          * between intr vector and event fd
5281          */
5282         if (!rte_intr_dp_is_en(intr_handle))
5283                 return;
5284
5285         if (rte_intr_allow_others(intr_handle))
5286                 vec = base = IXGBE_RX_VEC_START;
5287
5288         /* setup GPIE for MSI-x mode */
5289         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5290         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5291                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5292         /* auto clearing and auto setting corresponding bits in EIMS
5293          * when MSI-X interrupt is triggered
5294          */
5295         if (hw->mac.type == ixgbe_mac_82598EB) {
5296                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5297         } else {
5298                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5299                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5300         }
5301         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5302
5303         /* Populate the IVAR table and set the ITR values to the
5304          * corresponding register.
5305          */
5306         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5307              queue_id++) {
5308                 /* by default, 1:1 mapping */
5309                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5310                 intr_handle->intr_vec[queue_id] = vec;
5311                 if (vec < base + intr_handle->nb_efd - 1)
5312                         vec++;
5313         }
5314
5315         switch (hw->mac.type) {
5316         case ixgbe_mac_82598EB:
5317                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5318                                    IXGBE_MISC_VEC_ID);
5319                 break;
5320         case ixgbe_mac_82599EB:
5321         case ixgbe_mac_X540:
5322                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5323                 break;
5324         default:
5325                 break;
5326         }
5327         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5328                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5329
5330         /* set up to autoclear timer, and the vectors */
5331         mask = IXGBE_EIMS_ENABLE_MASK;
5332         mask &= ~(IXGBE_EIMS_OTHER |
5333                   IXGBE_EIMS_MAILBOX |
5334                   IXGBE_EIMS_LSC);
5335
5336         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5337 }
5338
5339 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5340         uint16_t queue_idx, uint16_t tx_rate)
5341 {
5342         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5343         uint32_t rf_dec, rf_int;
5344         uint32_t bcnrc_val;
5345         uint16_t link_speed = dev->data->dev_link.link_speed;
5346
5347         if (queue_idx >= hw->mac.max_tx_queues)
5348                 return -EINVAL;
5349
5350         if (tx_rate != 0) {
5351                 /* Calculate the rate factor values to set */
5352                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5353                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5354                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5355
5356                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5357                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5358                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5359                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5360         } else {
5361                 bcnrc_val = 0;
5362         }
5363
5364         /*
5365          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5366          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5367          * set as 0x4.
5368          */
5369         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5370                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5371                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5372                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5373                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5374         else
5375                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5376                         IXGBE_MMW_SIZE_DEFAULT);
5377
5378         /* Set RTTBCNRC of queue X */
5379         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5380         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5381         IXGBE_WRITE_FLUSH(hw);
5382
5383         return 0;
5384 }
5385
5386 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
5387         uint16_t tx_rate, uint64_t q_msk)
5388 {
5389         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5390         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5391         struct ixgbe_vf_info *vfinfo =
5392                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5393         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5394         uint32_t queue_stride =
5395                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5396         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
5397         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
5398         uint16_t total_rate = 0;
5399
5400         if (queue_end >= hw->mac.max_tx_queues)
5401                 return -EINVAL;
5402
5403         if (vfinfo != NULL) {
5404                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5405                         if (vf_idx == vf)
5406                                 continue;
5407                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5408                                 idx++)
5409                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5410                 }
5411         } else
5412                 return -EINVAL;
5413
5414         /* Store tx_rate for this vf. */
5415         for (idx = 0; idx < nb_q_per_pool; idx++) {
5416                 if (((uint64_t)0x1 << idx) & q_msk) {
5417                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5418                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5419                         total_rate += tx_rate;
5420                 }
5421         }
5422
5423         if (total_rate > dev->data->dev_link.link_speed) {
5424                 /*
5425                  * Reset stored TX rate of the VF if it causes exceed
5426                  * link speed.
5427                  */
5428                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5429                 return -EINVAL;
5430         }
5431
5432         /* Set RTTBCNRC of each queue/pool for vf X  */
5433         for (; queue_idx <= queue_end; queue_idx++) {
5434                 if (0x1 & q_msk)
5435                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5436                 q_msk = q_msk >> 1;
5437         }
5438
5439         return 0;
5440 }
5441
5442 static void
5443 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5444                      __attribute__((unused)) uint32_t index,
5445                      __attribute__((unused)) uint32_t pool)
5446 {
5447         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5448         int diag;
5449
5450         /*
5451          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5452          * operation. Trap this case to avoid exhausting the [very limited]
5453          * set of PF resources used to store VF MAC addresses.
5454          */
5455         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5456                 return;
5457         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5458         if (diag == 0)
5459                 return;
5460         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5461 }
5462
5463 static void
5464 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5465 {
5466         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5467         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5468         struct ether_addr *mac_addr;
5469         uint32_t i;
5470         int diag;
5471
5472         /*
5473          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5474          * not support the deletion of a given MAC address.
5475          * Instead, it imposes to delete all MAC addresses, then to add again
5476          * all MAC addresses with the exception of the one to be deleted.
5477          */
5478         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5479
5480         /*
5481          * Add again all MAC addresses, with the exception of the deleted one
5482          * and of the permanent MAC address.
5483          */
5484         for (i = 0, mac_addr = dev->data->mac_addrs;
5485              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5486                 /* Skip the deleted MAC address */
5487                 if (i == index)
5488                         continue;
5489                 /* Skip NULL MAC addresses */
5490                 if (is_zero_ether_addr(mac_addr))
5491                         continue;
5492                 /* Skip the permanent MAC address */
5493                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5494                         continue;
5495                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5496                 if (diag != 0)
5497                         PMD_DRV_LOG(ERR,
5498                                     "Adding again MAC address "
5499                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5500                                     "diag=%d",
5501                                     mac_addr->addr_bytes[0],
5502                                     mac_addr->addr_bytes[1],
5503                                     mac_addr->addr_bytes[2],
5504                                     mac_addr->addr_bytes[3],
5505                                     mac_addr->addr_bytes[4],
5506                                     mac_addr->addr_bytes[5],
5507                                     diag);
5508         }
5509 }
5510
5511 static void
5512 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5513 {
5514         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5515
5516         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5517 }
5518
5519 #define MAC_TYPE_FILTER_SUP(type)    do {\
5520         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5521                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5522                 (type) != ixgbe_mac_X550EM_a)\
5523                 return -ENOTSUP;\
5524 } while (0)
5525
5526 static int
5527 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5528                         struct rte_eth_syn_filter *filter,
5529                         bool add)
5530 {
5531         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5532         uint32_t synqf;
5533
5534         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5535                 return -EINVAL;
5536
5537         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5538
5539         if (add) {
5540                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5541                         return -EINVAL;
5542                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5543                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5544
5545                 if (filter->hig_pri)
5546                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5547                 else
5548                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5549         } else {
5550                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5551                         return -ENOENT;
5552                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5553         }
5554         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5555         IXGBE_WRITE_FLUSH(hw);
5556         return 0;
5557 }
5558
5559 static int
5560 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5561                         struct rte_eth_syn_filter *filter)
5562 {
5563         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5564         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5565
5566         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5567                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5568                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5569                 return 0;
5570         }
5571         return -ENOENT;
5572 }
5573
5574 static int
5575 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5576                         enum rte_filter_op filter_op,
5577                         void *arg)
5578 {
5579         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5580         int ret;
5581
5582         MAC_TYPE_FILTER_SUP(hw->mac.type);
5583
5584         if (filter_op == RTE_ETH_FILTER_NOP)
5585                 return 0;
5586
5587         if (arg == NULL) {
5588                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5589                             filter_op);
5590                 return -EINVAL;
5591         }
5592
5593         switch (filter_op) {
5594         case RTE_ETH_FILTER_ADD:
5595                 ret = ixgbe_syn_filter_set(dev,
5596                                 (struct rte_eth_syn_filter *)arg,
5597                                 TRUE);
5598                 break;
5599         case RTE_ETH_FILTER_DELETE:
5600                 ret = ixgbe_syn_filter_set(dev,
5601                                 (struct rte_eth_syn_filter *)arg,
5602                                 FALSE);
5603                 break;
5604         case RTE_ETH_FILTER_GET:
5605                 ret = ixgbe_syn_filter_get(dev,
5606                                 (struct rte_eth_syn_filter *)arg);
5607                 break;
5608         default:
5609                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5610                 ret = -EINVAL;
5611                 break;
5612         }
5613
5614         return ret;
5615 }
5616
5617
5618 static inline enum ixgbe_5tuple_protocol
5619 convert_protocol_type(uint8_t protocol_value)
5620 {
5621         if (protocol_value == IPPROTO_TCP)
5622                 return IXGBE_FILTER_PROTOCOL_TCP;
5623         else if (protocol_value == IPPROTO_UDP)
5624                 return IXGBE_FILTER_PROTOCOL_UDP;
5625         else if (protocol_value == IPPROTO_SCTP)
5626                 return IXGBE_FILTER_PROTOCOL_SCTP;
5627         else
5628                 return IXGBE_FILTER_PROTOCOL_NONE;
5629 }
5630
5631 /*
5632  * add a 5tuple filter
5633  *
5634  * @param
5635  * dev: Pointer to struct rte_eth_dev.
5636  * index: the index the filter allocates.
5637  * filter: ponter to the filter that will be added.
5638  * rx_queue: the queue id the filter assigned to.
5639  *
5640  * @return
5641  *    - On success, zero.
5642  *    - On failure, a negative value.
5643  */
5644 static int
5645 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5646                         struct ixgbe_5tuple_filter *filter)
5647 {
5648         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5649         struct ixgbe_filter_info *filter_info =
5650                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5651         int i, idx, shift;
5652         uint32_t ftqf, sdpqf;
5653         uint32_t l34timir = 0;
5654         uint8_t mask = 0xff;
5655
5656         /*
5657          * look for an unused 5tuple filter index,
5658          * and insert the filter to list.
5659          */
5660         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5661                 idx = i / (sizeof(uint32_t) * NBBY);
5662                 shift = i % (sizeof(uint32_t) * NBBY);
5663                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5664                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5665                         filter->index = i;
5666                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5667                                           filter,
5668                                           entries);
5669                         break;
5670                 }
5671         }
5672         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5673                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5674                 return -ENOSYS;
5675         }
5676
5677         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5678                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5679         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5680
5681         ftqf = (uint32_t)(filter->filter_info.proto &
5682                 IXGBE_FTQF_PROTOCOL_MASK);
5683         ftqf |= (uint32_t)((filter->filter_info.priority &
5684                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5685         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5686                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5687         if (filter->filter_info.dst_ip_mask == 0)
5688                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5689         if (filter->filter_info.src_port_mask == 0)
5690                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5691         if (filter->filter_info.dst_port_mask == 0)
5692                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5693         if (filter->filter_info.proto_mask == 0)
5694                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5695         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5696         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5697         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5698
5699         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5700         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5701         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5702         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5703
5704         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5705         l34timir |= (uint32_t)(filter->queue <<
5706                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5707         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5708         return 0;
5709 }
5710
5711 /*
5712  * remove a 5tuple filter
5713  *
5714  * @param
5715  * dev: Pointer to struct rte_eth_dev.
5716  * filter: the pointer of the filter will be removed.
5717  */
5718 static void
5719 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5720                         struct ixgbe_5tuple_filter *filter)
5721 {
5722         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5723         struct ixgbe_filter_info *filter_info =
5724                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5725         uint16_t index = filter->index;
5726
5727         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5728                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5729         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5730         rte_free(filter);
5731
5732         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5733         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5734         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5735         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5736         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5737 }
5738
5739 static int
5740 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5741 {
5742         struct ixgbe_hw *hw;
5743         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5744
5745         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5746
5747         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5748                 return -EINVAL;
5749
5750         /* refuse mtu that requires the support of scattered packets when this
5751          * feature has not been enabled before.
5752          */
5753         if (!dev->data->scattered_rx &&
5754             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5755              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5756                 return -EINVAL;
5757
5758         /*
5759          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5760          * request of the version 2.0 of the mailbox API.
5761          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5762          * of the mailbox API.
5763          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5764          * prior to 3.11.33 which contains the following change:
5765          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5766          */
5767         ixgbevf_rlpml_set_vf(hw, max_frame);
5768
5769         /* update max frame size */
5770         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5771         return 0;
5772 }
5773
5774 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5775         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5776                 return -ENOTSUP;\
5777 } while (0)
5778
5779 static inline struct ixgbe_5tuple_filter *
5780 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5781                         struct ixgbe_5tuple_filter_info *key)
5782 {
5783         struct ixgbe_5tuple_filter *it;
5784
5785         TAILQ_FOREACH(it, filter_list, entries) {
5786                 if (memcmp(key, &it->filter_info,
5787                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5788                         return it;
5789                 }
5790         }
5791         return NULL;
5792 }
5793
5794 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5795 static inline int
5796 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5797                         struct ixgbe_5tuple_filter_info *filter_info)
5798 {
5799         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5800                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5801                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5802                 return -EINVAL;
5803
5804         switch (filter->dst_ip_mask) {
5805         case UINT32_MAX:
5806                 filter_info->dst_ip_mask = 0;
5807                 filter_info->dst_ip = filter->dst_ip;
5808                 break;
5809         case 0:
5810                 filter_info->dst_ip_mask = 1;
5811                 break;
5812         default:
5813                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5814                 return -EINVAL;
5815         }
5816
5817         switch (filter->src_ip_mask) {
5818         case UINT32_MAX:
5819                 filter_info->src_ip_mask = 0;
5820                 filter_info->src_ip = filter->src_ip;
5821                 break;
5822         case 0:
5823                 filter_info->src_ip_mask = 1;
5824                 break;
5825         default:
5826                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5827                 return -EINVAL;
5828         }
5829
5830         switch (filter->dst_port_mask) {
5831         case UINT16_MAX:
5832                 filter_info->dst_port_mask = 0;
5833                 filter_info->dst_port = filter->dst_port;
5834                 break;
5835         case 0:
5836                 filter_info->dst_port_mask = 1;
5837                 break;
5838         default:
5839                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5840                 return -EINVAL;
5841         }
5842
5843         switch (filter->src_port_mask) {
5844         case UINT16_MAX:
5845                 filter_info->src_port_mask = 0;
5846                 filter_info->src_port = filter->src_port;
5847                 break;
5848         case 0:
5849                 filter_info->src_port_mask = 1;
5850                 break;
5851         default:
5852                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5853                 return -EINVAL;
5854         }
5855
5856         switch (filter->proto_mask) {
5857         case UINT8_MAX:
5858                 filter_info->proto_mask = 0;
5859                 filter_info->proto =
5860                         convert_protocol_type(filter->proto);
5861                 break;
5862         case 0:
5863                 filter_info->proto_mask = 1;
5864                 break;
5865         default:
5866                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5867                 return -EINVAL;
5868         }
5869
5870         filter_info->priority = (uint8_t)filter->priority;
5871         return 0;
5872 }
5873
5874 /*
5875  * add or delete a ntuple filter
5876  *
5877  * @param
5878  * dev: Pointer to struct rte_eth_dev.
5879  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5880  * add: if true, add filter, if false, remove filter
5881  *
5882  * @return
5883  *    - On success, zero.
5884  *    - On failure, a negative value.
5885  */
5886 static int
5887 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5888                         struct rte_eth_ntuple_filter *ntuple_filter,
5889                         bool add)
5890 {
5891         struct ixgbe_filter_info *filter_info =
5892                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5893         struct ixgbe_5tuple_filter_info filter_5tuple;
5894         struct ixgbe_5tuple_filter *filter;
5895         int ret;
5896
5897         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5898                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5899                 return -EINVAL;
5900         }
5901
5902         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5903         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5904         if (ret < 0)
5905                 return ret;
5906
5907         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5908                                          &filter_5tuple);
5909         if (filter != NULL && add) {
5910                 PMD_DRV_LOG(ERR, "filter exists.");
5911                 return -EEXIST;
5912         }
5913         if (filter == NULL && !add) {
5914                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5915                 return -ENOENT;
5916         }
5917
5918         if (add) {
5919                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5920                                 sizeof(struct ixgbe_5tuple_filter), 0);
5921                 if (filter == NULL)
5922                         return -ENOMEM;
5923                 (void)rte_memcpy(&filter->filter_info,
5924                                  &filter_5tuple,
5925                                  sizeof(struct ixgbe_5tuple_filter_info));
5926                 filter->queue = ntuple_filter->queue;
5927                 ret = ixgbe_add_5tuple_filter(dev, filter);
5928                 if (ret < 0) {
5929                         rte_free(filter);
5930                         return ret;
5931                 }
5932         } else
5933                 ixgbe_remove_5tuple_filter(dev, filter);
5934
5935         return 0;
5936 }
5937
5938 /*
5939  * get a ntuple filter
5940  *
5941  * @param
5942  * dev: Pointer to struct rte_eth_dev.
5943  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5944  *
5945  * @return
5946  *    - On success, zero.
5947  *    - On failure, a negative value.
5948  */
5949 static int
5950 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5951                         struct rte_eth_ntuple_filter *ntuple_filter)
5952 {
5953         struct ixgbe_filter_info *filter_info =
5954                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5955         struct ixgbe_5tuple_filter_info filter_5tuple;
5956         struct ixgbe_5tuple_filter *filter;
5957         int ret;
5958
5959         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5960                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5961                 return -EINVAL;
5962         }
5963
5964         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5965         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5966         if (ret < 0)
5967                 return ret;
5968
5969         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5970                                          &filter_5tuple);
5971         if (filter == NULL) {
5972                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5973                 return -ENOENT;
5974         }
5975         ntuple_filter->queue = filter->queue;
5976         return 0;
5977 }
5978
5979 /*
5980  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5981  * @dev: pointer to rte_eth_dev structure
5982  * @filter_op:operation will be taken.
5983  * @arg: a pointer to specific structure corresponding to the filter_op
5984  *
5985  * @return
5986  *    - On success, zero.
5987  *    - On failure, a negative value.
5988  */
5989 static int
5990 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5991                                 enum rte_filter_op filter_op,
5992                                 void *arg)
5993 {
5994         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5995         int ret;
5996
5997         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5998
5999         if (filter_op == RTE_ETH_FILTER_NOP)
6000                 return 0;
6001
6002         if (arg == NULL) {
6003                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6004                             filter_op);
6005                 return -EINVAL;
6006         }
6007
6008         switch (filter_op) {
6009         case RTE_ETH_FILTER_ADD:
6010                 ret = ixgbe_add_del_ntuple_filter(dev,
6011                         (struct rte_eth_ntuple_filter *)arg,
6012                         TRUE);
6013                 break;
6014         case RTE_ETH_FILTER_DELETE:
6015                 ret = ixgbe_add_del_ntuple_filter(dev,
6016                         (struct rte_eth_ntuple_filter *)arg,
6017                         FALSE);
6018                 break;
6019         case RTE_ETH_FILTER_GET:
6020                 ret = ixgbe_get_ntuple_filter(dev,
6021                         (struct rte_eth_ntuple_filter *)arg);
6022                 break;
6023         default:
6024                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6025                 ret = -EINVAL;
6026                 break;
6027         }
6028         return ret;
6029 }
6030
6031 static inline int
6032 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
6033                         uint16_t ethertype)
6034 {
6035         int i;
6036
6037         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6038                 if (filter_info->ethertype_filters[i] == ethertype &&
6039                     (filter_info->ethertype_mask & (1 << i)))
6040                         return i;
6041         }
6042         return -1;
6043 }
6044
6045 static inline int
6046 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
6047                         uint16_t ethertype)
6048 {
6049         int i;
6050
6051         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6052                 if (!(filter_info->ethertype_mask & (1 << i))) {
6053                         filter_info->ethertype_mask |= 1 << i;
6054                         filter_info->ethertype_filters[i] = ethertype;
6055                         return i;
6056                 }
6057         }
6058         return -1;
6059 }
6060
6061 static inline int
6062 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
6063                         uint8_t idx)
6064 {
6065         if (idx >= IXGBE_MAX_ETQF_FILTERS)
6066                 return -1;
6067         filter_info->ethertype_mask &= ~(1 << idx);
6068         filter_info->ethertype_filters[idx] = 0;
6069         return idx;
6070 }
6071
6072 static int
6073 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6074                         struct rte_eth_ethertype_filter *filter,
6075                         bool add)
6076 {
6077         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6078         struct ixgbe_filter_info *filter_info =
6079                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6080         uint32_t etqf = 0;
6081         uint32_t etqs = 0;
6082         int ret;
6083
6084         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6085                 return -EINVAL;
6086
6087         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6088                 filter->ether_type == ETHER_TYPE_IPv6) {
6089                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6090                         " ethertype filter.", filter->ether_type);
6091                 return -EINVAL;
6092         }
6093
6094         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6095                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6096                 return -EINVAL;
6097         }
6098         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6099                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6100                 return -EINVAL;
6101         }
6102
6103         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6104         if (ret >= 0 && add) {
6105                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6106                             filter->ether_type);
6107                 return -EEXIST;
6108         }
6109         if (ret < 0 && !add) {
6110                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6111                             filter->ether_type);
6112                 return -ENOENT;
6113         }
6114
6115         if (add) {
6116                 ret = ixgbe_ethertype_filter_insert(filter_info,
6117                         filter->ether_type);
6118                 if (ret < 0) {
6119                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6120                         return -ENOSYS;
6121                 }
6122                 etqf = IXGBE_ETQF_FILTER_EN;
6123                 etqf |= (uint32_t)filter->ether_type;
6124                 etqs |= (uint32_t)((filter->queue <<
6125                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6126                                     IXGBE_ETQS_RX_QUEUE);
6127                 etqs |= IXGBE_ETQS_QUEUE_EN;
6128         } else {
6129                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6130                 if (ret < 0)
6131                         return -ENOSYS;
6132         }
6133         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6134         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6135         IXGBE_WRITE_FLUSH(hw);
6136
6137         return 0;
6138 }
6139
6140 static int
6141 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6142                         struct rte_eth_ethertype_filter *filter)
6143 {
6144         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6145         struct ixgbe_filter_info *filter_info =
6146                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6147         uint32_t etqf, etqs;
6148         int ret;
6149
6150         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6151         if (ret < 0) {
6152                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6153                             filter->ether_type);
6154                 return -ENOENT;
6155         }
6156
6157         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6158         if (etqf & IXGBE_ETQF_FILTER_EN) {
6159                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6160                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6161                 filter->flags = 0;
6162                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6163                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6164                 return 0;
6165         }
6166         return -ENOENT;
6167 }
6168
6169 /*
6170  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6171  * @dev: pointer to rte_eth_dev structure
6172  * @filter_op:operation will be taken.
6173  * @arg: a pointer to specific structure corresponding to the filter_op
6174  */
6175 static int
6176 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6177                                 enum rte_filter_op filter_op,
6178                                 void *arg)
6179 {
6180         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6181         int ret;
6182
6183         MAC_TYPE_FILTER_SUP(hw->mac.type);
6184
6185         if (filter_op == RTE_ETH_FILTER_NOP)
6186                 return 0;
6187
6188         if (arg == NULL) {
6189                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6190                             filter_op);
6191                 return -EINVAL;
6192         }
6193
6194         switch (filter_op) {
6195         case RTE_ETH_FILTER_ADD:
6196                 ret = ixgbe_add_del_ethertype_filter(dev,
6197                         (struct rte_eth_ethertype_filter *)arg,
6198                         TRUE);
6199                 break;
6200         case RTE_ETH_FILTER_DELETE:
6201                 ret = ixgbe_add_del_ethertype_filter(dev,
6202                         (struct rte_eth_ethertype_filter *)arg,
6203                         FALSE);
6204                 break;
6205         case RTE_ETH_FILTER_GET:
6206                 ret = ixgbe_get_ethertype_filter(dev,
6207                         (struct rte_eth_ethertype_filter *)arg);
6208                 break;
6209         default:
6210                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6211                 ret = -EINVAL;
6212                 break;
6213         }
6214         return ret;
6215 }
6216
6217 static int
6218 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6219                      enum rte_filter_type filter_type,
6220                      enum rte_filter_op filter_op,
6221                      void *arg)
6222 {
6223         int ret = -EINVAL;
6224
6225         switch (filter_type) {
6226         case RTE_ETH_FILTER_NTUPLE:
6227                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6228                 break;
6229         case RTE_ETH_FILTER_ETHERTYPE:
6230                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6231                 break;
6232         case RTE_ETH_FILTER_SYN:
6233                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6234                 break;
6235         case RTE_ETH_FILTER_FDIR:
6236                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6237                 break;
6238         case RTE_ETH_FILTER_L2_TUNNEL:
6239                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6240                 break;
6241         default:
6242                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6243                                                         filter_type);
6244                 break;
6245         }
6246
6247         return ret;
6248 }
6249
6250 static u8 *
6251 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6252                         u8 **mc_addr_ptr, u32 *vmdq)
6253 {
6254         u8 *mc_addr;
6255
6256         *vmdq = 0;
6257         mc_addr = *mc_addr_ptr;
6258         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6259         return mc_addr;
6260 }
6261
6262 static int
6263 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6264                           struct ether_addr *mc_addr_set,
6265                           uint32_t nb_mc_addr)
6266 {
6267         struct ixgbe_hw *hw;
6268         u8 *mc_addr_list;
6269
6270         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6271         mc_addr_list = (u8 *)mc_addr_set;
6272         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6273                                          ixgbe_dev_addr_list_itr, TRUE);
6274 }
6275
6276 static uint64_t
6277 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6278 {
6279         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6280         uint64_t systime_cycles;
6281
6282         switch (hw->mac.type) {
6283         case ixgbe_mac_X550:
6284         case ixgbe_mac_X550EM_x:
6285         case ixgbe_mac_X550EM_a:
6286                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6287                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6288                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6289                                 * NSEC_PER_SEC;
6290                 break;
6291         default:
6292                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6293                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6294                                 << 32;
6295         }
6296
6297         return systime_cycles;
6298 }
6299
6300 static uint64_t
6301 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6302 {
6303         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6304         uint64_t rx_tstamp_cycles;
6305
6306         switch (hw->mac.type) {
6307         case ixgbe_mac_X550:
6308         case ixgbe_mac_X550EM_x:
6309         case ixgbe_mac_X550EM_a:
6310                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6311                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6312                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6313                                 * NSEC_PER_SEC;
6314                 break;
6315         default:
6316                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6317                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6318                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6319                                 << 32;
6320         }
6321
6322         return rx_tstamp_cycles;
6323 }
6324
6325 static uint64_t
6326 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6327 {
6328         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6329         uint64_t tx_tstamp_cycles;
6330
6331         switch (hw->mac.type) {
6332         case ixgbe_mac_X550:
6333         case ixgbe_mac_X550EM_x:
6334         case ixgbe_mac_X550EM_a:
6335                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6336                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6337                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6338                                 * NSEC_PER_SEC;
6339                 break;
6340         default:
6341                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6342                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6343                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6344                                 << 32;
6345         }
6346
6347         return tx_tstamp_cycles;
6348 }
6349
6350 static void
6351 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6352 {
6353         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6354         struct ixgbe_adapter *adapter =
6355                 (struct ixgbe_adapter *)dev->data->dev_private;
6356         struct rte_eth_link link;
6357         uint32_t incval = 0;
6358         uint32_t shift = 0;
6359
6360         /* Get current link speed. */
6361         memset(&link, 0, sizeof(link));
6362         ixgbe_dev_link_update(dev, 1);
6363         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6364
6365         switch (link.link_speed) {
6366         case ETH_SPEED_NUM_100M:
6367                 incval = IXGBE_INCVAL_100;
6368                 shift = IXGBE_INCVAL_SHIFT_100;
6369                 break;
6370         case ETH_SPEED_NUM_1G:
6371                 incval = IXGBE_INCVAL_1GB;
6372                 shift = IXGBE_INCVAL_SHIFT_1GB;
6373                 break;
6374         case ETH_SPEED_NUM_10G:
6375         default:
6376                 incval = IXGBE_INCVAL_10GB;
6377                 shift = IXGBE_INCVAL_SHIFT_10GB;
6378                 break;
6379         }
6380
6381         switch (hw->mac.type) {
6382         case ixgbe_mac_X550:
6383         case ixgbe_mac_X550EM_x:
6384         case ixgbe_mac_X550EM_a:
6385                 /* Independent of link speed. */
6386                 incval = 1;
6387                 /* Cycles read will be interpreted as ns. */
6388                 shift = 0;
6389                 /* Fall-through */
6390         case ixgbe_mac_X540:
6391                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6392                 break;
6393         case ixgbe_mac_82599EB:
6394                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6395                 shift -= IXGBE_INCVAL_SHIFT_82599;
6396                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6397                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6398                 break;
6399         default:
6400                 /* Not supported. */
6401                 return;
6402         }
6403
6404         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6405         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6406         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6407
6408         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6409         adapter->systime_tc.cc_shift = shift;
6410         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6411
6412         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6413         adapter->rx_tstamp_tc.cc_shift = shift;
6414         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6415
6416         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6417         adapter->tx_tstamp_tc.cc_shift = shift;
6418         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6419 }
6420
6421 static int
6422 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6423 {
6424         struct ixgbe_adapter *adapter =
6425                         (struct ixgbe_adapter *)dev->data->dev_private;
6426
6427         adapter->systime_tc.nsec += delta;
6428         adapter->rx_tstamp_tc.nsec += delta;
6429         adapter->tx_tstamp_tc.nsec += delta;
6430
6431         return 0;
6432 }
6433
6434 static int
6435 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6436 {
6437         uint64_t ns;
6438         struct ixgbe_adapter *adapter =
6439                         (struct ixgbe_adapter *)dev->data->dev_private;
6440
6441         ns = rte_timespec_to_ns(ts);
6442         /* Set the timecounters to a new value. */
6443         adapter->systime_tc.nsec = ns;
6444         adapter->rx_tstamp_tc.nsec = ns;
6445         adapter->tx_tstamp_tc.nsec = ns;
6446
6447         return 0;
6448 }
6449
6450 static int
6451 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6452 {
6453         uint64_t ns, systime_cycles;
6454         struct ixgbe_adapter *adapter =
6455                         (struct ixgbe_adapter *)dev->data->dev_private;
6456
6457         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6458         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6459         *ts = rte_ns_to_timespec(ns);
6460
6461         return 0;
6462 }
6463
6464 static int
6465 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6466 {
6467         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6468         uint32_t tsync_ctl;
6469         uint32_t tsauxc;
6470
6471         /* Stop the timesync system time. */
6472         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6473         /* Reset the timesync system time value. */
6474         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6475         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6476
6477         /* Enable system time for platforms where it isn't on by default. */
6478         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6479         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6480         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6481
6482         ixgbe_start_timecounters(dev);
6483
6484         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6485         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6486                         (ETHER_TYPE_1588 |
6487                          IXGBE_ETQF_FILTER_EN |
6488                          IXGBE_ETQF_1588));
6489
6490         /* Enable timestamping of received PTP packets. */
6491         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6492         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6493         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6494
6495         /* Enable timestamping of transmitted PTP packets. */
6496         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6497         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6498         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6499
6500         IXGBE_WRITE_FLUSH(hw);
6501
6502         return 0;
6503 }
6504
6505 static int
6506 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6507 {
6508         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6509         uint32_t tsync_ctl;
6510
6511         /* Disable timestamping of transmitted PTP packets. */
6512         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6513         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6514         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6515
6516         /* Disable timestamping of received PTP packets. */
6517         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6518         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6519         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6520
6521         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6522         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6523
6524         /* Stop incrementating the System Time registers. */
6525         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6526
6527         return 0;
6528 }
6529
6530 static int
6531 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6532                                  struct timespec *timestamp,
6533                                  uint32_t flags __rte_unused)
6534 {
6535         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6536         struct ixgbe_adapter *adapter =
6537                 (struct ixgbe_adapter *)dev->data->dev_private;
6538         uint32_t tsync_rxctl;
6539         uint64_t rx_tstamp_cycles;
6540         uint64_t ns;
6541
6542         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6543         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6544                 return -EINVAL;
6545
6546         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6547         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6548         *timestamp = rte_ns_to_timespec(ns);
6549
6550         return  0;
6551 }
6552
6553 static int
6554 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6555                                  struct timespec *timestamp)
6556 {
6557         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6558         struct ixgbe_adapter *adapter =
6559                 (struct ixgbe_adapter *)dev->data->dev_private;
6560         uint32_t tsync_txctl;
6561         uint64_t tx_tstamp_cycles;
6562         uint64_t ns;
6563
6564         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6565         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6566                 return -EINVAL;
6567
6568         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6569         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6570         *timestamp = rte_ns_to_timespec(ns);
6571
6572         return 0;
6573 }
6574
6575 static int
6576 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6577 {
6578         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6579         int count = 0;
6580         int g_ind = 0;
6581         const struct reg_info *reg_group;
6582         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6583                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6584
6585         while ((reg_group = reg_set[g_ind++]))
6586                 count += ixgbe_regs_group_count(reg_group);
6587
6588         return count;
6589 }
6590
6591 static int
6592 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6593 {
6594         int count = 0;
6595         int g_ind = 0;
6596         const struct reg_info *reg_group;
6597
6598         while ((reg_group = ixgbevf_regs[g_ind++]))
6599                 count += ixgbe_regs_group_count(reg_group);
6600
6601         return count;
6602 }
6603
6604 static int
6605 ixgbe_get_regs(struct rte_eth_dev *dev,
6606               struct rte_dev_reg_info *regs)
6607 {
6608         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6609         uint32_t *data = regs->data;
6610         int g_ind = 0;
6611         int count = 0;
6612         const struct reg_info *reg_group;
6613         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6614                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6615
6616         if (data == NULL) {
6617                 regs->length = ixgbe_get_reg_length(dev);
6618                 regs->width = sizeof(uint32_t);
6619                 return 0;
6620         }
6621
6622         /* Support only full register dump */
6623         if ((regs->length == 0) ||
6624             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6625                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6626                         hw->device_id;
6627                 while ((reg_group = reg_set[g_ind++]))
6628                         count += ixgbe_read_regs_group(dev, &data[count],
6629                                 reg_group);
6630                 return 0;
6631         }
6632
6633         return -ENOTSUP;
6634 }
6635
6636 static int
6637 ixgbevf_get_regs(struct rte_eth_dev *dev,
6638                 struct rte_dev_reg_info *regs)
6639 {
6640         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6641         uint32_t *data = regs->data;
6642         int g_ind = 0;
6643         int count = 0;
6644         const struct reg_info *reg_group;
6645
6646         if (data == NULL) {
6647                 regs->length = ixgbevf_get_reg_length(dev);
6648                 regs->width = sizeof(uint32_t);
6649                 return 0;
6650         }
6651
6652         /* Support only full register dump */
6653         if ((regs->length == 0) ||
6654             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6655                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6656                         hw->device_id;
6657                 while ((reg_group = ixgbevf_regs[g_ind++]))
6658                         count += ixgbe_read_regs_group(dev, &data[count],
6659                                                       reg_group);
6660                 return 0;
6661         }
6662
6663         return -ENOTSUP;
6664 }
6665
6666 static int
6667 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6668 {
6669         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6670
6671         /* Return unit is byte count */
6672         return hw->eeprom.word_size * 2;
6673 }
6674
6675 static int
6676 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6677                 struct rte_dev_eeprom_info *in_eeprom)
6678 {
6679         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6680         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6681         uint16_t *data = in_eeprom->data;
6682         int first, length;
6683
6684         first = in_eeprom->offset >> 1;
6685         length = in_eeprom->length >> 1;
6686         if ((first > hw->eeprom.word_size) ||
6687             ((first + length) > hw->eeprom.word_size))
6688                 return -EINVAL;
6689
6690         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6691
6692         return eeprom->ops.read_buffer(hw, first, length, data);
6693 }
6694
6695 static int
6696 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6697                 struct rte_dev_eeprom_info *in_eeprom)
6698 {
6699         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6700         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6701         uint16_t *data = in_eeprom->data;
6702         int first, length;
6703
6704         first = in_eeprom->offset >> 1;
6705         length = in_eeprom->length >> 1;
6706         if ((first > hw->eeprom.word_size) ||
6707             ((first + length) > hw->eeprom.word_size))
6708                 return -EINVAL;
6709
6710         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6711
6712         return eeprom->ops.write_buffer(hw,  first, length, data);
6713 }
6714
6715 uint16_t
6716 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6717         switch (mac_type) {
6718         case ixgbe_mac_X550:
6719         case ixgbe_mac_X550EM_x:
6720         case ixgbe_mac_X550EM_a:
6721                 return ETH_RSS_RETA_SIZE_512;
6722         case ixgbe_mac_X550_vf:
6723         case ixgbe_mac_X550EM_x_vf:
6724         case ixgbe_mac_X550EM_a_vf:
6725                 return ETH_RSS_RETA_SIZE_64;
6726         default:
6727                 return ETH_RSS_RETA_SIZE_128;
6728         }
6729 }
6730
6731 uint32_t
6732 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6733         switch (mac_type) {
6734         case ixgbe_mac_X550:
6735         case ixgbe_mac_X550EM_x:
6736         case ixgbe_mac_X550EM_a:
6737                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6738                         return IXGBE_RETA(reta_idx >> 2);
6739                 else
6740                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6741         case ixgbe_mac_X550_vf:
6742         case ixgbe_mac_X550EM_x_vf:
6743         case ixgbe_mac_X550EM_a_vf:
6744                 return IXGBE_VFRETA(reta_idx >> 2);
6745         default:
6746                 return IXGBE_RETA(reta_idx >> 2);
6747         }
6748 }
6749
6750 uint32_t
6751 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6752         switch (mac_type) {
6753         case ixgbe_mac_X550_vf:
6754         case ixgbe_mac_X550EM_x_vf:
6755         case ixgbe_mac_X550EM_a_vf:
6756                 return IXGBE_VFMRQC;
6757         default:
6758                 return IXGBE_MRQC;
6759         }
6760 }
6761
6762 uint32_t
6763 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6764         switch (mac_type) {
6765         case ixgbe_mac_X550_vf:
6766         case ixgbe_mac_X550EM_x_vf:
6767         case ixgbe_mac_X550EM_a_vf:
6768                 return IXGBE_VFRSSRK(i);
6769         default:
6770                 return IXGBE_RSSRK(i);
6771         }
6772 }
6773
6774 bool
6775 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6776         switch (mac_type) {
6777         case ixgbe_mac_82599_vf:
6778         case ixgbe_mac_X540_vf:
6779                 return 0;
6780         default:
6781                 return 1;
6782         }
6783 }
6784
6785 static int
6786 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6787                         struct rte_eth_dcb_info *dcb_info)
6788 {
6789         struct ixgbe_dcb_config *dcb_config =
6790                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6791         struct ixgbe_dcb_tc_config *tc;
6792         uint8_t i, j;
6793
6794         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6795                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6796         else
6797                 dcb_info->nb_tcs = 1;
6798
6799         if (dcb_config->vt_mode) { /* vt is enabled*/
6800                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6801                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6802                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6803                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6804                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6805                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6806                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6807                                                 i * dcb_info->nb_tcs + j;
6808                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6809                                 dcb_info->tc_queue.tc_txq[i][j].base =
6810                                                 i * dcb_info->nb_tcs + j;
6811                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6812                         }
6813                 }
6814         } else { /* vt is disabled*/
6815                 struct rte_eth_dcb_rx_conf *rx_conf =
6816                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6817                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6818                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6819                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6820                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6821                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6822                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6823                         }
6824                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6825                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6826                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6827                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6828                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6829                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6830                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6831                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6832                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6833                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6834                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6835                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6836                         }
6837                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6838                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6839                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6840                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6841                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6842                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6843                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6844                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6845                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6846                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6847                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6848                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6849                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6850                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6851                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6852                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6853                 }
6854         }
6855         for (i = 0; i < dcb_info->nb_tcs; i++) {
6856                 tc = &dcb_config->tc_config[i];
6857                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6858         }
6859         return 0;
6860 }
6861
6862 /* Update e-tag ether type */
6863 static int
6864 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6865                             uint16_t ether_type)
6866 {
6867         uint32_t etag_etype;
6868
6869         if (hw->mac.type != ixgbe_mac_X550 &&
6870             hw->mac.type != ixgbe_mac_X550EM_x &&
6871             hw->mac.type != ixgbe_mac_X550EM_a) {
6872                 return -ENOTSUP;
6873         }
6874
6875         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6876         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6877         etag_etype |= ether_type;
6878         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6879         IXGBE_WRITE_FLUSH(hw);
6880
6881         return 0;
6882 }
6883
6884 /* Config l2 tunnel ether type */
6885 static int
6886 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6887                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6888 {
6889         int ret = 0;
6890         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6891
6892         if (l2_tunnel == NULL)
6893                 return -EINVAL;
6894
6895         switch (l2_tunnel->l2_tunnel_type) {
6896         case RTE_L2_TUNNEL_TYPE_E_TAG:
6897                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6898                 break;
6899         default:
6900                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6901                 ret = -EINVAL;
6902                 break;
6903         }
6904
6905         return ret;
6906 }
6907
6908 /* Enable e-tag tunnel */
6909 static int
6910 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6911 {
6912         uint32_t etag_etype;
6913
6914         if (hw->mac.type != ixgbe_mac_X550 &&
6915             hw->mac.type != ixgbe_mac_X550EM_x &&
6916             hw->mac.type != ixgbe_mac_X550EM_a) {
6917                 return -ENOTSUP;
6918         }
6919
6920         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6921         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6922         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6923         IXGBE_WRITE_FLUSH(hw);
6924
6925         return 0;
6926 }
6927
6928 /* Enable l2 tunnel */
6929 static int
6930 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6931                            enum rte_eth_tunnel_type l2_tunnel_type)
6932 {
6933         int ret = 0;
6934         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6935
6936         switch (l2_tunnel_type) {
6937         case RTE_L2_TUNNEL_TYPE_E_TAG:
6938                 ret = ixgbe_e_tag_enable(hw);
6939                 break;
6940         default:
6941                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6942                 ret = -EINVAL;
6943                 break;
6944         }
6945
6946         return ret;
6947 }
6948
6949 /* Disable e-tag tunnel */
6950 static int
6951 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6952 {
6953         uint32_t etag_etype;
6954
6955         if (hw->mac.type != ixgbe_mac_X550 &&
6956             hw->mac.type != ixgbe_mac_X550EM_x &&
6957             hw->mac.type != ixgbe_mac_X550EM_a) {
6958                 return -ENOTSUP;
6959         }
6960
6961         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6962         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6963         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6964         IXGBE_WRITE_FLUSH(hw);
6965
6966         return 0;
6967 }
6968
6969 /* Disable l2 tunnel */
6970 static int
6971 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6972                             enum rte_eth_tunnel_type l2_tunnel_type)
6973 {
6974         int ret = 0;
6975         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6976
6977         switch (l2_tunnel_type) {
6978         case RTE_L2_TUNNEL_TYPE_E_TAG:
6979                 ret = ixgbe_e_tag_disable(hw);
6980                 break;
6981         default:
6982                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6983                 ret = -EINVAL;
6984                 break;
6985         }
6986
6987         return ret;
6988 }
6989
6990 static int
6991 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6992                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6993 {
6994         int ret = 0;
6995         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6996         uint32_t i, rar_entries;
6997         uint32_t rar_low, rar_high;
6998
6999         if (hw->mac.type != ixgbe_mac_X550 &&
7000             hw->mac.type != ixgbe_mac_X550EM_x &&
7001             hw->mac.type != ixgbe_mac_X550EM_a) {
7002                 return -ENOTSUP;
7003         }
7004
7005         rar_entries = ixgbe_get_num_rx_addrs(hw);
7006
7007         for (i = 1; i < rar_entries; i++) {
7008                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7009                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7010                 if ((rar_high & IXGBE_RAH_AV) &&
7011                     (rar_high & IXGBE_RAH_ADTYPE) &&
7012                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7013                      l2_tunnel->tunnel_id)) {
7014                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7015                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7016
7017                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7018
7019                         return ret;
7020                 }
7021         }
7022
7023         return ret;
7024 }
7025
7026 static int
7027 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7028                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7029 {
7030         int ret = 0;
7031         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7032         uint32_t i, rar_entries;
7033         uint32_t rar_low, rar_high;
7034
7035         if (hw->mac.type != ixgbe_mac_X550 &&
7036             hw->mac.type != ixgbe_mac_X550EM_x &&
7037             hw->mac.type != ixgbe_mac_X550EM_a) {
7038                 return -ENOTSUP;
7039         }
7040
7041         /* One entry for one tunnel. Try to remove potential existing entry. */
7042         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7043
7044         rar_entries = ixgbe_get_num_rx_addrs(hw);
7045
7046         for (i = 1; i < rar_entries; i++) {
7047                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7048                 if (rar_high & IXGBE_RAH_AV) {
7049                         continue;
7050                 } else {
7051                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7052                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7053                         rar_low = l2_tunnel->tunnel_id;
7054
7055                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7056                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7057
7058                         return ret;
7059                 }
7060         }
7061
7062         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7063                      " Please remove a rule before adding a new one.");
7064         return -EINVAL;
7065 }
7066
7067 /* Add l2 tunnel filter */
7068 static int
7069 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7070                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7071 {
7072         int ret = 0;
7073
7074         switch (l2_tunnel->l2_tunnel_type) {
7075         case RTE_L2_TUNNEL_TYPE_E_TAG:
7076                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7077                 break;
7078         default:
7079                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7080                 ret = -EINVAL;
7081                 break;
7082         }
7083
7084         return ret;
7085 }
7086
7087 /* Delete l2 tunnel filter */
7088 static int
7089 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7090                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7091 {
7092         int ret = 0;
7093
7094         switch (l2_tunnel->l2_tunnel_type) {
7095         case RTE_L2_TUNNEL_TYPE_E_TAG:
7096                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7097                 break;
7098         default:
7099                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7100                 ret = -EINVAL;
7101                 break;
7102         }
7103
7104         return ret;
7105 }
7106
7107 /**
7108  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7109  * @dev: pointer to rte_eth_dev structure
7110  * @filter_op:operation will be taken.
7111  * @arg: a pointer to specific structure corresponding to the filter_op
7112  */
7113 static int
7114 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7115                                   enum rte_filter_op filter_op,
7116                                   void *arg)
7117 {
7118         int ret = 0;
7119
7120         if (filter_op == RTE_ETH_FILTER_NOP)
7121                 return 0;
7122
7123         if (arg == NULL) {
7124                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7125                             filter_op);
7126                 return -EINVAL;
7127         }
7128
7129         switch (filter_op) {
7130         case RTE_ETH_FILTER_ADD:
7131                 ret = ixgbe_dev_l2_tunnel_filter_add
7132                         (dev,
7133                          (struct rte_eth_l2_tunnel_conf *)arg);
7134                 break;
7135         case RTE_ETH_FILTER_DELETE:
7136                 ret = ixgbe_dev_l2_tunnel_filter_del
7137                         (dev,
7138                          (struct rte_eth_l2_tunnel_conf *)arg);
7139                 break;
7140         default:
7141                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7142                 ret = -EINVAL;
7143                 break;
7144         }
7145         return ret;
7146 }
7147
7148 static int
7149 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7150 {
7151         int ret = 0;
7152         uint32_t ctrl;
7153         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7154
7155         if (hw->mac.type != ixgbe_mac_X550 &&
7156             hw->mac.type != ixgbe_mac_X550EM_x &&
7157             hw->mac.type != ixgbe_mac_X550EM_a) {
7158                 return -ENOTSUP;
7159         }
7160
7161         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7162         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7163         if (en)
7164                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7165         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7166
7167         return ret;
7168 }
7169
7170 /* Enable l2 tunnel forwarding */
7171 static int
7172 ixgbe_dev_l2_tunnel_forwarding_enable
7173         (struct rte_eth_dev *dev,
7174          enum rte_eth_tunnel_type l2_tunnel_type)
7175 {
7176         int ret = 0;
7177
7178         switch (l2_tunnel_type) {
7179         case RTE_L2_TUNNEL_TYPE_E_TAG:
7180                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7181                 break;
7182         default:
7183                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7184                 ret = -EINVAL;
7185                 break;
7186         }
7187
7188         return ret;
7189 }
7190
7191 /* Disable l2 tunnel forwarding */
7192 static int
7193 ixgbe_dev_l2_tunnel_forwarding_disable
7194         (struct rte_eth_dev *dev,
7195          enum rte_eth_tunnel_type l2_tunnel_type)
7196 {
7197         int ret = 0;
7198
7199         switch (l2_tunnel_type) {
7200         case RTE_L2_TUNNEL_TYPE_E_TAG:
7201                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7202                 break;
7203         default:
7204                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7205                 ret = -EINVAL;
7206                 break;
7207         }
7208
7209         return ret;
7210 }
7211
7212 static int
7213 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7214                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7215                              bool en)
7216 {
7217         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7218         int ret = 0;
7219         uint32_t vmtir, vmvir;
7220         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7221
7222         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7223                 PMD_DRV_LOG(ERR,
7224                             "VF id %u should be less than %u",
7225                             l2_tunnel->vf_id,
7226                             pci_dev->max_vfs);
7227                 return -EINVAL;
7228         }
7229
7230         if (hw->mac.type != ixgbe_mac_X550 &&
7231             hw->mac.type != ixgbe_mac_X550EM_x &&
7232             hw->mac.type != ixgbe_mac_X550EM_a) {
7233                 return -ENOTSUP;
7234         }
7235
7236         if (en)
7237                 vmtir = l2_tunnel->tunnel_id;
7238         else
7239                 vmtir = 0;
7240
7241         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7242
7243         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7244         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7245         if (en)
7246                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7247         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7248
7249         return ret;
7250 }
7251
7252 /* Enable l2 tunnel tag insertion */
7253 static int
7254 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7255                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7256 {
7257         int ret = 0;
7258
7259         switch (l2_tunnel->l2_tunnel_type) {
7260         case RTE_L2_TUNNEL_TYPE_E_TAG:
7261                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7262                 break;
7263         default:
7264                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7265                 ret = -EINVAL;
7266                 break;
7267         }
7268
7269         return ret;
7270 }
7271
7272 /* Disable l2 tunnel tag insertion */
7273 static int
7274 ixgbe_dev_l2_tunnel_insertion_disable
7275         (struct rte_eth_dev *dev,
7276          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7277 {
7278         int ret = 0;
7279
7280         switch (l2_tunnel->l2_tunnel_type) {
7281         case RTE_L2_TUNNEL_TYPE_E_TAG:
7282                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7283                 break;
7284         default:
7285                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7286                 ret = -EINVAL;
7287                 break;
7288         }
7289
7290         return ret;
7291 }
7292
7293 static int
7294 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7295                              bool en)
7296 {
7297         int ret = 0;
7298         uint32_t qde;
7299         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7300
7301         if (hw->mac.type != ixgbe_mac_X550 &&
7302             hw->mac.type != ixgbe_mac_X550EM_x &&
7303             hw->mac.type != ixgbe_mac_X550EM_a) {
7304                 return -ENOTSUP;
7305         }
7306
7307         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7308         if (en)
7309                 qde |= IXGBE_QDE_STRIP_TAG;
7310         else
7311                 qde &= ~IXGBE_QDE_STRIP_TAG;
7312         qde &= ~IXGBE_QDE_READ;
7313         qde |= IXGBE_QDE_WRITE;
7314         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7315
7316         return ret;
7317 }
7318
7319 /* Enable l2 tunnel tag stripping */
7320 static int
7321 ixgbe_dev_l2_tunnel_stripping_enable
7322         (struct rte_eth_dev *dev,
7323          enum rte_eth_tunnel_type l2_tunnel_type)
7324 {
7325         int ret = 0;
7326
7327         switch (l2_tunnel_type) {
7328         case RTE_L2_TUNNEL_TYPE_E_TAG:
7329                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7330                 break;
7331         default:
7332                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7333                 ret = -EINVAL;
7334                 break;
7335         }
7336
7337         return ret;
7338 }
7339
7340 /* Disable l2 tunnel tag stripping */
7341 static int
7342 ixgbe_dev_l2_tunnel_stripping_disable
7343         (struct rte_eth_dev *dev,
7344          enum rte_eth_tunnel_type l2_tunnel_type)
7345 {
7346         int ret = 0;
7347
7348         switch (l2_tunnel_type) {
7349         case RTE_L2_TUNNEL_TYPE_E_TAG:
7350                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7351                 break;
7352         default:
7353                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7354                 ret = -EINVAL;
7355                 break;
7356         }
7357
7358         return ret;
7359 }
7360
7361 /* Enable/disable l2 tunnel offload functions */
7362 static int
7363 ixgbe_dev_l2_tunnel_offload_set
7364         (struct rte_eth_dev *dev,
7365          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7366          uint32_t mask,
7367          uint8_t en)
7368 {
7369         int ret = 0;
7370
7371         if (l2_tunnel == NULL)
7372                 return -EINVAL;
7373
7374         ret = -EINVAL;
7375         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7376                 if (en)
7377                         ret = ixgbe_dev_l2_tunnel_enable(
7378                                 dev,
7379                                 l2_tunnel->l2_tunnel_type);
7380                 else
7381                         ret = ixgbe_dev_l2_tunnel_disable(
7382                                 dev,
7383                                 l2_tunnel->l2_tunnel_type);
7384         }
7385
7386         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7387                 if (en)
7388                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7389                                 dev,
7390                                 l2_tunnel);
7391                 else
7392                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7393                                 dev,
7394                                 l2_tunnel);
7395         }
7396
7397         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7398                 if (en)
7399                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7400                                 dev,
7401                                 l2_tunnel->l2_tunnel_type);
7402                 else
7403                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7404                                 dev,
7405                                 l2_tunnel->l2_tunnel_type);
7406         }
7407
7408         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7409                 if (en)
7410                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7411                                 dev,
7412                                 l2_tunnel->l2_tunnel_type);
7413                 else
7414                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7415                                 dev,
7416                                 l2_tunnel->l2_tunnel_type);
7417         }
7418
7419         return ret;
7420 }
7421
7422 static int
7423 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7424                         uint16_t port)
7425 {
7426         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7427         IXGBE_WRITE_FLUSH(hw);
7428
7429         return 0;
7430 }
7431
7432 /* There's only one register for VxLAN UDP port.
7433  * So, we cannot add several ports. Will update it.
7434  */
7435 static int
7436 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7437                      uint16_t port)
7438 {
7439         if (port == 0) {
7440                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7441                 return -EINVAL;
7442         }
7443
7444         return ixgbe_update_vxlan_port(hw, port);
7445 }
7446
7447 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7448  * UDP port, it must have a value.
7449  * So, will reset it to the original value 0.
7450  */
7451 static int
7452 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7453                      uint16_t port)
7454 {
7455         uint16_t cur_port;
7456
7457         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7458
7459         if (cur_port != port) {
7460                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7461                 return -EINVAL;
7462         }
7463
7464         return ixgbe_update_vxlan_port(hw, 0);
7465 }
7466
7467 /* Add UDP tunneling port */
7468 static int
7469 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7470                               struct rte_eth_udp_tunnel *udp_tunnel)
7471 {
7472         int ret = 0;
7473         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7474
7475         if (hw->mac.type != ixgbe_mac_X550 &&
7476             hw->mac.type != ixgbe_mac_X550EM_x &&
7477             hw->mac.type != ixgbe_mac_X550EM_a) {
7478                 return -ENOTSUP;
7479         }
7480
7481         if (udp_tunnel == NULL)
7482                 return -EINVAL;
7483
7484         switch (udp_tunnel->prot_type) {
7485         case RTE_TUNNEL_TYPE_VXLAN:
7486                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7487                 break;
7488
7489         case RTE_TUNNEL_TYPE_GENEVE:
7490         case RTE_TUNNEL_TYPE_TEREDO:
7491                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7492                 ret = -EINVAL;
7493                 break;
7494
7495         default:
7496                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7497                 ret = -EINVAL;
7498                 break;
7499         }
7500
7501         return ret;
7502 }
7503
7504 /* Remove UDP tunneling port */
7505 static int
7506 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7507                               struct rte_eth_udp_tunnel *udp_tunnel)
7508 {
7509         int ret = 0;
7510         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7511
7512         if (hw->mac.type != ixgbe_mac_X550 &&
7513             hw->mac.type != ixgbe_mac_X550EM_x &&
7514             hw->mac.type != ixgbe_mac_X550EM_a) {
7515                 return -ENOTSUP;
7516         }
7517
7518         if (udp_tunnel == NULL)
7519                 return -EINVAL;
7520
7521         switch (udp_tunnel->prot_type) {
7522         case RTE_TUNNEL_TYPE_VXLAN:
7523                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7524                 break;
7525         case RTE_TUNNEL_TYPE_GENEVE:
7526         case RTE_TUNNEL_TYPE_TEREDO:
7527                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7528                 ret = -EINVAL;
7529                 break;
7530         default:
7531                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7532                 ret = -EINVAL;
7533                 break;
7534         }
7535
7536         return ret;
7537 }
7538
7539 static void
7540 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7541 {
7542         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7543
7544         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7545 }
7546
7547 static void
7548 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7549 {
7550         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7551
7552         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7553 }
7554
7555 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7556 {
7557         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7558         u32 in_msg = 0;
7559
7560         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7561                 return;
7562
7563         /* PF reset VF event */
7564         if (in_msg == IXGBE_PF_CONTROL_MSG)
7565                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
7566 }
7567
7568 static int
7569 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7570 {
7571         uint32_t eicr;
7572         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7573         struct ixgbe_interrupt *intr =
7574                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7575         ixgbevf_intr_disable(hw);
7576
7577         /* read-on-clear nic registers here */
7578         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7579         intr->flags = 0;
7580
7581         /* only one misc vector supported - mailbox */
7582         eicr &= IXGBE_VTEICR_MASK;
7583         if (eicr == IXGBE_MISC_VEC_ID)
7584                 intr->flags |= IXGBE_FLAG_MAILBOX;
7585
7586         return 0;
7587 }
7588
7589 static int
7590 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7591 {
7592         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7593         struct ixgbe_interrupt *intr =
7594                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7595
7596         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7597                 ixgbevf_mbx_process(dev);
7598                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7599         }
7600
7601         ixgbevf_intr_enable(hw);
7602
7603         return 0;
7604 }
7605
7606 static void
7607 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7608                               void *param)
7609 {
7610         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7611
7612         ixgbevf_dev_interrupt_get_status(dev);
7613         ixgbevf_dev_interrupt_action(dev);
7614 }
7615
7616 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
7617 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
7618 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
7619 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
7620 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
7621 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");