4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
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18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
63 #include <rte_hash_crc.h>
65 #include "ixgbe_logs.h"
66 #include "base/ixgbe_api.h"
67 #include "base/ixgbe_vf.h"
68 #include "base/ixgbe_common.h"
69 #include "ixgbe_ethdev.h"
70 #include "ixgbe_bypass.h"
71 #include "ixgbe_rxtx.h"
72 #include "base/ixgbe_type.h"
73 #include "base/ixgbe_phy.h"
74 #include "ixgbe_regs.h"
76 #include "rte_pmd_ixgbe.h"
79 * High threshold controlling when to start sending XOFF frames. Must be at
80 * least 8 bytes less than receive packet buffer size. This value is in units
83 #define IXGBE_FC_HI 0x80
86 * Low threshold controlling when to start sending XON frames. This value is
87 * in units of 1024 bytes.
89 #define IXGBE_FC_LO 0x40
91 /* Default minimum inter-interrupt interval for EITR configuration */
92 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
94 /* Timer value included in XOFF frames. */
95 #define IXGBE_FC_PAUSE 0x680
97 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
98 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
99 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
101 #define IXGBE_MMW_SIZE_DEFAULT 0x4
102 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
103 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
106 * Default values for RX/TX configuration
108 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
109 #define IXGBE_DEFAULT_RX_PTHRESH 8
110 #define IXGBE_DEFAULT_RX_HTHRESH 8
111 #define IXGBE_DEFAULT_RX_WTHRESH 0
113 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
114 #define IXGBE_DEFAULT_TX_PTHRESH 32
115 #define IXGBE_DEFAULT_TX_HTHRESH 0
116 #define IXGBE_DEFAULT_TX_WTHRESH 0
117 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
119 /* Bit shift and mask */
120 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
121 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
122 #define IXGBE_8_BIT_WIDTH CHAR_BIT
123 #define IXGBE_8_BIT_MASK UINT8_MAX
125 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
127 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
129 #define IXGBE_HKEY_MAX_INDEX 10
131 /* Additional timesync values. */
132 #define NSEC_PER_SEC 1000000000L
133 #define IXGBE_INCVAL_10GB 0x66666666
134 #define IXGBE_INCVAL_1GB 0x40000000
135 #define IXGBE_INCVAL_100 0x50000000
136 #define IXGBE_INCVAL_SHIFT_10GB 28
137 #define IXGBE_INCVAL_SHIFT_1GB 24
138 #define IXGBE_INCVAL_SHIFT_100 21
139 #define IXGBE_INCVAL_SHIFT_82599 7
140 #define IXGBE_INCPER_SHIFT_82599 24
142 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
144 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
145 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
146 #define DEFAULT_ETAG_ETYPE 0x893f
147 #define IXGBE_ETAG_ETYPE 0x00005084
148 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
149 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
150 #define IXGBE_RAH_ADTYPE 0x40000000
151 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
152 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
153 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
154 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
155 #define IXGBE_QDE_STRIP_TAG 0x00000004
156 #define IXGBE_VTEICR_MASK 0x07
158 #define IXGBE_EXVET_VET_EXT_SHIFT 16
159 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
161 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
162 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
163 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
164 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
165 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
166 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
167 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
168 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
169 static int ixgbe_dev_start(struct rte_eth_dev *dev);
170 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
171 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
172 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
173 static void ixgbe_dev_close(struct rte_eth_dev *dev);
174 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
175 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
176 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
177 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
178 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
179 int wait_to_complete);
180 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
181 struct rte_eth_stats *stats);
182 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
183 struct rte_eth_xstat *xstats, unsigned n);
184 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
185 struct rte_eth_xstat *xstats, unsigned n);
186 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
187 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
188 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
189 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
190 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
191 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
192 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
196 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
198 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
199 struct rte_eth_dev_info *dev_info);
200 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
201 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
202 struct rte_eth_dev_info *dev_info);
203 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
205 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
206 uint16_t vlan_id, int on);
207 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
208 enum rte_vlan_type vlan_type,
210 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
211 uint16_t queue, bool on);
212 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
214 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
215 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
216 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
217 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
218 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
220 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
221 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
222 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
223 struct rte_eth_fc_conf *fc_conf);
224 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
225 struct rte_eth_fc_conf *fc_conf);
226 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
227 struct rte_eth_pfc_conf *pfc_conf);
228 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
229 struct rte_eth_rss_reta_entry64 *reta_conf,
231 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
232 struct rte_eth_rss_reta_entry64 *reta_conf,
234 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
235 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
236 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
237 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
238 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
239 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
240 struct rte_intr_handle *handle);
241 static void ixgbe_dev_interrupt_handler(void *param);
242 static void ixgbe_dev_interrupt_delayed_handler(void *param);
243 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
244 uint32_t index, uint32_t pool);
245 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
246 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
247 struct ether_addr *mac_addr);
248 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
249 static bool is_device_supported(struct rte_eth_dev *dev,
250 struct eth_driver *drv);
252 /* For Virtual Function support */
253 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
254 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
255 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
256 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
257 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
258 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
259 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
260 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
261 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
262 struct rte_eth_stats *stats);
263 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
264 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
265 uint16_t vlan_id, int on);
266 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
267 uint16_t queue, int on);
268 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
269 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
270 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
272 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
274 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
275 uint8_t queue, uint8_t msix_vector);
276 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
277 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
278 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
280 /* For Eth VMDQ APIs support */
281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
282 ether_addr * mac_addr, uint8_t on);
283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
285 struct rte_eth_mirror_conf *mirror_conf,
286 uint8_t rule_id, uint8_t on);
287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
294 uint8_t queue, uint8_t msix_vector);
295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
297 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
298 uint16_t queue_idx, uint16_t tx_rate);
300 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
301 struct ether_addr *mac_addr,
302 uint32_t index, uint32_t pool);
303 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
304 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
305 struct ether_addr *mac_addr);
306 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
307 struct rte_eth_syn_filter *filter);
308 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
309 enum rte_filter_op filter_op,
311 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
312 struct ixgbe_5tuple_filter *filter);
313 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
314 struct ixgbe_5tuple_filter *filter);
315 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
316 enum rte_filter_op filter_op,
318 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
319 struct rte_eth_ntuple_filter *filter);
320 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
321 enum rte_filter_op filter_op,
323 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
324 struct rte_eth_ethertype_filter *filter);
325 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
326 enum rte_filter_type filter_type,
327 enum rte_filter_op filter_op,
329 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
331 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
332 struct ether_addr *mc_addr_set,
333 uint32_t nb_mc_addr);
334 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
335 struct rte_eth_dcb_info *dcb_info);
337 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
338 static int ixgbe_get_regs(struct rte_eth_dev *dev,
339 struct rte_dev_reg_info *regs);
340 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
341 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
342 struct rte_dev_eeprom_info *eeprom);
343 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
344 struct rte_dev_eeprom_info *eeprom);
346 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
347 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
348 struct rte_dev_reg_info *regs);
350 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
351 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
352 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
353 struct timespec *timestamp,
355 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
356 struct timespec *timestamp);
357 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
358 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
359 struct timespec *timestamp);
360 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
361 const struct timespec *timestamp);
362 static void ixgbevf_dev_interrupt_handler(void *param);
364 static int ixgbe_dev_l2_tunnel_eth_type_conf
365 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
366 static int ixgbe_dev_l2_tunnel_offload_set
367 (struct rte_eth_dev *dev,
368 struct rte_eth_l2_tunnel_conf *l2_tunnel,
371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
372 enum rte_filter_op filter_op,
375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
376 struct rte_eth_udp_tunnel *udp_tunnel);
377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
378 struct rte_eth_udp_tunnel *udp_tunnel);
379 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
380 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
383 * Define VF Stats MACRO for Non "cleared on read" register
385 #define UPDATE_VF_STAT(reg, last, cur) \
387 uint32_t latest = IXGBE_READ_REG(hw, reg); \
388 cur += (latest - last) & UINT_MAX; \
392 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
394 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
395 u64 new_msb = IXGBE_READ_REG(hw, msb); \
396 u64 latest = ((new_msb << 32) | new_lsb); \
397 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
401 #define IXGBE_SET_HWSTRIP(h, q) do {\
402 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
403 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
404 (h)->bitmap[idx] |= 1 << bit;\
407 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
408 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
409 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
410 (h)->bitmap[idx] &= ~(1 << bit);\
413 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
414 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
415 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
416 (r) = (h)->bitmap[idx] >> bit & 1;\
420 * The set of PCI devices this driver supports
422 static const struct rte_pci_id pci_id_ixgbe_map[] = {
423 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
424 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
425 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
476 #ifdef RTE_NIC_BYPASS
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
479 { .vendor_id = 0, /* sentinel */ },
483 * The set of PCI devices this driver supports (for 82599 VF)
485 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
486 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
487 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
488 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
489 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
490 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
491 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
492 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
493 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
494 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
495 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
496 { .vendor_id = 0, /* sentinel */ },
499 static const struct rte_eth_desc_lim rx_desc_lim = {
500 .nb_max = IXGBE_MAX_RING_DESC,
501 .nb_min = IXGBE_MIN_RING_DESC,
502 .nb_align = IXGBE_RXD_ALIGN,
505 static const struct rte_eth_desc_lim tx_desc_lim = {
506 .nb_max = IXGBE_MAX_RING_DESC,
507 .nb_min = IXGBE_MIN_RING_DESC,
508 .nb_align = IXGBE_TXD_ALIGN,
509 .nb_seg_max = IXGBE_TX_MAX_SEG,
510 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
513 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
514 .dev_configure = ixgbe_dev_configure,
515 .dev_start = ixgbe_dev_start,
516 .dev_stop = ixgbe_dev_stop,
517 .dev_set_link_up = ixgbe_dev_set_link_up,
518 .dev_set_link_down = ixgbe_dev_set_link_down,
519 .dev_close = ixgbe_dev_close,
520 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
521 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
522 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
523 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
524 .link_update = ixgbe_dev_link_update,
525 .stats_get = ixgbe_dev_stats_get,
526 .xstats_get = ixgbe_dev_xstats_get,
527 .stats_reset = ixgbe_dev_stats_reset,
528 .xstats_reset = ixgbe_dev_xstats_reset,
529 .xstats_get_names = ixgbe_dev_xstats_get_names,
530 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
531 .fw_version_get = ixgbe_fw_version_get,
532 .dev_infos_get = ixgbe_dev_info_get,
533 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
534 .mtu_set = ixgbe_dev_mtu_set,
535 .vlan_filter_set = ixgbe_vlan_filter_set,
536 .vlan_tpid_set = ixgbe_vlan_tpid_set,
537 .vlan_offload_set = ixgbe_vlan_offload_set,
538 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
539 .rx_queue_start = ixgbe_dev_rx_queue_start,
540 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
541 .tx_queue_start = ixgbe_dev_tx_queue_start,
542 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
543 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
544 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
545 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
546 .rx_queue_release = ixgbe_dev_rx_queue_release,
547 .rx_queue_count = ixgbe_dev_rx_queue_count,
548 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
549 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
550 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
551 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
552 .tx_queue_release = ixgbe_dev_tx_queue_release,
553 .dev_led_on = ixgbe_dev_led_on,
554 .dev_led_off = ixgbe_dev_led_off,
555 .flow_ctrl_get = ixgbe_flow_ctrl_get,
556 .flow_ctrl_set = ixgbe_flow_ctrl_set,
557 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
558 .mac_addr_add = ixgbe_add_rar,
559 .mac_addr_remove = ixgbe_remove_rar,
560 .mac_addr_set = ixgbe_set_default_mac_addr,
561 .uc_hash_table_set = ixgbe_uc_hash_table_set,
562 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
563 .mirror_rule_set = ixgbe_mirror_rule_set,
564 .mirror_rule_reset = ixgbe_mirror_rule_reset,
565 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
566 .reta_update = ixgbe_dev_rss_reta_update,
567 .reta_query = ixgbe_dev_rss_reta_query,
568 #ifdef RTE_NIC_BYPASS
569 .bypass_init = ixgbe_bypass_init,
570 .bypass_state_set = ixgbe_bypass_state_store,
571 .bypass_state_show = ixgbe_bypass_state_show,
572 .bypass_event_set = ixgbe_bypass_event_store,
573 .bypass_event_show = ixgbe_bypass_event_show,
574 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
575 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
576 .bypass_ver_show = ixgbe_bypass_ver_show,
577 .bypass_wd_reset = ixgbe_bypass_wd_reset,
578 #endif /* RTE_NIC_BYPASS */
579 .rss_hash_update = ixgbe_dev_rss_hash_update,
580 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
581 .filter_ctrl = ixgbe_dev_filter_ctrl,
582 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
583 .rxq_info_get = ixgbe_rxq_info_get,
584 .txq_info_get = ixgbe_txq_info_get,
585 .timesync_enable = ixgbe_timesync_enable,
586 .timesync_disable = ixgbe_timesync_disable,
587 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
588 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
589 .get_reg = ixgbe_get_regs,
590 .get_eeprom_length = ixgbe_get_eeprom_length,
591 .get_eeprom = ixgbe_get_eeprom,
592 .set_eeprom = ixgbe_set_eeprom,
593 .get_dcb_info = ixgbe_dev_get_dcb_info,
594 .timesync_adjust_time = ixgbe_timesync_adjust_time,
595 .timesync_read_time = ixgbe_timesync_read_time,
596 .timesync_write_time = ixgbe_timesync_write_time,
597 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
598 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
599 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
600 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
604 * dev_ops for virtual function, bare necessities for basic vf
605 * operation have been implemented
607 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
608 .dev_configure = ixgbevf_dev_configure,
609 .dev_start = ixgbevf_dev_start,
610 .dev_stop = ixgbevf_dev_stop,
611 .link_update = ixgbe_dev_link_update,
612 .stats_get = ixgbevf_dev_stats_get,
613 .xstats_get = ixgbevf_dev_xstats_get,
614 .stats_reset = ixgbevf_dev_stats_reset,
615 .xstats_reset = ixgbevf_dev_stats_reset,
616 .xstats_get_names = ixgbevf_dev_xstats_get_names,
617 .dev_close = ixgbevf_dev_close,
618 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
619 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
620 .dev_infos_get = ixgbevf_dev_info_get,
621 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
622 .mtu_set = ixgbevf_dev_set_mtu,
623 .vlan_filter_set = ixgbevf_vlan_filter_set,
624 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
625 .vlan_offload_set = ixgbevf_vlan_offload_set,
626 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
627 .rx_queue_release = ixgbe_dev_rx_queue_release,
628 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
629 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
630 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
631 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
632 .tx_queue_release = ixgbe_dev_tx_queue_release,
633 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
634 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
635 .mac_addr_add = ixgbevf_add_mac_addr,
636 .mac_addr_remove = ixgbevf_remove_mac_addr,
637 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
638 .rxq_info_get = ixgbe_rxq_info_get,
639 .txq_info_get = ixgbe_txq_info_get,
640 .mac_addr_set = ixgbevf_set_default_mac_addr,
641 .get_reg = ixgbevf_get_regs,
642 .reta_update = ixgbe_dev_rss_reta_update,
643 .reta_query = ixgbe_dev_rss_reta_query,
644 .rss_hash_update = ixgbe_dev_rss_hash_update,
645 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
648 /* store statistics names and its offset in stats structure */
649 struct rte_ixgbe_xstats_name_off {
650 char name[RTE_ETH_XSTATS_NAME_SIZE];
654 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
655 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
656 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
657 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
658 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
659 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
660 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
661 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
662 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
663 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
664 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
665 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
666 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
667 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
668 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
669 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
671 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
673 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
674 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
675 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
676 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
677 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
678 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
679 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
680 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
681 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
682 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
683 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
684 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
685 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
686 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
687 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
688 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
689 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
691 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
693 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
694 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
695 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
696 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
698 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
700 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
702 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
704 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
706 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
708 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
711 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
712 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
713 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
715 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
716 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
717 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
718 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
719 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
721 {"rx_fcoe_no_direct_data_placement_ext_buff",
722 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
724 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
726 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
728 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
730 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
732 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
735 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
736 sizeof(rte_ixgbe_stats_strings[0]))
738 /* MACsec statistics */
739 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
740 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
742 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
743 out_pkts_encrypted)},
744 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
745 out_pkts_protected)},
746 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
747 out_octets_encrypted)},
748 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
749 out_octets_protected)},
750 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
752 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
754 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
756 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
757 in_pkts_unknownsci)},
758 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
759 in_octets_decrypted)},
760 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
761 in_octets_validated)},
762 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
764 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
766 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
768 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
770 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
772 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
774 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
776 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
777 in_pkts_notusingsa)},
780 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
781 sizeof(rte_ixgbe_macsec_strings[0]))
783 /* Per-queue statistics */
784 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
785 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
786 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
787 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
788 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
791 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
792 sizeof(rte_ixgbe_rxq_strings[0]))
793 #define IXGBE_NB_RXQ_PRIO_VALUES 8
795 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
796 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
797 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
798 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
802 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
803 sizeof(rte_ixgbe_txq_strings[0]))
804 #define IXGBE_NB_TXQ_PRIO_VALUES 8
806 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
807 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
810 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
811 sizeof(rte_ixgbevf_stats_strings[0]))
814 * Atomically reads the link status information from global
815 * structure rte_eth_dev.
818 * - Pointer to the structure rte_eth_dev to read from.
819 * - Pointer to the buffer to be saved with the link status.
822 * - On success, zero.
823 * - On failure, negative value.
826 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
827 struct rte_eth_link *link)
829 struct rte_eth_link *dst = link;
830 struct rte_eth_link *src = &(dev->data->dev_link);
832 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
833 *(uint64_t *)src) == 0)
840 * Atomically writes the link status information into global
841 * structure rte_eth_dev.
844 * - Pointer to the structure rte_eth_dev to read from.
845 * - Pointer to the buffer to be saved with the link status.
848 * - On success, zero.
849 * - On failure, negative value.
852 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
853 struct rte_eth_link *link)
855 struct rte_eth_link *dst = &(dev->data->dev_link);
856 struct rte_eth_link *src = link;
858 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
859 *(uint64_t *)src) == 0)
866 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
869 ixgbe_is_sfp(struct ixgbe_hw *hw)
871 switch (hw->phy.type) {
872 case ixgbe_phy_sfp_avago:
873 case ixgbe_phy_sfp_ftl:
874 case ixgbe_phy_sfp_intel:
875 case ixgbe_phy_sfp_unknown:
876 case ixgbe_phy_sfp_passive_tyco:
877 case ixgbe_phy_sfp_passive_unknown:
884 static inline int32_t
885 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
890 status = ixgbe_reset_hw(hw);
892 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
893 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
894 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
895 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
896 IXGBE_WRITE_FLUSH(hw);
898 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
899 status = IXGBE_SUCCESS;
904 ixgbe_enable_intr(struct rte_eth_dev *dev)
906 struct ixgbe_interrupt *intr =
907 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
908 struct ixgbe_hw *hw =
909 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
911 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
912 IXGBE_WRITE_FLUSH(hw);
916 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
919 ixgbe_disable_intr(struct ixgbe_hw *hw)
921 PMD_INIT_FUNC_TRACE();
923 if (hw->mac.type == ixgbe_mac_82598EB) {
924 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
926 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
927 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
928 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
930 IXGBE_WRITE_FLUSH(hw);
934 * This function resets queue statistics mapping registers.
935 * From Niantic datasheet, Initialization of Statistics section:
936 * "...if software requires the queue counters, the RQSMR and TQSM registers
937 * must be re-programmed following a device reset.
940 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
944 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
945 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
946 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
952 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
957 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
958 #define NB_QMAP_FIELDS_PER_QSM_REG 4
959 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
961 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
962 struct ixgbe_stat_mapping_registers *stat_mappings =
963 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
964 uint32_t qsmr_mask = 0;
965 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
969 if ((hw->mac.type != ixgbe_mac_82599EB) &&
970 (hw->mac.type != ixgbe_mac_X540) &&
971 (hw->mac.type != ixgbe_mac_X550) &&
972 (hw->mac.type != ixgbe_mac_X550EM_x) &&
973 (hw->mac.type != ixgbe_mac_X550EM_a))
976 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
977 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
980 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
981 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
982 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
985 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
987 /* Now clear any previous stat_idx set */
988 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
990 stat_mappings->tqsm[n] &= ~clearing_mask;
992 stat_mappings->rqsmr[n] &= ~clearing_mask;
994 q_map = (uint32_t)stat_idx;
995 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
996 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
998 stat_mappings->tqsm[n] |= qsmr_mask;
1000 stat_mappings->rqsmr[n] |= qsmr_mask;
1002 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1003 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1004 queue_id, stat_idx);
1005 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1006 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1008 /* Now write the mapping in the appropriate register */
1010 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1011 stat_mappings->rqsmr[n], n);
1012 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1014 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1015 stat_mappings->tqsm[n], n);
1016 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1022 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1024 struct ixgbe_stat_mapping_registers *stat_mappings =
1025 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1026 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1029 /* write whatever was in stat mapping table to the NIC */
1030 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1032 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1035 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1040 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1043 struct ixgbe_dcb_tc_config *tc;
1044 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1046 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1047 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1048 for (i = 0; i < dcb_max_tc; i++) {
1049 tc = &dcb_config->tc_config[i];
1050 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1051 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1052 (uint8_t)(100/dcb_max_tc + (i & 1));
1053 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1054 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1055 (uint8_t)(100/dcb_max_tc + (i & 1));
1056 tc->pfc = ixgbe_dcb_pfc_disabled;
1059 /* Initialize default user to priority mapping, UPx->TC0 */
1060 tc = &dcb_config->tc_config[0];
1061 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1062 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1063 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1064 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1065 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1067 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1068 dcb_config->pfc_mode_enable = false;
1069 dcb_config->vt_mode = true;
1070 dcb_config->round_robin_enable = false;
1071 /* support all DCB capabilities in 82599 */
1072 dcb_config->support.capabilities = 0xFF;
1074 /*we only support 4 Tcs for X540, X550 */
1075 if (hw->mac.type == ixgbe_mac_X540 ||
1076 hw->mac.type == ixgbe_mac_X550 ||
1077 hw->mac.type == ixgbe_mac_X550EM_x ||
1078 hw->mac.type == ixgbe_mac_X550EM_a) {
1079 dcb_config->num_tcs.pg_tcs = 4;
1080 dcb_config->num_tcs.pfc_tcs = 4;
1085 * Ensure that all locks are released before first NVM or PHY access
1088 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1093 * Phy lock should not fail in this early stage. If this is the case,
1094 * it is due to an improper exit of the application.
1095 * So force the release of the faulty lock. Release of common lock
1096 * is done automatically by swfw_sync function.
1098 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1099 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1100 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1102 ixgbe_release_swfw_semaphore(hw, mask);
1105 * These ones are more tricky since they are common to all ports; but
1106 * swfw_sync retries last long enough (1s) to be almost sure that if
1107 * lock can not be taken it is due to an improper lock of the
1110 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1111 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1112 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1114 ixgbe_release_swfw_semaphore(hw, mask);
1118 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1119 * It returns 0 on success.
1122 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1124 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1125 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1126 struct ixgbe_hw *hw =
1127 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1128 struct ixgbe_vfta *shadow_vfta =
1129 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1130 struct ixgbe_hwstrip *hwstrip =
1131 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1132 struct ixgbe_dcb_config *dcb_config =
1133 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1134 struct ixgbe_filter_info *filter_info =
1135 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1136 struct ixgbe_bw_conf *bw_conf =
1137 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1142 PMD_INIT_FUNC_TRACE();
1144 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1145 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1146 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1147 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1150 * For secondary processes, we don't initialise any further as primary
1151 * has already done this work. Only check we don't need a different
1152 * RX and TX function.
1154 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1155 struct ixgbe_tx_queue *txq;
1156 /* TX queue function in primary, set by last queue initialized
1157 * Tx queue may not initialized by primary process
1159 if (eth_dev->data->tx_queues) {
1160 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1161 ixgbe_set_tx_function(eth_dev, txq);
1163 /* Use default TX function if we get here */
1164 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1165 "Using default TX function.");
1168 ixgbe_set_rx_function(eth_dev);
1173 rte_eth_copy_pci_info(eth_dev, pci_dev);
1174 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1176 /* Vendor and Device ID need to be set before init of shared code */
1177 hw->device_id = pci_dev->id.device_id;
1178 hw->vendor_id = pci_dev->id.vendor_id;
1179 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1180 hw->allow_unsupported_sfp = 1;
1182 /* Initialize the shared code (base driver) */
1183 #ifdef RTE_NIC_BYPASS
1184 diag = ixgbe_bypass_init_shared_code(hw);
1186 diag = ixgbe_init_shared_code(hw);
1187 #endif /* RTE_NIC_BYPASS */
1189 if (diag != IXGBE_SUCCESS) {
1190 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1194 /* pick up the PCI bus settings for reporting later */
1195 ixgbe_get_bus_info(hw);
1197 /* Unlock any pending hardware semaphore */
1198 ixgbe_swfw_lock_reset(hw);
1200 /* Initialize DCB configuration*/
1201 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1202 ixgbe_dcb_init(hw, dcb_config);
1203 /* Get Hardware Flow Control setting */
1204 hw->fc.requested_mode = ixgbe_fc_full;
1205 hw->fc.current_mode = ixgbe_fc_full;
1206 hw->fc.pause_time = IXGBE_FC_PAUSE;
1207 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1208 hw->fc.low_water[i] = IXGBE_FC_LO;
1209 hw->fc.high_water[i] = IXGBE_FC_HI;
1211 hw->fc.send_xon = 1;
1213 /* Make sure we have a good EEPROM before we read from it */
1214 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1215 if (diag != IXGBE_SUCCESS) {
1216 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1220 #ifdef RTE_NIC_BYPASS
1221 diag = ixgbe_bypass_init_hw(hw);
1223 diag = ixgbe_init_hw(hw);
1224 #endif /* RTE_NIC_BYPASS */
1227 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1228 * is called too soon after the kernel driver unbinding/binding occurs.
1229 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1230 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1231 * also called. See ixgbe_identify_phy_82599(). The reason for the
1232 * failure is not known, and only occuts when virtualisation features
1233 * are disabled in the bios. A delay of 100ms was found to be enough by
1234 * trial-and-error, and is doubled to be safe.
1236 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1238 diag = ixgbe_init_hw(hw);
1241 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1242 diag = IXGBE_SUCCESS;
1244 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1245 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1246 "LOM. Please be aware there may be issues associated "
1247 "with your hardware.");
1248 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1249 "please contact your Intel or hardware representative "
1250 "who provided you with this hardware.");
1251 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1252 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1254 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1258 /* Reset the hw statistics */
1259 ixgbe_dev_stats_reset(eth_dev);
1261 /* disable interrupt */
1262 ixgbe_disable_intr(hw);
1264 /* reset mappings for queue statistics hw counters*/
1265 ixgbe_reset_qstat_mappings(hw);
1267 /* Allocate memory for storing MAC addresses */
1268 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1269 hw->mac.num_rar_entries, 0);
1270 if (eth_dev->data->mac_addrs == NULL) {
1272 "Failed to allocate %u bytes needed to store "
1274 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1277 /* Copy the permanent MAC address */
1278 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1279 ð_dev->data->mac_addrs[0]);
1281 /* Allocate memory for storing hash filter MAC addresses */
1282 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1283 IXGBE_VMDQ_NUM_UC_MAC, 0);
1284 if (eth_dev->data->hash_mac_addrs == NULL) {
1286 "Failed to allocate %d bytes needed to store MAC addresses",
1287 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1291 /* initialize the vfta */
1292 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1294 /* initialize the hw strip bitmap*/
1295 memset(hwstrip, 0, sizeof(*hwstrip));
1297 /* initialize PF if max_vfs not zero */
1298 ixgbe_pf_host_init(eth_dev);
1300 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1301 /* let hardware know driver is loaded */
1302 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1303 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1304 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1305 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1306 IXGBE_WRITE_FLUSH(hw);
1308 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1309 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1310 (int) hw->mac.type, (int) hw->phy.type,
1311 (int) hw->phy.sfp_type);
1313 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1314 (int) hw->mac.type, (int) hw->phy.type);
1316 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1317 eth_dev->data->port_id, pci_dev->id.vendor_id,
1318 pci_dev->id.device_id);
1320 rte_intr_callback_register(intr_handle,
1321 ixgbe_dev_interrupt_handler, eth_dev);
1323 /* enable uio/vfio intr/eventfd mapping */
1324 rte_intr_enable(intr_handle);
1326 /* enable support intr */
1327 ixgbe_enable_intr(eth_dev);
1329 /* initialize filter info */
1330 memset(filter_info, 0,
1331 sizeof(struct ixgbe_filter_info));
1333 /* initialize 5tuple filter list */
1334 TAILQ_INIT(&filter_info->fivetuple_list);
1336 /* initialize flow director filter list & hash */
1337 ixgbe_fdir_filter_init(eth_dev);
1339 /* initialize l2 tunnel filter list & hash */
1340 ixgbe_l2_tn_filter_init(eth_dev);
1342 TAILQ_INIT(&filter_ntuple_list);
1343 TAILQ_INIT(&filter_ethertype_list);
1344 TAILQ_INIT(&filter_syn_list);
1345 TAILQ_INIT(&filter_fdir_list);
1346 TAILQ_INIT(&filter_l2_tunnel_list);
1347 TAILQ_INIT(&ixgbe_flow_list);
1349 /* initialize bandwidth configuration info */
1350 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1356 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1358 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1359 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1360 struct ixgbe_hw *hw;
1362 PMD_INIT_FUNC_TRACE();
1364 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1367 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1369 if (hw->adapter_stopped == 0)
1370 ixgbe_dev_close(eth_dev);
1372 eth_dev->dev_ops = NULL;
1373 eth_dev->rx_pkt_burst = NULL;
1374 eth_dev->tx_pkt_burst = NULL;
1376 /* Unlock any pending hardware semaphore */
1377 ixgbe_swfw_lock_reset(hw);
1379 /* disable uio intr before callback unregister */
1380 rte_intr_disable(intr_handle);
1381 rte_intr_callback_unregister(intr_handle,
1382 ixgbe_dev_interrupt_handler, eth_dev);
1384 /* uninitialize PF if max_vfs not zero */
1385 ixgbe_pf_host_uninit(eth_dev);
1387 rte_free(eth_dev->data->mac_addrs);
1388 eth_dev->data->mac_addrs = NULL;
1390 rte_free(eth_dev->data->hash_mac_addrs);
1391 eth_dev->data->hash_mac_addrs = NULL;
1393 /* remove all the fdir filters & hash */
1394 ixgbe_fdir_filter_uninit(eth_dev);
1396 /* remove all the L2 tunnel filters & hash */
1397 ixgbe_l2_tn_filter_uninit(eth_dev);
1399 /* Remove all ntuple filters of the device */
1400 ixgbe_ntuple_filter_uninit(eth_dev);
1402 /* clear all the filters list */
1403 ixgbe_filterlist_flush();
1408 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1410 struct ixgbe_filter_info *filter_info =
1411 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1412 struct ixgbe_5tuple_filter *p_5tuple;
1414 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1415 TAILQ_REMOVE(&filter_info->fivetuple_list,
1420 memset(filter_info->fivetuple_mask, 0,
1421 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1426 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1428 struct ixgbe_hw_fdir_info *fdir_info =
1429 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1430 struct ixgbe_fdir_filter *fdir_filter;
1432 if (fdir_info->hash_map)
1433 rte_free(fdir_info->hash_map);
1434 if (fdir_info->hash_handle)
1435 rte_hash_free(fdir_info->hash_handle);
1437 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1438 TAILQ_REMOVE(&fdir_info->fdir_list,
1441 rte_free(fdir_filter);
1447 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1449 struct ixgbe_l2_tn_info *l2_tn_info =
1450 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1451 struct ixgbe_l2_tn_filter *l2_tn_filter;
1453 if (l2_tn_info->hash_map)
1454 rte_free(l2_tn_info->hash_map);
1455 if (l2_tn_info->hash_handle)
1456 rte_hash_free(l2_tn_info->hash_handle);
1458 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1459 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1462 rte_free(l2_tn_filter);
1468 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1470 struct ixgbe_hw_fdir_info *fdir_info =
1471 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1472 char fdir_hash_name[RTE_HASH_NAMESIZE];
1473 struct rte_hash_parameters fdir_hash_params = {
1474 .name = fdir_hash_name,
1475 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1476 .key_len = sizeof(union ixgbe_atr_input),
1477 .hash_func = rte_hash_crc,
1478 .hash_func_init_val = 0,
1479 .socket_id = rte_socket_id(),
1482 TAILQ_INIT(&fdir_info->fdir_list);
1483 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1484 "fdir_%s", eth_dev->data->name);
1485 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1486 if (!fdir_info->hash_handle) {
1487 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1490 fdir_info->hash_map = rte_zmalloc("ixgbe",
1491 sizeof(struct ixgbe_fdir_filter *) *
1492 IXGBE_MAX_FDIR_FILTER_NUM,
1494 if (!fdir_info->hash_map) {
1496 "Failed to allocate memory for fdir hash map!");
1499 fdir_info->mask_added = FALSE;
1504 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1506 struct ixgbe_l2_tn_info *l2_tn_info =
1507 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1508 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1509 struct rte_hash_parameters l2_tn_hash_params = {
1510 .name = l2_tn_hash_name,
1511 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1512 .key_len = sizeof(struct ixgbe_l2_tn_key),
1513 .hash_func = rte_hash_crc,
1514 .hash_func_init_val = 0,
1515 .socket_id = rte_socket_id(),
1518 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1519 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1520 "l2_tn_%s", eth_dev->data->name);
1521 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1522 if (!l2_tn_info->hash_handle) {
1523 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1526 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1527 sizeof(struct ixgbe_l2_tn_filter *) *
1528 IXGBE_MAX_L2_TN_FILTER_NUM,
1530 if (!l2_tn_info->hash_map) {
1532 "Failed to allocate memory for L2 TN hash map!");
1535 l2_tn_info->e_tag_en = FALSE;
1536 l2_tn_info->e_tag_fwd_en = FALSE;
1537 l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1542 * Negotiate mailbox API version with the PF.
1543 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1544 * Then we try to negotiate starting with the most recent one.
1545 * If all negotiation attempts fail, then we will proceed with
1546 * the default one (ixgbe_mbox_api_10).
1549 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1553 /* start with highest supported, proceed down */
1554 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1561 i != RTE_DIM(sup_ver) &&
1562 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1568 generate_random_mac_addr(struct ether_addr *mac_addr)
1572 /* Set Organizationally Unique Identifier (OUI) prefix. */
1573 mac_addr->addr_bytes[0] = 0x00;
1574 mac_addr->addr_bytes[1] = 0x09;
1575 mac_addr->addr_bytes[2] = 0xC0;
1576 /* Force indication of locally assigned MAC address. */
1577 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1578 /* Generate the last 3 bytes of the MAC address with a random number. */
1579 random = rte_rand();
1580 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1584 * Virtual Function device init
1587 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1591 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1592 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1593 struct ixgbe_hw *hw =
1594 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1595 struct ixgbe_vfta *shadow_vfta =
1596 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1597 struct ixgbe_hwstrip *hwstrip =
1598 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1599 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1601 PMD_INIT_FUNC_TRACE();
1603 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1604 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1605 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1607 /* for secondary processes, we don't initialise any further as primary
1608 * has already done this work. Only check we don't need a different
1611 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1612 struct ixgbe_tx_queue *txq;
1613 /* TX queue function in primary, set by last queue initialized
1614 * Tx queue may not initialized by primary process
1616 if (eth_dev->data->tx_queues) {
1617 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1618 ixgbe_set_tx_function(eth_dev, txq);
1620 /* Use default TX function if we get here */
1621 PMD_INIT_LOG(NOTICE,
1622 "No TX queues configured yet. Using default TX function.");
1625 ixgbe_set_rx_function(eth_dev);
1630 rte_eth_copy_pci_info(eth_dev, pci_dev);
1631 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1633 hw->device_id = pci_dev->id.device_id;
1634 hw->vendor_id = pci_dev->id.vendor_id;
1635 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1637 /* initialize the vfta */
1638 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1640 /* initialize the hw strip bitmap*/
1641 memset(hwstrip, 0, sizeof(*hwstrip));
1643 /* Initialize the shared code (base driver) */
1644 diag = ixgbe_init_shared_code(hw);
1645 if (diag != IXGBE_SUCCESS) {
1646 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1650 /* init_mailbox_params */
1651 hw->mbx.ops.init_params(hw);
1653 /* Reset the hw statistics */
1654 ixgbevf_dev_stats_reset(eth_dev);
1656 /* Disable the interrupts for VF */
1657 ixgbevf_intr_disable(hw);
1659 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1660 diag = hw->mac.ops.reset_hw(hw);
1663 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1664 * the underlying PF driver has not assigned a MAC address to the VF.
1665 * In this case, assign a random MAC address.
1667 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1668 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1672 /* negotiate mailbox API version to use with the PF. */
1673 ixgbevf_negotiate_api(hw);
1675 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1676 ixgbevf_get_queues(hw, &tcs, &tc);
1678 /* Allocate memory for storing MAC addresses */
1679 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1680 hw->mac.num_rar_entries, 0);
1681 if (eth_dev->data->mac_addrs == NULL) {
1683 "Failed to allocate %u bytes needed to store "
1685 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1689 /* Generate a random MAC address, if none was assigned by PF. */
1690 if (is_zero_ether_addr(perm_addr)) {
1691 generate_random_mac_addr(perm_addr);
1692 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1694 rte_free(eth_dev->data->mac_addrs);
1695 eth_dev->data->mac_addrs = NULL;
1698 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1699 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1700 "%02x:%02x:%02x:%02x:%02x:%02x",
1701 perm_addr->addr_bytes[0],
1702 perm_addr->addr_bytes[1],
1703 perm_addr->addr_bytes[2],
1704 perm_addr->addr_bytes[3],
1705 perm_addr->addr_bytes[4],
1706 perm_addr->addr_bytes[5]);
1709 /* Copy the permanent MAC address */
1710 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1712 /* reset the hardware with the new settings */
1713 diag = hw->mac.ops.start_hw(hw);
1719 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1723 rte_intr_callback_register(intr_handle,
1724 ixgbevf_dev_interrupt_handler, eth_dev);
1725 rte_intr_enable(intr_handle);
1726 ixgbevf_intr_enable(hw);
1728 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1729 eth_dev->data->port_id, pci_dev->id.vendor_id,
1730 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1735 /* Virtual Function device uninit */
1738 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1740 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1741 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1742 struct ixgbe_hw *hw;
1744 PMD_INIT_FUNC_TRACE();
1746 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1749 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1751 if (hw->adapter_stopped == 0)
1752 ixgbevf_dev_close(eth_dev);
1754 eth_dev->dev_ops = NULL;
1755 eth_dev->rx_pkt_burst = NULL;
1756 eth_dev->tx_pkt_burst = NULL;
1758 /* Disable the interrupts for VF */
1759 ixgbevf_intr_disable(hw);
1761 rte_free(eth_dev->data->mac_addrs);
1762 eth_dev->data->mac_addrs = NULL;
1764 rte_intr_disable(intr_handle);
1765 rte_intr_callback_unregister(intr_handle,
1766 ixgbevf_dev_interrupt_handler, eth_dev);
1771 static struct eth_driver rte_ixgbe_pmd = {
1773 .id_table = pci_id_ixgbe_map,
1774 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1775 .probe = rte_eth_dev_pci_probe,
1776 .remove = rte_eth_dev_pci_remove,
1778 .eth_dev_init = eth_ixgbe_dev_init,
1779 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1780 .dev_private_size = sizeof(struct ixgbe_adapter),
1784 * virtual function driver struct
1786 static struct eth_driver rte_ixgbevf_pmd = {
1788 .id_table = pci_id_ixgbevf_map,
1789 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1790 .probe = rte_eth_dev_pci_probe,
1791 .remove = rte_eth_dev_pci_remove,
1793 .eth_dev_init = eth_ixgbevf_dev_init,
1794 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1795 .dev_private_size = sizeof(struct ixgbe_adapter),
1799 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1801 struct ixgbe_hw *hw =
1802 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1803 struct ixgbe_vfta *shadow_vfta =
1804 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1809 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1810 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1811 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1816 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1818 /* update local VFTA copy */
1819 shadow_vfta->vfta[vid_idx] = vfta;
1825 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1828 ixgbe_vlan_hw_strip_enable(dev, queue);
1830 ixgbe_vlan_hw_strip_disable(dev, queue);
1834 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1835 enum rte_vlan_type vlan_type,
1838 struct ixgbe_hw *hw =
1839 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1844 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1845 qinq &= IXGBE_DMATXCTL_GDV;
1847 switch (vlan_type) {
1848 case ETH_VLAN_TYPE_INNER:
1850 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1851 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1852 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1853 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1854 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1855 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1856 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1859 PMD_DRV_LOG(ERR, "Inner type is not supported"
1863 case ETH_VLAN_TYPE_OUTER:
1865 /* Only the high 16-bits is valid */
1866 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1867 IXGBE_EXVET_VET_EXT_SHIFT);
1869 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1870 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1871 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1872 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1873 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1874 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1875 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1881 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1889 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1891 struct ixgbe_hw *hw =
1892 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1895 PMD_INIT_FUNC_TRACE();
1897 /* Filter Table Disable */
1898 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1899 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1901 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1905 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1907 struct ixgbe_hw *hw =
1908 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1909 struct ixgbe_vfta *shadow_vfta =
1910 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1914 PMD_INIT_FUNC_TRACE();
1916 /* Filter Table Enable */
1917 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1918 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1919 vlnctrl |= IXGBE_VLNCTRL_VFE;
1921 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1923 /* write whatever is in local vfta copy */
1924 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1925 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1929 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1931 struct ixgbe_hwstrip *hwstrip =
1932 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1933 struct ixgbe_rx_queue *rxq;
1935 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1939 IXGBE_SET_HWSTRIP(hwstrip, queue);
1941 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1943 if (queue >= dev->data->nb_rx_queues)
1946 rxq = dev->data->rx_queues[queue];
1949 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1951 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1955 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1957 struct ixgbe_hw *hw =
1958 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1961 PMD_INIT_FUNC_TRACE();
1963 if (hw->mac.type == ixgbe_mac_82598EB) {
1964 /* No queue level support */
1965 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1969 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1970 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1971 ctrl &= ~IXGBE_RXDCTL_VME;
1972 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1974 /* record those setting for HW strip per queue */
1975 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1979 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1981 struct ixgbe_hw *hw =
1982 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1985 PMD_INIT_FUNC_TRACE();
1987 if (hw->mac.type == ixgbe_mac_82598EB) {
1988 /* No queue level supported */
1989 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1993 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1994 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1995 ctrl |= IXGBE_RXDCTL_VME;
1996 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1998 /* record those setting for HW strip per queue */
1999 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2003 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2005 struct ixgbe_hw *hw =
2006 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2009 struct ixgbe_rx_queue *rxq;
2011 PMD_INIT_FUNC_TRACE();
2013 if (hw->mac.type == ixgbe_mac_82598EB) {
2014 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2015 ctrl &= ~IXGBE_VLNCTRL_VME;
2016 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2018 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2019 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2020 rxq = dev->data->rx_queues[i];
2021 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2022 ctrl &= ~IXGBE_RXDCTL_VME;
2023 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2025 /* record those setting for HW strip per queue */
2026 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2032 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2034 struct ixgbe_hw *hw =
2035 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2038 struct ixgbe_rx_queue *rxq;
2040 PMD_INIT_FUNC_TRACE();
2042 if (hw->mac.type == ixgbe_mac_82598EB) {
2043 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2044 ctrl |= IXGBE_VLNCTRL_VME;
2045 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2047 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2048 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2049 rxq = dev->data->rx_queues[i];
2050 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2051 ctrl |= IXGBE_RXDCTL_VME;
2052 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2054 /* record those setting for HW strip per queue */
2055 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2061 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2063 struct ixgbe_hw *hw =
2064 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2067 PMD_INIT_FUNC_TRACE();
2069 /* DMATXCTRL: Geric Double VLAN Disable */
2070 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2071 ctrl &= ~IXGBE_DMATXCTL_GDV;
2072 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2074 /* CTRL_EXT: Global Double VLAN Disable */
2075 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2076 ctrl &= ~IXGBE_EXTENDED_VLAN;
2077 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2082 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2084 struct ixgbe_hw *hw =
2085 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2088 PMD_INIT_FUNC_TRACE();
2090 /* DMATXCTRL: Geric Double VLAN Enable */
2091 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2092 ctrl |= IXGBE_DMATXCTL_GDV;
2093 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2095 /* CTRL_EXT: Global Double VLAN Enable */
2096 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2097 ctrl |= IXGBE_EXTENDED_VLAN;
2098 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2100 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2101 if (hw->mac.type == ixgbe_mac_X550 ||
2102 hw->mac.type == ixgbe_mac_X550EM_x ||
2103 hw->mac.type == ixgbe_mac_X550EM_a) {
2104 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2105 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2106 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2110 * VET EXT field in the EXVET register = 0x8100 by default
2111 * So no need to change. Same to VT field of DMATXCTL register
2116 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2118 if (mask & ETH_VLAN_STRIP_MASK) {
2119 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2120 ixgbe_vlan_hw_strip_enable_all(dev);
2122 ixgbe_vlan_hw_strip_disable_all(dev);
2125 if (mask & ETH_VLAN_FILTER_MASK) {
2126 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2127 ixgbe_vlan_hw_filter_enable(dev);
2129 ixgbe_vlan_hw_filter_disable(dev);
2132 if (mask & ETH_VLAN_EXTEND_MASK) {
2133 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2134 ixgbe_vlan_hw_extend_enable(dev);
2136 ixgbe_vlan_hw_extend_disable(dev);
2141 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2143 struct ixgbe_hw *hw =
2144 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2145 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2146 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2148 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2149 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2153 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2155 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2160 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2163 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2169 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2170 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2176 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2178 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2179 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2180 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2181 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2183 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2184 /* check multi-queue mode */
2185 switch (dev_conf->rxmode.mq_mode) {
2186 case ETH_MQ_RX_VMDQ_DCB:
2187 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2189 case ETH_MQ_RX_VMDQ_DCB_RSS:
2190 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2191 PMD_INIT_LOG(ERR, "SRIOV active,"
2192 " unsupported mq_mode rx %d.",
2193 dev_conf->rxmode.mq_mode);
2196 case ETH_MQ_RX_VMDQ_RSS:
2197 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2198 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2199 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2200 PMD_INIT_LOG(ERR, "SRIOV is active,"
2201 " invalid queue number"
2202 " for VMDQ RSS, allowed"
2203 " value are 1, 2 or 4.");
2207 case ETH_MQ_RX_VMDQ_ONLY:
2208 case ETH_MQ_RX_NONE:
2209 /* if nothing mq mode configure, use default scheme */
2210 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2211 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2212 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2214 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2215 /* SRIOV only works in VMDq enable mode */
2216 PMD_INIT_LOG(ERR, "SRIOV is active,"
2217 " wrong mq_mode rx %d.",
2218 dev_conf->rxmode.mq_mode);
2222 switch (dev_conf->txmode.mq_mode) {
2223 case ETH_MQ_TX_VMDQ_DCB:
2224 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2225 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2227 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2228 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2232 /* check valid queue number */
2233 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2234 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2235 PMD_INIT_LOG(ERR, "SRIOV is active,"
2236 " nb_rx_q=%d nb_tx_q=%d queue number"
2237 " must be less than or equal to %d.",
2239 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2243 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2244 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2248 /* check configuration for vmdb+dcb mode */
2249 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2250 const struct rte_eth_vmdq_dcb_conf *conf;
2252 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2253 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2254 IXGBE_VMDQ_DCB_NB_QUEUES);
2257 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2258 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2259 conf->nb_queue_pools == ETH_32_POOLS)) {
2260 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2261 " nb_queue_pools must be %d or %d.",
2262 ETH_16_POOLS, ETH_32_POOLS);
2266 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2267 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2269 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2270 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2271 IXGBE_VMDQ_DCB_NB_QUEUES);
2274 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2275 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2276 conf->nb_queue_pools == ETH_32_POOLS)) {
2277 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2278 " nb_queue_pools != %d and"
2279 " nb_queue_pools != %d.",
2280 ETH_16_POOLS, ETH_32_POOLS);
2285 /* For DCB mode check our configuration before we go further */
2286 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2287 const struct rte_eth_dcb_rx_conf *conf;
2289 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2290 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2291 IXGBE_DCB_NB_QUEUES);
2294 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2295 if (!(conf->nb_tcs == ETH_4_TCS ||
2296 conf->nb_tcs == ETH_8_TCS)) {
2297 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2298 " and nb_tcs != %d.",
2299 ETH_4_TCS, ETH_8_TCS);
2304 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2305 const struct rte_eth_dcb_tx_conf *conf;
2307 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2308 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2309 IXGBE_DCB_NB_QUEUES);
2312 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2313 if (!(conf->nb_tcs == ETH_4_TCS ||
2314 conf->nb_tcs == ETH_8_TCS)) {
2315 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2316 " and nb_tcs != %d.",
2317 ETH_4_TCS, ETH_8_TCS);
2323 * When DCB/VT is off, maximum number of queues changes,
2324 * except for 82598EB, which remains constant.
2326 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2327 hw->mac.type != ixgbe_mac_82598EB) {
2328 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2330 "Neither VT nor DCB are enabled, "
2332 IXGBE_NONE_MODE_TX_NB_QUEUES);
2341 ixgbe_dev_configure(struct rte_eth_dev *dev)
2343 struct ixgbe_interrupt *intr =
2344 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2345 struct ixgbe_adapter *adapter =
2346 (struct ixgbe_adapter *)dev->data->dev_private;
2349 PMD_INIT_FUNC_TRACE();
2350 /* multipe queue mode checking */
2351 ret = ixgbe_check_mq_mode(dev);
2353 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2358 /* set flag to update link status after init */
2359 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2362 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2363 * allocation or vector Rx preconditions we will reset it.
2365 adapter->rx_bulk_alloc_allowed = true;
2366 adapter->rx_vec_allowed = true;
2372 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2374 struct ixgbe_hw *hw =
2375 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2376 struct ixgbe_interrupt *intr =
2377 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2380 /* only set up it on X550EM_X */
2381 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2382 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2383 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2384 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2385 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2386 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2391 * Configure device link speed and setup link.
2392 * It returns 0 on success.
2395 ixgbe_dev_start(struct rte_eth_dev *dev)
2397 struct ixgbe_hw *hw =
2398 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2399 struct ixgbe_vf_info *vfinfo =
2400 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2401 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2402 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2403 uint32_t intr_vector = 0;
2404 int err, link_up = 0, negotiate = 0;
2409 uint32_t *link_speeds;
2411 PMD_INIT_FUNC_TRACE();
2413 /* IXGBE devices don't support:
2414 * - half duplex (checked afterwards for valid speeds)
2415 * - fixed speed: TODO implement
2417 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2418 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2419 dev->data->port_id);
2423 /* disable uio/vfio intr/eventfd mapping */
2424 rte_intr_disable(intr_handle);
2427 hw->adapter_stopped = 0;
2428 ixgbe_stop_adapter(hw);
2430 /* reinitialize adapter
2431 * this calls reset and start
2433 status = ixgbe_pf_reset_hw(hw);
2436 hw->mac.ops.start_hw(hw);
2437 hw->mac.get_link_status = true;
2439 /* configure PF module if SRIOV enabled */
2440 ixgbe_pf_host_configure(dev);
2442 ixgbe_dev_phy_intr_setup(dev);
2444 /* check and configure queue intr-vector mapping */
2445 if ((rte_intr_cap_multiple(intr_handle) ||
2446 !RTE_ETH_DEV_SRIOV(dev).active) &&
2447 dev->data->dev_conf.intr_conf.rxq != 0) {
2448 intr_vector = dev->data->nb_rx_queues;
2449 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2450 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2451 IXGBE_MAX_INTR_QUEUE_NUM);
2454 if (rte_intr_efd_enable(intr_handle, intr_vector))
2458 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2459 intr_handle->intr_vec =
2460 rte_zmalloc("intr_vec",
2461 dev->data->nb_rx_queues * sizeof(int), 0);
2462 if (intr_handle->intr_vec == NULL) {
2463 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2464 " intr_vec", dev->data->nb_rx_queues);
2469 /* confiugre msix for sleep until rx interrupt */
2470 ixgbe_configure_msix(dev);
2472 /* initialize transmission unit */
2473 ixgbe_dev_tx_init(dev);
2475 /* This can fail when allocating mbufs for descriptor rings */
2476 err = ixgbe_dev_rx_init(dev);
2478 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2482 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2483 ETH_VLAN_EXTEND_MASK;
2484 ixgbe_vlan_offload_set(dev, mask);
2486 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2487 /* Enable vlan filtering for VMDq */
2488 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2491 /* Configure DCB hw */
2492 ixgbe_configure_dcb(dev);
2494 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2495 err = ixgbe_fdir_configure(dev);
2500 /* Restore vf rate limit */
2501 if (vfinfo != NULL) {
2502 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2503 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2504 if (vfinfo[vf].tx_rate[idx] != 0)
2505 rte_pmd_ixgbe_set_vf_rate_limit(
2506 dev->data->port_id, vf,
2507 vfinfo[vf].tx_rate[idx],
2511 ixgbe_restore_statistics_mapping(dev);
2513 err = ixgbe_dev_rxtx_start(dev);
2515 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2519 /* Skip link setup if loopback mode is enabled for 82599. */
2520 if (hw->mac.type == ixgbe_mac_82599EB &&
2521 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2522 goto skip_link_setup;
2524 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2525 err = hw->mac.ops.setup_sfp(hw);
2530 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2531 /* Turn on the copper */
2532 ixgbe_set_phy_power(hw, true);
2534 /* Turn on the laser */
2535 ixgbe_enable_tx_laser(hw);
2538 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2541 dev->data->dev_link.link_status = link_up;
2543 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2547 link_speeds = &dev->data->dev_conf.link_speeds;
2548 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2549 ETH_LINK_SPEED_10G)) {
2550 PMD_INIT_LOG(ERR, "Invalid link setting");
2555 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2556 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2557 IXGBE_LINK_SPEED_82599_AUTONEG :
2558 IXGBE_LINK_SPEED_82598_AUTONEG;
2560 if (*link_speeds & ETH_LINK_SPEED_10G)
2561 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2562 if (*link_speeds & ETH_LINK_SPEED_1G)
2563 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2564 if (*link_speeds & ETH_LINK_SPEED_100M)
2565 speed |= IXGBE_LINK_SPEED_100_FULL;
2568 err = ixgbe_setup_link(hw, speed, link_up);
2574 if (rte_intr_allow_others(intr_handle)) {
2575 /* check if lsc interrupt is enabled */
2576 if (dev->data->dev_conf.intr_conf.lsc != 0)
2577 ixgbe_dev_lsc_interrupt_setup(dev);
2578 ixgbe_dev_macsec_interrupt_setup(dev);
2580 rte_intr_callback_unregister(intr_handle,
2581 ixgbe_dev_interrupt_handler, dev);
2582 if (dev->data->dev_conf.intr_conf.lsc != 0)
2583 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2584 " no intr multiplex");
2587 /* check if rxq interrupt is enabled */
2588 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2589 rte_intr_dp_is_en(intr_handle))
2590 ixgbe_dev_rxq_interrupt_setup(dev);
2592 /* enable uio/vfio intr/eventfd mapping */
2593 rte_intr_enable(intr_handle);
2595 /* resume enabled intr since hw reset */
2596 ixgbe_enable_intr(dev);
2597 ixgbe_l2_tunnel_conf(dev);
2598 ixgbe_filter_restore(dev);
2603 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2604 ixgbe_dev_clear_queues(dev);
2609 * Stop device: disable rx and tx functions to allow for reconfiguring.
2612 ixgbe_dev_stop(struct rte_eth_dev *dev)
2614 struct rte_eth_link link;
2615 struct ixgbe_hw *hw =
2616 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2617 struct ixgbe_vf_info *vfinfo =
2618 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2619 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2620 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2623 PMD_INIT_FUNC_TRACE();
2625 /* disable interrupts */
2626 ixgbe_disable_intr(hw);
2629 ixgbe_pf_reset_hw(hw);
2630 hw->adapter_stopped = 0;
2633 ixgbe_stop_adapter(hw);
2635 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2636 vfinfo[vf].clear_to_send = false;
2638 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2639 /* Turn off the copper */
2640 ixgbe_set_phy_power(hw, false);
2642 /* Turn off the laser */
2643 ixgbe_disable_tx_laser(hw);
2646 ixgbe_dev_clear_queues(dev);
2648 /* Clear stored conf */
2649 dev->data->scattered_rx = 0;
2652 /* Clear recorded link status */
2653 memset(&link, 0, sizeof(link));
2654 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2656 if (!rte_intr_allow_others(intr_handle))
2657 /* resume to the default handler */
2658 rte_intr_callback_register(intr_handle,
2659 ixgbe_dev_interrupt_handler,
2662 /* Clean datapath event and queue/vec mapping */
2663 rte_intr_efd_disable(intr_handle);
2664 if (intr_handle->intr_vec != NULL) {
2665 rte_free(intr_handle->intr_vec);
2666 intr_handle->intr_vec = NULL;
2671 * Set device link up: enable tx.
2674 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2676 struct ixgbe_hw *hw =
2677 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2678 if (hw->mac.type == ixgbe_mac_82599EB) {
2679 #ifdef RTE_NIC_BYPASS
2680 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2681 /* Not suported in bypass mode */
2682 PMD_INIT_LOG(ERR, "Set link up is not supported "
2683 "by device id 0x%x", hw->device_id);
2689 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2690 /* Turn on the copper */
2691 ixgbe_set_phy_power(hw, true);
2693 /* Turn on the laser */
2694 ixgbe_enable_tx_laser(hw);
2701 * Set device link down: disable tx.
2704 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2706 struct ixgbe_hw *hw =
2707 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2708 if (hw->mac.type == ixgbe_mac_82599EB) {
2709 #ifdef RTE_NIC_BYPASS
2710 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2711 /* Not suported in bypass mode */
2712 PMD_INIT_LOG(ERR, "Set link down is not supported "
2713 "by device id 0x%x", hw->device_id);
2719 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2720 /* Turn off the copper */
2721 ixgbe_set_phy_power(hw, false);
2723 /* Turn off the laser */
2724 ixgbe_disable_tx_laser(hw);
2731 * Reest and stop device.
2734 ixgbe_dev_close(struct rte_eth_dev *dev)
2736 struct ixgbe_hw *hw =
2737 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2739 PMD_INIT_FUNC_TRACE();
2741 ixgbe_pf_reset_hw(hw);
2743 ixgbe_dev_stop(dev);
2744 hw->adapter_stopped = 1;
2746 ixgbe_dev_free_queues(dev);
2748 ixgbe_disable_pcie_master(hw);
2750 /* reprogram the RAR[0] in case user changed it. */
2751 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2755 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2756 struct ixgbe_hw_stats *hw_stats,
2757 struct ixgbe_macsec_stats *macsec_stats,
2758 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2759 uint64_t *total_qprc, uint64_t *total_qprdc)
2761 uint32_t bprc, lxon, lxoff, total;
2762 uint32_t delta_gprc = 0;
2764 /* Workaround for RX byte count not including CRC bytes when CRC
2765 * strip is enabled. CRC bytes are removed from counters when crc_strip
2768 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2769 IXGBE_HLREG0_RXCRCSTRP);
2771 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2772 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2773 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2774 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2776 for (i = 0; i < 8; i++) {
2777 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2779 /* global total per queue */
2780 hw_stats->mpc[i] += mp;
2781 /* Running comprehensive total for stats display */
2782 *total_missed_rx += hw_stats->mpc[i];
2783 if (hw->mac.type == ixgbe_mac_82598EB) {
2784 hw_stats->rnbc[i] +=
2785 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2786 hw_stats->pxonrxc[i] +=
2787 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2788 hw_stats->pxoffrxc[i] +=
2789 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2791 hw_stats->pxonrxc[i] +=
2792 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2793 hw_stats->pxoffrxc[i] +=
2794 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2795 hw_stats->pxon2offc[i] +=
2796 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2798 hw_stats->pxontxc[i] +=
2799 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2800 hw_stats->pxofftxc[i] +=
2801 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2803 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2804 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2805 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2806 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2808 delta_gprc += delta_qprc;
2810 hw_stats->qprc[i] += delta_qprc;
2811 hw_stats->qptc[i] += delta_qptc;
2813 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2814 hw_stats->qbrc[i] +=
2815 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2817 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2819 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2820 hw_stats->qbtc[i] +=
2821 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2823 hw_stats->qprdc[i] += delta_qprdc;
2824 *total_qprdc += hw_stats->qprdc[i];
2826 *total_qprc += hw_stats->qprc[i];
2827 *total_qbrc += hw_stats->qbrc[i];
2829 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2830 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2831 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2834 * An errata states that gprc actually counts good + missed packets:
2835 * Workaround to set gprc to summated queue packet receives
2837 hw_stats->gprc = *total_qprc;
2839 if (hw->mac.type != ixgbe_mac_82598EB) {
2840 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2841 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2842 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2843 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2844 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2845 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2846 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2847 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2849 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2850 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2851 /* 82598 only has a counter in the high register */
2852 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2853 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2854 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2856 uint64_t old_tpr = hw_stats->tpr;
2858 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2859 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2862 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2864 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2865 hw_stats->gptc += delta_gptc;
2866 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2867 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2870 * Workaround: mprc hardware is incorrectly counting
2871 * broadcasts, so for now we subtract those.
2873 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2874 hw_stats->bprc += bprc;
2875 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2876 if (hw->mac.type == ixgbe_mac_82598EB)
2877 hw_stats->mprc -= bprc;
2879 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2880 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2881 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2882 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2883 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2884 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2886 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2887 hw_stats->lxontxc += lxon;
2888 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2889 hw_stats->lxofftxc += lxoff;
2890 total = lxon + lxoff;
2892 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2893 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2894 hw_stats->gptc -= total;
2895 hw_stats->mptc -= total;
2896 hw_stats->ptc64 -= total;
2897 hw_stats->gotc -= total * ETHER_MIN_LEN;
2899 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2900 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2901 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2902 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2903 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2904 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2905 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2906 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2907 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2908 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2909 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2910 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2911 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2912 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2913 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2914 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2915 /* Only read FCOE on 82599 */
2916 if (hw->mac.type != ixgbe_mac_82598EB) {
2917 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2918 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2919 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2920 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2921 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2924 /* Flow Director Stats registers */
2925 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2926 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2928 /* MACsec Stats registers */
2929 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2930 macsec_stats->out_pkts_encrypted +=
2931 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2932 macsec_stats->out_pkts_protected +=
2933 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2934 macsec_stats->out_octets_encrypted +=
2935 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2936 macsec_stats->out_octets_protected +=
2937 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2938 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2939 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2940 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2941 macsec_stats->in_pkts_unknownsci +=
2942 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2943 macsec_stats->in_octets_decrypted +=
2944 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2945 macsec_stats->in_octets_validated +=
2946 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2947 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2948 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2949 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2950 for (i = 0; i < 2; i++) {
2951 macsec_stats->in_pkts_ok +=
2952 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2953 macsec_stats->in_pkts_invalid +=
2954 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2955 macsec_stats->in_pkts_notvalid +=
2956 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2958 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2959 macsec_stats->in_pkts_notusingsa +=
2960 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2964 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2967 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2969 struct ixgbe_hw *hw =
2970 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2971 struct ixgbe_hw_stats *hw_stats =
2972 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2973 struct ixgbe_macsec_stats *macsec_stats =
2974 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2975 dev->data->dev_private);
2976 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2979 total_missed_rx = 0;
2984 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2985 &total_qbrc, &total_qprc, &total_qprdc);
2990 /* Fill out the rte_eth_stats statistics structure */
2991 stats->ipackets = total_qprc;
2992 stats->ibytes = total_qbrc;
2993 stats->opackets = hw_stats->gptc;
2994 stats->obytes = hw_stats->gotc;
2996 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2997 stats->q_ipackets[i] = hw_stats->qprc[i];
2998 stats->q_opackets[i] = hw_stats->qptc[i];
2999 stats->q_ibytes[i] = hw_stats->qbrc[i];
3000 stats->q_obytes[i] = hw_stats->qbtc[i];
3001 stats->q_errors[i] = hw_stats->qprdc[i];
3005 stats->imissed = total_missed_rx;
3006 stats->ierrors = hw_stats->crcerrs +
3022 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3024 struct ixgbe_hw_stats *stats =
3025 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3027 /* HW registers are cleared on read */
3028 ixgbe_dev_stats_get(dev, NULL);
3030 /* Reset software totals */
3031 memset(stats, 0, sizeof(*stats));
3034 /* This function calculates the number of xstats based on the current config */
3036 ixgbe_xstats_calc_num(void) {
3037 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3038 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3039 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3042 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3043 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
3045 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3046 unsigned stat, i, count;
3048 if (xstats_names != NULL) {
3051 /* Note: limit >= cnt_stats checked upstream
3052 * in rte_eth_xstats_names()
3055 /* Extended stats from ixgbe_hw_stats */
3056 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3057 snprintf(xstats_names[count].name,
3058 sizeof(xstats_names[count].name),
3060 rte_ixgbe_stats_strings[i].name);
3065 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3066 snprintf(xstats_names[count].name,
3067 sizeof(xstats_names[count].name),
3069 rte_ixgbe_macsec_strings[i].name);
3073 /* RX Priority Stats */
3074 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3075 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3076 snprintf(xstats_names[count].name,
3077 sizeof(xstats_names[count].name),
3078 "rx_priority%u_%s", i,
3079 rte_ixgbe_rxq_strings[stat].name);
3084 /* TX Priority Stats */
3085 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3086 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3087 snprintf(xstats_names[count].name,
3088 sizeof(xstats_names[count].name),
3089 "tx_priority%u_%s", i,
3090 rte_ixgbe_txq_strings[stat].name);
3098 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3099 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3103 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3106 if (xstats_names != NULL)
3107 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3108 snprintf(xstats_names[i].name,
3109 sizeof(xstats_names[i].name),
3110 "%s", rte_ixgbevf_stats_strings[i].name);
3111 return IXGBEVF_NB_XSTATS;
3115 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3118 struct ixgbe_hw *hw =
3119 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3120 struct ixgbe_hw_stats *hw_stats =
3121 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3122 struct ixgbe_macsec_stats *macsec_stats =
3123 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3124 dev->data->dev_private);
3125 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3126 unsigned i, stat, count = 0;
3128 count = ixgbe_xstats_calc_num();
3133 total_missed_rx = 0;
3138 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3139 &total_qbrc, &total_qprc, &total_qprdc);
3141 /* If this is a reset xstats is NULL, and we have cleared the
3142 * registers by reading them.
3147 /* Extended stats from ixgbe_hw_stats */
3149 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3150 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3151 rte_ixgbe_stats_strings[i].offset);
3152 xstats[count].id = count;
3157 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3158 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3159 rte_ixgbe_macsec_strings[i].offset);
3160 xstats[count].id = count;
3164 /* RX Priority Stats */
3165 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3166 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3167 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3168 rte_ixgbe_rxq_strings[stat].offset +
3169 (sizeof(uint64_t) * i));
3170 xstats[count].id = count;
3175 /* TX Priority Stats */
3176 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3177 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3178 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3179 rte_ixgbe_txq_strings[stat].offset +
3180 (sizeof(uint64_t) * i));
3181 xstats[count].id = count;
3189 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3191 struct ixgbe_hw_stats *stats =
3192 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3193 struct ixgbe_macsec_stats *macsec_stats =
3194 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3195 dev->data->dev_private);
3197 unsigned count = ixgbe_xstats_calc_num();
3199 /* HW registers are cleared on read */
3200 ixgbe_dev_xstats_get(dev, NULL, count);
3202 /* Reset software totals */
3203 memset(stats, 0, sizeof(*stats));
3204 memset(macsec_stats, 0, sizeof(*macsec_stats));
3208 ixgbevf_update_stats(struct rte_eth_dev *dev)
3210 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3211 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3212 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3214 /* Good Rx packet, include VF loopback */
3215 UPDATE_VF_STAT(IXGBE_VFGPRC,
3216 hw_stats->last_vfgprc, hw_stats->vfgprc);
3218 /* Good Rx octets, include VF loopback */
3219 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3220 hw_stats->last_vfgorc, hw_stats->vfgorc);
3222 /* Good Tx packet, include VF loopback */
3223 UPDATE_VF_STAT(IXGBE_VFGPTC,
3224 hw_stats->last_vfgptc, hw_stats->vfgptc);
3226 /* Good Tx octets, include VF loopback */
3227 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3228 hw_stats->last_vfgotc, hw_stats->vfgotc);
3230 /* Rx Multicst Packet */
3231 UPDATE_VF_STAT(IXGBE_VFMPRC,
3232 hw_stats->last_vfmprc, hw_stats->vfmprc);
3236 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3239 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3240 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3243 if (n < IXGBEVF_NB_XSTATS)
3244 return IXGBEVF_NB_XSTATS;
3246 ixgbevf_update_stats(dev);
3251 /* Extended stats */
3252 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3254 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3255 rte_ixgbevf_stats_strings[i].offset);
3258 return IXGBEVF_NB_XSTATS;
3262 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3264 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3265 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3267 ixgbevf_update_stats(dev);
3272 stats->ipackets = hw_stats->vfgprc;
3273 stats->ibytes = hw_stats->vfgorc;
3274 stats->opackets = hw_stats->vfgptc;
3275 stats->obytes = hw_stats->vfgotc;
3279 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3281 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3282 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3284 /* Sync HW register to the last stats */
3285 ixgbevf_dev_stats_get(dev, NULL);
3287 /* reset HW current stats*/
3288 hw_stats->vfgprc = 0;
3289 hw_stats->vfgorc = 0;
3290 hw_stats->vfgptc = 0;
3291 hw_stats->vfgotc = 0;
3295 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3297 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3298 u16 eeprom_verh, eeprom_verl;
3302 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3303 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3305 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3306 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3308 ret += 1; /* add the size of '\0' */
3309 if (fw_size < (u32)ret)
3316 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3318 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3319 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3320 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3322 dev_info->pci_dev = pci_dev;
3323 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3324 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3325 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3327 * When DCB/VT is off, maximum number of queues changes,
3328 * except for 82598EB, which remains constant.
3330 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3331 hw->mac.type != ixgbe_mac_82598EB)
3332 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3334 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3335 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3336 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3337 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3338 dev_info->max_vfs = pci_dev->max_vfs;
3339 if (hw->mac.type == ixgbe_mac_82598EB)
3340 dev_info->max_vmdq_pools = ETH_16_POOLS;
3342 dev_info->max_vmdq_pools = ETH_64_POOLS;
3343 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3344 dev_info->rx_offload_capa =
3345 DEV_RX_OFFLOAD_VLAN_STRIP |
3346 DEV_RX_OFFLOAD_IPV4_CKSUM |
3347 DEV_RX_OFFLOAD_UDP_CKSUM |
3348 DEV_RX_OFFLOAD_TCP_CKSUM;
3351 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3354 if ((hw->mac.type == ixgbe_mac_82599EB ||
3355 hw->mac.type == ixgbe_mac_X540) &&
3356 !RTE_ETH_DEV_SRIOV(dev).active)
3357 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3359 if (hw->mac.type == ixgbe_mac_82599EB ||
3360 hw->mac.type == ixgbe_mac_X540)
3361 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3363 if (hw->mac.type == ixgbe_mac_X550 ||
3364 hw->mac.type == ixgbe_mac_X550EM_x ||
3365 hw->mac.type == ixgbe_mac_X550EM_a)
3366 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3368 dev_info->tx_offload_capa =
3369 DEV_TX_OFFLOAD_VLAN_INSERT |
3370 DEV_TX_OFFLOAD_IPV4_CKSUM |
3371 DEV_TX_OFFLOAD_UDP_CKSUM |
3372 DEV_TX_OFFLOAD_TCP_CKSUM |
3373 DEV_TX_OFFLOAD_SCTP_CKSUM |
3374 DEV_TX_OFFLOAD_TCP_TSO;
3376 if (hw->mac.type == ixgbe_mac_82599EB ||
3377 hw->mac.type == ixgbe_mac_X540)
3378 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3380 if (hw->mac.type == ixgbe_mac_X550 ||
3381 hw->mac.type == ixgbe_mac_X550EM_x ||
3382 hw->mac.type == ixgbe_mac_X550EM_a)
3383 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3385 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3387 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3388 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3389 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3391 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3395 dev_info->default_txconf = (struct rte_eth_txconf) {
3397 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3398 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3399 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3401 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3402 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3403 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3404 ETH_TXQ_FLAGS_NOOFFLOADS,
3407 dev_info->rx_desc_lim = rx_desc_lim;
3408 dev_info->tx_desc_lim = tx_desc_lim;
3410 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3411 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3412 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3414 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3415 if (hw->mac.type == ixgbe_mac_X540 ||
3416 hw->mac.type == ixgbe_mac_X540_vf ||
3417 hw->mac.type == ixgbe_mac_X550 ||
3418 hw->mac.type == ixgbe_mac_X550_vf) {
3419 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3423 static const uint32_t *
3424 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3426 static const uint32_t ptypes[] = {
3427 /* For non-vec functions,
3428 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3429 * for vec functions,
3430 * refers to _recv_raw_pkts_vec().
3434 RTE_PTYPE_L3_IPV4_EXT,
3436 RTE_PTYPE_L3_IPV6_EXT,
3440 RTE_PTYPE_TUNNEL_IP,
3441 RTE_PTYPE_INNER_L3_IPV6,
3442 RTE_PTYPE_INNER_L3_IPV6_EXT,
3443 RTE_PTYPE_INNER_L4_TCP,
3444 RTE_PTYPE_INNER_L4_UDP,
3448 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3449 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3450 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3451 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3457 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3458 struct rte_eth_dev_info *dev_info)
3460 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3461 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3463 dev_info->pci_dev = pci_dev;
3464 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3465 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3466 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3467 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3468 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3469 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3470 dev_info->max_vfs = pci_dev->max_vfs;
3471 if (hw->mac.type == ixgbe_mac_82598EB)
3472 dev_info->max_vmdq_pools = ETH_16_POOLS;
3474 dev_info->max_vmdq_pools = ETH_64_POOLS;
3475 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3476 DEV_RX_OFFLOAD_IPV4_CKSUM |
3477 DEV_RX_OFFLOAD_UDP_CKSUM |
3478 DEV_RX_OFFLOAD_TCP_CKSUM;
3479 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3480 DEV_TX_OFFLOAD_IPV4_CKSUM |
3481 DEV_TX_OFFLOAD_UDP_CKSUM |
3482 DEV_TX_OFFLOAD_TCP_CKSUM |
3483 DEV_TX_OFFLOAD_SCTP_CKSUM |
3484 DEV_TX_OFFLOAD_TCP_TSO;
3486 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3488 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3489 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3490 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3492 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3496 dev_info->default_txconf = (struct rte_eth_txconf) {
3498 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3499 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3500 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3502 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3503 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3504 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3505 ETH_TXQ_FLAGS_NOOFFLOADS,
3508 dev_info->rx_desc_lim = rx_desc_lim;
3509 dev_info->tx_desc_lim = tx_desc_lim;
3512 /* return 0 means link status changed, -1 means not changed */
3514 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3516 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3517 struct rte_eth_link link, old;
3518 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3522 link.link_status = ETH_LINK_DOWN;
3523 link.link_speed = 0;
3524 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3525 memset(&old, 0, sizeof(old));
3526 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3528 hw->mac.get_link_status = true;
3530 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3531 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3532 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3534 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3537 link.link_speed = ETH_SPEED_NUM_100M;
3538 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3539 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3540 if (link.link_status == old.link_status)
3546 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3547 if (link.link_status == old.link_status)
3551 link.link_status = ETH_LINK_UP;
3552 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3554 switch (link_speed) {
3556 case IXGBE_LINK_SPEED_UNKNOWN:
3557 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3558 link.link_speed = ETH_SPEED_NUM_100M;
3561 case IXGBE_LINK_SPEED_100_FULL:
3562 link.link_speed = ETH_SPEED_NUM_100M;
3565 case IXGBE_LINK_SPEED_1GB_FULL:
3566 link.link_speed = ETH_SPEED_NUM_1G;
3569 case IXGBE_LINK_SPEED_10GB_FULL:
3570 link.link_speed = ETH_SPEED_NUM_10G;
3573 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3575 if (link.link_status == old.link_status)
3582 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3584 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3587 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3588 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3589 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3593 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3595 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3598 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3599 fctrl &= (~IXGBE_FCTRL_UPE);
3600 if (dev->data->all_multicast == 1)
3601 fctrl |= IXGBE_FCTRL_MPE;
3603 fctrl &= (~IXGBE_FCTRL_MPE);
3604 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3608 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3610 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3613 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3614 fctrl |= IXGBE_FCTRL_MPE;
3615 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3619 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3621 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3624 if (dev->data->promiscuous == 1)
3625 return; /* must remain in all_multicast mode */
3627 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3628 fctrl &= (~IXGBE_FCTRL_MPE);
3629 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3633 * It clears the interrupt causes and enables the interrupt.
3634 * It will be called once only during nic initialized.
3637 * Pointer to struct rte_eth_dev.
3640 * - On success, zero.
3641 * - On failure, a negative value.
3644 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3646 struct ixgbe_interrupt *intr =
3647 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3649 ixgbe_dev_link_status_print(dev);
3650 intr->mask |= IXGBE_EICR_LSC;
3656 * It clears the interrupt causes and enables the interrupt.
3657 * It will be called once only during nic initialized.
3660 * Pointer to struct rte_eth_dev.
3663 * - On success, zero.
3664 * - On failure, a negative value.
3667 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3669 struct ixgbe_interrupt *intr =
3670 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3672 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3678 * It clears the interrupt causes and enables the interrupt.
3679 * It will be called once only during nic initialized.
3682 * Pointer to struct rte_eth_dev.
3685 * - On success, zero.
3686 * - On failure, a negative value.
3689 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3691 struct ixgbe_interrupt *intr =
3692 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3694 intr->mask |= IXGBE_EICR_LINKSEC;
3700 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3703 * Pointer to struct rte_eth_dev.
3706 * - On success, zero.
3707 * - On failure, a negative value.
3710 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3713 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3714 struct ixgbe_interrupt *intr =
3715 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3717 /* clear all cause mask */
3718 ixgbe_disable_intr(hw);
3720 /* read-on-clear nic registers here */
3721 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3722 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3726 /* set flag for async link update */
3727 if (eicr & IXGBE_EICR_LSC)
3728 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3730 if (eicr & IXGBE_EICR_MAILBOX)
3731 intr->flags |= IXGBE_FLAG_MAILBOX;
3733 if (eicr & IXGBE_EICR_LINKSEC)
3734 intr->flags |= IXGBE_FLAG_MACSEC;
3736 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3737 hw->phy.type == ixgbe_phy_x550em_ext_t &&
3738 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3739 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3745 * It gets and then prints the link status.
3748 * Pointer to struct rte_eth_dev.
3751 * - On success, zero.
3752 * - On failure, a negative value.
3755 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3757 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3758 struct rte_eth_link link;
3760 memset(&link, 0, sizeof(link));
3761 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3762 if (link.link_status) {
3763 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3764 (int)(dev->data->port_id),
3765 (unsigned)link.link_speed,
3766 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3767 "full-duplex" : "half-duplex");
3769 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3770 (int)(dev->data->port_id));
3772 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3773 pci_dev->addr.domain,
3775 pci_dev->addr.devid,
3776 pci_dev->addr.function);
3780 * It executes link_update after knowing an interrupt occurred.
3783 * Pointer to struct rte_eth_dev.
3786 * - On success, zero.
3787 * - On failure, a negative value.
3790 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3791 struct rte_intr_handle *intr_handle)
3793 struct ixgbe_interrupt *intr =
3794 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3796 struct rte_eth_link link;
3797 struct ixgbe_hw *hw =
3798 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3800 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3802 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3803 ixgbe_pf_mbx_process(dev);
3804 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3807 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3808 ixgbe_handle_lasi(hw);
3809 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3812 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3813 /* get the link status before link update, for predicting later */
3814 memset(&link, 0, sizeof(link));
3815 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3817 ixgbe_dev_link_update(dev, 0);
3820 if (!link.link_status)
3821 /* handle it 1 sec later, wait it being stable */
3822 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3823 /* likely to down */
3825 /* handle it 4 sec later, wait it being stable */
3826 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3828 ixgbe_dev_link_status_print(dev);
3829 intr->mask_original = intr->mask;
3830 /* only disable lsc interrupt */
3831 intr->mask &= ~IXGBE_EIMS_LSC;
3832 if (rte_eal_alarm_set(timeout * 1000,
3833 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3834 PMD_DRV_LOG(ERR, "Error setting alarm");
3836 intr->mask = intr->mask_original;
3839 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3840 ixgbe_enable_intr(dev);
3841 rte_intr_enable(intr_handle);
3847 * Interrupt handler which shall be registered for alarm callback for delayed
3848 * handling specific interrupt to wait for the stable nic state. As the
3849 * NIC interrupt state is not stable for ixgbe after link is just down,
3850 * it needs to wait 4 seconds to get the stable status.
3853 * Pointer to interrupt handle.
3855 * The address of parameter (struct rte_eth_dev *) regsitered before.
3861 ixgbe_dev_interrupt_delayed_handler(void *param)
3863 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3864 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3865 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3866 struct ixgbe_interrupt *intr =
3867 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3868 struct ixgbe_hw *hw =
3869 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3872 ixgbe_disable_intr(hw);
3874 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3875 if (eicr & IXGBE_EICR_MAILBOX)
3876 ixgbe_pf_mbx_process(dev);
3878 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3879 ixgbe_handle_lasi(hw);
3880 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3883 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3884 ixgbe_dev_link_update(dev, 0);
3885 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3886 ixgbe_dev_link_status_print(dev);
3887 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3890 if (intr->flags & IXGBE_FLAG_MACSEC) {
3891 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3893 intr->flags &= ~IXGBE_FLAG_MACSEC;
3896 /* restore original mask */
3897 intr->mask = intr->mask_original;
3898 intr->mask_original = 0;
3900 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3901 ixgbe_enable_intr(dev);
3902 rte_intr_enable(intr_handle);
3906 * Interrupt handler triggered by NIC for handling
3907 * specific interrupt.
3910 * Pointer to interrupt handle.
3912 * The address of parameter (struct rte_eth_dev *) regsitered before.
3918 ixgbe_dev_interrupt_handler(void *param)
3920 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3922 ixgbe_dev_interrupt_get_status(dev);
3923 ixgbe_dev_interrupt_action(dev, dev->intr_handle);
3927 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3929 struct ixgbe_hw *hw;
3931 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3932 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3936 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3938 struct ixgbe_hw *hw;
3940 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3941 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3945 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3947 struct ixgbe_hw *hw;
3953 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3955 fc_conf->pause_time = hw->fc.pause_time;
3956 fc_conf->high_water = hw->fc.high_water[0];
3957 fc_conf->low_water = hw->fc.low_water[0];
3958 fc_conf->send_xon = hw->fc.send_xon;
3959 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3962 * Return rx_pause status according to actual setting of
3965 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3966 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3972 * Return tx_pause status according to actual setting of
3975 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3976 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3981 if (rx_pause && tx_pause)
3982 fc_conf->mode = RTE_FC_FULL;
3984 fc_conf->mode = RTE_FC_RX_PAUSE;
3986 fc_conf->mode = RTE_FC_TX_PAUSE;
3988 fc_conf->mode = RTE_FC_NONE;
3994 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3996 struct ixgbe_hw *hw;
3998 uint32_t rx_buf_size;
3999 uint32_t max_high_water;
4001 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4008 PMD_INIT_FUNC_TRACE();
4010 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4011 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4012 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4015 * At least reserve one Ethernet frame for watermark
4016 * high_water/low_water in kilo bytes for ixgbe
4018 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4019 if ((fc_conf->high_water > max_high_water) ||
4020 (fc_conf->high_water < fc_conf->low_water)) {
4021 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4022 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4026 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4027 hw->fc.pause_time = fc_conf->pause_time;
4028 hw->fc.high_water[0] = fc_conf->high_water;
4029 hw->fc.low_water[0] = fc_conf->low_water;
4030 hw->fc.send_xon = fc_conf->send_xon;
4031 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4033 err = ixgbe_fc_enable(hw);
4035 /* Not negotiated is not an error case */
4036 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4038 /* check if we want to forward MAC frames - driver doesn't have native
4039 * capability to do that, so we'll write the registers ourselves */
4041 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4043 /* set or clear MFLCN.PMCF bit depending on configuration */
4044 if (fc_conf->mac_ctrl_frame_fwd != 0)
4045 mflcn |= IXGBE_MFLCN_PMCF;
4047 mflcn &= ~IXGBE_MFLCN_PMCF;
4049 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4050 IXGBE_WRITE_FLUSH(hw);
4055 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4060 * ixgbe_pfc_enable_generic - Enable flow control
4061 * @hw: pointer to hardware structure
4062 * @tc_num: traffic class number
4063 * Enable flow control according to the current settings.
4066 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4069 uint32_t mflcn_reg, fccfg_reg;
4071 uint32_t fcrtl, fcrth;
4075 /* Validate the water mark configuration */
4076 if (!hw->fc.pause_time) {
4077 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4081 /* Low water mark of zero causes XOFF floods */
4082 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4083 /* High/Low water can not be 0 */
4084 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4085 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4086 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4090 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4091 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4092 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4096 /* Negotiate the fc mode to use */
4097 ixgbe_fc_autoneg(hw);
4099 /* Disable any previous flow control settings */
4100 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4101 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4103 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4104 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4106 switch (hw->fc.current_mode) {
4109 * If the count of enabled RX Priority Flow control >1,
4110 * and the TX pause can not be disabled
4113 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4114 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4115 if (reg & IXGBE_FCRTH_FCEN)
4119 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4121 case ixgbe_fc_rx_pause:
4123 * Rx Flow control is enabled and Tx Flow control is
4124 * disabled by software override. Since there really
4125 * isn't a way to advertise that we are capable of RX
4126 * Pause ONLY, we will advertise that we support both
4127 * symmetric and asymmetric Rx PAUSE. Later, we will
4128 * disable the adapter's ability to send PAUSE frames.
4130 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4132 * If the count of enabled RX Priority Flow control >1,
4133 * and the TX pause can not be disabled
4136 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4137 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4138 if (reg & IXGBE_FCRTH_FCEN)
4142 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4144 case ixgbe_fc_tx_pause:
4146 * Tx Flow control is enabled, and Rx Flow control is
4147 * disabled by software override.
4149 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4152 /* Flow control (both Rx and Tx) is enabled by SW override. */
4153 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4154 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4157 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4158 ret_val = IXGBE_ERR_CONFIG;
4162 /* Set 802.3x based flow control settings. */
4163 mflcn_reg |= IXGBE_MFLCN_DPF;
4164 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4165 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4167 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4168 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4169 hw->fc.high_water[tc_num]) {
4170 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4171 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4172 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4174 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4176 * In order to prevent Tx hangs when the internal Tx
4177 * switch is enabled we must set the high water mark
4178 * to the maximum FCRTH value. This allows the Tx
4179 * switch to function even under heavy Rx workloads.
4181 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4183 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4185 /* Configure pause time (2 TCs per register) */
4186 reg = hw->fc.pause_time * 0x00010001;
4187 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4188 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4190 /* Configure flow control refresh threshold value */
4191 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4198 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4200 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4201 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4203 if (hw->mac.type != ixgbe_mac_82598EB) {
4204 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4210 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4213 uint32_t rx_buf_size;
4214 uint32_t max_high_water;
4216 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4217 struct ixgbe_hw *hw =
4218 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4219 struct ixgbe_dcb_config *dcb_config =
4220 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4222 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4229 PMD_INIT_FUNC_TRACE();
4231 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4232 tc_num = map[pfc_conf->priority];
4233 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4234 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4236 * At least reserve one Ethernet frame for watermark
4237 * high_water/low_water in kilo bytes for ixgbe
4239 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4240 if ((pfc_conf->fc.high_water > max_high_water) ||
4241 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4242 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4243 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4247 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4248 hw->fc.pause_time = pfc_conf->fc.pause_time;
4249 hw->fc.send_xon = pfc_conf->fc.send_xon;
4250 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4251 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4253 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4255 /* Not negotiated is not an error case */
4256 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4259 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4264 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4265 struct rte_eth_rss_reta_entry64 *reta_conf,
4268 uint16_t i, sp_reta_size;
4271 uint16_t idx, shift;
4272 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4275 PMD_INIT_FUNC_TRACE();
4277 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4278 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4283 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4284 if (reta_size != sp_reta_size) {
4285 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4286 "(%d) doesn't match the number hardware can supported "
4287 "(%d)", reta_size, sp_reta_size);
4291 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4292 idx = i / RTE_RETA_GROUP_SIZE;
4293 shift = i % RTE_RETA_GROUP_SIZE;
4294 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4298 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4299 if (mask == IXGBE_4_BIT_MASK)
4302 r = IXGBE_READ_REG(hw, reta_reg);
4303 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4304 if (mask & (0x1 << j))
4305 reta |= reta_conf[idx].reta[shift + j] <<
4308 reta |= r & (IXGBE_8_BIT_MASK <<
4311 IXGBE_WRITE_REG(hw, reta_reg, reta);
4318 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4319 struct rte_eth_rss_reta_entry64 *reta_conf,
4322 uint16_t i, sp_reta_size;
4325 uint16_t idx, shift;
4326 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4329 PMD_INIT_FUNC_TRACE();
4330 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4331 if (reta_size != sp_reta_size) {
4332 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4333 "(%d) doesn't match the number hardware can supported "
4334 "(%d)", reta_size, sp_reta_size);
4338 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4339 idx = i / RTE_RETA_GROUP_SIZE;
4340 shift = i % RTE_RETA_GROUP_SIZE;
4341 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4346 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4347 reta = IXGBE_READ_REG(hw, reta_reg);
4348 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4349 if (mask & (0x1 << j))
4350 reta_conf[idx].reta[shift + j] =
4351 ((reta >> (CHAR_BIT * j)) &
4360 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4361 uint32_t index, uint32_t pool)
4363 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4364 uint32_t enable_addr = 1;
4366 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4370 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4372 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4374 ixgbe_clear_rar(hw, index);
4378 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4380 ixgbe_remove_rar(dev, 0);
4382 ixgbe_add_rar(dev, addr, 0, 0);
4386 is_device_supported(struct rte_eth_dev *dev, struct eth_driver *drv)
4388 if (strcmp(dev->driver->pci_drv.driver.name,
4389 drv->pci_drv.driver.name))
4396 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4397 struct ether_addr *mac_addr)
4399 struct ixgbe_hw *hw;
4400 struct ixgbe_vf_info *vfinfo;
4402 uint8_t *new_mac = (uint8_t *)(mac_addr);
4403 struct rte_eth_dev *dev;
4404 struct rte_pci_device *pci_dev;
4406 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4408 dev = &rte_eth_devices[port];
4409 pci_dev = IXGBE_DEV_TO_PCI(dev);
4411 if (!is_device_supported(dev, &rte_ixgbe_pmd))
4414 if (vf >= pci_dev->max_vfs)
4417 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4418 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4419 rar_entry = hw->mac.num_rar_entries - (vf + 1);
4421 if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4422 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4424 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4431 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4435 struct ixgbe_hw *hw;
4436 struct rte_eth_dev_info dev_info;
4437 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4439 ixgbe_dev_info_get(dev, &dev_info);
4441 /* check that mtu is within the allowed range */
4442 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4445 /* refuse mtu that requires the support of scattered packets when this
4446 * feature has not been enabled before.
4448 if (!dev->data->scattered_rx &&
4449 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4450 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4453 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4454 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4456 /* switch to jumbo mode if needed */
4457 if (frame_size > ETHER_MAX_LEN) {
4458 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4459 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4461 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4462 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4464 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4466 /* update max frame size */
4467 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4469 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4470 maxfrs &= 0x0000FFFF;
4471 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4472 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4478 * Virtual Function operations
4481 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4483 PMD_INIT_FUNC_TRACE();
4485 /* Clear interrupt mask to stop from interrupts being generated */
4486 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4488 IXGBE_WRITE_FLUSH(hw);
4492 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4494 PMD_INIT_FUNC_TRACE();
4496 /* VF enable interrupt autoclean */
4497 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4498 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4499 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4501 IXGBE_WRITE_FLUSH(hw);
4505 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4507 struct rte_eth_conf *conf = &dev->data->dev_conf;
4508 struct ixgbe_adapter *adapter =
4509 (struct ixgbe_adapter *)dev->data->dev_private;
4511 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4512 dev->data->port_id);
4515 * VF has no ability to enable/disable HW CRC
4516 * Keep the persistent behavior the same as Host PF
4518 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4519 if (!conf->rxmode.hw_strip_crc) {
4520 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4521 conf->rxmode.hw_strip_crc = 1;
4524 if (conf->rxmode.hw_strip_crc) {
4525 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4526 conf->rxmode.hw_strip_crc = 0;
4531 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4532 * allocation or vector Rx preconditions we will reset it.
4534 adapter->rx_bulk_alloc_allowed = true;
4535 adapter->rx_vec_allowed = true;
4541 ixgbevf_dev_start(struct rte_eth_dev *dev)
4543 struct ixgbe_hw *hw =
4544 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4545 uint32_t intr_vector = 0;
4546 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4547 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4551 PMD_INIT_FUNC_TRACE();
4553 hw->mac.ops.reset_hw(hw);
4554 hw->mac.get_link_status = true;
4556 /* negotiate mailbox API version to use with the PF. */
4557 ixgbevf_negotiate_api(hw);
4559 ixgbevf_dev_tx_init(dev);
4561 /* This can fail when allocating mbufs for descriptor rings */
4562 err = ixgbevf_dev_rx_init(dev);
4564 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4565 ixgbe_dev_clear_queues(dev);
4570 ixgbevf_set_vfta_all(dev, 1);
4573 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4574 ETH_VLAN_EXTEND_MASK;
4575 ixgbevf_vlan_offload_set(dev, mask);
4577 ixgbevf_dev_rxtx_start(dev);
4579 /* check and configure queue intr-vector mapping */
4580 if (dev->data->dev_conf.intr_conf.rxq != 0) {
4581 intr_vector = dev->data->nb_rx_queues;
4582 if (rte_intr_efd_enable(intr_handle, intr_vector))
4586 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4587 intr_handle->intr_vec =
4588 rte_zmalloc("intr_vec",
4589 dev->data->nb_rx_queues * sizeof(int), 0);
4590 if (intr_handle->intr_vec == NULL) {
4591 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4592 " intr_vec", dev->data->nb_rx_queues);
4596 ixgbevf_configure_msix(dev);
4598 rte_intr_enable(intr_handle);
4600 /* Re-enable interrupt for VF */
4601 ixgbevf_intr_enable(hw);
4607 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4609 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4610 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4611 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4613 PMD_INIT_FUNC_TRACE();
4615 ixgbevf_intr_disable(hw);
4617 hw->adapter_stopped = 1;
4618 ixgbe_stop_adapter(hw);
4621 * Clear what we set, but we still keep shadow_vfta to
4622 * restore after device starts
4624 ixgbevf_set_vfta_all(dev, 0);
4626 /* Clear stored conf */
4627 dev->data->scattered_rx = 0;
4629 ixgbe_dev_clear_queues(dev);
4631 /* Clean datapath event and queue/vec mapping */
4632 rte_intr_efd_disable(intr_handle);
4633 if (intr_handle->intr_vec != NULL) {
4634 rte_free(intr_handle->intr_vec);
4635 intr_handle->intr_vec = NULL;
4640 ixgbevf_dev_close(struct rte_eth_dev *dev)
4642 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4644 PMD_INIT_FUNC_TRACE();
4648 ixgbevf_dev_stop(dev);
4650 ixgbe_dev_free_queues(dev);
4653 * Remove the VF MAC address ro ensure
4654 * that the VF traffic goes to the PF
4655 * after stop, close and detach of the VF
4657 ixgbevf_remove_mac_addr(dev, 0);
4660 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4662 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4663 struct ixgbe_vfta *shadow_vfta =
4664 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4665 int i = 0, j = 0, vfta = 0, mask = 1;
4667 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4668 vfta = shadow_vfta->vfta[i];
4671 for (j = 0; j < 32; j++) {
4673 ixgbe_set_vfta(hw, (i<<5)+j, 0,
4683 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4685 struct ixgbe_hw *hw =
4686 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4687 struct ixgbe_vfta *shadow_vfta =
4688 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4689 uint32_t vid_idx = 0;
4690 uint32_t vid_bit = 0;
4693 PMD_INIT_FUNC_TRACE();
4695 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4696 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4698 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4701 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4702 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4704 /* Save what we set and retore it after device reset */
4706 shadow_vfta->vfta[vid_idx] |= vid_bit;
4708 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4714 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4716 struct ixgbe_hw *hw =
4717 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4720 PMD_INIT_FUNC_TRACE();
4722 if (queue >= hw->mac.max_rx_queues)
4725 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4727 ctrl |= IXGBE_RXDCTL_VME;
4729 ctrl &= ~IXGBE_RXDCTL_VME;
4730 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4732 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4736 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4738 struct ixgbe_hw *hw =
4739 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4743 /* VF function only support hw strip feature, others are not support */
4744 if (mask & ETH_VLAN_STRIP_MASK) {
4745 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4747 for (i = 0; i < hw->mac.max_rx_queues; i++)
4748 ixgbevf_vlan_strip_queue_set(dev, i, on);
4753 ixgbe_vt_check(struct ixgbe_hw *hw)
4757 /* if Virtualization Technology is enabled */
4758 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4759 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4760 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
4768 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4770 uint32_t vector = 0;
4772 switch (hw->mac.mc_filter_type) {
4773 case 0: /* use bits [47:36] of the address */
4774 vector = ((uc_addr->addr_bytes[4] >> 4) |
4775 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4777 case 1: /* use bits [46:35] of the address */
4778 vector = ((uc_addr->addr_bytes[4] >> 3) |
4779 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4781 case 2: /* use bits [45:34] of the address */
4782 vector = ((uc_addr->addr_bytes[4] >> 2) |
4783 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4785 case 3: /* use bits [43:32] of the address */
4786 vector = ((uc_addr->addr_bytes[4]) |
4787 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4789 default: /* Invalid mc_filter_type */
4793 /* vector can only be 12-bits or boundary will be exceeded */
4799 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4807 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4808 const uint32_t ixgbe_uta_bit_shift = 5;
4809 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4810 const uint32_t bit1 = 0x1;
4812 struct ixgbe_hw *hw =
4813 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4814 struct ixgbe_uta_info *uta_info =
4815 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4817 /* The UTA table only exists on 82599 hardware and newer */
4818 if (hw->mac.type < ixgbe_mac_82599EB)
4821 vector = ixgbe_uta_vector(hw, mac_addr);
4822 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4823 uta_shift = vector & ixgbe_uta_bit_mask;
4825 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4829 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4831 uta_info->uta_in_use++;
4832 reg_val |= (bit1 << uta_shift);
4833 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4835 uta_info->uta_in_use--;
4836 reg_val &= ~(bit1 << uta_shift);
4837 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4840 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4842 if (uta_info->uta_in_use > 0)
4843 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4844 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4846 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4852 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4855 struct ixgbe_hw *hw =
4856 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4857 struct ixgbe_uta_info *uta_info =
4858 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4860 /* The UTA table only exists on 82599 hardware and newer */
4861 if (hw->mac.type < ixgbe_mac_82599EB)
4865 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4866 uta_info->uta_shadow[i] = ~0;
4867 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4870 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4871 uta_info->uta_shadow[i] = 0;
4872 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4880 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4882 uint32_t new_val = orig_val;
4884 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4885 new_val |= IXGBE_VMOLR_AUPE;
4886 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4887 new_val |= IXGBE_VMOLR_ROMPE;
4888 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4889 new_val |= IXGBE_VMOLR_ROPE;
4890 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4891 new_val |= IXGBE_VMOLR_BAM;
4892 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4893 new_val |= IXGBE_VMOLR_MPE;
4899 rte_pmd_ixgbe_ping_vf(uint8_t port, uint16_t vf)
4901 struct ixgbe_hw *hw;
4902 struct ixgbe_vf_info *vfinfo;
4903 struct rte_eth_dev *dev;
4904 struct rte_pci_device *pci_dev;
4907 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4909 dev = &rte_eth_devices[port];
4910 pci_dev = IXGBE_DEV_TO_PCI(dev);
4912 if (!is_device_supported(dev, &rte_ixgbe_pmd))
4915 if (vf >= pci_dev->max_vfs)
4918 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4919 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4921 ctrl = IXGBE_PF_CONTROL_MSG;
4922 if (vfinfo[vf].clear_to_send)
4923 ctrl |= IXGBE_VT_MSGTYPE_CTS;
4925 ixgbe_write_mbx(hw, &ctrl, 1, vf);
4931 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4933 struct ixgbe_hw *hw;
4934 struct ixgbe_mac_info *mac;
4935 struct rte_eth_dev *dev;
4936 struct rte_pci_device *pci_dev;
4938 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4940 dev = &rte_eth_devices[port];
4941 pci_dev = IXGBE_DEV_TO_PCI(dev);
4943 if (!is_device_supported(dev, &rte_ixgbe_pmd))
4946 if (vf >= pci_dev->max_vfs)
4952 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4955 mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4961 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4963 struct ixgbe_hw *hw;
4964 struct ixgbe_mac_info *mac;
4965 struct rte_eth_dev *dev;
4966 struct rte_pci_device *pci_dev;
4968 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4970 dev = &rte_eth_devices[port];
4971 pci_dev = IXGBE_DEV_TO_PCI(dev);
4973 if (!is_device_supported(dev, &rte_ixgbe_pmd))
4976 if (vf >= pci_dev->max_vfs)
4982 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4984 mac->ops.set_mac_anti_spoofing(hw, on, vf);
4990 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4992 struct ixgbe_hw *hw;
4994 struct rte_eth_dev *dev;
4995 struct rte_pci_device *pci_dev;
4997 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4999 dev = &rte_eth_devices[port];
5000 pci_dev = IXGBE_DEV_TO_PCI(dev);
5002 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5005 if (vf >= pci_dev->max_vfs)
5008 if (vlan_id > ETHER_MAX_VLAN_ID)
5011 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5012 ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
5015 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
5020 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
5026 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
5028 struct ixgbe_hw *hw;
5030 struct rte_eth_dev *dev;
5032 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5034 dev = &rte_eth_devices[port];
5036 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5042 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5043 ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5044 /* enable or disable VMDQ loopback */
5046 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
5048 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5050 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
5056 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
5058 struct ixgbe_hw *hw;
5061 int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
5062 struct rte_eth_dev *dev;
5064 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5066 dev = &rte_eth_devices[port];
5068 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5074 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5075 for (i = 0; i <= num_queues; i++) {
5076 reg_value = IXGBE_QDE_WRITE |
5077 (i << IXGBE_QDE_IDX_SHIFT) |
5078 (on & IXGBE_QDE_ENABLE);
5079 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
5086 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
5088 struct ixgbe_hw *hw;
5090 struct rte_eth_dev *dev;
5091 struct rte_pci_device *pci_dev;
5093 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5095 dev = &rte_eth_devices[port];
5096 pci_dev = IXGBE_DEV_TO_PCI(dev);
5098 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5101 /* only support VF's 0 to 63 */
5102 if ((vf >= pci_dev->max_vfs) || (vf > 63))
5108 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5109 reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
5111 reg_value |= IXGBE_SRRCTL_DROP_EN;
5113 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
5115 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
5121 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
5123 struct rte_eth_dev *dev;
5124 struct rte_pci_device *pci_dev;
5125 struct ixgbe_hw *hw;
5126 uint16_t queues_per_pool;
5129 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5131 dev = &rte_eth_devices[port];
5132 pci_dev = IXGBE_DEV_TO_PCI(dev);
5133 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5135 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5138 if (vf >= pci_dev->max_vfs)
5144 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5146 /* The PF has 128 queue pairs and in SRIOV configuration
5147 * those queues will be assigned to VF's, so RXDCTL
5148 * registers will be dealing with queues which will be
5150 * Let's say we have SRIOV configured with 31 VF's then the
5151 * first 124 queues 0-123 will be allocated to VF's and only
5152 * the last 4 queues 123-127 will be assigned to the PF.
5154 if (hw->mac.type == ixgbe_mac_82598EB)
5155 queues_per_pool = (uint16_t)hw->mac.max_rx_queues /
5158 queues_per_pool = (uint16_t)hw->mac.max_rx_queues /
5161 for (q = 0; q < queues_per_pool; q++)
5162 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5163 q + vf * queues_per_pool, on);
5168 rte_pmd_ixgbe_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mask, uint8_t on)
5171 struct rte_eth_dev *dev;
5172 struct rte_pci_device *pci_dev;
5173 struct ixgbe_hw *hw;
5176 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5178 dev = &rte_eth_devices[port];
5179 pci_dev = IXGBE_DEV_TO_PCI(dev);
5181 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5184 if (vf >= pci_dev->max_vfs)
5190 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5191 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
5193 if (hw->mac.type == ixgbe_mac_82598EB) {
5194 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
5195 " on 82599 hardware and newer");
5198 if (ixgbe_vt_check(hw) < 0)
5201 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
5208 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
5214 rte_pmd_ixgbe_set_vf_rx(uint8_t port, uint16_t vf, uint8_t on)
5216 struct rte_eth_dev *dev;
5217 struct rte_pci_device *pci_dev;
5220 const uint8_t bit1 = 0x1;
5221 struct ixgbe_hw *hw;
5223 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5225 dev = &rte_eth_devices[port];
5226 pci_dev = IXGBE_DEV_TO_PCI(dev);
5228 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5231 if (vf >= pci_dev->max_vfs)
5237 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5239 if (ixgbe_vt_check(hw) < 0)
5242 /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
5244 addr = IXGBE_VFRE(1);
5245 val = bit1 << (vf - 32);
5247 addr = IXGBE_VFRE(0);
5251 reg = IXGBE_READ_REG(hw, addr);
5258 IXGBE_WRITE_REG(hw, addr, reg);
5264 rte_pmd_ixgbe_set_vf_tx(uint8_t port, uint16_t vf, uint8_t on)
5266 struct rte_eth_dev *dev;
5267 struct rte_pci_device *pci_dev;
5270 const uint8_t bit1 = 0x1;
5272 struct ixgbe_hw *hw;
5274 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5276 dev = &rte_eth_devices[port];
5277 pci_dev = IXGBE_DEV_TO_PCI(dev);
5279 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5282 if (vf >= pci_dev->max_vfs)
5288 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5289 if (ixgbe_vt_check(hw) < 0)
5292 /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
5294 addr = IXGBE_VFTE(1);
5295 val = bit1 << (vf - 32);
5297 addr = IXGBE_VFTE(0);
5301 reg = IXGBE_READ_REG(hw, addr);
5308 IXGBE_WRITE_REG(hw, addr, reg);
5314 rte_pmd_ixgbe_set_vf_vlan_filter(uint8_t port, uint16_t vlan,
5315 uint64_t vf_mask, uint8_t vlan_on)
5317 struct rte_eth_dev *dev;
5320 struct ixgbe_hw *hw;
5322 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5324 dev = &rte_eth_devices[port];
5326 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5329 if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
5332 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5333 if (ixgbe_vt_check(hw) < 0)
5336 for (vf_idx = 0; vf_idx < 64; vf_idx++) {
5337 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
5338 ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
5348 int rte_pmd_ixgbe_set_vf_rate_limit(uint8_t port, uint16_t vf,
5349 uint16_t tx_rate, uint64_t q_msk)
5351 struct rte_eth_dev *dev;
5352 struct ixgbe_hw *hw;
5353 struct ixgbe_vf_info *vfinfo;
5354 struct rte_eth_link link;
5355 uint8_t nb_q_per_pool;
5356 uint32_t queue_stride;
5357 uint32_t queue_idx, idx = 0, vf_idx;
5359 uint16_t total_rate = 0;
5360 struct rte_pci_device *pci_dev;
5362 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5364 dev = &rte_eth_devices[port];
5365 pci_dev = IXGBE_DEV_TO_PCI(dev);
5366 rte_eth_link_get_nowait(port, &link);
5368 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5371 if (vf >= pci_dev->max_vfs)
5374 if (tx_rate > link.link_speed)
5380 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5381 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5382 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5383 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5384 queue_idx = vf * queue_stride;
5385 queue_end = queue_idx + nb_q_per_pool - 1;
5386 if (queue_end >= hw->mac.max_tx_queues)
5390 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5393 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5395 total_rate += vfinfo[vf_idx].tx_rate[idx];
5401 /* Store tx_rate for this vf. */
5402 for (idx = 0; idx < nb_q_per_pool; idx++) {
5403 if (((uint64_t)0x1 << idx) & q_msk) {
5404 if (vfinfo[vf].tx_rate[idx] != tx_rate)
5405 vfinfo[vf].tx_rate[idx] = tx_rate;
5406 total_rate += tx_rate;
5410 if (total_rate > dev->data->dev_link.link_speed) {
5411 /* Reset stored TX rate of the VF if it causes exceed
5414 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5418 /* Set RTTBCNRC of each queue/pool for vf X */
5419 for (; queue_idx <= queue_end; queue_idx++) {
5421 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5428 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5429 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5430 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5431 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5432 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5433 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5434 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5437 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5438 struct rte_eth_mirror_conf *mirror_conf,
5439 uint8_t rule_id, uint8_t on)
5441 uint32_t mr_ctl, vlvf;
5442 uint32_t mp_lsb = 0;
5443 uint32_t mv_msb = 0;
5444 uint32_t mv_lsb = 0;
5445 uint32_t mp_msb = 0;
5448 uint64_t vlan_mask = 0;
5450 const uint8_t pool_mask_offset = 32;
5451 const uint8_t vlan_mask_offset = 32;
5452 const uint8_t dst_pool_offset = 8;
5453 const uint8_t rule_mr_offset = 4;
5454 const uint8_t mirror_rule_mask = 0x0F;
5456 struct ixgbe_mirror_info *mr_info =
5457 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5458 struct ixgbe_hw *hw =
5459 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5460 uint8_t mirror_type = 0;
5462 if (ixgbe_vt_check(hw) < 0)
5465 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5468 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5469 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5470 mirror_conf->rule_type);
5474 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5475 mirror_type |= IXGBE_MRCTL_VLME;
5476 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5477 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5478 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5479 /* search vlan id related pool vlan filter index */
5480 reg_index = ixgbe_find_vlvf_slot(hw,
5481 mirror_conf->vlan.vlan_id[i],
5485 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5486 if ((vlvf & IXGBE_VLVF_VIEN) &&
5487 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5488 mirror_conf->vlan.vlan_id[i]))
5489 vlan_mask |= (1ULL << reg_index);
5496 mv_lsb = vlan_mask & 0xFFFFFFFF;
5497 mv_msb = vlan_mask >> vlan_mask_offset;
5499 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5500 mirror_conf->vlan.vlan_mask;
5501 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5502 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5503 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5504 mirror_conf->vlan.vlan_id[i];
5509 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5510 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5511 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5516 * if enable pool mirror, write related pool mask register,if disable
5517 * pool mirror, clear PFMRVM register
5519 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5520 mirror_type |= IXGBE_MRCTL_VPME;
5522 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5523 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5524 mr_info->mr_conf[rule_id].pool_mask =
5525 mirror_conf->pool_mask;
5530 mr_info->mr_conf[rule_id].pool_mask = 0;
5533 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5534 mirror_type |= IXGBE_MRCTL_UPME;
5535 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5536 mirror_type |= IXGBE_MRCTL_DPME;
5538 /* read mirror control register and recalculate it */
5539 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5542 mr_ctl |= mirror_type;
5543 mr_ctl &= mirror_rule_mask;
5544 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5546 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5548 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5549 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5551 /* write mirrror control register */
5552 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5554 /* write pool mirrror control register */
5555 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5556 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5557 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5560 /* write VLAN mirrror control register */
5561 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5562 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5563 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5571 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5574 uint32_t lsb_val = 0;
5575 uint32_t msb_val = 0;
5576 const uint8_t rule_mr_offset = 4;
5578 struct ixgbe_hw *hw =
5579 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5580 struct ixgbe_mirror_info *mr_info =
5581 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5583 if (ixgbe_vt_check(hw) < 0)
5586 memset(&mr_info->mr_conf[rule_id], 0,
5587 sizeof(struct rte_eth_mirror_conf));
5589 /* clear PFVMCTL register */
5590 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5592 /* clear pool mask register */
5593 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5594 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5596 /* clear vlan mask register */
5597 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5598 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5604 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5606 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5607 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5609 struct ixgbe_hw *hw =
5610 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5612 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5613 mask |= (1 << IXGBE_MISC_VEC_ID);
5614 RTE_SET_USED(queue_id);
5615 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5617 rte_intr_enable(intr_handle);
5623 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5626 struct ixgbe_hw *hw =
5627 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5629 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5630 mask &= ~(1 << IXGBE_MISC_VEC_ID);
5631 RTE_SET_USED(queue_id);
5632 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5638 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5640 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5641 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5643 struct ixgbe_hw *hw =
5644 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5645 struct ixgbe_interrupt *intr =
5646 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5648 if (queue_id < 16) {
5649 ixgbe_disable_intr(hw);
5650 intr->mask |= (1 << queue_id);
5651 ixgbe_enable_intr(dev);
5652 } else if (queue_id < 32) {
5653 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5654 mask &= (1 << queue_id);
5655 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5656 } else if (queue_id < 64) {
5657 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5658 mask &= (1 << (queue_id - 32));
5659 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5661 rte_intr_enable(intr_handle);
5667 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5670 struct ixgbe_hw *hw =
5671 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5672 struct ixgbe_interrupt *intr =
5673 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5675 if (queue_id < 16) {
5676 ixgbe_disable_intr(hw);
5677 intr->mask &= ~(1 << queue_id);
5678 ixgbe_enable_intr(dev);
5679 } else if (queue_id < 32) {
5680 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5681 mask &= ~(1 << queue_id);
5682 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5683 } else if (queue_id < 64) {
5684 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5685 mask &= ~(1 << (queue_id - 32));
5686 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5693 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5694 uint8_t queue, uint8_t msix_vector)
5698 if (direction == -1) {
5700 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5701 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5704 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5706 /* rx or tx cause */
5707 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5708 idx = ((16 * (queue & 1)) + (8 * direction));
5709 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5710 tmp &= ~(0xFF << idx);
5711 tmp |= (msix_vector << idx);
5712 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5717 * set the IVAR registers, mapping interrupt causes to vectors
5719 * pointer to ixgbe_hw struct
5721 * 0 for Rx, 1 for Tx, -1 for other causes
5723 * queue to map the corresponding interrupt to
5725 * the vector to map to the corresponding queue
5728 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5729 uint8_t queue, uint8_t msix_vector)
5733 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5734 if (hw->mac.type == ixgbe_mac_82598EB) {
5735 if (direction == -1)
5737 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5738 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5739 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5740 tmp |= (msix_vector << (8 * (queue & 0x3)));
5741 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5742 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5743 (hw->mac.type == ixgbe_mac_X540)) {
5744 if (direction == -1) {
5746 idx = ((queue & 1) * 8);
5747 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5748 tmp &= ~(0xFF << idx);
5749 tmp |= (msix_vector << idx);
5750 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5752 /* rx or tx causes */
5753 idx = ((16 * (queue & 1)) + (8 * direction));
5754 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5755 tmp &= ~(0xFF << idx);
5756 tmp |= (msix_vector << idx);
5757 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5763 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5765 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5766 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5767 struct ixgbe_hw *hw =
5768 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5770 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5772 /* Configure VF other cause ivar */
5773 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5775 /* won't configure msix register if no mapping is done
5776 * between intr vector and event fd.
5778 if (!rte_intr_dp_is_en(intr_handle))
5781 /* Configure all RX queues of VF */
5782 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5783 /* Force all queue use vector 0,
5784 * as IXGBE_VF_MAXMSIVECOTR = 1
5786 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5787 intr_handle->intr_vec[q_idx] = vector_idx;
5792 * Sets up the hardware to properly generate MSI-X interrupts
5794 * board private structure
5797 ixgbe_configure_msix(struct rte_eth_dev *dev)
5799 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5800 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5801 struct ixgbe_hw *hw =
5802 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5803 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5804 uint32_t vec = IXGBE_MISC_VEC_ID;
5808 /* won't configure msix register if no mapping is done
5809 * between intr vector and event fd
5811 if (!rte_intr_dp_is_en(intr_handle))
5814 if (rte_intr_allow_others(intr_handle))
5815 vec = base = IXGBE_RX_VEC_START;
5817 /* setup GPIE for MSI-x mode */
5818 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5819 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5820 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5821 /* auto clearing and auto setting corresponding bits in EIMS
5822 * when MSI-X interrupt is triggered
5824 if (hw->mac.type == ixgbe_mac_82598EB) {
5825 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5827 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5828 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5830 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5832 /* Populate the IVAR table and set the ITR values to the
5833 * corresponding register.
5835 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5837 /* by default, 1:1 mapping */
5838 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5839 intr_handle->intr_vec[queue_id] = vec;
5840 if (vec < base + intr_handle->nb_efd - 1)
5844 switch (hw->mac.type) {
5845 case ixgbe_mac_82598EB:
5846 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5849 case ixgbe_mac_82599EB:
5850 case ixgbe_mac_X540:
5851 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5856 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5857 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5859 /* set up to autoclear timer, and the vectors */
5860 mask = IXGBE_EIMS_ENABLE_MASK;
5861 mask &= ~(IXGBE_EIMS_OTHER |
5862 IXGBE_EIMS_MAILBOX |
5865 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5868 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5869 uint16_t queue_idx, uint16_t tx_rate)
5871 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5872 uint32_t rf_dec, rf_int;
5874 uint16_t link_speed = dev->data->dev_link.link_speed;
5876 if (queue_idx >= hw->mac.max_tx_queues)
5880 /* Calculate the rate factor values to set */
5881 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5882 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5883 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5885 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5886 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5887 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5888 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5894 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5895 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5898 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5899 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5900 IXGBE_MAX_JUMBO_FRAME_SIZE))
5901 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5902 IXGBE_MMW_SIZE_JUMBO_FRAME);
5904 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5905 IXGBE_MMW_SIZE_DEFAULT);
5907 /* Set RTTBCNRC of queue X */
5908 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5909 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5910 IXGBE_WRITE_FLUSH(hw);
5916 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5917 __attribute__((unused)) uint32_t index,
5918 __attribute__((unused)) uint32_t pool)
5920 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5924 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5925 * operation. Trap this case to avoid exhausting the [very limited]
5926 * set of PF resources used to store VF MAC addresses.
5928 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5930 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5933 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5937 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5939 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5940 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5941 struct ether_addr *mac_addr;
5946 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5947 * not support the deletion of a given MAC address.
5948 * Instead, it imposes to delete all MAC addresses, then to add again
5949 * all MAC addresses with the exception of the one to be deleted.
5951 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5954 * Add again all MAC addresses, with the exception of the deleted one
5955 * and of the permanent MAC address.
5957 for (i = 0, mac_addr = dev->data->mac_addrs;
5958 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5959 /* Skip the deleted MAC address */
5962 /* Skip NULL MAC addresses */
5963 if (is_zero_ether_addr(mac_addr))
5965 /* Skip the permanent MAC address */
5966 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5968 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5971 "Adding again MAC address "
5972 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5974 mac_addr->addr_bytes[0],
5975 mac_addr->addr_bytes[1],
5976 mac_addr->addr_bytes[2],
5977 mac_addr->addr_bytes[3],
5978 mac_addr->addr_bytes[4],
5979 mac_addr->addr_bytes[5],
5985 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5987 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5989 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5993 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5994 struct rte_eth_syn_filter *filter,
5997 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5998 struct ixgbe_filter_info *filter_info =
5999 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6003 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6006 syn_info = filter_info->syn_info;
6009 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6011 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6012 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6014 if (filter->hig_pri)
6015 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6017 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6019 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6020 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6022 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6025 filter_info->syn_info = synqf;
6026 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6027 IXGBE_WRITE_FLUSH(hw);
6032 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6033 struct rte_eth_syn_filter *filter)
6035 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6036 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6038 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6039 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6040 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6047 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6048 enum rte_filter_op filter_op,
6051 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6054 MAC_TYPE_FILTER_SUP(hw->mac.type);
6056 if (filter_op == RTE_ETH_FILTER_NOP)
6060 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6065 switch (filter_op) {
6066 case RTE_ETH_FILTER_ADD:
6067 ret = ixgbe_syn_filter_set(dev,
6068 (struct rte_eth_syn_filter *)arg,
6071 case RTE_ETH_FILTER_DELETE:
6072 ret = ixgbe_syn_filter_set(dev,
6073 (struct rte_eth_syn_filter *)arg,
6076 case RTE_ETH_FILTER_GET:
6077 ret = ixgbe_syn_filter_get(dev,
6078 (struct rte_eth_syn_filter *)arg);
6081 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6090 static inline enum ixgbe_5tuple_protocol
6091 convert_protocol_type(uint8_t protocol_value)
6093 if (protocol_value == IPPROTO_TCP)
6094 return IXGBE_FILTER_PROTOCOL_TCP;
6095 else if (protocol_value == IPPROTO_UDP)
6096 return IXGBE_FILTER_PROTOCOL_UDP;
6097 else if (protocol_value == IPPROTO_SCTP)
6098 return IXGBE_FILTER_PROTOCOL_SCTP;
6100 return IXGBE_FILTER_PROTOCOL_NONE;
6103 /* inject a 5-tuple filter to HW */
6105 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6106 struct ixgbe_5tuple_filter *filter)
6108 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6110 uint32_t ftqf, sdpqf;
6111 uint32_t l34timir = 0;
6112 uint8_t mask = 0xff;
6116 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6117 IXGBE_SDPQF_DSTPORT_SHIFT);
6118 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6120 ftqf = (uint32_t)(filter->filter_info.proto &
6121 IXGBE_FTQF_PROTOCOL_MASK);
6122 ftqf |= (uint32_t)((filter->filter_info.priority &
6123 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6124 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6125 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6126 if (filter->filter_info.dst_ip_mask == 0)
6127 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6128 if (filter->filter_info.src_port_mask == 0)
6129 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6130 if (filter->filter_info.dst_port_mask == 0)
6131 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6132 if (filter->filter_info.proto_mask == 0)
6133 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6134 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6135 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6136 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6138 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6139 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6140 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6141 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6143 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6144 l34timir |= (uint32_t)(filter->queue <<
6145 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6146 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6150 * add a 5tuple filter
6153 * dev: Pointer to struct rte_eth_dev.
6154 * index: the index the filter allocates.
6155 * filter: ponter to the filter that will be added.
6156 * rx_queue: the queue id the filter assigned to.
6159 * - On success, zero.
6160 * - On failure, a negative value.
6163 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6164 struct ixgbe_5tuple_filter *filter)
6166 struct ixgbe_filter_info *filter_info =
6167 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6171 * look for an unused 5tuple filter index,
6172 * and insert the filter to list.
6174 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6175 idx = i / (sizeof(uint32_t) * NBBY);
6176 shift = i % (sizeof(uint32_t) * NBBY);
6177 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6178 filter_info->fivetuple_mask[idx] |= 1 << shift;
6180 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6186 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6187 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6191 ixgbe_inject_5tuple_filter(dev, filter);
6197 * remove a 5tuple filter
6200 * dev: Pointer to struct rte_eth_dev.
6201 * filter: the pointer of the filter will be removed.
6204 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6205 struct ixgbe_5tuple_filter *filter)
6207 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6208 struct ixgbe_filter_info *filter_info =
6209 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6210 uint16_t index = filter->index;
6212 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6213 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6214 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6217 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6218 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6219 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6220 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6221 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6225 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6227 struct ixgbe_hw *hw;
6228 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6230 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6232 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6235 /* refuse mtu that requires the support of scattered packets when this
6236 * feature has not been enabled before.
6238 if (!dev->data->scattered_rx &&
6239 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6240 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6244 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6245 * request of the version 2.0 of the mailbox API.
6246 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6247 * of the mailbox API.
6248 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6249 * prior to 3.11.33 which contains the following change:
6250 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6252 ixgbevf_rlpml_set_vf(hw, max_frame);
6254 /* update max frame size */
6255 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6259 static inline struct ixgbe_5tuple_filter *
6260 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6261 struct ixgbe_5tuple_filter_info *key)
6263 struct ixgbe_5tuple_filter *it;
6265 TAILQ_FOREACH(it, filter_list, entries) {
6266 if (memcmp(key, &it->filter_info,
6267 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6274 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6276 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6277 struct ixgbe_5tuple_filter_info *filter_info)
6279 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6280 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6281 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6284 switch (filter->dst_ip_mask) {
6286 filter_info->dst_ip_mask = 0;
6287 filter_info->dst_ip = filter->dst_ip;
6290 filter_info->dst_ip_mask = 1;
6293 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6297 switch (filter->src_ip_mask) {
6299 filter_info->src_ip_mask = 0;
6300 filter_info->src_ip = filter->src_ip;
6303 filter_info->src_ip_mask = 1;
6306 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6310 switch (filter->dst_port_mask) {
6312 filter_info->dst_port_mask = 0;
6313 filter_info->dst_port = filter->dst_port;
6316 filter_info->dst_port_mask = 1;
6319 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6323 switch (filter->src_port_mask) {
6325 filter_info->src_port_mask = 0;
6326 filter_info->src_port = filter->src_port;
6329 filter_info->src_port_mask = 1;
6332 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6336 switch (filter->proto_mask) {
6338 filter_info->proto_mask = 0;
6339 filter_info->proto =
6340 convert_protocol_type(filter->proto);
6343 filter_info->proto_mask = 1;
6346 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6350 filter_info->priority = (uint8_t)filter->priority;
6355 * add or delete a ntuple filter
6358 * dev: Pointer to struct rte_eth_dev.
6359 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6360 * add: if true, add filter, if false, remove filter
6363 * - On success, zero.
6364 * - On failure, a negative value.
6367 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6368 struct rte_eth_ntuple_filter *ntuple_filter,
6371 struct ixgbe_filter_info *filter_info =
6372 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6373 struct ixgbe_5tuple_filter_info filter_5tuple;
6374 struct ixgbe_5tuple_filter *filter;
6377 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6378 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6382 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6383 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6387 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6389 if (filter != NULL && add) {
6390 PMD_DRV_LOG(ERR, "filter exists.");
6393 if (filter == NULL && !add) {
6394 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6399 filter = rte_zmalloc("ixgbe_5tuple_filter",
6400 sizeof(struct ixgbe_5tuple_filter), 0);
6403 (void)rte_memcpy(&filter->filter_info,
6405 sizeof(struct ixgbe_5tuple_filter_info));
6406 filter->queue = ntuple_filter->queue;
6407 ret = ixgbe_add_5tuple_filter(dev, filter);
6413 ixgbe_remove_5tuple_filter(dev, filter);
6419 * get a ntuple filter
6422 * dev: Pointer to struct rte_eth_dev.
6423 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6426 * - On success, zero.
6427 * - On failure, a negative value.
6430 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6431 struct rte_eth_ntuple_filter *ntuple_filter)
6433 struct ixgbe_filter_info *filter_info =
6434 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6435 struct ixgbe_5tuple_filter_info filter_5tuple;
6436 struct ixgbe_5tuple_filter *filter;
6439 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6440 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6444 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6445 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6449 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6451 if (filter == NULL) {
6452 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6455 ntuple_filter->queue = filter->queue;
6460 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6461 * @dev: pointer to rte_eth_dev structure
6462 * @filter_op:operation will be taken.
6463 * @arg: a pointer to specific structure corresponding to the filter_op
6466 * - On success, zero.
6467 * - On failure, a negative value.
6470 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6471 enum rte_filter_op filter_op,
6474 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6477 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6479 if (filter_op == RTE_ETH_FILTER_NOP)
6483 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6488 switch (filter_op) {
6489 case RTE_ETH_FILTER_ADD:
6490 ret = ixgbe_add_del_ntuple_filter(dev,
6491 (struct rte_eth_ntuple_filter *)arg,
6494 case RTE_ETH_FILTER_DELETE:
6495 ret = ixgbe_add_del_ntuple_filter(dev,
6496 (struct rte_eth_ntuple_filter *)arg,
6499 case RTE_ETH_FILTER_GET:
6500 ret = ixgbe_get_ntuple_filter(dev,
6501 (struct rte_eth_ntuple_filter *)arg);
6504 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6512 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6513 struct rte_eth_ethertype_filter *filter,
6516 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6517 struct ixgbe_filter_info *filter_info =
6518 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6522 struct ixgbe_ethertype_filter ethertype_filter;
6524 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6527 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6528 filter->ether_type == ETHER_TYPE_IPv6) {
6529 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6530 " ethertype filter.", filter->ether_type);
6534 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6535 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6538 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6539 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6543 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6544 if (ret >= 0 && add) {
6545 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6546 filter->ether_type);
6549 if (ret < 0 && !add) {
6550 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6551 filter->ether_type);
6556 etqf = IXGBE_ETQF_FILTER_EN;
6557 etqf |= (uint32_t)filter->ether_type;
6558 etqs |= (uint32_t)((filter->queue <<
6559 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6560 IXGBE_ETQS_RX_QUEUE);
6561 etqs |= IXGBE_ETQS_QUEUE_EN;
6563 ethertype_filter.ethertype = filter->ether_type;
6564 ethertype_filter.etqf = etqf;
6565 ethertype_filter.etqs = etqs;
6566 ethertype_filter.conf = FALSE;
6567 ret = ixgbe_ethertype_filter_insert(filter_info,
6570 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6574 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6578 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6579 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6580 IXGBE_WRITE_FLUSH(hw);
6586 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6587 struct rte_eth_ethertype_filter *filter)
6589 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6590 struct ixgbe_filter_info *filter_info =
6591 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6592 uint32_t etqf, etqs;
6595 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6597 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6598 filter->ether_type);
6602 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6603 if (etqf & IXGBE_ETQF_FILTER_EN) {
6604 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6605 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6607 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6608 IXGBE_ETQS_RX_QUEUE_SHIFT;
6615 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6616 * @dev: pointer to rte_eth_dev structure
6617 * @filter_op:operation will be taken.
6618 * @arg: a pointer to specific structure corresponding to the filter_op
6621 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6622 enum rte_filter_op filter_op,
6625 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6628 MAC_TYPE_FILTER_SUP(hw->mac.type);
6630 if (filter_op == RTE_ETH_FILTER_NOP)
6634 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6639 switch (filter_op) {
6640 case RTE_ETH_FILTER_ADD:
6641 ret = ixgbe_add_del_ethertype_filter(dev,
6642 (struct rte_eth_ethertype_filter *)arg,
6645 case RTE_ETH_FILTER_DELETE:
6646 ret = ixgbe_add_del_ethertype_filter(dev,
6647 (struct rte_eth_ethertype_filter *)arg,
6650 case RTE_ETH_FILTER_GET:
6651 ret = ixgbe_get_ethertype_filter(dev,
6652 (struct rte_eth_ethertype_filter *)arg);
6655 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6663 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6664 enum rte_filter_type filter_type,
6665 enum rte_filter_op filter_op,
6670 switch (filter_type) {
6671 case RTE_ETH_FILTER_NTUPLE:
6672 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6674 case RTE_ETH_FILTER_ETHERTYPE:
6675 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6677 case RTE_ETH_FILTER_SYN:
6678 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6680 case RTE_ETH_FILTER_FDIR:
6681 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6683 case RTE_ETH_FILTER_L2_TUNNEL:
6684 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6686 case RTE_ETH_FILTER_GENERIC:
6687 if (filter_op != RTE_ETH_FILTER_GET)
6689 *(const void **)arg = &ixgbe_flow_ops;
6692 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6702 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6703 u8 **mc_addr_ptr, u32 *vmdq)
6708 mc_addr = *mc_addr_ptr;
6709 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6714 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6715 struct ether_addr *mc_addr_set,
6716 uint32_t nb_mc_addr)
6718 struct ixgbe_hw *hw;
6721 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6722 mc_addr_list = (u8 *)mc_addr_set;
6723 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6724 ixgbe_dev_addr_list_itr, TRUE);
6728 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6730 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6731 uint64_t systime_cycles;
6733 switch (hw->mac.type) {
6734 case ixgbe_mac_X550:
6735 case ixgbe_mac_X550EM_x:
6736 case ixgbe_mac_X550EM_a:
6737 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6738 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6739 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6743 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6744 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6748 return systime_cycles;
6752 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6754 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6755 uint64_t rx_tstamp_cycles;
6757 switch (hw->mac.type) {
6758 case ixgbe_mac_X550:
6759 case ixgbe_mac_X550EM_x:
6760 case ixgbe_mac_X550EM_a:
6761 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6762 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6763 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6767 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6768 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6769 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6773 return rx_tstamp_cycles;
6777 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6779 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6780 uint64_t tx_tstamp_cycles;
6782 switch (hw->mac.type) {
6783 case ixgbe_mac_X550:
6784 case ixgbe_mac_X550EM_x:
6785 case ixgbe_mac_X550EM_a:
6786 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6787 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6788 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6792 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6793 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6794 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6798 return tx_tstamp_cycles;
6802 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6804 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6805 struct ixgbe_adapter *adapter =
6806 (struct ixgbe_adapter *)dev->data->dev_private;
6807 struct rte_eth_link link;
6808 uint32_t incval = 0;
6811 /* Get current link speed. */
6812 memset(&link, 0, sizeof(link));
6813 ixgbe_dev_link_update(dev, 1);
6814 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6816 switch (link.link_speed) {
6817 case ETH_SPEED_NUM_100M:
6818 incval = IXGBE_INCVAL_100;
6819 shift = IXGBE_INCVAL_SHIFT_100;
6821 case ETH_SPEED_NUM_1G:
6822 incval = IXGBE_INCVAL_1GB;
6823 shift = IXGBE_INCVAL_SHIFT_1GB;
6825 case ETH_SPEED_NUM_10G:
6827 incval = IXGBE_INCVAL_10GB;
6828 shift = IXGBE_INCVAL_SHIFT_10GB;
6832 switch (hw->mac.type) {
6833 case ixgbe_mac_X550:
6834 case ixgbe_mac_X550EM_x:
6835 case ixgbe_mac_X550EM_a:
6836 /* Independent of link speed. */
6838 /* Cycles read will be interpreted as ns. */
6841 case ixgbe_mac_X540:
6842 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6844 case ixgbe_mac_82599EB:
6845 incval >>= IXGBE_INCVAL_SHIFT_82599;
6846 shift -= IXGBE_INCVAL_SHIFT_82599;
6847 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6848 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6851 /* Not supported. */
6855 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6856 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6857 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6859 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6860 adapter->systime_tc.cc_shift = shift;
6861 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6863 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6864 adapter->rx_tstamp_tc.cc_shift = shift;
6865 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6867 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6868 adapter->tx_tstamp_tc.cc_shift = shift;
6869 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6873 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6875 struct ixgbe_adapter *adapter =
6876 (struct ixgbe_adapter *)dev->data->dev_private;
6878 adapter->systime_tc.nsec += delta;
6879 adapter->rx_tstamp_tc.nsec += delta;
6880 adapter->tx_tstamp_tc.nsec += delta;
6886 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6889 struct ixgbe_adapter *adapter =
6890 (struct ixgbe_adapter *)dev->data->dev_private;
6892 ns = rte_timespec_to_ns(ts);
6893 /* Set the timecounters to a new value. */
6894 adapter->systime_tc.nsec = ns;
6895 adapter->rx_tstamp_tc.nsec = ns;
6896 adapter->tx_tstamp_tc.nsec = ns;
6902 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6904 uint64_t ns, systime_cycles;
6905 struct ixgbe_adapter *adapter =
6906 (struct ixgbe_adapter *)dev->data->dev_private;
6908 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6909 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6910 *ts = rte_ns_to_timespec(ns);
6916 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6918 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6922 /* Stop the timesync system time. */
6923 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6924 /* Reset the timesync system time value. */
6925 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6926 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6928 /* Enable system time for platforms where it isn't on by default. */
6929 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6930 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6931 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6933 ixgbe_start_timecounters(dev);
6935 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6936 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6938 IXGBE_ETQF_FILTER_EN |
6941 /* Enable timestamping of received PTP packets. */
6942 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6943 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6944 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6946 /* Enable timestamping of transmitted PTP packets. */
6947 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6948 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6949 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6951 IXGBE_WRITE_FLUSH(hw);
6957 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6959 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6962 /* Disable timestamping of transmitted PTP packets. */
6963 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6964 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6965 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6967 /* Disable timestamping of received PTP packets. */
6968 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6969 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6970 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6972 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6973 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6975 /* Stop incrementating the System Time registers. */
6976 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6982 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6983 struct timespec *timestamp,
6984 uint32_t flags __rte_unused)
6986 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6987 struct ixgbe_adapter *adapter =
6988 (struct ixgbe_adapter *)dev->data->dev_private;
6989 uint32_t tsync_rxctl;
6990 uint64_t rx_tstamp_cycles;
6993 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6994 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6997 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6998 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6999 *timestamp = rte_ns_to_timespec(ns);
7005 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7006 struct timespec *timestamp)
7008 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7009 struct ixgbe_adapter *adapter =
7010 (struct ixgbe_adapter *)dev->data->dev_private;
7011 uint32_t tsync_txctl;
7012 uint64_t tx_tstamp_cycles;
7015 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7016 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7019 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7020 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7021 *timestamp = rte_ns_to_timespec(ns);
7027 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7029 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7032 const struct reg_info *reg_group;
7033 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7034 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7036 while ((reg_group = reg_set[g_ind++]))
7037 count += ixgbe_regs_group_count(reg_group);
7043 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7047 const struct reg_info *reg_group;
7049 while ((reg_group = ixgbevf_regs[g_ind++]))
7050 count += ixgbe_regs_group_count(reg_group);
7056 ixgbe_get_regs(struct rte_eth_dev *dev,
7057 struct rte_dev_reg_info *regs)
7059 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7060 uint32_t *data = regs->data;
7063 const struct reg_info *reg_group;
7064 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7065 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7068 regs->length = ixgbe_get_reg_length(dev);
7069 regs->width = sizeof(uint32_t);
7073 /* Support only full register dump */
7074 if ((regs->length == 0) ||
7075 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7076 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7078 while ((reg_group = reg_set[g_ind++]))
7079 count += ixgbe_read_regs_group(dev, &data[count],
7088 ixgbevf_get_regs(struct rte_eth_dev *dev,
7089 struct rte_dev_reg_info *regs)
7091 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7092 uint32_t *data = regs->data;
7095 const struct reg_info *reg_group;
7098 regs->length = ixgbevf_get_reg_length(dev);
7099 regs->width = sizeof(uint32_t);
7103 /* Support only full register dump */
7104 if ((regs->length == 0) ||
7105 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7106 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7108 while ((reg_group = ixgbevf_regs[g_ind++]))
7109 count += ixgbe_read_regs_group(dev, &data[count],
7118 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7120 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7122 /* Return unit is byte count */
7123 return hw->eeprom.word_size * 2;
7127 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7128 struct rte_dev_eeprom_info *in_eeprom)
7130 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7131 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7132 uint16_t *data = in_eeprom->data;
7135 first = in_eeprom->offset >> 1;
7136 length = in_eeprom->length >> 1;
7137 if ((first > hw->eeprom.word_size) ||
7138 ((first + length) > hw->eeprom.word_size))
7141 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7143 return eeprom->ops.read_buffer(hw, first, length, data);
7147 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7148 struct rte_dev_eeprom_info *in_eeprom)
7150 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7151 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7152 uint16_t *data = in_eeprom->data;
7155 first = in_eeprom->offset >> 1;
7156 length = in_eeprom->length >> 1;
7157 if ((first > hw->eeprom.word_size) ||
7158 ((first + length) > hw->eeprom.word_size))
7161 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7163 return eeprom->ops.write_buffer(hw, first, length, data);
7167 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7169 case ixgbe_mac_X550:
7170 case ixgbe_mac_X550EM_x:
7171 case ixgbe_mac_X550EM_a:
7172 return ETH_RSS_RETA_SIZE_512;
7173 case ixgbe_mac_X550_vf:
7174 case ixgbe_mac_X550EM_x_vf:
7175 case ixgbe_mac_X550EM_a_vf:
7176 return ETH_RSS_RETA_SIZE_64;
7178 return ETH_RSS_RETA_SIZE_128;
7183 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7185 case ixgbe_mac_X550:
7186 case ixgbe_mac_X550EM_x:
7187 case ixgbe_mac_X550EM_a:
7188 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7189 return IXGBE_RETA(reta_idx >> 2);
7191 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7192 case ixgbe_mac_X550_vf:
7193 case ixgbe_mac_X550EM_x_vf:
7194 case ixgbe_mac_X550EM_a_vf:
7195 return IXGBE_VFRETA(reta_idx >> 2);
7197 return IXGBE_RETA(reta_idx >> 2);
7202 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7204 case ixgbe_mac_X550_vf:
7205 case ixgbe_mac_X550EM_x_vf:
7206 case ixgbe_mac_X550EM_a_vf:
7207 return IXGBE_VFMRQC;
7214 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7216 case ixgbe_mac_X550_vf:
7217 case ixgbe_mac_X550EM_x_vf:
7218 case ixgbe_mac_X550EM_a_vf:
7219 return IXGBE_VFRSSRK(i);
7221 return IXGBE_RSSRK(i);
7226 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7228 case ixgbe_mac_82599_vf:
7229 case ixgbe_mac_X540_vf:
7237 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7238 struct rte_eth_dcb_info *dcb_info)
7240 struct ixgbe_dcb_config *dcb_config =
7241 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7242 struct ixgbe_dcb_tc_config *tc;
7245 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7246 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7248 dcb_info->nb_tcs = 1;
7250 if (dcb_config->vt_mode) { /* vt is enabled*/
7251 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7252 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7253 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7254 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7255 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7256 for (j = 0; j < dcb_info->nb_tcs; j++) {
7257 dcb_info->tc_queue.tc_rxq[i][j].base =
7258 i * dcb_info->nb_tcs + j;
7259 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7260 dcb_info->tc_queue.tc_txq[i][j].base =
7261 i * dcb_info->nb_tcs + j;
7262 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7265 } else { /* vt is disabled*/
7266 struct rte_eth_dcb_rx_conf *rx_conf =
7267 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7268 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7269 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7270 if (dcb_info->nb_tcs == ETH_4_TCS) {
7271 for (i = 0; i < dcb_info->nb_tcs; i++) {
7272 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7273 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7275 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7276 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7277 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7278 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7279 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7280 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7281 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7282 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7283 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7284 for (i = 0; i < dcb_info->nb_tcs; i++) {
7285 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7286 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7288 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7289 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7290 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7291 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7292 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7293 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7294 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7295 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7296 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7297 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7298 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7299 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7300 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7301 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7302 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7303 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7306 for (i = 0; i < dcb_info->nb_tcs; i++) {
7307 tc = &dcb_config->tc_config[i];
7308 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7313 /* Update e-tag ether type */
7315 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7316 uint16_t ether_type)
7318 uint32_t etag_etype;
7320 if (hw->mac.type != ixgbe_mac_X550 &&
7321 hw->mac.type != ixgbe_mac_X550EM_x &&
7322 hw->mac.type != ixgbe_mac_X550EM_a) {
7326 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7327 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7328 etag_etype |= ether_type;
7329 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7330 IXGBE_WRITE_FLUSH(hw);
7335 /* Config l2 tunnel ether type */
7337 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7338 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7341 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7342 struct ixgbe_l2_tn_info *l2_tn_info =
7343 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7345 if (l2_tunnel == NULL)
7348 switch (l2_tunnel->l2_tunnel_type) {
7349 case RTE_L2_TUNNEL_TYPE_E_TAG:
7350 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7351 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7354 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7362 /* Enable e-tag tunnel */
7364 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7366 uint32_t etag_etype;
7368 if (hw->mac.type != ixgbe_mac_X550 &&
7369 hw->mac.type != ixgbe_mac_X550EM_x &&
7370 hw->mac.type != ixgbe_mac_X550EM_a) {
7374 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7375 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7376 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7377 IXGBE_WRITE_FLUSH(hw);
7382 /* Enable l2 tunnel */
7384 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7385 enum rte_eth_tunnel_type l2_tunnel_type)
7388 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7389 struct ixgbe_l2_tn_info *l2_tn_info =
7390 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7392 switch (l2_tunnel_type) {
7393 case RTE_L2_TUNNEL_TYPE_E_TAG:
7394 l2_tn_info->e_tag_en = TRUE;
7395 ret = ixgbe_e_tag_enable(hw);
7398 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7406 /* Disable e-tag tunnel */
7408 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7410 uint32_t etag_etype;
7412 if (hw->mac.type != ixgbe_mac_X550 &&
7413 hw->mac.type != ixgbe_mac_X550EM_x &&
7414 hw->mac.type != ixgbe_mac_X550EM_a) {
7418 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7419 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7420 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7421 IXGBE_WRITE_FLUSH(hw);
7426 /* Disable l2 tunnel */
7428 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7429 enum rte_eth_tunnel_type l2_tunnel_type)
7432 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7433 struct ixgbe_l2_tn_info *l2_tn_info =
7434 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7436 switch (l2_tunnel_type) {
7437 case RTE_L2_TUNNEL_TYPE_E_TAG:
7438 l2_tn_info->e_tag_en = FALSE;
7439 ret = ixgbe_e_tag_disable(hw);
7442 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7451 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7452 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7455 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7456 uint32_t i, rar_entries;
7457 uint32_t rar_low, rar_high;
7459 if (hw->mac.type != ixgbe_mac_X550 &&
7460 hw->mac.type != ixgbe_mac_X550EM_x &&
7461 hw->mac.type != ixgbe_mac_X550EM_a) {
7465 rar_entries = ixgbe_get_num_rx_addrs(hw);
7467 for (i = 1; i < rar_entries; i++) {
7468 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7469 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7470 if ((rar_high & IXGBE_RAH_AV) &&
7471 (rar_high & IXGBE_RAH_ADTYPE) &&
7472 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7473 l2_tunnel->tunnel_id)) {
7474 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7475 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7477 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7487 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7488 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7491 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7492 uint32_t i, rar_entries;
7493 uint32_t rar_low, rar_high;
7495 if (hw->mac.type != ixgbe_mac_X550 &&
7496 hw->mac.type != ixgbe_mac_X550EM_x &&
7497 hw->mac.type != ixgbe_mac_X550EM_a) {
7501 /* One entry for one tunnel. Try to remove potential existing entry. */
7502 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7504 rar_entries = ixgbe_get_num_rx_addrs(hw);
7506 for (i = 1; i < rar_entries; i++) {
7507 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7508 if (rar_high & IXGBE_RAH_AV) {
7511 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7512 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7513 rar_low = l2_tunnel->tunnel_id;
7515 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7516 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7522 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7523 " Please remove a rule before adding a new one.");
7527 static inline struct ixgbe_l2_tn_filter *
7528 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7529 struct ixgbe_l2_tn_key *key)
7533 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7537 return l2_tn_info->hash_map[ret];
7541 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7542 struct ixgbe_l2_tn_filter *l2_tn_filter)
7546 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7547 &l2_tn_filter->key);
7551 "Failed to insert L2 tunnel filter"
7552 " to hash table %d!",
7557 l2_tn_info->hash_map[ret] = l2_tn_filter;
7559 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7565 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7566 struct ixgbe_l2_tn_key *key)
7569 struct ixgbe_l2_tn_filter *l2_tn_filter;
7571 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7575 "No such L2 tunnel filter to delete %d!",
7580 l2_tn_filter = l2_tn_info->hash_map[ret];
7581 l2_tn_info->hash_map[ret] = NULL;
7583 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7584 rte_free(l2_tn_filter);
7589 /* Add l2 tunnel filter */
7591 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7592 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7596 struct ixgbe_l2_tn_info *l2_tn_info =
7597 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7598 struct ixgbe_l2_tn_key key;
7599 struct ixgbe_l2_tn_filter *node;
7602 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7603 key.tn_id = l2_tunnel->tunnel_id;
7605 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7609 "The L2 tunnel filter already exists!");
7613 node = rte_zmalloc("ixgbe_l2_tn",
7614 sizeof(struct ixgbe_l2_tn_filter),
7619 (void)rte_memcpy(&node->key,
7621 sizeof(struct ixgbe_l2_tn_key));
7622 node->pool = l2_tunnel->pool;
7623 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7630 switch (l2_tunnel->l2_tunnel_type) {
7631 case RTE_L2_TUNNEL_TYPE_E_TAG:
7632 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7635 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7640 if ((!restore) && (ret < 0))
7641 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7646 /* Delete l2 tunnel filter */
7648 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7649 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7652 struct ixgbe_l2_tn_info *l2_tn_info =
7653 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7654 struct ixgbe_l2_tn_key key;
7656 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7657 key.tn_id = l2_tunnel->tunnel_id;
7658 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7662 switch (l2_tunnel->l2_tunnel_type) {
7663 case RTE_L2_TUNNEL_TYPE_E_TAG:
7664 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7667 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7676 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7677 * @dev: pointer to rte_eth_dev structure
7678 * @filter_op:operation will be taken.
7679 * @arg: a pointer to specific structure corresponding to the filter_op
7682 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7683 enum rte_filter_op filter_op,
7688 if (filter_op == RTE_ETH_FILTER_NOP)
7692 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7697 switch (filter_op) {
7698 case RTE_ETH_FILTER_ADD:
7699 ret = ixgbe_dev_l2_tunnel_filter_add
7701 (struct rte_eth_l2_tunnel_conf *)arg,
7704 case RTE_ETH_FILTER_DELETE:
7705 ret = ixgbe_dev_l2_tunnel_filter_del
7707 (struct rte_eth_l2_tunnel_conf *)arg);
7710 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7718 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7722 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7724 if (hw->mac.type != ixgbe_mac_X550 &&
7725 hw->mac.type != ixgbe_mac_X550EM_x &&
7726 hw->mac.type != ixgbe_mac_X550EM_a) {
7730 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7731 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7733 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7734 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7739 /* Enable l2 tunnel forwarding */
7741 ixgbe_dev_l2_tunnel_forwarding_enable
7742 (struct rte_eth_dev *dev,
7743 enum rte_eth_tunnel_type l2_tunnel_type)
7745 struct ixgbe_l2_tn_info *l2_tn_info =
7746 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7749 switch (l2_tunnel_type) {
7750 case RTE_L2_TUNNEL_TYPE_E_TAG:
7751 l2_tn_info->e_tag_fwd_en = TRUE;
7752 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7755 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7763 /* Disable l2 tunnel forwarding */
7765 ixgbe_dev_l2_tunnel_forwarding_disable
7766 (struct rte_eth_dev *dev,
7767 enum rte_eth_tunnel_type l2_tunnel_type)
7769 struct ixgbe_l2_tn_info *l2_tn_info =
7770 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7773 switch (l2_tunnel_type) {
7774 case RTE_L2_TUNNEL_TYPE_E_TAG:
7775 l2_tn_info->e_tag_fwd_en = FALSE;
7776 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7779 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7788 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7789 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7792 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7794 uint32_t vmtir, vmvir;
7795 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7797 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7799 "VF id %u should be less than %u",
7805 if (hw->mac.type != ixgbe_mac_X550 &&
7806 hw->mac.type != ixgbe_mac_X550EM_x &&
7807 hw->mac.type != ixgbe_mac_X550EM_a) {
7812 vmtir = l2_tunnel->tunnel_id;
7816 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7818 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7819 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7821 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7822 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7827 /* Enable l2 tunnel tag insertion */
7829 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7830 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7834 switch (l2_tunnel->l2_tunnel_type) {
7835 case RTE_L2_TUNNEL_TYPE_E_TAG:
7836 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7839 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7847 /* Disable l2 tunnel tag insertion */
7849 ixgbe_dev_l2_tunnel_insertion_disable
7850 (struct rte_eth_dev *dev,
7851 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7855 switch (l2_tunnel->l2_tunnel_type) {
7856 case RTE_L2_TUNNEL_TYPE_E_TAG:
7857 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7860 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7869 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7874 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7876 if (hw->mac.type != ixgbe_mac_X550 &&
7877 hw->mac.type != ixgbe_mac_X550EM_x &&
7878 hw->mac.type != ixgbe_mac_X550EM_a) {
7882 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7884 qde |= IXGBE_QDE_STRIP_TAG;
7886 qde &= ~IXGBE_QDE_STRIP_TAG;
7887 qde &= ~IXGBE_QDE_READ;
7888 qde |= IXGBE_QDE_WRITE;
7889 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7894 /* Enable l2 tunnel tag stripping */
7896 ixgbe_dev_l2_tunnel_stripping_enable
7897 (struct rte_eth_dev *dev,
7898 enum rte_eth_tunnel_type l2_tunnel_type)
7902 switch (l2_tunnel_type) {
7903 case RTE_L2_TUNNEL_TYPE_E_TAG:
7904 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7907 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7915 /* Disable l2 tunnel tag stripping */
7917 ixgbe_dev_l2_tunnel_stripping_disable
7918 (struct rte_eth_dev *dev,
7919 enum rte_eth_tunnel_type l2_tunnel_type)
7923 switch (l2_tunnel_type) {
7924 case RTE_L2_TUNNEL_TYPE_E_TAG:
7925 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7928 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7936 /* Enable/disable l2 tunnel offload functions */
7938 ixgbe_dev_l2_tunnel_offload_set
7939 (struct rte_eth_dev *dev,
7940 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7946 if (l2_tunnel == NULL)
7950 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7952 ret = ixgbe_dev_l2_tunnel_enable(
7954 l2_tunnel->l2_tunnel_type);
7956 ret = ixgbe_dev_l2_tunnel_disable(
7958 l2_tunnel->l2_tunnel_type);
7961 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7963 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7967 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7972 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7974 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7976 l2_tunnel->l2_tunnel_type);
7978 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7980 l2_tunnel->l2_tunnel_type);
7983 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7985 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7987 l2_tunnel->l2_tunnel_type);
7989 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7991 l2_tunnel->l2_tunnel_type);
7998 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8001 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8002 IXGBE_WRITE_FLUSH(hw);
8007 /* There's only one register for VxLAN UDP port.
8008 * So, we cannot add several ports. Will update it.
8011 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8015 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8019 return ixgbe_update_vxlan_port(hw, port);
8022 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8023 * UDP port, it must have a value.
8024 * So, will reset it to the original value 0.
8027 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8032 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8034 if (cur_port != port) {
8035 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8039 return ixgbe_update_vxlan_port(hw, 0);
8042 /* Add UDP tunneling port */
8044 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8045 struct rte_eth_udp_tunnel *udp_tunnel)
8048 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8050 if (hw->mac.type != ixgbe_mac_X550 &&
8051 hw->mac.type != ixgbe_mac_X550EM_x &&
8052 hw->mac.type != ixgbe_mac_X550EM_a) {
8056 if (udp_tunnel == NULL)
8059 switch (udp_tunnel->prot_type) {
8060 case RTE_TUNNEL_TYPE_VXLAN:
8061 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8064 case RTE_TUNNEL_TYPE_GENEVE:
8065 case RTE_TUNNEL_TYPE_TEREDO:
8066 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8071 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8079 /* Remove UDP tunneling port */
8081 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8082 struct rte_eth_udp_tunnel *udp_tunnel)
8085 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8087 if (hw->mac.type != ixgbe_mac_X550 &&
8088 hw->mac.type != ixgbe_mac_X550EM_x &&
8089 hw->mac.type != ixgbe_mac_X550EM_a) {
8093 if (udp_tunnel == NULL)
8096 switch (udp_tunnel->prot_type) {
8097 case RTE_TUNNEL_TYPE_VXLAN:
8098 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8100 case RTE_TUNNEL_TYPE_GENEVE:
8101 case RTE_TUNNEL_TYPE_TEREDO:
8102 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8106 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8115 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8117 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8119 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8123 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8125 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8127 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8130 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8132 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8135 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8138 /* PF reset VF event */
8139 if (in_msg == IXGBE_PF_CONTROL_MSG)
8140 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
8144 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8147 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8148 struct ixgbe_interrupt *intr =
8149 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8150 ixgbevf_intr_disable(hw);
8152 /* read-on-clear nic registers here */
8153 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8156 /* only one misc vector supported - mailbox */
8157 eicr &= IXGBE_VTEICR_MASK;
8158 if (eicr == IXGBE_MISC_VEC_ID)
8159 intr->flags |= IXGBE_FLAG_MAILBOX;
8165 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8167 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8168 struct ixgbe_interrupt *intr =
8169 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8171 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8172 ixgbevf_mbx_process(dev);
8173 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8176 ixgbevf_intr_enable(hw);
8182 ixgbevf_dev_interrupt_handler(void *param)
8184 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8186 ixgbevf_dev_interrupt_get_status(dev);
8187 ixgbevf_dev_interrupt_action(dev);
8191 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8192 * @hw: pointer to hardware structure
8194 * Stops the transmit data path and waits for the HW to internally empty
8195 * the Tx security block
8197 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8199 #define IXGBE_MAX_SECTX_POLL 40
8204 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8205 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8206 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8207 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8208 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8209 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8211 /* Use interrupt-safe sleep just in case */
8215 /* For informational purposes only */
8216 if (i >= IXGBE_MAX_SECTX_POLL)
8217 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8218 "path fully disabled. Continuing with init.");
8220 return IXGBE_SUCCESS;
8224 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8225 * @hw: pointer to hardware structure
8227 * Enables the transmit data path.
8229 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8233 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8234 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8235 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8236 IXGBE_WRITE_FLUSH(hw);
8238 return IXGBE_SUCCESS;
8242 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
8244 struct ixgbe_hw *hw;
8245 struct rte_eth_dev *dev;
8248 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8250 dev = &rte_eth_devices[port];
8252 if (!is_device_supported(dev, &rte_ixgbe_pmd))
8255 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8257 /* Stop the data paths */
8258 if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8262 * As no ixgbe_disable_sec_rx_path equivalent is
8263 * implemented for tx in the base code, and we are
8264 * not allowed to modify the base code in DPDK, so
8265 * just call the hand-written one directly for now.
8266 * The hardware support has been checked by
8267 * ixgbe_disable_sec_rx_path().
8269 ixgbe_disable_sec_tx_path_generic(hw);
8271 /* Enable Ethernet CRC (required by MACsec offload) */
8272 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8273 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8274 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8276 /* Enable the TX and RX crypto engines */
8277 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8278 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8279 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8281 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8282 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8283 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8285 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8286 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8288 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8290 /* Enable SA lookup */
8291 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8292 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8293 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8294 IXGBE_LSECTXCTRL_AUTH;
8295 ctrl |= IXGBE_LSECTXCTRL_AISCI;
8296 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8297 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8298 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8300 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8301 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8302 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8303 ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8305 ctrl |= IXGBE_LSECRXCTRL_RP;
8307 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8308 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8310 /* Start the data paths */
8311 ixgbe_enable_sec_rx_path(hw);
8314 * As no ixgbe_enable_sec_rx_path equivalent is
8315 * implemented for tx in the base code, and we are
8316 * not allowed to modify the base code in DPDK, so
8317 * just call the hand-written one directly for now.
8319 ixgbe_enable_sec_tx_path_generic(hw);
8325 rte_pmd_ixgbe_macsec_disable(uint8_t port)
8327 struct ixgbe_hw *hw;
8328 struct rte_eth_dev *dev;
8331 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8333 dev = &rte_eth_devices[port];
8335 if (!is_device_supported(dev, &rte_ixgbe_pmd))
8338 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8340 /* Stop the data paths */
8341 if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8345 * As no ixgbe_disable_sec_rx_path equivalent is
8346 * implemented for tx in the base code, and we are
8347 * not allowed to modify the base code in DPDK, so
8348 * just call the hand-written one directly for now.
8349 * The hardware support has been checked by
8350 * ixgbe_disable_sec_rx_path().
8352 ixgbe_disable_sec_tx_path_generic(hw);
8354 /* Disable the TX and RX crypto engines */
8355 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8356 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8357 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8359 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8360 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8361 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8363 /* Disable SA lookup */
8364 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8365 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8366 ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8367 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8369 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8370 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8371 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8372 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8374 /* Start the data paths */
8375 ixgbe_enable_sec_rx_path(hw);
8378 * As no ixgbe_enable_sec_rx_path equivalent is
8379 * implemented for tx in the base code, and we are
8380 * not allowed to modify the base code in DPDK, so
8381 * just call the hand-written one directly for now.
8383 ixgbe_enable_sec_tx_path_generic(hw);
8389 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
8391 struct ixgbe_hw *hw;
8392 struct rte_eth_dev *dev;
8395 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8397 dev = &rte_eth_devices[port];
8399 if (!is_device_supported(dev, &rte_ixgbe_pmd))
8402 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8404 ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8405 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
8407 ctrl = mac[4] | (mac[5] << 8);
8408 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
8414 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
8416 struct ixgbe_hw *hw;
8417 struct rte_eth_dev *dev;
8420 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8422 dev = &rte_eth_devices[port];
8424 if (!is_device_supported(dev, &rte_ixgbe_pmd))
8427 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8429 ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8430 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
8432 pi = rte_cpu_to_be_16(pi);
8433 ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
8434 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
8440 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8441 uint32_t pn, uint8_t *key)
8443 struct ixgbe_hw *hw;
8444 struct rte_eth_dev *dev;
8447 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8449 dev = &rte_eth_devices[port];
8451 if (!is_device_supported(dev, &rte_ixgbe_pmd))
8454 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8456 if (idx != 0 && idx != 1)
8462 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8464 /* Set the PN and key */
8465 pn = rte_cpu_to_be_32(pn);
8467 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8469 for (i = 0; i < 4; i++) {
8470 ctrl = (key[i * 4 + 0] << 0) |
8471 (key[i * 4 + 1] << 8) |
8472 (key[i * 4 + 2] << 16) |
8473 (key[i * 4 + 3] << 24);
8474 IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8477 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8479 for (i = 0; i < 4; i++) {
8480 ctrl = (key[i * 4 + 0] << 0) |
8481 (key[i * 4 + 1] << 8) |
8482 (key[i * 4 + 2] << 16) |
8483 (key[i * 4 + 3] << 24);
8484 IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8488 /* Set AN and select the SA */
8489 ctrl = (an << idx * 2) | (idx << 4);
8490 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8496 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8497 uint32_t pn, uint8_t *key)
8499 struct ixgbe_hw *hw;
8500 struct rte_eth_dev *dev;
8503 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8505 dev = &rte_eth_devices[port];
8507 if (!is_device_supported(dev, &rte_ixgbe_pmd))
8510 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8512 if (idx != 0 && idx != 1)
8519 pn = rte_cpu_to_be_32(pn);
8520 IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8523 for (i = 0; i < 4; i++) {
8524 ctrl = (key[i * 4 + 0] << 0) |
8525 (key[i * 4 + 1] << 8) |
8526 (key[i * 4 + 2] << 16) |
8527 (key[i * 4 + 3] << 24);
8528 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8531 /* Set the AN and validate the SA */
8532 ctrl = an | (1 << 2);
8533 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8538 /* restore n-tuple filter */
8540 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8542 struct ixgbe_filter_info *filter_info =
8543 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8544 struct ixgbe_5tuple_filter *node;
8546 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8547 ixgbe_inject_5tuple_filter(dev, node);
8551 /* restore ethernet type filter */
8553 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8555 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8556 struct ixgbe_filter_info *filter_info =
8557 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8560 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8561 if (filter_info->ethertype_mask & (1 << i)) {
8562 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8563 filter_info->ethertype_filters[i].etqf);
8564 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8565 filter_info->ethertype_filters[i].etqs);
8566 IXGBE_WRITE_FLUSH(hw);
8571 /* restore SYN filter */
8573 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8575 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8576 struct ixgbe_filter_info *filter_info =
8577 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8580 synqf = filter_info->syn_info;
8582 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8583 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8584 IXGBE_WRITE_FLUSH(hw);
8588 /* restore L2 tunnel filter */
8590 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8592 struct ixgbe_l2_tn_info *l2_tn_info =
8593 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8594 struct ixgbe_l2_tn_filter *node;
8595 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8597 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8598 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8599 l2_tn_conf.tunnel_id = node->key.tn_id;
8600 l2_tn_conf.pool = node->pool;
8601 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8606 ixgbe_filter_restore(struct rte_eth_dev *dev)
8608 ixgbe_ntuple_filter_restore(dev);
8609 ixgbe_ethertype_filter_restore(dev);
8610 ixgbe_syn_filter_restore(dev);
8611 ixgbe_fdir_filter_restore(dev);
8612 ixgbe_l2_tn_filter_restore(dev);
8618 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8620 struct ixgbe_l2_tn_info *l2_tn_info =
8621 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8622 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8624 if (l2_tn_info->e_tag_en)
8625 (void)ixgbe_e_tag_enable(hw);
8627 if (l2_tn_info->e_tag_fwd_en)
8628 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8630 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8633 /* remove all the n-tuple filters */
8635 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8637 struct ixgbe_filter_info *filter_info =
8638 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8639 struct ixgbe_5tuple_filter *p_5tuple;
8641 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8642 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8645 /* remove all the ether type filters */
8647 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8649 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8650 struct ixgbe_filter_info *filter_info =
8651 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8654 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8655 if (filter_info->ethertype_mask & (1 << i) &&
8656 !filter_info->ethertype_filters[i].conf) {
8657 (void)ixgbe_ethertype_filter_remove(filter_info,
8659 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8660 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8661 IXGBE_WRITE_FLUSH(hw);
8666 /* remove the SYN filter */
8668 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8670 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8671 struct ixgbe_filter_info *filter_info =
8672 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8674 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8675 filter_info->syn_info = 0;
8677 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8678 IXGBE_WRITE_FLUSH(hw);
8682 /* remove all the L2 tunnel filters */
8684 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8686 struct ixgbe_l2_tn_info *l2_tn_info =
8687 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8688 struct ixgbe_l2_tn_filter *l2_tn_filter;
8689 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8692 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8693 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8694 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8695 l2_tn_conf.pool = l2_tn_filter->pool;
8696 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8705 rte_pmd_ixgbe_set_tc_bw_alloc(uint8_t port,
8709 struct rte_eth_dev *dev;
8710 struct ixgbe_dcb_config *dcb_config;
8711 struct ixgbe_dcb_tc_config *tc;
8712 struct rte_eth_conf *eth_conf;
8713 struct ixgbe_bw_conf *bw_conf;
8718 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8720 dev = &rte_eth_devices[port];
8722 if (!is_device_supported(dev, &rte_ixgbe_pmd))
8725 if (tc_num > IXGBE_DCB_MAX_TRAFFIC_CLASS) {
8726 PMD_DRV_LOG(ERR, "TCs should be no more than %d.",
8727 IXGBE_DCB_MAX_TRAFFIC_CLASS);
8731 dcb_config = IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
8732 bw_conf = IXGBE_DEV_PRIVATE_TO_BW_CONF(dev->data->dev_private);
8733 eth_conf = &dev->data->dev_conf;
8735 if (eth_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
8736 nb_tcs = eth_conf->tx_adv_conf.dcb_tx_conf.nb_tcs;
8737 } else if (eth_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
8738 if (eth_conf->tx_adv_conf.vmdq_dcb_tx_conf.nb_queue_pools ==
8747 if (nb_tcs != tc_num) {
8749 "Weight should be set for all %d enabled TCs.",
8755 for (i = 0; i < nb_tcs; i++)
8756 sum += bw_weight[i];
8759 "The summary of the TC weight should be 100.");
8763 for (i = 0; i < nb_tcs; i++) {
8764 tc = &dcb_config->tc_config[i];
8765 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = bw_weight[i];
8767 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
8768 tc = &dcb_config->tc_config[i];
8769 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
8772 bw_conf->tc_num = nb_tcs;
8777 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
8778 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8779 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8780 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
8781 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8782 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");