4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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14 * notice, this list of conditions and the following disclaimer in
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
64 #include "ixgbe_logs.h"
65 #include "base/ixgbe_api.h"
66 #include "base/ixgbe_vf.h"
67 #include "base/ixgbe_common.h"
68 #include "ixgbe_ethdev.h"
69 #include "ixgbe_bypass.h"
70 #include "ixgbe_rxtx.h"
71 #include "base/ixgbe_type.h"
72 #include "base/ixgbe_phy.h"
73 #include "ixgbe_regs.h"
76 * High threshold controlling when to start sending XOFF frames. Must be at
77 * least 8 bytes less than receive packet buffer size. This value is in units
80 #define IXGBE_FC_HI 0x80
83 * Low threshold controlling when to start sending XON frames. This value is
84 * in units of 1024 bytes.
86 #define IXGBE_FC_LO 0x40
88 /* Default minimum inter-interrupt interval for EITR configuration */
89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
91 /* Timer value included in XOFF frames. */
92 #define IXGBE_FC_PAUSE 0x680
94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
95 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
96 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
98 #define IXGBE_MMW_SIZE_DEFAULT 0x4
99 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
100 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
103 * Default values for RX/TX configuration
105 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
106 #define IXGBE_DEFAULT_RX_PTHRESH 8
107 #define IXGBE_DEFAULT_RX_HTHRESH 8
108 #define IXGBE_DEFAULT_RX_WTHRESH 0
110 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
111 #define IXGBE_DEFAULT_TX_PTHRESH 32
112 #define IXGBE_DEFAULT_TX_HTHRESH 0
113 #define IXGBE_DEFAULT_TX_WTHRESH 0
114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
116 /* Bit shift and mask */
117 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
118 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
119 #define IXGBE_8_BIT_WIDTH CHAR_BIT
120 #define IXGBE_8_BIT_MASK UINT8_MAX
122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
126 #define IXGBE_HKEY_MAX_INDEX 10
128 /* Additional timesync values. */
129 #define IXGBE_TIMINCA_16NS_SHIFT 24
130 #define IXGBE_TIMINCA_INCVALUE 16000000
131 #define IXGBE_TIMINCA_INIT ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
132 | IXGBE_TIMINCA_INCVALUE)
134 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
135 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
136 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
137 static int ixgbe_dev_start(struct rte_eth_dev *dev);
138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
139 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
140 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
142 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
143 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
144 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
145 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
146 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
147 int wait_to_complete);
148 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
149 struct rte_eth_stats *stats);
150 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
151 struct rte_eth_xstats *xstats, unsigned n);
152 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
153 struct rte_eth_xstats *xstats, unsigned n);
154 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
155 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
156 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
160 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
161 struct rte_eth_dev_info *dev_info);
162 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
163 struct rte_eth_dev_info *dev_info);
164 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
166 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
167 uint16_t vlan_id, int on);
168 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
169 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
170 uint16_t queue, bool on);
171 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
173 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
174 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
175 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
176 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
177 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
179 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
180 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
181 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
182 struct rte_eth_fc_conf *fc_conf);
183 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
184 struct rte_eth_fc_conf *fc_conf);
185 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
186 struct rte_eth_pfc_conf *pfc_conf);
187 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
188 struct rte_eth_rss_reta_entry64 *reta_conf,
190 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
191 struct rte_eth_rss_reta_entry64 *reta_conf,
193 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
194 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
195 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
196 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
197 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
198 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
200 static void ixgbe_dev_interrupt_delayed_handler(void *param);
201 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
202 uint32_t index, uint32_t pool);
203 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
204 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
205 struct ether_addr *mac_addr);
206 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
208 /* For Virtual Function support */
209 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
210 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
211 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
212 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
213 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
214 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
215 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
216 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
217 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
218 struct rte_eth_stats *stats);
219 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
220 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
221 uint16_t vlan_id, int on);
222 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
223 uint16_t queue, int on);
224 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
225 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
226 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
228 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
230 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
231 uint8_t queue, uint8_t msix_vector);
232 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
234 /* For Eth VMDQ APIs support */
235 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
236 ether_addr* mac_addr,uint8_t on);
237 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
238 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
239 uint16_t rx_mask, uint8_t on);
240 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
241 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
242 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
243 uint64_t pool_mask,uint8_t vlan_on);
244 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
245 struct rte_eth_mirror_conf *mirror_conf,
246 uint8_t rule_id, uint8_t on);
247 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
249 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
251 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
253 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
254 uint8_t queue, uint8_t msix_vector);
255 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
257 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
258 uint16_t queue_idx, uint16_t tx_rate);
259 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
260 uint16_t tx_rate, uint64_t q_msk);
262 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
263 struct ether_addr *mac_addr,
264 uint32_t index, uint32_t pool);
265 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
266 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
267 struct ether_addr *mac_addr);
268 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
269 struct rte_eth_syn_filter *filter,
271 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
272 struct rte_eth_syn_filter *filter);
273 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
274 enum rte_filter_op filter_op,
276 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
277 struct ixgbe_5tuple_filter *filter);
278 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
279 struct ixgbe_5tuple_filter *filter);
280 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
281 struct rte_eth_ntuple_filter *filter,
283 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
284 enum rte_filter_op filter_op,
286 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
287 struct rte_eth_ntuple_filter *filter);
288 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
289 struct rte_eth_ethertype_filter *filter,
291 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
292 enum rte_filter_op filter_op,
294 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
295 struct rte_eth_ethertype_filter *filter);
296 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
297 enum rte_filter_type filter_type,
298 enum rte_filter_op filter_op,
300 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
302 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
303 struct ether_addr *mc_addr_set,
304 uint32_t nb_mc_addr);
305 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
306 struct rte_eth_dcb_info *dcb_info);
308 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
309 static int ixgbe_get_regs(struct rte_eth_dev *dev,
310 struct rte_dev_reg_info *regs);
311 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
312 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
313 struct rte_dev_eeprom_info *eeprom);
314 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
315 struct rte_dev_eeprom_info *eeprom);
317 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
318 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
319 struct rte_dev_reg_info *regs);
321 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
322 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
323 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
324 struct timespec *timestamp,
326 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
327 struct timespec *timestamp);
330 * Define VF Stats MACRO for Non "cleared on read" register
332 #define UPDATE_VF_STAT(reg, last, cur) \
334 uint32_t latest = IXGBE_READ_REG(hw, reg); \
335 cur += (latest - last) & UINT_MAX; \
339 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
341 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
342 u64 new_msb = IXGBE_READ_REG(hw, msb); \
343 u64 latest = ((new_msb << 32) | new_lsb); \
344 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
348 #define IXGBE_SET_HWSTRIP(h, q) do{\
349 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
350 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
351 (h)->bitmap[idx] |= 1 << bit;\
354 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
355 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
356 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
357 (h)->bitmap[idx] &= ~(1 << bit);\
360 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
361 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
362 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
363 (r) = (h)->bitmap[idx] >> bit & 1;\
367 * The set of PCI devices this driver supports
369 static const struct rte_pci_id pci_id_ixgbe_map[] = {
371 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
372 #include "rte_pci_dev_ids.h"
374 { .vendor_id = 0, /* sentinel */ },
379 * The set of PCI devices this driver supports (for 82599 VF)
381 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
383 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
384 #include "rte_pci_dev_ids.h"
385 { .vendor_id = 0, /* sentinel */ },
389 static const struct rte_eth_desc_lim rx_desc_lim = {
390 .nb_max = IXGBE_MAX_RING_DESC,
391 .nb_min = IXGBE_MIN_RING_DESC,
392 .nb_align = IXGBE_RXD_ALIGN,
395 static const struct rte_eth_desc_lim tx_desc_lim = {
396 .nb_max = IXGBE_MAX_RING_DESC,
397 .nb_min = IXGBE_MIN_RING_DESC,
398 .nb_align = IXGBE_TXD_ALIGN,
401 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
402 .dev_configure = ixgbe_dev_configure,
403 .dev_start = ixgbe_dev_start,
404 .dev_stop = ixgbe_dev_stop,
405 .dev_set_link_up = ixgbe_dev_set_link_up,
406 .dev_set_link_down = ixgbe_dev_set_link_down,
407 .dev_close = ixgbe_dev_close,
408 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
409 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
410 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
411 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
412 .link_update = ixgbe_dev_link_update,
413 .stats_get = ixgbe_dev_stats_get,
414 .xstats_get = ixgbe_dev_xstats_get,
415 .stats_reset = ixgbe_dev_stats_reset,
416 .xstats_reset = ixgbe_dev_xstats_reset,
417 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
418 .dev_infos_get = ixgbe_dev_info_get,
419 .mtu_set = ixgbe_dev_mtu_set,
420 .vlan_filter_set = ixgbe_vlan_filter_set,
421 .vlan_tpid_set = ixgbe_vlan_tpid_set,
422 .vlan_offload_set = ixgbe_vlan_offload_set,
423 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
424 .rx_queue_start = ixgbe_dev_rx_queue_start,
425 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
426 .tx_queue_start = ixgbe_dev_tx_queue_start,
427 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
428 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
429 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
430 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
431 .rx_queue_release = ixgbe_dev_rx_queue_release,
432 .rx_queue_count = ixgbe_dev_rx_queue_count,
433 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
434 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
435 .tx_queue_release = ixgbe_dev_tx_queue_release,
436 .dev_led_on = ixgbe_dev_led_on,
437 .dev_led_off = ixgbe_dev_led_off,
438 .flow_ctrl_get = ixgbe_flow_ctrl_get,
439 .flow_ctrl_set = ixgbe_flow_ctrl_set,
440 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
441 .mac_addr_add = ixgbe_add_rar,
442 .mac_addr_remove = ixgbe_remove_rar,
443 .mac_addr_set = ixgbe_set_default_mac_addr,
444 .uc_hash_table_set = ixgbe_uc_hash_table_set,
445 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
446 .mirror_rule_set = ixgbe_mirror_rule_set,
447 .mirror_rule_reset = ixgbe_mirror_rule_reset,
448 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
449 .set_vf_rx = ixgbe_set_pool_rx,
450 .set_vf_tx = ixgbe_set_pool_tx,
451 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
452 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
453 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
454 .reta_update = ixgbe_dev_rss_reta_update,
455 .reta_query = ixgbe_dev_rss_reta_query,
456 #ifdef RTE_NIC_BYPASS
457 .bypass_init = ixgbe_bypass_init,
458 .bypass_state_set = ixgbe_bypass_state_store,
459 .bypass_state_show = ixgbe_bypass_state_show,
460 .bypass_event_set = ixgbe_bypass_event_store,
461 .bypass_event_show = ixgbe_bypass_event_show,
462 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
463 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
464 .bypass_ver_show = ixgbe_bypass_ver_show,
465 .bypass_wd_reset = ixgbe_bypass_wd_reset,
466 #endif /* RTE_NIC_BYPASS */
467 .rss_hash_update = ixgbe_dev_rss_hash_update,
468 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
469 .filter_ctrl = ixgbe_dev_filter_ctrl,
470 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
471 .rxq_info_get = ixgbe_rxq_info_get,
472 .txq_info_get = ixgbe_txq_info_get,
473 .timesync_enable = ixgbe_timesync_enable,
474 .timesync_disable = ixgbe_timesync_disable,
475 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
476 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
477 .get_reg_length = ixgbe_get_reg_length,
478 .get_reg = ixgbe_get_regs,
479 .get_eeprom_length = ixgbe_get_eeprom_length,
480 .get_eeprom = ixgbe_get_eeprom,
481 .set_eeprom = ixgbe_set_eeprom,
482 .get_dcb_info = ixgbe_dev_get_dcb_info,
486 * dev_ops for virtual function, bare necessities for basic vf
487 * operation have been implemented
489 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
490 .dev_configure = ixgbevf_dev_configure,
491 .dev_start = ixgbevf_dev_start,
492 .dev_stop = ixgbevf_dev_stop,
493 .link_update = ixgbe_dev_link_update,
494 .stats_get = ixgbevf_dev_stats_get,
495 .xstats_get = ixgbevf_dev_xstats_get,
496 .stats_reset = ixgbevf_dev_stats_reset,
497 .xstats_reset = ixgbevf_dev_stats_reset,
498 .dev_close = ixgbevf_dev_close,
499 .dev_infos_get = ixgbevf_dev_info_get,
500 .mtu_set = ixgbevf_dev_set_mtu,
501 .vlan_filter_set = ixgbevf_vlan_filter_set,
502 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
503 .vlan_offload_set = ixgbevf_vlan_offload_set,
504 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
505 .rx_queue_release = ixgbe_dev_rx_queue_release,
506 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
507 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
508 .tx_queue_release = ixgbe_dev_tx_queue_release,
509 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
510 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
511 .mac_addr_add = ixgbevf_add_mac_addr,
512 .mac_addr_remove = ixgbevf_remove_mac_addr,
513 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
514 .rxq_info_get = ixgbe_rxq_info_get,
515 .txq_info_get = ixgbe_txq_info_get,
516 .mac_addr_set = ixgbevf_set_default_mac_addr,
517 .get_reg_length = ixgbevf_get_reg_length,
518 .get_reg = ixgbevf_get_regs,
519 .reta_update = ixgbe_dev_rss_reta_update,
520 .reta_query = ixgbe_dev_rss_reta_query,
521 .rss_hash_update = ixgbe_dev_rss_hash_update,
522 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
525 /* store statistics names and its offset in stats structure */
526 struct rte_ixgbe_xstats_name_off {
527 char name[RTE_ETH_XSTATS_NAME_SIZE];
531 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
532 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
533 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
534 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
535 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
536 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
537 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
538 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
539 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
540 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
541 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
542 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
543 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
544 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
545 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
546 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
548 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
550 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
551 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
552 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
553 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
554 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
555 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
556 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
557 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
558 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
559 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
560 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
561 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
562 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
563 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
564 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
565 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
566 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
568 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
570 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
571 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
572 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
573 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
575 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
577 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
579 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
581 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
583 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
585 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
588 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
589 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
590 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
592 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
593 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
594 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
595 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
596 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
598 {"rx_fcoe_no_direct_data_placement_ext_buff",
599 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
601 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
603 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
605 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
607 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
609 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
612 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
613 sizeof(rte_ixgbe_stats_strings[0]))
615 /* Per-queue statistics */
616 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
617 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
618 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
619 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
620 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
623 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
624 sizeof(rte_ixgbe_rxq_strings[0]))
626 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
627 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
628 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
629 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
633 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
634 sizeof(rte_ixgbe_txq_strings[0]))
636 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
637 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
640 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
641 sizeof(rte_ixgbevf_stats_strings[0]))
644 * Atomically reads the link status information from global
645 * structure rte_eth_dev.
648 * - Pointer to the structure rte_eth_dev to read from.
649 * - Pointer to the buffer to be saved with the link status.
652 * - On success, zero.
653 * - On failure, negative value.
656 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
657 struct rte_eth_link *link)
659 struct rte_eth_link *dst = link;
660 struct rte_eth_link *src = &(dev->data->dev_link);
662 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
663 *(uint64_t *)src) == 0)
670 * Atomically writes the link status information into global
671 * structure rte_eth_dev.
674 * - Pointer to the structure rte_eth_dev to read from.
675 * - Pointer to the buffer to be saved with the link status.
678 * - On success, zero.
679 * - On failure, negative value.
682 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
683 struct rte_eth_link *link)
685 struct rte_eth_link *dst = &(dev->data->dev_link);
686 struct rte_eth_link *src = link;
688 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
689 *(uint64_t *)src) == 0)
696 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
699 ixgbe_is_sfp(struct ixgbe_hw *hw)
701 switch (hw->phy.type) {
702 case ixgbe_phy_sfp_avago:
703 case ixgbe_phy_sfp_ftl:
704 case ixgbe_phy_sfp_intel:
705 case ixgbe_phy_sfp_unknown:
706 case ixgbe_phy_sfp_passive_tyco:
707 case ixgbe_phy_sfp_passive_unknown:
714 static inline int32_t
715 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
720 status = ixgbe_reset_hw(hw);
722 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
723 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
724 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
725 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
726 IXGBE_WRITE_FLUSH(hw);
732 ixgbe_enable_intr(struct rte_eth_dev *dev)
734 struct ixgbe_interrupt *intr =
735 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
736 struct ixgbe_hw *hw =
737 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
739 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
740 IXGBE_WRITE_FLUSH(hw);
744 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
747 ixgbe_disable_intr(struct ixgbe_hw *hw)
749 PMD_INIT_FUNC_TRACE();
751 if (hw->mac.type == ixgbe_mac_82598EB) {
752 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
754 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
755 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
756 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
758 IXGBE_WRITE_FLUSH(hw);
762 * This function resets queue statistics mapping registers.
763 * From Niantic datasheet, Initialization of Statistics section:
764 * "...if software requires the queue counters, the RQSMR and TQSM registers
765 * must be re-programmed following a device reset.
768 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
772 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
773 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
774 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
780 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
785 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
786 #define NB_QMAP_FIELDS_PER_QSM_REG 4
787 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
789 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
790 struct ixgbe_stat_mapping_registers *stat_mappings =
791 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
792 uint32_t qsmr_mask = 0;
793 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
797 if ((hw->mac.type != ixgbe_mac_82599EB) &&
798 (hw->mac.type != ixgbe_mac_X540) &&
799 (hw->mac.type != ixgbe_mac_X550) &&
800 (hw->mac.type != ixgbe_mac_X550EM_x))
803 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
804 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
807 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
808 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
809 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
812 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
814 /* Now clear any previous stat_idx set */
815 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
817 stat_mappings->tqsm[n] &= ~clearing_mask;
819 stat_mappings->rqsmr[n] &= ~clearing_mask;
821 q_map = (uint32_t)stat_idx;
822 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
823 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
825 stat_mappings->tqsm[n] |= qsmr_mask;
827 stat_mappings->rqsmr[n] |= qsmr_mask;
829 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
830 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
832 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
833 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
835 /* Now write the mapping in the appropriate register */
837 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
838 stat_mappings->rqsmr[n], n);
839 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
842 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
843 stat_mappings->tqsm[n], n);
844 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
850 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
852 struct ixgbe_stat_mapping_registers *stat_mappings =
853 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
854 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
857 /* write whatever was in stat mapping table to the NIC */
858 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
860 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
863 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
868 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
871 struct ixgbe_dcb_tc_config *tc;
872 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
874 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
875 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
876 for (i = 0; i < dcb_max_tc; i++) {
877 tc = &dcb_config->tc_config[i];
878 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
879 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
880 (uint8_t)(100/dcb_max_tc + (i & 1));
881 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
882 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
883 (uint8_t)(100/dcb_max_tc + (i & 1));
884 tc->pfc = ixgbe_dcb_pfc_disabled;
887 /* Initialize default user to priority mapping, UPx->TC0 */
888 tc = &dcb_config->tc_config[0];
889 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
890 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
891 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
892 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
893 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
895 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
896 dcb_config->pfc_mode_enable = false;
897 dcb_config->vt_mode = true;
898 dcb_config->round_robin_enable = false;
899 /* support all DCB capabilities in 82599 */
900 dcb_config->support.capabilities = 0xFF;
902 /*we only support 4 Tcs for X540, X550 */
903 if (hw->mac.type == ixgbe_mac_X540 ||
904 hw->mac.type == ixgbe_mac_X550 ||
905 hw->mac.type == ixgbe_mac_X550EM_x) {
906 dcb_config->num_tcs.pg_tcs = 4;
907 dcb_config->num_tcs.pfc_tcs = 4;
912 * Ensure that all locks are released before first NVM or PHY access
915 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
920 * Phy lock should not fail in this early stage. If this is the case,
921 * it is due to an improper exit of the application.
922 * So force the release of the faulty lock. Release of common lock
923 * is done automatically by swfw_sync function.
925 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
926 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
927 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
929 ixgbe_release_swfw_semaphore(hw, mask);
932 * These ones are more tricky since they are common to all ports; but
933 * swfw_sync retries last long enough (1s) to be almost sure that if
934 * lock can not be taken it is due to an improper lock of the
937 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
938 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
939 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
941 ixgbe_release_swfw_semaphore(hw, mask);
945 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
946 * It returns 0 on success.
949 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
951 struct rte_pci_device *pci_dev;
952 struct ixgbe_hw *hw =
953 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
954 struct ixgbe_vfta * shadow_vfta =
955 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
956 struct ixgbe_hwstrip *hwstrip =
957 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
958 struct ixgbe_dcb_config *dcb_config =
959 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
960 struct ixgbe_filter_info *filter_info =
961 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
966 PMD_INIT_FUNC_TRACE();
968 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
969 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
970 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
973 * For secondary processes, we don't initialise any further as primary
974 * has already done this work. Only check we don't need a different
975 * RX and TX function.
977 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
978 struct ixgbe_tx_queue *txq;
979 /* TX queue function in primary, set by last queue initialized
980 * Tx queue may not initialized by primary process */
981 if (eth_dev->data->tx_queues) {
982 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
983 ixgbe_set_tx_function(eth_dev, txq);
985 /* Use default TX function if we get here */
986 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
987 "Using default TX function.");
990 ixgbe_set_rx_function(eth_dev);
994 pci_dev = eth_dev->pci_dev;
996 rte_eth_copy_pci_info(eth_dev, pci_dev);
998 /* Vendor and Device ID need to be set before init of shared code */
999 hw->device_id = pci_dev->id.device_id;
1000 hw->vendor_id = pci_dev->id.vendor_id;
1001 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1002 hw->allow_unsupported_sfp = 1;
1004 /* Initialize the shared code (base driver) */
1005 #ifdef RTE_NIC_BYPASS
1006 diag = ixgbe_bypass_init_shared_code(hw);
1008 diag = ixgbe_init_shared_code(hw);
1009 #endif /* RTE_NIC_BYPASS */
1011 if (diag != IXGBE_SUCCESS) {
1012 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1016 /* pick up the PCI bus settings for reporting later */
1017 ixgbe_get_bus_info(hw);
1019 /* Unlock any pending hardware semaphore */
1020 ixgbe_swfw_lock_reset(hw);
1022 /* Initialize DCB configuration*/
1023 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1024 ixgbe_dcb_init(hw,dcb_config);
1025 /* Get Hardware Flow Control setting */
1026 hw->fc.requested_mode = ixgbe_fc_full;
1027 hw->fc.current_mode = ixgbe_fc_full;
1028 hw->fc.pause_time = IXGBE_FC_PAUSE;
1029 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1030 hw->fc.low_water[i] = IXGBE_FC_LO;
1031 hw->fc.high_water[i] = IXGBE_FC_HI;
1033 hw->fc.send_xon = 1;
1035 /* Make sure we have a good EEPROM before we read from it */
1036 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1037 if (diag != IXGBE_SUCCESS) {
1038 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1042 #ifdef RTE_NIC_BYPASS
1043 diag = ixgbe_bypass_init_hw(hw);
1045 diag = ixgbe_init_hw(hw);
1046 #endif /* RTE_NIC_BYPASS */
1049 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1050 * is called too soon after the kernel driver unbinding/binding occurs.
1051 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1052 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1053 * also called. See ixgbe_identify_phy_82599(). The reason for the
1054 * failure is not known, and only occuts when virtualisation features
1055 * are disabled in the bios. A delay of 100ms was found to be enough by
1056 * trial-and-error, and is doubled to be safe.
1058 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1060 diag = ixgbe_init_hw(hw);
1063 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1064 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1065 "LOM. Please be aware there may be issues associated "
1066 "with your hardware.");
1067 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1068 "please contact your Intel or hardware representative "
1069 "who provided you with this hardware.");
1070 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1071 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1073 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1077 /* Reset the hw statistics */
1078 ixgbe_dev_stats_reset(eth_dev);
1080 /* disable interrupt */
1081 ixgbe_disable_intr(hw);
1083 /* reset mappings for queue statistics hw counters*/
1084 ixgbe_reset_qstat_mappings(hw);
1086 /* Allocate memory for storing MAC addresses */
1087 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1088 hw->mac.num_rar_entries, 0);
1089 if (eth_dev->data->mac_addrs == NULL) {
1091 "Failed to allocate %u bytes needed to store "
1093 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1096 /* Copy the permanent MAC address */
1097 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1098 ð_dev->data->mac_addrs[0]);
1100 /* Allocate memory for storing hash filter MAC addresses */
1101 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1102 IXGBE_VMDQ_NUM_UC_MAC, 0);
1103 if (eth_dev->data->hash_mac_addrs == NULL) {
1105 "Failed to allocate %d bytes needed to store MAC addresses",
1106 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1110 /* initialize the vfta */
1111 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1113 /* initialize the hw strip bitmap*/
1114 memset(hwstrip, 0, sizeof(*hwstrip));
1116 /* initialize PF if max_vfs not zero */
1117 ixgbe_pf_host_init(eth_dev);
1119 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1120 /* let hardware know driver is loaded */
1121 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1122 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1123 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1124 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1125 IXGBE_WRITE_FLUSH(hw);
1127 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1128 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1129 (int) hw->mac.type, (int) hw->phy.type,
1130 (int) hw->phy.sfp_type);
1132 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1133 (int) hw->mac.type, (int) hw->phy.type);
1135 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1136 eth_dev->data->port_id, pci_dev->id.vendor_id,
1137 pci_dev->id.device_id);
1139 rte_intr_callback_register(&pci_dev->intr_handle,
1140 ixgbe_dev_interrupt_handler,
1143 /* enable uio/vfio intr/eventfd mapping */
1144 rte_intr_enable(&pci_dev->intr_handle);
1146 /* enable support intr */
1147 ixgbe_enable_intr(eth_dev);
1149 /* initialize 5tuple filter list */
1150 TAILQ_INIT(&filter_info->fivetuple_list);
1151 memset(filter_info->fivetuple_mask, 0,
1152 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1158 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1160 struct rte_pci_device *pci_dev;
1161 struct ixgbe_hw *hw;
1163 PMD_INIT_FUNC_TRACE();
1165 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1168 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1169 pci_dev = eth_dev->pci_dev;
1171 if (hw->adapter_stopped == 0)
1172 ixgbe_dev_close(eth_dev);
1174 eth_dev->dev_ops = NULL;
1175 eth_dev->rx_pkt_burst = NULL;
1176 eth_dev->tx_pkt_burst = NULL;
1178 /* Unlock any pending hardware semaphore */
1179 ixgbe_swfw_lock_reset(hw);
1181 /* disable uio intr before callback unregister */
1182 rte_intr_disable(&(pci_dev->intr_handle));
1183 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1184 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1186 /* uninitialize PF if max_vfs not zero */
1187 ixgbe_pf_host_uninit(eth_dev);
1189 rte_free(eth_dev->data->mac_addrs);
1190 eth_dev->data->mac_addrs = NULL;
1192 rte_free(eth_dev->data->hash_mac_addrs);
1193 eth_dev->data->hash_mac_addrs = NULL;
1199 * Negotiate mailbox API version with the PF.
1200 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1201 * Then we try to negotiate starting with the most recent one.
1202 * If all negotiation attempts fail, then we will proceed with
1203 * the default one (ixgbe_mbox_api_10).
1206 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1210 /* start with highest supported, proceed down */
1211 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1217 i != RTE_DIM(sup_ver) &&
1218 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1224 generate_random_mac_addr(struct ether_addr *mac_addr)
1228 /* Set Organizationally Unique Identifier (OUI) prefix. */
1229 mac_addr->addr_bytes[0] = 0x00;
1230 mac_addr->addr_bytes[1] = 0x09;
1231 mac_addr->addr_bytes[2] = 0xC0;
1232 /* Force indication of locally assigned MAC address. */
1233 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1234 /* Generate the last 3 bytes of the MAC address with a random number. */
1235 random = rte_rand();
1236 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1240 * Virtual Function device init
1243 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1247 struct rte_pci_device *pci_dev;
1248 struct ixgbe_hw *hw =
1249 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1250 struct ixgbe_vfta * shadow_vfta =
1251 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1252 struct ixgbe_hwstrip *hwstrip =
1253 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1254 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1256 PMD_INIT_FUNC_TRACE();
1258 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1259 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1260 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1262 /* for secondary processes, we don't initialise any further as primary
1263 * has already done this work. Only check we don't need a different
1265 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1266 if (eth_dev->data->scattered_rx)
1267 eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1271 pci_dev = eth_dev->pci_dev;
1273 rte_eth_copy_pci_info(eth_dev, pci_dev);
1275 hw->device_id = pci_dev->id.device_id;
1276 hw->vendor_id = pci_dev->id.vendor_id;
1277 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1279 /* initialize the vfta */
1280 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1282 /* initialize the hw strip bitmap*/
1283 memset(hwstrip, 0, sizeof(*hwstrip));
1285 /* Initialize the shared code (base driver) */
1286 diag = ixgbe_init_shared_code(hw);
1287 if (diag != IXGBE_SUCCESS) {
1288 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1292 /* init_mailbox_params */
1293 hw->mbx.ops.init_params(hw);
1295 /* Reset the hw statistics */
1296 ixgbevf_dev_stats_reset(eth_dev);
1298 /* Disable the interrupts for VF */
1299 ixgbevf_intr_disable(hw);
1301 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1302 diag = hw->mac.ops.reset_hw(hw);
1305 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1306 * the underlying PF driver has not assigned a MAC address to the VF.
1307 * In this case, assign a random MAC address.
1309 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1310 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1314 /* negotiate mailbox API version to use with the PF. */
1315 ixgbevf_negotiate_api(hw);
1317 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1318 ixgbevf_get_queues(hw, &tcs, &tc);
1320 /* Allocate memory for storing MAC addresses */
1321 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1322 hw->mac.num_rar_entries, 0);
1323 if (eth_dev->data->mac_addrs == NULL) {
1325 "Failed to allocate %u bytes needed to store "
1327 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1331 /* Generate a random MAC address, if none was assigned by PF. */
1332 if (is_zero_ether_addr(perm_addr)) {
1333 generate_random_mac_addr(perm_addr);
1334 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1336 rte_free(eth_dev->data->mac_addrs);
1337 eth_dev->data->mac_addrs = NULL;
1340 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1341 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1342 "%02x:%02x:%02x:%02x:%02x:%02x",
1343 perm_addr->addr_bytes[0],
1344 perm_addr->addr_bytes[1],
1345 perm_addr->addr_bytes[2],
1346 perm_addr->addr_bytes[3],
1347 perm_addr->addr_bytes[4],
1348 perm_addr->addr_bytes[5]);
1351 /* Copy the permanent MAC address */
1352 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1354 /* reset the hardware with the new settings */
1355 diag = hw->mac.ops.start_hw(hw);
1361 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1365 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1366 eth_dev->data->port_id, pci_dev->id.vendor_id,
1367 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1372 /* Virtual Function device uninit */
1375 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1377 struct ixgbe_hw *hw;
1380 PMD_INIT_FUNC_TRACE();
1382 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1385 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1387 if (hw->adapter_stopped == 0)
1388 ixgbevf_dev_close(eth_dev);
1390 eth_dev->dev_ops = NULL;
1391 eth_dev->rx_pkt_burst = NULL;
1392 eth_dev->tx_pkt_burst = NULL;
1394 /* Disable the interrupts for VF */
1395 ixgbevf_intr_disable(hw);
1397 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1398 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1399 eth_dev->data->rx_queues[i] = NULL;
1401 eth_dev->data->nb_rx_queues = 0;
1403 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1404 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1405 eth_dev->data->tx_queues[i] = NULL;
1407 eth_dev->data->nb_tx_queues = 0;
1409 rte_free(eth_dev->data->mac_addrs);
1410 eth_dev->data->mac_addrs = NULL;
1415 static struct eth_driver rte_ixgbe_pmd = {
1417 .name = "rte_ixgbe_pmd",
1418 .id_table = pci_id_ixgbe_map,
1419 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1420 RTE_PCI_DRV_DETACHABLE,
1422 .eth_dev_init = eth_ixgbe_dev_init,
1423 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1424 .dev_private_size = sizeof(struct ixgbe_adapter),
1428 * virtual function driver struct
1430 static struct eth_driver rte_ixgbevf_pmd = {
1432 .name = "rte_ixgbevf_pmd",
1433 .id_table = pci_id_ixgbevf_map,
1434 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1436 .eth_dev_init = eth_ixgbevf_dev_init,
1437 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1438 .dev_private_size = sizeof(struct ixgbe_adapter),
1442 * Driver initialization routine.
1443 * Invoked once at EAL init time.
1444 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1447 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1449 PMD_INIT_FUNC_TRACE();
1451 rte_eth_driver_register(&rte_ixgbe_pmd);
1456 * VF Driver initialization routine.
1457 * Invoked one at EAL init time.
1458 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1461 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1463 PMD_INIT_FUNC_TRACE();
1465 rte_eth_driver_register(&rte_ixgbevf_pmd);
1470 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1472 struct ixgbe_hw *hw =
1473 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1474 struct ixgbe_vfta * shadow_vfta =
1475 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1480 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1481 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1482 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1487 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1489 /* update local VFTA copy */
1490 shadow_vfta->vfta[vid_idx] = vfta;
1496 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1499 ixgbe_vlan_hw_strip_enable(dev, queue);
1501 ixgbe_vlan_hw_strip_disable(dev, queue);
1505 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1507 struct ixgbe_hw *hw =
1508 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1510 /* Only the high 16-bits is valid */
1511 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1515 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1517 struct ixgbe_hw *hw =
1518 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1521 PMD_INIT_FUNC_TRACE();
1523 /* Filter Table Disable */
1524 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1525 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1527 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1531 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1533 struct ixgbe_hw *hw =
1534 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1535 struct ixgbe_vfta * shadow_vfta =
1536 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1540 PMD_INIT_FUNC_TRACE();
1542 /* Filter Table Enable */
1543 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1544 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1545 vlnctrl |= IXGBE_VLNCTRL_VFE;
1547 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1549 /* write whatever is in local vfta copy */
1550 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1551 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1555 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1557 struct ixgbe_hwstrip *hwstrip =
1558 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1560 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1564 IXGBE_SET_HWSTRIP(hwstrip, queue);
1566 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1570 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1572 struct ixgbe_hw *hw =
1573 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1576 PMD_INIT_FUNC_TRACE();
1578 if (hw->mac.type == ixgbe_mac_82598EB) {
1579 /* No queue level support */
1580 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1584 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1585 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1586 ctrl &= ~IXGBE_RXDCTL_VME;
1587 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1589 /* record those setting for HW strip per queue */
1590 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1594 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1596 struct ixgbe_hw *hw =
1597 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1600 PMD_INIT_FUNC_TRACE();
1602 if (hw->mac.type == ixgbe_mac_82598EB) {
1603 /* No queue level supported */
1604 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1608 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1609 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1610 ctrl |= IXGBE_RXDCTL_VME;
1611 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1613 /* record those setting for HW strip per queue */
1614 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1618 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1620 struct ixgbe_hw *hw =
1621 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1625 PMD_INIT_FUNC_TRACE();
1627 if (hw->mac.type == ixgbe_mac_82598EB) {
1628 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1629 ctrl &= ~IXGBE_VLNCTRL_VME;
1630 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1633 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1634 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1635 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1636 ctrl &= ~IXGBE_RXDCTL_VME;
1637 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1639 /* record those setting for HW strip per queue */
1640 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1646 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1648 struct ixgbe_hw *hw =
1649 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1653 PMD_INIT_FUNC_TRACE();
1655 if (hw->mac.type == ixgbe_mac_82598EB) {
1656 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1657 ctrl |= IXGBE_VLNCTRL_VME;
1658 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1661 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1662 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1663 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1664 ctrl |= IXGBE_RXDCTL_VME;
1665 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1667 /* record those setting for HW strip per queue */
1668 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1674 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1676 struct ixgbe_hw *hw =
1677 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1680 PMD_INIT_FUNC_TRACE();
1682 /* DMATXCTRL: Geric Double VLAN Disable */
1683 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1684 ctrl &= ~IXGBE_DMATXCTL_GDV;
1685 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1687 /* CTRL_EXT: Global Double VLAN Disable */
1688 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1689 ctrl &= ~IXGBE_EXTENDED_VLAN;
1690 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1695 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1697 struct ixgbe_hw *hw =
1698 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1701 PMD_INIT_FUNC_TRACE();
1703 /* DMATXCTRL: Geric Double VLAN Enable */
1704 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1705 ctrl |= IXGBE_DMATXCTL_GDV;
1706 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1708 /* CTRL_EXT: Global Double VLAN Enable */
1709 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1710 ctrl |= IXGBE_EXTENDED_VLAN;
1711 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1714 * VET EXT field in the EXVET register = 0x8100 by default
1715 * So no need to change. Same to VT field of DMATXCTL register
1720 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1722 if(mask & ETH_VLAN_STRIP_MASK){
1723 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1724 ixgbe_vlan_hw_strip_enable_all(dev);
1726 ixgbe_vlan_hw_strip_disable_all(dev);
1729 if(mask & ETH_VLAN_FILTER_MASK){
1730 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1731 ixgbe_vlan_hw_filter_enable(dev);
1733 ixgbe_vlan_hw_filter_disable(dev);
1736 if(mask & ETH_VLAN_EXTEND_MASK){
1737 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1738 ixgbe_vlan_hw_extend_enable(dev);
1740 ixgbe_vlan_hw_extend_disable(dev);
1745 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1747 struct ixgbe_hw *hw =
1748 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1749 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1750 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1751 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1752 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1756 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1761 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1764 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1770 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1771 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1777 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1779 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1780 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1781 uint16_t nb_tx_q = dev->data->nb_rx_queues;
1783 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1784 /* check multi-queue mode */
1785 switch (dev_conf->rxmode.mq_mode) {
1786 case ETH_MQ_RX_VMDQ_DCB:
1787 case ETH_MQ_RX_VMDQ_DCB_RSS:
1788 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1789 PMD_INIT_LOG(ERR, "SRIOV active,"
1790 " unsupported mq_mode rx %d.",
1791 dev_conf->rxmode.mq_mode);
1794 case ETH_MQ_RX_VMDQ_RSS:
1795 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1796 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1797 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1798 PMD_INIT_LOG(ERR, "SRIOV is active,"
1799 " invalid queue number"
1800 " for VMDQ RSS, allowed"
1801 " value are 1, 2 or 4.");
1805 case ETH_MQ_RX_VMDQ_ONLY:
1806 case ETH_MQ_RX_NONE:
1807 /* if nothing mq mode configure, use default scheme */
1808 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1809 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1810 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1812 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1813 /* SRIOV only works in VMDq enable mode */
1814 PMD_INIT_LOG(ERR, "SRIOV is active,"
1815 " wrong mq_mode rx %d.",
1816 dev_conf->rxmode.mq_mode);
1820 switch (dev_conf->txmode.mq_mode) {
1821 case ETH_MQ_TX_VMDQ_DCB:
1822 /* DCB VMDQ in SRIOV mode, not implement yet */
1823 PMD_INIT_LOG(ERR, "SRIOV is active,"
1824 " unsupported VMDQ mq_mode tx %d.",
1825 dev_conf->txmode.mq_mode);
1827 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1828 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1832 /* check valid queue number */
1833 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1834 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1835 PMD_INIT_LOG(ERR, "SRIOV is active,"
1836 " queue number must less equal to %d.",
1837 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1841 /* check configuration for vmdb+dcb mode */
1842 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1843 const struct rte_eth_vmdq_dcb_conf *conf;
1845 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1846 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1847 IXGBE_VMDQ_DCB_NB_QUEUES);
1850 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1851 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1852 conf->nb_queue_pools == ETH_32_POOLS)) {
1853 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1854 " nb_queue_pools must be %d or %d.",
1855 ETH_16_POOLS, ETH_32_POOLS);
1859 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1860 const struct rte_eth_vmdq_dcb_tx_conf *conf;
1862 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1863 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1864 IXGBE_VMDQ_DCB_NB_QUEUES);
1867 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1868 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1869 conf->nb_queue_pools == ETH_32_POOLS)) {
1870 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1871 " nb_queue_pools != %d and"
1872 " nb_queue_pools != %d.",
1873 ETH_16_POOLS, ETH_32_POOLS);
1878 /* For DCB mode check our configuration before we go further */
1879 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1880 const struct rte_eth_dcb_rx_conf *conf;
1882 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1883 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1884 IXGBE_DCB_NB_QUEUES);
1887 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1888 if (!(conf->nb_tcs == ETH_4_TCS ||
1889 conf->nb_tcs == ETH_8_TCS)) {
1890 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1891 " and nb_tcs != %d.",
1892 ETH_4_TCS, ETH_8_TCS);
1897 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1898 const struct rte_eth_dcb_tx_conf *conf;
1900 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1901 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1902 IXGBE_DCB_NB_QUEUES);
1905 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1906 if (!(conf->nb_tcs == ETH_4_TCS ||
1907 conf->nb_tcs == ETH_8_TCS)) {
1908 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1909 " and nb_tcs != %d.",
1910 ETH_4_TCS, ETH_8_TCS);
1919 ixgbe_dev_configure(struct rte_eth_dev *dev)
1921 struct ixgbe_interrupt *intr =
1922 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1923 struct ixgbe_adapter *adapter =
1924 (struct ixgbe_adapter *)dev->data->dev_private;
1927 PMD_INIT_FUNC_TRACE();
1928 /* multipe queue mode checking */
1929 ret = ixgbe_check_mq_mode(dev);
1931 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
1936 /* set flag to update link status after init */
1937 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1940 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1941 * allocation or vector Rx preconditions we will reset it.
1943 adapter->rx_bulk_alloc_allowed = true;
1944 adapter->rx_vec_allowed = true;
1950 * Configure device link speed and setup link.
1951 * It returns 0 on success.
1954 ixgbe_dev_start(struct rte_eth_dev *dev)
1956 struct ixgbe_hw *hw =
1957 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1958 struct ixgbe_vf_info *vfinfo =
1959 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1960 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1961 uint32_t intr_vector = 0;
1962 int err, link_up = 0, negotiate = 0;
1968 PMD_INIT_FUNC_TRACE();
1970 /* IXGBE devices don't support half duplex */
1971 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1972 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1973 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1974 dev->data->dev_conf.link_duplex,
1975 dev->data->port_id);
1980 hw->adapter_stopped = 0;
1981 ixgbe_stop_adapter(hw);
1983 /* reinitialize adapter
1984 * this calls reset and start */
1985 status = ixgbe_pf_reset_hw(hw);
1988 hw->mac.ops.start_hw(hw);
1989 hw->mac.get_link_status = true;
1991 /* configure PF module if SRIOV enabled */
1992 ixgbe_pf_host_configure(dev);
1994 /* check and configure queue intr-vector mapping */
1995 if ((rte_intr_cap_multiple(intr_handle) ||
1996 !RTE_ETH_DEV_SRIOV(dev).active) &&
1997 dev->data->dev_conf.intr_conf.rxq != 0) {
1998 intr_vector = dev->data->nb_rx_queues;
1999 if (rte_intr_efd_enable(intr_handle, intr_vector))
2003 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2004 intr_handle->intr_vec =
2005 rte_zmalloc("intr_vec",
2006 dev->data->nb_rx_queues * sizeof(int), 0);
2007 if (intr_handle->intr_vec == NULL) {
2008 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2009 " intr_vec\n", dev->data->nb_rx_queues);
2014 /* confiugre msix for sleep until rx interrupt */
2015 ixgbe_configure_msix(dev);
2017 /* initialize transmission unit */
2018 ixgbe_dev_tx_init(dev);
2020 /* This can fail when allocating mbufs for descriptor rings */
2021 err = ixgbe_dev_rx_init(dev);
2023 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2027 err = ixgbe_dev_rxtx_start(dev);
2029 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2033 /* Skip link setup if loopback mode is enabled for 82599. */
2034 if (hw->mac.type == ixgbe_mac_82599EB &&
2035 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2036 goto skip_link_setup;
2038 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2039 err = hw->mac.ops.setup_sfp(hw);
2044 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2045 /* Turn on the copper */
2046 ixgbe_set_phy_power(hw, true);
2048 /* Turn on the laser */
2049 ixgbe_enable_tx_laser(hw);
2052 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2055 dev->data->dev_link.link_status = link_up;
2057 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2061 switch(dev->data->dev_conf.link_speed) {
2062 case ETH_LINK_SPEED_AUTONEG:
2063 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2064 IXGBE_LINK_SPEED_82599_AUTONEG :
2065 IXGBE_LINK_SPEED_82598_AUTONEG;
2067 case ETH_LINK_SPEED_100:
2069 * Invalid for 82598 but error will be detected by
2070 * ixgbe_setup_link()
2072 speed = IXGBE_LINK_SPEED_100_FULL;
2074 case ETH_LINK_SPEED_1000:
2075 speed = IXGBE_LINK_SPEED_1GB_FULL;
2077 case ETH_LINK_SPEED_10000:
2078 speed = IXGBE_LINK_SPEED_10GB_FULL;
2081 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2082 dev->data->dev_conf.link_speed,
2083 dev->data->port_id);
2087 err = ixgbe_setup_link(hw, speed, link_up);
2093 if (rte_intr_allow_others(intr_handle)) {
2094 /* check if lsc interrupt is enabled */
2095 if (dev->data->dev_conf.intr_conf.lsc != 0)
2096 ixgbe_dev_lsc_interrupt_setup(dev);
2098 rte_intr_callback_unregister(intr_handle,
2099 ixgbe_dev_interrupt_handler,
2101 if (dev->data->dev_conf.intr_conf.lsc != 0)
2102 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2103 " no intr multiplex\n");
2106 /* check if rxq interrupt is enabled */
2107 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2108 rte_intr_dp_is_en(intr_handle))
2109 ixgbe_dev_rxq_interrupt_setup(dev);
2111 /* enable uio/vfio intr/eventfd mapping */
2112 rte_intr_enable(intr_handle);
2114 /* resume enabled intr since hw reset */
2115 ixgbe_enable_intr(dev);
2117 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2118 ETH_VLAN_EXTEND_MASK;
2119 ixgbe_vlan_offload_set(dev, mask);
2121 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2122 /* Enable vlan filtering for VMDq */
2123 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2126 /* Configure DCB hw */
2127 ixgbe_configure_dcb(dev);
2129 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2130 err = ixgbe_fdir_configure(dev);
2135 /* Restore vf rate limit */
2136 if (vfinfo != NULL) {
2137 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2138 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2139 if (vfinfo[vf].tx_rate[idx] != 0)
2140 ixgbe_set_vf_rate_limit(dev, vf,
2141 vfinfo[vf].tx_rate[idx],
2145 ixgbe_restore_statistics_mapping(dev);
2150 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2151 ixgbe_dev_clear_queues(dev);
2156 * Stop device: disable rx and tx functions to allow for reconfiguring.
2159 ixgbe_dev_stop(struct rte_eth_dev *dev)
2161 struct rte_eth_link link;
2162 struct ixgbe_hw *hw =
2163 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2164 struct ixgbe_vf_info *vfinfo =
2165 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2166 struct ixgbe_filter_info *filter_info =
2167 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2168 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2169 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2172 PMD_INIT_FUNC_TRACE();
2174 /* disable interrupts */
2175 ixgbe_disable_intr(hw);
2177 /* disable intr eventfd mapping */
2178 rte_intr_disable(intr_handle);
2181 ixgbe_pf_reset_hw(hw);
2182 hw->adapter_stopped = 0;
2185 ixgbe_stop_adapter(hw);
2187 for (vf = 0; vfinfo != NULL &&
2188 vf < dev->pci_dev->max_vfs; vf++)
2189 vfinfo[vf].clear_to_send = false;
2191 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2192 /* Turn off the copper */
2193 ixgbe_set_phy_power(hw, false);
2195 /* Turn off the laser */
2196 ixgbe_disable_tx_laser(hw);
2199 ixgbe_dev_clear_queues(dev);
2201 /* Clear stored conf */
2202 dev->data->scattered_rx = 0;
2205 /* Clear recorded link status */
2206 memset(&link, 0, sizeof(link));
2207 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2209 /* Remove all ntuple filters of the device */
2210 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2211 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2212 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2213 TAILQ_REMOVE(&filter_info->fivetuple_list,
2217 memset(filter_info->fivetuple_mask, 0,
2218 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2220 if (!rte_intr_allow_others(intr_handle))
2221 /* resume to the default handler */
2222 rte_intr_callback_register(intr_handle,
2223 ixgbe_dev_interrupt_handler,
2226 /* Clean datapath event and queue/vec mapping */
2227 rte_intr_efd_disable(intr_handle);
2228 if (intr_handle->intr_vec != NULL) {
2229 rte_free(intr_handle->intr_vec);
2230 intr_handle->intr_vec = NULL;
2235 * Set device link up: enable tx.
2238 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2240 struct ixgbe_hw *hw =
2241 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2242 if (hw->mac.type == ixgbe_mac_82599EB) {
2243 #ifdef RTE_NIC_BYPASS
2244 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2245 /* Not suported in bypass mode */
2246 PMD_INIT_LOG(ERR, "Set link up is not supported "
2247 "by device id 0x%x", hw->device_id);
2253 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2254 /* Turn on the copper */
2255 ixgbe_set_phy_power(hw, true);
2257 /* Turn on the laser */
2258 ixgbe_enable_tx_laser(hw);
2265 * Set device link down: disable tx.
2268 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2270 struct ixgbe_hw *hw =
2271 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2272 if (hw->mac.type == ixgbe_mac_82599EB) {
2273 #ifdef RTE_NIC_BYPASS
2274 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2275 /* Not suported in bypass mode */
2276 PMD_INIT_LOG(ERR, "Set link down is not supported "
2277 "by device id 0x%x", hw->device_id);
2283 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2284 /* Turn off the copper */
2285 ixgbe_set_phy_power(hw, false);
2287 /* Turn off the laser */
2288 ixgbe_disable_tx_laser(hw);
2295 * Reest and stop device.
2298 ixgbe_dev_close(struct rte_eth_dev *dev)
2300 struct ixgbe_hw *hw =
2301 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2303 PMD_INIT_FUNC_TRACE();
2305 ixgbe_pf_reset_hw(hw);
2307 ixgbe_dev_stop(dev);
2308 hw->adapter_stopped = 1;
2310 ixgbe_dev_free_queues(dev);
2312 ixgbe_disable_pcie_master(hw);
2314 /* reprogram the RAR[0] in case user changed it. */
2315 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2319 ixgbe_read_stats_registers(struct ixgbe_hw *hw, struct ixgbe_hw_stats
2320 *hw_stats, uint64_t *total_missed_rx,
2321 uint64_t *total_qbrc, uint64_t *total_qprc,
2322 uint64_t *total_qprdc)
2324 uint32_t bprc, lxon, lxoff, total;
2327 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2328 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2329 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2330 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2332 for (i = 0; i < 8; i++) {
2334 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2335 /* global total per queue */
2336 hw_stats->mpc[i] += mp;
2337 /* Running comprehensive total for stats display */
2338 *total_missed_rx += hw_stats->mpc[i];
2339 if (hw->mac.type == ixgbe_mac_82598EB) {
2340 hw_stats->rnbc[i] +=
2341 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2342 hw_stats->pxonrxc[i] +=
2343 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2344 hw_stats->pxoffrxc[i] +=
2345 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2347 hw_stats->pxonrxc[i] +=
2348 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2349 hw_stats->pxoffrxc[i] +=
2350 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2351 hw_stats->pxon2offc[i] +=
2352 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2354 hw_stats->pxontxc[i] +=
2355 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2356 hw_stats->pxofftxc[i] +=
2357 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2359 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2360 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2361 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2362 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2363 hw_stats->qbrc[i] +=
2364 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2365 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2366 hw_stats->qbtc[i] +=
2367 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2368 *total_qprdc += hw_stats->qprdc[i] +=
2369 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2371 *total_qprc += hw_stats->qprc[i];
2372 *total_qbrc += hw_stats->qbrc[i];
2374 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2375 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2376 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2378 /* Note that gprc counts missed packets */
2379 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2381 if (hw->mac.type != ixgbe_mac_82598EB) {
2382 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2383 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2384 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2385 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2386 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2387 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2388 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2389 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2391 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2392 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2393 /* 82598 only has a counter in the high register */
2394 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2395 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2396 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2400 * Workaround: mprc hardware is incorrectly counting
2401 * broadcasts, so for now we subtract those.
2403 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2404 hw_stats->bprc += bprc;
2405 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2406 if (hw->mac.type == ixgbe_mac_82598EB)
2407 hw_stats->mprc -= bprc;
2409 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2410 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2411 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2412 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2413 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2414 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2416 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2417 hw_stats->lxontxc += lxon;
2418 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2419 hw_stats->lxofftxc += lxoff;
2420 total = lxon + lxoff;
2422 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2423 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2424 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2425 hw_stats->gptc -= total;
2426 hw_stats->mptc -= total;
2427 hw_stats->ptc64 -= total;
2428 hw_stats->gotc -= total * ETHER_MIN_LEN;
2430 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2431 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2432 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2433 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2434 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2435 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2436 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2437 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2438 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2439 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2440 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2441 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2442 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2443 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2444 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2445 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2446 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2447 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2448 /* Only read FCOE on 82599 */
2449 if (hw->mac.type != ixgbe_mac_82598EB) {
2450 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2451 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2452 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2453 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2454 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2457 /* Flow Director Stats registers */
2458 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2459 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2463 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2466 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2468 struct ixgbe_hw *hw =
2469 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2470 struct ixgbe_hw_stats *hw_stats =
2471 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2472 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2475 total_missed_rx = 0;
2480 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2481 &total_qprc, &total_qprdc);
2486 /* Fill out the rte_eth_stats statistics structure */
2487 stats->ipackets = total_qprc;
2488 stats->ibytes = total_qbrc;
2489 stats->opackets = hw_stats->gptc;
2490 stats->obytes = hw_stats->gotc;
2492 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2493 stats->q_ipackets[i] = hw_stats->qprc[i];
2494 stats->q_opackets[i] = hw_stats->qptc[i];
2495 stats->q_ibytes[i] = hw_stats->qbrc[i];
2496 stats->q_obytes[i] = hw_stats->qbtc[i];
2497 stats->q_errors[i] = hw_stats->qprdc[i];
2501 stats->ierrors = hw_stats->crcerrs +
2518 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2520 struct ixgbe_hw_stats *stats =
2521 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2523 /* HW registers are cleared on read */
2524 ixgbe_dev_stats_get(dev, NULL);
2526 /* Reset software totals */
2527 memset(stats, 0, sizeof(*stats));
2530 /* This function calculates the number of xstats based on the current config */
2532 ixgbe_xstats_calc_num(void) {
2533 return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2534 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2538 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2541 struct ixgbe_hw *hw =
2542 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2543 struct ixgbe_hw_stats *hw_stats =
2544 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2545 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2546 unsigned i, stat, count = 0;
2548 count = ixgbe_xstats_calc_num();
2553 total_missed_rx = 0;
2558 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2559 &total_qprc, &total_qprdc);
2561 /* If this is a reset xstats is NULL, and we have cleared the
2562 * registers by reading them.
2567 /* Extended stats from ixgbe_hw_stats */
2569 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2570 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2571 rte_ixgbe_stats_strings[i].name);
2572 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2573 rte_ixgbe_stats_strings[i].offset);
2577 /* RX Priority Stats */
2578 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2579 for (i = 0; i < 8; i++) {
2580 snprintf(xstats[count].name, sizeof(xstats[count].name),
2581 "rx_priority%u_%s", i,
2582 rte_ixgbe_rxq_strings[stat].name);
2583 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2584 rte_ixgbe_rxq_strings[stat].offset +
2585 (sizeof(uint64_t) * i));
2590 /* TX Priority Stats */
2591 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2592 for (i = 0; i < 8; i++) {
2593 snprintf(xstats[count].name, sizeof(xstats[count].name),
2594 "tx_priority%u_%s", i,
2595 rte_ixgbe_txq_strings[stat].name);
2596 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2597 rte_ixgbe_txq_strings[stat].offset +
2598 (sizeof(uint64_t) * i));
2607 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2609 struct ixgbe_hw_stats *stats =
2610 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2612 unsigned count = ixgbe_xstats_calc_num();
2614 /* HW registers are cleared on read */
2615 ixgbe_dev_xstats_get(dev, NULL, count);
2617 /* Reset software totals */
2618 memset(stats, 0, sizeof(*stats));
2622 ixgbevf_update_stats(struct rte_eth_dev *dev)
2624 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2625 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2626 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2628 /* Good Rx packet, include VF loopback */
2629 UPDATE_VF_STAT(IXGBE_VFGPRC,
2630 hw_stats->last_vfgprc, hw_stats->vfgprc);
2632 /* Good Rx octets, include VF loopback */
2633 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2634 hw_stats->last_vfgorc, hw_stats->vfgorc);
2636 /* Good Tx packet, include VF loopback */
2637 UPDATE_VF_STAT(IXGBE_VFGPTC,
2638 hw_stats->last_vfgptc, hw_stats->vfgptc);
2640 /* Good Tx octets, include VF loopback */
2641 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2642 hw_stats->last_vfgotc, hw_stats->vfgotc);
2644 /* Rx Multicst Packet */
2645 UPDATE_VF_STAT(IXGBE_VFMPRC,
2646 hw_stats->last_vfmprc, hw_stats->vfmprc);
2650 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2653 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2654 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2657 if (n < IXGBEVF_NB_XSTATS)
2658 return IXGBEVF_NB_XSTATS;
2660 ixgbevf_update_stats(dev);
2665 /* Extended stats */
2666 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2667 snprintf(xstats[i].name, sizeof(xstats[i].name),
2668 "%s", rte_ixgbevf_stats_strings[i].name);
2669 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2670 rte_ixgbevf_stats_strings[i].offset);
2673 return IXGBEVF_NB_XSTATS;
2677 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2679 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2680 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2682 ixgbevf_update_stats(dev);
2687 stats->ipackets = hw_stats->vfgprc;
2688 stats->ibytes = hw_stats->vfgorc;
2689 stats->opackets = hw_stats->vfgptc;
2690 stats->obytes = hw_stats->vfgotc;
2691 stats->imcasts = hw_stats->vfmprc;
2692 /* stats->imcasts should be removed as imcasts is deprecated */
2696 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2698 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2699 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2701 /* Sync HW register to the last stats */
2702 ixgbevf_dev_stats_get(dev, NULL);
2704 /* reset HW current stats*/
2705 hw_stats->vfgprc = 0;
2706 hw_stats->vfgorc = 0;
2707 hw_stats->vfgptc = 0;
2708 hw_stats->vfgotc = 0;
2709 hw_stats->vfmprc = 0;
2714 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2716 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2718 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2719 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2720 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2721 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2722 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2723 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2724 dev_info->max_vfs = dev->pci_dev->max_vfs;
2725 if (hw->mac.type == ixgbe_mac_82598EB)
2726 dev_info->max_vmdq_pools = ETH_16_POOLS;
2728 dev_info->max_vmdq_pools = ETH_64_POOLS;
2729 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2730 dev_info->rx_offload_capa =
2731 DEV_RX_OFFLOAD_VLAN_STRIP |
2732 DEV_RX_OFFLOAD_IPV4_CKSUM |
2733 DEV_RX_OFFLOAD_UDP_CKSUM |
2734 DEV_RX_OFFLOAD_TCP_CKSUM;
2737 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2740 if ((hw->mac.type == ixgbe_mac_82599EB ||
2741 hw->mac.type == ixgbe_mac_X540) &&
2742 !RTE_ETH_DEV_SRIOV(dev).active)
2743 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2745 dev_info->tx_offload_capa =
2746 DEV_TX_OFFLOAD_VLAN_INSERT |
2747 DEV_TX_OFFLOAD_IPV4_CKSUM |
2748 DEV_TX_OFFLOAD_UDP_CKSUM |
2749 DEV_TX_OFFLOAD_TCP_CKSUM |
2750 DEV_TX_OFFLOAD_SCTP_CKSUM |
2751 DEV_TX_OFFLOAD_TCP_TSO;
2753 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2755 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2756 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2757 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2759 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2763 dev_info->default_txconf = (struct rte_eth_txconf) {
2765 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2766 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2767 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2769 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2770 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2771 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2772 ETH_TXQ_FLAGS_NOOFFLOADS,
2775 dev_info->rx_desc_lim = rx_desc_lim;
2776 dev_info->tx_desc_lim = tx_desc_lim;
2778 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2779 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2780 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2784 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2785 struct rte_eth_dev_info *dev_info)
2787 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2789 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2790 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2791 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2792 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2793 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2794 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2795 dev_info->max_vfs = dev->pci_dev->max_vfs;
2796 if (hw->mac.type == ixgbe_mac_82598EB)
2797 dev_info->max_vmdq_pools = ETH_16_POOLS;
2799 dev_info->max_vmdq_pools = ETH_64_POOLS;
2800 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2801 DEV_RX_OFFLOAD_IPV4_CKSUM |
2802 DEV_RX_OFFLOAD_UDP_CKSUM |
2803 DEV_RX_OFFLOAD_TCP_CKSUM;
2804 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2805 DEV_TX_OFFLOAD_IPV4_CKSUM |
2806 DEV_TX_OFFLOAD_UDP_CKSUM |
2807 DEV_TX_OFFLOAD_TCP_CKSUM |
2808 DEV_TX_OFFLOAD_SCTP_CKSUM |
2809 DEV_TX_OFFLOAD_TCP_TSO;
2811 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2813 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2814 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2815 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2817 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2821 dev_info->default_txconf = (struct rte_eth_txconf) {
2823 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2824 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2825 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2827 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2828 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2829 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2830 ETH_TXQ_FLAGS_NOOFFLOADS,
2833 dev_info->rx_desc_lim = rx_desc_lim;
2834 dev_info->tx_desc_lim = tx_desc_lim;
2837 /* return 0 means link status changed, -1 means not changed */
2839 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2841 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2842 struct rte_eth_link link, old;
2843 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2847 link.link_status = 0;
2848 link.link_speed = 0;
2849 link.link_duplex = 0;
2850 memset(&old, 0, sizeof(old));
2851 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2853 hw->mac.get_link_status = true;
2855 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2856 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2857 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2859 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2862 link.link_speed = ETH_LINK_SPEED_100;
2863 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2864 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2865 if (link.link_status == old.link_status)
2871 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2872 if (link.link_status == old.link_status)
2876 link.link_status = 1;
2877 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2879 switch (link_speed) {
2881 case IXGBE_LINK_SPEED_UNKNOWN:
2882 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2883 link.link_speed = ETH_LINK_SPEED_100;
2886 case IXGBE_LINK_SPEED_100_FULL:
2887 link.link_speed = ETH_LINK_SPEED_100;
2890 case IXGBE_LINK_SPEED_1GB_FULL:
2891 link.link_speed = ETH_LINK_SPEED_1000;
2894 case IXGBE_LINK_SPEED_10GB_FULL:
2895 link.link_speed = ETH_LINK_SPEED_10000;
2898 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2900 if (link.link_status == old.link_status)
2907 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2909 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2912 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2913 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2914 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2918 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2920 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2923 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2924 fctrl &= (~IXGBE_FCTRL_UPE);
2925 if (dev->data->all_multicast == 1)
2926 fctrl |= IXGBE_FCTRL_MPE;
2928 fctrl &= (~IXGBE_FCTRL_MPE);
2929 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2933 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2935 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2938 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2939 fctrl |= IXGBE_FCTRL_MPE;
2940 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2944 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2946 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2949 if (dev->data->promiscuous == 1)
2950 return; /* must remain in all_multicast mode */
2952 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2953 fctrl &= (~IXGBE_FCTRL_MPE);
2954 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2958 * It clears the interrupt causes and enables the interrupt.
2959 * It will be called once only during nic initialized.
2962 * Pointer to struct rte_eth_dev.
2965 * - On success, zero.
2966 * - On failure, a negative value.
2969 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2971 struct ixgbe_interrupt *intr =
2972 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2974 ixgbe_dev_link_status_print(dev);
2975 intr->mask |= IXGBE_EICR_LSC;
2981 * It clears the interrupt causes and enables the interrupt.
2982 * It will be called once only during nic initialized.
2985 * Pointer to struct rte_eth_dev.
2988 * - On success, zero.
2989 * - On failure, a negative value.
2992 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2994 struct ixgbe_interrupt *intr =
2995 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2997 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3003 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3006 * Pointer to struct rte_eth_dev.
3009 * - On success, zero.
3010 * - On failure, a negative value.
3013 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3016 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3017 struct ixgbe_interrupt *intr =
3018 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3020 /* clear all cause mask */
3021 ixgbe_disable_intr(hw);
3023 /* read-on-clear nic registers here */
3024 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3025 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3029 /* set flag for async link update */
3030 if (eicr & IXGBE_EICR_LSC)
3031 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3033 if (eicr & IXGBE_EICR_MAILBOX)
3034 intr->flags |= IXGBE_FLAG_MAILBOX;
3040 * It gets and then prints the link status.
3043 * Pointer to struct rte_eth_dev.
3046 * - On success, zero.
3047 * - On failure, a negative value.
3050 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3052 struct rte_eth_link link;
3054 memset(&link, 0, sizeof(link));
3055 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3056 if (link.link_status) {
3057 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3058 (int)(dev->data->port_id),
3059 (unsigned)link.link_speed,
3060 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3061 "full-duplex" : "half-duplex");
3063 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3064 (int)(dev->data->port_id));
3066 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3067 dev->pci_dev->addr.domain,
3068 dev->pci_dev->addr.bus,
3069 dev->pci_dev->addr.devid,
3070 dev->pci_dev->addr.function);
3074 * It executes link_update after knowing an interrupt occurred.
3077 * Pointer to struct rte_eth_dev.
3080 * - On success, zero.
3081 * - On failure, a negative value.
3084 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3086 struct ixgbe_interrupt *intr =
3087 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3089 struct rte_eth_link link;
3090 int intr_enable_delay = false;
3092 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3094 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3095 ixgbe_pf_mbx_process(dev);
3096 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3099 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3100 /* get the link status before link update, for predicting later */
3101 memset(&link, 0, sizeof(link));
3102 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3104 ixgbe_dev_link_update(dev, 0);
3107 if (!link.link_status)
3108 /* handle it 1 sec later, wait it being stable */
3109 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3110 /* likely to down */
3112 /* handle it 4 sec later, wait it being stable */
3113 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3115 ixgbe_dev_link_status_print(dev);
3117 intr_enable_delay = true;
3120 if (intr_enable_delay) {
3121 if (rte_eal_alarm_set(timeout * 1000,
3122 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3123 PMD_DRV_LOG(ERR, "Error setting alarm");
3125 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3126 ixgbe_enable_intr(dev);
3127 rte_intr_enable(&(dev->pci_dev->intr_handle));
3135 * Interrupt handler which shall be registered for alarm callback for delayed
3136 * handling specific interrupt to wait for the stable nic state. As the
3137 * NIC interrupt state is not stable for ixgbe after link is just down,
3138 * it needs to wait 4 seconds to get the stable status.
3141 * Pointer to interrupt handle.
3143 * The address of parameter (struct rte_eth_dev *) regsitered before.
3149 ixgbe_dev_interrupt_delayed_handler(void *param)
3151 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3152 struct ixgbe_interrupt *intr =
3153 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3154 struct ixgbe_hw *hw =
3155 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3158 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3159 if (eicr & IXGBE_EICR_MAILBOX)
3160 ixgbe_pf_mbx_process(dev);
3162 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3163 ixgbe_dev_link_update(dev, 0);
3164 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3165 ixgbe_dev_link_status_print(dev);
3166 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3169 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3170 ixgbe_enable_intr(dev);
3171 rte_intr_enable(&(dev->pci_dev->intr_handle));
3175 * Interrupt handler triggered by NIC for handling
3176 * specific interrupt.
3179 * Pointer to interrupt handle.
3181 * The address of parameter (struct rte_eth_dev *) regsitered before.
3187 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3190 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3192 ixgbe_dev_interrupt_get_status(dev);
3193 ixgbe_dev_interrupt_action(dev);
3197 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3199 struct ixgbe_hw *hw;
3201 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3202 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3206 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3208 struct ixgbe_hw *hw;
3210 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3211 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3215 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3217 struct ixgbe_hw *hw;
3223 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3225 fc_conf->pause_time = hw->fc.pause_time;
3226 fc_conf->high_water = hw->fc.high_water[0];
3227 fc_conf->low_water = hw->fc.low_water[0];
3228 fc_conf->send_xon = hw->fc.send_xon;
3229 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3232 * Return rx_pause status according to actual setting of
3235 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3236 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3242 * Return tx_pause status according to actual setting of
3245 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3246 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3251 if (rx_pause && tx_pause)
3252 fc_conf->mode = RTE_FC_FULL;
3254 fc_conf->mode = RTE_FC_RX_PAUSE;
3256 fc_conf->mode = RTE_FC_TX_PAUSE;
3258 fc_conf->mode = RTE_FC_NONE;
3264 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3266 struct ixgbe_hw *hw;
3268 uint32_t rx_buf_size;
3269 uint32_t max_high_water;
3271 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3278 PMD_INIT_FUNC_TRACE();
3280 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3281 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3282 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3285 * At least reserve one Ethernet frame for watermark
3286 * high_water/low_water in kilo bytes for ixgbe
3288 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3289 if ((fc_conf->high_water > max_high_water) ||
3290 (fc_conf->high_water < fc_conf->low_water)) {
3291 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3292 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3296 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3297 hw->fc.pause_time = fc_conf->pause_time;
3298 hw->fc.high_water[0] = fc_conf->high_water;
3299 hw->fc.low_water[0] = fc_conf->low_water;
3300 hw->fc.send_xon = fc_conf->send_xon;
3301 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3303 err = ixgbe_fc_enable(hw);
3305 /* Not negotiated is not an error case */
3306 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3308 /* check if we want to forward MAC frames - driver doesn't have native
3309 * capability to do that, so we'll write the registers ourselves */
3311 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3313 /* set or clear MFLCN.PMCF bit depending on configuration */
3314 if (fc_conf->mac_ctrl_frame_fwd != 0)
3315 mflcn |= IXGBE_MFLCN_PMCF;
3317 mflcn &= ~IXGBE_MFLCN_PMCF;
3319 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3320 IXGBE_WRITE_FLUSH(hw);
3325 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3330 * ixgbe_pfc_enable_generic - Enable flow control
3331 * @hw: pointer to hardware structure
3332 * @tc_num: traffic class number
3333 * Enable flow control according to the current settings.
3336 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3339 uint32_t mflcn_reg, fccfg_reg;
3341 uint32_t fcrtl, fcrth;
3345 /* Validate the water mark configuration */
3346 if (!hw->fc.pause_time) {
3347 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3351 /* Low water mark of zero causes XOFF floods */
3352 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3353 /* High/Low water can not be 0 */
3354 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
3355 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3356 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3360 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3361 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3362 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3366 /* Negotiate the fc mode to use */
3367 ixgbe_fc_autoneg(hw);
3369 /* Disable any previous flow control settings */
3370 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3371 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3373 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3374 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3376 switch (hw->fc.current_mode) {
3379 * If the count of enabled RX Priority Flow control >1,
3380 * and the TX pause can not be disabled
3383 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3384 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3385 if (reg & IXGBE_FCRTH_FCEN)
3389 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3391 case ixgbe_fc_rx_pause:
3393 * Rx Flow control is enabled and Tx Flow control is
3394 * disabled by software override. Since there really
3395 * isn't a way to advertise that we are capable of RX
3396 * Pause ONLY, we will advertise that we support both
3397 * symmetric and asymmetric Rx PAUSE. Later, we will
3398 * disable the adapter's ability to send PAUSE frames.
3400 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3402 * If the count of enabled RX Priority Flow control >1,
3403 * and the TX pause can not be disabled
3406 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3407 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3408 if (reg & IXGBE_FCRTH_FCEN)
3412 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3414 case ixgbe_fc_tx_pause:
3416 * Tx Flow control is enabled, and Rx Flow control is
3417 * disabled by software override.
3419 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3422 /* Flow control (both Rx and Tx) is enabled by SW override. */
3423 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3424 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3427 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3428 ret_val = IXGBE_ERR_CONFIG;
3433 /* Set 802.3x based flow control settings. */
3434 mflcn_reg |= IXGBE_MFLCN_DPF;
3435 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3436 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3438 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3439 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3440 hw->fc.high_water[tc_num]) {
3441 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3442 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3443 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3445 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3447 * In order to prevent Tx hangs when the internal Tx
3448 * switch is enabled we must set the high water mark
3449 * to the maximum FCRTH value. This allows the Tx
3450 * switch to function even under heavy Rx workloads.
3452 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3454 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3456 /* Configure pause time (2 TCs per register) */
3457 reg = hw->fc.pause_time * 0x00010001;
3458 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3459 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3461 /* Configure flow control refresh threshold value */
3462 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3469 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3471 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3472 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3474 if(hw->mac.type != ixgbe_mac_82598EB) {
3475 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3481 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3484 uint32_t rx_buf_size;
3485 uint32_t max_high_water;
3487 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3488 struct ixgbe_hw *hw =
3489 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3490 struct ixgbe_dcb_config *dcb_config =
3491 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3493 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3500 PMD_INIT_FUNC_TRACE();
3502 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3503 tc_num = map[pfc_conf->priority];
3504 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3505 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3507 * At least reserve one Ethernet frame for watermark
3508 * high_water/low_water in kilo bytes for ixgbe
3510 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3511 if ((pfc_conf->fc.high_water > max_high_water) ||
3512 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3513 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3514 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3518 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3519 hw->fc.pause_time = pfc_conf->fc.pause_time;
3520 hw->fc.send_xon = pfc_conf->fc.send_xon;
3521 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
3522 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3524 err = ixgbe_dcb_pfc_enable(dev,tc_num);
3526 /* Not negotiated is not an error case */
3527 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3530 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3535 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3536 struct rte_eth_rss_reta_entry64 *reta_conf,
3541 uint16_t idx, shift;
3542 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3543 uint16_t sp_reta_size;
3546 PMD_INIT_FUNC_TRACE();
3548 if (!ixgbe_rss_update_sp(hw->mac.type)) {
3549 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3554 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3555 if (reta_size != sp_reta_size) {
3556 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3557 "(%d) doesn't match the number hardware can supported "
3558 "(%d)\n", reta_size, sp_reta_size);
3562 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3563 idx = i / RTE_RETA_GROUP_SIZE;
3564 shift = i % RTE_RETA_GROUP_SIZE;
3565 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3569 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3570 if (mask == IXGBE_4_BIT_MASK)
3573 r = IXGBE_READ_REG(hw, reta_reg);
3574 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3575 if (mask & (0x1 << j))
3576 reta |= reta_conf[idx].reta[shift + j] <<
3579 reta |= r & (IXGBE_8_BIT_MASK <<
3582 IXGBE_WRITE_REG(hw, reta_reg, reta);
3589 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3590 struct rte_eth_rss_reta_entry64 *reta_conf,
3595 uint16_t idx, shift;
3596 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3597 uint16_t sp_reta_size;
3600 PMD_INIT_FUNC_TRACE();
3601 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3602 if (reta_size != sp_reta_size) {
3603 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3604 "(%d) doesn't match the number hardware can supported "
3605 "(%d)\n", reta_size, sp_reta_size);
3609 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3610 idx = i / RTE_RETA_GROUP_SIZE;
3611 shift = i % RTE_RETA_GROUP_SIZE;
3612 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3617 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3618 reta = IXGBE_READ_REG(hw, reta_reg);
3619 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3620 if (mask & (0x1 << j))
3621 reta_conf[idx].reta[shift + j] =
3622 ((reta >> (CHAR_BIT * j)) &
3631 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3632 uint32_t index, uint32_t pool)
3634 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3635 uint32_t enable_addr = 1;
3637 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3641 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3643 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3645 ixgbe_clear_rar(hw, index);
3649 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3651 ixgbe_remove_rar(dev, 0);
3653 ixgbe_add_rar(dev, addr, 0, 0);
3657 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3661 struct ixgbe_hw *hw;
3662 struct rte_eth_dev_info dev_info;
3663 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3665 ixgbe_dev_info_get(dev, &dev_info);
3667 /* check that mtu is within the allowed range */
3668 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3671 /* refuse mtu that requires the support of scattered packets when this
3672 * feature has not been enabled before. */
3673 if (!dev->data->scattered_rx &&
3674 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3675 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3678 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3679 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3681 /* switch to jumbo mode if needed */
3682 if (frame_size > ETHER_MAX_LEN) {
3683 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3684 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3686 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3687 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3689 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3691 /* update max frame size */
3692 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3694 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3695 maxfrs &= 0x0000FFFF;
3696 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3697 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3703 * Virtual Function operations
3706 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3708 PMD_INIT_FUNC_TRACE();
3710 /* Clear interrupt mask to stop from interrupts being generated */
3711 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3713 IXGBE_WRITE_FLUSH(hw);
3717 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3719 PMD_INIT_FUNC_TRACE();
3721 /* VF enable interrupt autoclean */
3722 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3723 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3724 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3726 IXGBE_WRITE_FLUSH(hw);
3730 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3732 struct rte_eth_conf* conf = &dev->data->dev_conf;
3733 struct ixgbe_adapter *adapter =
3734 (struct ixgbe_adapter *)dev->data->dev_private;
3736 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3737 dev->data->port_id);
3740 * VF has no ability to enable/disable HW CRC
3741 * Keep the persistent behavior the same as Host PF
3743 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3744 if (!conf->rxmode.hw_strip_crc) {
3745 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3746 conf->rxmode.hw_strip_crc = 1;
3749 if (conf->rxmode.hw_strip_crc) {
3750 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3751 conf->rxmode.hw_strip_crc = 0;
3756 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3757 * allocation or vector Rx preconditions we will reset it.
3759 adapter->rx_bulk_alloc_allowed = true;
3760 adapter->rx_vec_allowed = true;
3766 ixgbevf_dev_start(struct rte_eth_dev *dev)
3768 struct ixgbe_hw *hw =
3769 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3770 uint32_t intr_vector = 0;
3771 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3775 PMD_INIT_FUNC_TRACE();
3777 hw->mac.ops.reset_hw(hw);
3778 hw->mac.get_link_status = true;
3780 /* negotiate mailbox API version to use with the PF. */
3781 ixgbevf_negotiate_api(hw);
3783 ixgbevf_dev_tx_init(dev);
3785 /* This can fail when allocating mbufs for descriptor rings */
3786 err = ixgbevf_dev_rx_init(dev);
3788 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3789 ixgbe_dev_clear_queues(dev);
3794 ixgbevf_set_vfta_all(dev,1);
3797 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3798 ETH_VLAN_EXTEND_MASK;
3799 ixgbevf_vlan_offload_set(dev, mask);
3801 ixgbevf_dev_rxtx_start(dev);
3803 /* check and configure queue intr-vector mapping */
3804 if (dev->data->dev_conf.intr_conf.rxq != 0) {
3805 intr_vector = dev->data->nb_rx_queues;
3806 if (rte_intr_efd_enable(intr_handle, intr_vector))
3810 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3811 intr_handle->intr_vec =
3812 rte_zmalloc("intr_vec",
3813 dev->data->nb_rx_queues * sizeof(int), 0);
3814 if (intr_handle->intr_vec == NULL) {
3815 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3816 " intr_vec\n", dev->data->nb_rx_queues);
3820 ixgbevf_configure_msix(dev);
3822 rte_intr_enable(intr_handle);
3824 /* Re-enable interrupt for VF */
3825 ixgbevf_intr_enable(hw);
3831 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3833 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3834 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3836 PMD_INIT_FUNC_TRACE();
3838 hw->adapter_stopped = 1;
3839 ixgbe_stop_adapter(hw);
3842 * Clear what we set, but we still keep shadow_vfta to
3843 * restore after device starts
3845 ixgbevf_set_vfta_all(dev,0);
3847 /* Clear stored conf */
3848 dev->data->scattered_rx = 0;
3850 ixgbe_dev_clear_queues(dev);
3852 /* disable intr eventfd mapping */
3853 rte_intr_disable(intr_handle);
3855 /* Clean datapath event and queue/vec mapping */
3856 rte_intr_efd_disable(intr_handle);
3857 if (intr_handle->intr_vec != NULL) {
3858 rte_free(intr_handle->intr_vec);
3859 intr_handle->intr_vec = NULL;
3864 ixgbevf_dev_close(struct rte_eth_dev *dev)
3866 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3868 PMD_INIT_FUNC_TRACE();
3872 ixgbevf_dev_stop(dev);
3874 ixgbe_dev_free_queues(dev);
3876 /* reprogram the RAR[0] in case user changed it. */
3877 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3880 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3882 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3883 struct ixgbe_vfta * shadow_vfta =
3884 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3885 int i = 0, j = 0, vfta = 0, mask = 1;
3887 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3888 vfta = shadow_vfta->vfta[i];
3891 for (j = 0; j < 32; j++){
3893 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3902 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3904 struct ixgbe_hw *hw =
3905 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3906 struct ixgbe_vfta * shadow_vfta =
3907 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3908 uint32_t vid_idx = 0;
3909 uint32_t vid_bit = 0;
3912 PMD_INIT_FUNC_TRACE();
3914 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3915 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3917 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3920 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3921 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3923 /* Save what we set and retore it after device reset */
3925 shadow_vfta->vfta[vid_idx] |= vid_bit;
3927 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3933 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3935 struct ixgbe_hw *hw =
3936 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3939 PMD_INIT_FUNC_TRACE();
3941 if(queue >= hw->mac.max_rx_queues)
3944 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3946 ctrl |= IXGBE_RXDCTL_VME;
3948 ctrl &= ~IXGBE_RXDCTL_VME;
3949 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3951 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3955 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3957 struct ixgbe_hw *hw =
3958 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3962 /* VF function only support hw strip feature, others are not support */
3963 if(mask & ETH_VLAN_STRIP_MASK){
3964 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3966 for(i=0; i < hw->mac.max_rx_queues; i++)
3967 ixgbevf_vlan_strip_queue_set(dev,i,on);
3972 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3976 /* we only need to do this if VMDq is enabled */
3977 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3978 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3979 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3987 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3989 uint32_t vector = 0;
3990 switch (hw->mac.mc_filter_type) {
3991 case 0: /* use bits [47:36] of the address */
3992 vector = ((uc_addr->addr_bytes[4] >> 4) |
3993 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3995 case 1: /* use bits [46:35] of the address */
3996 vector = ((uc_addr->addr_bytes[4] >> 3) |
3997 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3999 case 2: /* use bits [45:34] of the address */
4000 vector = ((uc_addr->addr_bytes[4] >> 2) |
4001 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4003 case 3: /* use bits [43:32] of the address */
4004 vector = ((uc_addr->addr_bytes[4]) |
4005 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4007 default: /* Invalid mc_filter_type */
4011 /* vector can only be 12-bits or boundary will be exceeded */
4017 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4025 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4026 const uint32_t ixgbe_uta_bit_shift = 5;
4027 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4028 const uint32_t bit1 = 0x1;
4030 struct ixgbe_hw *hw =
4031 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4032 struct ixgbe_uta_info *uta_info =
4033 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4035 /* The UTA table only exists on 82599 hardware and newer */
4036 if (hw->mac.type < ixgbe_mac_82599EB)
4039 vector = ixgbe_uta_vector(hw,mac_addr);
4040 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4041 uta_shift = vector & ixgbe_uta_bit_mask;
4043 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4047 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4049 uta_info->uta_in_use++;
4050 reg_val |= (bit1 << uta_shift);
4051 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4053 uta_info->uta_in_use--;
4054 reg_val &= ~(bit1 << uta_shift);
4055 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4058 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4060 if (uta_info->uta_in_use > 0)
4061 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4062 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4064 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4070 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4073 struct ixgbe_hw *hw =
4074 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4075 struct ixgbe_uta_info *uta_info =
4076 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4078 /* The UTA table only exists on 82599 hardware and newer */
4079 if (hw->mac.type < ixgbe_mac_82599EB)
4083 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4084 uta_info->uta_shadow[i] = ~0;
4085 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4088 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4089 uta_info->uta_shadow[i] = 0;
4090 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4098 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4100 uint32_t new_val = orig_val;
4102 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4103 new_val |= IXGBE_VMOLR_AUPE;
4104 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4105 new_val |= IXGBE_VMOLR_ROMPE;
4106 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4107 new_val |= IXGBE_VMOLR_ROPE;
4108 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4109 new_val |= IXGBE_VMOLR_BAM;
4110 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4111 new_val |= IXGBE_VMOLR_MPE;
4117 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4118 uint16_t rx_mask, uint8_t on)
4122 struct ixgbe_hw *hw =
4123 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4124 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4126 if (hw->mac.type == ixgbe_mac_82598EB) {
4127 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4128 " on 82599 hardware and newer");
4131 if (ixgbe_vmdq_mode_check(hw) < 0)
4134 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4141 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4147 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4151 const uint8_t bit1 = 0x1;
4153 struct ixgbe_hw *hw =
4154 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4156 if (ixgbe_vmdq_mode_check(hw) < 0)
4159 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4160 reg = IXGBE_READ_REG(hw, addr);
4168 IXGBE_WRITE_REG(hw, addr,reg);
4174 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4178 const uint8_t bit1 = 0x1;
4180 struct ixgbe_hw *hw =
4181 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4183 if (ixgbe_vmdq_mode_check(hw) < 0)
4186 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4187 reg = IXGBE_READ_REG(hw, addr);
4195 IXGBE_WRITE_REG(hw, addr,reg);
4201 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4202 uint64_t pool_mask, uint8_t vlan_on)
4206 struct ixgbe_hw *hw =
4207 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4209 if (ixgbe_vmdq_mode_check(hw) < 0)
4211 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4212 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4213 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4221 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
4222 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
4223 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
4224 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
4225 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4226 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4227 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4230 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4231 struct rte_eth_mirror_conf *mirror_conf,
4232 uint8_t rule_id, uint8_t on)
4234 uint32_t mr_ctl,vlvf;
4235 uint32_t mp_lsb = 0;
4236 uint32_t mv_msb = 0;
4237 uint32_t mv_lsb = 0;
4238 uint32_t mp_msb = 0;
4241 uint64_t vlan_mask = 0;
4243 const uint8_t pool_mask_offset = 32;
4244 const uint8_t vlan_mask_offset = 32;
4245 const uint8_t dst_pool_offset = 8;
4246 const uint8_t rule_mr_offset = 4;
4247 const uint8_t mirror_rule_mask= 0x0F;
4249 struct ixgbe_mirror_info *mr_info =
4250 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4251 struct ixgbe_hw *hw =
4252 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4253 uint8_t mirror_type = 0;
4255 if (ixgbe_vmdq_mode_check(hw) < 0)
4258 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4261 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4262 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4263 mirror_conf->rule_type);
4267 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4268 mirror_type |= IXGBE_MRCTL_VLME;
4269 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4270 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4271 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4272 /* search vlan id related pool vlan filter index */
4273 reg_index = ixgbe_find_vlvf_slot(hw,
4274 mirror_conf->vlan.vlan_id[i]);
4277 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4278 if ((vlvf & IXGBE_VLVF_VIEN) &&
4279 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4280 mirror_conf->vlan.vlan_id[i]))
4281 vlan_mask |= (1ULL << reg_index);
4288 mv_lsb = vlan_mask & 0xFFFFFFFF;
4289 mv_msb = vlan_mask >> vlan_mask_offset;
4291 mr_info->mr_conf[rule_id].vlan.vlan_mask =
4292 mirror_conf->vlan.vlan_mask;
4293 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4294 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
4295 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4296 mirror_conf->vlan.vlan_id[i];
4301 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4302 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4303 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4308 * if enable pool mirror, write related pool mask register,if disable
4309 * pool mirror, clear PFMRVM register
4311 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4312 mirror_type |= IXGBE_MRCTL_VPME;
4314 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4315 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4316 mr_info->mr_conf[rule_id].pool_mask =
4317 mirror_conf->pool_mask;
4322 mr_info->mr_conf[rule_id].pool_mask = 0;
4325 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4326 mirror_type |= IXGBE_MRCTL_UPME;
4327 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4328 mirror_type |= IXGBE_MRCTL_DPME;
4330 /* read mirror control register and recalculate it */
4331 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4334 mr_ctl |= mirror_type;
4335 mr_ctl &= mirror_rule_mask;
4336 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4338 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4340 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4341 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4343 /* write mirrror control register */
4344 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4346 /* write pool mirrror control register */
4347 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4348 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4349 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4352 /* write VLAN mirrror control register */
4353 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4354 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4355 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4363 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4366 uint32_t lsb_val = 0;
4367 uint32_t msb_val = 0;
4368 const uint8_t rule_mr_offset = 4;
4370 struct ixgbe_hw *hw =
4371 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4372 struct ixgbe_mirror_info *mr_info =
4373 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4375 if (ixgbe_vmdq_mode_check(hw) < 0)
4378 memset(&mr_info->mr_conf[rule_id], 0,
4379 sizeof(struct rte_eth_mirror_conf));
4381 /* clear PFVMCTL register */
4382 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4384 /* clear pool mask register */
4385 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4386 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4388 /* clear vlan mask register */
4389 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4390 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4396 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4399 struct ixgbe_hw *hw =
4400 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4402 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4403 mask |= (1 << IXGBE_MISC_VEC_ID);
4404 RTE_SET_USED(queue_id);
4405 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4407 rte_intr_enable(&dev->pci_dev->intr_handle);
4413 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4416 struct ixgbe_hw *hw =
4417 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4419 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4420 mask &= ~(1 << IXGBE_MISC_VEC_ID);
4421 RTE_SET_USED(queue_id);
4422 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4428 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4431 struct ixgbe_hw *hw =
4432 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4433 struct ixgbe_interrupt *intr =
4434 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4436 if (queue_id < 16) {
4437 ixgbe_disable_intr(hw);
4438 intr->mask |= (1 << queue_id);
4439 ixgbe_enable_intr(dev);
4440 } else if (queue_id < 32) {
4441 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4442 mask &= (1 << queue_id);
4443 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4444 } else if (queue_id < 64) {
4445 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4446 mask &= (1 << (queue_id - 32));
4447 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4449 rte_intr_enable(&dev->pci_dev->intr_handle);
4455 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4458 struct ixgbe_hw *hw =
4459 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4460 struct ixgbe_interrupt *intr =
4461 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4463 if (queue_id < 16) {
4464 ixgbe_disable_intr(hw);
4465 intr->mask &= ~(1 << queue_id);
4466 ixgbe_enable_intr(dev);
4467 } else if (queue_id < 32) {
4468 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4469 mask &= ~(1 << queue_id);
4470 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4471 } else if (queue_id < 64) {
4472 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4473 mask &= ~(1 << (queue_id - 32));
4474 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4481 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4482 uint8_t queue, uint8_t msix_vector)
4486 if (direction == -1) {
4488 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4489 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4492 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4494 /* rx or tx cause */
4495 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4496 idx = ((16 * (queue & 1)) + (8 * direction));
4497 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4498 tmp &= ~(0xFF << idx);
4499 tmp |= (msix_vector << idx);
4500 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4505 * set the IVAR registers, mapping interrupt causes to vectors
4507 * pointer to ixgbe_hw struct
4509 * 0 for Rx, 1 for Tx, -1 for other causes
4511 * queue to map the corresponding interrupt to
4513 * the vector to map to the corresponding queue
4516 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4517 uint8_t queue, uint8_t msix_vector)
4521 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4522 if (hw->mac.type == ixgbe_mac_82598EB) {
4523 if (direction == -1)
4525 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4526 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4527 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4528 tmp |= (msix_vector << (8 * (queue & 0x3)));
4529 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4530 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4531 (hw->mac.type == ixgbe_mac_X540)) {
4532 if (direction == -1) {
4534 idx = ((queue & 1) * 8);
4535 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4536 tmp &= ~(0xFF << idx);
4537 tmp |= (msix_vector << idx);
4538 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4540 /* rx or tx causes */
4541 idx = ((16 * (queue & 1)) + (8 * direction));
4542 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4543 tmp &= ~(0xFF << idx);
4544 tmp |= (msix_vector << idx);
4545 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4551 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4553 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4554 struct ixgbe_hw *hw =
4555 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4557 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4559 /* won't configure msix register if no mapping is done
4560 * between intr vector and event fd.
4562 if (!rte_intr_dp_is_en(intr_handle))
4565 /* Configure all RX queues of VF */
4566 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4567 /* Force all queue use vector 0,
4568 * as IXGBE_VF_MAXMSIVECOTR = 1
4570 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4571 intr_handle->intr_vec[q_idx] = vector_idx;
4574 /* Configure VF other cause ivar */
4575 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4579 * Sets up the hardware to properly generate MSI-X interrupts
4581 * board private structure
4584 ixgbe_configure_msix(struct rte_eth_dev *dev)
4586 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4587 struct ixgbe_hw *hw =
4588 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4589 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4590 uint32_t vec = IXGBE_MISC_VEC_ID;
4594 /* won't configure msix register if no mapping is done
4595 * between intr vector and event fd
4597 if (!rte_intr_dp_is_en(intr_handle))
4600 if (rte_intr_allow_others(intr_handle))
4601 vec = base = IXGBE_RX_VEC_START;
4603 /* setup GPIE for MSI-x mode */
4604 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4605 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4606 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4607 /* auto clearing and auto setting corresponding bits in EIMS
4608 * when MSI-X interrupt is triggered
4610 if (hw->mac.type == ixgbe_mac_82598EB) {
4611 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4613 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4614 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4616 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4618 /* Populate the IVAR table and set the ITR values to the
4619 * corresponding register.
4621 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4623 /* by default, 1:1 mapping */
4624 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4625 intr_handle->intr_vec[queue_id] = vec;
4626 if (vec < base + intr_handle->nb_efd - 1)
4630 switch (hw->mac.type) {
4631 case ixgbe_mac_82598EB:
4632 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4635 case ixgbe_mac_82599EB:
4636 case ixgbe_mac_X540:
4637 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4642 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4643 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4645 /* set up to autoclear timer, and the vectors */
4646 mask = IXGBE_EIMS_ENABLE_MASK;
4647 mask &= ~(IXGBE_EIMS_OTHER |
4648 IXGBE_EIMS_MAILBOX |
4651 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4654 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4655 uint16_t queue_idx, uint16_t tx_rate)
4657 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4658 uint32_t rf_dec, rf_int;
4660 uint16_t link_speed = dev->data->dev_link.link_speed;
4662 if (queue_idx >= hw->mac.max_tx_queues)
4666 /* Calculate the rate factor values to set */
4667 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4668 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4669 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4671 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4672 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4673 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4674 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4680 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4681 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4684 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4685 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4686 IXGBE_MAX_JUMBO_FRAME_SIZE))
4687 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4688 IXGBE_MMW_SIZE_JUMBO_FRAME);
4690 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4691 IXGBE_MMW_SIZE_DEFAULT);
4693 /* Set RTTBCNRC of queue X */
4694 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4695 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4696 IXGBE_WRITE_FLUSH(hw);
4701 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4702 uint16_t tx_rate, uint64_t q_msk)
4704 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4705 struct ixgbe_vf_info *vfinfo =
4706 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4707 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4708 uint32_t queue_stride =
4709 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4710 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4711 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4712 uint16_t total_rate = 0;
4714 if (queue_end >= hw->mac.max_tx_queues)
4717 if (vfinfo != NULL) {
4718 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4721 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4723 total_rate += vfinfo[vf_idx].tx_rate[idx];
4728 /* Store tx_rate for this vf. */
4729 for (idx = 0; idx < nb_q_per_pool; idx++) {
4730 if (((uint64_t)0x1 << idx) & q_msk) {
4731 if (vfinfo[vf].tx_rate[idx] != tx_rate)
4732 vfinfo[vf].tx_rate[idx] = tx_rate;
4733 total_rate += tx_rate;
4737 if (total_rate > dev->data->dev_link.link_speed) {
4739 * Reset stored TX rate of the VF if it causes exceed
4742 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4746 /* Set RTTBCNRC of each queue/pool for vf X */
4747 for (; queue_idx <= queue_end; queue_idx++) {
4749 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4757 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4758 __attribute__((unused)) uint32_t index,
4759 __attribute__((unused)) uint32_t pool)
4761 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4765 * On a 82599 VF, adding again the same MAC addr is not an idempotent
4766 * operation. Trap this case to avoid exhausting the [very limited]
4767 * set of PF resources used to store VF MAC addresses.
4769 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4771 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4774 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4778 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4780 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4781 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4782 struct ether_addr *mac_addr;
4787 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4788 * not support the deletion of a given MAC address.
4789 * Instead, it imposes to delete all MAC addresses, then to add again
4790 * all MAC addresses with the exception of the one to be deleted.
4792 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4795 * Add again all MAC addresses, with the exception of the deleted one
4796 * and of the permanent MAC address.
4798 for (i = 0, mac_addr = dev->data->mac_addrs;
4799 i < hw->mac.num_rar_entries; i++, mac_addr++) {
4800 /* Skip the deleted MAC address */
4803 /* Skip NULL MAC addresses */
4804 if (is_zero_ether_addr(mac_addr))
4806 /* Skip the permanent MAC address */
4807 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4809 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4812 "Adding again MAC address "
4813 "%02x:%02x:%02x:%02x:%02x:%02x failed "
4815 mac_addr->addr_bytes[0],
4816 mac_addr->addr_bytes[1],
4817 mac_addr->addr_bytes[2],
4818 mac_addr->addr_bytes[3],
4819 mac_addr->addr_bytes[4],
4820 mac_addr->addr_bytes[5],
4826 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4828 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4830 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4833 #define MAC_TYPE_FILTER_SUP(type) do {\
4834 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4835 (type) != ixgbe_mac_X550)\
4840 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4841 struct rte_eth_syn_filter *filter,
4844 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4847 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4850 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4853 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4855 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4856 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4858 if (filter->hig_pri)
4859 synqf |= IXGBE_SYN_FILTER_SYNQFP;
4861 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4863 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4865 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4867 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4868 IXGBE_WRITE_FLUSH(hw);
4873 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4874 struct rte_eth_syn_filter *filter)
4876 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4877 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4879 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4880 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4881 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4888 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4889 enum rte_filter_op filter_op,
4892 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4895 MAC_TYPE_FILTER_SUP(hw->mac.type);
4897 if (filter_op == RTE_ETH_FILTER_NOP)
4901 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4906 switch (filter_op) {
4907 case RTE_ETH_FILTER_ADD:
4908 ret = ixgbe_syn_filter_set(dev,
4909 (struct rte_eth_syn_filter *)arg,
4912 case RTE_ETH_FILTER_DELETE:
4913 ret = ixgbe_syn_filter_set(dev,
4914 (struct rte_eth_syn_filter *)arg,
4917 case RTE_ETH_FILTER_GET:
4918 ret = ixgbe_syn_filter_get(dev,
4919 (struct rte_eth_syn_filter *)arg);
4922 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
4931 static inline enum ixgbe_5tuple_protocol
4932 convert_protocol_type(uint8_t protocol_value)
4934 if (protocol_value == IPPROTO_TCP)
4935 return IXGBE_FILTER_PROTOCOL_TCP;
4936 else if (protocol_value == IPPROTO_UDP)
4937 return IXGBE_FILTER_PROTOCOL_UDP;
4938 else if (protocol_value == IPPROTO_SCTP)
4939 return IXGBE_FILTER_PROTOCOL_SCTP;
4941 return IXGBE_FILTER_PROTOCOL_NONE;
4945 * add a 5tuple filter
4948 * dev: Pointer to struct rte_eth_dev.
4949 * index: the index the filter allocates.
4950 * filter: ponter to the filter that will be added.
4951 * rx_queue: the queue id the filter assigned to.
4954 * - On success, zero.
4955 * - On failure, a negative value.
4958 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
4959 struct ixgbe_5tuple_filter *filter)
4961 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4962 struct ixgbe_filter_info *filter_info =
4963 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4965 uint32_t ftqf, sdpqf;
4966 uint32_t l34timir = 0;
4967 uint8_t mask = 0xff;
4970 * look for an unused 5tuple filter index,
4971 * and insert the filter to list.
4973 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
4974 idx = i / (sizeof(uint32_t) * NBBY);
4975 shift = i % (sizeof(uint32_t) * NBBY);
4976 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
4977 filter_info->fivetuple_mask[idx] |= 1 << shift;
4979 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4985 if (i >= IXGBE_MAX_FTQF_FILTERS) {
4986 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4990 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
4991 IXGBE_SDPQF_DSTPORT_SHIFT);
4992 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
4994 ftqf = (uint32_t)(filter->filter_info.proto &
4995 IXGBE_FTQF_PROTOCOL_MASK);
4996 ftqf |= (uint32_t)((filter->filter_info.priority &
4997 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
4998 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
4999 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5000 if (filter->filter_info.dst_ip_mask == 0)
5001 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5002 if (filter->filter_info.src_port_mask == 0)
5003 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5004 if (filter->filter_info.dst_port_mask == 0)
5005 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5006 if (filter->filter_info.proto_mask == 0)
5007 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5008 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5009 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5010 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5012 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5013 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5014 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5015 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5017 l34timir |= IXGBE_L34T_IMIR_RESERVE;
5018 l34timir |= (uint32_t)(filter->queue <<
5019 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5020 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5025 * remove a 5tuple filter
5028 * dev: Pointer to struct rte_eth_dev.
5029 * filter: the pointer of the filter will be removed.
5032 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5033 struct ixgbe_5tuple_filter *filter)
5035 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5036 struct ixgbe_filter_info *filter_info =
5037 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5038 uint16_t index = filter->index;
5040 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5041 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5042 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5045 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5046 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5047 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5048 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5049 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5053 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5055 struct ixgbe_hw *hw;
5056 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5058 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5060 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5063 /* refuse mtu that requires the support of scattered packets when this
5064 * feature has not been enabled before. */
5065 if (!dev->data->scattered_rx &&
5066 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5067 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5071 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5072 * request of the version 2.0 of the mailbox API.
5073 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5074 * of the mailbox API.
5075 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5076 * prior to 3.11.33 which contains the following change:
5077 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5079 ixgbevf_rlpml_set_vf(hw, max_frame);
5081 /* update max frame size */
5082 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5086 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
5087 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5091 static inline struct ixgbe_5tuple_filter *
5092 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5093 struct ixgbe_5tuple_filter_info *key)
5095 struct ixgbe_5tuple_filter *it;
5097 TAILQ_FOREACH(it, filter_list, entries) {
5098 if (memcmp(key, &it->filter_info,
5099 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5106 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5108 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5109 struct ixgbe_5tuple_filter_info *filter_info)
5111 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5112 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5113 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5116 switch (filter->dst_ip_mask) {
5118 filter_info->dst_ip_mask = 0;
5119 filter_info->dst_ip = filter->dst_ip;
5122 filter_info->dst_ip_mask = 1;
5125 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5129 switch (filter->src_ip_mask) {
5131 filter_info->src_ip_mask = 0;
5132 filter_info->src_ip = filter->src_ip;
5135 filter_info->src_ip_mask = 1;
5138 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5142 switch (filter->dst_port_mask) {
5144 filter_info->dst_port_mask = 0;
5145 filter_info->dst_port = filter->dst_port;
5148 filter_info->dst_port_mask = 1;
5151 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5155 switch (filter->src_port_mask) {
5157 filter_info->src_port_mask = 0;
5158 filter_info->src_port = filter->src_port;
5161 filter_info->src_port_mask = 1;
5164 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5168 switch (filter->proto_mask) {
5170 filter_info->proto_mask = 0;
5171 filter_info->proto =
5172 convert_protocol_type(filter->proto);
5175 filter_info->proto_mask = 1;
5178 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5182 filter_info->priority = (uint8_t)filter->priority;
5187 * add or delete a ntuple filter
5190 * dev: Pointer to struct rte_eth_dev.
5191 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5192 * add: if true, add filter, if false, remove filter
5195 * - On success, zero.
5196 * - On failure, a negative value.
5199 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5200 struct rte_eth_ntuple_filter *ntuple_filter,
5203 struct ixgbe_filter_info *filter_info =
5204 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5205 struct ixgbe_5tuple_filter_info filter_5tuple;
5206 struct ixgbe_5tuple_filter *filter;
5209 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5210 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5214 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5215 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5219 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5221 if (filter != NULL && add) {
5222 PMD_DRV_LOG(ERR, "filter exists.");
5225 if (filter == NULL && !add) {
5226 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5231 filter = rte_zmalloc("ixgbe_5tuple_filter",
5232 sizeof(struct ixgbe_5tuple_filter), 0);
5235 (void)rte_memcpy(&filter->filter_info,
5237 sizeof(struct ixgbe_5tuple_filter_info));
5238 filter->queue = ntuple_filter->queue;
5239 ret = ixgbe_add_5tuple_filter(dev, filter);
5245 ixgbe_remove_5tuple_filter(dev, filter);
5251 * get a ntuple filter
5254 * dev: Pointer to struct rte_eth_dev.
5255 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5258 * - On success, zero.
5259 * - On failure, a negative value.
5262 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5263 struct rte_eth_ntuple_filter *ntuple_filter)
5265 struct ixgbe_filter_info *filter_info =
5266 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5267 struct ixgbe_5tuple_filter_info filter_5tuple;
5268 struct ixgbe_5tuple_filter *filter;
5271 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5272 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5276 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5277 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5281 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5283 if (filter == NULL) {
5284 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5287 ntuple_filter->queue = filter->queue;
5292 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5293 * @dev: pointer to rte_eth_dev structure
5294 * @filter_op:operation will be taken.
5295 * @arg: a pointer to specific structure corresponding to the filter_op
5298 * - On success, zero.
5299 * - On failure, a negative value.
5302 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5303 enum rte_filter_op filter_op,
5306 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5309 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5311 if (filter_op == RTE_ETH_FILTER_NOP)
5315 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5320 switch (filter_op) {
5321 case RTE_ETH_FILTER_ADD:
5322 ret = ixgbe_add_del_ntuple_filter(dev,
5323 (struct rte_eth_ntuple_filter *)arg,
5326 case RTE_ETH_FILTER_DELETE:
5327 ret = ixgbe_add_del_ntuple_filter(dev,
5328 (struct rte_eth_ntuple_filter *)arg,
5331 case RTE_ETH_FILTER_GET:
5332 ret = ixgbe_get_ntuple_filter(dev,
5333 (struct rte_eth_ntuple_filter *)arg);
5336 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5344 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5349 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5350 if (filter_info->ethertype_filters[i] == ethertype &&
5351 (filter_info->ethertype_mask & (1 << i)))
5358 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5363 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5364 if (!(filter_info->ethertype_mask & (1 << i))) {
5365 filter_info->ethertype_mask |= 1 << i;
5366 filter_info->ethertype_filters[i] = ethertype;
5374 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5377 if (idx >= IXGBE_MAX_ETQF_FILTERS)
5379 filter_info->ethertype_mask &= ~(1 << idx);
5380 filter_info->ethertype_filters[idx] = 0;
5385 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5386 struct rte_eth_ethertype_filter *filter,
5389 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5390 struct ixgbe_filter_info *filter_info =
5391 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5396 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5399 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5400 filter->ether_type == ETHER_TYPE_IPv6) {
5401 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5402 " ethertype filter.", filter->ether_type);
5406 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5407 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5410 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5411 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5415 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5416 if (ret >= 0 && add) {
5417 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5418 filter->ether_type);
5421 if (ret < 0 && !add) {
5422 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5423 filter->ether_type);
5428 ret = ixgbe_ethertype_filter_insert(filter_info,
5429 filter->ether_type);
5431 PMD_DRV_LOG(ERR, "ethertype filters are full.");
5434 etqf = IXGBE_ETQF_FILTER_EN;
5435 etqf |= (uint32_t)filter->ether_type;
5436 etqs |= (uint32_t)((filter->queue <<
5437 IXGBE_ETQS_RX_QUEUE_SHIFT) &
5438 IXGBE_ETQS_RX_QUEUE);
5439 etqs |= IXGBE_ETQS_QUEUE_EN;
5441 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5445 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5446 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5447 IXGBE_WRITE_FLUSH(hw);
5453 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5454 struct rte_eth_ethertype_filter *filter)
5456 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5457 struct ixgbe_filter_info *filter_info =
5458 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5459 uint32_t etqf, etqs;
5462 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5464 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5465 filter->ether_type);
5469 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5470 if (etqf & IXGBE_ETQF_FILTER_EN) {
5471 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5472 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5474 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5475 IXGBE_ETQS_RX_QUEUE_SHIFT;
5482 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5483 * @dev: pointer to rte_eth_dev structure
5484 * @filter_op:operation will be taken.
5485 * @arg: a pointer to specific structure corresponding to the filter_op
5488 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5489 enum rte_filter_op filter_op,
5492 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5495 MAC_TYPE_FILTER_SUP(hw->mac.type);
5497 if (filter_op == RTE_ETH_FILTER_NOP)
5501 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5506 switch (filter_op) {
5507 case RTE_ETH_FILTER_ADD:
5508 ret = ixgbe_add_del_ethertype_filter(dev,
5509 (struct rte_eth_ethertype_filter *)arg,
5512 case RTE_ETH_FILTER_DELETE:
5513 ret = ixgbe_add_del_ethertype_filter(dev,
5514 (struct rte_eth_ethertype_filter *)arg,
5517 case RTE_ETH_FILTER_GET:
5518 ret = ixgbe_get_ethertype_filter(dev,
5519 (struct rte_eth_ethertype_filter *)arg);
5522 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5530 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5531 enum rte_filter_type filter_type,
5532 enum rte_filter_op filter_op,
5537 switch (filter_type) {
5538 case RTE_ETH_FILTER_NTUPLE:
5539 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5541 case RTE_ETH_FILTER_ETHERTYPE:
5542 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5544 case RTE_ETH_FILTER_SYN:
5545 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5547 case RTE_ETH_FILTER_FDIR:
5548 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5551 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5560 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5561 u8 **mc_addr_ptr, u32 *vmdq)
5566 mc_addr = *mc_addr_ptr;
5567 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5572 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5573 struct ether_addr *mc_addr_set,
5574 uint32_t nb_mc_addr)
5576 struct ixgbe_hw *hw;
5579 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5580 mc_addr_list = (u8 *)mc_addr_set;
5581 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5582 ixgbe_dev_addr_list_itr, TRUE);
5586 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5588 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5592 /* Enable system time for platforms where it isn't on by default. */
5593 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5594 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5595 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5597 /* Start incrementing the register used to timestamp PTP packets. */
5598 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
5600 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5601 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5603 IXGBE_ETQF_FILTER_EN |
5606 /* Enable timestamping of received PTP packets. */
5607 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5608 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5609 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5611 /* Enable timestamping of transmitted PTP packets. */
5612 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5613 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5614 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5620 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5622 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5625 /* Disable timestamping of transmitted PTP packets. */
5626 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5627 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5628 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5630 /* Disable timestamping of received PTP packets. */
5631 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5632 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5633 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5635 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5636 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5638 /* Stop incrementating the System Time registers. */
5639 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5645 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5646 struct timespec *timestamp,
5647 uint32_t flags __rte_unused)
5649 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5650 uint32_t tsync_rxctl;
5654 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5655 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5658 rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5659 rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
5661 timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
5662 timestamp->tv_nsec = 0;
5668 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5669 struct timespec *timestamp)
5671 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5672 uint32_t tsync_txctl;
5676 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5677 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5680 tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5681 tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
5683 timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
5684 timestamp->tv_nsec = 0;
5690 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5692 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5695 const struct reg_info *reg_group;
5696 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5697 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5699 while ((reg_group = reg_set[g_ind++]))
5700 count += ixgbe_regs_group_count(reg_group);
5706 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5710 const struct reg_info *reg_group;
5712 while ((reg_group = ixgbevf_regs[g_ind++]))
5713 count += ixgbe_regs_group_count(reg_group);
5719 ixgbe_get_regs(struct rte_eth_dev *dev,
5720 struct rte_dev_reg_info *regs)
5722 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5723 uint32_t *data = regs->data;
5726 const struct reg_info *reg_group;
5727 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5728 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5730 /* Support only full register dump */
5731 if ((regs->length == 0) ||
5732 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
5733 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5735 while ((reg_group = reg_set[g_ind++]))
5736 count += ixgbe_read_regs_group(dev, &data[count],
5745 ixgbevf_get_regs(struct rte_eth_dev *dev,
5746 struct rte_dev_reg_info *regs)
5748 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5749 uint32_t *data = regs->data;
5752 const struct reg_info *reg_group;
5754 /* Support only full register dump */
5755 if ((regs->length == 0) ||
5756 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
5757 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5759 while ((reg_group = ixgbevf_regs[g_ind++]))
5760 count += ixgbe_read_regs_group(dev, &data[count],
5769 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
5771 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5773 /* Return unit is byte count */
5774 return hw->eeprom.word_size * 2;
5778 ixgbe_get_eeprom(struct rte_eth_dev *dev,
5779 struct rte_dev_eeprom_info *in_eeprom)
5781 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5782 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5783 uint16_t *data = in_eeprom->data;
5786 first = in_eeprom->offset >> 1;
5787 length = in_eeprom->length >> 1;
5788 if ((first > hw->eeprom.word_size) ||
5789 ((first + length) > hw->eeprom.word_size))
5792 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5794 return eeprom->ops.read_buffer(hw, first, length, data);
5798 ixgbe_set_eeprom(struct rte_eth_dev *dev,
5799 struct rte_dev_eeprom_info *in_eeprom)
5801 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5802 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5803 uint16_t *data = in_eeprom->data;
5806 first = in_eeprom->offset >> 1;
5807 length = in_eeprom->length >> 1;
5808 if ((first > hw->eeprom.word_size) ||
5809 ((first + length) > hw->eeprom.word_size))
5812 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5814 return eeprom->ops.write_buffer(hw, first, length, data);
5818 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
5820 case ixgbe_mac_X550:
5821 case ixgbe_mac_X550EM_x:
5822 return ETH_RSS_RETA_SIZE_512;
5823 case ixgbe_mac_X550_vf:
5824 case ixgbe_mac_X550EM_x_vf:
5825 return ETH_RSS_RETA_SIZE_64;
5827 return ETH_RSS_RETA_SIZE_128;
5832 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
5834 case ixgbe_mac_X550:
5835 case ixgbe_mac_X550EM_x:
5836 if (reta_idx < ETH_RSS_RETA_SIZE_128)
5837 return IXGBE_RETA(reta_idx >> 2);
5839 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
5840 case ixgbe_mac_X550_vf:
5841 case ixgbe_mac_X550EM_x_vf:
5842 return IXGBE_VFRETA(reta_idx >> 2);
5844 return IXGBE_RETA(reta_idx >> 2);
5849 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
5851 case ixgbe_mac_X550_vf:
5852 case ixgbe_mac_X550EM_x_vf:
5853 return IXGBE_VFMRQC;
5860 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
5862 case ixgbe_mac_X550_vf:
5863 case ixgbe_mac_X550EM_x_vf:
5864 return IXGBE_VFRSSRK(i);
5866 return IXGBE_RSSRK(i);
5871 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
5873 case ixgbe_mac_82599_vf:
5874 case ixgbe_mac_X540_vf:
5882 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
5883 struct rte_eth_dcb_info *dcb_info)
5885 struct ixgbe_dcb_config *dcb_config =
5886 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
5887 struct ixgbe_dcb_tc_config *tc;
5890 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
5891 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
5893 dcb_info->nb_tcs = 1;
5895 if (dcb_config->vt_mode) { /* vt is enabled*/
5896 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
5897 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
5898 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
5899 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
5900 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
5901 for (j = 0; j < dcb_info->nb_tcs; j++) {
5902 dcb_info->tc_queue.tc_rxq[i][j].base =
5903 i * dcb_info->nb_tcs + j;
5904 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
5905 dcb_info->tc_queue.tc_txq[i][j].base =
5906 i * dcb_info->nb_tcs + j;
5907 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
5910 } else { /* vt is disabled*/
5911 struct rte_eth_dcb_rx_conf *rx_conf =
5912 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
5913 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
5914 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
5915 if (dcb_info->nb_tcs == ETH_4_TCS) {
5916 for (i = 0; i < dcb_info->nb_tcs; i++) {
5917 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
5918 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
5920 dcb_info->tc_queue.tc_txq[0][0].base = 0;
5921 dcb_info->tc_queue.tc_txq[0][1].base = 64;
5922 dcb_info->tc_queue.tc_txq[0][2].base = 96;
5923 dcb_info->tc_queue.tc_txq[0][3].base = 112;
5924 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
5925 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
5926 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
5927 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
5928 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
5929 for (i = 0; i < dcb_info->nb_tcs; i++) {
5930 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
5931 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
5933 dcb_info->tc_queue.tc_txq[0][0].base = 0;
5934 dcb_info->tc_queue.tc_txq[0][1].base = 32;
5935 dcb_info->tc_queue.tc_txq[0][2].base = 64;
5936 dcb_info->tc_queue.tc_txq[0][3].base = 80;
5937 dcb_info->tc_queue.tc_txq[0][4].base = 96;
5938 dcb_info->tc_queue.tc_txq[0][5].base = 104;
5939 dcb_info->tc_queue.tc_txq[0][6].base = 112;
5940 dcb_info->tc_queue.tc_txq[0][7].base = 120;
5941 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
5942 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
5943 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
5944 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
5945 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
5946 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
5947 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
5948 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
5951 for (i = 0; i < dcb_info->nb_tcs; i++) {
5952 tc = &dcb_config->tc_config[i];
5953 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
5958 static struct rte_driver rte_ixgbe_driver = {
5960 .init = rte_ixgbe_pmd_init,
5963 static struct rte_driver rte_ixgbevf_driver = {
5965 .init = rte_ixgbevf_pmd_init,
5968 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
5969 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);