4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
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13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
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18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
64 #include "ixgbe_logs.h"
65 #include "base/ixgbe_api.h"
66 #include "base/ixgbe_vf.h"
67 #include "base/ixgbe_common.h"
68 #include "ixgbe_ethdev.h"
69 #include "ixgbe_bypass.h"
70 #include "ixgbe_rxtx.h"
71 #include "base/ixgbe_type.h"
72 #include "base/ixgbe_phy.h"
73 #include "ixgbe_regs.h"
75 #include "rte_pmd_ixgbe.h"
78 * High threshold controlling when to start sending XOFF frames. Must be at
79 * least 8 bytes less than receive packet buffer size. This value is in units
82 #define IXGBE_FC_HI 0x80
85 * Low threshold controlling when to start sending XON frames. This value is
86 * in units of 1024 bytes.
88 #define IXGBE_FC_LO 0x40
90 /* Default minimum inter-interrupt interval for EITR configuration */
91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
93 /* Timer value included in XOFF frames. */
94 #define IXGBE_FC_PAUSE 0x680
96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
97 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
98 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
100 #define IXGBE_MMW_SIZE_DEFAULT 0x4
101 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
102 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
105 * Default values for RX/TX configuration
107 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
108 #define IXGBE_DEFAULT_RX_PTHRESH 8
109 #define IXGBE_DEFAULT_RX_HTHRESH 8
110 #define IXGBE_DEFAULT_RX_WTHRESH 0
112 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
113 #define IXGBE_DEFAULT_TX_PTHRESH 32
114 #define IXGBE_DEFAULT_TX_HTHRESH 0
115 #define IXGBE_DEFAULT_TX_WTHRESH 0
116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
118 /* Bit shift and mask */
119 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
120 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
121 #define IXGBE_8_BIT_WIDTH CHAR_BIT
122 #define IXGBE_8_BIT_MASK UINT8_MAX
124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
128 #define IXGBE_HKEY_MAX_INDEX 10
130 /* Additional timesync values. */
131 #define NSEC_PER_SEC 1000000000L
132 #define IXGBE_INCVAL_10GB 0x66666666
133 #define IXGBE_INCVAL_1GB 0x40000000
134 #define IXGBE_INCVAL_100 0x50000000
135 #define IXGBE_INCVAL_SHIFT_10GB 28
136 #define IXGBE_INCVAL_SHIFT_1GB 24
137 #define IXGBE_INCVAL_SHIFT_100 21
138 #define IXGBE_INCVAL_SHIFT_82599 7
139 #define IXGBE_INCPER_SHIFT_82599 24
141 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
143 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
145 #define DEFAULT_ETAG_ETYPE 0x893f
146 #define IXGBE_ETAG_ETYPE 0x00005084
147 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
148 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
149 #define IXGBE_RAH_ADTYPE 0x40000000
150 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
151 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
154 #define IXGBE_QDE_STRIP_TAG 0x00000004
155 #define IXGBE_VTEICR_MASK 0x07
157 enum ixgbevf_xcast_modes {
158 IXGBEVF_XCAST_MODE_NONE = 0,
159 IXGBEVF_XCAST_MODE_MULTI,
160 IXGBEVF_XCAST_MODE_ALLMULTI,
163 #define IXGBE_EXVET_VET_EXT_SHIFT 16
164 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
166 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
167 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
168 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
169 static int ixgbe_dev_start(struct rte_eth_dev *dev);
170 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
171 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
172 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
173 static void ixgbe_dev_close(struct rte_eth_dev *dev);
174 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
175 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
176 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
177 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
178 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
179 int wait_to_complete);
180 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
181 struct rte_eth_stats *stats);
182 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
183 struct rte_eth_xstat *xstats, unsigned n);
184 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
185 struct rte_eth_xstat *xstats, unsigned n);
186 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
187 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
188 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
189 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
190 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
191 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
192 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
196 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
198 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
199 struct rte_eth_dev_info *dev_info);
200 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
201 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
202 struct rte_eth_dev_info *dev_info);
203 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
205 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
206 uint16_t vlan_id, int on);
207 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
208 enum rte_vlan_type vlan_type,
210 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
211 uint16_t queue, bool on);
212 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
214 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
215 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
216 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
217 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
218 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
220 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
221 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
222 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
223 struct rte_eth_fc_conf *fc_conf);
224 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
225 struct rte_eth_fc_conf *fc_conf);
226 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
227 struct rte_eth_pfc_conf *pfc_conf);
228 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
229 struct rte_eth_rss_reta_entry64 *reta_conf,
231 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
232 struct rte_eth_rss_reta_entry64 *reta_conf,
234 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
235 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
236 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
237 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
238 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
239 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
240 struct rte_intr_handle *handle);
241 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
243 static void ixgbe_dev_interrupt_delayed_handler(void *param);
244 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
245 uint32_t index, uint32_t pool);
246 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
247 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
248 struct ether_addr *mac_addr);
249 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
251 /* For Virtual Function support */
252 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
253 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
254 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
255 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
256 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
257 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
258 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
259 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
260 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
261 struct rte_eth_stats *stats);
262 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
263 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
264 uint16_t vlan_id, int on);
265 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
266 uint16_t queue, int on);
267 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
268 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
269 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
271 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
273 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
274 uint8_t queue, uint8_t msix_vector);
275 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
276 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
277 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
279 /* For Eth VMDQ APIs support */
280 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
281 ether_addr * mac_addr, uint8_t on);
282 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
283 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
284 struct rte_eth_mirror_conf *mirror_conf,
285 uint8_t rule_id, uint8_t on);
286 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
288 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
290 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
292 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
293 uint8_t queue, uint8_t msix_vector);
294 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
296 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
297 uint16_t queue_idx, uint16_t tx_rate);
299 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
300 struct ether_addr *mac_addr,
301 uint32_t index, uint32_t pool);
302 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
303 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
304 struct ether_addr *mac_addr);
305 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
306 struct rte_eth_syn_filter *filter,
308 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
309 struct rte_eth_syn_filter *filter);
310 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
311 enum rte_filter_op filter_op,
313 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
314 struct ixgbe_5tuple_filter *filter);
315 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
316 struct ixgbe_5tuple_filter *filter);
317 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
318 struct rte_eth_ntuple_filter *filter,
320 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
321 enum rte_filter_op filter_op,
323 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
324 struct rte_eth_ntuple_filter *filter);
325 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
326 struct rte_eth_ethertype_filter *filter,
328 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
329 enum rte_filter_op filter_op,
331 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
332 struct rte_eth_ethertype_filter *filter);
333 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
334 enum rte_filter_type filter_type,
335 enum rte_filter_op filter_op,
337 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
339 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
340 struct ether_addr *mc_addr_set,
341 uint32_t nb_mc_addr);
342 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
343 struct rte_eth_dcb_info *dcb_info);
345 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
346 static int ixgbe_get_regs(struct rte_eth_dev *dev,
347 struct rte_dev_reg_info *regs);
348 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
349 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
350 struct rte_dev_eeprom_info *eeprom);
351 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
352 struct rte_dev_eeprom_info *eeprom);
354 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
355 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
356 struct rte_dev_reg_info *regs);
358 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
359 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
360 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
361 struct timespec *timestamp,
363 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
364 struct timespec *timestamp);
365 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
366 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
367 struct timespec *timestamp);
368 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
369 const struct timespec *timestamp);
370 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
373 static int ixgbe_dev_l2_tunnel_eth_type_conf
374 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
375 static int ixgbe_dev_l2_tunnel_offload_set
376 (struct rte_eth_dev *dev,
377 struct rte_eth_l2_tunnel_conf *l2_tunnel,
380 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
381 enum rte_filter_op filter_op,
384 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
385 struct rte_eth_udp_tunnel *udp_tunnel);
386 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
387 struct rte_eth_udp_tunnel *udp_tunnel);
390 * Define VF Stats MACRO for Non "cleared on read" register
392 #define UPDATE_VF_STAT(reg, last, cur) \
394 uint32_t latest = IXGBE_READ_REG(hw, reg); \
395 cur += (latest - last) & UINT_MAX; \
399 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
401 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
402 u64 new_msb = IXGBE_READ_REG(hw, msb); \
403 u64 latest = ((new_msb << 32) | new_lsb); \
404 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
408 #define IXGBE_SET_HWSTRIP(h, q) do {\
409 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
410 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
411 (h)->bitmap[idx] |= 1 << bit;\
414 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
415 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
416 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
417 (h)->bitmap[idx] &= ~(1 << bit);\
420 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
421 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
422 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
423 (r) = (h)->bitmap[idx] >> bit & 1;\
427 * The set of PCI devices this driver supports
429 static const struct rte_pci_id pci_id_ixgbe_map[] = {
430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
483 #ifdef RTE_NIC_BYPASS
484 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
486 { .vendor_id = 0, /* sentinel */ },
490 * The set of PCI devices this driver supports (for 82599 VF)
492 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
493 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
494 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
495 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
500 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
501 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
502 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
503 { .vendor_id = 0, /* sentinel */ },
506 static const struct rte_eth_desc_lim rx_desc_lim = {
507 .nb_max = IXGBE_MAX_RING_DESC,
508 .nb_min = IXGBE_MIN_RING_DESC,
509 .nb_align = IXGBE_RXD_ALIGN,
512 static const struct rte_eth_desc_lim tx_desc_lim = {
513 .nb_max = IXGBE_MAX_RING_DESC,
514 .nb_min = IXGBE_MIN_RING_DESC,
515 .nb_align = IXGBE_TXD_ALIGN,
516 .nb_seg_max = IXGBE_TX_MAX_SEG,
517 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
520 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
521 .dev_configure = ixgbe_dev_configure,
522 .dev_start = ixgbe_dev_start,
523 .dev_stop = ixgbe_dev_stop,
524 .dev_set_link_up = ixgbe_dev_set_link_up,
525 .dev_set_link_down = ixgbe_dev_set_link_down,
526 .dev_close = ixgbe_dev_close,
527 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
528 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
529 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
530 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
531 .link_update = ixgbe_dev_link_update,
532 .stats_get = ixgbe_dev_stats_get,
533 .xstats_get = ixgbe_dev_xstats_get,
534 .stats_reset = ixgbe_dev_stats_reset,
535 .xstats_reset = ixgbe_dev_xstats_reset,
536 .xstats_get_names = ixgbe_dev_xstats_get_names,
537 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
538 .fw_version_get = ixgbe_fw_version_get,
539 .dev_infos_get = ixgbe_dev_info_get,
540 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
541 .mtu_set = ixgbe_dev_mtu_set,
542 .vlan_filter_set = ixgbe_vlan_filter_set,
543 .vlan_tpid_set = ixgbe_vlan_tpid_set,
544 .vlan_offload_set = ixgbe_vlan_offload_set,
545 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
546 .rx_queue_start = ixgbe_dev_rx_queue_start,
547 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
548 .tx_queue_start = ixgbe_dev_tx_queue_start,
549 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
550 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
551 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
552 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
553 .rx_queue_release = ixgbe_dev_rx_queue_release,
554 .rx_queue_count = ixgbe_dev_rx_queue_count,
555 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
556 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
557 .tx_queue_release = ixgbe_dev_tx_queue_release,
558 .dev_led_on = ixgbe_dev_led_on,
559 .dev_led_off = ixgbe_dev_led_off,
560 .flow_ctrl_get = ixgbe_flow_ctrl_get,
561 .flow_ctrl_set = ixgbe_flow_ctrl_set,
562 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
563 .mac_addr_add = ixgbe_add_rar,
564 .mac_addr_remove = ixgbe_remove_rar,
565 .mac_addr_set = ixgbe_set_default_mac_addr,
566 .uc_hash_table_set = ixgbe_uc_hash_table_set,
567 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
568 .mirror_rule_set = ixgbe_mirror_rule_set,
569 .mirror_rule_reset = ixgbe_mirror_rule_reset,
570 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
571 .reta_update = ixgbe_dev_rss_reta_update,
572 .reta_query = ixgbe_dev_rss_reta_query,
573 #ifdef RTE_NIC_BYPASS
574 .bypass_init = ixgbe_bypass_init,
575 .bypass_state_set = ixgbe_bypass_state_store,
576 .bypass_state_show = ixgbe_bypass_state_show,
577 .bypass_event_set = ixgbe_bypass_event_store,
578 .bypass_event_show = ixgbe_bypass_event_show,
579 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
580 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
581 .bypass_ver_show = ixgbe_bypass_ver_show,
582 .bypass_wd_reset = ixgbe_bypass_wd_reset,
583 #endif /* RTE_NIC_BYPASS */
584 .rss_hash_update = ixgbe_dev_rss_hash_update,
585 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
586 .filter_ctrl = ixgbe_dev_filter_ctrl,
587 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
588 .rxq_info_get = ixgbe_rxq_info_get,
589 .txq_info_get = ixgbe_txq_info_get,
590 .timesync_enable = ixgbe_timesync_enable,
591 .timesync_disable = ixgbe_timesync_disable,
592 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
593 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
594 .get_reg = ixgbe_get_regs,
595 .get_eeprom_length = ixgbe_get_eeprom_length,
596 .get_eeprom = ixgbe_get_eeprom,
597 .set_eeprom = ixgbe_set_eeprom,
598 .get_dcb_info = ixgbe_dev_get_dcb_info,
599 .timesync_adjust_time = ixgbe_timesync_adjust_time,
600 .timesync_read_time = ixgbe_timesync_read_time,
601 .timesync_write_time = ixgbe_timesync_write_time,
602 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
603 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
604 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
605 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
609 * dev_ops for virtual function, bare necessities for basic vf
610 * operation have been implemented
612 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
613 .dev_configure = ixgbevf_dev_configure,
614 .dev_start = ixgbevf_dev_start,
615 .dev_stop = ixgbevf_dev_stop,
616 .link_update = ixgbe_dev_link_update,
617 .stats_get = ixgbevf_dev_stats_get,
618 .xstats_get = ixgbevf_dev_xstats_get,
619 .stats_reset = ixgbevf_dev_stats_reset,
620 .xstats_reset = ixgbevf_dev_stats_reset,
621 .xstats_get_names = ixgbevf_dev_xstats_get_names,
622 .dev_close = ixgbevf_dev_close,
623 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
624 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
625 .dev_infos_get = ixgbevf_dev_info_get,
626 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
627 .mtu_set = ixgbevf_dev_set_mtu,
628 .vlan_filter_set = ixgbevf_vlan_filter_set,
629 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
630 .vlan_offload_set = ixgbevf_vlan_offload_set,
631 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
632 .rx_queue_release = ixgbe_dev_rx_queue_release,
633 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
634 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
635 .tx_queue_release = ixgbe_dev_tx_queue_release,
636 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
637 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
638 .mac_addr_add = ixgbevf_add_mac_addr,
639 .mac_addr_remove = ixgbevf_remove_mac_addr,
640 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
641 .rxq_info_get = ixgbe_rxq_info_get,
642 .txq_info_get = ixgbe_txq_info_get,
643 .mac_addr_set = ixgbevf_set_default_mac_addr,
644 .get_reg = ixgbevf_get_regs,
645 .reta_update = ixgbe_dev_rss_reta_update,
646 .reta_query = ixgbe_dev_rss_reta_query,
647 .rss_hash_update = ixgbe_dev_rss_hash_update,
648 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
651 /* store statistics names and its offset in stats structure */
652 struct rte_ixgbe_xstats_name_off {
653 char name[RTE_ETH_XSTATS_NAME_SIZE];
657 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
658 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
659 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
660 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
661 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
662 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
663 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
664 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
665 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
666 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
667 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
668 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
669 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
670 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
671 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
672 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
674 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
676 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
677 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
678 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
679 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
680 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
681 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
682 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
683 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
684 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
685 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
686 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
687 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
688 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
689 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
690 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
691 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
692 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
694 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
696 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
697 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
698 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
699 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
701 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
703 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
705 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
707 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
709 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
711 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
714 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
715 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
716 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
718 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
719 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
720 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
721 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
722 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
724 {"rx_fcoe_no_direct_data_placement_ext_buff",
725 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
727 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
729 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
731 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
733 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
735 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
738 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
739 sizeof(rte_ixgbe_stats_strings[0]))
741 /* MACsec statistics */
742 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
743 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
745 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
746 out_pkts_encrypted)},
747 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
748 out_pkts_protected)},
749 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
750 out_octets_encrypted)},
751 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
752 out_octets_protected)},
753 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
755 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
757 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
759 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
760 in_pkts_unknownsci)},
761 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
762 in_octets_decrypted)},
763 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
764 in_octets_validated)},
765 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
767 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
769 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
771 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
773 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
775 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
777 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
779 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
780 in_pkts_notusingsa)},
783 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
784 sizeof(rte_ixgbe_macsec_strings[0]))
786 /* Per-queue statistics */
787 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
788 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
789 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
790 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
791 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
794 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
795 sizeof(rte_ixgbe_rxq_strings[0]))
796 #define IXGBE_NB_RXQ_PRIO_VALUES 8
798 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
799 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
800 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
801 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
805 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
806 sizeof(rte_ixgbe_txq_strings[0]))
807 #define IXGBE_NB_TXQ_PRIO_VALUES 8
809 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
810 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
813 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
814 sizeof(rte_ixgbevf_stats_strings[0]))
817 * Atomically reads the link status information from global
818 * structure rte_eth_dev.
821 * - Pointer to the structure rte_eth_dev to read from.
822 * - Pointer to the buffer to be saved with the link status.
825 * - On success, zero.
826 * - On failure, negative value.
829 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
830 struct rte_eth_link *link)
832 struct rte_eth_link *dst = link;
833 struct rte_eth_link *src = &(dev->data->dev_link);
835 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
836 *(uint64_t *)src) == 0)
843 * Atomically writes the link status information into global
844 * structure rte_eth_dev.
847 * - Pointer to the structure rte_eth_dev to read from.
848 * - Pointer to the buffer to be saved with the link status.
851 * - On success, zero.
852 * - On failure, negative value.
855 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
856 struct rte_eth_link *link)
858 struct rte_eth_link *dst = &(dev->data->dev_link);
859 struct rte_eth_link *src = link;
861 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
862 *(uint64_t *)src) == 0)
869 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
872 ixgbe_is_sfp(struct ixgbe_hw *hw)
874 switch (hw->phy.type) {
875 case ixgbe_phy_sfp_avago:
876 case ixgbe_phy_sfp_ftl:
877 case ixgbe_phy_sfp_intel:
878 case ixgbe_phy_sfp_unknown:
879 case ixgbe_phy_sfp_passive_tyco:
880 case ixgbe_phy_sfp_passive_unknown:
887 static inline int32_t
888 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
893 status = ixgbe_reset_hw(hw);
895 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
896 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
897 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
898 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
899 IXGBE_WRITE_FLUSH(hw);
905 ixgbe_enable_intr(struct rte_eth_dev *dev)
907 struct ixgbe_interrupt *intr =
908 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
909 struct ixgbe_hw *hw =
910 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
912 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
913 IXGBE_WRITE_FLUSH(hw);
917 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
920 ixgbe_disable_intr(struct ixgbe_hw *hw)
922 PMD_INIT_FUNC_TRACE();
924 if (hw->mac.type == ixgbe_mac_82598EB) {
925 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
927 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
928 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
929 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
931 IXGBE_WRITE_FLUSH(hw);
935 * This function resets queue statistics mapping registers.
936 * From Niantic datasheet, Initialization of Statistics section:
937 * "...if software requires the queue counters, the RQSMR and TQSM registers
938 * must be re-programmed following a device reset.
941 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
945 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
946 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
947 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
953 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
958 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
959 #define NB_QMAP_FIELDS_PER_QSM_REG 4
960 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
962 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
963 struct ixgbe_stat_mapping_registers *stat_mappings =
964 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
965 uint32_t qsmr_mask = 0;
966 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
970 if ((hw->mac.type != ixgbe_mac_82599EB) &&
971 (hw->mac.type != ixgbe_mac_X540) &&
972 (hw->mac.type != ixgbe_mac_X550) &&
973 (hw->mac.type != ixgbe_mac_X550EM_x) &&
974 (hw->mac.type != ixgbe_mac_X550EM_a))
977 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
978 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
981 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
982 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
983 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
986 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
988 /* Now clear any previous stat_idx set */
989 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
991 stat_mappings->tqsm[n] &= ~clearing_mask;
993 stat_mappings->rqsmr[n] &= ~clearing_mask;
995 q_map = (uint32_t)stat_idx;
996 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
997 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
999 stat_mappings->tqsm[n] |= qsmr_mask;
1001 stat_mappings->rqsmr[n] |= qsmr_mask;
1003 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1004 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1005 queue_id, stat_idx);
1006 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1007 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1009 /* Now write the mapping in the appropriate register */
1011 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1012 stat_mappings->rqsmr[n], n);
1013 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1015 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1016 stat_mappings->tqsm[n], n);
1017 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1023 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1025 struct ixgbe_stat_mapping_registers *stat_mappings =
1026 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1027 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1030 /* write whatever was in stat mapping table to the NIC */
1031 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1033 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1036 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1041 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1044 struct ixgbe_dcb_tc_config *tc;
1045 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1047 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1048 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1049 for (i = 0; i < dcb_max_tc; i++) {
1050 tc = &dcb_config->tc_config[i];
1051 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1052 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1053 (uint8_t)(100/dcb_max_tc + (i & 1));
1054 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1055 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1056 (uint8_t)(100/dcb_max_tc + (i & 1));
1057 tc->pfc = ixgbe_dcb_pfc_disabled;
1060 /* Initialize default user to priority mapping, UPx->TC0 */
1061 tc = &dcb_config->tc_config[0];
1062 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1063 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1064 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1065 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1066 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1068 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1069 dcb_config->pfc_mode_enable = false;
1070 dcb_config->vt_mode = true;
1071 dcb_config->round_robin_enable = false;
1072 /* support all DCB capabilities in 82599 */
1073 dcb_config->support.capabilities = 0xFF;
1075 /*we only support 4 Tcs for X540, X550 */
1076 if (hw->mac.type == ixgbe_mac_X540 ||
1077 hw->mac.type == ixgbe_mac_X550 ||
1078 hw->mac.type == ixgbe_mac_X550EM_x ||
1079 hw->mac.type == ixgbe_mac_X550EM_a) {
1080 dcb_config->num_tcs.pg_tcs = 4;
1081 dcb_config->num_tcs.pfc_tcs = 4;
1086 * Ensure that all locks are released before first NVM or PHY access
1089 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1094 * Phy lock should not fail in this early stage. If this is the case,
1095 * it is due to an improper exit of the application.
1096 * So force the release of the faulty lock. Release of common lock
1097 * is done automatically by swfw_sync function.
1099 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1100 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1101 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1103 ixgbe_release_swfw_semaphore(hw, mask);
1106 * These ones are more tricky since they are common to all ports; but
1107 * swfw_sync retries last long enough (1s) to be almost sure that if
1108 * lock can not be taken it is due to an improper lock of the
1111 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1112 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1113 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1115 ixgbe_release_swfw_semaphore(hw, mask);
1119 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1120 * It returns 0 on success.
1123 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1125 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1126 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1127 struct ixgbe_hw *hw =
1128 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1129 struct ixgbe_vfta *shadow_vfta =
1130 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1131 struct ixgbe_hwstrip *hwstrip =
1132 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1133 struct ixgbe_dcb_config *dcb_config =
1134 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1135 struct ixgbe_filter_info *filter_info =
1136 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1141 PMD_INIT_FUNC_TRACE();
1143 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1144 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1145 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1146 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1149 * For secondary processes, we don't initialise any further as primary
1150 * has already done this work. Only check we don't need a different
1151 * RX and TX function.
1153 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1154 struct ixgbe_tx_queue *txq;
1155 /* TX queue function in primary, set by last queue initialized
1156 * Tx queue may not initialized by primary process
1158 if (eth_dev->data->tx_queues) {
1159 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1160 ixgbe_set_tx_function(eth_dev, txq);
1162 /* Use default TX function if we get here */
1163 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1164 "Using default TX function.");
1167 ixgbe_set_rx_function(eth_dev);
1172 rte_eth_copy_pci_info(eth_dev, pci_dev);
1173 eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1175 /* Vendor and Device ID need to be set before init of shared code */
1176 hw->device_id = pci_dev->id.device_id;
1177 hw->vendor_id = pci_dev->id.vendor_id;
1178 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1179 hw->allow_unsupported_sfp = 1;
1181 /* Initialize the shared code (base driver) */
1182 #ifdef RTE_NIC_BYPASS
1183 diag = ixgbe_bypass_init_shared_code(hw);
1185 diag = ixgbe_init_shared_code(hw);
1186 #endif /* RTE_NIC_BYPASS */
1188 if (diag != IXGBE_SUCCESS) {
1189 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1193 /* pick up the PCI bus settings for reporting later */
1194 ixgbe_get_bus_info(hw);
1196 /* Unlock any pending hardware semaphore */
1197 ixgbe_swfw_lock_reset(hw);
1199 /* Initialize DCB configuration*/
1200 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1201 ixgbe_dcb_init(hw, dcb_config);
1202 /* Get Hardware Flow Control setting */
1203 hw->fc.requested_mode = ixgbe_fc_full;
1204 hw->fc.current_mode = ixgbe_fc_full;
1205 hw->fc.pause_time = IXGBE_FC_PAUSE;
1206 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1207 hw->fc.low_water[i] = IXGBE_FC_LO;
1208 hw->fc.high_water[i] = IXGBE_FC_HI;
1210 hw->fc.send_xon = 1;
1212 /* Make sure we have a good EEPROM before we read from it */
1213 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1214 if (diag != IXGBE_SUCCESS) {
1215 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1219 #ifdef RTE_NIC_BYPASS
1220 diag = ixgbe_bypass_init_hw(hw);
1222 diag = ixgbe_init_hw(hw);
1223 #endif /* RTE_NIC_BYPASS */
1226 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1227 * is called too soon after the kernel driver unbinding/binding occurs.
1228 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1229 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1230 * also called. See ixgbe_identify_phy_82599(). The reason for the
1231 * failure is not known, and only occuts when virtualisation features
1232 * are disabled in the bios. A delay of 100ms was found to be enough by
1233 * trial-and-error, and is doubled to be safe.
1235 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1237 diag = ixgbe_init_hw(hw);
1240 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1241 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1242 "LOM. Please be aware there may be issues associated "
1243 "with your hardware.");
1244 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1245 "please contact your Intel or hardware representative "
1246 "who provided you with this hardware.");
1247 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1248 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1250 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1254 /* Reset the hw statistics */
1255 ixgbe_dev_stats_reset(eth_dev);
1257 /* disable interrupt */
1258 ixgbe_disable_intr(hw);
1260 /* reset mappings for queue statistics hw counters*/
1261 ixgbe_reset_qstat_mappings(hw);
1263 /* Allocate memory for storing MAC addresses */
1264 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1265 hw->mac.num_rar_entries, 0);
1266 if (eth_dev->data->mac_addrs == NULL) {
1268 "Failed to allocate %u bytes needed to store "
1270 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1273 /* Copy the permanent MAC address */
1274 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1275 ð_dev->data->mac_addrs[0]);
1277 /* Allocate memory for storing hash filter MAC addresses */
1278 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1279 IXGBE_VMDQ_NUM_UC_MAC, 0);
1280 if (eth_dev->data->hash_mac_addrs == NULL) {
1282 "Failed to allocate %d bytes needed to store MAC addresses",
1283 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1287 /* initialize the vfta */
1288 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1290 /* initialize the hw strip bitmap*/
1291 memset(hwstrip, 0, sizeof(*hwstrip));
1293 /* initialize PF if max_vfs not zero */
1294 ixgbe_pf_host_init(eth_dev);
1296 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1297 /* let hardware know driver is loaded */
1298 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1299 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1300 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1301 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1302 IXGBE_WRITE_FLUSH(hw);
1304 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1305 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1306 (int) hw->mac.type, (int) hw->phy.type,
1307 (int) hw->phy.sfp_type);
1309 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1310 (int) hw->mac.type, (int) hw->phy.type);
1312 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1313 eth_dev->data->port_id, pci_dev->id.vendor_id,
1314 pci_dev->id.device_id);
1316 rte_intr_callback_register(intr_handle,
1317 ixgbe_dev_interrupt_handler, eth_dev);
1319 /* enable uio/vfio intr/eventfd mapping */
1320 rte_intr_enable(intr_handle);
1322 /* enable support intr */
1323 ixgbe_enable_intr(eth_dev);
1325 /* initialize 5tuple filter list */
1326 TAILQ_INIT(&filter_info->fivetuple_list);
1327 memset(filter_info->fivetuple_mask, 0,
1328 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1334 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1336 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1337 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1338 struct ixgbe_hw *hw;
1340 PMD_INIT_FUNC_TRACE();
1342 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1345 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1347 if (hw->adapter_stopped == 0)
1348 ixgbe_dev_close(eth_dev);
1350 eth_dev->dev_ops = NULL;
1351 eth_dev->rx_pkt_burst = NULL;
1352 eth_dev->tx_pkt_burst = NULL;
1354 /* Unlock any pending hardware semaphore */
1355 ixgbe_swfw_lock_reset(hw);
1357 /* disable uio intr before callback unregister */
1358 rte_intr_disable(intr_handle);
1359 rte_intr_callback_unregister(intr_handle,
1360 ixgbe_dev_interrupt_handler, eth_dev);
1362 /* uninitialize PF if max_vfs not zero */
1363 ixgbe_pf_host_uninit(eth_dev);
1365 rte_free(eth_dev->data->mac_addrs);
1366 eth_dev->data->mac_addrs = NULL;
1368 rte_free(eth_dev->data->hash_mac_addrs);
1369 eth_dev->data->hash_mac_addrs = NULL;
1375 * Negotiate mailbox API version with the PF.
1376 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1377 * Then we try to negotiate starting with the most recent one.
1378 * If all negotiation attempts fail, then we will proceed with
1379 * the default one (ixgbe_mbox_api_10).
1382 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1386 /* start with highest supported, proceed down */
1387 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1394 i != RTE_DIM(sup_ver) &&
1395 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1401 generate_random_mac_addr(struct ether_addr *mac_addr)
1405 /* Set Organizationally Unique Identifier (OUI) prefix. */
1406 mac_addr->addr_bytes[0] = 0x00;
1407 mac_addr->addr_bytes[1] = 0x09;
1408 mac_addr->addr_bytes[2] = 0xC0;
1409 /* Force indication of locally assigned MAC address. */
1410 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1411 /* Generate the last 3 bytes of the MAC address with a random number. */
1412 random = rte_rand();
1413 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1417 * Virtual Function device init
1420 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1424 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1425 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1426 struct ixgbe_hw *hw =
1427 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1428 struct ixgbe_vfta *shadow_vfta =
1429 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1430 struct ixgbe_hwstrip *hwstrip =
1431 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1432 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1434 PMD_INIT_FUNC_TRACE();
1436 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1437 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1438 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1440 /* for secondary processes, we don't initialise any further as primary
1441 * has already done this work. Only check we don't need a different
1444 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1445 struct ixgbe_tx_queue *txq;
1446 /* TX queue function in primary, set by last queue initialized
1447 * Tx queue may not initialized by primary process
1449 if (eth_dev->data->tx_queues) {
1450 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1451 ixgbe_set_tx_function(eth_dev, txq);
1453 /* Use default TX function if we get here */
1454 PMD_INIT_LOG(NOTICE,
1455 "No TX queues configured yet. Using default TX function.");
1458 ixgbe_set_rx_function(eth_dev);
1463 rte_eth_copy_pci_info(eth_dev, pci_dev);
1464 eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1466 hw->device_id = pci_dev->id.device_id;
1467 hw->vendor_id = pci_dev->id.vendor_id;
1468 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1470 /* initialize the vfta */
1471 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1473 /* initialize the hw strip bitmap*/
1474 memset(hwstrip, 0, sizeof(*hwstrip));
1476 /* Initialize the shared code (base driver) */
1477 diag = ixgbe_init_shared_code(hw);
1478 if (diag != IXGBE_SUCCESS) {
1479 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1483 /* init_mailbox_params */
1484 hw->mbx.ops.init_params(hw);
1486 /* Reset the hw statistics */
1487 ixgbevf_dev_stats_reset(eth_dev);
1489 /* Disable the interrupts for VF */
1490 ixgbevf_intr_disable(hw);
1492 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1493 diag = hw->mac.ops.reset_hw(hw);
1496 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1497 * the underlying PF driver has not assigned a MAC address to the VF.
1498 * In this case, assign a random MAC address.
1500 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1501 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1505 /* negotiate mailbox API version to use with the PF. */
1506 ixgbevf_negotiate_api(hw);
1508 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1509 ixgbevf_get_queues(hw, &tcs, &tc);
1511 /* Allocate memory for storing MAC addresses */
1512 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1513 hw->mac.num_rar_entries, 0);
1514 if (eth_dev->data->mac_addrs == NULL) {
1516 "Failed to allocate %u bytes needed to store "
1518 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1522 /* Generate a random MAC address, if none was assigned by PF. */
1523 if (is_zero_ether_addr(perm_addr)) {
1524 generate_random_mac_addr(perm_addr);
1525 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1527 rte_free(eth_dev->data->mac_addrs);
1528 eth_dev->data->mac_addrs = NULL;
1531 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1532 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1533 "%02x:%02x:%02x:%02x:%02x:%02x",
1534 perm_addr->addr_bytes[0],
1535 perm_addr->addr_bytes[1],
1536 perm_addr->addr_bytes[2],
1537 perm_addr->addr_bytes[3],
1538 perm_addr->addr_bytes[4],
1539 perm_addr->addr_bytes[5]);
1542 /* Copy the permanent MAC address */
1543 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1545 /* reset the hardware with the new settings */
1546 diag = hw->mac.ops.start_hw(hw);
1552 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1556 rte_intr_callback_register(intr_handle,
1557 ixgbevf_dev_interrupt_handler, eth_dev);
1558 rte_intr_enable(intr_handle);
1559 ixgbevf_intr_enable(hw);
1561 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1562 eth_dev->data->port_id, pci_dev->id.vendor_id,
1563 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1568 /* Virtual Function device uninit */
1571 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1573 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1574 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1575 struct ixgbe_hw *hw;
1577 PMD_INIT_FUNC_TRACE();
1579 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1582 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1584 if (hw->adapter_stopped == 0)
1585 ixgbevf_dev_close(eth_dev);
1587 eth_dev->dev_ops = NULL;
1588 eth_dev->rx_pkt_burst = NULL;
1589 eth_dev->tx_pkt_burst = NULL;
1591 /* Disable the interrupts for VF */
1592 ixgbevf_intr_disable(hw);
1594 rte_free(eth_dev->data->mac_addrs);
1595 eth_dev->data->mac_addrs = NULL;
1597 rte_intr_disable(intr_handle);
1598 rte_intr_callback_unregister(intr_handle,
1599 ixgbevf_dev_interrupt_handler, eth_dev);
1604 static struct eth_driver rte_ixgbe_pmd = {
1606 .id_table = pci_id_ixgbe_map,
1607 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1608 .probe = rte_eth_dev_pci_probe,
1609 .remove = rte_eth_dev_pci_remove,
1611 .eth_dev_init = eth_ixgbe_dev_init,
1612 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1613 .dev_private_size = sizeof(struct ixgbe_adapter),
1617 * virtual function driver struct
1619 static struct eth_driver rte_ixgbevf_pmd = {
1621 .id_table = pci_id_ixgbevf_map,
1622 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1623 .probe = rte_eth_dev_pci_probe,
1624 .remove = rte_eth_dev_pci_remove,
1626 .eth_dev_init = eth_ixgbevf_dev_init,
1627 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1628 .dev_private_size = sizeof(struct ixgbe_adapter),
1632 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1634 struct ixgbe_hw *hw =
1635 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1636 struct ixgbe_vfta *shadow_vfta =
1637 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1642 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1643 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1644 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1649 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1651 /* update local VFTA copy */
1652 shadow_vfta->vfta[vid_idx] = vfta;
1658 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1661 ixgbe_vlan_hw_strip_enable(dev, queue);
1663 ixgbe_vlan_hw_strip_disable(dev, queue);
1667 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1668 enum rte_vlan_type vlan_type,
1671 struct ixgbe_hw *hw =
1672 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1677 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1678 qinq &= IXGBE_DMATXCTL_GDV;
1680 switch (vlan_type) {
1681 case ETH_VLAN_TYPE_INNER:
1683 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1684 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1685 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1686 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1687 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1688 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1689 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1692 PMD_DRV_LOG(ERR, "Inner type is not supported"
1696 case ETH_VLAN_TYPE_OUTER:
1698 /* Only the high 16-bits is valid */
1699 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1700 IXGBE_EXVET_VET_EXT_SHIFT);
1702 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1703 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1704 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1705 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1706 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1707 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1708 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1714 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1722 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1724 struct ixgbe_hw *hw =
1725 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1728 PMD_INIT_FUNC_TRACE();
1730 /* Filter Table Disable */
1731 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1732 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1734 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1738 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1740 struct ixgbe_hw *hw =
1741 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1742 struct ixgbe_vfta *shadow_vfta =
1743 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1747 PMD_INIT_FUNC_TRACE();
1749 /* Filter Table Enable */
1750 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1751 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1752 vlnctrl |= IXGBE_VLNCTRL_VFE;
1754 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1756 /* write whatever is in local vfta copy */
1757 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1758 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1762 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1764 struct ixgbe_hwstrip *hwstrip =
1765 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1766 struct ixgbe_rx_queue *rxq;
1768 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1772 IXGBE_SET_HWSTRIP(hwstrip, queue);
1774 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1776 if (queue >= dev->data->nb_rx_queues)
1779 rxq = dev->data->rx_queues[queue];
1782 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1784 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1788 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1790 struct ixgbe_hw *hw =
1791 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1794 PMD_INIT_FUNC_TRACE();
1796 if (hw->mac.type == ixgbe_mac_82598EB) {
1797 /* No queue level support */
1798 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1802 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1803 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1804 ctrl &= ~IXGBE_RXDCTL_VME;
1805 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1807 /* record those setting for HW strip per queue */
1808 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1812 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1814 struct ixgbe_hw *hw =
1815 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1818 PMD_INIT_FUNC_TRACE();
1820 if (hw->mac.type == ixgbe_mac_82598EB) {
1821 /* No queue level supported */
1822 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1826 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1827 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1828 ctrl |= IXGBE_RXDCTL_VME;
1829 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1831 /* record those setting for HW strip per queue */
1832 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1836 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1838 struct ixgbe_hw *hw =
1839 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1842 struct ixgbe_rx_queue *rxq;
1844 PMD_INIT_FUNC_TRACE();
1846 if (hw->mac.type == ixgbe_mac_82598EB) {
1847 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1848 ctrl &= ~IXGBE_VLNCTRL_VME;
1849 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1851 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1852 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1853 rxq = dev->data->rx_queues[i];
1854 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1855 ctrl &= ~IXGBE_RXDCTL_VME;
1856 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1858 /* record those setting for HW strip per queue */
1859 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1865 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1867 struct ixgbe_hw *hw =
1868 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1871 struct ixgbe_rx_queue *rxq;
1873 PMD_INIT_FUNC_TRACE();
1875 if (hw->mac.type == ixgbe_mac_82598EB) {
1876 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1877 ctrl |= IXGBE_VLNCTRL_VME;
1878 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1880 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1881 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1882 rxq = dev->data->rx_queues[i];
1883 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1884 ctrl |= IXGBE_RXDCTL_VME;
1885 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1887 /* record those setting for HW strip per queue */
1888 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1894 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1896 struct ixgbe_hw *hw =
1897 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1900 PMD_INIT_FUNC_TRACE();
1902 /* DMATXCTRL: Geric Double VLAN Disable */
1903 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1904 ctrl &= ~IXGBE_DMATXCTL_GDV;
1905 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1907 /* CTRL_EXT: Global Double VLAN Disable */
1908 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1909 ctrl &= ~IXGBE_EXTENDED_VLAN;
1910 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1915 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1917 struct ixgbe_hw *hw =
1918 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1921 PMD_INIT_FUNC_TRACE();
1923 /* DMATXCTRL: Geric Double VLAN Enable */
1924 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1925 ctrl |= IXGBE_DMATXCTL_GDV;
1926 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1928 /* CTRL_EXT: Global Double VLAN Enable */
1929 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1930 ctrl |= IXGBE_EXTENDED_VLAN;
1931 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1933 /* Clear pooling mode of PFVTCTL. It's required by X550. */
1934 if (hw->mac.type == ixgbe_mac_X550 ||
1935 hw->mac.type == ixgbe_mac_X550EM_x ||
1936 hw->mac.type == ixgbe_mac_X550EM_a) {
1937 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1938 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1939 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1943 * VET EXT field in the EXVET register = 0x8100 by default
1944 * So no need to change. Same to VT field of DMATXCTL register
1949 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1951 if (mask & ETH_VLAN_STRIP_MASK) {
1952 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1953 ixgbe_vlan_hw_strip_enable_all(dev);
1955 ixgbe_vlan_hw_strip_disable_all(dev);
1958 if (mask & ETH_VLAN_FILTER_MASK) {
1959 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1960 ixgbe_vlan_hw_filter_enable(dev);
1962 ixgbe_vlan_hw_filter_disable(dev);
1965 if (mask & ETH_VLAN_EXTEND_MASK) {
1966 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1967 ixgbe_vlan_hw_extend_enable(dev);
1969 ixgbe_vlan_hw_extend_disable(dev);
1974 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1976 struct ixgbe_hw *hw =
1977 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1978 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1979 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1981 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1982 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1986 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1988 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
1993 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1996 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2002 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2003 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2009 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2011 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2012 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2013 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2014 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2016 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2017 /* check multi-queue mode */
2018 switch (dev_conf->rxmode.mq_mode) {
2019 case ETH_MQ_RX_VMDQ_DCB:
2020 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2022 case ETH_MQ_RX_VMDQ_DCB_RSS:
2023 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2024 PMD_INIT_LOG(ERR, "SRIOV active,"
2025 " unsupported mq_mode rx %d.",
2026 dev_conf->rxmode.mq_mode);
2029 case ETH_MQ_RX_VMDQ_RSS:
2030 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2031 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2032 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2033 PMD_INIT_LOG(ERR, "SRIOV is active,"
2034 " invalid queue number"
2035 " for VMDQ RSS, allowed"
2036 " value are 1, 2 or 4.");
2040 case ETH_MQ_RX_VMDQ_ONLY:
2041 case ETH_MQ_RX_NONE:
2042 /* if nothing mq mode configure, use default scheme */
2043 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2044 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2045 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2047 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2048 /* SRIOV only works in VMDq enable mode */
2049 PMD_INIT_LOG(ERR, "SRIOV is active,"
2050 " wrong mq_mode rx %d.",
2051 dev_conf->rxmode.mq_mode);
2055 switch (dev_conf->txmode.mq_mode) {
2056 case ETH_MQ_TX_VMDQ_DCB:
2057 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2058 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2060 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2061 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2065 /* check valid queue number */
2066 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2067 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2068 PMD_INIT_LOG(ERR, "SRIOV is active,"
2069 " nb_rx_q=%d nb_tx_q=%d queue number"
2070 " must be less than or equal to %d.",
2072 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2076 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2077 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2081 /* check configuration for vmdb+dcb mode */
2082 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2083 const struct rte_eth_vmdq_dcb_conf *conf;
2085 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2086 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2087 IXGBE_VMDQ_DCB_NB_QUEUES);
2090 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2091 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2092 conf->nb_queue_pools == ETH_32_POOLS)) {
2093 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2094 " nb_queue_pools must be %d or %d.",
2095 ETH_16_POOLS, ETH_32_POOLS);
2099 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2100 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2102 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2103 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2104 IXGBE_VMDQ_DCB_NB_QUEUES);
2107 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2108 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2109 conf->nb_queue_pools == ETH_32_POOLS)) {
2110 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2111 " nb_queue_pools != %d and"
2112 " nb_queue_pools != %d.",
2113 ETH_16_POOLS, ETH_32_POOLS);
2118 /* For DCB mode check our configuration before we go further */
2119 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2120 const struct rte_eth_dcb_rx_conf *conf;
2122 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2123 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2124 IXGBE_DCB_NB_QUEUES);
2127 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2128 if (!(conf->nb_tcs == ETH_4_TCS ||
2129 conf->nb_tcs == ETH_8_TCS)) {
2130 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2131 " and nb_tcs != %d.",
2132 ETH_4_TCS, ETH_8_TCS);
2137 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2138 const struct rte_eth_dcb_tx_conf *conf;
2140 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2141 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2142 IXGBE_DCB_NB_QUEUES);
2145 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2146 if (!(conf->nb_tcs == ETH_4_TCS ||
2147 conf->nb_tcs == ETH_8_TCS)) {
2148 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2149 " and nb_tcs != %d.",
2150 ETH_4_TCS, ETH_8_TCS);
2156 * When DCB/VT is off, maximum number of queues changes,
2157 * except for 82598EB, which remains constant.
2159 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2160 hw->mac.type != ixgbe_mac_82598EB) {
2161 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2163 "Neither VT nor DCB are enabled, "
2165 IXGBE_NONE_MODE_TX_NB_QUEUES);
2174 ixgbe_dev_configure(struct rte_eth_dev *dev)
2176 struct ixgbe_interrupt *intr =
2177 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2178 struct ixgbe_adapter *adapter =
2179 (struct ixgbe_adapter *)dev->data->dev_private;
2182 PMD_INIT_FUNC_TRACE();
2183 /* multipe queue mode checking */
2184 ret = ixgbe_check_mq_mode(dev);
2186 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2191 /* set flag to update link status after init */
2192 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2195 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2196 * allocation or vector Rx preconditions we will reset it.
2198 adapter->rx_bulk_alloc_allowed = true;
2199 adapter->rx_vec_allowed = true;
2205 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2207 struct ixgbe_hw *hw =
2208 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2209 struct ixgbe_interrupt *intr =
2210 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2213 /* only set up it on X550EM_X */
2214 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2215 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2216 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2217 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2218 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2219 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2224 * Configure device link speed and setup link.
2225 * It returns 0 on success.
2228 ixgbe_dev_start(struct rte_eth_dev *dev)
2230 struct ixgbe_hw *hw =
2231 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2232 struct ixgbe_vf_info *vfinfo =
2233 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2234 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2235 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2236 uint32_t intr_vector = 0;
2237 int err, link_up = 0, negotiate = 0;
2242 uint32_t *link_speeds;
2244 PMD_INIT_FUNC_TRACE();
2246 /* IXGBE devices don't support:
2247 * - half duplex (checked afterwards for valid speeds)
2248 * - fixed speed: TODO implement
2250 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2251 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2252 dev->data->port_id);
2256 /* disable uio/vfio intr/eventfd mapping */
2257 rte_intr_disable(intr_handle);
2260 hw->adapter_stopped = 0;
2261 ixgbe_stop_adapter(hw);
2263 /* reinitialize adapter
2264 * this calls reset and start
2266 status = ixgbe_pf_reset_hw(hw);
2269 hw->mac.ops.start_hw(hw);
2270 hw->mac.get_link_status = true;
2272 /* configure PF module if SRIOV enabled */
2273 ixgbe_pf_host_configure(dev);
2275 ixgbe_dev_phy_intr_setup(dev);
2277 /* check and configure queue intr-vector mapping */
2278 if ((rte_intr_cap_multiple(intr_handle) ||
2279 !RTE_ETH_DEV_SRIOV(dev).active) &&
2280 dev->data->dev_conf.intr_conf.rxq != 0) {
2281 intr_vector = dev->data->nb_rx_queues;
2282 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2283 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2284 IXGBE_MAX_INTR_QUEUE_NUM);
2287 if (rte_intr_efd_enable(intr_handle, intr_vector))
2291 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2292 intr_handle->intr_vec =
2293 rte_zmalloc("intr_vec",
2294 dev->data->nb_rx_queues * sizeof(int), 0);
2295 if (intr_handle->intr_vec == NULL) {
2296 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2297 " intr_vec\n", dev->data->nb_rx_queues);
2302 /* confiugre msix for sleep until rx interrupt */
2303 ixgbe_configure_msix(dev);
2305 /* initialize transmission unit */
2306 ixgbe_dev_tx_init(dev);
2308 /* This can fail when allocating mbufs for descriptor rings */
2309 err = ixgbe_dev_rx_init(dev);
2311 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2315 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2316 ETH_VLAN_EXTEND_MASK;
2317 ixgbe_vlan_offload_set(dev, mask);
2319 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2320 /* Enable vlan filtering for VMDq */
2321 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2324 /* Configure DCB hw */
2325 ixgbe_configure_dcb(dev);
2327 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2328 err = ixgbe_fdir_configure(dev);
2333 /* Restore vf rate limit */
2334 if (vfinfo != NULL) {
2335 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2336 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2337 if (vfinfo[vf].tx_rate[idx] != 0)
2338 rte_pmd_ixgbe_set_vf_rate_limit(
2339 dev->data->port_id, vf,
2340 vfinfo[vf].tx_rate[idx],
2344 ixgbe_restore_statistics_mapping(dev);
2346 err = ixgbe_dev_rxtx_start(dev);
2348 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2352 /* Skip link setup if loopback mode is enabled for 82599. */
2353 if (hw->mac.type == ixgbe_mac_82599EB &&
2354 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2355 goto skip_link_setup;
2357 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2358 err = hw->mac.ops.setup_sfp(hw);
2363 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2364 /* Turn on the copper */
2365 ixgbe_set_phy_power(hw, true);
2367 /* Turn on the laser */
2368 ixgbe_enable_tx_laser(hw);
2371 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2374 dev->data->dev_link.link_status = link_up;
2376 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2380 link_speeds = &dev->data->dev_conf.link_speeds;
2381 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2382 ETH_LINK_SPEED_10G)) {
2383 PMD_INIT_LOG(ERR, "Invalid link setting");
2388 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2389 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2390 IXGBE_LINK_SPEED_82599_AUTONEG :
2391 IXGBE_LINK_SPEED_82598_AUTONEG;
2393 if (*link_speeds & ETH_LINK_SPEED_10G)
2394 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2395 if (*link_speeds & ETH_LINK_SPEED_1G)
2396 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2397 if (*link_speeds & ETH_LINK_SPEED_100M)
2398 speed |= IXGBE_LINK_SPEED_100_FULL;
2401 err = ixgbe_setup_link(hw, speed, link_up);
2407 if (rte_intr_allow_others(intr_handle)) {
2408 /* check if lsc interrupt is enabled */
2409 if (dev->data->dev_conf.intr_conf.lsc != 0)
2410 ixgbe_dev_lsc_interrupt_setup(dev);
2411 ixgbe_dev_macsec_interrupt_setup(dev);
2413 rte_intr_callback_unregister(intr_handle,
2414 ixgbe_dev_interrupt_handler, dev);
2415 if (dev->data->dev_conf.intr_conf.lsc != 0)
2416 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2417 " no intr multiplex\n");
2420 /* check if rxq interrupt is enabled */
2421 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2422 rte_intr_dp_is_en(intr_handle))
2423 ixgbe_dev_rxq_interrupt_setup(dev);
2425 /* enable uio/vfio intr/eventfd mapping */
2426 rte_intr_enable(intr_handle);
2428 /* resume enabled intr since hw reset */
2429 ixgbe_enable_intr(dev);
2434 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2435 ixgbe_dev_clear_queues(dev);
2440 * Stop device: disable rx and tx functions to allow for reconfiguring.
2443 ixgbe_dev_stop(struct rte_eth_dev *dev)
2445 struct rte_eth_link link;
2446 struct ixgbe_hw *hw =
2447 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2448 struct ixgbe_vf_info *vfinfo =
2449 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2450 struct ixgbe_filter_info *filter_info =
2451 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2452 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2453 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2454 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2457 PMD_INIT_FUNC_TRACE();
2459 /* disable interrupts */
2460 ixgbe_disable_intr(hw);
2463 ixgbe_pf_reset_hw(hw);
2464 hw->adapter_stopped = 0;
2467 ixgbe_stop_adapter(hw);
2469 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2470 vfinfo[vf].clear_to_send = false;
2472 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2473 /* Turn off the copper */
2474 ixgbe_set_phy_power(hw, false);
2476 /* Turn off the laser */
2477 ixgbe_disable_tx_laser(hw);
2480 ixgbe_dev_clear_queues(dev);
2482 /* Clear stored conf */
2483 dev->data->scattered_rx = 0;
2486 /* Clear recorded link status */
2487 memset(&link, 0, sizeof(link));
2488 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2490 /* Remove all ntuple filters of the device */
2491 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2492 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2493 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2494 TAILQ_REMOVE(&filter_info->fivetuple_list,
2498 memset(filter_info->fivetuple_mask, 0,
2499 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2501 if (!rte_intr_allow_others(intr_handle))
2502 /* resume to the default handler */
2503 rte_intr_callback_register(intr_handle,
2504 ixgbe_dev_interrupt_handler,
2507 /* Clean datapath event and queue/vec mapping */
2508 rte_intr_efd_disable(intr_handle);
2509 if (intr_handle->intr_vec != NULL) {
2510 rte_free(intr_handle->intr_vec);
2511 intr_handle->intr_vec = NULL;
2516 * Set device link up: enable tx.
2519 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2521 struct ixgbe_hw *hw =
2522 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2523 if (hw->mac.type == ixgbe_mac_82599EB) {
2524 #ifdef RTE_NIC_BYPASS
2525 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2526 /* Not suported in bypass mode */
2527 PMD_INIT_LOG(ERR, "Set link up is not supported "
2528 "by device id 0x%x", hw->device_id);
2534 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2535 /* Turn on the copper */
2536 ixgbe_set_phy_power(hw, true);
2538 /* Turn on the laser */
2539 ixgbe_enable_tx_laser(hw);
2546 * Set device link down: disable tx.
2549 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2551 struct ixgbe_hw *hw =
2552 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2553 if (hw->mac.type == ixgbe_mac_82599EB) {
2554 #ifdef RTE_NIC_BYPASS
2555 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2556 /* Not suported in bypass mode */
2557 PMD_INIT_LOG(ERR, "Set link down is not supported "
2558 "by device id 0x%x", hw->device_id);
2564 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2565 /* Turn off the copper */
2566 ixgbe_set_phy_power(hw, false);
2568 /* Turn off the laser */
2569 ixgbe_disable_tx_laser(hw);
2576 * Reest and stop device.
2579 ixgbe_dev_close(struct rte_eth_dev *dev)
2581 struct ixgbe_hw *hw =
2582 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2584 PMD_INIT_FUNC_TRACE();
2586 ixgbe_pf_reset_hw(hw);
2588 ixgbe_dev_stop(dev);
2589 hw->adapter_stopped = 1;
2591 ixgbe_dev_free_queues(dev);
2593 ixgbe_disable_pcie_master(hw);
2595 /* reprogram the RAR[0] in case user changed it. */
2596 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2600 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2601 struct ixgbe_hw_stats *hw_stats,
2602 struct ixgbe_macsec_stats *macsec_stats,
2603 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2604 uint64_t *total_qprc, uint64_t *total_qprdc)
2606 uint32_t bprc, lxon, lxoff, total;
2607 uint32_t delta_gprc = 0;
2609 /* Workaround for RX byte count not including CRC bytes when CRC
2610 * strip is enabled. CRC bytes are removed from counters when crc_strip
2613 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2614 IXGBE_HLREG0_RXCRCSTRP);
2616 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2617 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2618 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2619 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2621 for (i = 0; i < 8; i++) {
2622 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2624 /* global total per queue */
2625 hw_stats->mpc[i] += mp;
2626 /* Running comprehensive total for stats display */
2627 *total_missed_rx += hw_stats->mpc[i];
2628 if (hw->mac.type == ixgbe_mac_82598EB) {
2629 hw_stats->rnbc[i] +=
2630 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2631 hw_stats->pxonrxc[i] +=
2632 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2633 hw_stats->pxoffrxc[i] +=
2634 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2636 hw_stats->pxonrxc[i] +=
2637 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2638 hw_stats->pxoffrxc[i] +=
2639 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2640 hw_stats->pxon2offc[i] +=
2641 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2643 hw_stats->pxontxc[i] +=
2644 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2645 hw_stats->pxofftxc[i] +=
2646 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2648 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2649 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2650 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2651 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2653 delta_gprc += delta_qprc;
2655 hw_stats->qprc[i] += delta_qprc;
2656 hw_stats->qptc[i] += delta_qptc;
2658 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2659 hw_stats->qbrc[i] +=
2660 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2662 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2664 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2665 hw_stats->qbtc[i] +=
2666 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2668 hw_stats->qprdc[i] += delta_qprdc;
2669 *total_qprdc += hw_stats->qprdc[i];
2671 *total_qprc += hw_stats->qprc[i];
2672 *total_qbrc += hw_stats->qbrc[i];
2674 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2675 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2676 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2679 * An errata states that gprc actually counts good + missed packets:
2680 * Workaround to set gprc to summated queue packet receives
2682 hw_stats->gprc = *total_qprc;
2684 if (hw->mac.type != ixgbe_mac_82598EB) {
2685 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2686 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2687 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2688 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2689 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2690 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2691 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2692 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2694 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2695 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2696 /* 82598 only has a counter in the high register */
2697 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2698 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2699 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2701 uint64_t old_tpr = hw_stats->tpr;
2703 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2704 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2707 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2709 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2710 hw_stats->gptc += delta_gptc;
2711 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2712 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2715 * Workaround: mprc hardware is incorrectly counting
2716 * broadcasts, so for now we subtract those.
2718 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2719 hw_stats->bprc += bprc;
2720 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2721 if (hw->mac.type == ixgbe_mac_82598EB)
2722 hw_stats->mprc -= bprc;
2724 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2725 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2726 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2727 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2728 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2729 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2731 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2732 hw_stats->lxontxc += lxon;
2733 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2734 hw_stats->lxofftxc += lxoff;
2735 total = lxon + lxoff;
2737 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2738 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2739 hw_stats->gptc -= total;
2740 hw_stats->mptc -= total;
2741 hw_stats->ptc64 -= total;
2742 hw_stats->gotc -= total * ETHER_MIN_LEN;
2744 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2745 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2746 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2747 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2748 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2749 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2750 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2751 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2752 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2753 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2754 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2755 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2756 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2757 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2758 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2759 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2760 /* Only read FCOE on 82599 */
2761 if (hw->mac.type != ixgbe_mac_82598EB) {
2762 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2763 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2764 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2765 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2766 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2769 /* Flow Director Stats registers */
2770 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2771 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2773 /* MACsec Stats registers */
2774 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2775 macsec_stats->out_pkts_encrypted +=
2776 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2777 macsec_stats->out_pkts_protected +=
2778 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2779 macsec_stats->out_octets_encrypted +=
2780 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2781 macsec_stats->out_octets_protected +=
2782 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2783 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2784 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2785 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2786 macsec_stats->in_pkts_unknownsci +=
2787 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2788 macsec_stats->in_octets_decrypted +=
2789 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2790 macsec_stats->in_octets_validated +=
2791 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2792 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2793 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2794 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2795 for (i = 0; i < 2; i++) {
2796 macsec_stats->in_pkts_ok +=
2797 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2798 macsec_stats->in_pkts_invalid +=
2799 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2800 macsec_stats->in_pkts_notvalid +=
2801 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2803 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2804 macsec_stats->in_pkts_notusingsa +=
2805 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2809 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2812 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2814 struct ixgbe_hw *hw =
2815 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2816 struct ixgbe_hw_stats *hw_stats =
2817 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2818 struct ixgbe_macsec_stats *macsec_stats =
2819 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2820 dev->data->dev_private);
2821 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2824 total_missed_rx = 0;
2829 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2830 &total_qbrc, &total_qprc, &total_qprdc);
2835 /* Fill out the rte_eth_stats statistics structure */
2836 stats->ipackets = total_qprc;
2837 stats->ibytes = total_qbrc;
2838 stats->opackets = hw_stats->gptc;
2839 stats->obytes = hw_stats->gotc;
2841 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2842 stats->q_ipackets[i] = hw_stats->qprc[i];
2843 stats->q_opackets[i] = hw_stats->qptc[i];
2844 stats->q_ibytes[i] = hw_stats->qbrc[i];
2845 stats->q_obytes[i] = hw_stats->qbtc[i];
2846 stats->q_errors[i] = hw_stats->qprdc[i];
2850 stats->imissed = total_missed_rx;
2851 stats->ierrors = hw_stats->crcerrs +
2867 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2869 struct ixgbe_hw_stats *stats =
2870 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2872 /* HW registers are cleared on read */
2873 ixgbe_dev_stats_get(dev, NULL);
2875 /* Reset software totals */
2876 memset(stats, 0, sizeof(*stats));
2879 /* This function calculates the number of xstats based on the current config */
2881 ixgbe_xstats_calc_num(void) {
2882 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
2883 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2884 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2887 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2888 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2890 const unsigned cnt_stats = ixgbe_xstats_calc_num();
2891 unsigned stat, i, count;
2893 if (xstats_names != NULL) {
2896 /* Note: limit >= cnt_stats checked upstream
2897 * in rte_eth_xstats_names()
2900 /* Extended stats from ixgbe_hw_stats */
2901 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2902 snprintf(xstats_names[count].name,
2903 sizeof(xstats_names[count].name),
2905 rte_ixgbe_stats_strings[i].name);
2910 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
2911 snprintf(xstats_names[count].name,
2912 sizeof(xstats_names[count].name),
2914 rte_ixgbe_macsec_strings[i].name);
2918 /* RX Priority Stats */
2919 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2920 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2921 snprintf(xstats_names[count].name,
2922 sizeof(xstats_names[count].name),
2923 "rx_priority%u_%s", i,
2924 rte_ixgbe_rxq_strings[stat].name);
2929 /* TX Priority Stats */
2930 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2931 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2932 snprintf(xstats_names[count].name,
2933 sizeof(xstats_names[count].name),
2934 "tx_priority%u_%s", i,
2935 rte_ixgbe_txq_strings[stat].name);
2943 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2944 struct rte_eth_xstat_name *xstats_names, unsigned limit)
2948 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2951 if (xstats_names != NULL)
2952 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2953 snprintf(xstats_names[i].name,
2954 sizeof(xstats_names[i].name),
2955 "%s", rte_ixgbevf_stats_strings[i].name);
2956 return IXGBEVF_NB_XSTATS;
2960 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2963 struct ixgbe_hw *hw =
2964 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2965 struct ixgbe_hw_stats *hw_stats =
2966 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2967 struct ixgbe_macsec_stats *macsec_stats =
2968 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2969 dev->data->dev_private);
2970 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2971 unsigned i, stat, count = 0;
2973 count = ixgbe_xstats_calc_num();
2978 total_missed_rx = 0;
2983 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2984 &total_qbrc, &total_qprc, &total_qprdc);
2986 /* If this is a reset xstats is NULL, and we have cleared the
2987 * registers by reading them.
2992 /* Extended stats from ixgbe_hw_stats */
2994 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2995 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2996 rte_ixgbe_stats_strings[i].offset);
2997 xstats[count].id = count;
3002 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3003 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3004 rte_ixgbe_macsec_strings[i].offset);
3005 xstats[count].id = count;
3009 /* RX Priority Stats */
3010 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3011 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3012 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3013 rte_ixgbe_rxq_strings[stat].offset +
3014 (sizeof(uint64_t) * i));
3015 xstats[count].id = count;
3020 /* TX Priority Stats */
3021 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3022 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3023 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3024 rte_ixgbe_txq_strings[stat].offset +
3025 (sizeof(uint64_t) * i));
3026 xstats[count].id = count;
3034 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3036 struct ixgbe_hw_stats *stats =
3037 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3038 struct ixgbe_macsec_stats *macsec_stats =
3039 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3040 dev->data->dev_private);
3042 unsigned count = ixgbe_xstats_calc_num();
3044 /* HW registers are cleared on read */
3045 ixgbe_dev_xstats_get(dev, NULL, count);
3047 /* Reset software totals */
3048 memset(stats, 0, sizeof(*stats));
3049 memset(macsec_stats, 0, sizeof(*macsec_stats));
3053 ixgbevf_update_stats(struct rte_eth_dev *dev)
3055 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3056 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3057 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3059 /* Good Rx packet, include VF loopback */
3060 UPDATE_VF_STAT(IXGBE_VFGPRC,
3061 hw_stats->last_vfgprc, hw_stats->vfgprc);
3063 /* Good Rx octets, include VF loopback */
3064 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3065 hw_stats->last_vfgorc, hw_stats->vfgorc);
3067 /* Good Tx packet, include VF loopback */
3068 UPDATE_VF_STAT(IXGBE_VFGPTC,
3069 hw_stats->last_vfgptc, hw_stats->vfgptc);
3071 /* Good Tx octets, include VF loopback */
3072 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3073 hw_stats->last_vfgotc, hw_stats->vfgotc);
3075 /* Rx Multicst Packet */
3076 UPDATE_VF_STAT(IXGBE_VFMPRC,
3077 hw_stats->last_vfmprc, hw_stats->vfmprc);
3081 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3084 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3085 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3088 if (n < IXGBEVF_NB_XSTATS)
3089 return IXGBEVF_NB_XSTATS;
3091 ixgbevf_update_stats(dev);
3096 /* Extended stats */
3097 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3098 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3099 rte_ixgbevf_stats_strings[i].offset);
3102 return IXGBEVF_NB_XSTATS;
3106 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3108 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3109 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3111 ixgbevf_update_stats(dev);
3116 stats->ipackets = hw_stats->vfgprc;
3117 stats->ibytes = hw_stats->vfgorc;
3118 stats->opackets = hw_stats->vfgptc;
3119 stats->obytes = hw_stats->vfgotc;
3123 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3125 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3126 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3128 /* Sync HW register to the last stats */
3129 ixgbevf_dev_stats_get(dev, NULL);
3131 /* reset HW current stats*/
3132 hw_stats->vfgprc = 0;
3133 hw_stats->vfgorc = 0;
3134 hw_stats->vfgptc = 0;
3135 hw_stats->vfgotc = 0;
3139 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3141 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3142 u16 eeprom_verh, eeprom_verl;
3146 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3147 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3149 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3150 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3152 ret += 1; /* add the size of '\0' */
3153 if (fw_size < (u32)ret)
3160 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3162 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3163 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3164 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3166 dev_info->pci_dev = pci_dev;
3167 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3168 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3169 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3171 * When DCB/VT is off, maximum number of queues changes,
3172 * except for 82598EB, which remains constant.
3174 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3175 hw->mac.type != ixgbe_mac_82598EB)
3176 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3178 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3179 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3180 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3181 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3182 dev_info->max_vfs = pci_dev->max_vfs;
3183 if (hw->mac.type == ixgbe_mac_82598EB)
3184 dev_info->max_vmdq_pools = ETH_16_POOLS;
3186 dev_info->max_vmdq_pools = ETH_64_POOLS;
3187 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3188 dev_info->rx_offload_capa =
3189 DEV_RX_OFFLOAD_VLAN_STRIP |
3190 DEV_RX_OFFLOAD_IPV4_CKSUM |
3191 DEV_RX_OFFLOAD_UDP_CKSUM |
3192 DEV_RX_OFFLOAD_TCP_CKSUM;
3195 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3198 if ((hw->mac.type == ixgbe_mac_82599EB ||
3199 hw->mac.type == ixgbe_mac_X540) &&
3200 !RTE_ETH_DEV_SRIOV(dev).active)
3201 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3203 if (hw->mac.type == ixgbe_mac_82599EB ||
3204 hw->mac.type == ixgbe_mac_X540)
3205 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3207 if (hw->mac.type == ixgbe_mac_X550 ||
3208 hw->mac.type == ixgbe_mac_X550EM_x ||
3209 hw->mac.type == ixgbe_mac_X550EM_a)
3210 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3212 dev_info->tx_offload_capa =
3213 DEV_TX_OFFLOAD_VLAN_INSERT |
3214 DEV_TX_OFFLOAD_IPV4_CKSUM |
3215 DEV_TX_OFFLOAD_UDP_CKSUM |
3216 DEV_TX_OFFLOAD_TCP_CKSUM |
3217 DEV_TX_OFFLOAD_SCTP_CKSUM |
3218 DEV_TX_OFFLOAD_TCP_TSO;
3220 if (hw->mac.type == ixgbe_mac_82599EB ||
3221 hw->mac.type == ixgbe_mac_X540)
3222 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3224 if (hw->mac.type == ixgbe_mac_X550 ||
3225 hw->mac.type == ixgbe_mac_X550EM_x ||
3226 hw->mac.type == ixgbe_mac_X550EM_a)
3227 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3229 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3231 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3232 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3233 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3235 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3239 dev_info->default_txconf = (struct rte_eth_txconf) {
3241 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3242 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3243 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3245 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3246 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3247 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3248 ETH_TXQ_FLAGS_NOOFFLOADS,
3251 dev_info->rx_desc_lim = rx_desc_lim;
3252 dev_info->tx_desc_lim = tx_desc_lim;
3254 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3255 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3256 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3258 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3259 if (hw->mac.type == ixgbe_mac_X540 ||
3260 hw->mac.type == ixgbe_mac_X540_vf ||
3261 hw->mac.type == ixgbe_mac_X550 ||
3262 hw->mac.type == ixgbe_mac_X550_vf) {
3263 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3267 static const uint32_t *
3268 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3270 static const uint32_t ptypes[] = {
3271 /* For non-vec functions,
3272 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3273 * for vec functions,
3274 * refers to _recv_raw_pkts_vec().
3278 RTE_PTYPE_L3_IPV4_EXT,
3280 RTE_PTYPE_L3_IPV6_EXT,
3284 RTE_PTYPE_TUNNEL_IP,
3285 RTE_PTYPE_INNER_L3_IPV6,
3286 RTE_PTYPE_INNER_L3_IPV6_EXT,
3287 RTE_PTYPE_INNER_L4_TCP,
3288 RTE_PTYPE_INNER_L4_UDP,
3292 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3293 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3294 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3295 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3301 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3302 struct rte_eth_dev_info *dev_info)
3304 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3305 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3307 dev_info->pci_dev = pci_dev;
3308 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3309 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3310 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3311 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3312 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3313 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3314 dev_info->max_vfs = pci_dev->max_vfs;
3315 if (hw->mac.type == ixgbe_mac_82598EB)
3316 dev_info->max_vmdq_pools = ETH_16_POOLS;
3318 dev_info->max_vmdq_pools = ETH_64_POOLS;
3319 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3320 DEV_RX_OFFLOAD_IPV4_CKSUM |
3321 DEV_RX_OFFLOAD_UDP_CKSUM |
3322 DEV_RX_OFFLOAD_TCP_CKSUM;
3323 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3324 DEV_TX_OFFLOAD_IPV4_CKSUM |
3325 DEV_TX_OFFLOAD_UDP_CKSUM |
3326 DEV_TX_OFFLOAD_TCP_CKSUM |
3327 DEV_TX_OFFLOAD_SCTP_CKSUM |
3328 DEV_TX_OFFLOAD_TCP_TSO;
3330 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3332 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3333 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3334 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3336 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3340 dev_info->default_txconf = (struct rte_eth_txconf) {
3342 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3343 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3344 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3346 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3347 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3348 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3349 ETH_TXQ_FLAGS_NOOFFLOADS,
3352 dev_info->rx_desc_lim = rx_desc_lim;
3353 dev_info->tx_desc_lim = tx_desc_lim;
3356 /* return 0 means link status changed, -1 means not changed */
3358 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3360 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3361 struct rte_eth_link link, old;
3362 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3366 link.link_status = ETH_LINK_DOWN;
3367 link.link_speed = 0;
3368 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3369 memset(&old, 0, sizeof(old));
3370 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3372 hw->mac.get_link_status = true;
3374 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3375 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3376 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3378 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3381 link.link_speed = ETH_SPEED_NUM_100M;
3382 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3383 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3384 if (link.link_status == old.link_status)
3390 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3391 if (link.link_status == old.link_status)
3395 link.link_status = ETH_LINK_UP;
3396 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3398 switch (link_speed) {
3400 case IXGBE_LINK_SPEED_UNKNOWN:
3401 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3402 link.link_speed = ETH_SPEED_NUM_100M;
3405 case IXGBE_LINK_SPEED_100_FULL:
3406 link.link_speed = ETH_SPEED_NUM_100M;
3409 case IXGBE_LINK_SPEED_1GB_FULL:
3410 link.link_speed = ETH_SPEED_NUM_1G;
3413 case IXGBE_LINK_SPEED_10GB_FULL:
3414 link.link_speed = ETH_SPEED_NUM_10G;
3417 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3419 if (link.link_status == old.link_status)
3426 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3428 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3431 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3432 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3433 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3437 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3439 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3442 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3443 fctrl &= (~IXGBE_FCTRL_UPE);
3444 if (dev->data->all_multicast == 1)
3445 fctrl |= IXGBE_FCTRL_MPE;
3447 fctrl &= (~IXGBE_FCTRL_MPE);
3448 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3452 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3454 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3457 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3458 fctrl |= IXGBE_FCTRL_MPE;
3459 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3463 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3465 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3468 if (dev->data->promiscuous == 1)
3469 return; /* must remain in all_multicast mode */
3471 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3472 fctrl &= (~IXGBE_FCTRL_MPE);
3473 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3477 * It clears the interrupt causes and enables the interrupt.
3478 * It will be called once only during nic initialized.
3481 * Pointer to struct rte_eth_dev.
3484 * - On success, zero.
3485 * - On failure, a negative value.
3488 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3490 struct ixgbe_interrupt *intr =
3491 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3493 ixgbe_dev_link_status_print(dev);
3494 intr->mask |= IXGBE_EICR_LSC;
3500 * It clears the interrupt causes and enables the interrupt.
3501 * It will be called once only during nic initialized.
3504 * Pointer to struct rte_eth_dev.
3507 * - On success, zero.
3508 * - On failure, a negative value.
3511 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3513 struct ixgbe_interrupt *intr =
3514 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3516 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3522 * It clears the interrupt causes and enables the interrupt.
3523 * It will be called once only during nic initialized.
3526 * Pointer to struct rte_eth_dev.
3529 * - On success, zero.
3530 * - On failure, a negative value.
3533 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3535 struct ixgbe_interrupt *intr =
3536 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3538 intr->mask |= IXGBE_EICR_LINKSEC;
3544 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3547 * Pointer to struct rte_eth_dev.
3550 * - On success, zero.
3551 * - On failure, a negative value.
3554 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3557 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3558 struct ixgbe_interrupt *intr =
3559 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3561 /* clear all cause mask */
3562 ixgbe_disable_intr(hw);
3564 /* read-on-clear nic registers here */
3565 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3566 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3570 /* set flag for async link update */
3571 if (eicr & IXGBE_EICR_LSC)
3572 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3574 if (eicr & IXGBE_EICR_MAILBOX)
3575 intr->flags |= IXGBE_FLAG_MAILBOX;
3577 if (eicr & IXGBE_EICR_LINKSEC)
3578 intr->flags |= IXGBE_FLAG_MACSEC;
3580 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3581 hw->phy.type == ixgbe_phy_x550em_ext_t &&
3582 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3583 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3589 * It gets and then prints the link status.
3592 * Pointer to struct rte_eth_dev.
3595 * - On success, zero.
3596 * - On failure, a negative value.
3599 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3601 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3602 struct rte_eth_link link;
3604 memset(&link, 0, sizeof(link));
3605 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3606 if (link.link_status) {
3607 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3608 (int)(dev->data->port_id),
3609 (unsigned)link.link_speed,
3610 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3611 "full-duplex" : "half-duplex");
3613 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3614 (int)(dev->data->port_id));
3616 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3617 pci_dev->addr.domain,
3619 pci_dev->addr.devid,
3620 pci_dev->addr.function);
3624 * It executes link_update after knowing an interrupt occurred.
3627 * Pointer to struct rte_eth_dev.
3630 * - On success, zero.
3631 * - On failure, a negative value.
3634 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3635 struct rte_intr_handle *intr_handle)
3637 struct ixgbe_interrupt *intr =
3638 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3640 struct rte_eth_link link;
3641 int intr_enable_delay = false;
3642 struct ixgbe_hw *hw =
3643 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3645 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3647 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3648 ixgbe_pf_mbx_process(dev);
3649 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3652 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3653 ixgbe_handle_lasi(hw);
3654 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3657 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3658 /* get the link status before link update, for predicting later */
3659 memset(&link, 0, sizeof(link));
3660 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3662 ixgbe_dev_link_update(dev, 0);
3665 if (!link.link_status)
3666 /* handle it 1 sec later, wait it being stable */
3667 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3668 /* likely to down */
3670 /* handle it 4 sec later, wait it being stable */
3671 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3673 ixgbe_dev_link_status_print(dev);
3675 intr_enable_delay = true;
3678 if (intr_enable_delay) {
3679 if (rte_eal_alarm_set(timeout * 1000,
3680 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3681 PMD_DRV_LOG(ERR, "Error setting alarm");
3683 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3684 ixgbe_enable_intr(dev);
3685 rte_intr_enable(intr_handle);
3693 * Interrupt handler which shall be registered for alarm callback for delayed
3694 * handling specific interrupt to wait for the stable nic state. As the
3695 * NIC interrupt state is not stable for ixgbe after link is just down,
3696 * it needs to wait 4 seconds to get the stable status.
3699 * Pointer to interrupt handle.
3701 * The address of parameter (struct rte_eth_dev *) regsitered before.
3707 ixgbe_dev_interrupt_delayed_handler(void *param)
3709 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3710 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3711 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3712 struct ixgbe_interrupt *intr =
3713 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3714 struct ixgbe_hw *hw =
3715 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3718 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3719 if (eicr & IXGBE_EICR_MAILBOX)
3720 ixgbe_pf_mbx_process(dev);
3722 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3723 ixgbe_handle_lasi(hw);
3724 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3727 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3728 ixgbe_dev_link_update(dev, 0);
3729 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3730 ixgbe_dev_link_status_print(dev);
3731 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3734 if (intr->flags & IXGBE_FLAG_MACSEC) {
3735 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3737 intr->flags &= ~IXGBE_FLAG_MACSEC;
3740 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3741 ixgbe_enable_intr(dev);
3742 rte_intr_enable(intr_handle);
3746 * Interrupt handler triggered by NIC for handling
3747 * specific interrupt.
3750 * Pointer to interrupt handle.
3752 * The address of parameter (struct rte_eth_dev *) regsitered before.
3758 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3761 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3763 ixgbe_dev_interrupt_get_status(dev);
3764 ixgbe_dev_interrupt_action(dev, handle);
3768 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3770 struct ixgbe_hw *hw;
3772 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3773 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3777 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3779 struct ixgbe_hw *hw;
3781 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3782 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3786 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3788 struct ixgbe_hw *hw;
3794 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3796 fc_conf->pause_time = hw->fc.pause_time;
3797 fc_conf->high_water = hw->fc.high_water[0];
3798 fc_conf->low_water = hw->fc.low_water[0];
3799 fc_conf->send_xon = hw->fc.send_xon;
3800 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3803 * Return rx_pause status according to actual setting of
3806 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3807 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3813 * Return tx_pause status according to actual setting of
3816 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3817 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3822 if (rx_pause && tx_pause)
3823 fc_conf->mode = RTE_FC_FULL;
3825 fc_conf->mode = RTE_FC_RX_PAUSE;
3827 fc_conf->mode = RTE_FC_TX_PAUSE;
3829 fc_conf->mode = RTE_FC_NONE;
3835 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3837 struct ixgbe_hw *hw;
3839 uint32_t rx_buf_size;
3840 uint32_t max_high_water;
3842 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3849 PMD_INIT_FUNC_TRACE();
3851 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3852 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3853 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3856 * At least reserve one Ethernet frame for watermark
3857 * high_water/low_water in kilo bytes for ixgbe
3859 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3860 if ((fc_conf->high_water > max_high_water) ||
3861 (fc_conf->high_water < fc_conf->low_water)) {
3862 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3863 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3867 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3868 hw->fc.pause_time = fc_conf->pause_time;
3869 hw->fc.high_water[0] = fc_conf->high_water;
3870 hw->fc.low_water[0] = fc_conf->low_water;
3871 hw->fc.send_xon = fc_conf->send_xon;
3872 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3874 err = ixgbe_fc_enable(hw);
3876 /* Not negotiated is not an error case */
3877 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3879 /* check if we want to forward MAC frames - driver doesn't have native
3880 * capability to do that, so we'll write the registers ourselves */
3882 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3884 /* set or clear MFLCN.PMCF bit depending on configuration */
3885 if (fc_conf->mac_ctrl_frame_fwd != 0)
3886 mflcn |= IXGBE_MFLCN_PMCF;
3888 mflcn &= ~IXGBE_MFLCN_PMCF;
3890 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3891 IXGBE_WRITE_FLUSH(hw);
3896 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3901 * ixgbe_pfc_enable_generic - Enable flow control
3902 * @hw: pointer to hardware structure
3903 * @tc_num: traffic class number
3904 * Enable flow control according to the current settings.
3907 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3910 uint32_t mflcn_reg, fccfg_reg;
3912 uint32_t fcrtl, fcrth;
3916 /* Validate the water mark configuration */
3917 if (!hw->fc.pause_time) {
3918 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3922 /* Low water mark of zero causes XOFF floods */
3923 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3924 /* High/Low water can not be 0 */
3925 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3926 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3927 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3931 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3932 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3933 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3937 /* Negotiate the fc mode to use */
3938 ixgbe_fc_autoneg(hw);
3940 /* Disable any previous flow control settings */
3941 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3942 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3944 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3945 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3947 switch (hw->fc.current_mode) {
3950 * If the count of enabled RX Priority Flow control >1,
3951 * and the TX pause can not be disabled
3954 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3955 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3956 if (reg & IXGBE_FCRTH_FCEN)
3960 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3962 case ixgbe_fc_rx_pause:
3964 * Rx Flow control is enabled and Tx Flow control is
3965 * disabled by software override. Since there really
3966 * isn't a way to advertise that we are capable of RX
3967 * Pause ONLY, we will advertise that we support both
3968 * symmetric and asymmetric Rx PAUSE. Later, we will
3969 * disable the adapter's ability to send PAUSE frames.
3971 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3973 * If the count of enabled RX Priority Flow control >1,
3974 * and the TX pause can not be disabled
3977 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3978 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3979 if (reg & IXGBE_FCRTH_FCEN)
3983 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3985 case ixgbe_fc_tx_pause:
3987 * Tx Flow control is enabled, and Rx Flow control is
3988 * disabled by software override.
3990 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3993 /* Flow control (both Rx and Tx) is enabled by SW override. */
3994 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3995 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3998 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3999 ret_val = IXGBE_ERR_CONFIG;
4003 /* Set 802.3x based flow control settings. */
4004 mflcn_reg |= IXGBE_MFLCN_DPF;
4005 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4006 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4008 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4009 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4010 hw->fc.high_water[tc_num]) {
4011 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4012 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4013 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4015 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4017 * In order to prevent Tx hangs when the internal Tx
4018 * switch is enabled we must set the high water mark
4019 * to the maximum FCRTH value. This allows the Tx
4020 * switch to function even under heavy Rx workloads.
4022 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4024 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4026 /* Configure pause time (2 TCs per register) */
4027 reg = hw->fc.pause_time * 0x00010001;
4028 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4029 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4031 /* Configure flow control refresh threshold value */
4032 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4039 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4041 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4042 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4044 if (hw->mac.type != ixgbe_mac_82598EB) {
4045 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4051 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4054 uint32_t rx_buf_size;
4055 uint32_t max_high_water;
4057 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4058 struct ixgbe_hw *hw =
4059 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4060 struct ixgbe_dcb_config *dcb_config =
4061 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4063 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4070 PMD_INIT_FUNC_TRACE();
4072 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4073 tc_num = map[pfc_conf->priority];
4074 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4075 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4077 * At least reserve one Ethernet frame for watermark
4078 * high_water/low_water in kilo bytes for ixgbe
4080 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4081 if ((pfc_conf->fc.high_water > max_high_water) ||
4082 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4083 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4084 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4088 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4089 hw->fc.pause_time = pfc_conf->fc.pause_time;
4090 hw->fc.send_xon = pfc_conf->fc.send_xon;
4091 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4092 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4094 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4096 /* Not negotiated is not an error case */
4097 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4100 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4105 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4106 struct rte_eth_rss_reta_entry64 *reta_conf,
4109 uint16_t i, sp_reta_size;
4112 uint16_t idx, shift;
4113 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4116 PMD_INIT_FUNC_TRACE();
4118 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4119 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4124 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4125 if (reta_size != sp_reta_size) {
4126 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4127 "(%d) doesn't match the number hardware can supported "
4128 "(%d)\n", reta_size, sp_reta_size);
4132 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4133 idx = i / RTE_RETA_GROUP_SIZE;
4134 shift = i % RTE_RETA_GROUP_SIZE;
4135 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4139 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4140 if (mask == IXGBE_4_BIT_MASK)
4143 r = IXGBE_READ_REG(hw, reta_reg);
4144 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4145 if (mask & (0x1 << j))
4146 reta |= reta_conf[idx].reta[shift + j] <<
4149 reta |= r & (IXGBE_8_BIT_MASK <<
4152 IXGBE_WRITE_REG(hw, reta_reg, reta);
4159 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4160 struct rte_eth_rss_reta_entry64 *reta_conf,
4163 uint16_t i, sp_reta_size;
4166 uint16_t idx, shift;
4167 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4170 PMD_INIT_FUNC_TRACE();
4171 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4172 if (reta_size != sp_reta_size) {
4173 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4174 "(%d) doesn't match the number hardware can supported "
4175 "(%d)\n", reta_size, sp_reta_size);
4179 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4180 idx = i / RTE_RETA_GROUP_SIZE;
4181 shift = i % RTE_RETA_GROUP_SIZE;
4182 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4187 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4188 reta = IXGBE_READ_REG(hw, reta_reg);
4189 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4190 if (mask & (0x1 << j))
4191 reta_conf[idx].reta[shift + j] =
4192 ((reta >> (CHAR_BIT * j)) &
4201 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4202 uint32_t index, uint32_t pool)
4204 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4205 uint32_t enable_addr = 1;
4207 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4211 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4213 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4215 ixgbe_clear_rar(hw, index);
4219 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4221 ixgbe_remove_rar(dev, 0);
4223 ixgbe_add_rar(dev, addr, 0, 0);
4227 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4228 struct ether_addr *mac_addr)
4230 struct ixgbe_hw *hw;
4231 struct ixgbe_vf_info *vfinfo;
4233 uint8_t *new_mac = (uint8_t *)(mac_addr);
4234 struct rte_eth_dev *dev;
4235 struct rte_eth_dev_info dev_info;
4237 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4239 dev = &rte_eth_devices[port];
4240 rte_eth_dev_info_get(port, &dev_info);
4242 if (vf >= dev_info.max_vfs)
4245 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4246 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4247 rar_entry = hw->mac.num_rar_entries - (vf + 1);
4249 if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4250 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4252 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4259 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4263 struct ixgbe_hw *hw;
4264 struct rte_eth_dev_info dev_info;
4265 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4267 ixgbe_dev_info_get(dev, &dev_info);
4269 /* check that mtu is within the allowed range */
4270 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4273 /* refuse mtu that requires the support of scattered packets when this
4274 * feature has not been enabled before.
4276 if (!dev->data->scattered_rx &&
4277 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4278 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4281 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4282 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4284 /* switch to jumbo mode if needed */
4285 if (frame_size > ETHER_MAX_LEN) {
4286 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4287 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4289 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4290 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4292 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4294 /* update max frame size */
4295 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4297 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4298 maxfrs &= 0x0000FFFF;
4299 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4300 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4306 * Virtual Function operations
4309 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4311 PMD_INIT_FUNC_TRACE();
4313 /* Clear interrupt mask to stop from interrupts being generated */
4314 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4316 IXGBE_WRITE_FLUSH(hw);
4320 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4322 PMD_INIT_FUNC_TRACE();
4324 /* VF enable interrupt autoclean */
4325 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4326 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4327 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4329 IXGBE_WRITE_FLUSH(hw);
4333 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4335 struct rte_eth_conf *conf = &dev->data->dev_conf;
4336 struct ixgbe_adapter *adapter =
4337 (struct ixgbe_adapter *)dev->data->dev_private;
4339 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4340 dev->data->port_id);
4343 * VF has no ability to enable/disable HW CRC
4344 * Keep the persistent behavior the same as Host PF
4346 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4347 if (!conf->rxmode.hw_strip_crc) {
4348 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4349 conf->rxmode.hw_strip_crc = 1;
4352 if (conf->rxmode.hw_strip_crc) {
4353 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4354 conf->rxmode.hw_strip_crc = 0;
4359 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4360 * allocation or vector Rx preconditions we will reset it.
4362 adapter->rx_bulk_alloc_allowed = true;
4363 adapter->rx_vec_allowed = true;
4369 ixgbevf_dev_start(struct rte_eth_dev *dev)
4371 struct ixgbe_hw *hw =
4372 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4373 uint32_t intr_vector = 0;
4374 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4375 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4379 PMD_INIT_FUNC_TRACE();
4381 hw->mac.ops.reset_hw(hw);
4382 hw->mac.get_link_status = true;
4384 /* negotiate mailbox API version to use with the PF. */
4385 ixgbevf_negotiate_api(hw);
4387 ixgbevf_dev_tx_init(dev);
4389 /* This can fail when allocating mbufs for descriptor rings */
4390 err = ixgbevf_dev_rx_init(dev);
4392 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4393 ixgbe_dev_clear_queues(dev);
4398 ixgbevf_set_vfta_all(dev, 1);
4401 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4402 ETH_VLAN_EXTEND_MASK;
4403 ixgbevf_vlan_offload_set(dev, mask);
4405 ixgbevf_dev_rxtx_start(dev);
4407 /* check and configure queue intr-vector mapping */
4408 if (dev->data->dev_conf.intr_conf.rxq != 0) {
4409 intr_vector = dev->data->nb_rx_queues;
4410 if (rte_intr_efd_enable(intr_handle, intr_vector))
4414 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4415 intr_handle->intr_vec =
4416 rte_zmalloc("intr_vec",
4417 dev->data->nb_rx_queues * sizeof(int), 0);
4418 if (intr_handle->intr_vec == NULL) {
4419 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4420 " intr_vec\n", dev->data->nb_rx_queues);
4424 ixgbevf_configure_msix(dev);
4426 rte_intr_enable(intr_handle);
4428 /* Re-enable interrupt for VF */
4429 ixgbevf_intr_enable(hw);
4435 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4437 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4438 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4439 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4441 PMD_INIT_FUNC_TRACE();
4443 ixgbevf_intr_disable(hw);
4445 hw->adapter_stopped = 1;
4446 ixgbe_stop_adapter(hw);
4449 * Clear what we set, but we still keep shadow_vfta to
4450 * restore after device starts
4452 ixgbevf_set_vfta_all(dev, 0);
4454 /* Clear stored conf */
4455 dev->data->scattered_rx = 0;
4457 ixgbe_dev_clear_queues(dev);
4459 /* Clean datapath event and queue/vec mapping */
4460 rte_intr_efd_disable(intr_handle);
4461 if (intr_handle->intr_vec != NULL) {
4462 rte_free(intr_handle->intr_vec);
4463 intr_handle->intr_vec = NULL;
4468 ixgbevf_dev_close(struct rte_eth_dev *dev)
4470 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4472 PMD_INIT_FUNC_TRACE();
4476 ixgbevf_dev_stop(dev);
4478 ixgbe_dev_free_queues(dev);
4481 * Remove the VF MAC address ro ensure
4482 * that the VF traffic goes to the PF
4483 * after stop, close and detach of the VF
4485 ixgbevf_remove_mac_addr(dev, 0);
4488 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4490 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4491 struct ixgbe_vfta *shadow_vfta =
4492 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4493 int i = 0, j = 0, vfta = 0, mask = 1;
4495 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4496 vfta = shadow_vfta->vfta[i];
4499 for (j = 0; j < 32; j++) {
4501 ixgbe_set_vfta(hw, (i<<5)+j, 0,
4511 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4513 struct ixgbe_hw *hw =
4514 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4515 struct ixgbe_vfta *shadow_vfta =
4516 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4517 uint32_t vid_idx = 0;
4518 uint32_t vid_bit = 0;
4521 PMD_INIT_FUNC_TRACE();
4523 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4524 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4526 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4529 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4530 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4532 /* Save what we set and retore it after device reset */
4534 shadow_vfta->vfta[vid_idx] |= vid_bit;
4536 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4542 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4544 struct ixgbe_hw *hw =
4545 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4548 PMD_INIT_FUNC_TRACE();
4550 if (queue >= hw->mac.max_rx_queues)
4553 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4555 ctrl |= IXGBE_RXDCTL_VME;
4557 ctrl &= ~IXGBE_RXDCTL_VME;
4558 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4560 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4564 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4566 struct ixgbe_hw *hw =
4567 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4571 /* VF function only support hw strip feature, others are not support */
4572 if (mask & ETH_VLAN_STRIP_MASK) {
4573 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4575 for (i = 0; i < hw->mac.max_rx_queues; i++)
4576 ixgbevf_vlan_strip_queue_set(dev, i, on);
4581 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4585 /* we only need to do this if VMDq is enabled */
4586 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4587 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4588 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4596 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4598 uint32_t vector = 0;
4600 switch (hw->mac.mc_filter_type) {
4601 case 0: /* use bits [47:36] of the address */
4602 vector = ((uc_addr->addr_bytes[4] >> 4) |
4603 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4605 case 1: /* use bits [46:35] of the address */
4606 vector = ((uc_addr->addr_bytes[4] >> 3) |
4607 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4609 case 2: /* use bits [45:34] of the address */
4610 vector = ((uc_addr->addr_bytes[4] >> 2) |
4611 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4613 case 3: /* use bits [43:32] of the address */
4614 vector = ((uc_addr->addr_bytes[4]) |
4615 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4617 default: /* Invalid mc_filter_type */
4621 /* vector can only be 12-bits or boundary will be exceeded */
4627 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4635 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4636 const uint32_t ixgbe_uta_bit_shift = 5;
4637 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4638 const uint32_t bit1 = 0x1;
4640 struct ixgbe_hw *hw =
4641 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4642 struct ixgbe_uta_info *uta_info =
4643 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4645 /* The UTA table only exists on 82599 hardware and newer */
4646 if (hw->mac.type < ixgbe_mac_82599EB)
4649 vector = ixgbe_uta_vector(hw, mac_addr);
4650 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4651 uta_shift = vector & ixgbe_uta_bit_mask;
4653 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4657 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4659 uta_info->uta_in_use++;
4660 reg_val |= (bit1 << uta_shift);
4661 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4663 uta_info->uta_in_use--;
4664 reg_val &= ~(bit1 << uta_shift);
4665 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4668 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4670 if (uta_info->uta_in_use > 0)
4671 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4672 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4674 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4680 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4683 struct ixgbe_hw *hw =
4684 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4685 struct ixgbe_uta_info *uta_info =
4686 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4688 /* The UTA table only exists on 82599 hardware and newer */
4689 if (hw->mac.type < ixgbe_mac_82599EB)
4693 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4694 uta_info->uta_shadow[i] = ~0;
4695 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4698 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4699 uta_info->uta_shadow[i] = 0;
4700 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4708 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4710 uint32_t new_val = orig_val;
4712 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4713 new_val |= IXGBE_VMOLR_AUPE;
4714 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4715 new_val |= IXGBE_VMOLR_ROMPE;
4716 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4717 new_val |= IXGBE_VMOLR_ROPE;
4718 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4719 new_val |= IXGBE_VMOLR_BAM;
4720 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4721 new_val |= IXGBE_VMOLR_MPE;
4728 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4730 struct ixgbe_hw *hw;
4731 struct ixgbe_mac_info *mac;
4732 struct rte_eth_dev *dev;
4733 struct rte_eth_dev_info dev_info;
4735 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4737 dev = &rte_eth_devices[port];
4738 rte_eth_dev_info_get(port, &dev_info);
4740 if (vf >= dev_info.max_vfs)
4746 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4749 mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4755 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4757 struct ixgbe_hw *hw;
4758 struct ixgbe_mac_info *mac;
4759 struct rte_eth_dev *dev;
4760 struct rte_eth_dev_info dev_info;
4762 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4764 dev = &rte_eth_devices[port];
4765 rte_eth_dev_info_get(port, &dev_info);
4767 if (vf >= dev_info.max_vfs)
4773 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4775 mac->ops.set_mac_anti_spoofing(hw, on, vf);
4781 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4783 struct ixgbe_hw *hw;
4785 struct rte_eth_dev *dev;
4786 struct rte_eth_dev_info dev_info;
4788 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4790 dev = &rte_eth_devices[port];
4791 rte_eth_dev_info_get(port, &dev_info);
4793 if (vf >= dev_info.max_vfs)
4799 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4800 ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4803 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4808 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4814 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4816 struct ixgbe_hw *hw;
4818 struct rte_eth_dev *dev;
4820 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4822 dev = &rte_eth_devices[port];
4827 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4828 ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4829 /* enable or disable VMDQ loopback */
4831 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
4833 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4835 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
4841 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
4843 struct ixgbe_hw *hw;
4846 int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
4847 struct rte_eth_dev *dev;
4849 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4851 dev = &rte_eth_devices[port];
4856 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4857 for (i = 0; i <= num_queues; i++) {
4858 reg_value = IXGBE_QDE_WRITE |
4859 (i << IXGBE_QDE_IDX_SHIFT) |
4860 (on & IXGBE_QDE_ENABLE);
4861 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
4868 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
4870 struct ixgbe_hw *hw;
4872 struct rte_eth_dev *dev;
4873 struct rte_eth_dev_info dev_info;
4875 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4877 dev = &rte_eth_devices[port];
4878 rte_eth_dev_info_get(port, &dev_info);
4880 /* only support VF's 0 to 63 */
4881 if ((vf >= dev_info.max_vfs) || (vf > 63))
4887 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4888 reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
4890 reg_value |= IXGBE_SRRCTL_DROP_EN;
4892 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
4894 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
4900 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
4902 struct rte_eth_dev *dev;
4903 struct rte_eth_dev_info dev_info;
4904 uint16_t queues_per_pool;
4907 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4909 dev = &rte_eth_devices[port];
4910 rte_eth_dev_info_get(port, &dev_info);
4912 if (vf >= dev_info.max_vfs)
4918 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
4920 /* The PF has 128 queue pairs and in SRIOV configuration
4921 * those queues will be assigned to VF's, so RXDCTL
4922 * registers will be dealing with queues which will be
4924 * Let's say we have SRIOV configured with 31 VF's then the
4925 * first 124 queues 0-123 will be allocated to VF's and only
4926 * the last 4 queues 123-127 will be assigned to the PF.
4929 queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
4931 for (q = 0; q < queues_per_pool; q++)
4932 (*dev->dev_ops->vlan_strip_queue_set)(dev,
4933 q + vf * queues_per_pool, on);
4938 rte_pmd_ixgbe_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mask, uint8_t on)
4941 struct rte_eth_dev *dev;
4942 struct rte_eth_dev_info dev_info;
4943 struct ixgbe_hw *hw;
4946 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4948 dev = &rte_eth_devices[port];
4949 rte_eth_dev_info_get(port, &dev_info);
4951 if (strstr(dev_info.driver_name, "ixgbe_vf"))
4954 if (vf >= dev_info.max_vfs)
4960 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4961 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
4963 if (hw->mac.type == ixgbe_mac_82598EB) {
4964 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4965 " on 82599 hardware and newer");
4968 if (ixgbe_vmdq_mode_check(hw) < 0)
4971 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4978 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
4984 rte_pmd_ixgbe_set_vf_rx(uint8_t port, uint16_t vf, uint8_t on)
4986 struct rte_eth_dev *dev;
4987 struct rte_eth_dev_info dev_info;
4990 const uint8_t bit1 = 0x1;
4991 struct ixgbe_hw *hw;
4993 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4995 dev = &rte_eth_devices[port];
4996 rte_eth_dev_info_get(port, &dev_info);
4998 if (strstr(dev_info.driver_name, "ixgbe_vf"))
5001 if (vf >= dev_info.max_vfs)
5007 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5009 if (ixgbe_vmdq_mode_check(hw) < 0)
5012 /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
5014 addr = IXGBE_VFRE(1);
5015 val = bit1 << (vf - 32);
5017 addr = IXGBE_VFRE(0);
5021 reg = IXGBE_READ_REG(hw, addr);
5028 IXGBE_WRITE_REG(hw, addr, reg);
5034 rte_pmd_ixgbe_set_vf_tx(uint8_t port, uint16_t vf, uint8_t on)
5036 struct rte_eth_dev *dev;
5037 struct rte_eth_dev_info dev_info;
5040 const uint8_t bit1 = 0x1;
5042 struct ixgbe_hw *hw;
5044 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5046 dev = &rte_eth_devices[port];
5047 rte_eth_dev_info_get(port, &dev_info);
5049 if (strstr(dev_info.driver_name, "ixgbe_vf"))
5052 if (vf >= dev_info.max_vfs)
5058 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5059 if (ixgbe_vmdq_mode_check(hw) < 0)
5062 /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
5064 addr = IXGBE_VFTE(1);
5065 val = bit1 << (vf - 32);
5067 addr = IXGBE_VFTE(0);
5071 reg = IXGBE_READ_REG(hw, addr);
5078 IXGBE_WRITE_REG(hw, addr, reg);
5084 rte_pmd_ixgbe_set_vf_vlan_filter(uint8_t port, uint16_t vlan,
5085 uint64_t vf_mask, uint8_t vlan_on)
5087 struct rte_eth_dev *dev;
5088 struct rte_eth_dev_info dev_info;
5091 struct ixgbe_hw *hw;
5093 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5095 dev = &rte_eth_devices[port];
5096 rte_eth_dev_info_get(port, &dev_info);
5098 if (strstr(dev_info.driver_name, "ixgbe_vf"))
5101 if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
5104 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5105 if (ixgbe_vmdq_mode_check(hw) < 0)
5108 for (vf_idx = 0; vf_idx < 64; vf_idx++) {
5109 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
5110 ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
5120 int rte_pmd_ixgbe_set_vf_rate_limit(uint8_t port, uint16_t vf,
5121 uint16_t tx_rate, uint64_t q_msk)
5123 struct rte_eth_dev *dev;
5124 struct rte_eth_dev_info dev_info;
5125 struct ixgbe_hw *hw;
5126 struct ixgbe_vf_info *vfinfo;
5127 struct rte_eth_link link;
5128 uint8_t nb_q_per_pool;
5129 uint32_t queue_stride;
5130 uint32_t queue_idx, idx = 0, vf_idx;
5132 uint16_t total_rate = 0;
5133 struct rte_pci_device *pci_dev;
5135 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5137 dev = &rte_eth_devices[port];
5138 rte_eth_dev_info_get(port, &dev_info);
5139 rte_eth_link_get_nowait(port, &link);
5141 if (strstr(dev_info.driver_name, "ixgbe_vf"))
5144 if (vf >= dev_info.max_vfs)
5147 if (tx_rate > link.link_speed)
5153 pci_dev = IXGBE_DEV_TO_PCI(dev);
5154 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5155 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5156 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5157 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5158 queue_idx = vf * queue_stride;
5159 queue_end = queue_idx + nb_q_per_pool - 1;
5160 if (queue_end >= hw->mac.max_tx_queues)
5164 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5167 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5169 total_rate += vfinfo[vf_idx].tx_rate[idx];
5175 /* Store tx_rate for this vf. */
5176 for (idx = 0; idx < nb_q_per_pool; idx++) {
5177 if (((uint64_t)0x1 << idx) & q_msk) {
5178 if (vfinfo[vf].tx_rate[idx] != tx_rate)
5179 vfinfo[vf].tx_rate[idx] = tx_rate;
5180 total_rate += tx_rate;
5184 if (total_rate > dev->data->dev_link.link_speed) {
5185 /* Reset stored TX rate of the VF if it causes exceed
5188 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5192 /* Set RTTBCNRC of each queue/pool for vf X */
5193 for (; queue_idx <= queue_end; queue_idx++) {
5195 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5202 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5203 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5204 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5205 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5206 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5207 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5208 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5211 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5212 struct rte_eth_mirror_conf *mirror_conf,
5213 uint8_t rule_id, uint8_t on)
5215 uint32_t mr_ctl, vlvf;
5216 uint32_t mp_lsb = 0;
5217 uint32_t mv_msb = 0;
5218 uint32_t mv_lsb = 0;
5219 uint32_t mp_msb = 0;
5222 uint64_t vlan_mask = 0;
5224 const uint8_t pool_mask_offset = 32;
5225 const uint8_t vlan_mask_offset = 32;
5226 const uint8_t dst_pool_offset = 8;
5227 const uint8_t rule_mr_offset = 4;
5228 const uint8_t mirror_rule_mask = 0x0F;
5230 struct ixgbe_mirror_info *mr_info =
5231 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5232 struct ixgbe_hw *hw =
5233 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5234 uint8_t mirror_type = 0;
5236 if (ixgbe_vmdq_mode_check(hw) < 0)
5239 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5242 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5243 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5244 mirror_conf->rule_type);
5248 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5249 mirror_type |= IXGBE_MRCTL_VLME;
5250 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5251 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5252 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5253 /* search vlan id related pool vlan filter index */
5254 reg_index = ixgbe_find_vlvf_slot(hw,
5255 mirror_conf->vlan.vlan_id[i],
5259 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5260 if ((vlvf & IXGBE_VLVF_VIEN) &&
5261 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5262 mirror_conf->vlan.vlan_id[i]))
5263 vlan_mask |= (1ULL << reg_index);
5270 mv_lsb = vlan_mask & 0xFFFFFFFF;
5271 mv_msb = vlan_mask >> vlan_mask_offset;
5273 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5274 mirror_conf->vlan.vlan_mask;
5275 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5276 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5277 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5278 mirror_conf->vlan.vlan_id[i];
5283 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5284 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5285 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5290 * if enable pool mirror, write related pool mask register,if disable
5291 * pool mirror, clear PFMRVM register
5293 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5294 mirror_type |= IXGBE_MRCTL_VPME;
5296 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5297 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5298 mr_info->mr_conf[rule_id].pool_mask =
5299 mirror_conf->pool_mask;
5304 mr_info->mr_conf[rule_id].pool_mask = 0;
5307 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5308 mirror_type |= IXGBE_MRCTL_UPME;
5309 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5310 mirror_type |= IXGBE_MRCTL_DPME;
5312 /* read mirror control register and recalculate it */
5313 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5316 mr_ctl |= mirror_type;
5317 mr_ctl &= mirror_rule_mask;
5318 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5320 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5322 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5323 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5325 /* write mirrror control register */
5326 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5328 /* write pool mirrror control register */
5329 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5330 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5331 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5334 /* write VLAN mirrror control register */
5335 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5336 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5337 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5345 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5348 uint32_t lsb_val = 0;
5349 uint32_t msb_val = 0;
5350 const uint8_t rule_mr_offset = 4;
5352 struct ixgbe_hw *hw =
5353 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5354 struct ixgbe_mirror_info *mr_info =
5355 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5357 if (ixgbe_vmdq_mode_check(hw) < 0)
5360 memset(&mr_info->mr_conf[rule_id], 0,
5361 sizeof(struct rte_eth_mirror_conf));
5363 /* clear PFVMCTL register */
5364 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5366 /* clear pool mask register */
5367 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5368 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5370 /* clear vlan mask register */
5371 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5372 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5378 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5380 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5381 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5383 struct ixgbe_hw *hw =
5384 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5386 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5387 mask |= (1 << IXGBE_MISC_VEC_ID);
5388 RTE_SET_USED(queue_id);
5389 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5391 rte_intr_enable(intr_handle);
5397 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5400 struct ixgbe_hw *hw =
5401 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5403 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5404 mask &= ~(1 << IXGBE_MISC_VEC_ID);
5405 RTE_SET_USED(queue_id);
5406 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5412 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5414 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5415 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5417 struct ixgbe_hw *hw =
5418 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5419 struct ixgbe_interrupt *intr =
5420 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5422 if (queue_id < 16) {
5423 ixgbe_disable_intr(hw);
5424 intr->mask |= (1 << queue_id);
5425 ixgbe_enable_intr(dev);
5426 } else if (queue_id < 32) {
5427 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5428 mask &= (1 << queue_id);
5429 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5430 } else if (queue_id < 64) {
5431 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5432 mask &= (1 << (queue_id - 32));
5433 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5435 rte_intr_enable(intr_handle);
5441 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5444 struct ixgbe_hw *hw =
5445 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5446 struct ixgbe_interrupt *intr =
5447 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5449 if (queue_id < 16) {
5450 ixgbe_disable_intr(hw);
5451 intr->mask &= ~(1 << queue_id);
5452 ixgbe_enable_intr(dev);
5453 } else if (queue_id < 32) {
5454 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5455 mask &= ~(1 << queue_id);
5456 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5457 } else if (queue_id < 64) {
5458 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5459 mask &= ~(1 << (queue_id - 32));
5460 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5467 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5468 uint8_t queue, uint8_t msix_vector)
5472 if (direction == -1) {
5474 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5475 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5478 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5480 /* rx or tx cause */
5481 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5482 idx = ((16 * (queue & 1)) + (8 * direction));
5483 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5484 tmp &= ~(0xFF << idx);
5485 tmp |= (msix_vector << idx);
5486 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5491 * set the IVAR registers, mapping interrupt causes to vectors
5493 * pointer to ixgbe_hw struct
5495 * 0 for Rx, 1 for Tx, -1 for other causes
5497 * queue to map the corresponding interrupt to
5499 * the vector to map to the corresponding queue
5502 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5503 uint8_t queue, uint8_t msix_vector)
5507 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5508 if (hw->mac.type == ixgbe_mac_82598EB) {
5509 if (direction == -1)
5511 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5512 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5513 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5514 tmp |= (msix_vector << (8 * (queue & 0x3)));
5515 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5516 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5517 (hw->mac.type == ixgbe_mac_X540)) {
5518 if (direction == -1) {
5520 idx = ((queue & 1) * 8);
5521 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5522 tmp &= ~(0xFF << idx);
5523 tmp |= (msix_vector << idx);
5524 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5526 /* rx or tx causes */
5527 idx = ((16 * (queue & 1)) + (8 * direction));
5528 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5529 tmp &= ~(0xFF << idx);
5530 tmp |= (msix_vector << idx);
5531 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5537 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5539 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5540 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5541 struct ixgbe_hw *hw =
5542 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5544 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5546 /* Configure VF other cause ivar */
5547 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5549 /* won't configure msix register if no mapping is done
5550 * between intr vector and event fd.
5552 if (!rte_intr_dp_is_en(intr_handle))
5555 /* Configure all RX queues of VF */
5556 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5557 /* Force all queue use vector 0,
5558 * as IXGBE_VF_MAXMSIVECOTR = 1
5560 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5561 intr_handle->intr_vec[q_idx] = vector_idx;
5566 * Sets up the hardware to properly generate MSI-X interrupts
5568 * board private structure
5571 ixgbe_configure_msix(struct rte_eth_dev *dev)
5573 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5574 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5575 struct ixgbe_hw *hw =
5576 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5577 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5578 uint32_t vec = IXGBE_MISC_VEC_ID;
5582 /* won't configure msix register if no mapping is done
5583 * between intr vector and event fd
5585 if (!rte_intr_dp_is_en(intr_handle))
5588 if (rte_intr_allow_others(intr_handle))
5589 vec = base = IXGBE_RX_VEC_START;
5591 /* setup GPIE for MSI-x mode */
5592 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5593 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5594 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5595 /* auto clearing and auto setting corresponding bits in EIMS
5596 * when MSI-X interrupt is triggered
5598 if (hw->mac.type == ixgbe_mac_82598EB) {
5599 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5601 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5602 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5604 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5606 /* Populate the IVAR table and set the ITR values to the
5607 * corresponding register.
5609 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5611 /* by default, 1:1 mapping */
5612 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5613 intr_handle->intr_vec[queue_id] = vec;
5614 if (vec < base + intr_handle->nb_efd - 1)
5618 switch (hw->mac.type) {
5619 case ixgbe_mac_82598EB:
5620 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5623 case ixgbe_mac_82599EB:
5624 case ixgbe_mac_X540:
5625 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5630 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5631 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5633 /* set up to autoclear timer, and the vectors */
5634 mask = IXGBE_EIMS_ENABLE_MASK;
5635 mask &= ~(IXGBE_EIMS_OTHER |
5636 IXGBE_EIMS_MAILBOX |
5639 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5642 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5643 uint16_t queue_idx, uint16_t tx_rate)
5645 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5646 uint32_t rf_dec, rf_int;
5648 uint16_t link_speed = dev->data->dev_link.link_speed;
5650 if (queue_idx >= hw->mac.max_tx_queues)
5654 /* Calculate the rate factor values to set */
5655 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5656 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5657 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5659 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5660 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5661 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5662 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5668 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5669 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5672 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5673 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5674 IXGBE_MAX_JUMBO_FRAME_SIZE))
5675 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5676 IXGBE_MMW_SIZE_JUMBO_FRAME);
5678 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5679 IXGBE_MMW_SIZE_DEFAULT);
5681 /* Set RTTBCNRC of queue X */
5682 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5683 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5684 IXGBE_WRITE_FLUSH(hw);
5690 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5691 __attribute__((unused)) uint32_t index,
5692 __attribute__((unused)) uint32_t pool)
5694 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5698 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5699 * operation. Trap this case to avoid exhausting the [very limited]
5700 * set of PF resources used to store VF MAC addresses.
5702 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5704 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5707 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5711 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5713 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5714 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5715 struct ether_addr *mac_addr;
5720 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5721 * not support the deletion of a given MAC address.
5722 * Instead, it imposes to delete all MAC addresses, then to add again
5723 * all MAC addresses with the exception of the one to be deleted.
5725 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5728 * Add again all MAC addresses, with the exception of the deleted one
5729 * and of the permanent MAC address.
5731 for (i = 0, mac_addr = dev->data->mac_addrs;
5732 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5733 /* Skip the deleted MAC address */
5736 /* Skip NULL MAC addresses */
5737 if (is_zero_ether_addr(mac_addr))
5739 /* Skip the permanent MAC address */
5740 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5742 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5745 "Adding again MAC address "
5746 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5748 mac_addr->addr_bytes[0],
5749 mac_addr->addr_bytes[1],
5750 mac_addr->addr_bytes[2],
5751 mac_addr->addr_bytes[3],
5752 mac_addr->addr_bytes[4],
5753 mac_addr->addr_bytes[5],
5759 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5761 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5763 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5766 #define MAC_TYPE_FILTER_SUP(type) do {\
5767 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5768 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5769 (type) != ixgbe_mac_X550EM_a)\
5774 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5775 struct rte_eth_syn_filter *filter,
5778 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5781 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5784 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5787 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5789 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5790 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5792 if (filter->hig_pri)
5793 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5795 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5797 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5799 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5801 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5802 IXGBE_WRITE_FLUSH(hw);
5807 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5808 struct rte_eth_syn_filter *filter)
5810 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5811 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5813 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5814 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5815 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5822 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5823 enum rte_filter_op filter_op,
5826 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5829 MAC_TYPE_FILTER_SUP(hw->mac.type);
5831 if (filter_op == RTE_ETH_FILTER_NOP)
5835 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5840 switch (filter_op) {
5841 case RTE_ETH_FILTER_ADD:
5842 ret = ixgbe_syn_filter_set(dev,
5843 (struct rte_eth_syn_filter *)arg,
5846 case RTE_ETH_FILTER_DELETE:
5847 ret = ixgbe_syn_filter_set(dev,
5848 (struct rte_eth_syn_filter *)arg,
5851 case RTE_ETH_FILTER_GET:
5852 ret = ixgbe_syn_filter_get(dev,
5853 (struct rte_eth_syn_filter *)arg);
5856 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5865 static inline enum ixgbe_5tuple_protocol
5866 convert_protocol_type(uint8_t protocol_value)
5868 if (protocol_value == IPPROTO_TCP)
5869 return IXGBE_FILTER_PROTOCOL_TCP;
5870 else if (protocol_value == IPPROTO_UDP)
5871 return IXGBE_FILTER_PROTOCOL_UDP;
5872 else if (protocol_value == IPPROTO_SCTP)
5873 return IXGBE_FILTER_PROTOCOL_SCTP;
5875 return IXGBE_FILTER_PROTOCOL_NONE;
5879 * add a 5tuple filter
5882 * dev: Pointer to struct rte_eth_dev.
5883 * index: the index the filter allocates.
5884 * filter: ponter to the filter that will be added.
5885 * rx_queue: the queue id the filter assigned to.
5888 * - On success, zero.
5889 * - On failure, a negative value.
5892 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5893 struct ixgbe_5tuple_filter *filter)
5895 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5896 struct ixgbe_filter_info *filter_info =
5897 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5899 uint32_t ftqf, sdpqf;
5900 uint32_t l34timir = 0;
5901 uint8_t mask = 0xff;
5904 * look for an unused 5tuple filter index,
5905 * and insert the filter to list.
5907 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5908 idx = i / (sizeof(uint32_t) * NBBY);
5909 shift = i % (sizeof(uint32_t) * NBBY);
5910 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5911 filter_info->fivetuple_mask[idx] |= 1 << shift;
5913 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5919 if (i >= IXGBE_MAX_FTQF_FILTERS) {
5920 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5924 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5925 IXGBE_SDPQF_DSTPORT_SHIFT);
5926 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5928 ftqf = (uint32_t)(filter->filter_info.proto &
5929 IXGBE_FTQF_PROTOCOL_MASK);
5930 ftqf |= (uint32_t)((filter->filter_info.priority &
5931 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5932 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5933 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5934 if (filter->filter_info.dst_ip_mask == 0)
5935 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5936 if (filter->filter_info.src_port_mask == 0)
5937 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5938 if (filter->filter_info.dst_port_mask == 0)
5939 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5940 if (filter->filter_info.proto_mask == 0)
5941 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5942 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5943 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5944 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5946 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5947 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5948 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5949 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5951 l34timir |= IXGBE_L34T_IMIR_RESERVE;
5952 l34timir |= (uint32_t)(filter->queue <<
5953 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5954 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5959 * remove a 5tuple filter
5962 * dev: Pointer to struct rte_eth_dev.
5963 * filter: the pointer of the filter will be removed.
5966 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5967 struct ixgbe_5tuple_filter *filter)
5969 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5970 struct ixgbe_filter_info *filter_info =
5971 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5972 uint16_t index = filter->index;
5974 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5975 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5976 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5979 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5980 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5981 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5982 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5983 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5987 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5989 struct ixgbe_hw *hw;
5990 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5992 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5994 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5997 /* refuse mtu that requires the support of scattered packets when this
5998 * feature has not been enabled before.
6000 if (!dev->data->scattered_rx &&
6001 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6002 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6006 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6007 * request of the version 2.0 of the mailbox API.
6008 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6009 * of the mailbox API.
6010 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6011 * prior to 3.11.33 which contains the following change:
6012 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6014 ixgbevf_rlpml_set_vf(hw, max_frame);
6016 /* update max frame size */
6017 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6021 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
6022 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
6026 static inline struct ixgbe_5tuple_filter *
6027 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6028 struct ixgbe_5tuple_filter_info *key)
6030 struct ixgbe_5tuple_filter *it;
6032 TAILQ_FOREACH(it, filter_list, entries) {
6033 if (memcmp(key, &it->filter_info,
6034 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6041 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6043 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6044 struct ixgbe_5tuple_filter_info *filter_info)
6046 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6047 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6048 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6051 switch (filter->dst_ip_mask) {
6053 filter_info->dst_ip_mask = 0;
6054 filter_info->dst_ip = filter->dst_ip;
6057 filter_info->dst_ip_mask = 1;
6060 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6064 switch (filter->src_ip_mask) {
6066 filter_info->src_ip_mask = 0;
6067 filter_info->src_ip = filter->src_ip;
6070 filter_info->src_ip_mask = 1;
6073 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6077 switch (filter->dst_port_mask) {
6079 filter_info->dst_port_mask = 0;
6080 filter_info->dst_port = filter->dst_port;
6083 filter_info->dst_port_mask = 1;
6086 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6090 switch (filter->src_port_mask) {
6092 filter_info->src_port_mask = 0;
6093 filter_info->src_port = filter->src_port;
6096 filter_info->src_port_mask = 1;
6099 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6103 switch (filter->proto_mask) {
6105 filter_info->proto_mask = 0;
6106 filter_info->proto =
6107 convert_protocol_type(filter->proto);
6110 filter_info->proto_mask = 1;
6113 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6117 filter_info->priority = (uint8_t)filter->priority;
6122 * add or delete a ntuple filter
6125 * dev: Pointer to struct rte_eth_dev.
6126 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6127 * add: if true, add filter, if false, remove filter
6130 * - On success, zero.
6131 * - On failure, a negative value.
6134 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6135 struct rte_eth_ntuple_filter *ntuple_filter,
6138 struct ixgbe_filter_info *filter_info =
6139 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6140 struct ixgbe_5tuple_filter_info filter_5tuple;
6141 struct ixgbe_5tuple_filter *filter;
6144 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6145 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6149 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6150 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6154 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6156 if (filter != NULL && add) {
6157 PMD_DRV_LOG(ERR, "filter exists.");
6160 if (filter == NULL && !add) {
6161 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6166 filter = rte_zmalloc("ixgbe_5tuple_filter",
6167 sizeof(struct ixgbe_5tuple_filter), 0);
6170 (void)rte_memcpy(&filter->filter_info,
6172 sizeof(struct ixgbe_5tuple_filter_info));
6173 filter->queue = ntuple_filter->queue;
6174 ret = ixgbe_add_5tuple_filter(dev, filter);
6180 ixgbe_remove_5tuple_filter(dev, filter);
6186 * get a ntuple filter
6189 * dev: Pointer to struct rte_eth_dev.
6190 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6193 * - On success, zero.
6194 * - On failure, a negative value.
6197 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6198 struct rte_eth_ntuple_filter *ntuple_filter)
6200 struct ixgbe_filter_info *filter_info =
6201 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6202 struct ixgbe_5tuple_filter_info filter_5tuple;
6203 struct ixgbe_5tuple_filter *filter;
6206 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6207 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6211 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6212 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6216 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6218 if (filter == NULL) {
6219 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6222 ntuple_filter->queue = filter->queue;
6227 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6228 * @dev: pointer to rte_eth_dev structure
6229 * @filter_op:operation will be taken.
6230 * @arg: a pointer to specific structure corresponding to the filter_op
6233 * - On success, zero.
6234 * - On failure, a negative value.
6237 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6238 enum rte_filter_op filter_op,
6241 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6244 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6246 if (filter_op == RTE_ETH_FILTER_NOP)
6250 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6255 switch (filter_op) {
6256 case RTE_ETH_FILTER_ADD:
6257 ret = ixgbe_add_del_ntuple_filter(dev,
6258 (struct rte_eth_ntuple_filter *)arg,
6261 case RTE_ETH_FILTER_DELETE:
6262 ret = ixgbe_add_del_ntuple_filter(dev,
6263 (struct rte_eth_ntuple_filter *)arg,
6266 case RTE_ETH_FILTER_GET:
6267 ret = ixgbe_get_ntuple_filter(dev,
6268 (struct rte_eth_ntuple_filter *)arg);
6271 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6279 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
6284 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6285 if (filter_info->ethertype_filters[i] == ethertype &&
6286 (filter_info->ethertype_mask & (1 << i)))
6293 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
6298 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6299 if (!(filter_info->ethertype_mask & (1 << i))) {
6300 filter_info->ethertype_mask |= 1 << i;
6301 filter_info->ethertype_filters[i] = ethertype;
6309 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
6312 if (idx >= IXGBE_MAX_ETQF_FILTERS)
6314 filter_info->ethertype_mask &= ~(1 << idx);
6315 filter_info->ethertype_filters[idx] = 0;
6320 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6321 struct rte_eth_ethertype_filter *filter,
6324 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6325 struct ixgbe_filter_info *filter_info =
6326 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6331 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6334 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6335 filter->ether_type == ETHER_TYPE_IPv6) {
6336 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6337 " ethertype filter.", filter->ether_type);
6341 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6342 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6345 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6346 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6350 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6351 if (ret >= 0 && add) {
6352 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6353 filter->ether_type);
6356 if (ret < 0 && !add) {
6357 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6358 filter->ether_type);
6363 ret = ixgbe_ethertype_filter_insert(filter_info,
6364 filter->ether_type);
6366 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6369 etqf = IXGBE_ETQF_FILTER_EN;
6370 etqf |= (uint32_t)filter->ether_type;
6371 etqs |= (uint32_t)((filter->queue <<
6372 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6373 IXGBE_ETQS_RX_QUEUE);
6374 etqs |= IXGBE_ETQS_QUEUE_EN;
6376 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6380 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6381 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6382 IXGBE_WRITE_FLUSH(hw);
6388 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6389 struct rte_eth_ethertype_filter *filter)
6391 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6392 struct ixgbe_filter_info *filter_info =
6393 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6394 uint32_t etqf, etqs;
6397 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6399 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6400 filter->ether_type);
6404 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6405 if (etqf & IXGBE_ETQF_FILTER_EN) {
6406 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6407 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6409 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6410 IXGBE_ETQS_RX_QUEUE_SHIFT;
6417 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6418 * @dev: pointer to rte_eth_dev structure
6419 * @filter_op:operation will be taken.
6420 * @arg: a pointer to specific structure corresponding to the filter_op
6423 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6424 enum rte_filter_op filter_op,
6427 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6430 MAC_TYPE_FILTER_SUP(hw->mac.type);
6432 if (filter_op == RTE_ETH_FILTER_NOP)
6436 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6441 switch (filter_op) {
6442 case RTE_ETH_FILTER_ADD:
6443 ret = ixgbe_add_del_ethertype_filter(dev,
6444 (struct rte_eth_ethertype_filter *)arg,
6447 case RTE_ETH_FILTER_DELETE:
6448 ret = ixgbe_add_del_ethertype_filter(dev,
6449 (struct rte_eth_ethertype_filter *)arg,
6452 case RTE_ETH_FILTER_GET:
6453 ret = ixgbe_get_ethertype_filter(dev,
6454 (struct rte_eth_ethertype_filter *)arg);
6457 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6465 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6466 enum rte_filter_type filter_type,
6467 enum rte_filter_op filter_op,
6472 switch (filter_type) {
6473 case RTE_ETH_FILTER_NTUPLE:
6474 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6476 case RTE_ETH_FILTER_ETHERTYPE:
6477 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6479 case RTE_ETH_FILTER_SYN:
6480 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6482 case RTE_ETH_FILTER_FDIR:
6483 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6485 case RTE_ETH_FILTER_L2_TUNNEL:
6486 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6489 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6498 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6499 u8 **mc_addr_ptr, u32 *vmdq)
6504 mc_addr = *mc_addr_ptr;
6505 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6510 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6511 struct ether_addr *mc_addr_set,
6512 uint32_t nb_mc_addr)
6514 struct ixgbe_hw *hw;
6517 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6518 mc_addr_list = (u8 *)mc_addr_set;
6519 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6520 ixgbe_dev_addr_list_itr, TRUE);
6524 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6526 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6527 uint64_t systime_cycles;
6529 switch (hw->mac.type) {
6530 case ixgbe_mac_X550:
6531 case ixgbe_mac_X550EM_x:
6532 case ixgbe_mac_X550EM_a:
6533 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6534 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6535 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6539 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6540 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6544 return systime_cycles;
6548 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6550 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6551 uint64_t rx_tstamp_cycles;
6553 switch (hw->mac.type) {
6554 case ixgbe_mac_X550:
6555 case ixgbe_mac_X550EM_x:
6556 case ixgbe_mac_X550EM_a:
6557 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6558 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6559 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6563 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6564 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6565 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6569 return rx_tstamp_cycles;
6573 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6575 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6576 uint64_t tx_tstamp_cycles;
6578 switch (hw->mac.type) {
6579 case ixgbe_mac_X550:
6580 case ixgbe_mac_X550EM_x:
6581 case ixgbe_mac_X550EM_a:
6582 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6583 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6584 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6588 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6589 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6590 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6594 return tx_tstamp_cycles;
6598 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6600 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6601 struct ixgbe_adapter *adapter =
6602 (struct ixgbe_adapter *)dev->data->dev_private;
6603 struct rte_eth_link link;
6604 uint32_t incval = 0;
6607 /* Get current link speed. */
6608 memset(&link, 0, sizeof(link));
6609 ixgbe_dev_link_update(dev, 1);
6610 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6612 switch (link.link_speed) {
6613 case ETH_SPEED_NUM_100M:
6614 incval = IXGBE_INCVAL_100;
6615 shift = IXGBE_INCVAL_SHIFT_100;
6617 case ETH_SPEED_NUM_1G:
6618 incval = IXGBE_INCVAL_1GB;
6619 shift = IXGBE_INCVAL_SHIFT_1GB;
6621 case ETH_SPEED_NUM_10G:
6623 incval = IXGBE_INCVAL_10GB;
6624 shift = IXGBE_INCVAL_SHIFT_10GB;
6628 switch (hw->mac.type) {
6629 case ixgbe_mac_X550:
6630 case ixgbe_mac_X550EM_x:
6631 case ixgbe_mac_X550EM_a:
6632 /* Independent of link speed. */
6634 /* Cycles read will be interpreted as ns. */
6637 case ixgbe_mac_X540:
6638 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6640 case ixgbe_mac_82599EB:
6641 incval >>= IXGBE_INCVAL_SHIFT_82599;
6642 shift -= IXGBE_INCVAL_SHIFT_82599;
6643 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6644 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6647 /* Not supported. */
6651 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6652 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6653 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6655 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6656 adapter->systime_tc.cc_shift = shift;
6657 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6659 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6660 adapter->rx_tstamp_tc.cc_shift = shift;
6661 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6663 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6664 adapter->tx_tstamp_tc.cc_shift = shift;
6665 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6669 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6671 struct ixgbe_adapter *adapter =
6672 (struct ixgbe_adapter *)dev->data->dev_private;
6674 adapter->systime_tc.nsec += delta;
6675 adapter->rx_tstamp_tc.nsec += delta;
6676 adapter->tx_tstamp_tc.nsec += delta;
6682 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6685 struct ixgbe_adapter *adapter =
6686 (struct ixgbe_adapter *)dev->data->dev_private;
6688 ns = rte_timespec_to_ns(ts);
6689 /* Set the timecounters to a new value. */
6690 adapter->systime_tc.nsec = ns;
6691 adapter->rx_tstamp_tc.nsec = ns;
6692 adapter->tx_tstamp_tc.nsec = ns;
6698 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6700 uint64_t ns, systime_cycles;
6701 struct ixgbe_adapter *adapter =
6702 (struct ixgbe_adapter *)dev->data->dev_private;
6704 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6705 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6706 *ts = rte_ns_to_timespec(ns);
6712 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6714 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6718 /* Stop the timesync system time. */
6719 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6720 /* Reset the timesync system time value. */
6721 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6722 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6724 /* Enable system time for platforms where it isn't on by default. */
6725 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6726 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6727 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6729 ixgbe_start_timecounters(dev);
6731 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6732 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6734 IXGBE_ETQF_FILTER_EN |
6737 /* Enable timestamping of received PTP packets. */
6738 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6739 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6740 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6742 /* Enable timestamping of transmitted PTP packets. */
6743 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6744 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6745 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6747 IXGBE_WRITE_FLUSH(hw);
6753 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6755 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6758 /* Disable timestamping of transmitted PTP packets. */
6759 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6760 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6761 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6763 /* Disable timestamping of received PTP packets. */
6764 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6765 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6766 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6768 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6769 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6771 /* Stop incrementating the System Time registers. */
6772 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6778 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6779 struct timespec *timestamp,
6780 uint32_t flags __rte_unused)
6782 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6783 struct ixgbe_adapter *adapter =
6784 (struct ixgbe_adapter *)dev->data->dev_private;
6785 uint32_t tsync_rxctl;
6786 uint64_t rx_tstamp_cycles;
6789 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6790 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6793 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6794 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6795 *timestamp = rte_ns_to_timespec(ns);
6801 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6802 struct timespec *timestamp)
6804 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6805 struct ixgbe_adapter *adapter =
6806 (struct ixgbe_adapter *)dev->data->dev_private;
6807 uint32_t tsync_txctl;
6808 uint64_t tx_tstamp_cycles;
6811 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6812 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6815 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6816 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6817 *timestamp = rte_ns_to_timespec(ns);
6823 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6825 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6828 const struct reg_info *reg_group;
6829 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6830 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6832 while ((reg_group = reg_set[g_ind++]))
6833 count += ixgbe_regs_group_count(reg_group);
6839 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6843 const struct reg_info *reg_group;
6845 while ((reg_group = ixgbevf_regs[g_ind++]))
6846 count += ixgbe_regs_group_count(reg_group);
6852 ixgbe_get_regs(struct rte_eth_dev *dev,
6853 struct rte_dev_reg_info *regs)
6855 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6856 uint32_t *data = regs->data;
6859 const struct reg_info *reg_group;
6860 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6861 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6864 regs->length = ixgbe_get_reg_length(dev);
6865 regs->width = sizeof(uint32_t);
6869 /* Support only full register dump */
6870 if ((regs->length == 0) ||
6871 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6872 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6874 while ((reg_group = reg_set[g_ind++]))
6875 count += ixgbe_read_regs_group(dev, &data[count],
6884 ixgbevf_get_regs(struct rte_eth_dev *dev,
6885 struct rte_dev_reg_info *regs)
6887 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6888 uint32_t *data = regs->data;
6891 const struct reg_info *reg_group;
6894 regs->length = ixgbevf_get_reg_length(dev);
6895 regs->width = sizeof(uint32_t);
6899 /* Support only full register dump */
6900 if ((regs->length == 0) ||
6901 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6902 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6904 while ((reg_group = ixgbevf_regs[g_ind++]))
6905 count += ixgbe_read_regs_group(dev, &data[count],
6914 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6916 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6918 /* Return unit is byte count */
6919 return hw->eeprom.word_size * 2;
6923 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6924 struct rte_dev_eeprom_info *in_eeprom)
6926 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6927 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6928 uint16_t *data = in_eeprom->data;
6931 first = in_eeprom->offset >> 1;
6932 length = in_eeprom->length >> 1;
6933 if ((first > hw->eeprom.word_size) ||
6934 ((first + length) > hw->eeprom.word_size))
6937 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6939 return eeprom->ops.read_buffer(hw, first, length, data);
6943 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6944 struct rte_dev_eeprom_info *in_eeprom)
6946 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6947 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6948 uint16_t *data = in_eeprom->data;
6951 first = in_eeprom->offset >> 1;
6952 length = in_eeprom->length >> 1;
6953 if ((first > hw->eeprom.word_size) ||
6954 ((first + length) > hw->eeprom.word_size))
6957 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6959 return eeprom->ops.write_buffer(hw, first, length, data);
6963 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6965 case ixgbe_mac_X550:
6966 case ixgbe_mac_X550EM_x:
6967 case ixgbe_mac_X550EM_a:
6968 return ETH_RSS_RETA_SIZE_512;
6969 case ixgbe_mac_X550_vf:
6970 case ixgbe_mac_X550EM_x_vf:
6971 case ixgbe_mac_X550EM_a_vf:
6972 return ETH_RSS_RETA_SIZE_64;
6974 return ETH_RSS_RETA_SIZE_128;
6979 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6981 case ixgbe_mac_X550:
6982 case ixgbe_mac_X550EM_x:
6983 case ixgbe_mac_X550EM_a:
6984 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6985 return IXGBE_RETA(reta_idx >> 2);
6987 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6988 case ixgbe_mac_X550_vf:
6989 case ixgbe_mac_X550EM_x_vf:
6990 case ixgbe_mac_X550EM_a_vf:
6991 return IXGBE_VFRETA(reta_idx >> 2);
6993 return IXGBE_RETA(reta_idx >> 2);
6998 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7000 case ixgbe_mac_X550_vf:
7001 case ixgbe_mac_X550EM_x_vf:
7002 case ixgbe_mac_X550EM_a_vf:
7003 return IXGBE_VFMRQC;
7010 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7012 case ixgbe_mac_X550_vf:
7013 case ixgbe_mac_X550EM_x_vf:
7014 case ixgbe_mac_X550EM_a_vf:
7015 return IXGBE_VFRSSRK(i);
7017 return IXGBE_RSSRK(i);
7022 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7024 case ixgbe_mac_82599_vf:
7025 case ixgbe_mac_X540_vf:
7033 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7034 struct rte_eth_dcb_info *dcb_info)
7036 struct ixgbe_dcb_config *dcb_config =
7037 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7038 struct ixgbe_dcb_tc_config *tc;
7041 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7042 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7044 dcb_info->nb_tcs = 1;
7046 if (dcb_config->vt_mode) { /* vt is enabled*/
7047 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7048 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7049 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7050 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7051 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7052 for (j = 0; j < dcb_info->nb_tcs; j++) {
7053 dcb_info->tc_queue.tc_rxq[i][j].base =
7054 i * dcb_info->nb_tcs + j;
7055 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7056 dcb_info->tc_queue.tc_txq[i][j].base =
7057 i * dcb_info->nb_tcs + j;
7058 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7061 } else { /* vt is disabled*/
7062 struct rte_eth_dcb_rx_conf *rx_conf =
7063 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7064 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7065 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7066 if (dcb_info->nb_tcs == ETH_4_TCS) {
7067 for (i = 0; i < dcb_info->nb_tcs; i++) {
7068 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7069 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7071 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7072 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7073 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7074 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7075 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7076 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7077 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7078 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7079 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7080 for (i = 0; i < dcb_info->nb_tcs; i++) {
7081 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7082 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7084 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7085 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7086 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7087 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7088 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7089 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7090 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7091 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7092 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7093 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7094 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7095 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7096 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7097 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7098 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7099 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7102 for (i = 0; i < dcb_info->nb_tcs; i++) {
7103 tc = &dcb_config->tc_config[i];
7104 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7109 /* Update e-tag ether type */
7111 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7112 uint16_t ether_type)
7114 uint32_t etag_etype;
7116 if (hw->mac.type != ixgbe_mac_X550 &&
7117 hw->mac.type != ixgbe_mac_X550EM_x &&
7118 hw->mac.type != ixgbe_mac_X550EM_a) {
7122 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7123 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7124 etag_etype |= ether_type;
7125 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7126 IXGBE_WRITE_FLUSH(hw);
7131 /* Config l2 tunnel ether type */
7133 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7134 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7137 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7139 if (l2_tunnel == NULL)
7142 switch (l2_tunnel->l2_tunnel_type) {
7143 case RTE_L2_TUNNEL_TYPE_E_TAG:
7144 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7147 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7155 /* Enable e-tag tunnel */
7157 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7159 uint32_t etag_etype;
7161 if (hw->mac.type != ixgbe_mac_X550 &&
7162 hw->mac.type != ixgbe_mac_X550EM_x &&
7163 hw->mac.type != ixgbe_mac_X550EM_a) {
7167 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7168 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7169 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7170 IXGBE_WRITE_FLUSH(hw);
7175 /* Enable l2 tunnel */
7177 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7178 enum rte_eth_tunnel_type l2_tunnel_type)
7181 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7183 switch (l2_tunnel_type) {
7184 case RTE_L2_TUNNEL_TYPE_E_TAG:
7185 ret = ixgbe_e_tag_enable(hw);
7188 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7196 /* Disable e-tag tunnel */
7198 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7200 uint32_t etag_etype;
7202 if (hw->mac.type != ixgbe_mac_X550 &&
7203 hw->mac.type != ixgbe_mac_X550EM_x &&
7204 hw->mac.type != ixgbe_mac_X550EM_a) {
7208 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7209 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7210 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7211 IXGBE_WRITE_FLUSH(hw);
7216 /* Disable l2 tunnel */
7218 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7219 enum rte_eth_tunnel_type l2_tunnel_type)
7222 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7224 switch (l2_tunnel_type) {
7225 case RTE_L2_TUNNEL_TYPE_E_TAG:
7226 ret = ixgbe_e_tag_disable(hw);
7229 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7238 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7239 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7242 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7243 uint32_t i, rar_entries;
7244 uint32_t rar_low, rar_high;
7246 if (hw->mac.type != ixgbe_mac_X550 &&
7247 hw->mac.type != ixgbe_mac_X550EM_x &&
7248 hw->mac.type != ixgbe_mac_X550EM_a) {
7252 rar_entries = ixgbe_get_num_rx_addrs(hw);
7254 for (i = 1; i < rar_entries; i++) {
7255 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7256 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7257 if ((rar_high & IXGBE_RAH_AV) &&
7258 (rar_high & IXGBE_RAH_ADTYPE) &&
7259 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7260 l2_tunnel->tunnel_id)) {
7261 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7262 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7264 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7274 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7275 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7278 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7279 uint32_t i, rar_entries;
7280 uint32_t rar_low, rar_high;
7282 if (hw->mac.type != ixgbe_mac_X550 &&
7283 hw->mac.type != ixgbe_mac_X550EM_x &&
7284 hw->mac.type != ixgbe_mac_X550EM_a) {
7288 /* One entry for one tunnel. Try to remove potential existing entry. */
7289 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7291 rar_entries = ixgbe_get_num_rx_addrs(hw);
7293 for (i = 1; i < rar_entries; i++) {
7294 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7295 if (rar_high & IXGBE_RAH_AV) {
7298 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7299 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7300 rar_low = l2_tunnel->tunnel_id;
7302 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7303 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7309 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7310 " Please remove a rule before adding a new one.");
7314 /* Add l2 tunnel filter */
7316 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7317 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7321 switch (l2_tunnel->l2_tunnel_type) {
7322 case RTE_L2_TUNNEL_TYPE_E_TAG:
7323 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7326 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7334 /* Delete l2 tunnel filter */
7336 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7337 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7341 switch (l2_tunnel->l2_tunnel_type) {
7342 case RTE_L2_TUNNEL_TYPE_E_TAG:
7343 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7346 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7355 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7356 * @dev: pointer to rte_eth_dev structure
7357 * @filter_op:operation will be taken.
7358 * @arg: a pointer to specific structure corresponding to the filter_op
7361 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7362 enum rte_filter_op filter_op,
7367 if (filter_op == RTE_ETH_FILTER_NOP)
7371 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7376 switch (filter_op) {
7377 case RTE_ETH_FILTER_ADD:
7378 ret = ixgbe_dev_l2_tunnel_filter_add
7380 (struct rte_eth_l2_tunnel_conf *)arg);
7382 case RTE_ETH_FILTER_DELETE:
7383 ret = ixgbe_dev_l2_tunnel_filter_del
7385 (struct rte_eth_l2_tunnel_conf *)arg);
7388 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7396 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7400 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7402 if (hw->mac.type != ixgbe_mac_X550 &&
7403 hw->mac.type != ixgbe_mac_X550EM_x &&
7404 hw->mac.type != ixgbe_mac_X550EM_a) {
7408 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7409 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7411 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7412 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7417 /* Enable l2 tunnel forwarding */
7419 ixgbe_dev_l2_tunnel_forwarding_enable
7420 (struct rte_eth_dev *dev,
7421 enum rte_eth_tunnel_type l2_tunnel_type)
7425 switch (l2_tunnel_type) {
7426 case RTE_L2_TUNNEL_TYPE_E_TAG:
7427 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7430 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7438 /* Disable l2 tunnel forwarding */
7440 ixgbe_dev_l2_tunnel_forwarding_disable
7441 (struct rte_eth_dev *dev,
7442 enum rte_eth_tunnel_type l2_tunnel_type)
7446 switch (l2_tunnel_type) {
7447 case RTE_L2_TUNNEL_TYPE_E_TAG:
7448 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7451 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7460 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7461 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7464 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7466 uint32_t vmtir, vmvir;
7467 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7469 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7471 "VF id %u should be less than %u",
7477 if (hw->mac.type != ixgbe_mac_X550 &&
7478 hw->mac.type != ixgbe_mac_X550EM_x &&
7479 hw->mac.type != ixgbe_mac_X550EM_a) {
7484 vmtir = l2_tunnel->tunnel_id;
7488 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7490 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7491 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7493 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7494 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7499 /* Enable l2 tunnel tag insertion */
7501 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7502 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7506 switch (l2_tunnel->l2_tunnel_type) {
7507 case RTE_L2_TUNNEL_TYPE_E_TAG:
7508 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7511 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7519 /* Disable l2 tunnel tag insertion */
7521 ixgbe_dev_l2_tunnel_insertion_disable
7522 (struct rte_eth_dev *dev,
7523 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7527 switch (l2_tunnel->l2_tunnel_type) {
7528 case RTE_L2_TUNNEL_TYPE_E_TAG:
7529 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7532 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7541 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7546 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7548 if (hw->mac.type != ixgbe_mac_X550 &&
7549 hw->mac.type != ixgbe_mac_X550EM_x &&
7550 hw->mac.type != ixgbe_mac_X550EM_a) {
7554 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7556 qde |= IXGBE_QDE_STRIP_TAG;
7558 qde &= ~IXGBE_QDE_STRIP_TAG;
7559 qde &= ~IXGBE_QDE_READ;
7560 qde |= IXGBE_QDE_WRITE;
7561 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7566 /* Enable l2 tunnel tag stripping */
7568 ixgbe_dev_l2_tunnel_stripping_enable
7569 (struct rte_eth_dev *dev,
7570 enum rte_eth_tunnel_type l2_tunnel_type)
7574 switch (l2_tunnel_type) {
7575 case RTE_L2_TUNNEL_TYPE_E_TAG:
7576 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7579 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7587 /* Disable l2 tunnel tag stripping */
7589 ixgbe_dev_l2_tunnel_stripping_disable
7590 (struct rte_eth_dev *dev,
7591 enum rte_eth_tunnel_type l2_tunnel_type)
7595 switch (l2_tunnel_type) {
7596 case RTE_L2_TUNNEL_TYPE_E_TAG:
7597 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7600 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7608 /* Enable/disable l2 tunnel offload functions */
7610 ixgbe_dev_l2_tunnel_offload_set
7611 (struct rte_eth_dev *dev,
7612 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7618 if (l2_tunnel == NULL)
7622 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7624 ret = ixgbe_dev_l2_tunnel_enable(
7626 l2_tunnel->l2_tunnel_type);
7628 ret = ixgbe_dev_l2_tunnel_disable(
7630 l2_tunnel->l2_tunnel_type);
7633 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7635 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7639 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7644 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7646 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7648 l2_tunnel->l2_tunnel_type);
7650 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7652 l2_tunnel->l2_tunnel_type);
7655 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7657 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7659 l2_tunnel->l2_tunnel_type);
7661 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7663 l2_tunnel->l2_tunnel_type);
7670 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7673 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7674 IXGBE_WRITE_FLUSH(hw);
7679 /* There's only one register for VxLAN UDP port.
7680 * So, we cannot add several ports. Will update it.
7683 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7687 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7691 return ixgbe_update_vxlan_port(hw, port);
7694 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7695 * UDP port, it must have a value.
7696 * So, will reset it to the original value 0.
7699 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7704 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7706 if (cur_port != port) {
7707 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7711 return ixgbe_update_vxlan_port(hw, 0);
7714 /* Add UDP tunneling port */
7716 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7717 struct rte_eth_udp_tunnel *udp_tunnel)
7720 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7722 if (hw->mac.type != ixgbe_mac_X550 &&
7723 hw->mac.type != ixgbe_mac_X550EM_x &&
7724 hw->mac.type != ixgbe_mac_X550EM_a) {
7728 if (udp_tunnel == NULL)
7731 switch (udp_tunnel->prot_type) {
7732 case RTE_TUNNEL_TYPE_VXLAN:
7733 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7736 case RTE_TUNNEL_TYPE_GENEVE:
7737 case RTE_TUNNEL_TYPE_TEREDO:
7738 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7743 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7751 /* Remove UDP tunneling port */
7753 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7754 struct rte_eth_udp_tunnel *udp_tunnel)
7757 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7759 if (hw->mac.type != ixgbe_mac_X550 &&
7760 hw->mac.type != ixgbe_mac_X550EM_x &&
7761 hw->mac.type != ixgbe_mac_X550EM_a) {
7765 if (udp_tunnel == NULL)
7768 switch (udp_tunnel->prot_type) {
7769 case RTE_TUNNEL_TYPE_VXLAN:
7770 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7772 case RTE_TUNNEL_TYPE_GENEVE:
7773 case RTE_TUNNEL_TYPE_TEREDO:
7774 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7778 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7787 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7789 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7791 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7795 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7797 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7799 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7802 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7804 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7807 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7810 /* PF reset VF event */
7811 if (in_msg == IXGBE_PF_CONTROL_MSG)
7812 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
7816 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7819 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7820 struct ixgbe_interrupt *intr =
7821 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7822 ixgbevf_intr_disable(hw);
7824 /* read-on-clear nic registers here */
7825 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7828 /* only one misc vector supported - mailbox */
7829 eicr &= IXGBE_VTEICR_MASK;
7830 if (eicr == IXGBE_MISC_VEC_ID)
7831 intr->flags |= IXGBE_FLAG_MAILBOX;
7837 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7839 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7840 struct ixgbe_interrupt *intr =
7841 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7843 if (intr->flags & IXGBE_FLAG_MAILBOX) {
7844 ixgbevf_mbx_process(dev);
7845 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7848 ixgbevf_intr_enable(hw);
7854 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7857 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7859 ixgbevf_dev_interrupt_get_status(dev);
7860 ixgbevf_dev_interrupt_action(dev);
7864 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
7865 * @hw: pointer to hardware structure
7867 * Stops the transmit data path and waits for the HW to internally empty
7868 * the Tx security block
7870 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
7872 #define IXGBE_MAX_SECTX_POLL 40
7877 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7878 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
7879 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7880 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
7881 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
7882 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
7884 /* Use interrupt-safe sleep just in case */
7888 /* For informational purposes only */
7889 if (i >= IXGBE_MAX_SECTX_POLL)
7890 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
7891 "path fully disabled. Continuing with init.\n");
7893 return IXGBE_SUCCESS;
7897 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
7898 * @hw: pointer to hardware structure
7900 * Enables the transmit data path.
7902 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
7906 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7907 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
7908 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7909 IXGBE_WRITE_FLUSH(hw);
7911 return IXGBE_SUCCESS;
7915 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
7917 struct ixgbe_hw *hw;
7918 struct rte_eth_dev *dev;
7921 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
7923 dev = &rte_eth_devices[port];
7924 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7926 /* Stop the data paths */
7927 if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
7931 * As no ixgbe_disable_sec_rx_path equivalent is
7932 * implemented for tx in the base code, and we are
7933 * not allowed to modify the base code in DPDK, so
7934 * just call the hand-written one directly for now.
7935 * The hardware support has been checked by
7936 * ixgbe_disable_sec_rx_path().
7938 ixgbe_disable_sec_tx_path_generic(hw);
7940 /* Enable Ethernet CRC (required by MACsec offload) */
7941 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
7942 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
7943 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
7945 /* Enable the TX and RX crypto engines */
7946 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7947 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
7948 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
7950 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
7951 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
7952 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
7954 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
7955 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
7957 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
7959 /* Enable SA lookup */
7960 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
7961 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
7962 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
7963 IXGBE_LSECTXCTRL_AUTH;
7964 ctrl |= IXGBE_LSECTXCTRL_AISCI;
7965 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
7966 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
7967 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
7969 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
7970 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
7971 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
7972 ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
7974 ctrl |= IXGBE_LSECRXCTRL_RP;
7976 ctrl &= ~IXGBE_LSECRXCTRL_RP;
7977 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
7979 /* Start the data paths */
7980 ixgbe_enable_sec_rx_path(hw);
7983 * As no ixgbe_enable_sec_rx_path equivalent is
7984 * implemented for tx in the base code, and we are
7985 * not allowed to modify the base code in DPDK, so
7986 * just call the hand-written one directly for now.
7988 ixgbe_enable_sec_tx_path_generic(hw);
7994 rte_pmd_ixgbe_macsec_disable(uint8_t port)
7996 struct ixgbe_hw *hw;
7997 struct rte_eth_dev *dev;
8000 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8002 dev = &rte_eth_devices[port];
8003 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8005 /* Stop the data paths */
8006 if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8010 * As no ixgbe_disable_sec_rx_path equivalent is
8011 * implemented for tx in the base code, and we are
8012 * not allowed to modify the base code in DPDK, so
8013 * just call the hand-written one directly for now.
8014 * The hardware support has been checked by
8015 * ixgbe_disable_sec_rx_path().
8017 ixgbe_disable_sec_tx_path_generic(hw);
8019 /* Disable the TX and RX crypto engines */
8020 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8021 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8022 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8024 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8025 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8026 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8028 /* Disable SA lookup */
8029 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8030 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8031 ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8032 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8034 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8035 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8036 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8037 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8039 /* Start the data paths */
8040 ixgbe_enable_sec_rx_path(hw);
8043 * As no ixgbe_enable_sec_rx_path equivalent is
8044 * implemented for tx in the base code, and we are
8045 * not allowed to modify the base code in DPDK, so
8046 * just call the hand-written one directly for now.
8048 ixgbe_enable_sec_tx_path_generic(hw);
8054 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
8056 struct ixgbe_hw *hw;
8057 struct rte_eth_dev *dev;
8060 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8062 dev = &rte_eth_devices[port];
8063 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8065 ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8066 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
8068 ctrl = mac[4] | (mac[5] << 8);
8069 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
8075 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
8077 struct ixgbe_hw *hw;
8078 struct rte_eth_dev *dev;
8081 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8083 dev = &rte_eth_devices[port];
8084 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8086 ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8087 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
8089 pi = rte_cpu_to_be_16(pi);
8090 ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
8091 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
8097 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8098 uint32_t pn, uint8_t *key)
8100 struct ixgbe_hw *hw;
8101 struct rte_eth_dev *dev;
8104 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8106 dev = &rte_eth_devices[port];
8107 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8109 if (idx != 0 && idx != 1)
8115 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8117 /* Set the PN and key */
8118 pn = rte_cpu_to_be_32(pn);
8120 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8122 for (i = 0; i < 4; i++) {
8123 ctrl = (key[i * 4 + 0] << 0) |
8124 (key[i * 4 + 1] << 8) |
8125 (key[i * 4 + 2] << 16) |
8126 (key[i * 4 + 3] << 24);
8127 IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8130 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8132 for (i = 0; i < 4; i++) {
8133 ctrl = (key[i * 4 + 0] << 0) |
8134 (key[i * 4 + 1] << 8) |
8135 (key[i * 4 + 2] << 16) |
8136 (key[i * 4 + 3] << 24);
8137 IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8141 /* Set AN and select the SA */
8142 ctrl = (an << idx * 2) | (idx << 4);
8143 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8149 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8150 uint32_t pn, uint8_t *key)
8152 struct ixgbe_hw *hw;
8153 struct rte_eth_dev *dev;
8156 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8158 dev = &rte_eth_devices[port];
8159 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8161 if (idx != 0 && idx != 1)
8168 pn = rte_cpu_to_be_32(pn);
8169 IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8172 for (i = 0; i < 4; i++) {
8173 ctrl = (key[i * 4 + 0] << 0) |
8174 (key[i * 4 + 1] << 8) |
8175 (key[i * 4 + 2] << 16) |
8176 (key[i * 4 + 3] << 24);
8177 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8180 /* Set the AN and validate the SA */
8181 ctrl = an | (1 << 2);
8182 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8187 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
8188 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8189 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8190 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
8191 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8192 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");