4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
64 #include "ixgbe_logs.h"
65 #include "base/ixgbe_api.h"
66 #include "base/ixgbe_vf.h"
67 #include "base/ixgbe_common.h"
68 #include "ixgbe_ethdev.h"
69 #include "ixgbe_bypass.h"
70 #include "ixgbe_rxtx.h"
71 #include "base/ixgbe_type.h"
72 #include "base/ixgbe_phy.h"
73 #include "ixgbe_regs.h"
76 * High threshold controlling when to start sending XOFF frames. Must be at
77 * least 8 bytes less than receive packet buffer size. This value is in units
80 #define IXGBE_FC_HI 0x80
83 * Low threshold controlling when to start sending XON frames. This value is
84 * in units of 1024 bytes.
86 #define IXGBE_FC_LO 0x40
88 /* Default minimum inter-interrupt interval for EITR configuration */
89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
91 /* Timer value included in XOFF frames. */
92 #define IXGBE_FC_PAUSE 0x680
94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
95 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
96 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
98 #define IXGBE_MMW_SIZE_DEFAULT 0x4
99 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
100 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
103 * Default values for RX/TX configuration
105 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
106 #define IXGBE_DEFAULT_RX_PTHRESH 8
107 #define IXGBE_DEFAULT_RX_HTHRESH 8
108 #define IXGBE_DEFAULT_RX_WTHRESH 0
110 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
111 #define IXGBE_DEFAULT_TX_PTHRESH 32
112 #define IXGBE_DEFAULT_TX_HTHRESH 0
113 #define IXGBE_DEFAULT_TX_WTHRESH 0
114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
116 /* Bit shift and mask */
117 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
118 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
119 #define IXGBE_8_BIT_WIDTH CHAR_BIT
120 #define IXGBE_8_BIT_MASK UINT8_MAX
122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
126 #define IXGBE_HKEY_MAX_INDEX 10
128 /* Additional timesync values. */
129 #define IXGBE_TIMINCA_16NS_SHIFT 24
130 #define IXGBE_TIMINCA_INCVALUE 16000000
131 #define IXGBE_TIMINCA_INIT ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
132 | IXGBE_TIMINCA_INCVALUE)
134 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
135 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
136 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
137 static int ixgbe_dev_start(struct rte_eth_dev *dev);
138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
139 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
140 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
142 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
143 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
144 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
145 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
146 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
147 int wait_to_complete);
148 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
149 struct rte_eth_stats *stats);
150 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
151 struct rte_eth_xstats *xstats, unsigned n);
152 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
153 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
154 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
158 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
159 struct rte_eth_dev_info *dev_info);
160 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
161 struct rte_eth_dev_info *dev_info);
162 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
164 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
165 uint16_t vlan_id, int on);
166 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
167 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
168 uint16_t queue, bool on);
169 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
171 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
172 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
173 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
174 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
175 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
177 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
178 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
179 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
180 struct rte_eth_fc_conf *fc_conf);
181 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
182 struct rte_eth_fc_conf *fc_conf);
183 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
184 struct rte_eth_pfc_conf *pfc_conf);
185 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
186 struct rte_eth_rss_reta_entry64 *reta_conf,
188 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
189 struct rte_eth_rss_reta_entry64 *reta_conf,
191 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
192 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
193 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
194 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
195 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
196 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
198 static void ixgbe_dev_interrupt_delayed_handler(void *param);
199 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
200 uint32_t index, uint32_t pool);
201 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
202 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
203 struct ether_addr *mac_addr);
204 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
206 /* For Virtual Function support */
207 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
208 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
209 static int ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev);
210 static int ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev);
211 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
212 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
213 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
214 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
215 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
216 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
217 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
218 struct rte_eth_stats *stats);
219 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
220 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
221 uint16_t vlan_id, int on);
222 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
223 uint16_t queue, int on);
224 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
225 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
226 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
228 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
230 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
232 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
233 uint8_t queue, uint8_t msix_vector);
234 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
236 /* For Eth VMDQ APIs support */
237 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
238 ether_addr* mac_addr,uint8_t on);
239 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
240 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
241 uint16_t rx_mask, uint8_t on);
242 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
243 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
244 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
245 uint64_t pool_mask,uint8_t vlan_on);
246 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
247 struct rte_eth_mirror_conf *mirror_conf,
248 uint8_t rule_id, uint8_t on);
249 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
251 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
253 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
255 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
256 uint8_t queue, uint8_t msix_vector);
257 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
259 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
260 uint16_t queue_idx, uint16_t tx_rate);
261 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
262 uint16_t tx_rate, uint64_t q_msk);
264 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
265 struct ether_addr *mac_addr,
266 uint32_t index, uint32_t pool);
267 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
268 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
269 struct ether_addr *mac_addr);
270 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
271 struct rte_eth_syn_filter *filter,
273 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
274 struct rte_eth_syn_filter *filter);
275 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
276 enum rte_filter_op filter_op,
278 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
279 struct ixgbe_5tuple_filter *filter);
280 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
281 struct ixgbe_5tuple_filter *filter);
282 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
283 struct rte_eth_ntuple_filter *filter,
285 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
286 enum rte_filter_op filter_op,
288 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
289 struct rte_eth_ntuple_filter *filter);
290 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
291 struct rte_eth_ethertype_filter *filter,
293 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
294 enum rte_filter_op filter_op,
296 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
297 struct rte_eth_ethertype_filter *filter);
298 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
299 enum rte_filter_type filter_type,
300 enum rte_filter_op filter_op,
302 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
304 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
305 struct ether_addr *mc_addr_set,
306 uint32_t nb_mc_addr);
307 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
308 struct rte_eth_dcb_info *dcb_info);
310 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
311 static int ixgbe_get_regs(struct rte_eth_dev *dev,
312 struct rte_dev_reg_info *regs);
313 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
314 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
315 struct rte_dev_eeprom_info *eeprom);
316 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
317 struct rte_dev_eeprom_info *eeprom);
319 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
320 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
321 struct rte_dev_reg_info *regs);
323 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
324 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
325 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
326 struct timespec *timestamp,
328 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
329 struct timespec *timestamp);
332 * Define VF Stats MACRO for Non "cleared on read" register
334 #define UPDATE_VF_STAT(reg, last, cur) \
336 uint32_t latest = IXGBE_READ_REG(hw, reg); \
337 cur += (latest - last) & UINT_MAX; \
341 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
343 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
344 u64 new_msb = IXGBE_READ_REG(hw, msb); \
345 u64 latest = ((new_msb << 32) | new_lsb); \
346 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
350 #define IXGBE_SET_HWSTRIP(h, q) do{\
351 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
352 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
353 (h)->bitmap[idx] |= 1 << bit;\
356 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
357 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
358 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
359 (h)->bitmap[idx] &= ~(1 << bit);\
362 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
363 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
364 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
365 (r) = (h)->bitmap[idx] >> bit & 1;\
369 * The set of PCI devices this driver supports
371 static const struct rte_pci_id pci_id_ixgbe_map[] = {
373 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
374 #include "rte_pci_dev_ids.h"
376 { .vendor_id = 0, /* sentinel */ },
381 * The set of PCI devices this driver supports (for 82599 VF)
383 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
385 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
386 #include "rte_pci_dev_ids.h"
387 { .vendor_id = 0, /* sentinel */ },
391 static const struct rte_eth_desc_lim rx_desc_lim = {
392 .nb_max = IXGBE_MAX_RING_DESC,
393 .nb_min = IXGBE_MIN_RING_DESC,
394 .nb_align = IXGBE_RXD_ALIGN,
397 static const struct rte_eth_desc_lim tx_desc_lim = {
398 .nb_max = IXGBE_MAX_RING_DESC,
399 .nb_min = IXGBE_MIN_RING_DESC,
400 .nb_align = IXGBE_TXD_ALIGN,
403 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
404 .dev_configure = ixgbe_dev_configure,
405 .dev_start = ixgbe_dev_start,
406 .dev_stop = ixgbe_dev_stop,
407 .dev_set_link_up = ixgbe_dev_set_link_up,
408 .dev_set_link_down = ixgbe_dev_set_link_down,
409 .dev_close = ixgbe_dev_close,
410 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
411 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
412 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
413 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
414 .link_update = ixgbe_dev_link_update,
415 .stats_get = ixgbe_dev_stats_get,
416 .xstats_get = ixgbe_dev_xstats_get,
417 .stats_reset = ixgbe_dev_stats_reset,
418 .xstats_reset = ixgbe_dev_xstats_reset,
419 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
420 .dev_infos_get = ixgbe_dev_info_get,
421 .mtu_set = ixgbe_dev_mtu_set,
422 .vlan_filter_set = ixgbe_vlan_filter_set,
423 .vlan_tpid_set = ixgbe_vlan_tpid_set,
424 .vlan_offload_set = ixgbe_vlan_offload_set,
425 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
426 .rx_queue_start = ixgbe_dev_rx_queue_start,
427 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
428 .tx_queue_start = ixgbe_dev_tx_queue_start,
429 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
430 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
431 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
432 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
433 .rx_queue_release = ixgbe_dev_rx_queue_release,
434 .rx_queue_count = ixgbe_dev_rx_queue_count,
435 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
436 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
437 .tx_queue_release = ixgbe_dev_tx_queue_release,
438 .dev_led_on = ixgbe_dev_led_on,
439 .dev_led_off = ixgbe_dev_led_off,
440 .flow_ctrl_get = ixgbe_flow_ctrl_get,
441 .flow_ctrl_set = ixgbe_flow_ctrl_set,
442 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
443 .mac_addr_add = ixgbe_add_rar,
444 .mac_addr_remove = ixgbe_remove_rar,
445 .mac_addr_set = ixgbe_set_default_mac_addr,
446 .uc_hash_table_set = ixgbe_uc_hash_table_set,
447 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
448 .mirror_rule_set = ixgbe_mirror_rule_set,
449 .mirror_rule_reset = ixgbe_mirror_rule_reset,
450 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
451 .set_vf_rx = ixgbe_set_pool_rx,
452 .set_vf_tx = ixgbe_set_pool_tx,
453 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
454 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
455 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
456 .reta_update = ixgbe_dev_rss_reta_update,
457 .reta_query = ixgbe_dev_rss_reta_query,
458 #ifdef RTE_NIC_BYPASS
459 .bypass_init = ixgbe_bypass_init,
460 .bypass_state_set = ixgbe_bypass_state_store,
461 .bypass_state_show = ixgbe_bypass_state_show,
462 .bypass_event_set = ixgbe_bypass_event_store,
463 .bypass_event_show = ixgbe_bypass_event_show,
464 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
465 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
466 .bypass_ver_show = ixgbe_bypass_ver_show,
467 .bypass_wd_reset = ixgbe_bypass_wd_reset,
468 #endif /* RTE_NIC_BYPASS */
469 .rss_hash_update = ixgbe_dev_rss_hash_update,
470 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
471 .filter_ctrl = ixgbe_dev_filter_ctrl,
472 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
473 .rxq_info_get = ixgbe_rxq_info_get,
474 .txq_info_get = ixgbe_txq_info_get,
475 .timesync_enable = ixgbe_timesync_enable,
476 .timesync_disable = ixgbe_timesync_disable,
477 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
478 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
479 .get_reg_length = ixgbe_get_reg_length,
480 .get_reg = ixgbe_get_regs,
481 .get_eeprom_length = ixgbe_get_eeprom_length,
482 .get_eeprom = ixgbe_get_eeprom,
483 .set_eeprom = ixgbe_set_eeprom,
484 .get_dcb_info = ixgbe_dev_get_dcb_info,
488 * dev_ops for virtual function, bare necessities for basic vf
489 * operation have been implemented
491 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
492 .dev_configure = ixgbevf_dev_configure,
493 .dev_start = ixgbevf_dev_start,
494 .dev_stop = ixgbevf_dev_stop,
495 .link_update = ixgbe_dev_link_update,
496 .stats_get = ixgbevf_dev_stats_get,
497 .stats_reset = ixgbevf_dev_stats_reset,
498 .dev_close = ixgbevf_dev_close,
499 .dev_infos_get = ixgbevf_dev_info_get,
500 .mtu_set = ixgbevf_dev_set_mtu,
501 .vlan_filter_set = ixgbevf_vlan_filter_set,
502 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
503 .vlan_offload_set = ixgbevf_vlan_offload_set,
504 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
505 .rx_queue_release = ixgbe_dev_rx_queue_release,
506 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
507 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
508 .tx_queue_release = ixgbe_dev_tx_queue_release,
509 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
510 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
511 .mac_addr_add = ixgbevf_add_mac_addr,
512 .mac_addr_remove = ixgbevf_remove_mac_addr,
513 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
514 .rxq_info_get = ixgbe_rxq_info_get,
515 .txq_info_get = ixgbe_txq_info_get,
516 .mac_addr_set = ixgbevf_set_default_mac_addr,
517 .get_reg_length = ixgbevf_get_reg_length,
518 .get_reg = ixgbevf_get_regs,
519 .reta_update = ixgbe_dev_rss_reta_update,
520 .reta_query = ixgbe_dev_rss_reta_query,
521 .rss_hash_update = ixgbe_dev_rss_hash_update,
522 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
525 /* store statistics names and its offset in stats structure */
526 struct rte_ixgbe_xstats_name_off {
527 char name[RTE_ETH_XSTATS_NAME_SIZE];
531 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
532 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
533 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
534 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
535 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
536 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
537 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
538 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
539 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
540 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
541 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
542 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
543 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
544 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
545 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
546 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
548 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
550 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
551 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
552 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
553 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
554 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
555 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
556 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
557 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
558 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
559 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
560 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
561 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
562 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
563 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
564 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
565 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
566 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
568 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
570 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
571 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
572 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
573 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
575 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
577 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
579 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
581 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
583 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
585 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
588 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
589 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
590 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
592 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
593 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
594 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
595 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
596 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
598 {"rx_fcoe_no_direct_data_placement_ext_buff",
599 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
601 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
603 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
605 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
607 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
609 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
612 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
613 sizeof(rte_ixgbe_stats_strings[0]))
615 /* Per-queue statistics */
616 #define IXBGE_NB_8_PER_Q_STATS (8 * 7)
617 #define IXBGE_NB_16_PER_Q_STATS (16 * 5)
618 #define IXGBE_NB_Q_STATS (IXBGE_NB_8_PER_Q_STATS + IXBGE_NB_16_PER_Q_STATS)
620 #define IXGBE_NB_XSTATS (IXGBE_NB_HW_STATS + IXGBE_NB_Q_STATS)
623 * Atomically reads the link status information from global
624 * structure rte_eth_dev.
627 * - Pointer to the structure rte_eth_dev to read from.
628 * - Pointer to the buffer to be saved with the link status.
631 * - On success, zero.
632 * - On failure, negative value.
635 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
636 struct rte_eth_link *link)
638 struct rte_eth_link *dst = link;
639 struct rte_eth_link *src = &(dev->data->dev_link);
641 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
642 *(uint64_t *)src) == 0)
649 * Atomically writes the link status information into global
650 * structure rte_eth_dev.
653 * - Pointer to the structure rte_eth_dev to read from.
654 * - Pointer to the buffer to be saved with the link status.
657 * - On success, zero.
658 * - On failure, negative value.
661 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
662 struct rte_eth_link *link)
664 struct rte_eth_link *dst = &(dev->data->dev_link);
665 struct rte_eth_link *src = link;
667 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
668 *(uint64_t *)src) == 0)
675 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
678 ixgbe_is_sfp(struct ixgbe_hw *hw)
680 switch (hw->phy.type) {
681 case ixgbe_phy_sfp_avago:
682 case ixgbe_phy_sfp_ftl:
683 case ixgbe_phy_sfp_intel:
684 case ixgbe_phy_sfp_unknown:
685 case ixgbe_phy_sfp_passive_tyco:
686 case ixgbe_phy_sfp_passive_unknown:
693 static inline int32_t
694 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
699 status = ixgbe_reset_hw(hw);
701 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
702 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
703 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
704 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
705 IXGBE_WRITE_FLUSH(hw);
711 ixgbe_enable_intr(struct rte_eth_dev *dev)
713 struct ixgbe_interrupt *intr =
714 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
715 struct ixgbe_hw *hw =
716 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
718 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
719 IXGBE_WRITE_FLUSH(hw);
723 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
726 ixgbe_disable_intr(struct ixgbe_hw *hw)
728 PMD_INIT_FUNC_TRACE();
730 if (hw->mac.type == ixgbe_mac_82598EB) {
731 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
733 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
734 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
735 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
737 IXGBE_WRITE_FLUSH(hw);
741 * This function resets queue statistics mapping registers.
742 * From Niantic datasheet, Initialization of Statistics section:
743 * "...if software requires the queue counters, the RQSMR and TQSM registers
744 * must be re-programmed following a device reset.
747 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
751 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
752 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
753 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
759 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
764 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
765 #define NB_QMAP_FIELDS_PER_QSM_REG 4
766 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
768 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
769 struct ixgbe_stat_mapping_registers *stat_mappings =
770 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
771 uint32_t qsmr_mask = 0;
772 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
776 if ((hw->mac.type != ixgbe_mac_82599EB) &&
777 (hw->mac.type != ixgbe_mac_X540) &&
778 (hw->mac.type != ixgbe_mac_X550) &&
779 (hw->mac.type != ixgbe_mac_X550EM_x))
782 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
783 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
786 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
787 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
788 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
791 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
793 /* Now clear any previous stat_idx set */
794 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
796 stat_mappings->tqsm[n] &= ~clearing_mask;
798 stat_mappings->rqsmr[n] &= ~clearing_mask;
800 q_map = (uint32_t)stat_idx;
801 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
802 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
804 stat_mappings->tqsm[n] |= qsmr_mask;
806 stat_mappings->rqsmr[n] |= qsmr_mask;
808 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
809 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
811 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
812 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
814 /* Now write the mapping in the appropriate register */
816 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
817 stat_mappings->rqsmr[n], n);
818 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
821 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
822 stat_mappings->tqsm[n], n);
823 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
829 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
831 struct ixgbe_stat_mapping_registers *stat_mappings =
832 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
833 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
836 /* write whatever was in stat mapping table to the NIC */
837 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
839 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
842 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
847 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
850 struct ixgbe_dcb_tc_config *tc;
851 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
853 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
854 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
855 for (i = 0; i < dcb_max_tc; i++) {
856 tc = &dcb_config->tc_config[i];
857 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
858 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
859 (uint8_t)(100/dcb_max_tc + (i & 1));
860 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
861 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
862 (uint8_t)(100/dcb_max_tc + (i & 1));
863 tc->pfc = ixgbe_dcb_pfc_disabled;
866 /* Initialize default user to priority mapping, UPx->TC0 */
867 tc = &dcb_config->tc_config[0];
868 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
869 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
870 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
871 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
872 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
874 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
875 dcb_config->pfc_mode_enable = false;
876 dcb_config->vt_mode = true;
877 dcb_config->round_robin_enable = false;
878 /* support all DCB capabilities in 82599 */
879 dcb_config->support.capabilities = 0xFF;
881 /*we only support 4 Tcs for X540, X550 */
882 if (hw->mac.type == ixgbe_mac_X540 ||
883 hw->mac.type == ixgbe_mac_X550 ||
884 hw->mac.type == ixgbe_mac_X550EM_x) {
885 dcb_config->num_tcs.pg_tcs = 4;
886 dcb_config->num_tcs.pfc_tcs = 4;
891 * Ensure that all locks are released before first NVM or PHY access
894 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
899 * Phy lock should not fail in this early stage. If this is the case,
900 * it is due to an improper exit of the application.
901 * So force the release of the faulty lock. Release of common lock
902 * is done automatically by swfw_sync function.
904 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
905 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
906 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
908 ixgbe_release_swfw_semaphore(hw, mask);
911 * These ones are more tricky since they are common to all ports; but
912 * swfw_sync retries last long enough (1s) to be almost sure that if
913 * lock can not be taken it is due to an improper lock of the
916 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
917 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
918 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
920 ixgbe_release_swfw_semaphore(hw, mask);
924 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
925 * It returns 0 on success.
928 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
930 struct rte_pci_device *pci_dev;
931 struct ixgbe_hw *hw =
932 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
933 struct ixgbe_vfta * shadow_vfta =
934 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
935 struct ixgbe_hwstrip *hwstrip =
936 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
937 struct ixgbe_dcb_config *dcb_config =
938 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
939 struct ixgbe_filter_info *filter_info =
940 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
945 PMD_INIT_FUNC_TRACE();
947 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
948 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
949 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
952 * For secondary processes, we don't initialise any further as primary
953 * has already done this work. Only check we don't need a different
954 * RX and TX function.
956 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
957 struct ixgbe_tx_queue *txq;
958 /* TX queue function in primary, set by last queue initialized
959 * Tx queue may not initialized by primary process */
960 if (eth_dev->data->tx_queues) {
961 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
962 ixgbe_set_tx_function(eth_dev, txq);
964 /* Use default TX function if we get here */
965 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
966 "Using default TX function.");
969 ixgbe_set_rx_function(eth_dev);
973 pci_dev = eth_dev->pci_dev;
975 /* Vendor and Device ID need to be set before init of shared code */
976 hw->device_id = pci_dev->id.device_id;
977 hw->vendor_id = pci_dev->id.vendor_id;
978 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
979 hw->allow_unsupported_sfp = 1;
981 /* Initialize the shared code (base driver) */
982 #ifdef RTE_NIC_BYPASS
983 diag = ixgbe_bypass_init_shared_code(hw);
985 diag = ixgbe_init_shared_code(hw);
986 #endif /* RTE_NIC_BYPASS */
988 if (diag != IXGBE_SUCCESS) {
989 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
993 /* pick up the PCI bus settings for reporting later */
994 ixgbe_get_bus_info(hw);
996 /* Unlock any pending hardware semaphore */
997 ixgbe_swfw_lock_reset(hw);
999 /* Initialize DCB configuration*/
1000 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1001 ixgbe_dcb_init(hw,dcb_config);
1002 /* Get Hardware Flow Control setting */
1003 hw->fc.requested_mode = ixgbe_fc_full;
1004 hw->fc.current_mode = ixgbe_fc_full;
1005 hw->fc.pause_time = IXGBE_FC_PAUSE;
1006 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1007 hw->fc.low_water[i] = IXGBE_FC_LO;
1008 hw->fc.high_water[i] = IXGBE_FC_HI;
1010 hw->fc.send_xon = 1;
1012 /* Make sure we have a good EEPROM before we read from it */
1013 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1014 if (diag != IXGBE_SUCCESS) {
1015 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1019 #ifdef RTE_NIC_BYPASS
1020 diag = ixgbe_bypass_init_hw(hw);
1022 diag = ixgbe_init_hw(hw);
1023 #endif /* RTE_NIC_BYPASS */
1026 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1027 * is called too soon after the kernel driver unbinding/binding occurs.
1028 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1029 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1030 * also called. See ixgbe_identify_phy_82599(). The reason for the
1031 * failure is not known, and only occuts when virtualisation features
1032 * are disabled in the bios. A delay of 100ms was found to be enough by
1033 * trial-and-error, and is doubled to be safe.
1035 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1037 diag = ixgbe_init_hw(hw);
1040 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1041 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1042 "LOM. Please be aware there may be issues associated "
1043 "with your hardware.");
1044 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1045 "please contact your Intel or hardware representative "
1046 "who provided you with this hardware.");
1047 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1048 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1050 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1054 /* Reset the hw statistics */
1055 ixgbe_dev_stats_reset(eth_dev);
1057 /* disable interrupt */
1058 ixgbe_disable_intr(hw);
1060 /* reset mappings for queue statistics hw counters*/
1061 ixgbe_reset_qstat_mappings(hw);
1063 /* Allocate memory for storing MAC addresses */
1064 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1065 hw->mac.num_rar_entries, 0);
1066 if (eth_dev->data->mac_addrs == NULL) {
1068 "Failed to allocate %u bytes needed to store "
1070 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1073 /* Copy the permanent MAC address */
1074 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1075 ð_dev->data->mac_addrs[0]);
1077 /* Allocate memory for storing hash filter MAC addresses */
1078 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1079 IXGBE_VMDQ_NUM_UC_MAC, 0);
1080 if (eth_dev->data->hash_mac_addrs == NULL) {
1082 "Failed to allocate %d bytes needed to store MAC addresses",
1083 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1087 /* initialize the vfta */
1088 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1090 /* initialize the hw strip bitmap*/
1091 memset(hwstrip, 0, sizeof(*hwstrip));
1093 /* initialize PF if max_vfs not zero */
1094 ixgbe_pf_host_init(eth_dev);
1096 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1097 /* let hardware know driver is loaded */
1098 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1099 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1100 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1101 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1102 IXGBE_WRITE_FLUSH(hw);
1104 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1105 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1106 (int) hw->mac.type, (int) hw->phy.type,
1107 (int) hw->phy.sfp_type);
1109 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1110 (int) hw->mac.type, (int) hw->phy.type);
1112 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1113 eth_dev->data->port_id, pci_dev->id.vendor_id,
1114 pci_dev->id.device_id);
1116 /* enable support intr */
1117 ixgbe_enable_intr(eth_dev);
1119 /* initialize 5tuple filter list */
1120 TAILQ_INIT(&filter_info->fivetuple_list);
1121 memset(filter_info->fivetuple_mask, 0,
1122 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1128 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1130 struct rte_pci_device *pci_dev;
1131 struct ixgbe_hw *hw;
1133 PMD_INIT_FUNC_TRACE();
1135 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1138 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1139 pci_dev = eth_dev->pci_dev;
1141 if (hw->adapter_stopped == 0)
1142 ixgbe_dev_close(eth_dev);
1144 eth_dev->dev_ops = NULL;
1145 eth_dev->rx_pkt_burst = NULL;
1146 eth_dev->tx_pkt_burst = NULL;
1148 /* Unlock any pending hardware semaphore */
1149 ixgbe_swfw_lock_reset(hw);
1151 /* disable uio intr before callback unregister */
1152 rte_intr_disable(&(pci_dev->intr_handle));
1153 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1154 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1156 /* uninitialize PF if max_vfs not zero */
1157 ixgbe_pf_host_uninit(eth_dev);
1159 rte_free(eth_dev->data->mac_addrs);
1160 eth_dev->data->mac_addrs = NULL;
1162 rte_free(eth_dev->data->hash_mac_addrs);
1163 eth_dev->data->hash_mac_addrs = NULL;
1169 * Negotiate mailbox API version with the PF.
1170 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1171 * Then we try to negotiate starting with the most recent one.
1172 * If all negotiation attempts fail, then we will proceed with
1173 * the default one (ixgbe_mbox_api_10).
1176 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1180 /* start with highest supported, proceed down */
1181 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1187 i != RTE_DIM(sup_ver) &&
1188 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1194 generate_random_mac_addr(struct ether_addr *mac_addr)
1198 /* Set Organizationally Unique Identifier (OUI) prefix. */
1199 mac_addr->addr_bytes[0] = 0x00;
1200 mac_addr->addr_bytes[1] = 0x09;
1201 mac_addr->addr_bytes[2] = 0xC0;
1202 /* Force indication of locally assigned MAC address. */
1203 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1204 /* Generate the last 3 bytes of the MAC address with a random number. */
1205 random = rte_rand();
1206 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1210 * Virtual Function device init
1213 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1217 struct rte_pci_device *pci_dev;
1218 struct ixgbe_hw *hw =
1219 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1220 struct ixgbe_vfta * shadow_vfta =
1221 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1222 struct ixgbe_hwstrip *hwstrip =
1223 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1224 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1226 PMD_INIT_FUNC_TRACE();
1228 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1229 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1230 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1232 /* for secondary processes, we don't initialise any further as primary
1233 * has already done this work. Only check we don't need a different
1235 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1236 if (eth_dev->data->scattered_rx)
1237 eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1241 pci_dev = eth_dev->pci_dev;
1243 hw->device_id = pci_dev->id.device_id;
1244 hw->vendor_id = pci_dev->id.vendor_id;
1245 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1247 /* initialize the vfta */
1248 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1250 /* initialize the hw strip bitmap*/
1251 memset(hwstrip, 0, sizeof(*hwstrip));
1253 /* Initialize the shared code (base driver) */
1254 diag = ixgbe_init_shared_code(hw);
1255 if (diag != IXGBE_SUCCESS) {
1256 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1260 /* init_mailbox_params */
1261 hw->mbx.ops.init_params(hw);
1263 /* Reset the hw statistics */
1264 ixgbevf_dev_stats_reset(eth_dev);
1266 /* Disable the interrupts for VF */
1267 ixgbevf_intr_disable(hw);
1269 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1270 diag = hw->mac.ops.reset_hw(hw);
1273 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1274 * the underlying PF driver has not assigned a MAC address to the VF.
1275 * In this case, assign a random MAC address.
1277 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1278 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1282 /* negotiate mailbox API version to use with the PF. */
1283 ixgbevf_negotiate_api(hw);
1285 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1286 ixgbevf_get_queues(hw, &tcs, &tc);
1288 /* Allocate memory for storing MAC addresses */
1289 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1290 hw->mac.num_rar_entries, 0);
1291 if (eth_dev->data->mac_addrs == NULL) {
1293 "Failed to allocate %u bytes needed to store "
1295 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1299 /* Generate a random MAC address, if none was assigned by PF. */
1300 if (is_zero_ether_addr(perm_addr)) {
1301 generate_random_mac_addr(perm_addr);
1302 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1304 rte_free(eth_dev->data->mac_addrs);
1305 eth_dev->data->mac_addrs = NULL;
1308 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1309 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1310 "%02x:%02x:%02x:%02x:%02x:%02x",
1311 perm_addr->addr_bytes[0],
1312 perm_addr->addr_bytes[1],
1313 perm_addr->addr_bytes[2],
1314 perm_addr->addr_bytes[3],
1315 perm_addr->addr_bytes[4],
1316 perm_addr->addr_bytes[5]);
1319 /* Copy the permanent MAC address */
1320 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1322 /* reset the hardware with the new settings */
1323 diag = hw->mac.ops.start_hw(hw);
1329 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1333 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1334 eth_dev->data->port_id, pci_dev->id.vendor_id,
1335 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1340 /* Virtual Function device uninit */
1343 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1345 struct ixgbe_hw *hw;
1348 PMD_INIT_FUNC_TRACE();
1350 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1353 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1355 if (hw->adapter_stopped == 0)
1356 ixgbevf_dev_close(eth_dev);
1358 eth_dev->dev_ops = NULL;
1359 eth_dev->rx_pkt_burst = NULL;
1360 eth_dev->tx_pkt_burst = NULL;
1362 /* Disable the interrupts for VF */
1363 ixgbevf_intr_disable(hw);
1365 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1366 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1367 eth_dev->data->rx_queues[i] = NULL;
1369 eth_dev->data->nb_rx_queues = 0;
1371 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1372 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1373 eth_dev->data->tx_queues[i] = NULL;
1375 eth_dev->data->nb_tx_queues = 0;
1377 rte_free(eth_dev->data->mac_addrs);
1378 eth_dev->data->mac_addrs = NULL;
1383 static struct eth_driver rte_ixgbe_pmd = {
1385 .name = "rte_ixgbe_pmd",
1386 .id_table = pci_id_ixgbe_map,
1387 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1388 RTE_PCI_DRV_DETACHABLE,
1390 .eth_dev_init = eth_ixgbe_dev_init,
1391 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1392 .dev_private_size = sizeof(struct ixgbe_adapter),
1396 * virtual function driver struct
1398 static struct eth_driver rte_ixgbevf_pmd = {
1400 .name = "rte_ixgbevf_pmd",
1401 .id_table = pci_id_ixgbevf_map,
1402 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1404 .eth_dev_init = eth_ixgbevf_dev_init,
1405 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1406 .dev_private_size = sizeof(struct ixgbe_adapter),
1410 * Driver initialization routine.
1411 * Invoked once at EAL init time.
1412 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1415 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1417 PMD_INIT_FUNC_TRACE();
1419 rte_eth_driver_register(&rte_ixgbe_pmd);
1424 * VF Driver initialization routine.
1425 * Invoked one at EAL init time.
1426 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1429 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1431 PMD_INIT_FUNC_TRACE();
1433 rte_eth_driver_register(&rte_ixgbevf_pmd);
1438 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1440 struct ixgbe_hw *hw =
1441 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1442 struct ixgbe_vfta * shadow_vfta =
1443 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1448 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1449 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1450 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1455 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1457 /* update local VFTA copy */
1458 shadow_vfta->vfta[vid_idx] = vfta;
1464 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1467 ixgbe_vlan_hw_strip_enable(dev, queue);
1469 ixgbe_vlan_hw_strip_disable(dev, queue);
1473 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1475 struct ixgbe_hw *hw =
1476 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1478 /* Only the high 16-bits is valid */
1479 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1483 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1485 struct ixgbe_hw *hw =
1486 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1489 PMD_INIT_FUNC_TRACE();
1491 /* Filter Table Disable */
1492 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1493 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1495 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1499 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1501 struct ixgbe_hw *hw =
1502 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1503 struct ixgbe_vfta * shadow_vfta =
1504 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1508 PMD_INIT_FUNC_TRACE();
1510 /* Filter Table Enable */
1511 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1512 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1513 vlnctrl |= IXGBE_VLNCTRL_VFE;
1515 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1517 /* write whatever is in local vfta copy */
1518 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1519 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1523 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1525 struct ixgbe_hwstrip *hwstrip =
1526 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1528 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1532 IXGBE_SET_HWSTRIP(hwstrip, queue);
1534 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1538 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1540 struct ixgbe_hw *hw =
1541 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1544 PMD_INIT_FUNC_TRACE();
1546 if (hw->mac.type == ixgbe_mac_82598EB) {
1547 /* No queue level support */
1548 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1552 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1553 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1554 ctrl &= ~IXGBE_RXDCTL_VME;
1555 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1557 /* record those setting for HW strip per queue */
1558 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1562 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1564 struct ixgbe_hw *hw =
1565 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1568 PMD_INIT_FUNC_TRACE();
1570 if (hw->mac.type == ixgbe_mac_82598EB) {
1571 /* No queue level supported */
1572 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1576 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1577 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1578 ctrl |= IXGBE_RXDCTL_VME;
1579 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1581 /* record those setting for HW strip per queue */
1582 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1586 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1588 struct ixgbe_hw *hw =
1589 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1593 PMD_INIT_FUNC_TRACE();
1595 if (hw->mac.type == ixgbe_mac_82598EB) {
1596 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1597 ctrl &= ~IXGBE_VLNCTRL_VME;
1598 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1601 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1602 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1603 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1604 ctrl &= ~IXGBE_RXDCTL_VME;
1605 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1607 /* record those setting for HW strip per queue */
1608 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1614 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1616 struct ixgbe_hw *hw =
1617 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1621 PMD_INIT_FUNC_TRACE();
1623 if (hw->mac.type == ixgbe_mac_82598EB) {
1624 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1625 ctrl |= IXGBE_VLNCTRL_VME;
1626 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1629 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1630 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1631 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1632 ctrl |= IXGBE_RXDCTL_VME;
1633 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1635 /* record those setting for HW strip per queue */
1636 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1642 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1644 struct ixgbe_hw *hw =
1645 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1648 PMD_INIT_FUNC_TRACE();
1650 /* DMATXCTRL: Geric Double VLAN Disable */
1651 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1652 ctrl &= ~IXGBE_DMATXCTL_GDV;
1653 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1655 /* CTRL_EXT: Global Double VLAN Disable */
1656 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1657 ctrl &= ~IXGBE_EXTENDED_VLAN;
1658 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1663 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1665 struct ixgbe_hw *hw =
1666 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1669 PMD_INIT_FUNC_TRACE();
1671 /* DMATXCTRL: Geric Double VLAN Enable */
1672 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1673 ctrl |= IXGBE_DMATXCTL_GDV;
1674 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1676 /* CTRL_EXT: Global Double VLAN Enable */
1677 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1678 ctrl |= IXGBE_EXTENDED_VLAN;
1679 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1682 * VET EXT field in the EXVET register = 0x8100 by default
1683 * So no need to change. Same to VT field of DMATXCTL register
1688 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1690 if(mask & ETH_VLAN_STRIP_MASK){
1691 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1692 ixgbe_vlan_hw_strip_enable_all(dev);
1694 ixgbe_vlan_hw_strip_disable_all(dev);
1697 if(mask & ETH_VLAN_FILTER_MASK){
1698 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1699 ixgbe_vlan_hw_filter_enable(dev);
1701 ixgbe_vlan_hw_filter_disable(dev);
1704 if(mask & ETH_VLAN_EXTEND_MASK){
1705 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1706 ixgbe_vlan_hw_extend_enable(dev);
1708 ixgbe_vlan_hw_extend_disable(dev);
1713 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1715 struct ixgbe_hw *hw =
1716 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1717 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1718 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1719 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1720 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1724 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1729 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1732 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1738 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1739 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1745 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1747 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1748 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1749 uint16_t nb_tx_q = dev->data->nb_rx_queues;
1751 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1752 /* check multi-queue mode */
1753 switch (dev_conf->rxmode.mq_mode) {
1754 case ETH_MQ_RX_VMDQ_DCB:
1755 case ETH_MQ_RX_VMDQ_DCB_RSS:
1756 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1757 PMD_INIT_LOG(ERR, "SRIOV active,"
1758 " unsupported mq_mode rx %d.",
1759 dev_conf->rxmode.mq_mode);
1762 case ETH_MQ_RX_VMDQ_RSS:
1763 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1764 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1765 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1766 PMD_INIT_LOG(ERR, "SRIOV is active,"
1767 " invalid queue number"
1768 " for VMDQ RSS, allowed"
1769 " value are 1, 2 or 4.");
1773 case ETH_MQ_RX_VMDQ_ONLY:
1774 case ETH_MQ_RX_NONE:
1775 /* if nothing mq mode configure, use default scheme */
1776 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1777 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1778 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1780 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1781 /* SRIOV only works in VMDq enable mode */
1782 PMD_INIT_LOG(ERR, "SRIOV is active,"
1783 " wrong mq_mode rx %d.",
1784 dev_conf->rxmode.mq_mode);
1788 switch (dev_conf->txmode.mq_mode) {
1789 case ETH_MQ_TX_VMDQ_DCB:
1790 /* DCB VMDQ in SRIOV mode, not implement yet */
1791 PMD_INIT_LOG(ERR, "SRIOV is active,"
1792 " unsupported VMDQ mq_mode tx %d.",
1793 dev_conf->txmode.mq_mode);
1795 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1796 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1800 /* check valid queue number */
1801 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1802 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1803 PMD_INIT_LOG(ERR, "SRIOV is active,"
1804 " queue number must less equal to %d.",
1805 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1809 /* check configuration for vmdb+dcb mode */
1810 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1811 const struct rte_eth_vmdq_dcb_conf *conf;
1813 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1814 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1815 IXGBE_VMDQ_DCB_NB_QUEUES);
1818 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1819 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1820 conf->nb_queue_pools == ETH_32_POOLS)) {
1821 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1822 " nb_queue_pools must be %d or %d.",
1823 ETH_16_POOLS, ETH_32_POOLS);
1827 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1828 const struct rte_eth_vmdq_dcb_tx_conf *conf;
1830 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1831 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1832 IXGBE_VMDQ_DCB_NB_QUEUES);
1835 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1836 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1837 conf->nb_queue_pools == ETH_32_POOLS)) {
1838 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1839 " nb_queue_pools != %d and"
1840 " nb_queue_pools != %d.",
1841 ETH_16_POOLS, ETH_32_POOLS);
1846 /* For DCB mode check our configuration before we go further */
1847 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1848 const struct rte_eth_dcb_rx_conf *conf;
1850 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1851 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1852 IXGBE_DCB_NB_QUEUES);
1855 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1856 if (!(conf->nb_tcs == ETH_4_TCS ||
1857 conf->nb_tcs == ETH_8_TCS)) {
1858 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1859 " and nb_tcs != %d.",
1860 ETH_4_TCS, ETH_8_TCS);
1865 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1866 const struct rte_eth_dcb_tx_conf *conf;
1868 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1869 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1870 IXGBE_DCB_NB_QUEUES);
1873 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1874 if (!(conf->nb_tcs == ETH_4_TCS ||
1875 conf->nb_tcs == ETH_8_TCS)) {
1876 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1877 " and nb_tcs != %d.",
1878 ETH_4_TCS, ETH_8_TCS);
1887 ixgbe_dev_configure(struct rte_eth_dev *dev)
1889 struct ixgbe_interrupt *intr =
1890 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1891 struct ixgbe_adapter *adapter =
1892 (struct ixgbe_adapter *)dev->data->dev_private;
1895 PMD_INIT_FUNC_TRACE();
1896 /* multipe queue mode checking */
1897 ret = ixgbe_check_mq_mode(dev);
1899 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
1904 /* set flag to update link status after init */
1905 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1908 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1909 * allocation or vector Rx preconditions we will reset it.
1911 adapter->rx_bulk_alloc_allowed = true;
1912 adapter->rx_vec_allowed = true;
1918 * Configure device link speed and setup link.
1919 * It returns 0 on success.
1922 ixgbe_dev_start(struct rte_eth_dev *dev)
1924 struct ixgbe_hw *hw =
1925 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1926 struct ixgbe_vf_info *vfinfo =
1927 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1928 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1929 uint32_t intr_vector = 0;
1930 int err, link_up = 0, negotiate = 0;
1936 PMD_INIT_FUNC_TRACE();
1938 /* IXGBE devices don't support half duplex */
1939 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1940 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1941 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1942 dev->data->dev_conf.link_duplex,
1943 dev->data->port_id);
1948 hw->adapter_stopped = 0;
1949 ixgbe_stop_adapter(hw);
1951 /* reinitialize adapter
1952 * this calls reset and start */
1953 status = ixgbe_pf_reset_hw(hw);
1956 hw->mac.ops.start_hw(hw);
1957 hw->mac.get_link_status = true;
1959 /* configure PF module if SRIOV enabled */
1960 ixgbe_pf_host_configure(dev);
1962 /* check and configure queue intr-vector mapping */
1963 if (dev->data->dev_conf.intr_conf.rxq != 0)
1964 intr_vector = dev->data->nb_rx_queues;
1966 if (rte_intr_efd_enable(intr_handle, intr_vector))
1969 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1970 intr_handle->intr_vec =
1971 rte_zmalloc("intr_vec",
1972 dev->data->nb_rx_queues * sizeof(int),
1974 if (intr_handle->intr_vec == NULL) {
1975 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1976 " intr_vec\n", dev->data->nb_rx_queues);
1981 /* confiugre msix for sleep until rx interrupt */
1982 ixgbe_configure_msix(dev);
1984 /* initialize transmission unit */
1985 ixgbe_dev_tx_init(dev);
1987 /* This can fail when allocating mbufs for descriptor rings */
1988 err = ixgbe_dev_rx_init(dev);
1990 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1994 err = ixgbe_dev_rxtx_start(dev);
1996 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2000 /* Skip link setup if loopback mode is enabled for 82599. */
2001 if (hw->mac.type == ixgbe_mac_82599EB &&
2002 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2003 goto skip_link_setup;
2005 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2006 err = hw->mac.ops.setup_sfp(hw);
2011 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2012 /* Turn on the copper */
2013 ixgbe_set_phy_power(hw, true);
2015 /* Turn on the laser */
2016 ixgbe_enable_tx_laser(hw);
2019 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2022 dev->data->dev_link.link_status = link_up;
2024 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2028 switch(dev->data->dev_conf.link_speed) {
2029 case ETH_LINK_SPEED_AUTONEG:
2030 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2031 IXGBE_LINK_SPEED_82599_AUTONEG :
2032 IXGBE_LINK_SPEED_82598_AUTONEG;
2034 case ETH_LINK_SPEED_100:
2036 * Invalid for 82598 but error will be detected by
2037 * ixgbe_setup_link()
2039 speed = IXGBE_LINK_SPEED_100_FULL;
2041 case ETH_LINK_SPEED_1000:
2042 speed = IXGBE_LINK_SPEED_1GB_FULL;
2044 case ETH_LINK_SPEED_10000:
2045 speed = IXGBE_LINK_SPEED_10GB_FULL;
2048 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2049 dev->data->dev_conf.link_speed,
2050 dev->data->port_id);
2054 err = ixgbe_setup_link(hw, speed, link_up);
2060 /* check if lsc interrupt is enabled */
2061 if (dev->data->dev_conf.intr_conf.lsc != 0) {
2062 if (rte_intr_allow_others(intr_handle)) {
2063 rte_intr_callback_register(intr_handle,
2064 ixgbe_dev_interrupt_handler,
2066 ixgbe_dev_lsc_interrupt_setup(dev);
2068 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2069 " no intr multiplex\n");
2072 /* check if rxq interrupt is enabled */
2073 if (dev->data->dev_conf.intr_conf.rxq != 0)
2074 ixgbe_dev_rxq_interrupt_setup(dev);
2076 /* enable uio/vfio intr/eventfd mapping */
2077 rte_intr_enable(intr_handle);
2079 /* resume enabled intr since hw reset */
2080 ixgbe_enable_intr(dev);
2082 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2083 ETH_VLAN_EXTEND_MASK;
2084 ixgbe_vlan_offload_set(dev, mask);
2086 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2087 /* Enable vlan filtering for VMDq */
2088 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2091 /* Configure DCB hw */
2092 ixgbe_configure_dcb(dev);
2094 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2095 err = ixgbe_fdir_configure(dev);
2100 /* Restore vf rate limit */
2101 if (vfinfo != NULL) {
2102 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2103 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2104 if (vfinfo[vf].tx_rate[idx] != 0)
2105 ixgbe_set_vf_rate_limit(dev, vf,
2106 vfinfo[vf].tx_rate[idx],
2110 ixgbe_restore_statistics_mapping(dev);
2115 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2116 ixgbe_dev_clear_queues(dev);
2121 * Stop device: disable rx and tx functions to allow for reconfiguring.
2124 ixgbe_dev_stop(struct rte_eth_dev *dev)
2126 struct rte_eth_link link;
2127 struct ixgbe_hw *hw =
2128 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2129 struct ixgbe_vf_info *vfinfo =
2130 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2131 struct ixgbe_filter_info *filter_info =
2132 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2133 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2134 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2137 PMD_INIT_FUNC_TRACE();
2139 /* disable interrupts */
2140 ixgbe_disable_intr(hw);
2142 /* disable intr eventfd mapping */
2143 rte_intr_disable(intr_handle);
2146 ixgbe_pf_reset_hw(hw);
2147 hw->adapter_stopped = 0;
2150 ixgbe_stop_adapter(hw);
2152 for (vf = 0; vfinfo != NULL &&
2153 vf < dev->pci_dev->max_vfs; vf++)
2154 vfinfo[vf].clear_to_send = false;
2156 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2157 /* Turn off the copper */
2158 ixgbe_set_phy_power(hw, false);
2160 /* Turn off the laser */
2161 ixgbe_disable_tx_laser(hw);
2164 ixgbe_dev_clear_queues(dev);
2166 /* Clear stored conf */
2167 dev->data->scattered_rx = 0;
2170 /* Clear recorded link status */
2171 memset(&link, 0, sizeof(link));
2172 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2174 /* Remove all ntuple filters of the device */
2175 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2176 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2177 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2178 TAILQ_REMOVE(&filter_info->fivetuple_list,
2182 memset(filter_info->fivetuple_mask, 0,
2183 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2185 /* Clean datapath event and queue/vec mapping */
2186 rte_intr_efd_disable(intr_handle);
2187 if (intr_handle->intr_vec != NULL) {
2188 rte_free(intr_handle->intr_vec);
2189 intr_handle->intr_vec = NULL;
2194 * Set device link up: enable tx.
2197 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2199 struct ixgbe_hw *hw =
2200 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2201 if (hw->mac.type == ixgbe_mac_82599EB) {
2202 #ifdef RTE_NIC_BYPASS
2203 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2204 /* Not suported in bypass mode */
2205 PMD_INIT_LOG(ERR, "Set link up is not supported "
2206 "by device id 0x%x", hw->device_id);
2212 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2213 /* Turn on the copper */
2214 ixgbe_set_phy_power(hw, true);
2216 /* Turn on the laser */
2217 ixgbe_enable_tx_laser(hw);
2224 * Set device link down: disable tx.
2227 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2229 struct ixgbe_hw *hw =
2230 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2231 if (hw->mac.type == ixgbe_mac_82599EB) {
2232 #ifdef RTE_NIC_BYPASS
2233 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2234 /* Not suported in bypass mode */
2235 PMD_INIT_LOG(ERR, "Set link down is not supported "
2236 "by device id 0x%x", hw->device_id);
2242 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2243 /* Turn off the copper */
2244 ixgbe_set_phy_power(hw, false);
2246 /* Turn off the laser */
2247 ixgbe_disable_tx_laser(hw);
2254 * Reest and stop device.
2257 ixgbe_dev_close(struct rte_eth_dev *dev)
2259 struct ixgbe_hw *hw =
2260 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2262 PMD_INIT_FUNC_TRACE();
2264 ixgbe_pf_reset_hw(hw);
2266 ixgbe_dev_stop(dev);
2267 hw->adapter_stopped = 1;
2269 ixgbe_dev_free_queues(dev);
2271 ixgbe_disable_pcie_master(hw);
2273 /* reprogram the RAR[0] in case user changed it. */
2274 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2278 ixgbe_read_stats_registers(struct ixgbe_hw *hw, struct ixgbe_hw_stats
2279 *hw_stats, uint64_t *total_missed_rx,
2280 uint64_t *total_qbrc, uint64_t *total_qprc,
2281 uint64_t *total_qprdc)
2283 uint32_t bprc, lxon, lxoff, total;
2286 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2287 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2288 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2289 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2291 for (i = 0; i < 8; i++) {
2293 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2294 /* global total per queue */
2295 hw_stats->mpc[i] += mp;
2296 /* Running comprehensive total for stats display */
2297 *total_missed_rx += hw_stats->mpc[i];
2298 if (hw->mac.type == ixgbe_mac_82598EB) {
2299 hw_stats->rnbc[i] +=
2300 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2301 hw_stats->pxonrxc[i] +=
2302 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2303 hw_stats->pxoffrxc[i] +=
2304 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2306 hw_stats->pxonrxc[i] +=
2307 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2308 hw_stats->pxoffrxc[i] +=
2309 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2310 hw_stats->pxon2offc[i] +=
2311 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2313 hw_stats->pxontxc[i] +=
2314 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2315 hw_stats->pxofftxc[i] +=
2316 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2318 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2319 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2320 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2321 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2322 hw_stats->qbrc[i] +=
2323 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2324 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2325 hw_stats->qbtc[i] +=
2326 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2327 *total_qprdc += hw_stats->qprdc[i] +=
2328 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2330 *total_qprc += hw_stats->qprc[i];
2331 *total_qbrc += hw_stats->qbrc[i];
2333 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2334 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2335 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2337 /* Note that gprc counts missed packets */
2338 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2340 if (hw->mac.type != ixgbe_mac_82598EB) {
2341 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2342 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2343 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2344 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2345 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2346 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2347 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2348 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2350 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2351 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2352 /* 82598 only has a counter in the high register */
2353 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2354 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2355 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2359 * Workaround: mprc hardware is incorrectly counting
2360 * broadcasts, so for now we subtract those.
2362 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2363 hw_stats->bprc += bprc;
2364 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2365 if (hw->mac.type == ixgbe_mac_82598EB)
2366 hw_stats->mprc -= bprc;
2368 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2369 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2370 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2371 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2372 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2373 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2375 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2376 hw_stats->lxontxc += lxon;
2377 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2378 hw_stats->lxofftxc += lxoff;
2379 total = lxon + lxoff;
2381 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2382 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2383 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2384 hw_stats->gptc -= total;
2385 hw_stats->mptc -= total;
2386 hw_stats->ptc64 -= total;
2387 hw_stats->gotc -= total * ETHER_MIN_LEN;
2389 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2390 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2391 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2392 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2393 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2394 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2395 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2396 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2397 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2398 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2399 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2400 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2401 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2402 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2403 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2404 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2405 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2406 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2407 /* Only read FCOE on 82599 */
2408 if (hw->mac.type != ixgbe_mac_82598EB) {
2409 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2410 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2411 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2412 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2413 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2416 /* Flow Director Stats registers */
2417 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2418 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2422 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2425 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2427 struct ixgbe_hw *hw =
2428 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2429 struct ixgbe_hw_stats *hw_stats =
2430 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2431 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2434 total_missed_rx = 0;
2439 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2440 &total_qprc, &total_qprdc);
2445 /* Fill out the rte_eth_stats statistics structure */
2446 stats->ipackets = total_qprc;
2447 stats->ibytes = total_qbrc;
2448 stats->opackets = hw_stats->gptc;
2449 stats->obytes = hw_stats->gotc;
2451 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2452 stats->q_ipackets[i] = hw_stats->qprc[i];
2453 stats->q_opackets[i] = hw_stats->qptc[i];
2454 stats->q_ibytes[i] = hw_stats->qbrc[i];
2455 stats->q_obytes[i] = hw_stats->qbtc[i];
2456 stats->q_errors[i] = hw_stats->qprdc[i];
2460 stats->ierrors = hw_stats->crcerrs +
2480 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2482 struct ixgbe_hw_stats *stats =
2483 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2485 /* HW registers are cleared on read */
2486 ixgbe_dev_stats_get(dev, NULL);
2488 /* Reset software totals */
2489 memset(stats, 0, sizeof(*stats));
2493 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2496 struct ixgbe_hw *hw =
2497 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2498 struct ixgbe_hw_stats *hw_stats =
2499 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2500 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2501 unsigned i, count = IXGBE_NB_XSTATS;
2506 total_missed_rx = 0;
2511 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2512 &total_qprc, &total_qprdc);
2514 /* If this is a reset xstats is NULL, and we have cleared the
2515 * registers by reading them.
2520 /* Extended stats from ixgbe_hw_stats */
2522 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2523 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2524 rte_ixgbe_stats_strings[i].name);
2525 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2526 rte_ixgbe_stats_strings[i].offset);
2530 /* Per-Q stats, with 8 queues available */
2531 for (i = 0; i < 8; i++) {
2532 snprintf(xstats[count].name, sizeof(xstats[count].name),
2533 "rx_q%u_mbuf_allocation_errors", i);
2534 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2535 offsetof(struct ixgbe_hw_stats, rnbc[i]));
2538 snprintf(xstats[count].name, sizeof(xstats[count].name),
2539 "rx_q%u_missed_packets", i);
2540 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2541 offsetof(struct ixgbe_hw_stats, mpc[i]));
2544 snprintf(xstats[count].name, sizeof(xstats[count].name),
2545 "rx_q%u_xon_priority_packets", i);
2546 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2547 offsetof(struct ixgbe_hw_stats, pxonrxc[i]));
2550 snprintf(xstats[count].name, sizeof(xstats[count].name),
2551 "tx_q%u_xon_priority_packets", i);
2552 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2553 offsetof(struct ixgbe_hw_stats, pxontxc[i]));
2556 snprintf(xstats[count].name, sizeof(xstats[count].name),
2557 "rx_q%u_xoff_priority_packets", i);
2558 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2559 offsetof(struct ixgbe_hw_stats, pxoffrxc[i]));
2562 snprintf(xstats[count].name, sizeof(xstats[count].name),
2563 "tx_q%u_xoff_priority_packets", i);
2564 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2565 offsetof(struct ixgbe_hw_stats, pxofftxc[i]));
2568 snprintf(xstats[count].name, sizeof(xstats[count].name),
2569 "xx_q%u_xon_to_xoff_priority_packets", i);
2570 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2571 offsetof(struct ixgbe_hw_stats, pxon2offc[i]));
2575 for (i = 0; i < 16; i++) {
2576 snprintf(xstats[count].name, sizeof(xstats[count].name),
2577 "rx_q%u_packets", i);
2578 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2579 offsetof(struct ixgbe_hw_stats, qprc[i]));
2582 snprintf(xstats[count].name, sizeof(xstats[count].name),
2584 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2585 offsetof(struct ixgbe_hw_stats, qbrc[i]));
2588 snprintf(xstats[count].name, sizeof(xstats[count].name),
2589 "tx_q%u_packets", i);
2590 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2591 offsetof(struct ixgbe_hw_stats, qptc[i]));
2594 snprintf(xstats[count].name, sizeof(xstats[count].name),
2596 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2597 offsetof(struct ixgbe_hw_stats, qbtc[i]));
2600 snprintf(xstats[count].name, sizeof(xstats[count].name),
2601 "rx_q%u_dropped", i);
2602 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2603 offsetof(struct ixgbe_hw_stats, qprdc[i]));
2611 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2613 struct ixgbe_hw_stats *stats =
2614 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2616 /* HW registers are cleared on read */
2617 ixgbe_dev_xstats_get(dev, NULL, IXGBE_NB_XSTATS);
2619 /* Reset software totals */
2620 memset(stats, 0, sizeof(*stats));
2624 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2626 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2627 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2628 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2630 /* Good Rx packet, include VF loopback */
2631 UPDATE_VF_STAT(IXGBE_VFGPRC,
2632 hw_stats->last_vfgprc, hw_stats->vfgprc);
2634 /* Good Rx octets, include VF loopback */
2635 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2636 hw_stats->last_vfgorc, hw_stats->vfgorc);
2638 /* Good Tx packet, include VF loopback */
2639 UPDATE_VF_STAT(IXGBE_VFGPTC,
2640 hw_stats->last_vfgptc, hw_stats->vfgptc);
2642 /* Good Tx octets, include VF loopback */
2643 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2644 hw_stats->last_vfgotc, hw_stats->vfgotc);
2646 /* Rx Multicst Packet */
2647 UPDATE_VF_STAT(IXGBE_VFMPRC,
2648 hw_stats->last_vfmprc, hw_stats->vfmprc);
2653 stats->ipackets = hw_stats->vfgprc;
2654 stats->ibytes = hw_stats->vfgorc;
2655 stats->opackets = hw_stats->vfgptc;
2656 stats->obytes = hw_stats->vfgotc;
2657 stats->imcasts = hw_stats->vfmprc;
2658 /* stats->imcasts should be removed as imcasts is deprecated */
2662 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2664 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2665 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2667 /* Sync HW register to the last stats */
2668 ixgbevf_dev_stats_get(dev, NULL);
2670 /* reset HW current stats*/
2671 hw_stats->vfgprc = 0;
2672 hw_stats->vfgorc = 0;
2673 hw_stats->vfgptc = 0;
2674 hw_stats->vfgotc = 0;
2675 hw_stats->vfmprc = 0;
2680 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2682 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2684 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2685 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2686 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2687 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2688 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2689 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2690 dev_info->max_vfs = dev->pci_dev->max_vfs;
2691 if (hw->mac.type == ixgbe_mac_82598EB)
2692 dev_info->max_vmdq_pools = ETH_16_POOLS;
2694 dev_info->max_vmdq_pools = ETH_64_POOLS;
2695 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2696 dev_info->rx_offload_capa =
2697 DEV_RX_OFFLOAD_VLAN_STRIP |
2698 DEV_RX_OFFLOAD_IPV4_CKSUM |
2699 DEV_RX_OFFLOAD_UDP_CKSUM |
2700 DEV_RX_OFFLOAD_TCP_CKSUM;
2703 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2706 if ((hw->mac.type == ixgbe_mac_82599EB ||
2707 hw->mac.type == ixgbe_mac_X540) &&
2708 !RTE_ETH_DEV_SRIOV(dev).active)
2709 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2711 dev_info->tx_offload_capa =
2712 DEV_TX_OFFLOAD_VLAN_INSERT |
2713 DEV_TX_OFFLOAD_IPV4_CKSUM |
2714 DEV_TX_OFFLOAD_UDP_CKSUM |
2715 DEV_TX_OFFLOAD_TCP_CKSUM |
2716 DEV_TX_OFFLOAD_SCTP_CKSUM |
2717 DEV_TX_OFFLOAD_TCP_TSO;
2719 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2721 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2722 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2723 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2725 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2729 dev_info->default_txconf = (struct rte_eth_txconf) {
2731 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2732 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2733 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2735 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2736 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2737 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2738 ETH_TXQ_FLAGS_NOOFFLOADS,
2741 dev_info->rx_desc_lim = rx_desc_lim;
2742 dev_info->tx_desc_lim = tx_desc_lim;
2744 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2745 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2746 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2750 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2751 struct rte_eth_dev_info *dev_info)
2753 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2755 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2756 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2757 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2758 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2759 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2760 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2761 dev_info->max_vfs = dev->pci_dev->max_vfs;
2762 if (hw->mac.type == ixgbe_mac_82598EB)
2763 dev_info->max_vmdq_pools = ETH_16_POOLS;
2765 dev_info->max_vmdq_pools = ETH_64_POOLS;
2766 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2767 DEV_RX_OFFLOAD_IPV4_CKSUM |
2768 DEV_RX_OFFLOAD_UDP_CKSUM |
2769 DEV_RX_OFFLOAD_TCP_CKSUM;
2770 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2771 DEV_TX_OFFLOAD_IPV4_CKSUM |
2772 DEV_TX_OFFLOAD_UDP_CKSUM |
2773 DEV_TX_OFFLOAD_TCP_CKSUM |
2774 DEV_TX_OFFLOAD_SCTP_CKSUM |
2775 DEV_TX_OFFLOAD_TCP_TSO;
2777 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2779 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2780 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2781 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2783 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2787 dev_info->default_txconf = (struct rte_eth_txconf) {
2789 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2790 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2791 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2793 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2794 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2795 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2796 ETH_TXQ_FLAGS_NOOFFLOADS,
2799 dev_info->rx_desc_lim = rx_desc_lim;
2800 dev_info->tx_desc_lim = tx_desc_lim;
2803 /* return 0 means link status changed, -1 means not changed */
2805 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2807 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2808 struct rte_eth_link link, old;
2809 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2813 link.link_status = 0;
2814 link.link_speed = 0;
2815 link.link_duplex = 0;
2816 memset(&old, 0, sizeof(old));
2817 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2819 hw->mac.get_link_status = true;
2821 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2822 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2823 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2825 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2828 link.link_speed = ETH_LINK_SPEED_100;
2829 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2830 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2831 if (link.link_status == old.link_status)
2837 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2838 if (link.link_status == old.link_status)
2842 link.link_status = 1;
2843 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2845 switch (link_speed) {
2847 case IXGBE_LINK_SPEED_UNKNOWN:
2848 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2849 link.link_speed = ETH_LINK_SPEED_100;
2852 case IXGBE_LINK_SPEED_100_FULL:
2853 link.link_speed = ETH_LINK_SPEED_100;
2856 case IXGBE_LINK_SPEED_1GB_FULL:
2857 link.link_speed = ETH_LINK_SPEED_1000;
2860 case IXGBE_LINK_SPEED_10GB_FULL:
2861 link.link_speed = ETH_LINK_SPEED_10000;
2864 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2866 if (link.link_status == old.link_status)
2873 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2875 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2878 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2879 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2880 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2884 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2886 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2889 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2890 fctrl &= (~IXGBE_FCTRL_UPE);
2891 if (dev->data->all_multicast == 1)
2892 fctrl |= IXGBE_FCTRL_MPE;
2894 fctrl &= (~IXGBE_FCTRL_MPE);
2895 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2899 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2901 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2904 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2905 fctrl |= IXGBE_FCTRL_MPE;
2906 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2910 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2912 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2915 if (dev->data->promiscuous == 1)
2916 return; /* must remain in all_multicast mode */
2918 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2919 fctrl &= (~IXGBE_FCTRL_MPE);
2920 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2924 * It clears the interrupt causes and enables the interrupt.
2925 * It will be called once only during nic initialized.
2928 * Pointer to struct rte_eth_dev.
2931 * - On success, zero.
2932 * - On failure, a negative value.
2935 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2937 struct ixgbe_interrupt *intr =
2938 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2940 ixgbe_dev_link_status_print(dev);
2941 intr->mask |= IXGBE_EICR_LSC;
2947 * It clears the interrupt causes and enables the interrupt.
2948 * It will be called once only during nic initialized.
2951 * Pointer to struct rte_eth_dev.
2954 * - On success, zero.
2955 * - On failure, a negative value.
2958 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2960 struct ixgbe_interrupt *intr =
2961 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2963 intr->mask |= IXGBE_EICR_RTX_QUEUE;
2969 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2972 * Pointer to struct rte_eth_dev.
2975 * - On success, zero.
2976 * - On failure, a negative value.
2979 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2982 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2983 struct ixgbe_interrupt *intr =
2984 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2986 /* clear all cause mask */
2987 ixgbe_disable_intr(hw);
2989 /* read-on-clear nic registers here */
2990 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2991 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2995 /* set flag for async link update */
2996 if (eicr & IXGBE_EICR_LSC)
2997 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2999 if (eicr & IXGBE_EICR_MAILBOX)
3000 intr->flags |= IXGBE_FLAG_MAILBOX;
3006 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
3009 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3010 struct ixgbe_interrupt *intr =
3011 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3013 /* clear all cause mask */
3014 ixgbevf_intr_disable(hw);
3016 /* read-on-clear nic registers here */
3017 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
3018 PMD_DRV_LOG(INFO, "eicr %x", eicr);
3022 /* set flag for async link update */
3023 if (eicr & IXGBE_EICR_LSC)
3024 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3030 * It gets and then prints the link status.
3033 * Pointer to struct rte_eth_dev.
3036 * - On success, zero.
3037 * - On failure, a negative value.
3040 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3042 struct rte_eth_link link;
3044 memset(&link, 0, sizeof(link));
3045 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3046 if (link.link_status) {
3047 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3048 (int)(dev->data->port_id),
3049 (unsigned)link.link_speed,
3050 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3051 "full-duplex" : "half-duplex");
3053 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3054 (int)(dev->data->port_id));
3056 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3057 dev->pci_dev->addr.domain,
3058 dev->pci_dev->addr.bus,
3059 dev->pci_dev->addr.devid,
3060 dev->pci_dev->addr.function);
3064 * It executes link_update after knowing an interrupt occurred.
3067 * Pointer to struct rte_eth_dev.
3070 * - On success, zero.
3071 * - On failure, a negative value.
3074 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3076 struct ixgbe_interrupt *intr =
3077 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3079 struct rte_eth_link link;
3080 int intr_enable_delay = false;
3082 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3084 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3085 ixgbe_pf_mbx_process(dev);
3086 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3089 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3090 /* get the link status before link update, for predicting later */
3091 memset(&link, 0, sizeof(link));
3092 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3094 ixgbe_dev_link_update(dev, 0);
3097 if (!link.link_status)
3098 /* handle it 1 sec later, wait it being stable */
3099 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3100 /* likely to down */
3102 /* handle it 4 sec later, wait it being stable */
3103 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3105 ixgbe_dev_link_status_print(dev);
3107 intr_enable_delay = true;
3110 if (intr_enable_delay) {
3111 if (rte_eal_alarm_set(timeout * 1000,
3112 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3113 PMD_DRV_LOG(ERR, "Error setting alarm");
3115 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3116 ixgbe_enable_intr(dev);
3117 rte_intr_enable(&(dev->pci_dev->intr_handle));
3125 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
3127 struct ixgbe_hw *hw =
3128 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3130 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3131 ixgbevf_intr_enable(hw);
3132 rte_intr_enable(&dev->pci_dev->intr_handle);
3137 * Interrupt handler which shall be registered for alarm callback for delayed
3138 * handling specific interrupt to wait for the stable nic state. As the
3139 * NIC interrupt state is not stable for ixgbe after link is just down,
3140 * it needs to wait 4 seconds to get the stable status.
3143 * Pointer to interrupt handle.
3145 * The address of parameter (struct rte_eth_dev *) regsitered before.
3151 ixgbe_dev_interrupt_delayed_handler(void *param)
3153 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3154 struct ixgbe_interrupt *intr =
3155 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3156 struct ixgbe_hw *hw =
3157 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3160 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3161 if (eicr & IXGBE_EICR_MAILBOX)
3162 ixgbe_pf_mbx_process(dev);
3164 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3165 ixgbe_dev_link_update(dev, 0);
3166 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3167 ixgbe_dev_link_status_print(dev);
3168 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3171 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3172 ixgbe_enable_intr(dev);
3173 rte_intr_enable(&(dev->pci_dev->intr_handle));
3177 * Interrupt handler triggered by NIC for handling
3178 * specific interrupt.
3181 * Pointer to interrupt handle.
3183 * The address of parameter (struct rte_eth_dev *) regsitered before.
3189 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3192 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3194 ixgbe_dev_interrupt_get_status(dev);
3195 ixgbe_dev_interrupt_action(dev);
3199 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3202 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3204 ixgbevf_dev_interrupt_get_status(dev);
3205 ixgbevf_dev_interrupt_action(dev);
3209 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3211 struct ixgbe_hw *hw;
3213 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3214 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3218 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3220 struct ixgbe_hw *hw;
3222 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3223 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3227 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3229 struct ixgbe_hw *hw;
3235 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3237 fc_conf->pause_time = hw->fc.pause_time;
3238 fc_conf->high_water = hw->fc.high_water[0];
3239 fc_conf->low_water = hw->fc.low_water[0];
3240 fc_conf->send_xon = hw->fc.send_xon;
3241 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3244 * Return rx_pause status according to actual setting of
3247 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3248 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3254 * Return tx_pause status according to actual setting of
3257 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3258 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3263 if (rx_pause && tx_pause)
3264 fc_conf->mode = RTE_FC_FULL;
3266 fc_conf->mode = RTE_FC_RX_PAUSE;
3268 fc_conf->mode = RTE_FC_TX_PAUSE;
3270 fc_conf->mode = RTE_FC_NONE;
3276 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3278 struct ixgbe_hw *hw;
3280 uint32_t rx_buf_size;
3281 uint32_t max_high_water;
3283 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3290 PMD_INIT_FUNC_TRACE();
3292 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3293 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3294 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3297 * At least reserve one Ethernet frame for watermark
3298 * high_water/low_water in kilo bytes for ixgbe
3300 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3301 if ((fc_conf->high_water > max_high_water) ||
3302 (fc_conf->high_water < fc_conf->low_water)) {
3303 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3304 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3308 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3309 hw->fc.pause_time = fc_conf->pause_time;
3310 hw->fc.high_water[0] = fc_conf->high_water;
3311 hw->fc.low_water[0] = fc_conf->low_water;
3312 hw->fc.send_xon = fc_conf->send_xon;
3313 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3315 err = ixgbe_fc_enable(hw);
3317 /* Not negotiated is not an error case */
3318 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3320 /* check if we want to forward MAC frames - driver doesn't have native
3321 * capability to do that, so we'll write the registers ourselves */
3323 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3325 /* set or clear MFLCN.PMCF bit depending on configuration */
3326 if (fc_conf->mac_ctrl_frame_fwd != 0)
3327 mflcn |= IXGBE_MFLCN_PMCF;
3329 mflcn &= ~IXGBE_MFLCN_PMCF;
3331 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3332 IXGBE_WRITE_FLUSH(hw);
3337 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3342 * ixgbe_pfc_enable_generic - Enable flow control
3343 * @hw: pointer to hardware structure
3344 * @tc_num: traffic class number
3345 * Enable flow control according to the current settings.
3348 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3351 uint32_t mflcn_reg, fccfg_reg;
3353 uint32_t fcrtl, fcrth;
3357 /* Validate the water mark configuration */
3358 if (!hw->fc.pause_time) {
3359 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3363 /* Low water mark of zero causes XOFF floods */
3364 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3365 /* High/Low water can not be 0 */
3366 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
3367 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3368 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3372 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3373 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3374 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3378 /* Negotiate the fc mode to use */
3379 ixgbe_fc_autoneg(hw);
3381 /* Disable any previous flow control settings */
3382 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3383 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3385 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3386 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3388 switch (hw->fc.current_mode) {
3391 * If the count of enabled RX Priority Flow control >1,
3392 * and the TX pause can not be disabled
3395 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3396 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3397 if (reg & IXGBE_FCRTH_FCEN)
3401 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3403 case ixgbe_fc_rx_pause:
3405 * Rx Flow control is enabled and Tx Flow control is
3406 * disabled by software override. Since there really
3407 * isn't a way to advertise that we are capable of RX
3408 * Pause ONLY, we will advertise that we support both
3409 * symmetric and asymmetric Rx PAUSE. Later, we will
3410 * disable the adapter's ability to send PAUSE frames.
3412 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3414 * If the count of enabled RX Priority Flow control >1,
3415 * and the TX pause can not be disabled
3418 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3419 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3420 if (reg & IXGBE_FCRTH_FCEN)
3424 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3426 case ixgbe_fc_tx_pause:
3428 * Tx Flow control is enabled, and Rx Flow control is
3429 * disabled by software override.
3431 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3434 /* Flow control (both Rx and Tx) is enabled by SW override. */
3435 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3436 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3439 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3440 ret_val = IXGBE_ERR_CONFIG;
3445 /* Set 802.3x based flow control settings. */
3446 mflcn_reg |= IXGBE_MFLCN_DPF;
3447 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3448 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3450 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3451 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3452 hw->fc.high_water[tc_num]) {
3453 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3454 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3455 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3457 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3459 * In order to prevent Tx hangs when the internal Tx
3460 * switch is enabled we must set the high water mark
3461 * to the maximum FCRTH value. This allows the Tx
3462 * switch to function even under heavy Rx workloads.
3464 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3466 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3468 /* Configure pause time (2 TCs per register) */
3469 reg = hw->fc.pause_time * 0x00010001;
3470 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3471 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3473 /* Configure flow control refresh threshold value */
3474 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3481 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3483 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3484 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3486 if(hw->mac.type != ixgbe_mac_82598EB) {
3487 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3493 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3496 uint32_t rx_buf_size;
3497 uint32_t max_high_water;
3499 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3500 struct ixgbe_hw *hw =
3501 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3502 struct ixgbe_dcb_config *dcb_config =
3503 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3505 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3512 PMD_INIT_FUNC_TRACE();
3514 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3515 tc_num = map[pfc_conf->priority];
3516 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3517 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3519 * At least reserve one Ethernet frame for watermark
3520 * high_water/low_water in kilo bytes for ixgbe
3522 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3523 if ((pfc_conf->fc.high_water > max_high_water) ||
3524 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3525 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3526 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3530 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3531 hw->fc.pause_time = pfc_conf->fc.pause_time;
3532 hw->fc.send_xon = pfc_conf->fc.send_xon;
3533 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
3534 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3536 err = ixgbe_dcb_pfc_enable(dev,tc_num);
3538 /* Not negotiated is not an error case */
3539 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3542 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3547 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3548 struct rte_eth_rss_reta_entry64 *reta_conf,
3553 uint16_t idx, shift;
3554 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3555 uint16_t sp_reta_size;
3558 PMD_INIT_FUNC_TRACE();
3560 if (!ixgbe_rss_update_sp(hw->mac.type)) {
3561 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3566 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3567 if (reta_size != sp_reta_size) {
3568 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3569 "(%d) doesn't match the number hardware can supported "
3570 "(%d)\n", reta_size, sp_reta_size);
3574 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3575 idx = i / RTE_RETA_GROUP_SIZE;
3576 shift = i % RTE_RETA_GROUP_SIZE;
3577 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3581 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3582 if (mask == IXGBE_4_BIT_MASK)
3585 r = IXGBE_READ_REG(hw, reta_reg);
3586 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3587 if (mask & (0x1 << j))
3588 reta |= reta_conf[idx].reta[shift + j] <<
3591 reta |= r & (IXGBE_8_BIT_MASK <<
3594 IXGBE_WRITE_REG(hw, reta_reg, reta);
3601 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3602 struct rte_eth_rss_reta_entry64 *reta_conf,
3607 uint16_t idx, shift;
3608 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3609 uint16_t sp_reta_size;
3612 PMD_INIT_FUNC_TRACE();
3613 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3614 if (reta_size != sp_reta_size) {
3615 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3616 "(%d) doesn't match the number hardware can supported "
3617 "(%d)\n", reta_size, sp_reta_size);
3621 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3622 idx = i / RTE_RETA_GROUP_SIZE;
3623 shift = i % RTE_RETA_GROUP_SIZE;
3624 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3629 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3630 reta = IXGBE_READ_REG(hw, reta_reg);
3631 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3632 if (mask & (0x1 << j))
3633 reta_conf[idx].reta[shift + j] =
3634 ((reta >> (CHAR_BIT * j)) &
3643 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3644 uint32_t index, uint32_t pool)
3646 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3647 uint32_t enable_addr = 1;
3649 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3653 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3655 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3657 ixgbe_clear_rar(hw, index);
3661 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3663 ixgbe_remove_rar(dev, 0);
3665 ixgbe_add_rar(dev, addr, 0, 0);
3669 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3673 struct ixgbe_hw *hw;
3674 struct rte_eth_dev_info dev_info;
3675 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3677 ixgbe_dev_info_get(dev, &dev_info);
3679 /* check that mtu is within the allowed range */
3680 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3683 /* refuse mtu that requires the support of scattered packets when this
3684 * feature has not been enabled before. */
3685 if (!dev->data->scattered_rx &&
3686 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3687 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3690 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3691 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3693 /* switch to jumbo mode if needed */
3694 if (frame_size > ETHER_MAX_LEN) {
3695 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3696 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3698 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3699 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3701 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3703 /* update max frame size */
3704 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3706 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3707 maxfrs &= 0x0000FFFF;
3708 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3709 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3715 * Virtual Function operations
3718 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3720 PMD_INIT_FUNC_TRACE();
3722 /* Clear interrupt mask to stop from interrupts being generated */
3723 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3725 IXGBE_WRITE_FLUSH(hw);
3729 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3731 PMD_INIT_FUNC_TRACE();
3733 /* VF enable interrupt autoclean */
3734 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3735 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3736 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3738 IXGBE_WRITE_FLUSH(hw);
3742 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3744 struct rte_eth_conf* conf = &dev->data->dev_conf;
3745 struct ixgbe_adapter *adapter =
3746 (struct ixgbe_adapter *)dev->data->dev_private;
3748 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3749 dev->data->port_id);
3752 * VF has no ability to enable/disable HW CRC
3753 * Keep the persistent behavior the same as Host PF
3755 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3756 if (!conf->rxmode.hw_strip_crc) {
3757 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3758 conf->rxmode.hw_strip_crc = 1;
3761 if (conf->rxmode.hw_strip_crc) {
3762 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3763 conf->rxmode.hw_strip_crc = 0;
3768 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3769 * allocation or vector Rx preconditions we will reset it.
3771 adapter->rx_bulk_alloc_allowed = true;
3772 adapter->rx_vec_allowed = true;
3778 ixgbevf_dev_start(struct rte_eth_dev *dev)
3780 struct ixgbe_hw *hw =
3781 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3782 uint32_t intr_vector = 0;
3783 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3787 PMD_INIT_FUNC_TRACE();
3789 hw->mac.ops.reset_hw(hw);
3790 hw->mac.get_link_status = true;
3792 /* negotiate mailbox API version to use with the PF. */
3793 ixgbevf_negotiate_api(hw);
3795 ixgbevf_dev_tx_init(dev);
3797 /* This can fail when allocating mbufs for descriptor rings */
3798 err = ixgbevf_dev_rx_init(dev);
3800 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3801 ixgbe_dev_clear_queues(dev);
3806 ixgbevf_set_vfta_all(dev,1);
3809 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3810 ETH_VLAN_EXTEND_MASK;
3811 ixgbevf_vlan_offload_set(dev, mask);
3813 ixgbevf_dev_rxtx_start(dev);
3815 /* check and configure queue intr-vector mapping */
3816 if (dev->data->dev_conf.intr_conf.rxq != 0)
3817 intr_vector = dev->data->nb_rx_queues;
3819 if (rte_intr_efd_enable(intr_handle, intr_vector))
3822 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3823 intr_handle->intr_vec =
3824 rte_zmalloc("intr_vec",
3825 dev->data->nb_rx_queues * sizeof(int), 0);
3826 if (intr_handle->intr_vec == NULL) {
3827 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3828 " intr_vec\n", dev->data->nb_rx_queues);
3832 ixgbevf_configure_msix(dev);
3834 if (dev->data->dev_conf.intr_conf.lsc != 0) {
3835 if (rte_intr_allow_others(intr_handle))
3836 rte_intr_callback_register(intr_handle,
3837 ixgbevf_dev_interrupt_handler,
3840 PMD_INIT_LOG(INFO, "lsc won't enable because of"
3841 " no intr multiplex\n");
3844 rte_intr_enable(intr_handle);
3846 /* Re-enable interrupt for VF */
3847 ixgbevf_intr_enable(hw);
3853 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3855 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3856 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3858 PMD_INIT_FUNC_TRACE();
3860 hw->adapter_stopped = 1;
3861 ixgbe_stop_adapter(hw);
3864 * Clear what we set, but we still keep shadow_vfta to
3865 * restore after device starts
3867 ixgbevf_set_vfta_all(dev,0);
3869 /* Clear stored conf */
3870 dev->data->scattered_rx = 0;
3872 ixgbe_dev_clear_queues(dev);
3874 /* disable intr eventfd mapping */
3875 rte_intr_disable(intr_handle);
3877 /* Clean datapath event and queue/vec mapping */
3878 rte_intr_efd_disable(intr_handle);
3879 if (intr_handle->intr_vec != NULL) {
3880 rte_free(intr_handle->intr_vec);
3881 intr_handle->intr_vec = NULL;
3886 ixgbevf_dev_close(struct rte_eth_dev *dev)
3888 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3889 struct rte_pci_device *pci_dev;
3891 PMD_INIT_FUNC_TRACE();
3895 ixgbevf_dev_stop(dev);
3897 ixgbe_dev_free_queues(dev);
3899 /* reprogram the RAR[0] in case user changed it. */
3900 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3902 pci_dev = dev->pci_dev;
3903 if (pci_dev->intr_handle.intr_vec) {
3904 rte_free(pci_dev->intr_handle.intr_vec);
3905 pci_dev->intr_handle.intr_vec = NULL;
3909 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3911 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3912 struct ixgbe_vfta * shadow_vfta =
3913 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3914 int i = 0, j = 0, vfta = 0, mask = 1;
3916 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3917 vfta = shadow_vfta->vfta[i];
3920 for (j = 0; j < 32; j++){
3922 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3931 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3933 struct ixgbe_hw *hw =
3934 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3935 struct ixgbe_vfta * shadow_vfta =
3936 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3937 uint32_t vid_idx = 0;
3938 uint32_t vid_bit = 0;
3941 PMD_INIT_FUNC_TRACE();
3943 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3944 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3946 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3949 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3950 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3952 /* Save what we set and retore it after device reset */
3954 shadow_vfta->vfta[vid_idx] |= vid_bit;
3956 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3962 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3964 struct ixgbe_hw *hw =
3965 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3968 PMD_INIT_FUNC_TRACE();
3970 if(queue >= hw->mac.max_rx_queues)
3973 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3975 ctrl |= IXGBE_RXDCTL_VME;
3977 ctrl &= ~IXGBE_RXDCTL_VME;
3978 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3980 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3984 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3986 struct ixgbe_hw *hw =
3987 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3991 /* VF function only support hw strip feature, others are not support */
3992 if(mask & ETH_VLAN_STRIP_MASK){
3993 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3995 for(i=0; i < hw->mac.max_rx_queues; i++)
3996 ixgbevf_vlan_strip_queue_set(dev,i,on);
4001 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4005 /* we only need to do this if VMDq is enabled */
4006 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4007 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4008 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4016 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4018 uint32_t vector = 0;
4019 switch (hw->mac.mc_filter_type) {
4020 case 0: /* use bits [47:36] of the address */
4021 vector = ((uc_addr->addr_bytes[4] >> 4) |
4022 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4024 case 1: /* use bits [46:35] of the address */
4025 vector = ((uc_addr->addr_bytes[4] >> 3) |
4026 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4028 case 2: /* use bits [45:34] of the address */
4029 vector = ((uc_addr->addr_bytes[4] >> 2) |
4030 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4032 case 3: /* use bits [43:32] of the address */
4033 vector = ((uc_addr->addr_bytes[4]) |
4034 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4036 default: /* Invalid mc_filter_type */
4040 /* vector can only be 12-bits or boundary will be exceeded */
4046 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4054 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4055 const uint32_t ixgbe_uta_bit_shift = 5;
4056 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4057 const uint32_t bit1 = 0x1;
4059 struct ixgbe_hw *hw =
4060 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4061 struct ixgbe_uta_info *uta_info =
4062 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4064 /* The UTA table only exists on 82599 hardware and newer */
4065 if (hw->mac.type < ixgbe_mac_82599EB)
4068 vector = ixgbe_uta_vector(hw,mac_addr);
4069 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4070 uta_shift = vector & ixgbe_uta_bit_mask;
4072 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4076 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4078 uta_info->uta_in_use++;
4079 reg_val |= (bit1 << uta_shift);
4080 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4082 uta_info->uta_in_use--;
4083 reg_val &= ~(bit1 << uta_shift);
4084 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4087 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4089 if (uta_info->uta_in_use > 0)
4090 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4091 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4093 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4099 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4102 struct ixgbe_hw *hw =
4103 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4104 struct ixgbe_uta_info *uta_info =
4105 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4107 /* The UTA table only exists on 82599 hardware and newer */
4108 if (hw->mac.type < ixgbe_mac_82599EB)
4112 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4113 uta_info->uta_shadow[i] = ~0;
4114 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4117 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4118 uta_info->uta_shadow[i] = 0;
4119 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4127 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4129 uint32_t new_val = orig_val;
4131 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4132 new_val |= IXGBE_VMOLR_AUPE;
4133 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4134 new_val |= IXGBE_VMOLR_ROMPE;
4135 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4136 new_val |= IXGBE_VMOLR_ROPE;
4137 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4138 new_val |= IXGBE_VMOLR_BAM;
4139 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4140 new_val |= IXGBE_VMOLR_MPE;
4146 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4147 uint16_t rx_mask, uint8_t on)
4151 struct ixgbe_hw *hw =
4152 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4153 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4155 if (hw->mac.type == ixgbe_mac_82598EB) {
4156 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4157 " on 82599 hardware and newer");
4160 if (ixgbe_vmdq_mode_check(hw) < 0)
4163 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4170 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4176 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4180 const uint8_t bit1 = 0x1;
4182 struct ixgbe_hw *hw =
4183 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4185 if (ixgbe_vmdq_mode_check(hw) < 0)
4188 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4189 reg = IXGBE_READ_REG(hw, addr);
4197 IXGBE_WRITE_REG(hw, addr,reg);
4203 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4207 const uint8_t bit1 = 0x1;
4209 struct ixgbe_hw *hw =
4210 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4212 if (ixgbe_vmdq_mode_check(hw) < 0)
4215 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4216 reg = IXGBE_READ_REG(hw, addr);
4224 IXGBE_WRITE_REG(hw, addr,reg);
4230 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4231 uint64_t pool_mask, uint8_t vlan_on)
4235 struct ixgbe_hw *hw =
4236 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4238 if (ixgbe_vmdq_mode_check(hw) < 0)
4240 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4241 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4242 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4250 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
4251 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
4252 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
4253 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
4254 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4255 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4256 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4259 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4260 struct rte_eth_mirror_conf *mirror_conf,
4261 uint8_t rule_id, uint8_t on)
4263 uint32_t mr_ctl,vlvf;
4264 uint32_t mp_lsb = 0;
4265 uint32_t mv_msb = 0;
4266 uint32_t mv_lsb = 0;
4267 uint32_t mp_msb = 0;
4270 uint64_t vlan_mask = 0;
4272 const uint8_t pool_mask_offset = 32;
4273 const uint8_t vlan_mask_offset = 32;
4274 const uint8_t dst_pool_offset = 8;
4275 const uint8_t rule_mr_offset = 4;
4276 const uint8_t mirror_rule_mask= 0x0F;
4278 struct ixgbe_mirror_info *mr_info =
4279 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4280 struct ixgbe_hw *hw =
4281 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4282 uint8_t mirror_type = 0;
4284 if (ixgbe_vmdq_mode_check(hw) < 0)
4287 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4290 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4291 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4292 mirror_conf->rule_type);
4296 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4297 mirror_type |= IXGBE_MRCTL_VLME;
4298 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4299 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4300 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4301 /* search vlan id related pool vlan filter index */
4302 reg_index = ixgbe_find_vlvf_slot(hw,
4303 mirror_conf->vlan.vlan_id[i]);
4306 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4307 if ((vlvf & IXGBE_VLVF_VIEN) &&
4308 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4309 mirror_conf->vlan.vlan_id[i]))
4310 vlan_mask |= (1ULL << reg_index);
4317 mv_lsb = vlan_mask & 0xFFFFFFFF;
4318 mv_msb = vlan_mask >> vlan_mask_offset;
4320 mr_info->mr_conf[rule_id].vlan.vlan_mask =
4321 mirror_conf->vlan.vlan_mask;
4322 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4323 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
4324 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4325 mirror_conf->vlan.vlan_id[i];
4330 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4331 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4332 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4337 * if enable pool mirror, write related pool mask register,if disable
4338 * pool mirror, clear PFMRVM register
4340 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4341 mirror_type |= IXGBE_MRCTL_VPME;
4343 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4344 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4345 mr_info->mr_conf[rule_id].pool_mask =
4346 mirror_conf->pool_mask;
4351 mr_info->mr_conf[rule_id].pool_mask = 0;
4354 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4355 mirror_type |= IXGBE_MRCTL_UPME;
4356 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4357 mirror_type |= IXGBE_MRCTL_DPME;
4359 /* read mirror control register and recalculate it */
4360 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4363 mr_ctl |= mirror_type;
4364 mr_ctl &= mirror_rule_mask;
4365 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4367 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4369 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4370 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4372 /* write mirrror control register */
4373 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4375 /* write pool mirrror control register */
4376 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4377 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4378 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4381 /* write VLAN mirrror control register */
4382 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4383 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4384 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4392 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4395 uint32_t lsb_val = 0;
4396 uint32_t msb_val = 0;
4397 const uint8_t rule_mr_offset = 4;
4399 struct ixgbe_hw *hw =
4400 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4401 struct ixgbe_mirror_info *mr_info =
4402 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4404 if (ixgbe_vmdq_mode_check(hw) < 0)
4407 memset(&mr_info->mr_conf[rule_id], 0,
4408 sizeof(struct rte_eth_mirror_conf));
4410 /* clear PFVMCTL register */
4411 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4413 /* clear pool mask register */
4414 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4415 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4417 /* clear vlan mask register */
4418 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4419 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4425 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4428 struct ixgbe_hw *hw =
4429 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4431 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4432 mask |= (1 << queue_id);
4433 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4435 rte_intr_enable(&dev->pci_dev->intr_handle);
4441 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4444 struct ixgbe_hw *hw =
4445 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4447 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4448 mask &= ~(1 << queue_id);
4449 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4455 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4458 struct ixgbe_hw *hw =
4459 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4460 struct ixgbe_interrupt *intr =
4461 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4463 if (queue_id < 16) {
4464 ixgbe_disable_intr(hw);
4465 intr->mask |= (1 << queue_id);
4466 ixgbe_enable_intr(dev);
4467 } else if (queue_id < 32) {
4468 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4469 mask &= (1 << queue_id);
4470 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4471 } else if (queue_id < 64) {
4472 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4473 mask &= (1 << (queue_id - 32));
4474 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4476 rte_intr_enable(&dev->pci_dev->intr_handle);
4482 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4485 struct ixgbe_hw *hw =
4486 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4487 struct ixgbe_interrupt *intr =
4488 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4490 if (queue_id < 16) {
4491 ixgbe_disable_intr(hw);
4492 intr->mask &= ~(1 << queue_id);
4493 ixgbe_enable_intr(dev);
4494 } else if (queue_id < 32) {
4495 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4496 mask &= ~(1 << queue_id);
4497 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4498 } else if (queue_id < 64) {
4499 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4500 mask &= ~(1 << (queue_id - 32));
4501 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4508 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4509 uint8_t queue, uint8_t msix_vector)
4513 if (direction == -1) {
4515 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4516 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4519 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4521 /* rx or tx cause */
4522 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4523 idx = ((16 * (queue & 1)) + (8 * direction));
4524 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4525 tmp &= ~(0xFF << idx);
4526 tmp |= (msix_vector << idx);
4527 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4532 * set the IVAR registers, mapping interrupt causes to vectors
4534 * pointer to ixgbe_hw struct
4536 * 0 for Rx, 1 for Tx, -1 for other causes
4538 * queue to map the corresponding interrupt to
4540 * the vector to map to the corresponding queue
4543 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4544 uint8_t queue, uint8_t msix_vector)
4548 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4549 if (hw->mac.type == ixgbe_mac_82598EB) {
4550 if (direction == -1)
4552 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4553 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4554 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4555 tmp |= (msix_vector << (8 * (queue & 0x3)));
4556 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4557 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4558 (hw->mac.type == ixgbe_mac_X540)) {
4559 if (direction == -1) {
4561 idx = ((queue & 1) * 8);
4562 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4563 tmp &= ~(0xFF << idx);
4564 tmp |= (msix_vector << idx);
4565 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4567 /* rx or tx causes */
4568 idx = ((16 * (queue & 1)) + (8 * direction));
4569 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4570 tmp &= ~(0xFF << idx);
4571 tmp |= (msix_vector << idx);
4572 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4578 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4580 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4581 struct ixgbe_hw *hw =
4582 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4584 uint32_t vector_idx = 0;
4586 /* won't configure msix register if no mapping is done
4587 * between intr vector and event fd.
4589 if (!rte_intr_dp_is_en(intr_handle))
4592 /* Configure all RX queues of VF */
4593 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4594 /* Force all queue use vector 0,
4595 * as IXGBE_VF_MAXMSIVECOTR = 1
4597 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4598 intr_handle->intr_vec[q_idx] = vector_idx;
4601 /* Configure VF Rx queue ivar */
4602 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4606 * Sets up the hardware to properly generate MSI-X interrupts
4608 * board private structure
4611 ixgbe_configure_msix(struct rte_eth_dev *dev)
4613 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4614 struct ixgbe_hw *hw =
4615 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4616 uint32_t queue_id, vec = 0;
4620 /* won't configure msix register if no mapping is done
4621 * between intr vector and event fd
4623 if (!rte_intr_dp_is_en(intr_handle))
4626 /* setup GPIE for MSI-x mode */
4627 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4628 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4629 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4630 /* auto clearing and auto setting corresponding bits in EIMS
4631 * when MSI-X interrupt is triggered
4633 if (hw->mac.type == ixgbe_mac_82598EB) {
4634 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4636 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4637 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4639 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4641 /* Populate the IVAR table and set the ITR values to the
4642 * corresponding register.
4644 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4646 /* by default, 1:1 mapping */
4647 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4648 intr_handle->intr_vec[queue_id] = vec;
4649 if (vec < intr_handle->nb_efd - 1)
4653 switch (hw->mac.type) {
4654 case ixgbe_mac_82598EB:
4655 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4656 intr_handle->max_intr - 1);
4658 case ixgbe_mac_82599EB:
4659 case ixgbe_mac_X540:
4660 ixgbe_set_ivar_map(hw, -1, 1, intr_handle->max_intr - 1);
4665 IXGBE_WRITE_REG(hw, IXGBE_EITR(queue_id),
4666 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4668 /* set up to autoclear timer, and the vectors */
4669 mask = IXGBE_EIMS_ENABLE_MASK;
4670 mask &= ~(IXGBE_EIMS_OTHER |
4671 IXGBE_EIMS_MAILBOX |
4674 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4677 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4678 uint16_t queue_idx, uint16_t tx_rate)
4680 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4681 uint32_t rf_dec, rf_int;
4683 uint16_t link_speed = dev->data->dev_link.link_speed;
4685 if (queue_idx >= hw->mac.max_tx_queues)
4689 /* Calculate the rate factor values to set */
4690 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4691 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4692 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4694 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4695 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4696 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4697 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4703 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4704 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4707 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4708 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4709 IXGBE_MAX_JUMBO_FRAME_SIZE))
4710 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4711 IXGBE_MMW_SIZE_JUMBO_FRAME);
4713 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4714 IXGBE_MMW_SIZE_DEFAULT);
4716 /* Set RTTBCNRC of queue X */
4717 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4718 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4719 IXGBE_WRITE_FLUSH(hw);
4724 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4725 uint16_t tx_rate, uint64_t q_msk)
4727 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4728 struct ixgbe_vf_info *vfinfo =
4729 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4730 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4731 uint32_t queue_stride =
4732 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4733 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4734 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4735 uint16_t total_rate = 0;
4737 if (queue_end >= hw->mac.max_tx_queues)
4740 if (vfinfo != NULL) {
4741 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4744 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4746 total_rate += vfinfo[vf_idx].tx_rate[idx];
4751 /* Store tx_rate for this vf. */
4752 for (idx = 0; idx < nb_q_per_pool; idx++) {
4753 if (((uint64_t)0x1 << idx) & q_msk) {
4754 if (vfinfo[vf].tx_rate[idx] != tx_rate)
4755 vfinfo[vf].tx_rate[idx] = tx_rate;
4756 total_rate += tx_rate;
4760 if (total_rate > dev->data->dev_link.link_speed) {
4762 * Reset stored TX rate of the VF if it causes exceed
4765 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4769 /* Set RTTBCNRC of each queue/pool for vf X */
4770 for (; queue_idx <= queue_end; queue_idx++) {
4772 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4780 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4781 __attribute__((unused)) uint32_t index,
4782 __attribute__((unused)) uint32_t pool)
4784 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4788 * On a 82599 VF, adding again the same MAC addr is not an idempotent
4789 * operation. Trap this case to avoid exhausting the [very limited]
4790 * set of PF resources used to store VF MAC addresses.
4792 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4794 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4797 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4801 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4803 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4804 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4805 struct ether_addr *mac_addr;
4810 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4811 * not support the deletion of a given MAC address.
4812 * Instead, it imposes to delete all MAC addresses, then to add again
4813 * all MAC addresses with the exception of the one to be deleted.
4815 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4818 * Add again all MAC addresses, with the exception of the deleted one
4819 * and of the permanent MAC address.
4821 for (i = 0, mac_addr = dev->data->mac_addrs;
4822 i < hw->mac.num_rar_entries; i++, mac_addr++) {
4823 /* Skip the deleted MAC address */
4826 /* Skip NULL MAC addresses */
4827 if (is_zero_ether_addr(mac_addr))
4829 /* Skip the permanent MAC address */
4830 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4832 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4835 "Adding again MAC address "
4836 "%02x:%02x:%02x:%02x:%02x:%02x failed "
4838 mac_addr->addr_bytes[0],
4839 mac_addr->addr_bytes[1],
4840 mac_addr->addr_bytes[2],
4841 mac_addr->addr_bytes[3],
4842 mac_addr->addr_bytes[4],
4843 mac_addr->addr_bytes[5],
4849 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4851 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4853 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4856 #define MAC_TYPE_FILTER_SUP(type) do {\
4857 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4858 (type) != ixgbe_mac_X550)\
4863 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4864 struct rte_eth_syn_filter *filter,
4867 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4870 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4873 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4876 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4878 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4879 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4881 if (filter->hig_pri)
4882 synqf |= IXGBE_SYN_FILTER_SYNQFP;
4884 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4886 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4888 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4890 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4891 IXGBE_WRITE_FLUSH(hw);
4896 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4897 struct rte_eth_syn_filter *filter)
4899 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4900 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4902 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4903 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4904 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4911 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4912 enum rte_filter_op filter_op,
4915 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4918 MAC_TYPE_FILTER_SUP(hw->mac.type);
4920 if (filter_op == RTE_ETH_FILTER_NOP)
4924 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4929 switch (filter_op) {
4930 case RTE_ETH_FILTER_ADD:
4931 ret = ixgbe_syn_filter_set(dev,
4932 (struct rte_eth_syn_filter *)arg,
4935 case RTE_ETH_FILTER_DELETE:
4936 ret = ixgbe_syn_filter_set(dev,
4937 (struct rte_eth_syn_filter *)arg,
4940 case RTE_ETH_FILTER_GET:
4941 ret = ixgbe_syn_filter_get(dev,
4942 (struct rte_eth_syn_filter *)arg);
4945 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
4954 static inline enum ixgbe_5tuple_protocol
4955 convert_protocol_type(uint8_t protocol_value)
4957 if (protocol_value == IPPROTO_TCP)
4958 return IXGBE_FILTER_PROTOCOL_TCP;
4959 else if (protocol_value == IPPROTO_UDP)
4960 return IXGBE_FILTER_PROTOCOL_UDP;
4961 else if (protocol_value == IPPROTO_SCTP)
4962 return IXGBE_FILTER_PROTOCOL_SCTP;
4964 return IXGBE_FILTER_PROTOCOL_NONE;
4968 * add a 5tuple filter
4971 * dev: Pointer to struct rte_eth_dev.
4972 * index: the index the filter allocates.
4973 * filter: ponter to the filter that will be added.
4974 * rx_queue: the queue id the filter assigned to.
4977 * - On success, zero.
4978 * - On failure, a negative value.
4981 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
4982 struct ixgbe_5tuple_filter *filter)
4984 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4985 struct ixgbe_filter_info *filter_info =
4986 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4988 uint32_t ftqf, sdpqf;
4989 uint32_t l34timir = 0;
4990 uint8_t mask = 0xff;
4993 * look for an unused 5tuple filter index,
4994 * and insert the filter to list.
4996 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
4997 idx = i / (sizeof(uint32_t) * NBBY);
4998 shift = i % (sizeof(uint32_t) * NBBY);
4999 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5000 filter_info->fivetuple_mask[idx] |= 1 << shift;
5002 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5008 if (i >= IXGBE_MAX_FTQF_FILTERS) {
5009 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5013 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5014 IXGBE_SDPQF_DSTPORT_SHIFT);
5015 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5017 ftqf = (uint32_t)(filter->filter_info.proto &
5018 IXGBE_FTQF_PROTOCOL_MASK);
5019 ftqf |= (uint32_t)((filter->filter_info.priority &
5020 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5021 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5022 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5023 if (filter->filter_info.dst_ip_mask == 0)
5024 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5025 if (filter->filter_info.src_port_mask == 0)
5026 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5027 if (filter->filter_info.dst_port_mask == 0)
5028 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5029 if (filter->filter_info.proto_mask == 0)
5030 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5031 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5032 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5033 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5035 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5036 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5037 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5038 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5040 l34timir |= IXGBE_L34T_IMIR_RESERVE;
5041 l34timir |= (uint32_t)(filter->queue <<
5042 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5043 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5048 * remove a 5tuple filter
5051 * dev: Pointer to struct rte_eth_dev.
5052 * filter: the pointer of the filter will be removed.
5055 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5056 struct ixgbe_5tuple_filter *filter)
5058 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5059 struct ixgbe_filter_info *filter_info =
5060 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5061 uint16_t index = filter->index;
5063 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5064 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5065 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5068 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5069 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5070 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5071 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5072 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5076 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5078 struct ixgbe_hw *hw;
5079 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5081 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5083 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5086 /* refuse mtu that requires the support of scattered packets when this
5087 * feature has not been enabled before. */
5088 if (!dev->data->scattered_rx &&
5089 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5090 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5094 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5095 * request of the version 2.0 of the mailbox API.
5096 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5097 * of the mailbox API.
5098 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5099 * prior to 3.11.33 which contains the following change:
5100 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5102 ixgbevf_rlpml_set_vf(hw, max_frame);
5104 /* update max frame size */
5105 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5109 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
5110 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5114 static inline struct ixgbe_5tuple_filter *
5115 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5116 struct ixgbe_5tuple_filter_info *key)
5118 struct ixgbe_5tuple_filter *it;
5120 TAILQ_FOREACH(it, filter_list, entries) {
5121 if (memcmp(key, &it->filter_info,
5122 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5129 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5131 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5132 struct ixgbe_5tuple_filter_info *filter_info)
5134 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5135 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5136 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5139 switch (filter->dst_ip_mask) {
5141 filter_info->dst_ip_mask = 0;
5142 filter_info->dst_ip = filter->dst_ip;
5145 filter_info->dst_ip_mask = 1;
5148 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5152 switch (filter->src_ip_mask) {
5154 filter_info->src_ip_mask = 0;
5155 filter_info->src_ip = filter->src_ip;
5158 filter_info->src_ip_mask = 1;
5161 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5165 switch (filter->dst_port_mask) {
5167 filter_info->dst_port_mask = 0;
5168 filter_info->dst_port = filter->dst_port;
5171 filter_info->dst_port_mask = 1;
5174 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5178 switch (filter->src_port_mask) {
5180 filter_info->src_port_mask = 0;
5181 filter_info->src_port = filter->src_port;
5184 filter_info->src_port_mask = 1;
5187 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5191 switch (filter->proto_mask) {
5193 filter_info->proto_mask = 0;
5194 filter_info->proto =
5195 convert_protocol_type(filter->proto);
5198 filter_info->proto_mask = 1;
5201 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5205 filter_info->priority = (uint8_t)filter->priority;
5210 * add or delete a ntuple filter
5213 * dev: Pointer to struct rte_eth_dev.
5214 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5215 * add: if true, add filter, if false, remove filter
5218 * - On success, zero.
5219 * - On failure, a negative value.
5222 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5223 struct rte_eth_ntuple_filter *ntuple_filter,
5226 struct ixgbe_filter_info *filter_info =
5227 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5228 struct ixgbe_5tuple_filter_info filter_5tuple;
5229 struct ixgbe_5tuple_filter *filter;
5232 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5233 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5237 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5238 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5242 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5244 if (filter != NULL && add) {
5245 PMD_DRV_LOG(ERR, "filter exists.");
5248 if (filter == NULL && !add) {
5249 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5254 filter = rte_zmalloc("ixgbe_5tuple_filter",
5255 sizeof(struct ixgbe_5tuple_filter), 0);
5258 (void)rte_memcpy(&filter->filter_info,
5260 sizeof(struct ixgbe_5tuple_filter_info));
5261 filter->queue = ntuple_filter->queue;
5262 ret = ixgbe_add_5tuple_filter(dev, filter);
5268 ixgbe_remove_5tuple_filter(dev, filter);
5274 * get a ntuple filter
5277 * dev: Pointer to struct rte_eth_dev.
5278 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5281 * - On success, zero.
5282 * - On failure, a negative value.
5285 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5286 struct rte_eth_ntuple_filter *ntuple_filter)
5288 struct ixgbe_filter_info *filter_info =
5289 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5290 struct ixgbe_5tuple_filter_info filter_5tuple;
5291 struct ixgbe_5tuple_filter *filter;
5294 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5295 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5299 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5300 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5304 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5306 if (filter == NULL) {
5307 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5310 ntuple_filter->queue = filter->queue;
5315 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5316 * @dev: pointer to rte_eth_dev structure
5317 * @filter_op:operation will be taken.
5318 * @arg: a pointer to specific structure corresponding to the filter_op
5321 * - On success, zero.
5322 * - On failure, a negative value.
5325 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5326 enum rte_filter_op filter_op,
5329 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5332 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5334 if (filter_op == RTE_ETH_FILTER_NOP)
5338 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5343 switch (filter_op) {
5344 case RTE_ETH_FILTER_ADD:
5345 ret = ixgbe_add_del_ntuple_filter(dev,
5346 (struct rte_eth_ntuple_filter *)arg,
5349 case RTE_ETH_FILTER_DELETE:
5350 ret = ixgbe_add_del_ntuple_filter(dev,
5351 (struct rte_eth_ntuple_filter *)arg,
5354 case RTE_ETH_FILTER_GET:
5355 ret = ixgbe_get_ntuple_filter(dev,
5356 (struct rte_eth_ntuple_filter *)arg);
5359 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5367 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5372 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5373 if (filter_info->ethertype_filters[i] == ethertype &&
5374 (filter_info->ethertype_mask & (1 << i)))
5381 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5386 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5387 if (!(filter_info->ethertype_mask & (1 << i))) {
5388 filter_info->ethertype_mask |= 1 << i;
5389 filter_info->ethertype_filters[i] = ethertype;
5397 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5400 if (idx >= IXGBE_MAX_ETQF_FILTERS)
5402 filter_info->ethertype_mask &= ~(1 << idx);
5403 filter_info->ethertype_filters[idx] = 0;
5408 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5409 struct rte_eth_ethertype_filter *filter,
5412 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5413 struct ixgbe_filter_info *filter_info =
5414 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5419 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5422 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5423 filter->ether_type == ETHER_TYPE_IPv6) {
5424 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5425 " ethertype filter.", filter->ether_type);
5429 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5430 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5433 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5434 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5438 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5439 if (ret >= 0 && add) {
5440 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5441 filter->ether_type);
5444 if (ret < 0 && !add) {
5445 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5446 filter->ether_type);
5451 ret = ixgbe_ethertype_filter_insert(filter_info,
5452 filter->ether_type);
5454 PMD_DRV_LOG(ERR, "ethertype filters are full.");
5457 etqf = IXGBE_ETQF_FILTER_EN;
5458 etqf |= (uint32_t)filter->ether_type;
5459 etqs |= (uint32_t)((filter->queue <<
5460 IXGBE_ETQS_RX_QUEUE_SHIFT) &
5461 IXGBE_ETQS_RX_QUEUE);
5462 etqs |= IXGBE_ETQS_QUEUE_EN;
5464 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5468 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5469 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5470 IXGBE_WRITE_FLUSH(hw);
5476 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5477 struct rte_eth_ethertype_filter *filter)
5479 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5480 struct ixgbe_filter_info *filter_info =
5481 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5482 uint32_t etqf, etqs;
5485 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5487 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5488 filter->ether_type);
5492 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5493 if (etqf & IXGBE_ETQF_FILTER_EN) {
5494 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5495 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5497 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5498 IXGBE_ETQS_RX_QUEUE_SHIFT;
5505 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5506 * @dev: pointer to rte_eth_dev structure
5507 * @filter_op:operation will be taken.
5508 * @arg: a pointer to specific structure corresponding to the filter_op
5511 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5512 enum rte_filter_op filter_op,
5515 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5518 MAC_TYPE_FILTER_SUP(hw->mac.type);
5520 if (filter_op == RTE_ETH_FILTER_NOP)
5524 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5529 switch (filter_op) {
5530 case RTE_ETH_FILTER_ADD:
5531 ret = ixgbe_add_del_ethertype_filter(dev,
5532 (struct rte_eth_ethertype_filter *)arg,
5535 case RTE_ETH_FILTER_DELETE:
5536 ret = ixgbe_add_del_ethertype_filter(dev,
5537 (struct rte_eth_ethertype_filter *)arg,
5540 case RTE_ETH_FILTER_GET:
5541 ret = ixgbe_get_ethertype_filter(dev,
5542 (struct rte_eth_ethertype_filter *)arg);
5545 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5553 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5554 enum rte_filter_type filter_type,
5555 enum rte_filter_op filter_op,
5560 switch (filter_type) {
5561 case RTE_ETH_FILTER_NTUPLE:
5562 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5564 case RTE_ETH_FILTER_ETHERTYPE:
5565 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5567 case RTE_ETH_FILTER_SYN:
5568 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5570 case RTE_ETH_FILTER_FDIR:
5571 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5574 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5583 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5584 u8 **mc_addr_ptr, u32 *vmdq)
5589 mc_addr = *mc_addr_ptr;
5590 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5595 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5596 struct ether_addr *mc_addr_set,
5597 uint32_t nb_mc_addr)
5599 struct ixgbe_hw *hw;
5602 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5603 mc_addr_list = (u8 *)mc_addr_set;
5604 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5605 ixgbe_dev_addr_list_itr, TRUE);
5609 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5611 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5615 /* Enable system time for platforms where it isn't on by default. */
5616 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5617 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5618 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5620 /* Start incrementing the register used to timestamp PTP packets. */
5621 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
5623 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5624 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5626 IXGBE_ETQF_FILTER_EN |
5629 /* Enable timestamping of received PTP packets. */
5630 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5631 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5632 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5634 /* Enable timestamping of transmitted PTP packets. */
5635 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5636 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5637 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5643 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5645 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5648 /* Disable timestamping of transmitted PTP packets. */
5649 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5650 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5651 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5653 /* Disable timestamping of received PTP packets. */
5654 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5655 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5656 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5658 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5659 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5661 /* Stop incrementating the System Time registers. */
5662 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5668 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5669 struct timespec *timestamp,
5670 uint32_t flags __rte_unused)
5672 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5673 uint32_t tsync_rxctl;
5677 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5678 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5681 rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5682 rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
5684 timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
5685 timestamp->tv_nsec = 0;
5691 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5692 struct timespec *timestamp)
5694 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5695 uint32_t tsync_txctl;
5699 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5700 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5703 tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5704 tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
5706 timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
5707 timestamp->tv_nsec = 0;
5713 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5715 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5718 const struct reg_info *reg_group;
5719 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5720 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5722 while ((reg_group = reg_set[g_ind++]))
5723 count += ixgbe_regs_group_count(reg_group);
5729 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5733 const struct reg_info *reg_group;
5735 while ((reg_group = ixgbevf_regs[g_ind++]))
5736 count += ixgbe_regs_group_count(reg_group);
5742 ixgbe_get_regs(struct rte_eth_dev *dev,
5743 struct rte_dev_reg_info *regs)
5745 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5746 uint32_t *data = regs->data;
5749 const struct reg_info *reg_group;
5750 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5751 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5753 /* Support only full register dump */
5754 if ((regs->length == 0) ||
5755 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
5756 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5758 while ((reg_group = reg_set[g_ind++]))
5759 count += ixgbe_read_regs_group(dev, &data[count],
5768 ixgbevf_get_regs(struct rte_eth_dev *dev,
5769 struct rte_dev_reg_info *regs)
5771 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5772 uint32_t *data = regs->data;
5775 const struct reg_info *reg_group;
5777 /* Support only full register dump */
5778 if ((regs->length == 0) ||
5779 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
5780 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5782 while ((reg_group = ixgbevf_regs[g_ind++]))
5783 count += ixgbe_read_regs_group(dev, &data[count],
5792 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
5794 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5796 /* Return unit is byte count */
5797 return hw->eeprom.word_size * 2;
5801 ixgbe_get_eeprom(struct rte_eth_dev *dev,
5802 struct rte_dev_eeprom_info *in_eeprom)
5804 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5805 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5806 uint16_t *data = in_eeprom->data;
5809 first = in_eeprom->offset >> 1;
5810 length = in_eeprom->length >> 1;
5811 if ((first > hw->eeprom.word_size) ||
5812 ((first + length) > hw->eeprom.word_size))
5815 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5817 return eeprom->ops.read_buffer(hw, first, length, data);
5821 ixgbe_set_eeprom(struct rte_eth_dev *dev,
5822 struct rte_dev_eeprom_info *in_eeprom)
5824 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5825 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5826 uint16_t *data = in_eeprom->data;
5829 first = in_eeprom->offset >> 1;
5830 length = in_eeprom->length >> 1;
5831 if ((first > hw->eeprom.word_size) ||
5832 ((first + length) > hw->eeprom.word_size))
5835 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5837 return eeprom->ops.write_buffer(hw, first, length, data);
5841 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
5843 case ixgbe_mac_X550:
5844 case ixgbe_mac_X550EM_x:
5845 return ETH_RSS_RETA_SIZE_512;
5846 case ixgbe_mac_X550_vf:
5847 case ixgbe_mac_X550EM_x_vf:
5848 return ETH_RSS_RETA_SIZE_64;
5850 return ETH_RSS_RETA_SIZE_128;
5855 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
5857 case ixgbe_mac_X550:
5858 case ixgbe_mac_X550EM_x:
5859 if (reta_idx < ETH_RSS_RETA_SIZE_128)
5860 return IXGBE_RETA(reta_idx >> 2);
5862 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
5863 case ixgbe_mac_X550_vf:
5864 case ixgbe_mac_X550EM_x_vf:
5865 return IXGBE_VFRETA(reta_idx >> 2);
5867 return IXGBE_RETA(reta_idx >> 2);
5872 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
5874 case ixgbe_mac_X550_vf:
5875 case ixgbe_mac_X550EM_x_vf:
5876 return IXGBE_VFMRQC;
5883 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
5885 case ixgbe_mac_X550_vf:
5886 case ixgbe_mac_X550EM_x_vf:
5887 return IXGBE_VFRSSRK(i);
5889 return IXGBE_RSSRK(i);
5894 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
5896 case ixgbe_mac_82599_vf:
5897 case ixgbe_mac_X540_vf:
5905 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
5906 struct rte_eth_dcb_info *dcb_info)
5908 struct ixgbe_dcb_config *dcb_config =
5909 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
5910 struct ixgbe_dcb_tc_config *tc;
5913 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
5914 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
5916 dcb_info->nb_tcs = 1;
5918 if (dcb_config->vt_mode) { /* vt is enabled*/
5919 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
5920 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
5921 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
5922 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
5923 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
5924 for (j = 0; j < dcb_info->nb_tcs; j++) {
5925 dcb_info->tc_queue.tc_rxq[i][j].base =
5926 i * dcb_info->nb_tcs + j;
5927 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
5928 dcb_info->tc_queue.tc_txq[i][j].base =
5929 i * dcb_info->nb_tcs + j;
5930 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
5933 } else { /* vt is disabled*/
5934 struct rte_eth_dcb_rx_conf *rx_conf =
5935 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
5936 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
5937 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
5938 if (dcb_info->nb_tcs == ETH_4_TCS) {
5939 for (i = 0; i < dcb_info->nb_tcs; i++) {
5940 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
5941 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
5943 dcb_info->tc_queue.tc_txq[0][0].base = 0;
5944 dcb_info->tc_queue.tc_txq[0][1].base = 64;
5945 dcb_info->tc_queue.tc_txq[0][2].base = 96;
5946 dcb_info->tc_queue.tc_txq[0][3].base = 112;
5947 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
5948 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
5949 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
5950 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
5951 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
5952 for (i = 0; i < dcb_info->nb_tcs; i++) {
5953 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
5954 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
5956 dcb_info->tc_queue.tc_txq[0][0].base = 0;
5957 dcb_info->tc_queue.tc_txq[0][1].base = 32;
5958 dcb_info->tc_queue.tc_txq[0][2].base = 64;
5959 dcb_info->tc_queue.tc_txq[0][3].base = 80;
5960 dcb_info->tc_queue.tc_txq[0][4].base = 96;
5961 dcb_info->tc_queue.tc_txq[0][5].base = 104;
5962 dcb_info->tc_queue.tc_txq[0][6].base = 112;
5963 dcb_info->tc_queue.tc_txq[0][7].base = 120;
5964 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
5965 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
5966 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
5967 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
5968 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
5969 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
5970 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
5971 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
5974 for (i = 0; i < dcb_info->nb_tcs; i++) {
5975 tc = &dcb_config->tc_config[i];
5976 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
5981 static struct rte_driver rte_ixgbe_driver = {
5983 .init = rte_ixgbe_pmd_init,
5986 static struct rte_driver rte_ixgbevf_driver = {
5988 .init = rte_ixgbevf_pmd_init,
5991 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
5992 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);