1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
13 #include <netinet/in.h>
14 #include <rte_string_fns.h>
15 #include <rte_byteorder.h>
16 #include <rte_common.h>
17 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_branch_prediction.h>
25 #include <rte_memory.h>
26 #include <rte_kvargs.h>
28 #include <rte_alarm.h>
29 #include <rte_ether.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
32 #include <rte_malloc.h>
33 #include <rte_random.h>
35 #include <rte_hash_crc.h>
36 #ifdef RTE_LIBRTE_SECURITY
37 #include <rte_security_driver.h>
40 #include "ixgbe_logs.h"
41 #include "base/ixgbe_api.h"
42 #include "base/ixgbe_vf.h"
43 #include "base/ixgbe_common.h"
44 #include "ixgbe_ethdev.h"
45 #include "ixgbe_bypass.h"
46 #include "ixgbe_rxtx.h"
47 #include "base/ixgbe_type.h"
48 #include "base/ixgbe_phy.h"
49 #include "ixgbe_regs.h"
52 * High threshold controlling when to start sending XOFF frames. Must be at
53 * least 8 bytes less than receive packet buffer size. This value is in units
56 #define IXGBE_FC_HI 0x80
59 * Low threshold controlling when to start sending XON frames. This value is
60 * in units of 1024 bytes.
62 #define IXGBE_FC_LO 0x40
64 /* Timer value included in XOFF frames. */
65 #define IXGBE_FC_PAUSE 0x680
67 /*Default value of Max Rx Queue*/
68 #define IXGBE_MAX_RX_QUEUE_NUM 128
70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
71 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
72 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
74 #define IXGBE_MMW_SIZE_DEFAULT 0x4
75 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
76 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
79 * Default values for RX/TX configuration
81 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
82 #define IXGBE_DEFAULT_RX_PTHRESH 8
83 #define IXGBE_DEFAULT_RX_HTHRESH 8
84 #define IXGBE_DEFAULT_RX_WTHRESH 0
86 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
87 #define IXGBE_DEFAULT_TX_PTHRESH 32
88 #define IXGBE_DEFAULT_TX_HTHRESH 0
89 #define IXGBE_DEFAULT_TX_WTHRESH 0
90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
92 /* Bit shift and mask */
93 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
94 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
95 #define IXGBE_8_BIT_WIDTH CHAR_BIT
96 #define IXGBE_8_BIT_MASK UINT8_MAX
98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
102 /* Additional timesync values. */
103 #define NSEC_PER_SEC 1000000000L
104 #define IXGBE_INCVAL_10GB 0x66666666
105 #define IXGBE_INCVAL_1GB 0x40000000
106 #define IXGBE_INCVAL_100 0x50000000
107 #define IXGBE_INCVAL_SHIFT_10GB 28
108 #define IXGBE_INCVAL_SHIFT_1GB 24
109 #define IXGBE_INCVAL_SHIFT_100 21
110 #define IXGBE_INCVAL_SHIFT_82599 7
111 #define IXGBE_INCPER_SHIFT_82599 24
113 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
115 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
117 #define IXGBE_ETAG_ETYPE 0x00005084
118 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
119 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
120 #define IXGBE_RAH_ADTYPE 0x40000000
121 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
122 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
125 #define IXGBE_QDE_STRIP_TAG 0x00000004
126 #define IXGBE_VTEICR_MASK 0x07
128 #define IXGBE_EXVET_VET_EXT_SHIFT 16
129 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK "pflink_fullchk"
133 static const char * const ixgbevf_valid_arguments[] = {
134 IXGBEVF_DEVARG_PFLINK_FULLCHK,
138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
150 static void ixgbe_dev_close(struct rte_eth_dev *dev);
151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
157 int wait_to_complete);
158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
159 struct rte_eth_stats *stats);
160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
161 struct rte_eth_xstat *xstats, unsigned n);
162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
163 struct rte_eth_xstat *xstats, unsigned n);
165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
166 uint64_t *values, unsigned int n);
167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
170 struct rte_eth_xstat_name *xstats_names,
172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
173 struct rte_eth_xstat_name *xstats_names, unsigned limit);
174 static int ixgbe_dev_xstats_get_names_by_id(
175 struct rte_eth_dev *dev,
176 struct rte_eth_xstat_name *xstats_names,
179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
186 struct rte_eth_dev_info *dev_info);
187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
189 struct rte_eth_dev_info *dev_info);
190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
193 uint16_t vlan_id, int on);
194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
195 enum rte_vlan_type vlan_type,
197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
198 uint16_t queue, bool on);
199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
213 struct rte_eth_fc_conf *fc_conf);
214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
215 struct rte_eth_fc_conf *fc_conf);
216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
217 struct rte_eth_pfc_conf *pfc_conf);
218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
219 struct rte_eth_rss_reta_entry64 *reta_conf,
221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
222 struct rte_eth_rss_reta_entry64 *reta_conf,
224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
230 static void ixgbe_dev_interrupt_handler(void *param);
231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
233 static void ixgbe_dev_cancel_link_thread(struct rte_eth_dev *dev);
235 static int ixgbe_add_rar(struct rte_eth_dev *dev,
236 struct rte_ether_addr *mac_addr,
237 uint32_t index, uint32_t pool);
238 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
239 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
240 struct rte_ether_addr *mac_addr);
241 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
242 static bool is_device_supported(struct rte_eth_dev *dev,
243 struct rte_pci_driver *drv);
245 /* For Virtual Function support */
246 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
247 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
248 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
249 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
250 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
251 int wait_to_complete);
252 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
253 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
254 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
255 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
256 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
257 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
258 struct rte_eth_stats *stats);
259 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
260 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
261 uint16_t vlan_id, int on);
262 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
263 uint16_t queue, int on);
264 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
265 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
266 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
267 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
269 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
271 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
272 uint8_t queue, uint8_t msix_vector);
273 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
274 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
275 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
276 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
277 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
279 /* For Eth VMDQ APIs support */
280 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
281 rte_ether_addr * mac_addr, uint8_t on);
282 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
283 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
284 struct rte_eth_mirror_conf *mirror_conf,
285 uint8_t rule_id, uint8_t on);
286 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
288 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
290 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
292 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
293 uint8_t queue, uint8_t msix_vector);
294 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
296 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
297 struct rte_ether_addr *mac_addr,
298 uint32_t index, uint32_t pool);
299 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
300 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
301 struct rte_ether_addr *mac_addr);
302 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
303 struct rte_eth_syn_filter *filter);
304 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
305 enum rte_filter_op filter_op,
307 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
308 struct ixgbe_5tuple_filter *filter);
309 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
310 struct ixgbe_5tuple_filter *filter);
311 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
312 enum rte_filter_op filter_op,
314 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
315 struct rte_eth_ntuple_filter *filter);
316 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
317 enum rte_filter_op filter_op,
319 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
320 struct rte_eth_ethertype_filter *filter);
321 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
322 enum rte_filter_type filter_type,
323 enum rte_filter_op filter_op,
325 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
327 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
328 struct rte_ether_addr *mc_addr_set,
329 uint32_t nb_mc_addr);
330 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
331 struct rte_eth_dcb_info *dcb_info);
333 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
334 static int ixgbe_get_regs(struct rte_eth_dev *dev,
335 struct rte_dev_reg_info *regs);
336 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
337 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
338 struct rte_dev_eeprom_info *eeprom);
339 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
340 struct rte_dev_eeprom_info *eeprom);
342 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
343 struct rte_eth_dev_module_info *modinfo);
344 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
345 struct rte_dev_eeprom_info *info);
347 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
348 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
349 struct rte_dev_reg_info *regs);
351 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
352 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
353 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
354 struct timespec *timestamp,
356 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
357 struct timespec *timestamp);
358 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
359 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
360 struct timespec *timestamp);
361 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
362 const struct timespec *timestamp);
363 static void ixgbevf_dev_interrupt_handler(void *param);
365 static int ixgbe_dev_l2_tunnel_eth_type_conf
366 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
367 static int ixgbe_dev_l2_tunnel_offload_set
368 (struct rte_eth_dev *dev,
369 struct rte_eth_l2_tunnel_conf *l2_tunnel,
372 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
373 enum rte_filter_op filter_op,
376 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
377 struct rte_eth_udp_tunnel *udp_tunnel);
378 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
379 struct rte_eth_udp_tunnel *udp_tunnel);
380 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
381 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
382 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
385 * Define VF Stats MACRO for Non "cleared on read" register
387 #define UPDATE_VF_STAT(reg, last, cur) \
389 uint32_t latest = IXGBE_READ_REG(hw, reg); \
390 cur += (latest - last) & UINT_MAX; \
394 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
396 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
397 u64 new_msb = IXGBE_READ_REG(hw, msb); \
398 u64 latest = ((new_msb << 32) | new_lsb); \
399 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
403 #define IXGBE_SET_HWSTRIP(h, q) do {\
404 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
405 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
406 (h)->bitmap[idx] |= 1 << bit;\
409 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
410 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
411 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
412 (h)->bitmap[idx] &= ~(1 << bit);\
415 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
416 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
417 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
418 (r) = (h)->bitmap[idx] >> bit & 1;\
421 int ixgbe_logtype_init;
422 int ixgbe_logtype_driver;
424 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
425 int ixgbe_logtype_rx;
427 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
428 int ixgbe_logtype_tx;
430 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
431 int ixgbe_logtype_tx_free;
435 * The set of PCI devices this driver supports
437 static const struct rte_pci_id pci_id_ixgbe_map[] = {
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
483 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
484 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
486 #ifdef RTE_LIBRTE_IXGBE_BYPASS
487 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
489 { .vendor_id = 0, /* sentinel */ },
493 * The set of PCI devices this driver supports (for 82599 VF)
495 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
500 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
501 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
502 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
503 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
504 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
505 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
506 { .vendor_id = 0, /* sentinel */ },
509 static const struct rte_eth_desc_lim rx_desc_lim = {
510 .nb_max = IXGBE_MAX_RING_DESC,
511 .nb_min = IXGBE_MIN_RING_DESC,
512 .nb_align = IXGBE_RXD_ALIGN,
515 static const struct rte_eth_desc_lim tx_desc_lim = {
516 .nb_max = IXGBE_MAX_RING_DESC,
517 .nb_min = IXGBE_MIN_RING_DESC,
518 .nb_align = IXGBE_TXD_ALIGN,
519 .nb_seg_max = IXGBE_TX_MAX_SEG,
520 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
523 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
524 .dev_configure = ixgbe_dev_configure,
525 .dev_start = ixgbe_dev_start,
526 .dev_stop = ixgbe_dev_stop,
527 .dev_set_link_up = ixgbe_dev_set_link_up,
528 .dev_set_link_down = ixgbe_dev_set_link_down,
529 .dev_close = ixgbe_dev_close,
530 .dev_reset = ixgbe_dev_reset,
531 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
532 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
533 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
534 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
535 .link_update = ixgbe_dev_link_update,
536 .stats_get = ixgbe_dev_stats_get,
537 .xstats_get = ixgbe_dev_xstats_get,
538 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
539 .stats_reset = ixgbe_dev_stats_reset,
540 .xstats_reset = ixgbe_dev_xstats_reset,
541 .xstats_get_names = ixgbe_dev_xstats_get_names,
542 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
543 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
544 .fw_version_get = ixgbe_fw_version_get,
545 .dev_infos_get = ixgbe_dev_info_get,
546 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
547 .mtu_set = ixgbe_dev_mtu_set,
548 .vlan_filter_set = ixgbe_vlan_filter_set,
549 .vlan_tpid_set = ixgbe_vlan_tpid_set,
550 .vlan_offload_set = ixgbe_vlan_offload_set,
551 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
552 .rx_queue_start = ixgbe_dev_rx_queue_start,
553 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
554 .tx_queue_start = ixgbe_dev_tx_queue_start,
555 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
556 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
557 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
558 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
559 .rx_queue_release = ixgbe_dev_rx_queue_release,
560 .rx_queue_count = ixgbe_dev_rx_queue_count,
561 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
562 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
563 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
564 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
565 .tx_queue_release = ixgbe_dev_tx_queue_release,
566 .dev_led_on = ixgbe_dev_led_on,
567 .dev_led_off = ixgbe_dev_led_off,
568 .flow_ctrl_get = ixgbe_flow_ctrl_get,
569 .flow_ctrl_set = ixgbe_flow_ctrl_set,
570 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
571 .mac_addr_add = ixgbe_add_rar,
572 .mac_addr_remove = ixgbe_remove_rar,
573 .mac_addr_set = ixgbe_set_default_mac_addr,
574 .uc_hash_table_set = ixgbe_uc_hash_table_set,
575 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
576 .mirror_rule_set = ixgbe_mirror_rule_set,
577 .mirror_rule_reset = ixgbe_mirror_rule_reset,
578 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
579 .reta_update = ixgbe_dev_rss_reta_update,
580 .reta_query = ixgbe_dev_rss_reta_query,
581 .rss_hash_update = ixgbe_dev_rss_hash_update,
582 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
583 .filter_ctrl = ixgbe_dev_filter_ctrl,
584 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
585 .rxq_info_get = ixgbe_rxq_info_get,
586 .txq_info_get = ixgbe_txq_info_get,
587 .timesync_enable = ixgbe_timesync_enable,
588 .timesync_disable = ixgbe_timesync_disable,
589 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
590 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
591 .get_reg = ixgbe_get_regs,
592 .get_eeprom_length = ixgbe_get_eeprom_length,
593 .get_eeprom = ixgbe_get_eeprom,
594 .set_eeprom = ixgbe_set_eeprom,
595 .get_module_info = ixgbe_get_module_info,
596 .get_module_eeprom = ixgbe_get_module_eeprom,
597 .get_dcb_info = ixgbe_dev_get_dcb_info,
598 .timesync_adjust_time = ixgbe_timesync_adjust_time,
599 .timesync_read_time = ixgbe_timesync_read_time,
600 .timesync_write_time = ixgbe_timesync_write_time,
601 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
602 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
603 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
604 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
605 .tm_ops_get = ixgbe_tm_ops_get,
606 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup,
610 * dev_ops for virtual function, bare necessities for basic vf
611 * operation have been implemented
613 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
614 .dev_configure = ixgbevf_dev_configure,
615 .dev_start = ixgbevf_dev_start,
616 .dev_stop = ixgbevf_dev_stop,
617 .link_update = ixgbevf_dev_link_update,
618 .stats_get = ixgbevf_dev_stats_get,
619 .xstats_get = ixgbevf_dev_xstats_get,
620 .stats_reset = ixgbevf_dev_stats_reset,
621 .xstats_reset = ixgbevf_dev_stats_reset,
622 .xstats_get_names = ixgbevf_dev_xstats_get_names,
623 .dev_close = ixgbevf_dev_close,
624 .dev_reset = ixgbevf_dev_reset,
625 .promiscuous_enable = ixgbevf_dev_promiscuous_enable,
626 .promiscuous_disable = ixgbevf_dev_promiscuous_disable,
627 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
628 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
629 .dev_infos_get = ixgbevf_dev_info_get,
630 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
631 .mtu_set = ixgbevf_dev_set_mtu,
632 .vlan_filter_set = ixgbevf_vlan_filter_set,
633 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
634 .vlan_offload_set = ixgbevf_vlan_offload_set,
635 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
636 .rx_queue_release = ixgbe_dev_rx_queue_release,
637 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
638 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
639 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
640 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
641 .tx_queue_release = ixgbe_dev_tx_queue_release,
642 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
643 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
644 .mac_addr_add = ixgbevf_add_mac_addr,
645 .mac_addr_remove = ixgbevf_remove_mac_addr,
646 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
647 .rxq_info_get = ixgbe_rxq_info_get,
648 .txq_info_get = ixgbe_txq_info_get,
649 .mac_addr_set = ixgbevf_set_default_mac_addr,
650 .get_reg = ixgbevf_get_regs,
651 .reta_update = ixgbe_dev_rss_reta_update,
652 .reta_query = ixgbe_dev_rss_reta_query,
653 .rss_hash_update = ixgbe_dev_rss_hash_update,
654 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
655 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup,
658 /* store statistics names and its offset in stats structure */
659 struct rte_ixgbe_xstats_name_off {
660 char name[RTE_ETH_XSTATS_NAME_SIZE];
664 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
665 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
666 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
667 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
668 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
669 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
670 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
671 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
672 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
673 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
674 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
675 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
676 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
677 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
678 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
679 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
681 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
683 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
684 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
685 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
686 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
687 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
688 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
689 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
690 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
691 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
692 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
693 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
694 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
695 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
696 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
697 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
698 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
699 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
701 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
703 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
704 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
705 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
706 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
708 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
710 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
712 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
714 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
716 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
718 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
721 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
722 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
723 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
725 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
726 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
727 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
728 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
729 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
731 {"rx_fcoe_no_direct_data_placement_ext_buff",
732 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
734 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
736 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
738 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
740 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
742 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
745 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
746 sizeof(rte_ixgbe_stats_strings[0]))
748 /* MACsec statistics */
749 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
750 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
752 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
753 out_pkts_encrypted)},
754 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
755 out_pkts_protected)},
756 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
757 out_octets_encrypted)},
758 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
759 out_octets_protected)},
760 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
762 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
764 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
766 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
767 in_pkts_unknownsci)},
768 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
769 in_octets_decrypted)},
770 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
771 in_octets_validated)},
772 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
774 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
776 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
778 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
780 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
782 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
784 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
786 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
787 in_pkts_notusingsa)},
790 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
791 sizeof(rte_ixgbe_macsec_strings[0]))
793 /* Per-queue statistics */
794 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
795 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
796 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
797 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
798 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
801 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
802 sizeof(rte_ixgbe_rxq_strings[0]))
803 #define IXGBE_NB_RXQ_PRIO_VALUES 8
805 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
806 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
807 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
808 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
812 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
813 sizeof(rte_ixgbe_txq_strings[0]))
814 #define IXGBE_NB_TXQ_PRIO_VALUES 8
816 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
817 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
820 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
821 sizeof(rte_ixgbevf_stats_strings[0]))
824 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
827 ixgbe_is_sfp(struct ixgbe_hw *hw)
829 switch (hw->phy.type) {
830 case ixgbe_phy_sfp_avago:
831 case ixgbe_phy_sfp_ftl:
832 case ixgbe_phy_sfp_intel:
833 case ixgbe_phy_sfp_unknown:
834 case ixgbe_phy_sfp_passive_tyco:
835 case ixgbe_phy_sfp_passive_unknown:
842 static inline int32_t
843 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
848 status = ixgbe_reset_hw(hw);
850 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
851 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
852 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
853 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
854 IXGBE_WRITE_FLUSH(hw);
856 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
857 status = IXGBE_SUCCESS;
862 ixgbe_enable_intr(struct rte_eth_dev *dev)
864 struct ixgbe_interrupt *intr =
865 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
866 struct ixgbe_hw *hw =
867 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
869 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
870 IXGBE_WRITE_FLUSH(hw);
874 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
877 ixgbe_disable_intr(struct ixgbe_hw *hw)
879 PMD_INIT_FUNC_TRACE();
881 if (hw->mac.type == ixgbe_mac_82598EB) {
882 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
884 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
885 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
886 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
888 IXGBE_WRITE_FLUSH(hw);
892 * This function resets queue statistics mapping registers.
893 * From Niantic datasheet, Initialization of Statistics section:
894 * "...if software requires the queue counters, the RQSMR and TQSM registers
895 * must be re-programmed following a device reset.
898 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
902 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
903 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
904 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
910 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
915 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
916 #define NB_QMAP_FIELDS_PER_QSM_REG 4
917 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
919 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
920 struct ixgbe_stat_mapping_registers *stat_mappings =
921 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
922 uint32_t qsmr_mask = 0;
923 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
927 if ((hw->mac.type != ixgbe_mac_82599EB) &&
928 (hw->mac.type != ixgbe_mac_X540) &&
929 (hw->mac.type != ixgbe_mac_X550) &&
930 (hw->mac.type != ixgbe_mac_X550EM_x) &&
931 (hw->mac.type != ixgbe_mac_X550EM_a))
934 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
935 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
938 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
939 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
940 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
943 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
945 /* Now clear any previous stat_idx set */
946 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
948 stat_mappings->tqsm[n] &= ~clearing_mask;
950 stat_mappings->rqsmr[n] &= ~clearing_mask;
952 q_map = (uint32_t)stat_idx;
953 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
954 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
956 stat_mappings->tqsm[n] |= qsmr_mask;
958 stat_mappings->rqsmr[n] |= qsmr_mask;
960 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
961 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
963 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
964 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
966 /* Now write the mapping in the appropriate register */
968 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
969 stat_mappings->rqsmr[n], n);
970 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
972 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
973 stat_mappings->tqsm[n], n);
974 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
980 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
982 struct ixgbe_stat_mapping_registers *stat_mappings =
983 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
984 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
987 /* write whatever was in stat mapping table to the NIC */
988 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
990 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
993 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
998 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1001 struct ixgbe_dcb_tc_config *tc;
1002 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1004 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1005 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1006 for (i = 0; i < dcb_max_tc; i++) {
1007 tc = &dcb_config->tc_config[i];
1008 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1009 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1010 (uint8_t)(100/dcb_max_tc + (i & 1));
1011 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1012 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1013 (uint8_t)(100/dcb_max_tc + (i & 1));
1014 tc->pfc = ixgbe_dcb_pfc_disabled;
1017 /* Initialize default user to priority mapping, UPx->TC0 */
1018 tc = &dcb_config->tc_config[0];
1019 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1020 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1021 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1022 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1023 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1025 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1026 dcb_config->pfc_mode_enable = false;
1027 dcb_config->vt_mode = true;
1028 dcb_config->round_robin_enable = false;
1029 /* support all DCB capabilities in 82599 */
1030 dcb_config->support.capabilities = 0xFF;
1032 /*we only support 4 Tcs for X540, X550 */
1033 if (hw->mac.type == ixgbe_mac_X540 ||
1034 hw->mac.type == ixgbe_mac_X550 ||
1035 hw->mac.type == ixgbe_mac_X550EM_x ||
1036 hw->mac.type == ixgbe_mac_X550EM_a) {
1037 dcb_config->num_tcs.pg_tcs = 4;
1038 dcb_config->num_tcs.pfc_tcs = 4;
1043 * Ensure that all locks are released before first NVM or PHY access
1046 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1051 * Phy lock should not fail in this early stage. If this is the case,
1052 * it is due to an improper exit of the application.
1053 * So force the release of the faulty lock. Release of common lock
1054 * is done automatically by swfw_sync function.
1056 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1057 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1058 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1060 ixgbe_release_swfw_semaphore(hw, mask);
1063 * These ones are more tricky since they are common to all ports; but
1064 * swfw_sync retries last long enough (1s) to be almost sure that if
1065 * lock can not be taken it is due to an improper lock of the
1068 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1069 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1070 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1072 ixgbe_release_swfw_semaphore(hw, mask);
1076 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1077 * It returns 0 on success.
1080 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1082 struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1083 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1084 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1085 struct ixgbe_hw *hw =
1086 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1087 struct ixgbe_vfta *shadow_vfta =
1088 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1089 struct ixgbe_hwstrip *hwstrip =
1090 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1091 struct ixgbe_dcb_config *dcb_config =
1092 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1093 struct ixgbe_filter_info *filter_info =
1094 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1095 struct ixgbe_bw_conf *bw_conf =
1096 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1101 PMD_INIT_FUNC_TRACE();
1103 ixgbe_dev_macsec_setting_reset(eth_dev);
1105 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1106 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1107 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1108 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1111 * For secondary processes, we don't initialise any further as primary
1112 * has already done this work. Only check we don't need a different
1113 * RX and TX function.
1115 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1116 struct ixgbe_tx_queue *txq;
1117 /* TX queue function in primary, set by last queue initialized
1118 * Tx queue may not initialized by primary process
1120 if (eth_dev->data->tx_queues) {
1121 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1122 ixgbe_set_tx_function(eth_dev, txq);
1124 /* Use default TX function if we get here */
1125 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1126 "Using default TX function.");
1129 ixgbe_set_rx_function(eth_dev);
1134 rte_atomic32_clear(&ad->link_thread_running);
1135 rte_eth_copy_pci_info(eth_dev, pci_dev);
1137 /* Vendor and Device ID need to be set before init of shared code */
1138 hw->device_id = pci_dev->id.device_id;
1139 hw->vendor_id = pci_dev->id.vendor_id;
1140 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1141 hw->allow_unsupported_sfp = 1;
1143 /* Initialize the shared code (base driver) */
1144 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1145 diag = ixgbe_bypass_init_shared_code(hw);
1147 diag = ixgbe_init_shared_code(hw);
1148 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1150 if (diag != IXGBE_SUCCESS) {
1151 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1155 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1156 PMD_INIT_LOG(ERR, "\nERROR: "
1157 "Firmware recovery mode detected. Limiting functionality.\n"
1158 "Refer to the Intel(R) Ethernet Adapters and Devices "
1159 "User Guide for details on firmware recovery mode.");
1163 /* pick up the PCI bus settings for reporting later */
1164 ixgbe_get_bus_info(hw);
1166 /* Unlock any pending hardware semaphore */
1167 ixgbe_swfw_lock_reset(hw);
1169 #ifdef RTE_LIBRTE_SECURITY
1170 /* Initialize security_ctx only for primary process*/
1171 if (ixgbe_ipsec_ctx_create(eth_dev))
1175 /* Initialize DCB configuration*/
1176 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1177 ixgbe_dcb_init(hw, dcb_config);
1178 /* Get Hardware Flow Control setting */
1179 hw->fc.requested_mode = ixgbe_fc_none;
1180 hw->fc.current_mode = ixgbe_fc_none;
1181 hw->fc.pause_time = IXGBE_FC_PAUSE;
1182 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1183 hw->fc.low_water[i] = IXGBE_FC_LO;
1184 hw->fc.high_water[i] = IXGBE_FC_HI;
1186 hw->fc.send_xon = 1;
1188 /* Make sure we have a good EEPROM before we read from it */
1189 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1190 if (diag != IXGBE_SUCCESS) {
1191 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1195 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1196 diag = ixgbe_bypass_init_hw(hw);
1198 diag = ixgbe_init_hw(hw);
1199 hw->mac.autotry_restart = false;
1200 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1203 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1204 * is called too soon after the kernel driver unbinding/binding occurs.
1205 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1206 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1207 * also called. See ixgbe_identify_phy_82599(). The reason for the
1208 * failure is not known, and only occuts when virtualisation features
1209 * are disabled in the bios. A delay of 100ms was found to be enough by
1210 * trial-and-error, and is doubled to be safe.
1212 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1214 diag = ixgbe_init_hw(hw);
1217 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1218 diag = IXGBE_SUCCESS;
1220 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1221 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1222 "LOM. Please be aware there may be issues associated "
1223 "with your hardware.");
1224 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1225 "please contact your Intel or hardware representative "
1226 "who provided you with this hardware.");
1227 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1228 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1230 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1234 /* Reset the hw statistics */
1235 ixgbe_dev_stats_reset(eth_dev);
1237 /* disable interrupt */
1238 ixgbe_disable_intr(hw);
1240 /* reset mappings for queue statistics hw counters*/
1241 ixgbe_reset_qstat_mappings(hw);
1243 /* Allocate memory for storing MAC addresses */
1244 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1245 hw->mac.num_rar_entries, 0);
1246 if (eth_dev->data->mac_addrs == NULL) {
1248 "Failed to allocate %u bytes needed to store "
1250 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1253 /* Copy the permanent MAC address */
1254 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1255 ð_dev->data->mac_addrs[0]);
1257 /* Allocate memory for storing hash filter MAC addresses */
1258 eth_dev->data->hash_mac_addrs = rte_zmalloc(
1259 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1260 if (eth_dev->data->hash_mac_addrs == NULL) {
1262 "Failed to allocate %d bytes needed to store MAC addresses",
1263 RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1267 /* Pass the information to the rte_eth_dev_close() that it should also
1268 * release the private port resources.
1270 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1272 /* initialize the vfta */
1273 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1275 /* initialize the hw strip bitmap*/
1276 memset(hwstrip, 0, sizeof(*hwstrip));
1278 /* initialize PF if max_vfs not zero */
1279 ixgbe_pf_host_init(eth_dev);
1281 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1282 /* let hardware know driver is loaded */
1283 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1284 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1285 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1286 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1287 IXGBE_WRITE_FLUSH(hw);
1289 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1290 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1291 (int) hw->mac.type, (int) hw->phy.type,
1292 (int) hw->phy.sfp_type);
1294 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1295 (int) hw->mac.type, (int) hw->phy.type);
1297 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1298 eth_dev->data->port_id, pci_dev->id.vendor_id,
1299 pci_dev->id.device_id);
1301 rte_intr_callback_register(intr_handle,
1302 ixgbe_dev_interrupt_handler, eth_dev);
1304 /* enable uio/vfio intr/eventfd mapping */
1305 rte_intr_enable(intr_handle);
1307 /* enable support intr */
1308 ixgbe_enable_intr(eth_dev);
1310 ixgbe_dev_set_link_down(eth_dev);
1312 /* initialize filter info */
1313 memset(filter_info, 0,
1314 sizeof(struct ixgbe_filter_info));
1316 /* initialize 5tuple filter list */
1317 TAILQ_INIT(&filter_info->fivetuple_list);
1319 /* initialize flow director filter list & hash */
1320 ixgbe_fdir_filter_init(eth_dev);
1322 /* initialize l2 tunnel filter list & hash */
1323 ixgbe_l2_tn_filter_init(eth_dev);
1325 /* initialize flow filter lists */
1326 ixgbe_filterlist_init();
1328 /* initialize bandwidth configuration info */
1329 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1331 /* initialize Traffic Manager configuration */
1332 ixgbe_tm_conf_init(eth_dev);
1338 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1340 PMD_INIT_FUNC_TRACE();
1342 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1345 ixgbe_dev_close(eth_dev);
1350 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1352 struct ixgbe_filter_info *filter_info =
1353 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1354 struct ixgbe_5tuple_filter *p_5tuple;
1356 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1357 TAILQ_REMOVE(&filter_info->fivetuple_list,
1362 memset(filter_info->fivetuple_mask, 0,
1363 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1368 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1370 struct ixgbe_hw_fdir_info *fdir_info =
1371 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1372 struct ixgbe_fdir_filter *fdir_filter;
1374 if (fdir_info->hash_map)
1375 rte_free(fdir_info->hash_map);
1376 if (fdir_info->hash_handle)
1377 rte_hash_free(fdir_info->hash_handle);
1379 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1380 TAILQ_REMOVE(&fdir_info->fdir_list,
1383 rte_free(fdir_filter);
1389 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1391 struct ixgbe_l2_tn_info *l2_tn_info =
1392 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1393 struct ixgbe_l2_tn_filter *l2_tn_filter;
1395 if (l2_tn_info->hash_map)
1396 rte_free(l2_tn_info->hash_map);
1397 if (l2_tn_info->hash_handle)
1398 rte_hash_free(l2_tn_info->hash_handle);
1400 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1401 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1404 rte_free(l2_tn_filter);
1410 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1412 struct ixgbe_hw_fdir_info *fdir_info =
1413 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1414 char fdir_hash_name[RTE_HASH_NAMESIZE];
1415 struct rte_hash_parameters fdir_hash_params = {
1416 .name = fdir_hash_name,
1417 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1418 .key_len = sizeof(union ixgbe_atr_input),
1419 .hash_func = rte_hash_crc,
1420 .hash_func_init_val = 0,
1421 .socket_id = rte_socket_id(),
1424 TAILQ_INIT(&fdir_info->fdir_list);
1425 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1426 "fdir_%s", eth_dev->device->name);
1427 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1428 if (!fdir_info->hash_handle) {
1429 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1432 fdir_info->hash_map = rte_zmalloc("ixgbe",
1433 sizeof(struct ixgbe_fdir_filter *) *
1434 IXGBE_MAX_FDIR_FILTER_NUM,
1436 if (!fdir_info->hash_map) {
1438 "Failed to allocate memory for fdir hash map!");
1441 fdir_info->mask_added = FALSE;
1446 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1448 struct ixgbe_l2_tn_info *l2_tn_info =
1449 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1450 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1451 struct rte_hash_parameters l2_tn_hash_params = {
1452 .name = l2_tn_hash_name,
1453 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1454 .key_len = sizeof(struct ixgbe_l2_tn_key),
1455 .hash_func = rte_hash_crc,
1456 .hash_func_init_val = 0,
1457 .socket_id = rte_socket_id(),
1460 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1461 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1462 "l2_tn_%s", eth_dev->device->name);
1463 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1464 if (!l2_tn_info->hash_handle) {
1465 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1468 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1469 sizeof(struct ixgbe_l2_tn_filter *) *
1470 IXGBE_MAX_L2_TN_FILTER_NUM,
1472 if (!l2_tn_info->hash_map) {
1474 "Failed to allocate memory for L2 TN hash map!");
1477 l2_tn_info->e_tag_en = FALSE;
1478 l2_tn_info->e_tag_fwd_en = FALSE;
1479 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1484 * Negotiate mailbox API version with the PF.
1485 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1486 * Then we try to negotiate starting with the most recent one.
1487 * If all negotiation attempts fail, then we will proceed with
1488 * the default one (ixgbe_mbox_api_10).
1491 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1495 /* start with highest supported, proceed down */
1496 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1504 i != RTE_DIM(sup_ver) &&
1505 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1511 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1515 /* Set Organizationally Unique Identifier (OUI) prefix. */
1516 mac_addr->addr_bytes[0] = 0x00;
1517 mac_addr->addr_bytes[1] = 0x09;
1518 mac_addr->addr_bytes[2] = 0xC0;
1519 /* Force indication of locally assigned MAC address. */
1520 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1521 /* Generate the last 3 bytes of the MAC address with a random number. */
1522 random = rte_rand();
1523 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1527 devarg_handle_int(__rte_unused const char *key, const char *value,
1530 uint16_t *n = extra_args;
1532 if (value == NULL || extra_args == NULL)
1535 *n = (uint16_t)strtoul(value, NULL, 0);
1536 if (*n == USHRT_MAX && errno == ERANGE)
1543 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1544 struct rte_devargs *devargs)
1546 struct rte_kvargs *kvlist;
1547 uint16_t pflink_fullchk;
1549 if (devargs == NULL)
1552 kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1556 if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1557 rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1558 devarg_handle_int, &pflink_fullchk) == 0 &&
1559 pflink_fullchk == 1)
1560 adapter->pflink_fullchk = 1;
1562 rte_kvargs_free(kvlist);
1566 * Virtual Function device init
1569 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1573 struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1574 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1575 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1576 struct ixgbe_hw *hw =
1577 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1578 struct ixgbe_vfta *shadow_vfta =
1579 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1580 struct ixgbe_hwstrip *hwstrip =
1581 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1582 struct rte_ether_addr *perm_addr =
1583 (struct rte_ether_addr *)hw->mac.perm_addr;
1585 PMD_INIT_FUNC_TRACE();
1587 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1588 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1589 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1591 /* for secondary processes, we don't initialise any further as primary
1592 * has already done this work. Only check we don't need a different
1595 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1596 struct ixgbe_tx_queue *txq;
1597 /* TX queue function in primary, set by last queue initialized
1598 * Tx queue may not initialized by primary process
1600 if (eth_dev->data->tx_queues) {
1601 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1602 ixgbe_set_tx_function(eth_dev, txq);
1604 /* Use default TX function if we get here */
1605 PMD_INIT_LOG(NOTICE,
1606 "No TX queues configured yet. Using default TX function.");
1609 ixgbe_set_rx_function(eth_dev);
1614 rte_atomic32_clear(&ad->link_thread_running);
1615 ixgbevf_parse_devargs(eth_dev->data->dev_private,
1616 pci_dev->device.devargs);
1618 rte_eth_copy_pci_info(eth_dev, pci_dev);
1620 hw->device_id = pci_dev->id.device_id;
1621 hw->vendor_id = pci_dev->id.vendor_id;
1622 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1624 /* initialize the vfta */
1625 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1627 /* initialize the hw strip bitmap*/
1628 memset(hwstrip, 0, sizeof(*hwstrip));
1630 /* Initialize the shared code (base driver) */
1631 diag = ixgbe_init_shared_code(hw);
1632 if (diag != IXGBE_SUCCESS) {
1633 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1637 /* init_mailbox_params */
1638 hw->mbx.ops.init_params(hw);
1640 /* Reset the hw statistics */
1641 ixgbevf_dev_stats_reset(eth_dev);
1643 /* Disable the interrupts for VF */
1644 ixgbevf_intr_disable(eth_dev);
1646 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1647 diag = hw->mac.ops.reset_hw(hw);
1650 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1651 * the underlying PF driver has not assigned a MAC address to the VF.
1652 * In this case, assign a random MAC address.
1654 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1655 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1657 * This error code will be propagated to the app by
1658 * rte_eth_dev_reset, so use a public error code rather than
1659 * the internal-only IXGBE_ERR_RESET_FAILED
1664 /* negotiate mailbox API version to use with the PF. */
1665 ixgbevf_negotiate_api(hw);
1667 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1668 ixgbevf_get_queues(hw, &tcs, &tc);
1670 /* Allocate memory for storing MAC addresses */
1671 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1672 hw->mac.num_rar_entries, 0);
1673 if (eth_dev->data->mac_addrs == NULL) {
1675 "Failed to allocate %u bytes needed to store "
1677 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1681 /* Pass the information to the rte_eth_dev_close() that it should also
1682 * release the private port resources.
1684 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1686 /* Generate a random MAC address, if none was assigned by PF. */
1687 if (rte_is_zero_ether_addr(perm_addr)) {
1688 generate_random_mac_addr(perm_addr);
1689 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1691 rte_free(eth_dev->data->mac_addrs);
1692 eth_dev->data->mac_addrs = NULL;
1695 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1696 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1697 "%02x:%02x:%02x:%02x:%02x:%02x",
1698 perm_addr->addr_bytes[0],
1699 perm_addr->addr_bytes[1],
1700 perm_addr->addr_bytes[2],
1701 perm_addr->addr_bytes[3],
1702 perm_addr->addr_bytes[4],
1703 perm_addr->addr_bytes[5]);
1706 /* Copy the permanent MAC address */
1707 rte_ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1709 /* reset the hardware with the new settings */
1710 diag = hw->mac.ops.start_hw(hw);
1716 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1720 rte_intr_callback_register(intr_handle,
1721 ixgbevf_dev_interrupt_handler, eth_dev);
1722 rte_intr_enable(intr_handle);
1723 ixgbevf_intr_enable(eth_dev);
1725 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1726 eth_dev->data->port_id, pci_dev->id.vendor_id,
1727 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1732 /* Virtual Function device uninit */
1735 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1737 PMD_INIT_FUNC_TRACE();
1739 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1742 ixgbevf_dev_close(eth_dev);
1748 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1749 struct rte_pci_device *pci_dev)
1751 char name[RTE_ETH_NAME_MAX_LEN];
1752 struct rte_eth_dev *pf_ethdev;
1753 struct rte_eth_devargs eth_da;
1756 if (pci_dev->device.devargs) {
1757 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1762 memset(ð_da, 0, sizeof(eth_da));
1764 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1765 sizeof(struct ixgbe_adapter),
1766 eth_dev_pci_specific_init, pci_dev,
1767 eth_ixgbe_dev_init, NULL);
1769 if (retval || eth_da.nb_representor_ports < 1)
1772 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1773 if (pf_ethdev == NULL)
1776 /* probe VF representor ports */
1777 for (i = 0; i < eth_da.nb_representor_ports; i++) {
1778 struct ixgbe_vf_info *vfinfo;
1779 struct ixgbe_vf_representor representor;
1781 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1782 pf_ethdev->data->dev_private);
1783 if (vfinfo == NULL) {
1785 "no virtual functions supported by PF");
1789 representor.vf_id = eth_da.representor_ports[i];
1790 representor.switch_domain_id = vfinfo->switch_domain_id;
1791 representor.pf_ethdev = pf_ethdev;
1793 /* representor port net_bdf_port */
1794 snprintf(name, sizeof(name), "net_%s_representor_%d",
1795 pci_dev->device.name,
1796 eth_da.representor_ports[i]);
1798 retval = rte_eth_dev_create(&pci_dev->device, name,
1799 sizeof(struct ixgbe_vf_representor), NULL, NULL,
1800 ixgbe_vf_representor_init, &representor);
1803 PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1804 "representor %s.", name);
1810 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1812 struct rte_eth_dev *ethdev;
1814 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1818 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1819 return rte_eth_dev_pci_generic_remove(pci_dev,
1820 ixgbe_vf_representor_uninit);
1822 return rte_eth_dev_pci_generic_remove(pci_dev,
1823 eth_ixgbe_dev_uninit);
1826 static struct rte_pci_driver rte_ixgbe_pmd = {
1827 .id_table = pci_id_ixgbe_map,
1828 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1829 .probe = eth_ixgbe_pci_probe,
1830 .remove = eth_ixgbe_pci_remove,
1833 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1834 struct rte_pci_device *pci_dev)
1836 return rte_eth_dev_pci_generic_probe(pci_dev,
1837 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1840 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1842 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1846 * virtual function driver struct
1848 static struct rte_pci_driver rte_ixgbevf_pmd = {
1849 .id_table = pci_id_ixgbevf_map,
1850 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1851 .probe = eth_ixgbevf_pci_probe,
1852 .remove = eth_ixgbevf_pci_remove,
1856 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1858 struct ixgbe_hw *hw =
1859 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1860 struct ixgbe_vfta *shadow_vfta =
1861 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1866 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1867 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1868 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1873 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1875 /* update local VFTA copy */
1876 shadow_vfta->vfta[vid_idx] = vfta;
1882 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1885 ixgbe_vlan_hw_strip_enable(dev, queue);
1887 ixgbe_vlan_hw_strip_disable(dev, queue);
1891 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1892 enum rte_vlan_type vlan_type,
1895 struct ixgbe_hw *hw =
1896 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1901 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1902 qinq &= IXGBE_DMATXCTL_GDV;
1904 switch (vlan_type) {
1905 case ETH_VLAN_TYPE_INNER:
1907 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1908 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1909 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1910 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1911 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1912 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1913 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1916 PMD_DRV_LOG(ERR, "Inner type is not supported"
1920 case ETH_VLAN_TYPE_OUTER:
1922 /* Only the high 16-bits is valid */
1923 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1924 IXGBE_EXVET_VET_EXT_SHIFT);
1926 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1927 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1928 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1929 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1930 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1931 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1932 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1938 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1946 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1948 struct ixgbe_hw *hw =
1949 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1952 PMD_INIT_FUNC_TRACE();
1954 /* Filter Table Disable */
1955 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1956 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1958 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1962 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1964 struct ixgbe_hw *hw =
1965 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1966 struct ixgbe_vfta *shadow_vfta =
1967 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1971 PMD_INIT_FUNC_TRACE();
1973 /* Filter Table Enable */
1974 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1975 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1976 vlnctrl |= IXGBE_VLNCTRL_VFE;
1978 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1980 /* write whatever is in local vfta copy */
1981 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1982 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1986 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1988 struct ixgbe_hwstrip *hwstrip =
1989 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1990 struct ixgbe_rx_queue *rxq;
1992 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1996 IXGBE_SET_HWSTRIP(hwstrip, queue);
1998 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
2000 if (queue >= dev->data->nb_rx_queues)
2003 rxq = dev->data->rx_queues[queue];
2006 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2007 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2009 rxq->vlan_flags = PKT_RX_VLAN;
2010 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2015 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2017 struct ixgbe_hw *hw =
2018 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2021 PMD_INIT_FUNC_TRACE();
2023 if (hw->mac.type == ixgbe_mac_82598EB) {
2024 /* No queue level support */
2025 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2029 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2030 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2031 ctrl &= ~IXGBE_RXDCTL_VME;
2032 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2034 /* record those setting for HW strip per queue */
2035 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2039 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2041 struct ixgbe_hw *hw =
2042 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2045 PMD_INIT_FUNC_TRACE();
2047 if (hw->mac.type == ixgbe_mac_82598EB) {
2048 /* No queue level supported */
2049 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2053 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2054 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2055 ctrl |= IXGBE_RXDCTL_VME;
2056 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2058 /* record those setting for HW strip per queue */
2059 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2063 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2065 struct ixgbe_hw *hw =
2066 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2069 PMD_INIT_FUNC_TRACE();
2071 /* DMATXCTRL: Geric Double VLAN Disable */
2072 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2073 ctrl &= ~IXGBE_DMATXCTL_GDV;
2074 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2076 /* CTRL_EXT: Global Double VLAN Disable */
2077 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2078 ctrl &= ~IXGBE_EXTENDED_VLAN;
2079 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2084 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2086 struct ixgbe_hw *hw =
2087 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2090 PMD_INIT_FUNC_TRACE();
2092 /* DMATXCTRL: Geric Double VLAN Enable */
2093 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2094 ctrl |= IXGBE_DMATXCTL_GDV;
2095 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2097 /* CTRL_EXT: Global Double VLAN Enable */
2098 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2099 ctrl |= IXGBE_EXTENDED_VLAN;
2100 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2102 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2103 if (hw->mac.type == ixgbe_mac_X550 ||
2104 hw->mac.type == ixgbe_mac_X550EM_x ||
2105 hw->mac.type == ixgbe_mac_X550EM_a) {
2106 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2107 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2108 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2112 * VET EXT field in the EXVET register = 0x8100 by default
2113 * So no need to change. Same to VT field of DMATXCTL register
2118 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2120 struct ixgbe_hw *hw =
2121 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2122 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2125 struct ixgbe_rx_queue *rxq;
2128 PMD_INIT_FUNC_TRACE();
2130 if (hw->mac.type == ixgbe_mac_82598EB) {
2131 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2132 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2133 ctrl |= IXGBE_VLNCTRL_VME;
2134 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2136 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2137 ctrl &= ~IXGBE_VLNCTRL_VME;
2138 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2142 * Other 10G NIC, the VLAN strip can be setup
2143 * per queue in RXDCTL
2145 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2146 rxq = dev->data->rx_queues[i];
2147 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2148 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2149 ctrl |= IXGBE_RXDCTL_VME;
2152 ctrl &= ~IXGBE_RXDCTL_VME;
2155 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2157 /* record those setting for HW strip per queue */
2158 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2164 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2167 struct rte_eth_rxmode *rxmode;
2168 struct ixgbe_rx_queue *rxq;
2170 if (mask & ETH_VLAN_STRIP_MASK) {
2171 rxmode = &dev->data->dev_conf.rxmode;
2172 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2173 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2174 rxq = dev->data->rx_queues[i];
2175 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2178 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2179 rxq = dev->data->rx_queues[i];
2180 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2186 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2188 struct rte_eth_rxmode *rxmode;
2189 rxmode = &dev->data->dev_conf.rxmode;
2191 if (mask & ETH_VLAN_STRIP_MASK) {
2192 ixgbe_vlan_hw_strip_config(dev);
2195 if (mask & ETH_VLAN_FILTER_MASK) {
2196 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2197 ixgbe_vlan_hw_filter_enable(dev);
2199 ixgbe_vlan_hw_filter_disable(dev);
2202 if (mask & ETH_VLAN_EXTEND_MASK) {
2203 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2204 ixgbe_vlan_hw_extend_enable(dev);
2206 ixgbe_vlan_hw_extend_disable(dev);
2213 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2215 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2217 ixgbe_vlan_offload_config(dev, mask);
2223 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2225 struct ixgbe_hw *hw =
2226 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2227 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2228 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2230 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2231 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2235 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2237 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2242 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2245 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2251 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2252 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2253 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2254 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2259 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2261 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2262 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2263 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2264 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2266 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2267 /* check multi-queue mode */
2268 switch (dev_conf->rxmode.mq_mode) {
2269 case ETH_MQ_RX_VMDQ_DCB:
2270 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2272 case ETH_MQ_RX_VMDQ_DCB_RSS:
2273 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2274 PMD_INIT_LOG(ERR, "SRIOV active,"
2275 " unsupported mq_mode rx %d.",
2276 dev_conf->rxmode.mq_mode);
2279 case ETH_MQ_RX_VMDQ_RSS:
2280 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2281 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2282 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2283 PMD_INIT_LOG(ERR, "SRIOV is active,"
2284 " invalid queue number"
2285 " for VMDQ RSS, allowed"
2286 " value are 1, 2 or 4.");
2290 case ETH_MQ_RX_VMDQ_ONLY:
2291 case ETH_MQ_RX_NONE:
2292 /* if nothing mq mode configure, use default scheme */
2293 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2295 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2296 /* SRIOV only works in VMDq enable mode */
2297 PMD_INIT_LOG(ERR, "SRIOV is active,"
2298 " wrong mq_mode rx %d.",
2299 dev_conf->rxmode.mq_mode);
2303 switch (dev_conf->txmode.mq_mode) {
2304 case ETH_MQ_TX_VMDQ_DCB:
2305 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2306 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2308 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2309 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2313 /* check valid queue number */
2314 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2315 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2316 PMD_INIT_LOG(ERR, "SRIOV is active,"
2317 " nb_rx_q=%d nb_tx_q=%d queue number"
2318 " must be less than or equal to %d.",
2320 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2324 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2325 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2329 /* check configuration for vmdb+dcb mode */
2330 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2331 const struct rte_eth_vmdq_dcb_conf *conf;
2333 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2334 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2335 IXGBE_VMDQ_DCB_NB_QUEUES);
2338 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2339 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2340 conf->nb_queue_pools == ETH_32_POOLS)) {
2341 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2342 " nb_queue_pools must be %d or %d.",
2343 ETH_16_POOLS, ETH_32_POOLS);
2347 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2348 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2350 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2351 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2352 IXGBE_VMDQ_DCB_NB_QUEUES);
2355 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2356 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2357 conf->nb_queue_pools == ETH_32_POOLS)) {
2358 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2359 " nb_queue_pools != %d and"
2360 " nb_queue_pools != %d.",
2361 ETH_16_POOLS, ETH_32_POOLS);
2366 /* For DCB mode check our configuration before we go further */
2367 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2368 const struct rte_eth_dcb_rx_conf *conf;
2370 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2371 if (!(conf->nb_tcs == ETH_4_TCS ||
2372 conf->nb_tcs == ETH_8_TCS)) {
2373 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2374 " and nb_tcs != %d.",
2375 ETH_4_TCS, ETH_8_TCS);
2380 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2381 const struct rte_eth_dcb_tx_conf *conf;
2383 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2384 if (!(conf->nb_tcs == ETH_4_TCS ||
2385 conf->nb_tcs == ETH_8_TCS)) {
2386 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2387 " and nb_tcs != %d.",
2388 ETH_4_TCS, ETH_8_TCS);
2394 * When DCB/VT is off, maximum number of queues changes,
2395 * except for 82598EB, which remains constant.
2397 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2398 hw->mac.type != ixgbe_mac_82598EB) {
2399 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2401 "Neither VT nor DCB are enabled, "
2403 IXGBE_NONE_MODE_TX_NB_QUEUES);
2412 ixgbe_dev_configure(struct rte_eth_dev *dev)
2414 struct ixgbe_interrupt *intr =
2415 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2416 struct ixgbe_adapter *adapter = dev->data->dev_private;
2419 PMD_INIT_FUNC_TRACE();
2421 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2422 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2424 /* multipe queue mode checking */
2425 ret = ixgbe_check_mq_mode(dev);
2427 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2432 /* set flag to update link status after init */
2433 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2436 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2437 * allocation or vector Rx preconditions we will reset it.
2439 adapter->rx_bulk_alloc_allowed = true;
2440 adapter->rx_vec_allowed = true;
2446 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2448 struct ixgbe_hw *hw =
2449 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2450 struct ixgbe_interrupt *intr =
2451 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2454 /* only set up it on X550EM_X */
2455 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2456 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2457 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2458 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2459 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2460 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2465 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2466 uint16_t tx_rate, uint64_t q_msk)
2468 struct ixgbe_hw *hw;
2469 struct ixgbe_vf_info *vfinfo;
2470 struct rte_eth_link link;
2471 uint8_t nb_q_per_pool;
2472 uint32_t queue_stride;
2473 uint32_t queue_idx, idx = 0, vf_idx;
2475 uint16_t total_rate = 0;
2476 struct rte_pci_device *pci_dev;
2479 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2480 ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2484 if (vf >= pci_dev->max_vfs)
2487 if (tx_rate > link.link_speed)
2493 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2494 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2495 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2496 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2497 queue_idx = vf * queue_stride;
2498 queue_end = queue_idx + nb_q_per_pool - 1;
2499 if (queue_end >= hw->mac.max_tx_queues)
2503 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2506 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2508 total_rate += vfinfo[vf_idx].tx_rate[idx];
2514 /* Store tx_rate for this vf. */
2515 for (idx = 0; idx < nb_q_per_pool; idx++) {
2516 if (((uint64_t)0x1 << idx) & q_msk) {
2517 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2518 vfinfo[vf].tx_rate[idx] = tx_rate;
2519 total_rate += tx_rate;
2523 if (total_rate > dev->data->dev_link.link_speed) {
2524 /* Reset stored TX rate of the VF if it causes exceed
2527 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2531 /* Set RTTBCNRC of each queue/pool for vf X */
2532 for (; queue_idx <= queue_end; queue_idx++) {
2534 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2542 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2544 struct ixgbe_adapter *adapter = dev->data->dev_private;
2548 err = ixgbe_fc_enable(hw);
2550 /* Not negotiated is not an error case */
2551 if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2553 *check if we want to forward MAC frames - driver doesn't
2554 *have native capability to do that,
2555 *so we'll write the registers ourselves
2558 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2560 /* set or clear MFLCN.PMCF bit depending on configuration */
2561 if (adapter->mac_ctrl_frame_fwd != 0)
2562 mflcn |= IXGBE_MFLCN_PMCF;
2564 mflcn &= ~IXGBE_MFLCN_PMCF;
2566 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2567 IXGBE_WRITE_FLUSH(hw);
2575 * Configure device link speed and setup link.
2576 * It returns 0 on success.
2579 ixgbe_dev_start(struct rte_eth_dev *dev)
2581 struct ixgbe_hw *hw =
2582 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2583 struct ixgbe_vf_info *vfinfo =
2584 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2585 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2586 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2587 uint32_t intr_vector = 0;
2589 bool link_up = false, negotiate = 0;
2591 uint32_t allowed_speeds = 0;
2595 uint32_t *link_speeds;
2596 struct ixgbe_tm_conf *tm_conf =
2597 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2598 struct ixgbe_macsec_setting *macsec_setting =
2599 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2601 PMD_INIT_FUNC_TRACE();
2603 /* Stop the link setup handler before resetting the HW. */
2604 ixgbe_dev_cancel_link_thread(dev);
2606 /* disable uio/vfio intr/eventfd mapping */
2607 rte_intr_disable(intr_handle);
2610 hw->adapter_stopped = 0;
2611 ixgbe_stop_adapter(hw);
2613 /* reinitialize adapter
2614 * this calls reset and start
2616 status = ixgbe_pf_reset_hw(hw);
2619 hw->mac.ops.start_hw(hw);
2620 hw->mac.get_link_status = true;
2622 /* configure PF module if SRIOV enabled */
2623 ixgbe_pf_host_configure(dev);
2625 ixgbe_dev_phy_intr_setup(dev);
2627 /* check and configure queue intr-vector mapping */
2628 if ((rte_intr_cap_multiple(intr_handle) ||
2629 !RTE_ETH_DEV_SRIOV(dev).active) &&
2630 dev->data->dev_conf.intr_conf.rxq != 0) {
2631 intr_vector = dev->data->nb_rx_queues;
2632 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2633 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2634 IXGBE_MAX_INTR_QUEUE_NUM);
2637 if (rte_intr_efd_enable(intr_handle, intr_vector))
2641 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2642 intr_handle->intr_vec =
2643 rte_zmalloc("intr_vec",
2644 dev->data->nb_rx_queues * sizeof(int), 0);
2645 if (intr_handle->intr_vec == NULL) {
2646 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2647 " intr_vec", dev->data->nb_rx_queues);
2652 /* confiugre msix for sleep until rx interrupt */
2653 ixgbe_configure_msix(dev);
2655 /* initialize transmission unit */
2656 ixgbe_dev_tx_init(dev);
2658 /* This can fail when allocating mbufs for descriptor rings */
2659 err = ixgbe_dev_rx_init(dev);
2661 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2665 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2666 ETH_VLAN_EXTEND_MASK;
2667 err = ixgbe_vlan_offload_config(dev, mask);
2669 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2673 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2674 /* Enable vlan filtering for VMDq */
2675 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2678 /* Configure DCB hw */
2679 ixgbe_configure_dcb(dev);
2681 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2682 err = ixgbe_fdir_configure(dev);
2687 /* Restore vf rate limit */
2688 if (vfinfo != NULL) {
2689 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2690 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2691 if (vfinfo[vf].tx_rate[idx] != 0)
2692 ixgbe_set_vf_rate_limit(
2694 vfinfo[vf].tx_rate[idx],
2698 ixgbe_restore_statistics_mapping(dev);
2700 err = ixgbe_flow_ctrl_enable(dev, hw);
2702 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2706 err = ixgbe_dev_rxtx_start(dev);
2708 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2712 /* Skip link setup if loopback mode is enabled. */
2713 if (dev->data->dev_conf.lpbk_mode != 0) {
2714 err = ixgbe_check_supported_loopback_mode(dev);
2716 PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2719 goto skip_link_setup;
2723 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2724 err = hw->mac.ops.setup_sfp(hw);
2729 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2730 /* Turn on the copper */
2731 ixgbe_set_phy_power(hw, true);
2733 /* Turn on the laser */
2734 ixgbe_enable_tx_laser(hw);
2737 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2740 dev->data->dev_link.link_status = link_up;
2742 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2746 switch (hw->mac.type) {
2747 case ixgbe_mac_X550:
2748 case ixgbe_mac_X550EM_x:
2749 case ixgbe_mac_X550EM_a:
2750 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2751 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G |
2753 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2754 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2755 allowed_speeds = ETH_LINK_SPEED_10M |
2756 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2759 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2763 link_speeds = &dev->data->dev_conf.link_speeds;
2765 /* Ignore autoneg flag bit and check the validity ofÂ
2768 if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2769 PMD_INIT_LOG(ERR, "Invalid link setting");
2774 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2775 switch (hw->mac.type) {
2776 case ixgbe_mac_82598EB:
2777 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2779 case ixgbe_mac_82599EB:
2780 case ixgbe_mac_X540:
2781 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2783 case ixgbe_mac_X550:
2784 case ixgbe_mac_X550EM_x:
2785 case ixgbe_mac_X550EM_a:
2786 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2789 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2792 if (*link_speeds & ETH_LINK_SPEED_10G)
2793 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2794 if (*link_speeds & ETH_LINK_SPEED_5G)
2795 speed |= IXGBE_LINK_SPEED_5GB_FULL;
2796 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2797 speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2798 if (*link_speeds & ETH_LINK_SPEED_1G)
2799 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2800 if (*link_speeds & ETH_LINK_SPEED_100M)
2801 speed |= IXGBE_LINK_SPEED_100_FULL;
2802 if (*link_speeds & ETH_LINK_SPEED_10M)
2803 speed |= IXGBE_LINK_SPEED_10_FULL;
2806 err = ixgbe_setup_link(hw, speed, link_up);
2812 if (rte_intr_allow_others(intr_handle)) {
2813 /* check if lsc interrupt is enabled */
2814 if (dev->data->dev_conf.intr_conf.lsc != 0)
2815 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2817 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2818 ixgbe_dev_macsec_interrupt_setup(dev);
2820 rte_intr_callback_unregister(intr_handle,
2821 ixgbe_dev_interrupt_handler, dev);
2822 if (dev->data->dev_conf.intr_conf.lsc != 0)
2823 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2824 " no intr multiplex");
2827 /* check if rxq interrupt is enabled */
2828 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2829 rte_intr_dp_is_en(intr_handle))
2830 ixgbe_dev_rxq_interrupt_setup(dev);
2832 /* enable uio/vfio intr/eventfd mapping */
2833 rte_intr_enable(intr_handle);
2835 /* resume enabled intr since hw reset */
2836 ixgbe_enable_intr(dev);
2837 ixgbe_l2_tunnel_conf(dev);
2838 ixgbe_filter_restore(dev);
2840 if (tm_conf->root && !tm_conf->committed)
2841 PMD_DRV_LOG(WARNING,
2842 "please call hierarchy_commit() "
2843 "before starting the port");
2845 /* wait for the controller to acquire link */
2846 err = ixgbe_wait_for_link_up(hw);
2851 * Update link status right before return, because it may
2852 * start link configuration process in a separate thread.
2854 ixgbe_dev_link_update(dev, 0);
2856 /* setup the macsec setting register */
2857 if (macsec_setting->offload_en)
2858 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2863 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2864 ixgbe_dev_clear_queues(dev);
2869 * Stop device: disable rx and tx functions to allow for reconfiguring.
2872 ixgbe_dev_stop(struct rte_eth_dev *dev)
2874 struct rte_eth_link link;
2875 struct ixgbe_adapter *adapter = dev->data->dev_private;
2876 struct ixgbe_hw *hw =
2877 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2878 struct ixgbe_vf_info *vfinfo =
2879 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2880 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2881 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2883 struct ixgbe_tm_conf *tm_conf =
2884 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2886 if (hw->adapter_stopped)
2889 PMD_INIT_FUNC_TRACE();
2891 ixgbe_dev_cancel_link_thread(dev);
2893 /* disable interrupts */
2894 ixgbe_disable_intr(hw);
2897 ixgbe_pf_reset_hw(hw);
2898 hw->adapter_stopped = 0;
2901 ixgbe_stop_adapter(hw);
2903 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2904 vfinfo[vf].clear_to_send = false;
2906 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2907 /* Turn off the copper */
2908 ixgbe_set_phy_power(hw, false);
2910 /* Turn off the laser */
2911 ixgbe_disable_tx_laser(hw);
2914 ixgbe_dev_clear_queues(dev);
2916 /* Clear stored conf */
2917 dev->data->scattered_rx = 0;
2920 /* Clear recorded link status */
2921 memset(&link, 0, sizeof(link));
2922 rte_eth_linkstatus_set(dev, &link);
2924 if (!rte_intr_allow_others(intr_handle))
2925 /* resume to the default handler */
2926 rte_intr_callback_register(intr_handle,
2927 ixgbe_dev_interrupt_handler,
2930 /* Clean datapath event and queue/vec mapping */
2931 rte_intr_efd_disable(intr_handle);
2932 if (intr_handle->intr_vec != NULL) {
2933 rte_free(intr_handle->intr_vec);
2934 intr_handle->intr_vec = NULL;
2937 /* reset hierarchy commit */
2938 tm_conf->committed = false;
2940 adapter->rss_reta_updated = 0;
2942 adapter->mac_ctrl_frame_fwd = 0;
2944 hw->adapter_stopped = true;
2948 * Set device link up: enable tx.
2951 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2953 struct ixgbe_hw *hw =
2954 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2955 if (hw->mac.type == ixgbe_mac_82599EB) {
2956 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2957 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2958 /* Not suported in bypass mode */
2959 PMD_INIT_LOG(ERR, "Set link up is not supported "
2960 "by device id 0x%x", hw->device_id);
2966 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2967 /* Turn on the copper */
2968 ixgbe_set_phy_power(hw, true);
2970 /* Turn on the laser */
2971 ixgbe_enable_tx_laser(hw);
2972 ixgbe_dev_link_update(dev, 0);
2979 * Set device link down: disable tx.
2982 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2984 struct ixgbe_hw *hw =
2985 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2986 if (hw->mac.type == ixgbe_mac_82599EB) {
2987 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2988 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2989 /* Not suported in bypass mode */
2990 PMD_INIT_LOG(ERR, "Set link down is not supported "
2991 "by device id 0x%x", hw->device_id);
2997 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2998 /* Turn off the copper */
2999 ixgbe_set_phy_power(hw, false);
3001 /* Turn off the laser */
3002 ixgbe_disable_tx_laser(hw);
3003 ixgbe_dev_link_update(dev, 0);
3010 * Reset and stop device.
3013 ixgbe_dev_close(struct rte_eth_dev *dev)
3015 struct ixgbe_hw *hw =
3016 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3017 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3018 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3022 PMD_INIT_FUNC_TRACE();
3024 ixgbe_pf_reset_hw(hw);
3026 ixgbe_dev_stop(dev);
3028 ixgbe_dev_free_queues(dev);
3030 ixgbe_disable_pcie_master(hw);
3032 /* reprogram the RAR[0] in case user changed it. */
3033 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3035 dev->dev_ops = NULL;
3036 dev->rx_pkt_burst = NULL;
3037 dev->tx_pkt_burst = NULL;
3039 /* Unlock any pending hardware semaphore */
3040 ixgbe_swfw_lock_reset(hw);
3042 /* disable uio intr before callback unregister */
3043 rte_intr_disable(intr_handle);
3046 ret = rte_intr_callback_unregister(intr_handle,
3047 ixgbe_dev_interrupt_handler, dev);
3048 if (ret >= 0 || ret == -ENOENT) {
3050 } else if (ret != -EAGAIN) {
3052 "intr callback unregister failed: %d",
3056 } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3058 /* cancel the delay handler before remove dev */
3059 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3061 /* uninitialize PF if max_vfs not zero */
3062 ixgbe_pf_host_uninit(dev);
3064 /* remove all the fdir filters & hash */
3065 ixgbe_fdir_filter_uninit(dev);
3067 /* remove all the L2 tunnel filters & hash */
3068 ixgbe_l2_tn_filter_uninit(dev);
3070 /* Remove all ntuple filters of the device */
3071 ixgbe_ntuple_filter_uninit(dev);
3073 /* clear all the filters list */
3074 ixgbe_filterlist_flush();
3076 /* Remove all Traffic Manager configuration */
3077 ixgbe_tm_conf_uninit(dev);
3079 #ifdef RTE_LIBRTE_SECURITY
3080 rte_free(dev->security_ctx);
3089 ixgbe_dev_reset(struct rte_eth_dev *dev)
3093 /* When a DPDK PMD PF begin to reset PF port, it should notify all
3094 * its VF to make them align with it. The detailed notification
3095 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3096 * To avoid unexpected behavior in VF, currently reset of PF with
3097 * SR-IOV activation is not supported. It might be supported later.
3099 if (dev->data->sriov.active)
3102 ret = eth_ixgbe_dev_uninit(dev);
3106 ret = eth_ixgbe_dev_init(dev, NULL);
3112 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3113 struct ixgbe_hw_stats *hw_stats,
3114 struct ixgbe_macsec_stats *macsec_stats,
3115 uint64_t *total_missed_rx, uint64_t *total_qbrc,
3116 uint64_t *total_qprc, uint64_t *total_qprdc)
3118 uint32_t bprc, lxon, lxoff, total;
3119 uint32_t delta_gprc = 0;
3121 /* Workaround for RX byte count not including CRC bytes when CRC
3122 * strip is enabled. CRC bytes are removed from counters when crc_strip
3125 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3126 IXGBE_HLREG0_RXCRCSTRP);
3128 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3129 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3130 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3131 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3133 for (i = 0; i < 8; i++) {
3134 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3136 /* global total per queue */
3137 hw_stats->mpc[i] += mp;
3138 /* Running comprehensive total for stats display */
3139 *total_missed_rx += hw_stats->mpc[i];
3140 if (hw->mac.type == ixgbe_mac_82598EB) {
3141 hw_stats->rnbc[i] +=
3142 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3143 hw_stats->pxonrxc[i] +=
3144 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3145 hw_stats->pxoffrxc[i] +=
3146 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3148 hw_stats->pxonrxc[i] +=
3149 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3150 hw_stats->pxoffrxc[i] +=
3151 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3152 hw_stats->pxon2offc[i] +=
3153 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3155 hw_stats->pxontxc[i] +=
3156 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3157 hw_stats->pxofftxc[i] +=
3158 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3160 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3161 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3162 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3163 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3165 delta_gprc += delta_qprc;
3167 hw_stats->qprc[i] += delta_qprc;
3168 hw_stats->qptc[i] += delta_qptc;
3170 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3171 hw_stats->qbrc[i] +=
3172 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3174 hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3176 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3177 hw_stats->qbtc[i] +=
3178 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3180 hw_stats->qprdc[i] += delta_qprdc;
3181 *total_qprdc += hw_stats->qprdc[i];
3183 *total_qprc += hw_stats->qprc[i];
3184 *total_qbrc += hw_stats->qbrc[i];
3186 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3187 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3188 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3191 * An errata states that gprc actually counts good + missed packets:
3192 * Workaround to set gprc to summated queue packet receives
3194 hw_stats->gprc = *total_qprc;
3196 if (hw->mac.type != ixgbe_mac_82598EB) {
3197 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3198 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3199 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3200 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3201 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3202 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3203 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3204 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3206 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3207 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3208 /* 82598 only has a counter in the high register */
3209 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3210 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3211 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3213 uint64_t old_tpr = hw_stats->tpr;
3215 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3216 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3219 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3221 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3222 hw_stats->gptc += delta_gptc;
3223 hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3224 hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3227 * Workaround: mprc hardware is incorrectly counting
3228 * broadcasts, so for now we subtract those.
3230 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3231 hw_stats->bprc += bprc;
3232 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3233 if (hw->mac.type == ixgbe_mac_82598EB)
3234 hw_stats->mprc -= bprc;
3236 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3237 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3238 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3239 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3240 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3241 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3243 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3244 hw_stats->lxontxc += lxon;
3245 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3246 hw_stats->lxofftxc += lxoff;
3247 total = lxon + lxoff;
3249 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3250 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3251 hw_stats->gptc -= total;
3252 hw_stats->mptc -= total;
3253 hw_stats->ptc64 -= total;
3254 hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3256 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3257 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3258 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3259 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3260 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3261 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3262 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3263 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3264 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3265 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3266 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3267 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3268 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3269 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3270 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3271 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3272 /* Only read FCOE on 82599 */
3273 if (hw->mac.type != ixgbe_mac_82598EB) {
3274 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3275 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3276 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3277 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3278 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3281 /* Flow Director Stats registers */
3282 if (hw->mac.type != ixgbe_mac_82598EB) {
3283 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3284 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3285 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3286 IXGBE_FDIRUSTAT) & 0xFFFF;
3287 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3288 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3289 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3290 IXGBE_FDIRFSTAT) & 0xFFFF;
3291 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3292 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3294 /* MACsec Stats registers */
3295 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3296 macsec_stats->out_pkts_encrypted +=
3297 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3298 macsec_stats->out_pkts_protected +=
3299 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3300 macsec_stats->out_octets_encrypted +=
3301 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3302 macsec_stats->out_octets_protected +=
3303 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3304 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3305 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3306 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3307 macsec_stats->in_pkts_unknownsci +=
3308 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3309 macsec_stats->in_octets_decrypted +=
3310 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3311 macsec_stats->in_octets_validated +=
3312 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3313 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3314 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3315 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3316 for (i = 0; i < 2; i++) {
3317 macsec_stats->in_pkts_ok +=
3318 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3319 macsec_stats->in_pkts_invalid +=
3320 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3321 macsec_stats->in_pkts_notvalid +=
3322 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3324 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3325 macsec_stats->in_pkts_notusingsa +=
3326 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3330 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3333 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3335 struct ixgbe_hw *hw =
3336 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3337 struct ixgbe_hw_stats *hw_stats =
3338 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3339 struct ixgbe_macsec_stats *macsec_stats =
3340 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3341 dev->data->dev_private);
3342 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3345 total_missed_rx = 0;
3350 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3351 &total_qbrc, &total_qprc, &total_qprdc);
3356 /* Fill out the rte_eth_stats statistics structure */
3357 stats->ipackets = total_qprc;
3358 stats->ibytes = total_qbrc;
3359 stats->opackets = hw_stats->gptc;
3360 stats->obytes = hw_stats->gotc;
3362 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3363 stats->q_ipackets[i] = hw_stats->qprc[i];
3364 stats->q_opackets[i] = hw_stats->qptc[i];
3365 stats->q_ibytes[i] = hw_stats->qbrc[i];
3366 stats->q_obytes[i] = hw_stats->qbtc[i];
3367 stats->q_errors[i] = hw_stats->qprdc[i];
3371 stats->imissed = total_missed_rx;
3372 stats->ierrors = hw_stats->crcerrs +
3389 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3391 struct ixgbe_hw_stats *stats =
3392 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3394 /* HW registers are cleared on read */
3395 ixgbe_dev_stats_get(dev, NULL);
3397 /* Reset software totals */
3398 memset(stats, 0, sizeof(*stats));
3403 /* This function calculates the number of xstats based on the current config */
3405 ixgbe_xstats_calc_num(void) {
3406 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3407 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3408 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3411 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3412 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3414 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3415 unsigned stat, i, count;
3417 if (xstats_names != NULL) {
3420 /* Note: limit >= cnt_stats checked upstream
3421 * in rte_eth_xstats_names()
3424 /* Extended stats from ixgbe_hw_stats */
3425 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3426 strlcpy(xstats_names[count].name,
3427 rte_ixgbe_stats_strings[i].name,
3428 sizeof(xstats_names[count].name));
3433 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3434 strlcpy(xstats_names[count].name,
3435 rte_ixgbe_macsec_strings[i].name,
3436 sizeof(xstats_names[count].name));
3440 /* RX Priority Stats */
3441 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3442 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3443 snprintf(xstats_names[count].name,
3444 sizeof(xstats_names[count].name),
3445 "rx_priority%u_%s", i,
3446 rte_ixgbe_rxq_strings[stat].name);
3451 /* TX Priority Stats */
3452 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3453 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3454 snprintf(xstats_names[count].name,
3455 sizeof(xstats_names[count].name),
3456 "tx_priority%u_%s", i,
3457 rte_ixgbe_txq_strings[stat].name);
3465 static int ixgbe_dev_xstats_get_names_by_id(
3466 struct rte_eth_dev *dev,
3467 struct rte_eth_xstat_name *xstats_names,
3468 const uint64_t *ids,
3472 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3473 unsigned int stat, i, count;
3475 if (xstats_names != NULL) {
3478 /* Note: limit >= cnt_stats checked upstream
3479 * in rte_eth_xstats_names()
3482 /* Extended stats from ixgbe_hw_stats */
3483 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3484 strlcpy(xstats_names[count].name,
3485 rte_ixgbe_stats_strings[i].name,
3486 sizeof(xstats_names[count].name));
3491 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3492 strlcpy(xstats_names[count].name,
3493 rte_ixgbe_macsec_strings[i].name,
3494 sizeof(xstats_names[count].name));
3498 /* RX Priority Stats */
3499 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3500 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3501 snprintf(xstats_names[count].name,
3502 sizeof(xstats_names[count].name),
3503 "rx_priority%u_%s", i,
3504 rte_ixgbe_rxq_strings[stat].name);
3509 /* TX Priority Stats */
3510 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3511 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3512 snprintf(xstats_names[count].name,
3513 sizeof(xstats_names[count].name),
3514 "tx_priority%u_%s", i,
3515 rte_ixgbe_txq_strings[stat].name);
3524 uint16_t size = ixgbe_xstats_calc_num();
3525 struct rte_eth_xstat_name xstats_names_copy[size];
3527 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3530 for (i = 0; i < limit; i++) {
3531 if (ids[i] >= size) {
3532 PMD_INIT_LOG(ERR, "id value isn't valid");
3535 strcpy(xstats_names[i].name,
3536 xstats_names_copy[ids[i]].name);
3541 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3542 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3546 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3549 if (xstats_names != NULL)
3550 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3551 strlcpy(xstats_names[i].name,
3552 rte_ixgbevf_stats_strings[i].name,
3553 sizeof(xstats_names[i].name));
3554 return IXGBEVF_NB_XSTATS;
3558 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3561 struct ixgbe_hw *hw =
3562 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3563 struct ixgbe_hw_stats *hw_stats =
3564 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3565 struct ixgbe_macsec_stats *macsec_stats =
3566 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3567 dev->data->dev_private);
3568 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3569 unsigned i, stat, count = 0;
3571 count = ixgbe_xstats_calc_num();
3576 total_missed_rx = 0;
3581 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3582 &total_qbrc, &total_qprc, &total_qprdc);
3584 /* If this is a reset xstats is NULL, and we have cleared the
3585 * registers by reading them.
3590 /* Extended stats from ixgbe_hw_stats */
3592 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3593 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3594 rte_ixgbe_stats_strings[i].offset);
3595 xstats[count].id = count;
3600 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3601 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3602 rte_ixgbe_macsec_strings[i].offset);
3603 xstats[count].id = count;
3607 /* RX Priority Stats */
3608 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3609 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3610 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3611 rte_ixgbe_rxq_strings[stat].offset +
3612 (sizeof(uint64_t) * i));
3613 xstats[count].id = count;
3618 /* TX Priority Stats */
3619 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3620 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3621 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3622 rte_ixgbe_txq_strings[stat].offset +
3623 (sizeof(uint64_t) * i));
3624 xstats[count].id = count;
3632 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3633 uint64_t *values, unsigned int n)
3636 struct ixgbe_hw *hw =
3637 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3638 struct ixgbe_hw_stats *hw_stats =
3639 IXGBE_DEV_PRIVATE_TO_STATS(
3640 dev->data->dev_private);
3641 struct ixgbe_macsec_stats *macsec_stats =
3642 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3643 dev->data->dev_private);
3644 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3645 unsigned int i, stat, count = 0;
3647 count = ixgbe_xstats_calc_num();
3649 if (!ids && n < count)
3652 total_missed_rx = 0;
3657 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3658 &total_missed_rx, &total_qbrc, &total_qprc,
3661 /* If this is a reset xstats is NULL, and we have cleared the
3662 * registers by reading them.
3664 if (!ids && !values)
3667 /* Extended stats from ixgbe_hw_stats */
3669 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3670 values[count] = *(uint64_t *)(((char *)hw_stats) +
3671 rte_ixgbe_stats_strings[i].offset);
3676 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3677 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3678 rte_ixgbe_macsec_strings[i].offset);
3682 /* RX Priority Stats */
3683 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3684 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3686 *(uint64_t *)(((char *)hw_stats) +
3687 rte_ixgbe_rxq_strings[stat].offset +
3688 (sizeof(uint64_t) * i));
3693 /* TX Priority Stats */
3694 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3695 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3697 *(uint64_t *)(((char *)hw_stats) +
3698 rte_ixgbe_txq_strings[stat].offset +
3699 (sizeof(uint64_t) * i));
3707 uint16_t size = ixgbe_xstats_calc_num();
3708 uint64_t values_copy[size];
3710 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3712 for (i = 0; i < n; i++) {
3713 if (ids[i] >= size) {
3714 PMD_INIT_LOG(ERR, "id value isn't valid");
3717 values[i] = values_copy[ids[i]];
3723 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3725 struct ixgbe_hw_stats *stats =
3726 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3727 struct ixgbe_macsec_stats *macsec_stats =
3728 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3729 dev->data->dev_private);
3731 unsigned count = ixgbe_xstats_calc_num();
3733 /* HW registers are cleared on read */
3734 ixgbe_dev_xstats_get(dev, NULL, count);
3736 /* Reset software totals */
3737 memset(stats, 0, sizeof(*stats));
3738 memset(macsec_stats, 0, sizeof(*macsec_stats));
3744 ixgbevf_update_stats(struct rte_eth_dev *dev)
3746 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3747 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3748 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3750 /* Good Rx packet, include VF loopback */
3751 UPDATE_VF_STAT(IXGBE_VFGPRC,
3752 hw_stats->last_vfgprc, hw_stats->vfgprc);
3754 /* Good Rx octets, include VF loopback */
3755 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3756 hw_stats->last_vfgorc, hw_stats->vfgorc);
3758 /* Good Tx packet, include VF loopback */
3759 UPDATE_VF_STAT(IXGBE_VFGPTC,
3760 hw_stats->last_vfgptc, hw_stats->vfgptc);
3762 /* Good Tx octets, include VF loopback */
3763 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3764 hw_stats->last_vfgotc, hw_stats->vfgotc);
3766 /* Rx Multicst Packet */
3767 UPDATE_VF_STAT(IXGBE_VFMPRC,
3768 hw_stats->last_vfmprc, hw_stats->vfmprc);
3772 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3775 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3776 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3779 if (n < IXGBEVF_NB_XSTATS)
3780 return IXGBEVF_NB_XSTATS;
3782 ixgbevf_update_stats(dev);
3787 /* Extended stats */
3788 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3790 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3791 rte_ixgbevf_stats_strings[i].offset);
3794 return IXGBEVF_NB_XSTATS;
3798 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3800 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3801 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3803 ixgbevf_update_stats(dev);
3808 stats->ipackets = hw_stats->vfgprc;
3809 stats->ibytes = hw_stats->vfgorc;
3810 stats->opackets = hw_stats->vfgptc;
3811 stats->obytes = hw_stats->vfgotc;
3816 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3818 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3819 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3821 /* Sync HW register to the last stats */
3822 ixgbevf_dev_stats_get(dev, NULL);
3824 /* reset HW current stats*/
3825 hw_stats->vfgprc = 0;
3826 hw_stats->vfgorc = 0;
3827 hw_stats->vfgptc = 0;
3828 hw_stats->vfgotc = 0;
3834 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3836 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3837 u16 eeprom_verh, eeprom_verl;
3841 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3842 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3844 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3845 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3847 ret += 1; /* add the size of '\0' */
3848 if (fw_size < (u32)ret)
3855 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3857 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3858 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3859 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3861 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3862 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3863 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3865 * When DCB/VT is off, maximum number of queues changes,
3866 * except for 82598EB, which remains constant.
3868 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3869 hw->mac.type != ixgbe_mac_82598EB)
3870 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3872 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3873 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3874 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3875 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3876 dev_info->max_vfs = pci_dev->max_vfs;
3877 if (hw->mac.type == ixgbe_mac_82598EB)
3878 dev_info->max_vmdq_pools = ETH_16_POOLS;
3880 dev_info->max_vmdq_pools = ETH_64_POOLS;
3881 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3882 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3883 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3884 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3885 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3886 dev_info->rx_queue_offload_capa);
3887 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3888 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3890 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3892 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3893 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3894 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3896 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3901 dev_info->default_txconf = (struct rte_eth_txconf) {
3903 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3904 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3905 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3907 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3908 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3912 dev_info->rx_desc_lim = rx_desc_lim;
3913 dev_info->tx_desc_lim = tx_desc_lim;
3915 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3916 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3917 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3919 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3920 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3921 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3922 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3923 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3925 if (hw->mac.type == ixgbe_mac_X540 ||
3926 hw->mac.type == ixgbe_mac_X540_vf ||
3927 hw->mac.type == ixgbe_mac_X550 ||
3928 hw->mac.type == ixgbe_mac_X550_vf) {
3929 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3931 if (hw->mac.type == ixgbe_mac_X550) {
3932 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3933 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3936 /* Driver-preferred Rx/Tx parameters */
3937 dev_info->default_rxportconf.burst_size = 32;
3938 dev_info->default_txportconf.burst_size = 32;
3939 dev_info->default_rxportconf.nb_queues = 1;
3940 dev_info->default_txportconf.nb_queues = 1;
3941 dev_info->default_rxportconf.ring_size = 256;
3942 dev_info->default_txportconf.ring_size = 256;
3947 static const uint32_t *
3948 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3950 static const uint32_t ptypes[] = {
3951 /* For non-vec functions,
3952 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3953 * for vec functions,
3954 * refers to _recv_raw_pkts_vec().
3958 RTE_PTYPE_L3_IPV4_EXT,
3960 RTE_PTYPE_L3_IPV6_EXT,
3964 RTE_PTYPE_TUNNEL_IP,
3965 RTE_PTYPE_INNER_L3_IPV6,
3966 RTE_PTYPE_INNER_L3_IPV6_EXT,
3967 RTE_PTYPE_INNER_L4_TCP,
3968 RTE_PTYPE_INNER_L4_UDP,
3972 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3973 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3974 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3975 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3978 #if defined(RTE_ARCH_X86) || defined(RTE_MACHINE_CPUFLAG_NEON)
3979 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3980 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3987 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3988 struct rte_eth_dev_info *dev_info)
3990 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3991 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3993 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3994 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3995 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3996 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3997 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3998 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3999 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
4000 dev_info->max_vfs = pci_dev->max_vfs;
4001 if (hw->mac.type == ixgbe_mac_82598EB)
4002 dev_info->max_vmdq_pools = ETH_16_POOLS;
4004 dev_info->max_vmdq_pools = ETH_64_POOLS;
4005 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
4006 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
4007 dev_info->rx_queue_offload_capa);
4008 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
4009 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
4010 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
4011 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
4012 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
4014 dev_info->default_rxconf = (struct rte_eth_rxconf) {
4016 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
4017 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
4018 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
4020 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
4025 dev_info->default_txconf = (struct rte_eth_txconf) {
4027 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
4028 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
4029 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
4031 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
4032 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4036 dev_info->rx_desc_lim = rx_desc_lim;
4037 dev_info->tx_desc_lim = tx_desc_lim;
4043 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4044 bool *link_up, int wait_to_complete)
4046 struct ixgbe_adapter *adapter = container_of(hw,
4047 struct ixgbe_adapter, hw);
4048 struct ixgbe_mbx_info *mbx = &hw->mbx;
4049 struct ixgbe_mac_info *mac = &hw->mac;
4050 uint32_t links_reg, in_msg;
4053 /* If we were hit with a reset drop the link */
4054 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4055 mac->get_link_status = true;
4057 if (!mac->get_link_status)
4060 /* if link status is down no point in checking to see if pf is up */
4061 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4062 if (!(links_reg & IXGBE_LINKS_UP))
4065 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4066 * before the link status is correct
4068 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4071 for (i = 0; i < 5; i++) {
4073 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4075 if (!(links_reg & IXGBE_LINKS_UP))
4080 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4081 case IXGBE_LINKS_SPEED_10G_82599:
4082 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4083 if (hw->mac.type >= ixgbe_mac_X550) {
4084 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4085 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4088 case IXGBE_LINKS_SPEED_1G_82599:
4089 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4091 case IXGBE_LINKS_SPEED_100_82599:
4092 *speed = IXGBE_LINK_SPEED_100_FULL;
4093 if (hw->mac.type == ixgbe_mac_X550) {
4094 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4095 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4098 case IXGBE_LINKS_SPEED_10_X550EM_A:
4099 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4100 /* Since Reserved in older MAC's */
4101 if (hw->mac.type >= ixgbe_mac_X550)
4102 *speed = IXGBE_LINK_SPEED_10_FULL;
4105 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4108 if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4109 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4110 mac->get_link_status = true;
4112 mac->get_link_status = false;
4117 /* if the read failed it could just be a mailbox collision, best wait
4118 * until we are called again and don't report an error
4120 if (mbx->ops.read(hw, &in_msg, 1, 0))
4123 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4124 /* msg is not CTS and is NACK we must have lost CTS status */
4125 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4126 mac->get_link_status = false;
4130 /* the pf is talking, if we timed out in the past we reinit */
4131 if (!mbx->timeout) {
4136 /* if we passed all the tests above then the link is up and we no
4137 * longer need to check for link
4139 mac->get_link_status = false;
4142 *link_up = !mac->get_link_status;
4146 /* return 1: setup complete, return 0: setup not complete, and wait timeout*/
4148 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev)
4150 #define DELAY_INTERVAL 100 /* 100ms */
4151 #define MAX_TIMEOUT 90 /* 9s (90 * 100ms) in total */
4152 struct ixgbe_adapter *ad = dev->data->dev_private;
4153 int timeout = MAX_TIMEOUT;
4155 while (rte_atomic32_read(&ad->link_thread_running) && timeout) {
4156 msec_delay(DELAY_INTERVAL);
4165 ixgbe_dev_cancel_link_thread(struct rte_eth_dev *dev)
4167 struct ixgbe_adapter *ad = dev->data->dev_private;
4170 if (!ixgbe_dev_wait_setup_link_complete(dev)) {
4171 pthread_cancel(ad->link_thread_tid);
4172 pthread_join(ad->link_thread_tid, &retval);
4173 rte_atomic32_clear(&ad->link_thread_running);
4174 PMD_DRV_LOG(ERR, "Link thread not complete, cancel it!");
4179 ixgbe_dev_setup_link_thread_handler(void *param)
4181 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4182 struct ixgbe_adapter *ad = dev->data->dev_private;
4183 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4184 struct ixgbe_interrupt *intr =
4185 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4187 bool autoneg = false;
4189 speed = hw->phy.autoneg_advertised;
4191 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4193 ixgbe_setup_link(hw, speed, true);
4195 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4196 rte_atomic32_clear(&ad->link_thread_running);
4201 * In freebsd environment, nic_uio drivers do not support interrupts,
4202 * rte_intr_callback_register() will fail to register interrupts.
4203 * We can not make link status to change from down to up by interrupt
4204 * callback. So we need to wait for the controller to acquire link
4206 * It returns 0 on link up.
4209 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4211 #ifdef RTE_EXEC_ENV_FREEBSD
4213 bool link_up = false;
4215 const int nb_iter = 25;
4217 for (i = 0; i < nb_iter; i++) {
4218 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4233 /* return 0 means link status changed, -1 means not changed */
4235 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4236 int wait_to_complete, int vf)
4238 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4239 struct ixgbe_adapter *ad = dev->data->dev_private;
4240 struct rte_eth_link link;
4241 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4242 struct ixgbe_interrupt *intr =
4243 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4249 memset(&link, 0, sizeof(link));
4250 link.link_status = ETH_LINK_DOWN;
4251 link.link_speed = ETH_SPEED_NUM_NONE;
4252 link.link_duplex = ETH_LINK_HALF_DUPLEX;
4253 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4254 ETH_LINK_SPEED_FIXED);
4256 hw->mac.get_link_status = true;
4258 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4259 return rte_eth_linkstatus_set(dev, &link);
4261 /* check if it needs to wait to complete, if lsc interrupt is enabled */
4262 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4266 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4268 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4271 link.link_speed = ETH_SPEED_NUM_100M;
4272 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4273 return rte_eth_linkstatus_set(dev, &link);
4276 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4277 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4278 if ((esdp_reg & IXGBE_ESDP_SDP3))
4283 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4284 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4285 if (ixgbe_dev_wait_setup_link_complete(dev) &&
4286 rte_atomic32_test_and_set(&ad->link_thread_running)) {
4287 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4288 "ixgbe-link-handler",
4290 ixgbe_dev_setup_link_thread_handler,
4293 "Create link thread failed!");
4294 rte_atomic32_clear(&ad->link_thread_running);
4298 "Other link thread is running now!");
4301 return rte_eth_linkstatus_set(dev, &link);
4304 link.link_status = ETH_LINK_UP;
4305 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4307 switch (link_speed) {
4309 case IXGBE_LINK_SPEED_UNKNOWN:
4310 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4311 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4312 link.link_speed = ETH_SPEED_NUM_10M;
4314 link.link_speed = ETH_SPEED_NUM_100M;
4317 case IXGBE_LINK_SPEED_100_FULL:
4318 link.link_speed = ETH_SPEED_NUM_100M;
4321 case IXGBE_LINK_SPEED_1GB_FULL:
4322 link.link_speed = ETH_SPEED_NUM_1G;
4325 case IXGBE_LINK_SPEED_2_5GB_FULL:
4326 link.link_speed = ETH_SPEED_NUM_2_5G;
4329 case IXGBE_LINK_SPEED_5GB_FULL:
4330 link.link_speed = ETH_SPEED_NUM_5G;
4333 case IXGBE_LINK_SPEED_10GB_FULL:
4334 link.link_speed = ETH_SPEED_NUM_10G;
4338 return rte_eth_linkstatus_set(dev, &link);
4342 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4344 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4348 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4350 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4354 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4356 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4359 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4360 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4361 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4367 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4369 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4372 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4373 fctrl &= (~IXGBE_FCTRL_UPE);
4374 if (dev->data->all_multicast == 1)
4375 fctrl |= IXGBE_FCTRL_MPE;
4377 fctrl &= (~IXGBE_FCTRL_MPE);
4378 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4384 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4386 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4389 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4390 fctrl |= IXGBE_FCTRL_MPE;
4391 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4397 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4399 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4402 if (dev->data->promiscuous == 1)
4403 return 0; /* must remain in all_multicast mode */
4405 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4406 fctrl &= (~IXGBE_FCTRL_MPE);
4407 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4413 * It clears the interrupt causes and enables the interrupt.
4414 * It will be called once only during nic initialized.
4417 * Pointer to struct rte_eth_dev.
4419 * Enable or Disable.
4422 * - On success, zero.
4423 * - On failure, a negative value.
4426 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4428 struct ixgbe_interrupt *intr =
4429 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4431 ixgbe_dev_link_status_print(dev);
4433 intr->mask |= IXGBE_EICR_LSC;
4435 intr->mask &= ~IXGBE_EICR_LSC;
4441 * It clears the interrupt causes and enables the interrupt.
4442 * It will be called once only during nic initialized.
4445 * Pointer to struct rte_eth_dev.
4448 * - On success, zero.
4449 * - On failure, a negative value.
4452 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4454 struct ixgbe_interrupt *intr =
4455 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4457 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4463 * It clears the interrupt causes and enables the interrupt.
4464 * It will be called once only during nic initialized.
4467 * Pointer to struct rte_eth_dev.
4470 * - On success, zero.
4471 * - On failure, a negative value.
4474 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4476 struct ixgbe_interrupt *intr =
4477 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4479 intr->mask |= IXGBE_EICR_LINKSEC;
4485 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4488 * Pointer to struct rte_eth_dev.
4491 * - On success, zero.
4492 * - On failure, a negative value.
4495 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4498 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4499 struct ixgbe_interrupt *intr =
4500 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4502 /* clear all cause mask */
4503 ixgbe_disable_intr(hw);
4505 /* read-on-clear nic registers here */
4506 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4507 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4511 /* set flag for async link update */
4512 if (eicr & IXGBE_EICR_LSC)
4513 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4515 if (eicr & IXGBE_EICR_MAILBOX)
4516 intr->flags |= IXGBE_FLAG_MAILBOX;
4518 if (eicr & IXGBE_EICR_LINKSEC)
4519 intr->flags |= IXGBE_FLAG_MACSEC;
4521 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4522 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4523 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4524 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4530 * It gets and then prints the link status.
4533 * Pointer to struct rte_eth_dev.
4536 * - On success, zero.
4537 * - On failure, a negative value.
4540 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4542 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4543 struct rte_eth_link link;
4545 rte_eth_linkstatus_get(dev, &link);
4547 if (link.link_status) {
4548 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4549 (int)(dev->data->port_id),
4550 (unsigned)link.link_speed,
4551 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4552 "full-duplex" : "half-duplex");
4554 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4555 (int)(dev->data->port_id));
4557 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4558 pci_dev->addr.domain,
4560 pci_dev->addr.devid,
4561 pci_dev->addr.function);
4565 * It executes link_update after knowing an interrupt occurred.
4568 * Pointer to struct rte_eth_dev.
4571 * - On success, zero.
4572 * - On failure, a negative value.
4575 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4577 struct ixgbe_interrupt *intr =
4578 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4580 struct ixgbe_hw *hw =
4581 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4583 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4585 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4586 ixgbe_pf_mbx_process(dev);
4587 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4590 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4591 ixgbe_handle_lasi(hw);
4592 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4595 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4596 struct rte_eth_link link;
4598 /* get the link status before link update, for predicting later */
4599 rte_eth_linkstatus_get(dev, &link);
4601 ixgbe_dev_link_update(dev, 0);
4604 if (!link.link_status)
4605 /* handle it 1 sec later, wait it being stable */
4606 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4607 /* likely to down */
4609 /* handle it 4 sec later, wait it being stable */
4610 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4612 ixgbe_dev_link_status_print(dev);
4613 if (rte_eal_alarm_set(timeout * 1000,
4614 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4615 PMD_DRV_LOG(ERR, "Error setting alarm");
4617 /* remember original mask */
4618 intr->mask_original = intr->mask;
4619 /* only disable lsc interrupt */
4620 intr->mask &= ~IXGBE_EIMS_LSC;
4624 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4625 ixgbe_enable_intr(dev);
4631 * Interrupt handler which shall be registered for alarm callback for delayed
4632 * handling specific interrupt to wait for the stable nic state. As the
4633 * NIC interrupt state is not stable for ixgbe after link is just down,
4634 * it needs to wait 4 seconds to get the stable status.
4637 * Pointer to interrupt handle.
4639 * The address of parameter (struct rte_eth_dev *) regsitered before.
4645 ixgbe_dev_interrupt_delayed_handler(void *param)
4647 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4648 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4649 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4650 struct ixgbe_interrupt *intr =
4651 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4652 struct ixgbe_hw *hw =
4653 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4656 ixgbe_disable_intr(hw);
4658 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4659 if (eicr & IXGBE_EICR_MAILBOX)
4660 ixgbe_pf_mbx_process(dev);
4662 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4663 ixgbe_handle_lasi(hw);
4664 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4667 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4668 ixgbe_dev_link_update(dev, 0);
4669 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4670 ixgbe_dev_link_status_print(dev);
4671 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4675 if (intr->flags & IXGBE_FLAG_MACSEC) {
4676 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4678 intr->flags &= ~IXGBE_FLAG_MACSEC;
4681 /* restore original mask */
4682 intr->mask = intr->mask_original;
4683 intr->mask_original = 0;
4685 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4686 ixgbe_enable_intr(dev);
4687 rte_intr_ack(intr_handle);
4691 * Interrupt handler triggered by NIC for handling
4692 * specific interrupt.
4695 * Pointer to interrupt handle.
4697 * The address of parameter (struct rte_eth_dev *) regsitered before.
4703 ixgbe_dev_interrupt_handler(void *param)
4705 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4707 ixgbe_dev_interrupt_get_status(dev);
4708 ixgbe_dev_interrupt_action(dev);
4712 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4714 struct ixgbe_hw *hw;
4716 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4717 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4721 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4723 struct ixgbe_hw *hw;
4725 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4726 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4730 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4732 struct ixgbe_hw *hw;
4738 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4740 fc_conf->pause_time = hw->fc.pause_time;
4741 fc_conf->high_water = hw->fc.high_water[0];
4742 fc_conf->low_water = hw->fc.low_water[0];
4743 fc_conf->send_xon = hw->fc.send_xon;
4744 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4747 * Return rx_pause status according to actual setting of
4750 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4751 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4757 * Return tx_pause status according to actual setting of
4760 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4761 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4766 if (rx_pause && tx_pause)
4767 fc_conf->mode = RTE_FC_FULL;
4769 fc_conf->mode = RTE_FC_RX_PAUSE;
4771 fc_conf->mode = RTE_FC_TX_PAUSE;
4773 fc_conf->mode = RTE_FC_NONE;
4779 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4781 struct ixgbe_hw *hw;
4782 struct ixgbe_adapter *adapter = dev->data->dev_private;
4784 uint32_t rx_buf_size;
4785 uint32_t max_high_water;
4786 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4793 PMD_INIT_FUNC_TRACE();
4795 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4796 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4797 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4800 * At least reserve one Ethernet frame for watermark
4801 * high_water/low_water in kilo bytes for ixgbe
4803 max_high_water = (rx_buf_size -
4804 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4805 if ((fc_conf->high_water > max_high_water) ||
4806 (fc_conf->high_water < fc_conf->low_water)) {
4807 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4808 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4812 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4813 hw->fc.pause_time = fc_conf->pause_time;
4814 hw->fc.high_water[0] = fc_conf->high_water;
4815 hw->fc.low_water[0] = fc_conf->low_water;
4816 hw->fc.send_xon = fc_conf->send_xon;
4817 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4818 adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4820 err = ixgbe_flow_ctrl_enable(dev, hw);
4822 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4829 * ixgbe_pfc_enable_generic - Enable flow control
4830 * @hw: pointer to hardware structure
4831 * @tc_num: traffic class number
4832 * Enable flow control according to the current settings.
4835 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4838 uint32_t mflcn_reg, fccfg_reg;
4840 uint32_t fcrtl, fcrth;
4844 /* Validate the water mark configuration */
4845 if (!hw->fc.pause_time) {
4846 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4850 /* Low water mark of zero causes XOFF floods */
4851 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4852 /* High/Low water can not be 0 */
4853 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4854 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4855 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4859 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4860 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4861 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4865 /* Negotiate the fc mode to use */
4866 ixgbe_fc_autoneg(hw);
4868 /* Disable any previous flow control settings */
4869 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4870 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4872 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4873 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4875 switch (hw->fc.current_mode) {
4878 * If the count of enabled RX Priority Flow control >1,
4879 * and the TX pause can not be disabled
4882 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4883 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4884 if (reg & IXGBE_FCRTH_FCEN)
4888 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4890 case ixgbe_fc_rx_pause:
4892 * Rx Flow control is enabled and Tx Flow control is
4893 * disabled by software override. Since there really
4894 * isn't a way to advertise that we are capable of RX
4895 * Pause ONLY, we will advertise that we support both
4896 * symmetric and asymmetric Rx PAUSE. Later, we will
4897 * disable the adapter's ability to send PAUSE frames.
4899 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4901 * If the count of enabled RX Priority Flow control >1,
4902 * and the TX pause can not be disabled
4905 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4906 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4907 if (reg & IXGBE_FCRTH_FCEN)
4911 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4913 case ixgbe_fc_tx_pause:
4915 * Tx Flow control is enabled, and Rx Flow control is
4916 * disabled by software override.
4918 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4921 /* Flow control (both Rx and Tx) is enabled by SW override. */
4922 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4923 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4926 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4927 ret_val = IXGBE_ERR_CONFIG;
4931 /* Set 802.3x based flow control settings. */
4932 mflcn_reg |= IXGBE_MFLCN_DPF;
4933 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4934 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4936 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4937 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4938 hw->fc.high_water[tc_num]) {
4939 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4940 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4941 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4943 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4945 * In order to prevent Tx hangs when the internal Tx
4946 * switch is enabled we must set the high water mark
4947 * to the maximum FCRTH value. This allows the Tx
4948 * switch to function even under heavy Rx workloads.
4950 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4952 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4954 /* Configure pause time (2 TCs per register) */
4955 reg = hw->fc.pause_time * 0x00010001;
4956 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4957 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4959 /* Configure flow control refresh threshold value */
4960 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4967 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4969 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4970 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4972 if (hw->mac.type != ixgbe_mac_82598EB) {
4973 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4979 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4982 uint32_t rx_buf_size;
4983 uint32_t max_high_water;
4985 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4986 struct ixgbe_hw *hw =
4987 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4988 struct ixgbe_dcb_config *dcb_config =
4989 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4991 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4998 PMD_INIT_FUNC_TRACE();
5000 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
5001 tc_num = map[pfc_conf->priority];
5002 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
5003 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
5005 * At least reserve one Ethernet frame for watermark
5006 * high_water/low_water in kilo bytes for ixgbe
5008 max_high_water = (rx_buf_size -
5009 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
5010 if ((pfc_conf->fc.high_water > max_high_water) ||
5011 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
5012 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
5013 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
5017 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
5018 hw->fc.pause_time = pfc_conf->fc.pause_time;
5019 hw->fc.send_xon = pfc_conf->fc.send_xon;
5020 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
5021 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
5023 err = ixgbe_dcb_pfc_enable(dev, tc_num);
5025 /* Not negotiated is not an error case */
5026 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5029 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5034 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5035 struct rte_eth_rss_reta_entry64 *reta_conf,
5038 uint16_t i, sp_reta_size;
5041 uint16_t idx, shift;
5042 struct ixgbe_adapter *adapter = dev->data->dev_private;
5043 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5046 PMD_INIT_FUNC_TRACE();
5048 if (!ixgbe_rss_update_sp(hw->mac.type)) {
5049 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5054 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5055 if (reta_size != sp_reta_size) {
5056 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5057 "(%d) doesn't match the number hardware can supported "
5058 "(%d)", reta_size, sp_reta_size);
5062 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5063 idx = i / RTE_RETA_GROUP_SIZE;
5064 shift = i % RTE_RETA_GROUP_SIZE;
5065 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5069 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5070 if (mask == IXGBE_4_BIT_MASK)
5073 r = IXGBE_READ_REG(hw, reta_reg);
5074 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5075 if (mask & (0x1 << j))
5076 reta |= reta_conf[idx].reta[shift + j] <<
5079 reta |= r & (IXGBE_8_BIT_MASK <<
5082 IXGBE_WRITE_REG(hw, reta_reg, reta);
5084 adapter->rss_reta_updated = 1;
5090 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5091 struct rte_eth_rss_reta_entry64 *reta_conf,
5094 uint16_t i, sp_reta_size;
5097 uint16_t idx, shift;
5098 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5101 PMD_INIT_FUNC_TRACE();
5102 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5103 if (reta_size != sp_reta_size) {
5104 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5105 "(%d) doesn't match the number hardware can supported "
5106 "(%d)", reta_size, sp_reta_size);
5110 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5111 idx = i / RTE_RETA_GROUP_SIZE;
5112 shift = i % RTE_RETA_GROUP_SIZE;
5113 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5118 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5119 reta = IXGBE_READ_REG(hw, reta_reg);
5120 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5121 if (mask & (0x1 << j))
5122 reta_conf[idx].reta[shift + j] =
5123 ((reta >> (CHAR_BIT * j)) &
5132 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5133 uint32_t index, uint32_t pool)
5135 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5136 uint32_t enable_addr = 1;
5138 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5143 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5145 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5147 ixgbe_clear_rar(hw, index);
5151 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5153 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5155 ixgbe_remove_rar(dev, 0);
5156 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5162 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5164 if (strcmp(dev->device->driver->name, drv->driver.name))
5171 is_ixgbe_supported(struct rte_eth_dev *dev)
5173 return is_device_supported(dev, &rte_ixgbe_pmd);
5177 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5181 struct ixgbe_hw *hw;
5182 struct rte_eth_dev_info dev_info;
5183 uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5184 struct rte_eth_dev_data *dev_data = dev->data;
5187 ret = ixgbe_dev_info_get(dev, &dev_info);
5191 /* check that mtu is within the allowed range */
5192 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5195 /* If device is started, refuse mtu that requires the support of
5196 * scattered packets when this feature has not been enabled before.
5198 if (dev_data->dev_started && !dev_data->scattered_rx &&
5199 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5200 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5201 PMD_INIT_LOG(ERR, "Stop port first.");
5205 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5206 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5208 /* switch to jumbo mode if needed */
5209 if (frame_size > RTE_ETHER_MAX_LEN) {
5210 dev->data->dev_conf.rxmode.offloads |=
5211 DEV_RX_OFFLOAD_JUMBO_FRAME;
5212 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5214 dev->data->dev_conf.rxmode.offloads &=
5215 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5216 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5218 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5220 /* update max frame size */
5221 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5223 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5224 maxfrs &= 0x0000FFFF;
5225 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5226 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5232 * Virtual Function operations
5235 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5237 struct ixgbe_interrupt *intr =
5238 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5239 struct ixgbe_hw *hw =
5240 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5242 PMD_INIT_FUNC_TRACE();
5244 /* Clear interrupt mask to stop from interrupts being generated */
5245 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5247 IXGBE_WRITE_FLUSH(hw);
5249 /* Clear mask value. */
5254 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5256 struct ixgbe_interrupt *intr =
5257 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5258 struct ixgbe_hw *hw =
5259 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5261 PMD_INIT_FUNC_TRACE();
5263 /* VF enable interrupt autoclean */
5264 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5265 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5266 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5268 IXGBE_WRITE_FLUSH(hw);
5270 /* Save IXGBE_VTEIMS value to mask. */
5271 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5275 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5277 struct rte_eth_conf *conf = &dev->data->dev_conf;
5278 struct ixgbe_adapter *adapter = dev->data->dev_private;
5280 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5281 dev->data->port_id);
5283 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5284 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5287 * VF has no ability to enable/disable HW CRC
5288 * Keep the persistent behavior the same as Host PF
5290 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5291 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5292 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5293 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5296 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5297 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5298 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5303 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5304 * allocation or vector Rx preconditions we will reset it.
5306 adapter->rx_bulk_alloc_allowed = true;
5307 adapter->rx_vec_allowed = true;
5313 ixgbevf_dev_start(struct rte_eth_dev *dev)
5315 struct ixgbe_hw *hw =
5316 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5317 uint32_t intr_vector = 0;
5318 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5319 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5323 PMD_INIT_FUNC_TRACE();
5325 /* Stop the link setup handler before resetting the HW. */
5326 ixgbe_dev_cancel_link_thread(dev);
5328 err = hw->mac.ops.reset_hw(hw);
5330 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5333 hw->mac.get_link_status = true;
5335 /* negotiate mailbox API version to use with the PF. */
5336 ixgbevf_negotiate_api(hw);
5338 ixgbevf_dev_tx_init(dev);
5340 /* This can fail when allocating mbufs for descriptor rings */
5341 err = ixgbevf_dev_rx_init(dev);
5343 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5344 ixgbe_dev_clear_queues(dev);
5349 ixgbevf_set_vfta_all(dev, 1);
5352 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5353 ETH_VLAN_EXTEND_MASK;
5354 err = ixgbevf_vlan_offload_config(dev, mask);
5356 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5357 ixgbe_dev_clear_queues(dev);
5361 ixgbevf_dev_rxtx_start(dev);
5363 /* check and configure queue intr-vector mapping */
5364 if (rte_intr_cap_multiple(intr_handle) &&
5365 dev->data->dev_conf.intr_conf.rxq) {
5366 /* According to datasheet, only vector 0/1/2 can be used,
5367 * now only one vector is used for Rx queue
5370 if (rte_intr_efd_enable(intr_handle, intr_vector))
5374 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5375 intr_handle->intr_vec =
5376 rte_zmalloc("intr_vec",
5377 dev->data->nb_rx_queues * sizeof(int), 0);
5378 if (intr_handle->intr_vec == NULL) {
5379 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5380 " intr_vec", dev->data->nb_rx_queues);
5384 ixgbevf_configure_msix(dev);
5386 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5387 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5388 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5389 * is not cleared, it will fail when following rte_intr_enable( ) tries
5390 * to map Rx queue interrupt to other VFIO vectors.
5391 * So clear uio/vfio intr/evevnfd first to avoid failure.
5393 rte_intr_disable(intr_handle);
5395 rte_intr_enable(intr_handle);
5397 /* Re-enable interrupt for VF */
5398 ixgbevf_intr_enable(dev);
5401 * Update link status right before return, because it may
5402 * start link configuration process in a separate thread.
5404 ixgbevf_dev_link_update(dev, 0);
5406 hw->adapter_stopped = false;
5412 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5414 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5415 struct ixgbe_adapter *adapter = dev->data->dev_private;
5416 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5417 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5419 if (hw->adapter_stopped)
5422 PMD_INIT_FUNC_TRACE();
5424 ixgbe_dev_cancel_link_thread(dev);
5426 ixgbevf_intr_disable(dev);
5428 hw->adapter_stopped = 1;
5429 ixgbe_stop_adapter(hw);
5432 * Clear what we set, but we still keep shadow_vfta to
5433 * restore after device starts
5435 ixgbevf_set_vfta_all(dev, 0);
5437 /* Clear stored conf */
5438 dev->data->scattered_rx = 0;
5440 ixgbe_dev_clear_queues(dev);
5442 /* Clean datapath event and queue/vec mapping */
5443 rte_intr_efd_disable(intr_handle);
5444 if (intr_handle->intr_vec != NULL) {
5445 rte_free(intr_handle->intr_vec);
5446 intr_handle->intr_vec = NULL;
5449 adapter->rss_reta_updated = 0;
5453 ixgbevf_dev_close(struct rte_eth_dev *dev)
5455 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5456 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5457 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5459 PMD_INIT_FUNC_TRACE();
5463 ixgbevf_dev_stop(dev);
5465 ixgbe_dev_free_queues(dev);
5468 * Remove the VF MAC address ro ensure
5469 * that the VF traffic goes to the PF
5470 * after stop, close and detach of the VF
5472 ixgbevf_remove_mac_addr(dev, 0);
5474 dev->dev_ops = NULL;
5475 dev->rx_pkt_burst = NULL;
5476 dev->tx_pkt_burst = NULL;
5478 rte_intr_disable(intr_handle);
5479 rte_intr_callback_unregister(intr_handle,
5480 ixgbevf_dev_interrupt_handler, dev);
5487 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5491 ret = eth_ixgbevf_dev_uninit(dev);
5495 ret = eth_ixgbevf_dev_init(dev);
5500 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5502 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5503 struct ixgbe_vfta *shadow_vfta =
5504 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5505 int i = 0, j = 0, vfta = 0, mask = 1;
5507 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5508 vfta = shadow_vfta->vfta[i];
5511 for (j = 0; j < 32; j++) {
5513 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5523 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5525 struct ixgbe_hw *hw =
5526 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5527 struct ixgbe_vfta *shadow_vfta =
5528 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5529 uint32_t vid_idx = 0;
5530 uint32_t vid_bit = 0;
5533 PMD_INIT_FUNC_TRACE();
5535 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5536 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5538 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5541 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5542 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5544 /* Save what we set and retore it after device reset */
5546 shadow_vfta->vfta[vid_idx] |= vid_bit;
5548 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5554 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5556 struct ixgbe_hw *hw =
5557 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5560 PMD_INIT_FUNC_TRACE();
5562 if (queue >= hw->mac.max_rx_queues)
5565 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5567 ctrl |= IXGBE_RXDCTL_VME;
5569 ctrl &= ~IXGBE_RXDCTL_VME;
5570 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5572 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5576 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5578 struct ixgbe_rx_queue *rxq;
5582 /* VF function only support hw strip feature, others are not support */
5583 if (mask & ETH_VLAN_STRIP_MASK) {
5584 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5585 rxq = dev->data->rx_queues[i];
5586 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5587 ixgbevf_vlan_strip_queue_set(dev, i, on);
5595 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5597 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5599 ixgbevf_vlan_offload_config(dev, mask);
5605 ixgbe_vt_check(struct ixgbe_hw *hw)
5609 /* if Virtualization Technology is enabled */
5610 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5611 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5612 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5620 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5622 uint32_t vector = 0;
5624 switch (hw->mac.mc_filter_type) {
5625 case 0: /* use bits [47:36] of the address */
5626 vector = ((uc_addr->addr_bytes[4] >> 4) |
5627 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5629 case 1: /* use bits [46:35] of the address */
5630 vector = ((uc_addr->addr_bytes[4] >> 3) |
5631 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5633 case 2: /* use bits [45:34] of the address */
5634 vector = ((uc_addr->addr_bytes[4] >> 2) |
5635 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5637 case 3: /* use bits [43:32] of the address */
5638 vector = ((uc_addr->addr_bytes[4]) |
5639 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5641 default: /* Invalid mc_filter_type */
5645 /* vector can only be 12-bits or boundary will be exceeded */
5651 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5652 struct rte_ether_addr *mac_addr, uint8_t on)
5659 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5660 const uint32_t ixgbe_uta_bit_shift = 5;
5661 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5662 const uint32_t bit1 = 0x1;
5664 struct ixgbe_hw *hw =
5665 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5666 struct ixgbe_uta_info *uta_info =
5667 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5669 /* The UTA table only exists on 82599 hardware and newer */
5670 if (hw->mac.type < ixgbe_mac_82599EB)
5673 vector = ixgbe_uta_vector(hw, mac_addr);
5674 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5675 uta_shift = vector & ixgbe_uta_bit_mask;
5677 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5681 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5683 uta_info->uta_in_use++;
5684 reg_val |= (bit1 << uta_shift);
5685 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5687 uta_info->uta_in_use--;
5688 reg_val &= ~(bit1 << uta_shift);
5689 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5692 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5694 if (uta_info->uta_in_use > 0)
5695 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5696 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5698 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5704 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5707 struct ixgbe_hw *hw =
5708 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5709 struct ixgbe_uta_info *uta_info =
5710 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5712 /* The UTA table only exists on 82599 hardware and newer */
5713 if (hw->mac.type < ixgbe_mac_82599EB)
5717 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5718 uta_info->uta_shadow[i] = ~0;
5719 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5722 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5723 uta_info->uta_shadow[i] = 0;
5724 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5732 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5734 uint32_t new_val = orig_val;
5736 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5737 new_val |= IXGBE_VMOLR_AUPE;
5738 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5739 new_val |= IXGBE_VMOLR_ROMPE;
5740 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5741 new_val |= IXGBE_VMOLR_ROPE;
5742 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5743 new_val |= IXGBE_VMOLR_BAM;
5744 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5745 new_val |= IXGBE_VMOLR_MPE;
5750 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5751 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5752 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5753 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5754 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5755 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5756 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5759 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5760 struct rte_eth_mirror_conf *mirror_conf,
5761 uint8_t rule_id, uint8_t on)
5763 uint32_t mr_ctl, vlvf;
5764 uint32_t mp_lsb = 0;
5765 uint32_t mv_msb = 0;
5766 uint32_t mv_lsb = 0;
5767 uint32_t mp_msb = 0;
5770 uint64_t vlan_mask = 0;
5772 const uint8_t pool_mask_offset = 32;
5773 const uint8_t vlan_mask_offset = 32;
5774 const uint8_t dst_pool_offset = 8;
5775 const uint8_t rule_mr_offset = 4;
5776 const uint8_t mirror_rule_mask = 0x0F;
5778 struct ixgbe_mirror_info *mr_info =
5779 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5780 struct ixgbe_hw *hw =
5781 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5782 uint8_t mirror_type = 0;
5784 if (ixgbe_vt_check(hw) < 0)
5787 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5790 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5791 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5792 mirror_conf->rule_type);
5796 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5797 mirror_type |= IXGBE_MRCTL_VLME;
5798 /* Check if vlan id is valid and find conresponding VLAN ID
5801 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5802 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5803 /* search vlan id related pool vlan filter
5806 reg_index = ixgbe_find_vlvf_slot(
5808 mirror_conf->vlan.vlan_id[i],
5812 vlvf = IXGBE_READ_REG(hw,
5813 IXGBE_VLVF(reg_index));
5814 if ((vlvf & IXGBE_VLVF_VIEN) &&
5815 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5816 mirror_conf->vlan.vlan_id[i]))
5817 vlan_mask |= (1ULL << reg_index);
5824 mv_lsb = vlan_mask & 0xFFFFFFFF;
5825 mv_msb = vlan_mask >> vlan_mask_offset;
5827 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5828 mirror_conf->vlan.vlan_mask;
5829 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5830 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5831 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5832 mirror_conf->vlan.vlan_id[i];
5837 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5838 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5839 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5844 * if enable pool mirror, write related pool mask register,if disable
5845 * pool mirror, clear PFMRVM register
5847 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5848 mirror_type |= IXGBE_MRCTL_VPME;
5850 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5851 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5852 mr_info->mr_conf[rule_id].pool_mask =
5853 mirror_conf->pool_mask;
5858 mr_info->mr_conf[rule_id].pool_mask = 0;
5861 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5862 mirror_type |= IXGBE_MRCTL_UPME;
5863 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5864 mirror_type |= IXGBE_MRCTL_DPME;
5866 /* read mirror control register and recalculate it */
5867 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5870 mr_ctl |= mirror_type;
5871 mr_ctl &= mirror_rule_mask;
5872 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5874 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5877 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5878 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5880 /* write mirrror control register */
5881 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5883 /* write pool mirrror control register */
5884 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5885 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5886 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5889 /* write VLAN mirrror control register */
5890 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5891 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5892 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5900 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5903 uint32_t lsb_val = 0;
5904 uint32_t msb_val = 0;
5905 const uint8_t rule_mr_offset = 4;
5907 struct ixgbe_hw *hw =
5908 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5909 struct ixgbe_mirror_info *mr_info =
5910 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5912 if (ixgbe_vt_check(hw) < 0)
5915 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5918 memset(&mr_info->mr_conf[rule_id], 0,
5919 sizeof(struct rte_eth_mirror_conf));
5921 /* clear PFVMCTL register */
5922 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5924 /* clear pool mask register */
5925 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5926 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5928 /* clear vlan mask register */
5929 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5930 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5936 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5938 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5939 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5940 struct ixgbe_interrupt *intr =
5941 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5942 struct ixgbe_hw *hw =
5943 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5944 uint32_t vec = IXGBE_MISC_VEC_ID;
5946 if (rte_intr_allow_others(intr_handle))
5947 vec = IXGBE_RX_VEC_START;
5948 intr->mask |= (1 << vec);
5949 RTE_SET_USED(queue_id);
5950 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5952 rte_intr_ack(intr_handle);
5958 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5960 struct ixgbe_interrupt *intr =
5961 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5962 struct ixgbe_hw *hw =
5963 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5964 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5965 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5966 uint32_t vec = IXGBE_MISC_VEC_ID;
5968 if (rte_intr_allow_others(intr_handle))
5969 vec = IXGBE_RX_VEC_START;
5970 intr->mask &= ~(1 << vec);
5971 RTE_SET_USED(queue_id);
5972 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5978 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5980 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5981 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5983 struct ixgbe_hw *hw =
5984 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5985 struct ixgbe_interrupt *intr =
5986 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5988 if (queue_id < 16) {
5989 ixgbe_disable_intr(hw);
5990 intr->mask |= (1 << queue_id);
5991 ixgbe_enable_intr(dev);
5992 } else if (queue_id < 32) {
5993 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5994 mask &= (1 << queue_id);
5995 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5996 } else if (queue_id < 64) {
5997 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5998 mask &= (1 << (queue_id - 32));
5999 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6001 rte_intr_ack(intr_handle);
6007 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
6010 struct ixgbe_hw *hw =
6011 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6012 struct ixgbe_interrupt *intr =
6013 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
6015 if (queue_id < 16) {
6016 ixgbe_disable_intr(hw);
6017 intr->mask &= ~(1 << queue_id);
6018 ixgbe_enable_intr(dev);
6019 } else if (queue_id < 32) {
6020 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6021 mask &= ~(1 << queue_id);
6022 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6023 } else if (queue_id < 64) {
6024 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6025 mask &= ~(1 << (queue_id - 32));
6026 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6033 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6034 uint8_t queue, uint8_t msix_vector)
6038 if (direction == -1) {
6040 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6041 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6044 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6046 /* rx or tx cause */
6047 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6048 idx = ((16 * (queue & 1)) + (8 * direction));
6049 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6050 tmp &= ~(0xFF << idx);
6051 tmp |= (msix_vector << idx);
6052 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6057 * set the IVAR registers, mapping interrupt causes to vectors
6059 * pointer to ixgbe_hw struct
6061 * 0 for Rx, 1 for Tx, -1 for other causes
6063 * queue to map the corresponding interrupt to
6065 * the vector to map to the corresponding queue
6068 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6069 uint8_t queue, uint8_t msix_vector)
6073 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6074 if (hw->mac.type == ixgbe_mac_82598EB) {
6075 if (direction == -1)
6077 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6078 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6079 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6080 tmp |= (msix_vector << (8 * (queue & 0x3)));
6081 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6082 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6083 (hw->mac.type == ixgbe_mac_X540) ||
6084 (hw->mac.type == ixgbe_mac_X550) ||
6085 (hw->mac.type == ixgbe_mac_X550EM_x)) {
6086 if (direction == -1) {
6088 idx = ((queue & 1) * 8);
6089 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6090 tmp &= ~(0xFF << idx);
6091 tmp |= (msix_vector << idx);
6092 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6094 /* rx or tx causes */
6095 idx = ((16 * (queue & 1)) + (8 * direction));
6096 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6097 tmp &= ~(0xFF << idx);
6098 tmp |= (msix_vector << idx);
6099 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6105 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6107 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6108 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6109 struct ixgbe_hw *hw =
6110 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6112 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6113 uint32_t base = IXGBE_MISC_VEC_ID;
6115 /* Configure VF other cause ivar */
6116 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6118 /* won't configure msix register if no mapping is done
6119 * between intr vector and event fd.
6121 if (!rte_intr_dp_is_en(intr_handle))
6124 if (rte_intr_allow_others(intr_handle)) {
6125 base = IXGBE_RX_VEC_START;
6126 vector_idx = IXGBE_RX_VEC_START;
6129 /* Configure all RX queues of VF */
6130 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6131 /* Force all queue use vector 0,
6132 * as IXGBE_VF_MAXMSIVECOTR = 1
6134 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6135 intr_handle->intr_vec[q_idx] = vector_idx;
6136 if (vector_idx < base + intr_handle->nb_efd - 1)
6140 /* As RX queue setting above show, all queues use the vector 0.
6141 * Set only the ITR value of IXGBE_MISC_VEC_ID.
6143 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6144 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6145 | IXGBE_EITR_CNT_WDIS);
6149 * Sets up the hardware to properly generate MSI-X interrupts
6151 * board private structure
6154 ixgbe_configure_msix(struct rte_eth_dev *dev)
6156 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6157 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6158 struct ixgbe_hw *hw =
6159 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6160 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6161 uint32_t vec = IXGBE_MISC_VEC_ID;
6165 /* won't configure msix register if no mapping is done
6166 * between intr vector and event fd
6167 * but if misx has been enabled already, need to configure
6168 * auto clean, auto mask and throttling.
6170 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6171 if (!rte_intr_dp_is_en(intr_handle) &&
6172 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6175 if (rte_intr_allow_others(intr_handle))
6176 vec = base = IXGBE_RX_VEC_START;
6178 /* setup GPIE for MSI-x mode */
6179 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6180 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6181 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6182 /* auto clearing and auto setting corresponding bits in EIMS
6183 * when MSI-X interrupt is triggered
6185 if (hw->mac.type == ixgbe_mac_82598EB) {
6186 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6188 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6189 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6191 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6193 /* Populate the IVAR table and set the ITR values to the
6194 * corresponding register.
6196 if (rte_intr_dp_is_en(intr_handle)) {
6197 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6199 /* by default, 1:1 mapping */
6200 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6201 intr_handle->intr_vec[queue_id] = vec;
6202 if (vec < base + intr_handle->nb_efd - 1)
6206 switch (hw->mac.type) {
6207 case ixgbe_mac_82598EB:
6208 ixgbe_set_ivar_map(hw, -1,
6209 IXGBE_IVAR_OTHER_CAUSES_INDEX,
6212 case ixgbe_mac_82599EB:
6213 case ixgbe_mac_X540:
6214 case ixgbe_mac_X550:
6215 case ixgbe_mac_X550EM_x:
6216 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6222 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6223 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6224 | IXGBE_EITR_CNT_WDIS);
6226 /* set up to autoclear timer, and the vectors */
6227 mask = IXGBE_EIMS_ENABLE_MASK;
6228 mask &= ~(IXGBE_EIMS_OTHER |
6229 IXGBE_EIMS_MAILBOX |
6232 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6236 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6237 uint16_t queue_idx, uint16_t tx_rate)
6239 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6240 struct rte_eth_rxmode *rxmode;
6241 uint32_t rf_dec, rf_int;
6243 uint16_t link_speed = dev->data->dev_link.link_speed;
6245 if (queue_idx >= hw->mac.max_tx_queues)
6249 /* Calculate the rate factor values to set */
6250 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6251 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6252 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6254 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6255 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6256 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6257 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6262 rxmode = &dev->data->dev_conf.rxmode;
6264 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6265 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6268 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6269 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6270 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6271 IXGBE_MMW_SIZE_JUMBO_FRAME);
6273 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6274 IXGBE_MMW_SIZE_DEFAULT);
6276 /* Set RTTBCNRC of queue X */
6277 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6278 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6279 IXGBE_WRITE_FLUSH(hw);
6285 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6286 __rte_unused uint32_t index,
6287 __rte_unused uint32_t pool)
6289 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6293 * On a 82599 VF, adding again the same MAC addr is not an idempotent
6294 * operation. Trap this case to avoid exhausting the [very limited]
6295 * set of PF resources used to store VF MAC addresses.
6297 if (memcmp(hw->mac.perm_addr, mac_addr,
6298 sizeof(struct rte_ether_addr)) == 0)
6300 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6302 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6303 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6304 mac_addr->addr_bytes[0],
6305 mac_addr->addr_bytes[1],
6306 mac_addr->addr_bytes[2],
6307 mac_addr->addr_bytes[3],
6308 mac_addr->addr_bytes[4],
6309 mac_addr->addr_bytes[5],
6315 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6317 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6318 struct rte_ether_addr *perm_addr =
6319 (struct rte_ether_addr *)hw->mac.perm_addr;
6320 struct rte_ether_addr *mac_addr;
6325 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6326 * not support the deletion of a given MAC address.
6327 * Instead, it imposes to delete all MAC addresses, then to add again
6328 * all MAC addresses with the exception of the one to be deleted.
6330 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6333 * Add again all MAC addresses, with the exception of the deleted one
6334 * and of the permanent MAC address.
6336 for (i = 0, mac_addr = dev->data->mac_addrs;
6337 i < hw->mac.num_rar_entries; i++, mac_addr++) {
6338 /* Skip the deleted MAC address */
6341 /* Skip NULL MAC addresses */
6342 if (rte_is_zero_ether_addr(mac_addr))
6344 /* Skip the permanent MAC address */
6345 if (memcmp(perm_addr, mac_addr,
6346 sizeof(struct rte_ether_addr)) == 0)
6348 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6351 "Adding again MAC address "
6352 "%02x:%02x:%02x:%02x:%02x:%02x failed "
6354 mac_addr->addr_bytes[0],
6355 mac_addr->addr_bytes[1],
6356 mac_addr->addr_bytes[2],
6357 mac_addr->addr_bytes[3],
6358 mac_addr->addr_bytes[4],
6359 mac_addr->addr_bytes[5],
6365 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6366 struct rte_ether_addr *addr)
6368 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6370 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6376 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6377 struct rte_eth_syn_filter *filter,
6380 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6381 struct ixgbe_filter_info *filter_info =
6382 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6386 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6389 syn_info = filter_info->syn_info;
6392 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6394 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6395 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6397 if (filter->hig_pri)
6398 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6400 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6402 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6403 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6405 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6408 filter_info->syn_info = synqf;
6409 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6410 IXGBE_WRITE_FLUSH(hw);
6415 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6416 struct rte_eth_syn_filter *filter)
6418 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6419 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6421 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6422 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6423 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6430 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6431 enum rte_filter_op filter_op,
6434 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6437 MAC_TYPE_FILTER_SUP(hw->mac.type);
6439 if (filter_op == RTE_ETH_FILTER_NOP)
6443 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6448 switch (filter_op) {
6449 case RTE_ETH_FILTER_ADD:
6450 ret = ixgbe_syn_filter_set(dev,
6451 (struct rte_eth_syn_filter *)arg,
6454 case RTE_ETH_FILTER_DELETE:
6455 ret = ixgbe_syn_filter_set(dev,
6456 (struct rte_eth_syn_filter *)arg,
6459 case RTE_ETH_FILTER_GET:
6460 ret = ixgbe_syn_filter_get(dev,
6461 (struct rte_eth_syn_filter *)arg);
6464 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6473 static inline enum ixgbe_5tuple_protocol
6474 convert_protocol_type(uint8_t protocol_value)
6476 if (protocol_value == IPPROTO_TCP)
6477 return IXGBE_FILTER_PROTOCOL_TCP;
6478 else if (protocol_value == IPPROTO_UDP)
6479 return IXGBE_FILTER_PROTOCOL_UDP;
6480 else if (protocol_value == IPPROTO_SCTP)
6481 return IXGBE_FILTER_PROTOCOL_SCTP;
6483 return IXGBE_FILTER_PROTOCOL_NONE;
6486 /* inject a 5-tuple filter to HW */
6488 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6489 struct ixgbe_5tuple_filter *filter)
6491 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6493 uint32_t ftqf, sdpqf;
6494 uint32_t l34timir = 0;
6495 uint8_t mask = 0xff;
6499 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6500 IXGBE_SDPQF_DSTPORT_SHIFT);
6501 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6503 ftqf = (uint32_t)(filter->filter_info.proto &
6504 IXGBE_FTQF_PROTOCOL_MASK);
6505 ftqf |= (uint32_t)((filter->filter_info.priority &
6506 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6507 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6508 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6509 if (filter->filter_info.dst_ip_mask == 0)
6510 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6511 if (filter->filter_info.src_port_mask == 0)
6512 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6513 if (filter->filter_info.dst_port_mask == 0)
6514 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6515 if (filter->filter_info.proto_mask == 0)
6516 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6517 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6518 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6519 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6521 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6522 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6523 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6524 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6526 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6527 l34timir |= (uint32_t)(filter->queue <<
6528 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6529 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6533 * add a 5tuple filter
6536 * dev: Pointer to struct rte_eth_dev.
6537 * index: the index the filter allocates.
6538 * filter: ponter to the filter that will be added.
6539 * rx_queue: the queue id the filter assigned to.
6542 * - On success, zero.
6543 * - On failure, a negative value.
6546 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6547 struct ixgbe_5tuple_filter *filter)
6549 struct ixgbe_filter_info *filter_info =
6550 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6554 * look for an unused 5tuple filter index,
6555 * and insert the filter to list.
6557 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6558 idx = i / (sizeof(uint32_t) * NBBY);
6559 shift = i % (sizeof(uint32_t) * NBBY);
6560 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6561 filter_info->fivetuple_mask[idx] |= 1 << shift;
6563 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6569 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6570 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6574 ixgbe_inject_5tuple_filter(dev, filter);
6580 * remove a 5tuple filter
6583 * dev: Pointer to struct rte_eth_dev.
6584 * filter: the pointer of the filter will be removed.
6587 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6588 struct ixgbe_5tuple_filter *filter)
6590 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6591 struct ixgbe_filter_info *filter_info =
6592 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6593 uint16_t index = filter->index;
6595 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6596 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6597 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6600 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6601 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6602 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6603 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6604 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6608 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6610 struct ixgbe_hw *hw;
6611 uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6612 struct rte_eth_dev_data *dev_data = dev->data;
6614 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6616 if (mtu < RTE_ETHER_MIN_MTU ||
6617 max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6620 /* If device is started, refuse mtu that requires the support of
6621 * scattered packets when this feature has not been enabled before.
6623 if (dev_data->dev_started && !dev_data->scattered_rx &&
6624 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6625 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6626 PMD_INIT_LOG(ERR, "Stop port first.");
6631 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6632 * request of the version 2.0 of the mailbox API.
6633 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6634 * of the mailbox API.
6635 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6636 * prior to 3.11.33 which contains the following change:
6637 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6639 ixgbevf_rlpml_set_vf(hw, max_frame);
6641 /* update max frame size */
6642 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6646 static inline struct ixgbe_5tuple_filter *
6647 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6648 struct ixgbe_5tuple_filter_info *key)
6650 struct ixgbe_5tuple_filter *it;
6652 TAILQ_FOREACH(it, filter_list, entries) {
6653 if (memcmp(key, &it->filter_info,
6654 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6661 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6663 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6664 struct ixgbe_5tuple_filter_info *filter_info)
6666 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6667 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6668 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6671 switch (filter->dst_ip_mask) {
6673 filter_info->dst_ip_mask = 0;
6674 filter_info->dst_ip = filter->dst_ip;
6677 filter_info->dst_ip_mask = 1;
6680 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6684 switch (filter->src_ip_mask) {
6686 filter_info->src_ip_mask = 0;
6687 filter_info->src_ip = filter->src_ip;
6690 filter_info->src_ip_mask = 1;
6693 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6697 switch (filter->dst_port_mask) {
6699 filter_info->dst_port_mask = 0;
6700 filter_info->dst_port = filter->dst_port;
6703 filter_info->dst_port_mask = 1;
6706 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6710 switch (filter->src_port_mask) {
6712 filter_info->src_port_mask = 0;
6713 filter_info->src_port = filter->src_port;
6716 filter_info->src_port_mask = 1;
6719 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6723 switch (filter->proto_mask) {
6725 filter_info->proto_mask = 0;
6726 filter_info->proto =
6727 convert_protocol_type(filter->proto);
6730 filter_info->proto_mask = 1;
6733 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6737 filter_info->priority = (uint8_t)filter->priority;
6742 * add or delete a ntuple filter
6745 * dev: Pointer to struct rte_eth_dev.
6746 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6747 * add: if true, add filter, if false, remove filter
6750 * - On success, zero.
6751 * - On failure, a negative value.
6754 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6755 struct rte_eth_ntuple_filter *ntuple_filter,
6758 struct ixgbe_filter_info *filter_info =
6759 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6760 struct ixgbe_5tuple_filter_info filter_5tuple;
6761 struct ixgbe_5tuple_filter *filter;
6764 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6765 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6769 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6770 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6774 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6776 if (filter != NULL && add) {
6777 PMD_DRV_LOG(ERR, "filter exists.");
6780 if (filter == NULL && !add) {
6781 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6786 filter = rte_zmalloc("ixgbe_5tuple_filter",
6787 sizeof(struct ixgbe_5tuple_filter), 0);
6790 rte_memcpy(&filter->filter_info,
6792 sizeof(struct ixgbe_5tuple_filter_info));
6793 filter->queue = ntuple_filter->queue;
6794 ret = ixgbe_add_5tuple_filter(dev, filter);
6800 ixgbe_remove_5tuple_filter(dev, filter);
6806 * get a ntuple filter
6809 * dev: Pointer to struct rte_eth_dev.
6810 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6813 * - On success, zero.
6814 * - On failure, a negative value.
6817 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6818 struct rte_eth_ntuple_filter *ntuple_filter)
6820 struct ixgbe_filter_info *filter_info =
6821 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6822 struct ixgbe_5tuple_filter_info filter_5tuple;
6823 struct ixgbe_5tuple_filter *filter;
6826 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6827 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6831 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6832 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6836 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6838 if (filter == NULL) {
6839 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6842 ntuple_filter->queue = filter->queue;
6847 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6848 * @dev: pointer to rte_eth_dev structure
6849 * @filter_op:operation will be taken.
6850 * @arg: a pointer to specific structure corresponding to the filter_op
6853 * - On success, zero.
6854 * - On failure, a negative value.
6857 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6858 enum rte_filter_op filter_op,
6861 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6864 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6866 if (filter_op == RTE_ETH_FILTER_NOP)
6870 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6875 switch (filter_op) {
6876 case RTE_ETH_FILTER_ADD:
6877 ret = ixgbe_add_del_ntuple_filter(dev,
6878 (struct rte_eth_ntuple_filter *)arg,
6881 case RTE_ETH_FILTER_DELETE:
6882 ret = ixgbe_add_del_ntuple_filter(dev,
6883 (struct rte_eth_ntuple_filter *)arg,
6886 case RTE_ETH_FILTER_GET:
6887 ret = ixgbe_get_ntuple_filter(dev,
6888 (struct rte_eth_ntuple_filter *)arg);
6891 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6899 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6900 struct rte_eth_ethertype_filter *filter,
6903 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6904 struct ixgbe_filter_info *filter_info =
6905 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6909 struct ixgbe_ethertype_filter ethertype_filter;
6911 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6914 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6915 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6916 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6917 " ethertype filter.", filter->ether_type);
6921 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6922 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6925 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6926 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6930 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6931 if (ret >= 0 && add) {
6932 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6933 filter->ether_type);
6936 if (ret < 0 && !add) {
6937 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6938 filter->ether_type);
6943 etqf = IXGBE_ETQF_FILTER_EN;
6944 etqf |= (uint32_t)filter->ether_type;
6945 etqs |= (uint32_t)((filter->queue <<
6946 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6947 IXGBE_ETQS_RX_QUEUE);
6948 etqs |= IXGBE_ETQS_QUEUE_EN;
6950 ethertype_filter.ethertype = filter->ether_type;
6951 ethertype_filter.etqf = etqf;
6952 ethertype_filter.etqs = etqs;
6953 ethertype_filter.conf = FALSE;
6954 ret = ixgbe_ethertype_filter_insert(filter_info,
6957 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6961 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6965 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6966 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6967 IXGBE_WRITE_FLUSH(hw);
6973 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6974 struct rte_eth_ethertype_filter *filter)
6976 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6977 struct ixgbe_filter_info *filter_info =
6978 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6979 uint32_t etqf, etqs;
6982 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6984 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6985 filter->ether_type);
6989 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6990 if (etqf & IXGBE_ETQF_FILTER_EN) {
6991 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6992 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6994 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6995 IXGBE_ETQS_RX_QUEUE_SHIFT;
7002 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
7003 * @dev: pointer to rte_eth_dev structure
7004 * @filter_op:operation will be taken.
7005 * @arg: a pointer to specific structure corresponding to the filter_op
7008 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
7009 enum rte_filter_op filter_op,
7012 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7015 MAC_TYPE_FILTER_SUP(hw->mac.type);
7017 if (filter_op == RTE_ETH_FILTER_NOP)
7021 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7026 switch (filter_op) {
7027 case RTE_ETH_FILTER_ADD:
7028 ret = ixgbe_add_del_ethertype_filter(dev,
7029 (struct rte_eth_ethertype_filter *)arg,
7032 case RTE_ETH_FILTER_DELETE:
7033 ret = ixgbe_add_del_ethertype_filter(dev,
7034 (struct rte_eth_ethertype_filter *)arg,
7037 case RTE_ETH_FILTER_GET:
7038 ret = ixgbe_get_ethertype_filter(dev,
7039 (struct rte_eth_ethertype_filter *)arg);
7042 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7050 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
7051 enum rte_filter_type filter_type,
7052 enum rte_filter_op filter_op,
7057 switch (filter_type) {
7058 case RTE_ETH_FILTER_NTUPLE:
7059 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
7061 case RTE_ETH_FILTER_ETHERTYPE:
7062 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
7064 case RTE_ETH_FILTER_SYN:
7065 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
7067 case RTE_ETH_FILTER_FDIR:
7068 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
7070 case RTE_ETH_FILTER_L2_TUNNEL:
7071 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
7073 case RTE_ETH_FILTER_GENERIC:
7074 if (filter_op != RTE_ETH_FILTER_GET)
7076 *(const void **)arg = &ixgbe_flow_ops;
7079 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7089 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
7090 u8 **mc_addr_ptr, u32 *vmdq)
7095 mc_addr = *mc_addr_ptr;
7096 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
7101 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
7102 struct rte_ether_addr *mc_addr_set,
7103 uint32_t nb_mc_addr)
7105 struct ixgbe_hw *hw;
7108 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7109 mc_addr_list = (u8 *)mc_addr_set;
7110 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
7111 ixgbe_dev_addr_list_itr, TRUE);
7115 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
7117 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7118 uint64_t systime_cycles;
7120 switch (hw->mac.type) {
7121 case ixgbe_mac_X550:
7122 case ixgbe_mac_X550EM_x:
7123 case ixgbe_mac_X550EM_a:
7124 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
7125 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7126 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7130 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7131 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7135 return systime_cycles;
7139 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7141 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7142 uint64_t rx_tstamp_cycles;
7144 switch (hw->mac.type) {
7145 case ixgbe_mac_X550:
7146 case ixgbe_mac_X550EM_x:
7147 case ixgbe_mac_X550EM_a:
7148 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7149 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7150 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7154 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7155 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7156 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7160 return rx_tstamp_cycles;
7164 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7166 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7167 uint64_t tx_tstamp_cycles;
7169 switch (hw->mac.type) {
7170 case ixgbe_mac_X550:
7171 case ixgbe_mac_X550EM_x:
7172 case ixgbe_mac_X550EM_a:
7173 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7174 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7175 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7179 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7180 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7181 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7185 return tx_tstamp_cycles;
7189 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7191 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7192 struct ixgbe_adapter *adapter = dev->data->dev_private;
7193 struct rte_eth_link link;
7194 uint32_t incval = 0;
7197 /* Get current link speed. */
7198 ixgbe_dev_link_update(dev, 1);
7199 rte_eth_linkstatus_get(dev, &link);
7201 switch (link.link_speed) {
7202 case ETH_SPEED_NUM_100M:
7203 incval = IXGBE_INCVAL_100;
7204 shift = IXGBE_INCVAL_SHIFT_100;
7206 case ETH_SPEED_NUM_1G:
7207 incval = IXGBE_INCVAL_1GB;
7208 shift = IXGBE_INCVAL_SHIFT_1GB;
7210 case ETH_SPEED_NUM_10G:
7212 incval = IXGBE_INCVAL_10GB;
7213 shift = IXGBE_INCVAL_SHIFT_10GB;
7217 switch (hw->mac.type) {
7218 case ixgbe_mac_X550:
7219 case ixgbe_mac_X550EM_x:
7220 case ixgbe_mac_X550EM_a:
7221 /* Independent of link speed. */
7223 /* Cycles read will be interpreted as ns. */
7226 case ixgbe_mac_X540:
7227 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7229 case ixgbe_mac_82599EB:
7230 incval >>= IXGBE_INCVAL_SHIFT_82599;
7231 shift -= IXGBE_INCVAL_SHIFT_82599;
7232 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7233 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7236 /* Not supported. */
7240 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7241 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7242 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7244 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7245 adapter->systime_tc.cc_shift = shift;
7246 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7248 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7249 adapter->rx_tstamp_tc.cc_shift = shift;
7250 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7252 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7253 adapter->tx_tstamp_tc.cc_shift = shift;
7254 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7258 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7260 struct ixgbe_adapter *adapter = dev->data->dev_private;
7262 adapter->systime_tc.nsec += delta;
7263 adapter->rx_tstamp_tc.nsec += delta;
7264 adapter->tx_tstamp_tc.nsec += delta;
7270 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7273 struct ixgbe_adapter *adapter = dev->data->dev_private;
7275 ns = rte_timespec_to_ns(ts);
7276 /* Set the timecounters to a new value. */
7277 adapter->systime_tc.nsec = ns;
7278 adapter->rx_tstamp_tc.nsec = ns;
7279 adapter->tx_tstamp_tc.nsec = ns;
7285 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7287 uint64_t ns, systime_cycles;
7288 struct ixgbe_adapter *adapter = dev->data->dev_private;
7290 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7291 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7292 *ts = rte_ns_to_timespec(ns);
7298 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7300 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7304 /* Stop the timesync system time. */
7305 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7306 /* Reset the timesync system time value. */
7307 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7308 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7310 /* Enable system time for platforms where it isn't on by default. */
7311 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7312 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7313 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7315 ixgbe_start_timecounters(dev);
7317 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7318 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7319 (RTE_ETHER_TYPE_1588 |
7320 IXGBE_ETQF_FILTER_EN |
7323 /* Enable timestamping of received PTP packets. */
7324 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7325 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7326 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7328 /* Enable timestamping of transmitted PTP packets. */
7329 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7330 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7331 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7333 IXGBE_WRITE_FLUSH(hw);
7339 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7341 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7344 /* Disable timestamping of transmitted PTP packets. */
7345 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7346 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7347 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7349 /* Disable timestamping of received PTP packets. */
7350 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7351 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7352 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7354 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7355 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7357 /* Stop incrementating the System Time registers. */
7358 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7364 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7365 struct timespec *timestamp,
7366 uint32_t flags __rte_unused)
7368 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7369 struct ixgbe_adapter *adapter = dev->data->dev_private;
7370 uint32_t tsync_rxctl;
7371 uint64_t rx_tstamp_cycles;
7374 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7375 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7378 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7379 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7380 *timestamp = rte_ns_to_timespec(ns);
7386 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7387 struct timespec *timestamp)
7389 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7390 struct ixgbe_adapter *adapter = dev->data->dev_private;
7391 uint32_t tsync_txctl;
7392 uint64_t tx_tstamp_cycles;
7395 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7396 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7399 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7400 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7401 *timestamp = rte_ns_to_timespec(ns);
7407 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7409 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7412 const struct reg_info *reg_group;
7413 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7414 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7416 while ((reg_group = reg_set[g_ind++]))
7417 count += ixgbe_regs_group_count(reg_group);
7423 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7427 const struct reg_info *reg_group;
7429 while ((reg_group = ixgbevf_regs[g_ind++]))
7430 count += ixgbe_regs_group_count(reg_group);
7436 ixgbe_get_regs(struct rte_eth_dev *dev,
7437 struct rte_dev_reg_info *regs)
7439 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7440 uint32_t *data = regs->data;
7443 const struct reg_info *reg_group;
7444 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7445 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7448 regs->length = ixgbe_get_reg_length(dev);
7449 regs->width = sizeof(uint32_t);
7453 /* Support only full register dump */
7454 if ((regs->length == 0) ||
7455 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7456 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7458 while ((reg_group = reg_set[g_ind++]))
7459 count += ixgbe_read_regs_group(dev, &data[count],
7468 ixgbevf_get_regs(struct rte_eth_dev *dev,
7469 struct rte_dev_reg_info *regs)
7471 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7472 uint32_t *data = regs->data;
7475 const struct reg_info *reg_group;
7478 regs->length = ixgbevf_get_reg_length(dev);
7479 regs->width = sizeof(uint32_t);
7483 /* Support only full register dump */
7484 if ((regs->length == 0) ||
7485 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7486 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7488 while ((reg_group = ixgbevf_regs[g_ind++]))
7489 count += ixgbe_read_regs_group(dev, &data[count],
7498 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7500 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7502 /* Return unit is byte count */
7503 return hw->eeprom.word_size * 2;
7507 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7508 struct rte_dev_eeprom_info *in_eeprom)
7510 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7511 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7512 uint16_t *data = in_eeprom->data;
7515 first = in_eeprom->offset >> 1;
7516 length = in_eeprom->length >> 1;
7517 if ((first > hw->eeprom.word_size) ||
7518 ((first + length) > hw->eeprom.word_size))
7521 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7523 return eeprom->ops.read_buffer(hw, first, length, data);
7527 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7528 struct rte_dev_eeprom_info *in_eeprom)
7530 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7531 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7532 uint16_t *data = in_eeprom->data;
7535 first = in_eeprom->offset >> 1;
7536 length = in_eeprom->length >> 1;
7537 if ((first > hw->eeprom.word_size) ||
7538 ((first + length) > hw->eeprom.word_size))
7541 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7543 return eeprom->ops.write_buffer(hw, first, length, data);
7547 ixgbe_get_module_info(struct rte_eth_dev *dev,
7548 struct rte_eth_dev_module_info *modinfo)
7550 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7552 uint8_t sff8472_rev, addr_mode;
7553 bool page_swap = false;
7555 /* Check whether we support SFF-8472 or not */
7556 status = hw->phy.ops.read_i2c_eeprom(hw,
7557 IXGBE_SFF_SFF_8472_COMP,
7562 /* addressing mode is not supported */
7563 status = hw->phy.ops.read_i2c_eeprom(hw,
7564 IXGBE_SFF_SFF_8472_SWAP,
7569 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7571 "Address change required to access page 0xA2, "
7572 "but not supported. Please report the module "
7573 "type to the driver maintainers.");
7577 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7578 /* We have a SFP, but it does not support SFF-8472 */
7579 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7580 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7582 /* We have a SFP which supports a revision of SFF-8472. */
7583 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7584 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7591 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7592 struct rte_dev_eeprom_info *info)
7594 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7595 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7596 uint8_t databyte = 0xFF;
7597 uint8_t *data = info->data;
7600 if (info->length == 0)
7603 for (i = info->offset; i < info->offset + info->length; i++) {
7604 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7605 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7607 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7612 data[i - info->offset] = databyte;
7619 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7621 case ixgbe_mac_X550:
7622 case ixgbe_mac_X550EM_x:
7623 case ixgbe_mac_X550EM_a:
7624 return ETH_RSS_RETA_SIZE_512;
7625 case ixgbe_mac_X550_vf:
7626 case ixgbe_mac_X550EM_x_vf:
7627 case ixgbe_mac_X550EM_a_vf:
7628 return ETH_RSS_RETA_SIZE_64;
7629 case ixgbe_mac_X540_vf:
7630 case ixgbe_mac_82599_vf:
7633 return ETH_RSS_RETA_SIZE_128;
7638 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7640 case ixgbe_mac_X550:
7641 case ixgbe_mac_X550EM_x:
7642 case ixgbe_mac_X550EM_a:
7643 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7644 return IXGBE_RETA(reta_idx >> 2);
7646 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7647 case ixgbe_mac_X550_vf:
7648 case ixgbe_mac_X550EM_x_vf:
7649 case ixgbe_mac_X550EM_a_vf:
7650 return IXGBE_VFRETA(reta_idx >> 2);
7652 return IXGBE_RETA(reta_idx >> 2);
7657 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7659 case ixgbe_mac_X550_vf:
7660 case ixgbe_mac_X550EM_x_vf:
7661 case ixgbe_mac_X550EM_a_vf:
7662 return IXGBE_VFMRQC;
7669 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7671 case ixgbe_mac_X550_vf:
7672 case ixgbe_mac_X550EM_x_vf:
7673 case ixgbe_mac_X550EM_a_vf:
7674 return IXGBE_VFRSSRK(i);
7676 return IXGBE_RSSRK(i);
7681 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7683 case ixgbe_mac_82599_vf:
7684 case ixgbe_mac_X540_vf:
7692 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7693 struct rte_eth_dcb_info *dcb_info)
7695 struct ixgbe_dcb_config *dcb_config =
7696 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7697 struct ixgbe_dcb_tc_config *tc;
7698 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7702 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7703 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7705 dcb_info->nb_tcs = 1;
7707 tc_queue = &dcb_info->tc_queue;
7708 nb_tcs = dcb_info->nb_tcs;
7710 if (dcb_config->vt_mode) { /* vt is enabled*/
7711 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7712 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7713 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7714 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7715 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7716 for (j = 0; j < nb_tcs; j++) {
7717 tc_queue->tc_rxq[0][j].base = j;
7718 tc_queue->tc_rxq[0][j].nb_queue = 1;
7719 tc_queue->tc_txq[0][j].base = j;
7720 tc_queue->tc_txq[0][j].nb_queue = 1;
7723 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7724 for (j = 0; j < nb_tcs; j++) {
7725 tc_queue->tc_rxq[i][j].base =
7727 tc_queue->tc_rxq[i][j].nb_queue = 1;
7728 tc_queue->tc_txq[i][j].base =
7730 tc_queue->tc_txq[i][j].nb_queue = 1;
7734 } else { /* vt is disabled*/
7735 struct rte_eth_dcb_rx_conf *rx_conf =
7736 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7737 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7738 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7739 if (dcb_info->nb_tcs == ETH_4_TCS) {
7740 for (i = 0; i < dcb_info->nb_tcs; i++) {
7741 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7742 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7744 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7745 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7746 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7747 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7748 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7749 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7750 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7751 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7752 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7753 for (i = 0; i < dcb_info->nb_tcs; i++) {
7754 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7755 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7757 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7758 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7759 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7760 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7761 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7762 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7763 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7764 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7765 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7766 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7767 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7768 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7769 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7770 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7771 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7772 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7775 for (i = 0; i < dcb_info->nb_tcs; i++) {
7776 tc = &dcb_config->tc_config[i];
7777 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7782 /* Update e-tag ether type */
7784 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7785 uint16_t ether_type)
7787 uint32_t etag_etype;
7789 if (hw->mac.type != ixgbe_mac_X550 &&
7790 hw->mac.type != ixgbe_mac_X550EM_x &&
7791 hw->mac.type != ixgbe_mac_X550EM_a) {
7795 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7796 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7797 etag_etype |= ether_type;
7798 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7799 IXGBE_WRITE_FLUSH(hw);
7804 /* Config l2 tunnel ether type */
7806 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7807 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7810 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7811 struct ixgbe_l2_tn_info *l2_tn_info =
7812 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7814 if (l2_tunnel == NULL)
7817 switch (l2_tunnel->l2_tunnel_type) {
7818 case RTE_L2_TUNNEL_TYPE_E_TAG:
7819 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7820 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7823 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7831 /* Enable e-tag tunnel */
7833 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7835 uint32_t etag_etype;
7837 if (hw->mac.type != ixgbe_mac_X550 &&
7838 hw->mac.type != ixgbe_mac_X550EM_x &&
7839 hw->mac.type != ixgbe_mac_X550EM_a) {
7843 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7844 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7845 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7846 IXGBE_WRITE_FLUSH(hw);
7851 /* Enable l2 tunnel */
7853 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7854 enum rte_eth_tunnel_type l2_tunnel_type)
7857 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7858 struct ixgbe_l2_tn_info *l2_tn_info =
7859 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7861 switch (l2_tunnel_type) {
7862 case RTE_L2_TUNNEL_TYPE_E_TAG:
7863 l2_tn_info->e_tag_en = TRUE;
7864 ret = ixgbe_e_tag_enable(hw);
7867 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7875 /* Disable e-tag tunnel */
7877 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7879 uint32_t etag_etype;
7881 if (hw->mac.type != ixgbe_mac_X550 &&
7882 hw->mac.type != ixgbe_mac_X550EM_x &&
7883 hw->mac.type != ixgbe_mac_X550EM_a) {
7887 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7888 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7889 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7890 IXGBE_WRITE_FLUSH(hw);
7895 /* Disable l2 tunnel */
7897 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7898 enum rte_eth_tunnel_type l2_tunnel_type)
7901 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7902 struct ixgbe_l2_tn_info *l2_tn_info =
7903 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7905 switch (l2_tunnel_type) {
7906 case RTE_L2_TUNNEL_TYPE_E_TAG:
7907 l2_tn_info->e_tag_en = FALSE;
7908 ret = ixgbe_e_tag_disable(hw);
7911 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7920 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7921 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7924 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7925 uint32_t i, rar_entries;
7926 uint32_t rar_low, rar_high;
7928 if (hw->mac.type != ixgbe_mac_X550 &&
7929 hw->mac.type != ixgbe_mac_X550EM_x &&
7930 hw->mac.type != ixgbe_mac_X550EM_a) {
7934 rar_entries = ixgbe_get_num_rx_addrs(hw);
7936 for (i = 1; i < rar_entries; i++) {
7937 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7938 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7939 if ((rar_high & IXGBE_RAH_AV) &&
7940 (rar_high & IXGBE_RAH_ADTYPE) &&
7941 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7942 l2_tunnel->tunnel_id)) {
7943 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7944 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7946 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7956 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7957 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7960 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7961 uint32_t i, rar_entries;
7962 uint32_t rar_low, rar_high;
7964 if (hw->mac.type != ixgbe_mac_X550 &&
7965 hw->mac.type != ixgbe_mac_X550EM_x &&
7966 hw->mac.type != ixgbe_mac_X550EM_a) {
7970 /* One entry for one tunnel. Try to remove potential existing entry. */
7971 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7973 rar_entries = ixgbe_get_num_rx_addrs(hw);
7975 for (i = 1; i < rar_entries; i++) {
7976 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7977 if (rar_high & IXGBE_RAH_AV) {
7980 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7981 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7982 rar_low = l2_tunnel->tunnel_id;
7984 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7985 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7991 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7992 " Please remove a rule before adding a new one.");
7996 static inline struct ixgbe_l2_tn_filter *
7997 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7998 struct ixgbe_l2_tn_key *key)
8002 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
8006 return l2_tn_info->hash_map[ret];
8010 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8011 struct ixgbe_l2_tn_filter *l2_tn_filter)
8015 ret = rte_hash_add_key(l2_tn_info->hash_handle,
8016 &l2_tn_filter->key);
8020 "Failed to insert L2 tunnel filter"
8021 " to hash table %d!",
8026 l2_tn_info->hash_map[ret] = l2_tn_filter;
8028 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8034 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8035 struct ixgbe_l2_tn_key *key)
8038 struct ixgbe_l2_tn_filter *l2_tn_filter;
8040 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
8044 "No such L2 tunnel filter to delete %d!",
8049 l2_tn_filter = l2_tn_info->hash_map[ret];
8050 l2_tn_info->hash_map[ret] = NULL;
8052 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8053 rte_free(l2_tn_filter);
8058 /* Add l2 tunnel filter */
8060 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
8061 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8065 struct ixgbe_l2_tn_info *l2_tn_info =
8066 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8067 struct ixgbe_l2_tn_key key;
8068 struct ixgbe_l2_tn_filter *node;
8071 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8072 key.tn_id = l2_tunnel->tunnel_id;
8074 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
8078 "The L2 tunnel filter already exists!");
8082 node = rte_zmalloc("ixgbe_l2_tn",
8083 sizeof(struct ixgbe_l2_tn_filter),
8088 rte_memcpy(&node->key,
8090 sizeof(struct ixgbe_l2_tn_key));
8091 node->pool = l2_tunnel->pool;
8092 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
8099 switch (l2_tunnel->l2_tunnel_type) {
8100 case RTE_L2_TUNNEL_TYPE_E_TAG:
8101 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
8104 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8109 if ((!restore) && (ret < 0))
8110 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8115 /* Delete l2 tunnel filter */
8117 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
8118 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8121 struct ixgbe_l2_tn_info *l2_tn_info =
8122 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8123 struct ixgbe_l2_tn_key key;
8125 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8126 key.tn_id = l2_tunnel->tunnel_id;
8127 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8131 switch (l2_tunnel->l2_tunnel_type) {
8132 case RTE_L2_TUNNEL_TYPE_E_TAG:
8133 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8136 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8145 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8146 * @dev: pointer to rte_eth_dev structure
8147 * @filter_op:operation will be taken.
8148 * @arg: a pointer to specific structure corresponding to the filter_op
8151 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8152 enum rte_filter_op filter_op,
8157 if (filter_op == RTE_ETH_FILTER_NOP)
8161 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8166 switch (filter_op) {
8167 case RTE_ETH_FILTER_ADD:
8168 ret = ixgbe_dev_l2_tunnel_filter_add
8170 (struct rte_eth_l2_tunnel_conf *)arg,
8173 case RTE_ETH_FILTER_DELETE:
8174 ret = ixgbe_dev_l2_tunnel_filter_del
8176 (struct rte_eth_l2_tunnel_conf *)arg);
8179 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8187 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8191 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8193 if (hw->mac.type != ixgbe_mac_X550 &&
8194 hw->mac.type != ixgbe_mac_X550EM_x &&
8195 hw->mac.type != ixgbe_mac_X550EM_a) {
8199 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8200 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8202 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8203 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8208 /* Enable l2 tunnel forwarding */
8210 ixgbe_dev_l2_tunnel_forwarding_enable
8211 (struct rte_eth_dev *dev,
8212 enum rte_eth_tunnel_type l2_tunnel_type)
8214 struct ixgbe_l2_tn_info *l2_tn_info =
8215 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8218 switch (l2_tunnel_type) {
8219 case RTE_L2_TUNNEL_TYPE_E_TAG:
8220 l2_tn_info->e_tag_fwd_en = TRUE;
8221 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8224 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8232 /* Disable l2 tunnel forwarding */
8234 ixgbe_dev_l2_tunnel_forwarding_disable
8235 (struct rte_eth_dev *dev,
8236 enum rte_eth_tunnel_type l2_tunnel_type)
8238 struct ixgbe_l2_tn_info *l2_tn_info =
8239 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8242 switch (l2_tunnel_type) {
8243 case RTE_L2_TUNNEL_TYPE_E_TAG:
8244 l2_tn_info->e_tag_fwd_en = FALSE;
8245 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8248 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8257 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8258 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8261 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8263 uint32_t vmtir, vmvir;
8264 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8266 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8268 "VF id %u should be less than %u",
8274 if (hw->mac.type != ixgbe_mac_X550 &&
8275 hw->mac.type != ixgbe_mac_X550EM_x &&
8276 hw->mac.type != ixgbe_mac_X550EM_a) {
8281 vmtir = l2_tunnel->tunnel_id;
8285 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8287 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8288 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8290 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8291 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8296 /* Enable l2 tunnel tag insertion */
8298 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8299 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8303 switch (l2_tunnel->l2_tunnel_type) {
8304 case RTE_L2_TUNNEL_TYPE_E_TAG:
8305 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8308 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8316 /* Disable l2 tunnel tag insertion */
8318 ixgbe_dev_l2_tunnel_insertion_disable
8319 (struct rte_eth_dev *dev,
8320 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8324 switch (l2_tunnel->l2_tunnel_type) {
8325 case RTE_L2_TUNNEL_TYPE_E_TAG:
8326 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8329 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8338 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8343 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8345 if (hw->mac.type != ixgbe_mac_X550 &&
8346 hw->mac.type != ixgbe_mac_X550EM_x &&
8347 hw->mac.type != ixgbe_mac_X550EM_a) {
8351 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8353 qde |= IXGBE_QDE_STRIP_TAG;
8355 qde &= ~IXGBE_QDE_STRIP_TAG;
8356 qde &= ~IXGBE_QDE_READ;
8357 qde |= IXGBE_QDE_WRITE;
8358 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8363 /* Enable l2 tunnel tag stripping */
8365 ixgbe_dev_l2_tunnel_stripping_enable
8366 (struct rte_eth_dev *dev,
8367 enum rte_eth_tunnel_type l2_tunnel_type)
8371 switch (l2_tunnel_type) {
8372 case RTE_L2_TUNNEL_TYPE_E_TAG:
8373 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8376 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8384 /* Disable l2 tunnel tag stripping */
8386 ixgbe_dev_l2_tunnel_stripping_disable
8387 (struct rte_eth_dev *dev,
8388 enum rte_eth_tunnel_type l2_tunnel_type)
8392 switch (l2_tunnel_type) {
8393 case RTE_L2_TUNNEL_TYPE_E_TAG:
8394 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8397 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8405 /* Enable/disable l2 tunnel offload functions */
8407 ixgbe_dev_l2_tunnel_offload_set
8408 (struct rte_eth_dev *dev,
8409 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8415 if (l2_tunnel == NULL)
8419 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8421 ret = ixgbe_dev_l2_tunnel_enable(
8423 l2_tunnel->l2_tunnel_type);
8425 ret = ixgbe_dev_l2_tunnel_disable(
8427 l2_tunnel->l2_tunnel_type);
8430 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8432 ret = ixgbe_dev_l2_tunnel_insertion_enable(
8436 ret = ixgbe_dev_l2_tunnel_insertion_disable(
8441 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8443 ret = ixgbe_dev_l2_tunnel_stripping_enable(
8445 l2_tunnel->l2_tunnel_type);
8447 ret = ixgbe_dev_l2_tunnel_stripping_disable(
8449 l2_tunnel->l2_tunnel_type);
8452 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8454 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8456 l2_tunnel->l2_tunnel_type);
8458 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8460 l2_tunnel->l2_tunnel_type);
8467 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8470 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8471 IXGBE_WRITE_FLUSH(hw);
8476 /* There's only one register for VxLAN UDP port.
8477 * So, we cannot add several ports. Will update it.
8480 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8484 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8488 return ixgbe_update_vxlan_port(hw, port);
8491 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8492 * UDP port, it must have a value.
8493 * So, will reset it to the original value 0.
8496 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8501 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8503 if (cur_port != port) {
8504 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8508 return ixgbe_update_vxlan_port(hw, 0);
8511 /* Add UDP tunneling port */
8513 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8514 struct rte_eth_udp_tunnel *udp_tunnel)
8517 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8519 if (hw->mac.type != ixgbe_mac_X550 &&
8520 hw->mac.type != ixgbe_mac_X550EM_x &&
8521 hw->mac.type != ixgbe_mac_X550EM_a) {
8525 if (udp_tunnel == NULL)
8528 switch (udp_tunnel->prot_type) {
8529 case RTE_TUNNEL_TYPE_VXLAN:
8530 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8533 case RTE_TUNNEL_TYPE_GENEVE:
8534 case RTE_TUNNEL_TYPE_TEREDO:
8535 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8540 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8548 /* Remove UDP tunneling port */
8550 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8551 struct rte_eth_udp_tunnel *udp_tunnel)
8554 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8556 if (hw->mac.type != ixgbe_mac_X550 &&
8557 hw->mac.type != ixgbe_mac_X550EM_x &&
8558 hw->mac.type != ixgbe_mac_X550EM_a) {
8562 if (udp_tunnel == NULL)
8565 switch (udp_tunnel->prot_type) {
8566 case RTE_TUNNEL_TYPE_VXLAN:
8567 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8569 case RTE_TUNNEL_TYPE_GENEVE:
8570 case RTE_TUNNEL_TYPE_TEREDO:
8571 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8575 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8584 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8586 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8589 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8593 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8605 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8607 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8610 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8614 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8626 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8628 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8630 int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8632 switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8636 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8648 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8650 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8653 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8657 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8668 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8670 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8673 /* peek the message first */
8674 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8676 /* PF reset VF event */
8677 if (in_msg == IXGBE_PF_CONTROL_MSG) {
8678 /* dummy mbx read to ack pf */
8679 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8681 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8687 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8690 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8691 struct ixgbe_interrupt *intr =
8692 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8693 ixgbevf_intr_disable(dev);
8695 /* read-on-clear nic registers here */
8696 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8699 /* only one misc vector supported - mailbox */
8700 eicr &= IXGBE_VTEICR_MASK;
8701 if (eicr == IXGBE_MISC_VEC_ID)
8702 intr->flags |= IXGBE_FLAG_MAILBOX;
8708 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8710 struct ixgbe_interrupt *intr =
8711 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8713 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8714 ixgbevf_mbx_process(dev);
8715 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8718 ixgbevf_intr_enable(dev);
8724 ixgbevf_dev_interrupt_handler(void *param)
8726 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8728 ixgbevf_dev_interrupt_get_status(dev);
8729 ixgbevf_dev_interrupt_action(dev);
8733 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8734 * @hw: pointer to hardware structure
8736 * Stops the transmit data path and waits for the HW to internally empty
8737 * the Tx security block
8739 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8741 #define IXGBE_MAX_SECTX_POLL 40
8746 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8747 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8748 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8749 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8750 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8751 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8753 /* Use interrupt-safe sleep just in case */
8757 /* For informational purposes only */
8758 if (i >= IXGBE_MAX_SECTX_POLL)
8759 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8760 "path fully disabled. Continuing with init.");
8762 return IXGBE_SUCCESS;
8766 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8767 * @hw: pointer to hardware structure
8769 * Enables the transmit data path.
8771 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8775 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8776 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8777 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8778 IXGBE_WRITE_FLUSH(hw);
8780 return IXGBE_SUCCESS;
8783 /* restore n-tuple filter */
8785 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8787 struct ixgbe_filter_info *filter_info =
8788 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8789 struct ixgbe_5tuple_filter *node;
8791 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8792 ixgbe_inject_5tuple_filter(dev, node);
8796 /* restore ethernet type filter */
8798 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8800 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8801 struct ixgbe_filter_info *filter_info =
8802 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8805 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8806 if (filter_info->ethertype_mask & (1 << i)) {
8807 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8808 filter_info->ethertype_filters[i].etqf);
8809 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8810 filter_info->ethertype_filters[i].etqs);
8811 IXGBE_WRITE_FLUSH(hw);
8816 /* restore SYN filter */
8818 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8820 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8821 struct ixgbe_filter_info *filter_info =
8822 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8825 synqf = filter_info->syn_info;
8827 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8828 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8829 IXGBE_WRITE_FLUSH(hw);
8833 /* restore L2 tunnel filter */
8835 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8837 struct ixgbe_l2_tn_info *l2_tn_info =
8838 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8839 struct ixgbe_l2_tn_filter *node;
8840 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8842 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8843 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8844 l2_tn_conf.tunnel_id = node->key.tn_id;
8845 l2_tn_conf.pool = node->pool;
8846 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8850 /* restore rss filter */
8852 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8854 struct ixgbe_filter_info *filter_info =
8855 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8857 if (filter_info->rss_info.conf.queue_num)
8858 ixgbe_config_rss_filter(dev,
8859 &filter_info->rss_info, TRUE);
8863 ixgbe_filter_restore(struct rte_eth_dev *dev)
8865 ixgbe_ntuple_filter_restore(dev);
8866 ixgbe_ethertype_filter_restore(dev);
8867 ixgbe_syn_filter_restore(dev);
8868 ixgbe_fdir_filter_restore(dev);
8869 ixgbe_l2_tn_filter_restore(dev);
8870 ixgbe_rss_filter_restore(dev);
8876 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8878 struct ixgbe_l2_tn_info *l2_tn_info =
8879 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8880 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8882 if (l2_tn_info->e_tag_en)
8883 (void)ixgbe_e_tag_enable(hw);
8885 if (l2_tn_info->e_tag_fwd_en)
8886 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8888 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8891 /* remove all the n-tuple filters */
8893 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8895 struct ixgbe_filter_info *filter_info =
8896 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8897 struct ixgbe_5tuple_filter *p_5tuple;
8899 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8900 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8903 /* remove all the ether type filters */
8905 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8907 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8908 struct ixgbe_filter_info *filter_info =
8909 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8912 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8913 if (filter_info->ethertype_mask & (1 << i) &&
8914 !filter_info->ethertype_filters[i].conf) {
8915 (void)ixgbe_ethertype_filter_remove(filter_info,
8917 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8918 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8919 IXGBE_WRITE_FLUSH(hw);
8924 /* remove the SYN filter */
8926 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8928 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8929 struct ixgbe_filter_info *filter_info =
8930 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8932 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8933 filter_info->syn_info = 0;
8935 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8936 IXGBE_WRITE_FLUSH(hw);
8940 /* remove all the L2 tunnel filters */
8942 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8944 struct ixgbe_l2_tn_info *l2_tn_info =
8945 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8946 struct ixgbe_l2_tn_filter *l2_tn_filter;
8947 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8950 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8951 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8952 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8953 l2_tn_conf.pool = l2_tn_filter->pool;
8954 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8963 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8964 struct ixgbe_macsec_setting *macsec_setting)
8966 struct ixgbe_macsec_setting *macsec =
8967 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8969 macsec->offload_en = macsec_setting->offload_en;
8970 macsec->encrypt_en = macsec_setting->encrypt_en;
8971 macsec->replayprotect_en = macsec_setting->replayprotect_en;
8975 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8977 struct ixgbe_macsec_setting *macsec =
8978 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8980 macsec->offload_en = 0;
8981 macsec->encrypt_en = 0;
8982 macsec->replayprotect_en = 0;
8986 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8987 struct ixgbe_macsec_setting *macsec_setting)
8989 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8991 uint8_t en = macsec_setting->encrypt_en;
8992 uint8_t rp = macsec_setting->replayprotect_en;
8996 * As no ixgbe_disable_sec_rx_path equivalent is
8997 * implemented for tx in the base code, and we are
8998 * not allowed to modify the base code in DPDK, so
8999 * just call the hand-written one directly for now.
9000 * The hardware support has been checked by
9001 * ixgbe_disable_sec_rx_path().
9003 ixgbe_disable_sec_tx_path_generic(hw);
9005 /* Enable Ethernet CRC (required by MACsec offload) */
9006 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
9007 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
9008 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
9010 /* Enable the TX and RX crypto engines */
9011 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9012 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
9013 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9015 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9016 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
9017 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9019 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
9020 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
9022 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
9024 /* Enable SA lookup */
9025 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9026 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9027 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
9028 IXGBE_LSECTXCTRL_AUTH;
9029 ctrl |= IXGBE_LSECTXCTRL_AISCI;
9030 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9031 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9032 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9034 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9035 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9036 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
9037 ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
9039 ctrl |= IXGBE_LSECRXCTRL_RP;
9041 ctrl &= ~IXGBE_LSECRXCTRL_RP;
9042 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9044 /* Start the data paths */
9045 ixgbe_enable_sec_rx_path(hw);
9048 * As no ixgbe_enable_sec_rx_path equivalent is
9049 * implemented for tx in the base code, and we are
9050 * not allowed to modify the base code in DPDK, so
9051 * just call the hand-written one directly for now.
9053 ixgbe_enable_sec_tx_path_generic(hw);
9057 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
9059 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9064 * As no ixgbe_disable_sec_rx_path equivalent is
9065 * implemented for tx in the base code, and we are
9066 * not allowed to modify the base code in DPDK, so
9067 * just call the hand-written one directly for now.
9068 * The hardware support has been checked by
9069 * ixgbe_disable_sec_rx_path().
9071 ixgbe_disable_sec_tx_path_generic(hw);
9073 /* Disable the TX and RX crypto engines */
9074 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9075 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
9076 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9078 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9079 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
9080 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9082 /* Disable SA lookup */
9083 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9084 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9085 ctrl |= IXGBE_LSECTXCTRL_DISABLE;
9086 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9088 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9089 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9090 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
9091 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9093 /* Start the data paths */
9094 ixgbe_enable_sec_rx_path(hw);
9097 * As no ixgbe_enable_sec_rx_path equivalent is
9098 * implemented for tx in the base code, and we are
9099 * not allowed to modify the base code in DPDK, so
9100 * just call the hand-written one directly for now.
9102 ixgbe_enable_sec_tx_path_generic(hw);
9105 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
9106 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
9107 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
9108 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
9109 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
9110 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
9111 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
9112 IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
9114 RTE_INIT(ixgbe_init_log)
9116 ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
9117 if (ixgbe_logtype_init >= 0)
9118 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
9119 ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
9120 if (ixgbe_logtype_driver >= 0)
9121 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
9122 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
9123 ixgbe_logtype_rx = rte_log_register("pmd.net.ixgbe.rx");
9124 if (ixgbe_logtype_rx >= 0)
9125 rte_log_set_level(ixgbe_logtype_rx, RTE_LOG_DEBUG);
9128 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
9129 ixgbe_logtype_tx = rte_log_register("pmd.net.ixgbe.tx");
9130 if (ixgbe_logtype_tx >= 0)
9131 rte_log_set_level(ixgbe_logtype_tx, RTE_LOG_DEBUG);
9134 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9135 ixgbe_logtype_tx_free = rte_log_register("pmd.net.ixgbe.tx_free");
9136 if (ixgbe_logtype_tx_free >= 0)
9137 rte_log_set_level(ixgbe_logtype_tx_free, RTE_LOG_DEBUG);