1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
13 #include <netinet/in.h>
14 #include <rte_string_fns.h>
15 #include <rte_byteorder.h>
16 #include <rte_common.h>
17 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_branch_prediction.h>
25 #include <rte_memory.h>
26 #include <rte_kvargs.h>
28 #include <rte_alarm.h>
29 #include <rte_ether.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
32 #include <rte_malloc.h>
33 #include <rte_random.h>
35 #include <rte_hash_crc.h>
36 #ifdef RTE_LIBRTE_SECURITY
37 #include <rte_security_driver.h>
40 #include "ixgbe_logs.h"
41 #include "base/ixgbe_api.h"
42 #include "base/ixgbe_vf.h"
43 #include "base/ixgbe_common.h"
44 #include "ixgbe_ethdev.h"
45 #include "ixgbe_bypass.h"
46 #include "ixgbe_rxtx.h"
47 #include "base/ixgbe_type.h"
48 #include "base/ixgbe_phy.h"
49 #include "ixgbe_regs.h"
52 * High threshold controlling when to start sending XOFF frames. Must be at
53 * least 8 bytes less than receive packet buffer size. This value is in units
56 #define IXGBE_FC_HI 0x80
59 * Low threshold controlling when to start sending XON frames. This value is
60 * in units of 1024 bytes.
62 #define IXGBE_FC_LO 0x40
64 /* Timer value included in XOFF frames. */
65 #define IXGBE_FC_PAUSE 0x680
67 /*Default value of Max Rx Queue*/
68 #define IXGBE_MAX_RX_QUEUE_NUM 128
70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
71 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
72 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
74 #define IXGBE_MMW_SIZE_DEFAULT 0x4
75 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
76 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
79 * Default values for RX/TX configuration
81 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
82 #define IXGBE_DEFAULT_RX_PTHRESH 8
83 #define IXGBE_DEFAULT_RX_HTHRESH 8
84 #define IXGBE_DEFAULT_RX_WTHRESH 0
86 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
87 #define IXGBE_DEFAULT_TX_PTHRESH 32
88 #define IXGBE_DEFAULT_TX_HTHRESH 0
89 #define IXGBE_DEFAULT_TX_WTHRESH 0
90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
92 /* Bit shift and mask */
93 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
94 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
95 #define IXGBE_8_BIT_WIDTH CHAR_BIT
96 #define IXGBE_8_BIT_MASK UINT8_MAX
98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
102 /* Additional timesync values. */
103 #define NSEC_PER_SEC 1000000000L
104 #define IXGBE_INCVAL_10GB 0x66666666
105 #define IXGBE_INCVAL_1GB 0x40000000
106 #define IXGBE_INCVAL_100 0x50000000
107 #define IXGBE_INCVAL_SHIFT_10GB 28
108 #define IXGBE_INCVAL_SHIFT_1GB 24
109 #define IXGBE_INCVAL_SHIFT_100 21
110 #define IXGBE_INCVAL_SHIFT_82599 7
111 #define IXGBE_INCPER_SHIFT_82599 24
113 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
115 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
117 #define IXGBE_ETAG_ETYPE 0x00005084
118 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
119 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
120 #define IXGBE_RAH_ADTYPE 0x40000000
121 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
122 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
125 #define IXGBE_QDE_STRIP_TAG 0x00000004
126 #define IXGBE_VTEICR_MASK 0x07
128 #define IXGBE_EXVET_VET_EXT_SHIFT 16
129 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK "pflink_fullchk"
133 static const char * const ixgbevf_valid_arguments[] = {
134 IXGBEVF_DEVARG_PFLINK_FULLCHK,
138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
150 static void ixgbe_dev_close(struct rte_eth_dev *dev);
151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
157 int wait_to_complete);
158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
159 struct rte_eth_stats *stats);
160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
161 struct rte_eth_xstat *xstats, unsigned n);
162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
163 struct rte_eth_xstat *xstats, unsigned n);
165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
166 uint64_t *values, unsigned int n);
167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
170 struct rte_eth_xstat_name *xstats_names,
172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
173 struct rte_eth_xstat_name *xstats_names, unsigned limit);
174 static int ixgbe_dev_xstats_get_names_by_id(
175 struct rte_eth_dev *dev,
176 struct rte_eth_xstat_name *xstats_names,
179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
186 struct rte_eth_dev_info *dev_info);
187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
189 struct rte_eth_dev_info *dev_info);
190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
193 uint16_t vlan_id, int on);
194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
195 enum rte_vlan_type vlan_type,
197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
198 uint16_t queue, bool on);
199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
213 struct rte_eth_fc_conf *fc_conf);
214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
215 struct rte_eth_fc_conf *fc_conf);
216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
217 struct rte_eth_pfc_conf *pfc_conf);
218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
219 struct rte_eth_rss_reta_entry64 *reta_conf,
221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
222 struct rte_eth_rss_reta_entry64 *reta_conf,
224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
230 static void ixgbe_dev_interrupt_handler(void *param);
231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
232 static void ixgbe_dev_setup_link_alarm_handler(void *param);
234 static int ixgbe_add_rar(struct rte_eth_dev *dev,
235 struct rte_ether_addr *mac_addr,
236 uint32_t index, uint32_t pool);
237 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
238 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
239 struct rte_ether_addr *mac_addr);
240 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
241 static bool is_device_supported(struct rte_eth_dev *dev,
242 struct rte_pci_driver *drv);
244 /* For Virtual Function support */
245 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
246 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
247 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
248 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
249 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
250 int wait_to_complete);
251 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
252 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
253 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
254 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
255 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
256 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
257 struct rte_eth_stats *stats);
258 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
259 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
260 uint16_t vlan_id, int on);
261 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
262 uint16_t queue, int on);
263 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
264 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
265 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
266 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
268 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
270 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
271 uint8_t queue, uint8_t msix_vector);
272 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
273 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
274 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
275 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
276 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
278 /* For Eth VMDQ APIs support */
279 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
280 rte_ether_addr * mac_addr, uint8_t on);
281 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
282 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
283 struct rte_eth_mirror_conf *mirror_conf,
284 uint8_t rule_id, uint8_t on);
285 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
287 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
289 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
291 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
292 uint8_t queue, uint8_t msix_vector);
293 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
295 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
296 struct rte_ether_addr *mac_addr,
297 uint32_t index, uint32_t pool);
298 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
299 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
300 struct rte_ether_addr *mac_addr);
301 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
302 struct rte_eth_syn_filter *filter);
303 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
304 enum rte_filter_op filter_op,
306 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
307 struct ixgbe_5tuple_filter *filter);
308 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
309 struct ixgbe_5tuple_filter *filter);
310 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
311 enum rte_filter_op filter_op,
313 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
314 struct rte_eth_ntuple_filter *filter);
315 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
316 enum rte_filter_op filter_op,
318 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
319 struct rte_eth_ethertype_filter *filter);
320 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
321 enum rte_filter_type filter_type,
322 enum rte_filter_op filter_op,
324 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
326 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
327 struct rte_ether_addr *mc_addr_set,
328 uint32_t nb_mc_addr);
329 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
330 struct rte_eth_dcb_info *dcb_info);
332 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
333 static int ixgbe_get_regs(struct rte_eth_dev *dev,
334 struct rte_dev_reg_info *regs);
335 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
336 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
337 struct rte_dev_eeprom_info *eeprom);
338 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
339 struct rte_dev_eeprom_info *eeprom);
341 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
342 struct rte_eth_dev_module_info *modinfo);
343 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
344 struct rte_dev_eeprom_info *info);
346 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
347 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
348 struct rte_dev_reg_info *regs);
350 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
351 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
352 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
353 struct timespec *timestamp,
355 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
356 struct timespec *timestamp);
357 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
358 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
359 struct timespec *timestamp);
360 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
361 const struct timespec *timestamp);
362 static void ixgbevf_dev_interrupt_handler(void *param);
364 static int ixgbe_dev_l2_tunnel_eth_type_conf
365 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
366 static int ixgbe_dev_l2_tunnel_offload_set
367 (struct rte_eth_dev *dev,
368 struct rte_eth_l2_tunnel_conf *l2_tunnel,
371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
372 enum rte_filter_op filter_op,
375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
376 struct rte_eth_udp_tunnel *udp_tunnel);
377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
378 struct rte_eth_udp_tunnel *udp_tunnel);
379 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
380 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
383 * Define VF Stats MACRO for Non "cleared on read" register
385 #define UPDATE_VF_STAT(reg, last, cur) \
387 uint32_t latest = IXGBE_READ_REG(hw, reg); \
388 cur += (latest - last) & UINT_MAX; \
392 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
394 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
395 u64 new_msb = IXGBE_READ_REG(hw, msb); \
396 u64 latest = ((new_msb << 32) | new_lsb); \
397 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
401 #define IXGBE_SET_HWSTRIP(h, q) do {\
402 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
403 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
404 (h)->bitmap[idx] |= 1 << bit;\
407 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
408 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
409 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
410 (h)->bitmap[idx] &= ~(1 << bit);\
413 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
414 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
415 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
416 (r) = (h)->bitmap[idx] >> bit & 1;\
419 int ixgbe_logtype_init;
420 int ixgbe_logtype_driver;
422 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
423 int ixgbe_logtype_rx;
425 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
426 int ixgbe_logtype_tx;
428 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
429 int ixgbe_logtype_tx_free;
433 * The set of PCI devices this driver supports
435 static const struct rte_pci_id pci_id_ixgbe_map[] = {
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
483 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
484 #ifdef RTE_LIBRTE_IXGBE_BYPASS
485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
487 { .vendor_id = 0, /* sentinel */ },
491 * The set of PCI devices this driver supports (for 82599 VF)
493 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
494 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
495 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
500 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
501 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
502 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
503 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
504 { .vendor_id = 0, /* sentinel */ },
507 static const struct rte_eth_desc_lim rx_desc_lim = {
508 .nb_max = IXGBE_MAX_RING_DESC,
509 .nb_min = IXGBE_MIN_RING_DESC,
510 .nb_align = IXGBE_RXD_ALIGN,
513 static const struct rte_eth_desc_lim tx_desc_lim = {
514 .nb_max = IXGBE_MAX_RING_DESC,
515 .nb_min = IXGBE_MIN_RING_DESC,
516 .nb_align = IXGBE_TXD_ALIGN,
517 .nb_seg_max = IXGBE_TX_MAX_SEG,
518 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
521 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
522 .dev_configure = ixgbe_dev_configure,
523 .dev_start = ixgbe_dev_start,
524 .dev_stop = ixgbe_dev_stop,
525 .dev_set_link_up = ixgbe_dev_set_link_up,
526 .dev_set_link_down = ixgbe_dev_set_link_down,
527 .dev_close = ixgbe_dev_close,
528 .dev_reset = ixgbe_dev_reset,
529 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
530 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
531 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
532 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
533 .link_update = ixgbe_dev_link_update,
534 .stats_get = ixgbe_dev_stats_get,
535 .xstats_get = ixgbe_dev_xstats_get,
536 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
537 .stats_reset = ixgbe_dev_stats_reset,
538 .xstats_reset = ixgbe_dev_xstats_reset,
539 .xstats_get_names = ixgbe_dev_xstats_get_names,
540 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
541 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
542 .fw_version_get = ixgbe_fw_version_get,
543 .dev_infos_get = ixgbe_dev_info_get,
544 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
545 .mtu_set = ixgbe_dev_mtu_set,
546 .vlan_filter_set = ixgbe_vlan_filter_set,
547 .vlan_tpid_set = ixgbe_vlan_tpid_set,
548 .vlan_offload_set = ixgbe_vlan_offload_set,
549 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
550 .rx_queue_start = ixgbe_dev_rx_queue_start,
551 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
552 .tx_queue_start = ixgbe_dev_tx_queue_start,
553 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
554 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
555 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
556 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
557 .rx_queue_release = ixgbe_dev_rx_queue_release,
558 .rx_queue_count = ixgbe_dev_rx_queue_count,
559 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
560 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
561 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
562 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
563 .tx_queue_release = ixgbe_dev_tx_queue_release,
564 .dev_led_on = ixgbe_dev_led_on,
565 .dev_led_off = ixgbe_dev_led_off,
566 .flow_ctrl_get = ixgbe_flow_ctrl_get,
567 .flow_ctrl_set = ixgbe_flow_ctrl_set,
568 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
569 .mac_addr_add = ixgbe_add_rar,
570 .mac_addr_remove = ixgbe_remove_rar,
571 .mac_addr_set = ixgbe_set_default_mac_addr,
572 .uc_hash_table_set = ixgbe_uc_hash_table_set,
573 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
574 .mirror_rule_set = ixgbe_mirror_rule_set,
575 .mirror_rule_reset = ixgbe_mirror_rule_reset,
576 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
577 .reta_update = ixgbe_dev_rss_reta_update,
578 .reta_query = ixgbe_dev_rss_reta_query,
579 .rss_hash_update = ixgbe_dev_rss_hash_update,
580 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
581 .filter_ctrl = ixgbe_dev_filter_ctrl,
582 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
583 .rxq_info_get = ixgbe_rxq_info_get,
584 .txq_info_get = ixgbe_txq_info_get,
585 .timesync_enable = ixgbe_timesync_enable,
586 .timesync_disable = ixgbe_timesync_disable,
587 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
588 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
589 .get_reg = ixgbe_get_regs,
590 .get_eeprom_length = ixgbe_get_eeprom_length,
591 .get_eeprom = ixgbe_get_eeprom,
592 .set_eeprom = ixgbe_set_eeprom,
593 .get_module_info = ixgbe_get_module_info,
594 .get_module_eeprom = ixgbe_get_module_eeprom,
595 .get_dcb_info = ixgbe_dev_get_dcb_info,
596 .timesync_adjust_time = ixgbe_timesync_adjust_time,
597 .timesync_read_time = ixgbe_timesync_read_time,
598 .timesync_write_time = ixgbe_timesync_write_time,
599 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
600 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
601 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
602 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
603 .tm_ops_get = ixgbe_tm_ops_get,
607 * dev_ops for virtual function, bare necessities for basic vf
608 * operation have been implemented
610 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
611 .dev_configure = ixgbevf_dev_configure,
612 .dev_start = ixgbevf_dev_start,
613 .dev_stop = ixgbevf_dev_stop,
614 .link_update = ixgbevf_dev_link_update,
615 .stats_get = ixgbevf_dev_stats_get,
616 .xstats_get = ixgbevf_dev_xstats_get,
617 .stats_reset = ixgbevf_dev_stats_reset,
618 .xstats_reset = ixgbevf_dev_stats_reset,
619 .xstats_get_names = ixgbevf_dev_xstats_get_names,
620 .dev_close = ixgbevf_dev_close,
621 .dev_reset = ixgbevf_dev_reset,
622 .promiscuous_enable = ixgbevf_dev_promiscuous_enable,
623 .promiscuous_disable = ixgbevf_dev_promiscuous_disable,
624 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
625 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
626 .dev_infos_get = ixgbevf_dev_info_get,
627 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
628 .mtu_set = ixgbevf_dev_set_mtu,
629 .vlan_filter_set = ixgbevf_vlan_filter_set,
630 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
631 .vlan_offload_set = ixgbevf_vlan_offload_set,
632 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
633 .rx_queue_release = ixgbe_dev_rx_queue_release,
634 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
635 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
636 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
637 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
638 .tx_queue_release = ixgbe_dev_tx_queue_release,
639 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
640 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
641 .mac_addr_add = ixgbevf_add_mac_addr,
642 .mac_addr_remove = ixgbevf_remove_mac_addr,
643 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
644 .rxq_info_get = ixgbe_rxq_info_get,
645 .txq_info_get = ixgbe_txq_info_get,
646 .mac_addr_set = ixgbevf_set_default_mac_addr,
647 .get_reg = ixgbevf_get_regs,
648 .reta_update = ixgbe_dev_rss_reta_update,
649 .reta_query = ixgbe_dev_rss_reta_query,
650 .rss_hash_update = ixgbe_dev_rss_hash_update,
651 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
654 /* store statistics names and its offset in stats structure */
655 struct rte_ixgbe_xstats_name_off {
656 char name[RTE_ETH_XSTATS_NAME_SIZE];
660 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
661 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
662 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
663 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
664 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
665 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
666 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
667 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
668 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
669 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
670 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
671 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
672 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
673 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
674 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
675 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
677 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
679 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
680 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
681 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
682 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
683 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
684 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
685 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
686 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
687 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
688 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
689 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
690 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
691 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
692 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
693 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
694 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
695 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
697 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
699 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
700 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
701 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
702 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
704 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
706 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
708 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
710 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
712 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
714 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
717 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
718 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
719 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
721 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
722 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
723 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
724 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
725 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
727 {"rx_fcoe_no_direct_data_placement_ext_buff",
728 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
730 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
732 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
734 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
736 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
738 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
741 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
742 sizeof(rte_ixgbe_stats_strings[0]))
744 /* MACsec statistics */
745 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
746 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
748 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
749 out_pkts_encrypted)},
750 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
751 out_pkts_protected)},
752 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
753 out_octets_encrypted)},
754 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
755 out_octets_protected)},
756 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
758 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
760 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
762 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
763 in_pkts_unknownsci)},
764 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
765 in_octets_decrypted)},
766 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
767 in_octets_validated)},
768 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
770 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
772 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
774 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
776 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
778 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
780 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
782 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
783 in_pkts_notusingsa)},
786 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
787 sizeof(rte_ixgbe_macsec_strings[0]))
789 /* Per-queue statistics */
790 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
791 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
792 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
793 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
794 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
797 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
798 sizeof(rte_ixgbe_rxq_strings[0]))
799 #define IXGBE_NB_RXQ_PRIO_VALUES 8
801 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
802 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
803 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
804 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
808 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
809 sizeof(rte_ixgbe_txq_strings[0]))
810 #define IXGBE_NB_TXQ_PRIO_VALUES 8
812 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
813 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
816 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
817 sizeof(rte_ixgbevf_stats_strings[0]))
820 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
823 ixgbe_is_sfp(struct ixgbe_hw *hw)
825 switch (hw->phy.type) {
826 case ixgbe_phy_sfp_avago:
827 case ixgbe_phy_sfp_ftl:
828 case ixgbe_phy_sfp_intel:
829 case ixgbe_phy_sfp_unknown:
830 case ixgbe_phy_sfp_passive_tyco:
831 case ixgbe_phy_sfp_passive_unknown:
838 static inline int32_t
839 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
844 status = ixgbe_reset_hw(hw);
846 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
847 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
848 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
849 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
850 IXGBE_WRITE_FLUSH(hw);
852 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
853 status = IXGBE_SUCCESS;
858 ixgbe_enable_intr(struct rte_eth_dev *dev)
860 struct ixgbe_interrupt *intr =
861 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
862 struct ixgbe_hw *hw =
863 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
865 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
866 IXGBE_WRITE_FLUSH(hw);
870 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
873 ixgbe_disable_intr(struct ixgbe_hw *hw)
875 PMD_INIT_FUNC_TRACE();
877 if (hw->mac.type == ixgbe_mac_82598EB) {
878 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
880 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
881 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
882 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
884 IXGBE_WRITE_FLUSH(hw);
888 * This function resets queue statistics mapping registers.
889 * From Niantic datasheet, Initialization of Statistics section:
890 * "...if software requires the queue counters, the RQSMR and TQSM registers
891 * must be re-programmed following a device reset.
894 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
898 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
899 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
900 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
906 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
911 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
912 #define NB_QMAP_FIELDS_PER_QSM_REG 4
913 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
915 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
916 struct ixgbe_stat_mapping_registers *stat_mappings =
917 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
918 uint32_t qsmr_mask = 0;
919 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
923 if ((hw->mac.type != ixgbe_mac_82599EB) &&
924 (hw->mac.type != ixgbe_mac_X540) &&
925 (hw->mac.type != ixgbe_mac_X550) &&
926 (hw->mac.type != ixgbe_mac_X550EM_x) &&
927 (hw->mac.type != ixgbe_mac_X550EM_a))
930 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
931 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
934 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
935 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
936 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
939 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
941 /* Now clear any previous stat_idx set */
942 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
944 stat_mappings->tqsm[n] &= ~clearing_mask;
946 stat_mappings->rqsmr[n] &= ~clearing_mask;
948 q_map = (uint32_t)stat_idx;
949 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
950 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
952 stat_mappings->tqsm[n] |= qsmr_mask;
954 stat_mappings->rqsmr[n] |= qsmr_mask;
956 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
957 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
959 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
960 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
962 /* Now write the mapping in the appropriate register */
964 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
965 stat_mappings->rqsmr[n], n);
966 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
968 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
969 stat_mappings->tqsm[n], n);
970 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
976 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
978 struct ixgbe_stat_mapping_registers *stat_mappings =
979 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
980 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
983 /* write whatever was in stat mapping table to the NIC */
984 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
986 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
989 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
994 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
997 struct ixgbe_dcb_tc_config *tc;
998 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1000 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1001 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1002 for (i = 0; i < dcb_max_tc; i++) {
1003 tc = &dcb_config->tc_config[i];
1004 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1005 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1006 (uint8_t)(100/dcb_max_tc + (i & 1));
1007 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1008 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1009 (uint8_t)(100/dcb_max_tc + (i & 1));
1010 tc->pfc = ixgbe_dcb_pfc_disabled;
1013 /* Initialize default user to priority mapping, UPx->TC0 */
1014 tc = &dcb_config->tc_config[0];
1015 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1016 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1017 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1018 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1019 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1021 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1022 dcb_config->pfc_mode_enable = false;
1023 dcb_config->vt_mode = true;
1024 dcb_config->round_robin_enable = false;
1025 /* support all DCB capabilities in 82599 */
1026 dcb_config->support.capabilities = 0xFF;
1028 /*we only support 4 Tcs for X540, X550 */
1029 if (hw->mac.type == ixgbe_mac_X540 ||
1030 hw->mac.type == ixgbe_mac_X550 ||
1031 hw->mac.type == ixgbe_mac_X550EM_x ||
1032 hw->mac.type == ixgbe_mac_X550EM_a) {
1033 dcb_config->num_tcs.pg_tcs = 4;
1034 dcb_config->num_tcs.pfc_tcs = 4;
1039 * Ensure that all locks are released before first NVM or PHY access
1042 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1047 * Phy lock should not fail in this early stage. If this is the case,
1048 * it is due to an improper exit of the application.
1049 * So force the release of the faulty lock. Release of common lock
1050 * is done automatically by swfw_sync function.
1052 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1053 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1054 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1056 ixgbe_release_swfw_semaphore(hw, mask);
1059 * These ones are more tricky since they are common to all ports; but
1060 * swfw_sync retries last long enough (1s) to be almost sure that if
1061 * lock can not be taken it is due to an improper lock of the
1064 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1065 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1066 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1068 ixgbe_release_swfw_semaphore(hw, mask);
1072 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1073 * It returns 0 on success.
1076 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1078 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1079 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1080 struct ixgbe_hw *hw =
1081 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1082 struct ixgbe_vfta *shadow_vfta =
1083 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1084 struct ixgbe_hwstrip *hwstrip =
1085 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1086 struct ixgbe_dcb_config *dcb_config =
1087 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1088 struct ixgbe_filter_info *filter_info =
1089 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1090 struct ixgbe_bw_conf *bw_conf =
1091 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1096 PMD_INIT_FUNC_TRACE();
1098 ixgbe_dev_macsec_setting_reset(eth_dev);
1100 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1101 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1102 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1103 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1106 * For secondary processes, we don't initialise any further as primary
1107 * has already done this work. Only check we don't need a different
1108 * RX and TX function.
1110 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1111 struct ixgbe_tx_queue *txq;
1112 /* TX queue function in primary, set by last queue initialized
1113 * Tx queue may not initialized by primary process
1115 if (eth_dev->data->tx_queues) {
1116 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1117 ixgbe_set_tx_function(eth_dev, txq);
1119 /* Use default TX function if we get here */
1120 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1121 "Using default TX function.");
1124 ixgbe_set_rx_function(eth_dev);
1129 rte_eth_copy_pci_info(eth_dev, pci_dev);
1131 /* Vendor and Device ID need to be set before init of shared code */
1132 hw->device_id = pci_dev->id.device_id;
1133 hw->vendor_id = pci_dev->id.vendor_id;
1134 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1135 hw->allow_unsupported_sfp = 1;
1137 /* Initialize the shared code (base driver) */
1138 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1139 diag = ixgbe_bypass_init_shared_code(hw);
1141 diag = ixgbe_init_shared_code(hw);
1142 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1144 if (diag != IXGBE_SUCCESS) {
1145 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1149 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1150 PMD_INIT_LOG(ERR, "\nERROR: "
1151 "Firmware recovery mode detected. Limiting functionality.\n"
1152 "Refer to the Intel(R) Ethernet Adapters and Devices "
1153 "User Guide for details on firmware recovery mode.");
1157 /* pick up the PCI bus settings for reporting later */
1158 ixgbe_get_bus_info(hw);
1160 /* Unlock any pending hardware semaphore */
1161 ixgbe_swfw_lock_reset(hw);
1163 #ifdef RTE_LIBRTE_SECURITY
1164 /* Initialize security_ctx only for primary process*/
1165 if (ixgbe_ipsec_ctx_create(eth_dev))
1169 /* Initialize DCB configuration*/
1170 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1171 ixgbe_dcb_init(hw, dcb_config);
1172 /* Get Hardware Flow Control setting */
1173 hw->fc.requested_mode = ixgbe_fc_full;
1174 hw->fc.current_mode = ixgbe_fc_full;
1175 hw->fc.pause_time = IXGBE_FC_PAUSE;
1176 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1177 hw->fc.low_water[i] = IXGBE_FC_LO;
1178 hw->fc.high_water[i] = IXGBE_FC_HI;
1180 hw->fc.send_xon = 1;
1182 /* Make sure we have a good EEPROM before we read from it */
1183 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1184 if (diag != IXGBE_SUCCESS) {
1185 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1189 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1190 diag = ixgbe_bypass_init_hw(hw);
1192 diag = ixgbe_init_hw(hw);
1193 hw->mac.autotry_restart = false;
1194 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1197 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1198 * is called too soon after the kernel driver unbinding/binding occurs.
1199 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1200 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1201 * also called. See ixgbe_identify_phy_82599(). The reason for the
1202 * failure is not known, and only occuts when virtualisation features
1203 * are disabled in the bios. A delay of 100ms was found to be enough by
1204 * trial-and-error, and is doubled to be safe.
1206 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1208 diag = ixgbe_init_hw(hw);
1211 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1212 diag = IXGBE_SUCCESS;
1214 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1215 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1216 "LOM. Please be aware there may be issues associated "
1217 "with your hardware.");
1218 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1219 "please contact your Intel or hardware representative "
1220 "who provided you with this hardware.");
1221 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1222 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1224 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1228 /* Reset the hw statistics */
1229 ixgbe_dev_stats_reset(eth_dev);
1231 /* disable interrupt */
1232 ixgbe_disable_intr(hw);
1234 /* reset mappings for queue statistics hw counters*/
1235 ixgbe_reset_qstat_mappings(hw);
1237 /* Allocate memory for storing MAC addresses */
1238 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1239 hw->mac.num_rar_entries, 0);
1240 if (eth_dev->data->mac_addrs == NULL) {
1242 "Failed to allocate %u bytes needed to store "
1244 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1247 /* Copy the permanent MAC address */
1248 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1249 ð_dev->data->mac_addrs[0]);
1251 /* Allocate memory for storing hash filter MAC addresses */
1252 eth_dev->data->hash_mac_addrs = rte_zmalloc(
1253 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1254 if (eth_dev->data->hash_mac_addrs == NULL) {
1256 "Failed to allocate %d bytes needed to store MAC addresses",
1257 RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1261 /* Pass the information to the rte_eth_dev_close() that it should also
1262 * release the private port resources.
1264 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1266 /* initialize the vfta */
1267 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1269 /* initialize the hw strip bitmap*/
1270 memset(hwstrip, 0, sizeof(*hwstrip));
1272 /* initialize PF if max_vfs not zero */
1273 ixgbe_pf_host_init(eth_dev);
1275 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1276 /* let hardware know driver is loaded */
1277 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1278 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1279 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1280 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1281 IXGBE_WRITE_FLUSH(hw);
1283 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1284 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1285 (int) hw->mac.type, (int) hw->phy.type,
1286 (int) hw->phy.sfp_type);
1288 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1289 (int) hw->mac.type, (int) hw->phy.type);
1291 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1292 eth_dev->data->port_id, pci_dev->id.vendor_id,
1293 pci_dev->id.device_id);
1295 rte_intr_callback_register(intr_handle,
1296 ixgbe_dev_interrupt_handler, eth_dev);
1298 /* enable uio/vfio intr/eventfd mapping */
1299 rte_intr_enable(intr_handle);
1301 /* enable support intr */
1302 ixgbe_enable_intr(eth_dev);
1304 ixgbe_dev_set_link_down(eth_dev);
1306 /* initialize filter info */
1307 memset(filter_info, 0,
1308 sizeof(struct ixgbe_filter_info));
1310 /* initialize 5tuple filter list */
1311 TAILQ_INIT(&filter_info->fivetuple_list);
1313 /* initialize flow director filter list & hash */
1314 ixgbe_fdir_filter_init(eth_dev);
1316 /* initialize l2 tunnel filter list & hash */
1317 ixgbe_l2_tn_filter_init(eth_dev);
1319 /* initialize flow filter lists */
1320 ixgbe_filterlist_init();
1322 /* initialize bandwidth configuration info */
1323 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1325 /* initialize Traffic Manager configuration */
1326 ixgbe_tm_conf_init(eth_dev);
1332 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1334 PMD_INIT_FUNC_TRACE();
1336 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1339 ixgbe_dev_close(eth_dev);
1344 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1346 struct ixgbe_filter_info *filter_info =
1347 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1348 struct ixgbe_5tuple_filter *p_5tuple;
1350 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1351 TAILQ_REMOVE(&filter_info->fivetuple_list,
1356 memset(filter_info->fivetuple_mask, 0,
1357 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1362 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1364 struct ixgbe_hw_fdir_info *fdir_info =
1365 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1366 struct ixgbe_fdir_filter *fdir_filter;
1368 if (fdir_info->hash_map)
1369 rte_free(fdir_info->hash_map);
1370 if (fdir_info->hash_handle)
1371 rte_hash_free(fdir_info->hash_handle);
1373 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1374 TAILQ_REMOVE(&fdir_info->fdir_list,
1377 rte_free(fdir_filter);
1383 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1385 struct ixgbe_l2_tn_info *l2_tn_info =
1386 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1387 struct ixgbe_l2_tn_filter *l2_tn_filter;
1389 if (l2_tn_info->hash_map)
1390 rte_free(l2_tn_info->hash_map);
1391 if (l2_tn_info->hash_handle)
1392 rte_hash_free(l2_tn_info->hash_handle);
1394 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1395 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1398 rte_free(l2_tn_filter);
1404 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1406 struct ixgbe_hw_fdir_info *fdir_info =
1407 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1408 char fdir_hash_name[RTE_HASH_NAMESIZE];
1409 struct rte_hash_parameters fdir_hash_params = {
1410 .name = fdir_hash_name,
1411 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1412 .key_len = sizeof(union ixgbe_atr_input),
1413 .hash_func = rte_hash_crc,
1414 .hash_func_init_val = 0,
1415 .socket_id = rte_socket_id(),
1418 TAILQ_INIT(&fdir_info->fdir_list);
1419 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1420 "fdir_%s", eth_dev->device->name);
1421 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1422 if (!fdir_info->hash_handle) {
1423 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1426 fdir_info->hash_map = rte_zmalloc("ixgbe",
1427 sizeof(struct ixgbe_fdir_filter *) *
1428 IXGBE_MAX_FDIR_FILTER_NUM,
1430 if (!fdir_info->hash_map) {
1432 "Failed to allocate memory for fdir hash map!");
1435 fdir_info->mask_added = FALSE;
1440 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1442 struct ixgbe_l2_tn_info *l2_tn_info =
1443 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1444 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1445 struct rte_hash_parameters l2_tn_hash_params = {
1446 .name = l2_tn_hash_name,
1447 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1448 .key_len = sizeof(struct ixgbe_l2_tn_key),
1449 .hash_func = rte_hash_crc,
1450 .hash_func_init_val = 0,
1451 .socket_id = rte_socket_id(),
1454 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1455 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1456 "l2_tn_%s", eth_dev->device->name);
1457 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1458 if (!l2_tn_info->hash_handle) {
1459 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1462 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1463 sizeof(struct ixgbe_l2_tn_filter *) *
1464 IXGBE_MAX_L2_TN_FILTER_NUM,
1466 if (!l2_tn_info->hash_map) {
1468 "Failed to allocate memory for L2 TN hash map!");
1471 l2_tn_info->e_tag_en = FALSE;
1472 l2_tn_info->e_tag_fwd_en = FALSE;
1473 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1478 * Negotiate mailbox API version with the PF.
1479 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1480 * Then we try to negotiate starting with the most recent one.
1481 * If all negotiation attempts fail, then we will proceed with
1482 * the default one (ixgbe_mbox_api_10).
1485 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1489 /* start with highest supported, proceed down */
1490 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1498 i != RTE_DIM(sup_ver) &&
1499 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1505 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1509 /* Set Organizationally Unique Identifier (OUI) prefix. */
1510 mac_addr->addr_bytes[0] = 0x00;
1511 mac_addr->addr_bytes[1] = 0x09;
1512 mac_addr->addr_bytes[2] = 0xC0;
1513 /* Force indication of locally assigned MAC address. */
1514 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1515 /* Generate the last 3 bytes of the MAC address with a random number. */
1516 random = rte_rand();
1517 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1521 devarg_handle_int(__rte_unused const char *key, const char *value,
1524 uint16_t *n = extra_args;
1526 if (value == NULL || extra_args == NULL)
1529 *n = (uint16_t)strtoul(value, NULL, 0);
1530 if (*n == USHRT_MAX && errno == ERANGE)
1537 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1538 struct rte_devargs *devargs)
1540 struct rte_kvargs *kvlist;
1541 uint16_t pflink_fullchk;
1543 if (devargs == NULL)
1546 kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1550 if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1551 rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1552 devarg_handle_int, &pflink_fullchk) == 0 &&
1553 pflink_fullchk == 1)
1554 adapter->pflink_fullchk = 1;
1556 rte_kvargs_free(kvlist);
1560 * Virtual Function device init
1563 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1567 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1568 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1569 struct ixgbe_hw *hw =
1570 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1571 struct ixgbe_vfta *shadow_vfta =
1572 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1573 struct ixgbe_hwstrip *hwstrip =
1574 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1575 struct rte_ether_addr *perm_addr =
1576 (struct rte_ether_addr *)hw->mac.perm_addr;
1578 PMD_INIT_FUNC_TRACE();
1580 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1581 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1582 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1584 /* for secondary processes, we don't initialise any further as primary
1585 * has already done this work. Only check we don't need a different
1588 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1589 struct ixgbe_tx_queue *txq;
1590 /* TX queue function in primary, set by last queue initialized
1591 * Tx queue may not initialized by primary process
1593 if (eth_dev->data->tx_queues) {
1594 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1595 ixgbe_set_tx_function(eth_dev, txq);
1597 /* Use default TX function if we get here */
1598 PMD_INIT_LOG(NOTICE,
1599 "No TX queues configured yet. Using default TX function.");
1602 ixgbe_set_rx_function(eth_dev);
1607 ixgbevf_parse_devargs(eth_dev->data->dev_private,
1608 pci_dev->device.devargs);
1610 rte_eth_copy_pci_info(eth_dev, pci_dev);
1612 hw->device_id = pci_dev->id.device_id;
1613 hw->vendor_id = pci_dev->id.vendor_id;
1614 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1616 /* initialize the vfta */
1617 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1619 /* initialize the hw strip bitmap*/
1620 memset(hwstrip, 0, sizeof(*hwstrip));
1622 /* Initialize the shared code (base driver) */
1623 diag = ixgbe_init_shared_code(hw);
1624 if (diag != IXGBE_SUCCESS) {
1625 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1629 /* init_mailbox_params */
1630 hw->mbx.ops.init_params(hw);
1632 /* Reset the hw statistics */
1633 ixgbevf_dev_stats_reset(eth_dev);
1635 /* Disable the interrupts for VF */
1636 ixgbevf_intr_disable(eth_dev);
1638 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1639 diag = hw->mac.ops.reset_hw(hw);
1642 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1643 * the underlying PF driver has not assigned a MAC address to the VF.
1644 * In this case, assign a random MAC address.
1646 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1647 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1649 * This error code will be propagated to the app by
1650 * rte_eth_dev_reset, so use a public error code rather than
1651 * the internal-only IXGBE_ERR_RESET_FAILED
1656 /* negotiate mailbox API version to use with the PF. */
1657 ixgbevf_negotiate_api(hw);
1659 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1660 ixgbevf_get_queues(hw, &tcs, &tc);
1662 /* Allocate memory for storing MAC addresses */
1663 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1664 hw->mac.num_rar_entries, 0);
1665 if (eth_dev->data->mac_addrs == NULL) {
1667 "Failed to allocate %u bytes needed to store "
1669 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1673 /* Pass the information to the rte_eth_dev_close() that it should also
1674 * release the private port resources.
1676 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1678 /* Generate a random MAC address, if none was assigned by PF. */
1679 if (rte_is_zero_ether_addr(perm_addr)) {
1680 generate_random_mac_addr(perm_addr);
1681 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1683 rte_free(eth_dev->data->mac_addrs);
1684 eth_dev->data->mac_addrs = NULL;
1687 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1688 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1689 "%02x:%02x:%02x:%02x:%02x:%02x",
1690 perm_addr->addr_bytes[0],
1691 perm_addr->addr_bytes[1],
1692 perm_addr->addr_bytes[2],
1693 perm_addr->addr_bytes[3],
1694 perm_addr->addr_bytes[4],
1695 perm_addr->addr_bytes[5]);
1698 /* Copy the permanent MAC address */
1699 rte_ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1701 /* reset the hardware with the new settings */
1702 diag = hw->mac.ops.start_hw(hw);
1708 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1712 rte_intr_callback_register(intr_handle,
1713 ixgbevf_dev_interrupt_handler, eth_dev);
1714 rte_intr_enable(intr_handle);
1715 ixgbevf_intr_enable(eth_dev);
1717 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1718 eth_dev->data->port_id, pci_dev->id.vendor_id,
1719 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1724 /* Virtual Function device uninit */
1727 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1729 PMD_INIT_FUNC_TRACE();
1731 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1734 ixgbevf_dev_close(eth_dev);
1740 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1741 struct rte_pci_device *pci_dev)
1743 char name[RTE_ETH_NAME_MAX_LEN];
1744 struct rte_eth_dev *pf_ethdev;
1745 struct rte_eth_devargs eth_da;
1748 if (pci_dev->device.devargs) {
1749 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1754 memset(ð_da, 0, sizeof(eth_da));
1756 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1757 sizeof(struct ixgbe_adapter),
1758 eth_dev_pci_specific_init, pci_dev,
1759 eth_ixgbe_dev_init, NULL);
1761 if (retval || eth_da.nb_representor_ports < 1)
1764 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1765 if (pf_ethdev == NULL)
1768 /* probe VF representor ports */
1769 for (i = 0; i < eth_da.nb_representor_ports; i++) {
1770 struct ixgbe_vf_info *vfinfo;
1771 struct ixgbe_vf_representor representor;
1773 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1774 pf_ethdev->data->dev_private);
1775 if (vfinfo == NULL) {
1777 "no virtual functions supported by PF");
1781 representor.vf_id = eth_da.representor_ports[i];
1782 representor.switch_domain_id = vfinfo->switch_domain_id;
1783 representor.pf_ethdev = pf_ethdev;
1785 /* representor port net_bdf_port */
1786 snprintf(name, sizeof(name), "net_%s_representor_%d",
1787 pci_dev->device.name,
1788 eth_da.representor_ports[i]);
1790 retval = rte_eth_dev_create(&pci_dev->device, name,
1791 sizeof(struct ixgbe_vf_representor), NULL, NULL,
1792 ixgbe_vf_representor_init, &representor);
1795 PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1796 "representor %s.", name);
1802 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1804 struct rte_eth_dev *ethdev;
1806 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1810 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1811 return rte_eth_dev_pci_generic_remove(pci_dev,
1812 ixgbe_vf_representor_uninit);
1814 return rte_eth_dev_pci_generic_remove(pci_dev,
1815 eth_ixgbe_dev_uninit);
1818 static struct rte_pci_driver rte_ixgbe_pmd = {
1819 .id_table = pci_id_ixgbe_map,
1820 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1821 .probe = eth_ixgbe_pci_probe,
1822 .remove = eth_ixgbe_pci_remove,
1825 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1826 struct rte_pci_device *pci_dev)
1828 return rte_eth_dev_pci_generic_probe(pci_dev,
1829 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1832 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1834 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1838 * virtual function driver struct
1840 static struct rte_pci_driver rte_ixgbevf_pmd = {
1841 .id_table = pci_id_ixgbevf_map,
1842 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1843 .probe = eth_ixgbevf_pci_probe,
1844 .remove = eth_ixgbevf_pci_remove,
1848 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1850 struct ixgbe_hw *hw =
1851 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1852 struct ixgbe_vfta *shadow_vfta =
1853 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1858 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1859 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1860 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1865 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1867 /* update local VFTA copy */
1868 shadow_vfta->vfta[vid_idx] = vfta;
1874 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1877 ixgbe_vlan_hw_strip_enable(dev, queue);
1879 ixgbe_vlan_hw_strip_disable(dev, queue);
1883 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1884 enum rte_vlan_type vlan_type,
1887 struct ixgbe_hw *hw =
1888 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1893 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1894 qinq &= IXGBE_DMATXCTL_GDV;
1896 switch (vlan_type) {
1897 case ETH_VLAN_TYPE_INNER:
1899 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1900 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1901 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1902 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1903 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1904 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1905 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1908 PMD_DRV_LOG(ERR, "Inner type is not supported"
1912 case ETH_VLAN_TYPE_OUTER:
1914 /* Only the high 16-bits is valid */
1915 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1916 IXGBE_EXVET_VET_EXT_SHIFT);
1918 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1919 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1920 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1921 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1922 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1923 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1924 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1930 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1938 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1940 struct ixgbe_hw *hw =
1941 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1944 PMD_INIT_FUNC_TRACE();
1946 /* Filter Table Disable */
1947 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1948 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1950 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1954 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1956 struct ixgbe_hw *hw =
1957 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1958 struct ixgbe_vfta *shadow_vfta =
1959 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1963 PMD_INIT_FUNC_TRACE();
1965 /* Filter Table Enable */
1966 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1967 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1968 vlnctrl |= IXGBE_VLNCTRL_VFE;
1970 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1972 /* write whatever is in local vfta copy */
1973 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1974 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1978 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1980 struct ixgbe_hwstrip *hwstrip =
1981 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1982 struct ixgbe_rx_queue *rxq;
1984 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1988 IXGBE_SET_HWSTRIP(hwstrip, queue);
1990 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1992 if (queue >= dev->data->nb_rx_queues)
1995 rxq = dev->data->rx_queues[queue];
1998 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1999 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2001 rxq->vlan_flags = PKT_RX_VLAN;
2002 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2007 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2009 struct ixgbe_hw *hw =
2010 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2013 PMD_INIT_FUNC_TRACE();
2015 if (hw->mac.type == ixgbe_mac_82598EB) {
2016 /* No queue level support */
2017 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2021 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2022 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2023 ctrl &= ~IXGBE_RXDCTL_VME;
2024 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2026 /* record those setting for HW strip per queue */
2027 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2031 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2033 struct ixgbe_hw *hw =
2034 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2037 PMD_INIT_FUNC_TRACE();
2039 if (hw->mac.type == ixgbe_mac_82598EB) {
2040 /* No queue level supported */
2041 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2045 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2046 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2047 ctrl |= IXGBE_RXDCTL_VME;
2048 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2050 /* record those setting for HW strip per queue */
2051 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2055 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2057 struct ixgbe_hw *hw =
2058 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2061 PMD_INIT_FUNC_TRACE();
2063 /* DMATXCTRL: Geric Double VLAN Disable */
2064 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2065 ctrl &= ~IXGBE_DMATXCTL_GDV;
2066 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2068 /* CTRL_EXT: Global Double VLAN Disable */
2069 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2070 ctrl &= ~IXGBE_EXTENDED_VLAN;
2071 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2076 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2078 struct ixgbe_hw *hw =
2079 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2082 PMD_INIT_FUNC_TRACE();
2084 /* DMATXCTRL: Geric Double VLAN Enable */
2085 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2086 ctrl |= IXGBE_DMATXCTL_GDV;
2087 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2089 /* CTRL_EXT: Global Double VLAN Enable */
2090 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2091 ctrl |= IXGBE_EXTENDED_VLAN;
2092 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2094 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2095 if (hw->mac.type == ixgbe_mac_X550 ||
2096 hw->mac.type == ixgbe_mac_X550EM_x ||
2097 hw->mac.type == ixgbe_mac_X550EM_a) {
2098 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2099 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2100 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2104 * VET EXT field in the EXVET register = 0x8100 by default
2105 * So no need to change. Same to VT field of DMATXCTL register
2110 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2112 struct ixgbe_hw *hw =
2113 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2114 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2117 struct ixgbe_rx_queue *rxq;
2120 PMD_INIT_FUNC_TRACE();
2122 if (hw->mac.type == ixgbe_mac_82598EB) {
2123 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2124 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2125 ctrl |= IXGBE_VLNCTRL_VME;
2126 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2128 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2129 ctrl &= ~IXGBE_VLNCTRL_VME;
2130 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2134 * Other 10G NIC, the VLAN strip can be setup
2135 * per queue in RXDCTL
2137 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2138 rxq = dev->data->rx_queues[i];
2139 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2140 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2141 ctrl |= IXGBE_RXDCTL_VME;
2144 ctrl &= ~IXGBE_RXDCTL_VME;
2147 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2149 /* record those setting for HW strip per queue */
2150 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2156 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2159 struct rte_eth_rxmode *rxmode;
2160 struct ixgbe_rx_queue *rxq;
2162 if (mask & ETH_VLAN_STRIP_MASK) {
2163 rxmode = &dev->data->dev_conf.rxmode;
2164 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2165 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2166 rxq = dev->data->rx_queues[i];
2167 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2170 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2171 rxq = dev->data->rx_queues[i];
2172 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2178 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2180 struct rte_eth_rxmode *rxmode;
2181 rxmode = &dev->data->dev_conf.rxmode;
2183 if (mask & ETH_VLAN_STRIP_MASK) {
2184 ixgbe_vlan_hw_strip_config(dev);
2187 if (mask & ETH_VLAN_FILTER_MASK) {
2188 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2189 ixgbe_vlan_hw_filter_enable(dev);
2191 ixgbe_vlan_hw_filter_disable(dev);
2194 if (mask & ETH_VLAN_EXTEND_MASK) {
2195 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2196 ixgbe_vlan_hw_extend_enable(dev);
2198 ixgbe_vlan_hw_extend_disable(dev);
2205 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2207 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2209 ixgbe_vlan_offload_config(dev, mask);
2215 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2217 struct ixgbe_hw *hw =
2218 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2219 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2220 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2222 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2223 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2227 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2229 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2234 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2237 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2243 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2244 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2245 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2246 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2251 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2253 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2254 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2255 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2256 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2258 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2259 /* check multi-queue mode */
2260 switch (dev_conf->rxmode.mq_mode) {
2261 case ETH_MQ_RX_VMDQ_DCB:
2262 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2264 case ETH_MQ_RX_VMDQ_DCB_RSS:
2265 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2266 PMD_INIT_LOG(ERR, "SRIOV active,"
2267 " unsupported mq_mode rx %d.",
2268 dev_conf->rxmode.mq_mode);
2271 case ETH_MQ_RX_VMDQ_RSS:
2272 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2273 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2274 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2275 PMD_INIT_LOG(ERR, "SRIOV is active,"
2276 " invalid queue number"
2277 " for VMDQ RSS, allowed"
2278 " value are 1, 2 or 4.");
2282 case ETH_MQ_RX_VMDQ_ONLY:
2283 case ETH_MQ_RX_NONE:
2284 /* if nothing mq mode configure, use default scheme */
2285 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2287 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2288 /* SRIOV only works in VMDq enable mode */
2289 PMD_INIT_LOG(ERR, "SRIOV is active,"
2290 " wrong mq_mode rx %d.",
2291 dev_conf->rxmode.mq_mode);
2295 switch (dev_conf->txmode.mq_mode) {
2296 case ETH_MQ_TX_VMDQ_DCB:
2297 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2298 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2300 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2301 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2305 /* check valid queue number */
2306 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2307 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2308 PMD_INIT_LOG(ERR, "SRIOV is active,"
2309 " nb_rx_q=%d nb_tx_q=%d queue number"
2310 " must be less than or equal to %d.",
2312 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2316 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2317 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2321 /* check configuration for vmdb+dcb mode */
2322 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2323 const struct rte_eth_vmdq_dcb_conf *conf;
2325 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2326 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2327 IXGBE_VMDQ_DCB_NB_QUEUES);
2330 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2331 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2332 conf->nb_queue_pools == ETH_32_POOLS)) {
2333 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2334 " nb_queue_pools must be %d or %d.",
2335 ETH_16_POOLS, ETH_32_POOLS);
2339 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2340 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2342 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2343 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2344 IXGBE_VMDQ_DCB_NB_QUEUES);
2347 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2348 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2349 conf->nb_queue_pools == ETH_32_POOLS)) {
2350 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2351 " nb_queue_pools != %d and"
2352 " nb_queue_pools != %d.",
2353 ETH_16_POOLS, ETH_32_POOLS);
2358 /* For DCB mode check our configuration before we go further */
2359 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2360 const struct rte_eth_dcb_rx_conf *conf;
2362 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2363 if (!(conf->nb_tcs == ETH_4_TCS ||
2364 conf->nb_tcs == ETH_8_TCS)) {
2365 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2366 " and nb_tcs != %d.",
2367 ETH_4_TCS, ETH_8_TCS);
2372 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2373 const struct rte_eth_dcb_tx_conf *conf;
2375 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2376 if (!(conf->nb_tcs == ETH_4_TCS ||
2377 conf->nb_tcs == ETH_8_TCS)) {
2378 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2379 " and nb_tcs != %d.",
2380 ETH_4_TCS, ETH_8_TCS);
2386 * When DCB/VT is off, maximum number of queues changes,
2387 * except for 82598EB, which remains constant.
2389 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2390 hw->mac.type != ixgbe_mac_82598EB) {
2391 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2393 "Neither VT nor DCB are enabled, "
2395 IXGBE_NONE_MODE_TX_NB_QUEUES);
2404 ixgbe_dev_configure(struct rte_eth_dev *dev)
2406 struct ixgbe_interrupt *intr =
2407 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2408 struct ixgbe_adapter *adapter = dev->data->dev_private;
2411 PMD_INIT_FUNC_TRACE();
2413 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2414 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2416 /* multipe queue mode checking */
2417 ret = ixgbe_check_mq_mode(dev);
2419 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2424 /* set flag to update link status after init */
2425 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2428 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2429 * allocation or vector Rx preconditions we will reset it.
2431 adapter->rx_bulk_alloc_allowed = true;
2432 adapter->rx_vec_allowed = true;
2438 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2440 struct ixgbe_hw *hw =
2441 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2442 struct ixgbe_interrupt *intr =
2443 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2446 /* only set up it on X550EM_X */
2447 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2448 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2449 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2450 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2451 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2452 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2457 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2458 uint16_t tx_rate, uint64_t q_msk)
2460 struct ixgbe_hw *hw;
2461 struct ixgbe_vf_info *vfinfo;
2462 struct rte_eth_link link;
2463 uint8_t nb_q_per_pool;
2464 uint32_t queue_stride;
2465 uint32_t queue_idx, idx = 0, vf_idx;
2467 uint16_t total_rate = 0;
2468 struct rte_pci_device *pci_dev;
2471 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2472 ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2476 if (vf >= pci_dev->max_vfs)
2479 if (tx_rate > link.link_speed)
2485 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2486 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2487 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2488 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2489 queue_idx = vf * queue_stride;
2490 queue_end = queue_idx + nb_q_per_pool - 1;
2491 if (queue_end >= hw->mac.max_tx_queues)
2495 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2498 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2500 total_rate += vfinfo[vf_idx].tx_rate[idx];
2506 /* Store tx_rate for this vf. */
2507 for (idx = 0; idx < nb_q_per_pool; idx++) {
2508 if (((uint64_t)0x1 << idx) & q_msk) {
2509 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2510 vfinfo[vf].tx_rate[idx] = tx_rate;
2511 total_rate += tx_rate;
2515 if (total_rate > dev->data->dev_link.link_speed) {
2516 /* Reset stored TX rate of the VF if it causes exceed
2519 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2523 /* Set RTTBCNRC of each queue/pool for vf X */
2524 for (; queue_idx <= queue_end; queue_idx++) {
2526 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2534 * Configure device link speed and setup link.
2535 * It returns 0 on success.
2538 ixgbe_dev_start(struct rte_eth_dev *dev)
2540 struct ixgbe_hw *hw =
2541 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2542 struct ixgbe_vf_info *vfinfo =
2543 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2544 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2545 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2546 uint32_t intr_vector = 0;
2547 int err, link_up = 0, negotiate = 0;
2549 uint32_t allowed_speeds = 0;
2553 uint32_t *link_speeds;
2554 struct ixgbe_tm_conf *tm_conf =
2555 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2556 struct ixgbe_macsec_setting *macsec_setting =
2557 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2559 PMD_INIT_FUNC_TRACE();
2561 /* IXGBE devices don't support:
2562 * - half duplex (checked afterwards for valid speeds)
2563 * - fixed speed: TODO implement
2565 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2567 "Invalid link_speeds for port %u, fix speed not supported",
2568 dev->data->port_id);
2572 /* Stop the link setup handler before resetting the HW. */
2573 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2575 /* disable uio/vfio intr/eventfd mapping */
2576 rte_intr_disable(intr_handle);
2579 hw->adapter_stopped = 0;
2580 ixgbe_stop_adapter(hw);
2582 /* reinitialize adapter
2583 * this calls reset and start
2585 status = ixgbe_pf_reset_hw(hw);
2588 hw->mac.ops.start_hw(hw);
2589 hw->mac.get_link_status = true;
2591 /* configure PF module if SRIOV enabled */
2592 ixgbe_pf_host_configure(dev);
2594 ixgbe_dev_phy_intr_setup(dev);
2596 /* check and configure queue intr-vector mapping */
2597 if ((rte_intr_cap_multiple(intr_handle) ||
2598 !RTE_ETH_DEV_SRIOV(dev).active) &&
2599 dev->data->dev_conf.intr_conf.rxq != 0) {
2600 intr_vector = dev->data->nb_rx_queues;
2601 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2602 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2603 IXGBE_MAX_INTR_QUEUE_NUM);
2606 if (rte_intr_efd_enable(intr_handle, intr_vector))
2610 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2611 intr_handle->intr_vec =
2612 rte_zmalloc("intr_vec",
2613 dev->data->nb_rx_queues * sizeof(int), 0);
2614 if (intr_handle->intr_vec == NULL) {
2615 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2616 " intr_vec", dev->data->nb_rx_queues);
2621 /* confiugre msix for sleep until rx interrupt */
2622 ixgbe_configure_msix(dev);
2624 /* initialize transmission unit */
2625 ixgbe_dev_tx_init(dev);
2627 /* This can fail when allocating mbufs for descriptor rings */
2628 err = ixgbe_dev_rx_init(dev);
2630 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2634 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2635 ETH_VLAN_EXTEND_MASK;
2636 err = ixgbe_vlan_offload_config(dev, mask);
2638 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2642 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2643 /* Enable vlan filtering for VMDq */
2644 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2647 /* Configure DCB hw */
2648 ixgbe_configure_dcb(dev);
2650 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2651 err = ixgbe_fdir_configure(dev);
2656 /* Restore vf rate limit */
2657 if (vfinfo != NULL) {
2658 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2659 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2660 if (vfinfo[vf].tx_rate[idx] != 0)
2661 ixgbe_set_vf_rate_limit(
2663 vfinfo[vf].tx_rate[idx],
2667 ixgbe_restore_statistics_mapping(dev);
2669 err = ixgbe_dev_rxtx_start(dev);
2671 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2675 /* Skip link setup if loopback mode is enabled. */
2676 if (dev->data->dev_conf.lpbk_mode != 0) {
2677 err = ixgbe_check_supported_loopback_mode(dev);
2679 PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2682 goto skip_link_setup;
2686 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2687 err = hw->mac.ops.setup_sfp(hw);
2692 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2693 /* Turn on the copper */
2694 ixgbe_set_phy_power(hw, true);
2696 /* Turn on the laser */
2697 ixgbe_enable_tx_laser(hw);
2700 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2703 dev->data->dev_link.link_status = link_up;
2705 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2709 switch (hw->mac.type) {
2710 case ixgbe_mac_X550:
2711 case ixgbe_mac_X550EM_x:
2712 case ixgbe_mac_X550EM_a:
2713 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2714 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G |
2716 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2717 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2718 allowed_speeds = ETH_LINK_SPEED_10M |
2719 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2722 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2726 link_speeds = &dev->data->dev_conf.link_speeds;
2727 if (*link_speeds & ~allowed_speeds) {
2728 PMD_INIT_LOG(ERR, "Invalid link setting");
2733 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2734 switch (hw->mac.type) {
2735 case ixgbe_mac_82598EB:
2736 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2738 case ixgbe_mac_82599EB:
2739 case ixgbe_mac_X540:
2740 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2742 case ixgbe_mac_X550:
2743 case ixgbe_mac_X550EM_x:
2744 case ixgbe_mac_X550EM_a:
2745 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2748 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2751 if (*link_speeds & ETH_LINK_SPEED_10G)
2752 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2753 if (*link_speeds & ETH_LINK_SPEED_5G)
2754 speed |= IXGBE_LINK_SPEED_5GB_FULL;
2755 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2756 speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2757 if (*link_speeds & ETH_LINK_SPEED_1G)
2758 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2759 if (*link_speeds & ETH_LINK_SPEED_100M)
2760 speed |= IXGBE_LINK_SPEED_100_FULL;
2761 if (*link_speeds & ETH_LINK_SPEED_10M)
2762 speed |= IXGBE_LINK_SPEED_10_FULL;
2765 err = ixgbe_setup_link(hw, speed, link_up);
2771 if (rte_intr_allow_others(intr_handle)) {
2772 /* check if lsc interrupt is enabled */
2773 if (dev->data->dev_conf.intr_conf.lsc != 0)
2774 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2776 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2777 ixgbe_dev_macsec_interrupt_setup(dev);
2779 rte_intr_callback_unregister(intr_handle,
2780 ixgbe_dev_interrupt_handler, dev);
2781 if (dev->data->dev_conf.intr_conf.lsc != 0)
2782 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2783 " no intr multiplex");
2786 /* check if rxq interrupt is enabled */
2787 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2788 rte_intr_dp_is_en(intr_handle))
2789 ixgbe_dev_rxq_interrupt_setup(dev);
2791 /* enable uio/vfio intr/eventfd mapping */
2792 rte_intr_enable(intr_handle);
2794 /* resume enabled intr since hw reset */
2795 ixgbe_enable_intr(dev);
2796 ixgbe_l2_tunnel_conf(dev);
2797 ixgbe_filter_restore(dev);
2799 if (tm_conf->root && !tm_conf->committed)
2800 PMD_DRV_LOG(WARNING,
2801 "please call hierarchy_commit() "
2802 "before starting the port");
2805 * Update link status right before return, because it may
2806 * start link configuration process in a separate thread.
2808 ixgbe_dev_link_update(dev, 0);
2810 /* setup the macsec setting register */
2811 if (macsec_setting->offload_en)
2812 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2817 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2818 ixgbe_dev_clear_queues(dev);
2823 * Stop device: disable rx and tx functions to allow for reconfiguring.
2826 ixgbe_dev_stop(struct rte_eth_dev *dev)
2828 struct rte_eth_link link;
2829 struct ixgbe_adapter *adapter = dev->data->dev_private;
2830 struct ixgbe_hw *hw =
2831 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2832 struct ixgbe_vf_info *vfinfo =
2833 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2834 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2835 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2837 struct ixgbe_tm_conf *tm_conf =
2838 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2840 if (hw->adapter_stopped)
2843 PMD_INIT_FUNC_TRACE();
2845 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2847 /* disable interrupts */
2848 ixgbe_disable_intr(hw);
2851 ixgbe_pf_reset_hw(hw);
2852 hw->adapter_stopped = 0;
2855 ixgbe_stop_adapter(hw);
2857 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2858 vfinfo[vf].clear_to_send = false;
2860 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2861 /* Turn off the copper */
2862 ixgbe_set_phy_power(hw, false);
2864 /* Turn off the laser */
2865 ixgbe_disable_tx_laser(hw);
2868 ixgbe_dev_clear_queues(dev);
2870 /* Clear stored conf */
2871 dev->data->scattered_rx = 0;
2874 /* Clear recorded link status */
2875 memset(&link, 0, sizeof(link));
2876 rte_eth_linkstatus_set(dev, &link);
2878 if (!rte_intr_allow_others(intr_handle))
2879 /* resume to the default handler */
2880 rte_intr_callback_register(intr_handle,
2881 ixgbe_dev_interrupt_handler,
2884 /* Clean datapath event and queue/vec mapping */
2885 rte_intr_efd_disable(intr_handle);
2886 if (intr_handle->intr_vec != NULL) {
2887 rte_free(intr_handle->intr_vec);
2888 intr_handle->intr_vec = NULL;
2891 /* reset hierarchy commit */
2892 tm_conf->committed = false;
2894 adapter->rss_reta_updated = 0;
2896 hw->adapter_stopped = true;
2900 * Set device link up: enable tx.
2903 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2905 struct ixgbe_hw *hw =
2906 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2907 if (hw->mac.type == ixgbe_mac_82599EB) {
2908 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2909 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2910 /* Not suported in bypass mode */
2911 PMD_INIT_LOG(ERR, "Set link up is not supported "
2912 "by device id 0x%x", hw->device_id);
2918 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2919 /* Turn on the copper */
2920 ixgbe_set_phy_power(hw, true);
2922 /* Turn on the laser */
2923 ixgbe_enable_tx_laser(hw);
2924 ixgbe_dev_link_update(dev, 0);
2931 * Set device link down: disable tx.
2934 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2936 struct ixgbe_hw *hw =
2937 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2938 if (hw->mac.type == ixgbe_mac_82599EB) {
2939 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2940 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2941 /* Not suported in bypass mode */
2942 PMD_INIT_LOG(ERR, "Set link down is not supported "
2943 "by device id 0x%x", hw->device_id);
2949 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2950 /* Turn off the copper */
2951 ixgbe_set_phy_power(hw, false);
2953 /* Turn off the laser */
2954 ixgbe_disable_tx_laser(hw);
2955 ixgbe_dev_link_update(dev, 0);
2962 * Reset and stop device.
2965 ixgbe_dev_close(struct rte_eth_dev *dev)
2967 struct ixgbe_hw *hw =
2968 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2969 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2970 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2974 PMD_INIT_FUNC_TRACE();
2976 ixgbe_pf_reset_hw(hw);
2978 ixgbe_dev_stop(dev);
2980 ixgbe_dev_free_queues(dev);
2982 ixgbe_disable_pcie_master(hw);
2984 /* reprogram the RAR[0] in case user changed it. */
2985 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2987 dev->dev_ops = NULL;
2988 dev->rx_pkt_burst = NULL;
2989 dev->tx_pkt_burst = NULL;
2991 /* Unlock any pending hardware semaphore */
2992 ixgbe_swfw_lock_reset(hw);
2994 /* disable uio intr before callback unregister */
2995 rte_intr_disable(intr_handle);
2998 ret = rte_intr_callback_unregister(intr_handle,
2999 ixgbe_dev_interrupt_handler, dev);
3000 if (ret >= 0 || ret == -ENOENT) {
3002 } else if (ret != -EAGAIN) {
3004 "intr callback unregister failed: %d",
3008 } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3010 /* cancel the delay handler before remove dev */
3011 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3013 /* uninitialize PF if max_vfs not zero */
3014 ixgbe_pf_host_uninit(dev);
3016 /* remove all the fdir filters & hash */
3017 ixgbe_fdir_filter_uninit(dev);
3019 /* remove all the L2 tunnel filters & hash */
3020 ixgbe_l2_tn_filter_uninit(dev);
3022 /* Remove all ntuple filters of the device */
3023 ixgbe_ntuple_filter_uninit(dev);
3025 /* clear all the filters list */
3026 ixgbe_filterlist_flush();
3028 /* Remove all Traffic Manager configuration */
3029 ixgbe_tm_conf_uninit(dev);
3031 #ifdef RTE_LIBRTE_SECURITY
3032 rte_free(dev->security_ctx);
3041 ixgbe_dev_reset(struct rte_eth_dev *dev)
3045 /* When a DPDK PMD PF begin to reset PF port, it should notify all
3046 * its VF to make them align with it. The detailed notification
3047 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3048 * To avoid unexpected behavior in VF, currently reset of PF with
3049 * SR-IOV activation is not supported. It might be supported later.
3051 if (dev->data->sriov.active)
3054 ret = eth_ixgbe_dev_uninit(dev);
3058 ret = eth_ixgbe_dev_init(dev, NULL);
3064 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3065 struct ixgbe_hw_stats *hw_stats,
3066 struct ixgbe_macsec_stats *macsec_stats,
3067 uint64_t *total_missed_rx, uint64_t *total_qbrc,
3068 uint64_t *total_qprc, uint64_t *total_qprdc)
3070 uint32_t bprc, lxon, lxoff, total;
3071 uint32_t delta_gprc = 0;
3073 /* Workaround for RX byte count not including CRC bytes when CRC
3074 * strip is enabled. CRC bytes are removed from counters when crc_strip
3077 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3078 IXGBE_HLREG0_RXCRCSTRP);
3080 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3081 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3082 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3083 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3085 for (i = 0; i < 8; i++) {
3086 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3088 /* global total per queue */
3089 hw_stats->mpc[i] += mp;
3090 /* Running comprehensive total for stats display */
3091 *total_missed_rx += hw_stats->mpc[i];
3092 if (hw->mac.type == ixgbe_mac_82598EB) {
3093 hw_stats->rnbc[i] +=
3094 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3095 hw_stats->pxonrxc[i] +=
3096 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3097 hw_stats->pxoffrxc[i] +=
3098 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3100 hw_stats->pxonrxc[i] +=
3101 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3102 hw_stats->pxoffrxc[i] +=
3103 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3104 hw_stats->pxon2offc[i] +=
3105 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3107 hw_stats->pxontxc[i] +=
3108 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3109 hw_stats->pxofftxc[i] +=
3110 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3112 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3113 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3114 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3115 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3117 delta_gprc += delta_qprc;
3119 hw_stats->qprc[i] += delta_qprc;
3120 hw_stats->qptc[i] += delta_qptc;
3122 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3123 hw_stats->qbrc[i] +=
3124 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3126 hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3128 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3129 hw_stats->qbtc[i] +=
3130 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3132 hw_stats->qprdc[i] += delta_qprdc;
3133 *total_qprdc += hw_stats->qprdc[i];
3135 *total_qprc += hw_stats->qprc[i];
3136 *total_qbrc += hw_stats->qbrc[i];
3138 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3139 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3140 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3143 * An errata states that gprc actually counts good + missed packets:
3144 * Workaround to set gprc to summated queue packet receives
3146 hw_stats->gprc = *total_qprc;
3148 if (hw->mac.type != ixgbe_mac_82598EB) {
3149 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3150 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3151 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3152 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3153 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3154 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3155 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3156 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3158 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3159 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3160 /* 82598 only has a counter in the high register */
3161 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3162 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3163 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3165 uint64_t old_tpr = hw_stats->tpr;
3167 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3168 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3171 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3173 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3174 hw_stats->gptc += delta_gptc;
3175 hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3176 hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3179 * Workaround: mprc hardware is incorrectly counting
3180 * broadcasts, so for now we subtract those.
3182 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3183 hw_stats->bprc += bprc;
3184 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3185 if (hw->mac.type == ixgbe_mac_82598EB)
3186 hw_stats->mprc -= bprc;
3188 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3189 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3190 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3191 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3192 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3193 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3195 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3196 hw_stats->lxontxc += lxon;
3197 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3198 hw_stats->lxofftxc += lxoff;
3199 total = lxon + lxoff;
3201 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3202 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3203 hw_stats->gptc -= total;
3204 hw_stats->mptc -= total;
3205 hw_stats->ptc64 -= total;
3206 hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3208 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3209 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3210 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3211 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3212 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3213 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3214 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3215 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3216 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3217 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3218 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3219 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3220 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3221 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3222 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3223 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3224 /* Only read FCOE on 82599 */
3225 if (hw->mac.type != ixgbe_mac_82598EB) {
3226 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3227 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3228 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3229 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3230 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3233 /* Flow Director Stats registers */
3234 if (hw->mac.type != ixgbe_mac_82598EB) {
3235 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3236 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3237 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3238 IXGBE_FDIRUSTAT) & 0xFFFF;
3239 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3240 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3241 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3242 IXGBE_FDIRFSTAT) & 0xFFFF;
3243 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3244 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3246 /* MACsec Stats registers */
3247 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3248 macsec_stats->out_pkts_encrypted +=
3249 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3250 macsec_stats->out_pkts_protected +=
3251 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3252 macsec_stats->out_octets_encrypted +=
3253 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3254 macsec_stats->out_octets_protected +=
3255 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3256 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3257 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3258 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3259 macsec_stats->in_pkts_unknownsci +=
3260 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3261 macsec_stats->in_octets_decrypted +=
3262 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3263 macsec_stats->in_octets_validated +=
3264 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3265 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3266 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3267 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3268 for (i = 0; i < 2; i++) {
3269 macsec_stats->in_pkts_ok +=
3270 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3271 macsec_stats->in_pkts_invalid +=
3272 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3273 macsec_stats->in_pkts_notvalid +=
3274 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3276 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3277 macsec_stats->in_pkts_notusingsa +=
3278 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3282 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3285 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3287 struct ixgbe_hw *hw =
3288 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3289 struct ixgbe_hw_stats *hw_stats =
3290 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3291 struct ixgbe_macsec_stats *macsec_stats =
3292 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3293 dev->data->dev_private);
3294 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3297 total_missed_rx = 0;
3302 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3303 &total_qbrc, &total_qprc, &total_qprdc);
3308 /* Fill out the rte_eth_stats statistics structure */
3309 stats->ipackets = total_qprc;
3310 stats->ibytes = total_qbrc;
3311 stats->opackets = hw_stats->gptc;
3312 stats->obytes = hw_stats->gotc;
3314 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3315 stats->q_ipackets[i] = hw_stats->qprc[i];
3316 stats->q_opackets[i] = hw_stats->qptc[i];
3317 stats->q_ibytes[i] = hw_stats->qbrc[i];
3318 stats->q_obytes[i] = hw_stats->qbtc[i];
3319 stats->q_errors[i] = hw_stats->qprdc[i];
3323 stats->imissed = total_missed_rx;
3324 stats->ierrors = hw_stats->crcerrs +
3341 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3343 struct ixgbe_hw_stats *stats =
3344 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3346 /* HW registers are cleared on read */
3347 ixgbe_dev_stats_get(dev, NULL);
3349 /* Reset software totals */
3350 memset(stats, 0, sizeof(*stats));
3355 /* This function calculates the number of xstats based on the current config */
3357 ixgbe_xstats_calc_num(void) {
3358 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3359 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3360 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3363 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3364 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3366 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3367 unsigned stat, i, count;
3369 if (xstats_names != NULL) {
3372 /* Note: limit >= cnt_stats checked upstream
3373 * in rte_eth_xstats_names()
3376 /* Extended stats from ixgbe_hw_stats */
3377 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3378 strlcpy(xstats_names[count].name,
3379 rte_ixgbe_stats_strings[i].name,
3380 sizeof(xstats_names[count].name));
3385 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3386 strlcpy(xstats_names[count].name,
3387 rte_ixgbe_macsec_strings[i].name,
3388 sizeof(xstats_names[count].name));
3392 /* RX Priority Stats */
3393 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3394 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3395 snprintf(xstats_names[count].name,
3396 sizeof(xstats_names[count].name),
3397 "rx_priority%u_%s", i,
3398 rte_ixgbe_rxq_strings[stat].name);
3403 /* TX Priority Stats */
3404 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3405 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3406 snprintf(xstats_names[count].name,
3407 sizeof(xstats_names[count].name),
3408 "tx_priority%u_%s", i,
3409 rte_ixgbe_txq_strings[stat].name);
3417 static int ixgbe_dev_xstats_get_names_by_id(
3418 struct rte_eth_dev *dev,
3419 struct rte_eth_xstat_name *xstats_names,
3420 const uint64_t *ids,
3424 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3425 unsigned int stat, i, count;
3427 if (xstats_names != NULL) {
3430 /* Note: limit >= cnt_stats checked upstream
3431 * in rte_eth_xstats_names()
3434 /* Extended stats from ixgbe_hw_stats */
3435 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3436 strlcpy(xstats_names[count].name,
3437 rte_ixgbe_stats_strings[i].name,
3438 sizeof(xstats_names[count].name));
3443 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3444 strlcpy(xstats_names[count].name,
3445 rte_ixgbe_macsec_strings[i].name,
3446 sizeof(xstats_names[count].name));
3450 /* RX Priority Stats */
3451 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3452 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3453 snprintf(xstats_names[count].name,
3454 sizeof(xstats_names[count].name),
3455 "rx_priority%u_%s", i,
3456 rte_ixgbe_rxq_strings[stat].name);
3461 /* TX Priority Stats */
3462 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3463 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3464 snprintf(xstats_names[count].name,
3465 sizeof(xstats_names[count].name),
3466 "tx_priority%u_%s", i,
3467 rte_ixgbe_txq_strings[stat].name);
3476 uint16_t size = ixgbe_xstats_calc_num();
3477 struct rte_eth_xstat_name xstats_names_copy[size];
3479 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3482 for (i = 0; i < limit; i++) {
3483 if (ids[i] >= size) {
3484 PMD_INIT_LOG(ERR, "id value isn't valid");
3487 strcpy(xstats_names[i].name,
3488 xstats_names_copy[ids[i]].name);
3493 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3494 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3498 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3501 if (xstats_names != NULL)
3502 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3503 strlcpy(xstats_names[i].name,
3504 rte_ixgbevf_stats_strings[i].name,
3505 sizeof(xstats_names[i].name));
3506 return IXGBEVF_NB_XSTATS;
3510 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3513 struct ixgbe_hw *hw =
3514 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3515 struct ixgbe_hw_stats *hw_stats =
3516 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3517 struct ixgbe_macsec_stats *macsec_stats =
3518 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3519 dev->data->dev_private);
3520 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3521 unsigned i, stat, count = 0;
3523 count = ixgbe_xstats_calc_num();
3528 total_missed_rx = 0;
3533 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3534 &total_qbrc, &total_qprc, &total_qprdc);
3536 /* If this is a reset xstats is NULL, and we have cleared the
3537 * registers by reading them.
3542 /* Extended stats from ixgbe_hw_stats */
3544 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3545 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3546 rte_ixgbe_stats_strings[i].offset);
3547 xstats[count].id = count;
3552 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3553 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3554 rte_ixgbe_macsec_strings[i].offset);
3555 xstats[count].id = count;
3559 /* RX Priority Stats */
3560 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3561 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3562 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3563 rte_ixgbe_rxq_strings[stat].offset +
3564 (sizeof(uint64_t) * i));
3565 xstats[count].id = count;
3570 /* TX Priority Stats */
3571 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3572 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3573 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3574 rte_ixgbe_txq_strings[stat].offset +
3575 (sizeof(uint64_t) * i));
3576 xstats[count].id = count;
3584 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3585 uint64_t *values, unsigned int n)
3588 struct ixgbe_hw *hw =
3589 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3590 struct ixgbe_hw_stats *hw_stats =
3591 IXGBE_DEV_PRIVATE_TO_STATS(
3592 dev->data->dev_private);
3593 struct ixgbe_macsec_stats *macsec_stats =
3594 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3595 dev->data->dev_private);
3596 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3597 unsigned int i, stat, count = 0;
3599 count = ixgbe_xstats_calc_num();
3601 if (!ids && n < count)
3604 total_missed_rx = 0;
3609 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3610 &total_missed_rx, &total_qbrc, &total_qprc,
3613 /* If this is a reset xstats is NULL, and we have cleared the
3614 * registers by reading them.
3616 if (!ids && !values)
3619 /* Extended stats from ixgbe_hw_stats */
3621 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3622 values[count] = *(uint64_t *)(((char *)hw_stats) +
3623 rte_ixgbe_stats_strings[i].offset);
3628 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3629 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3630 rte_ixgbe_macsec_strings[i].offset);
3634 /* RX Priority Stats */
3635 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3636 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3638 *(uint64_t *)(((char *)hw_stats) +
3639 rte_ixgbe_rxq_strings[stat].offset +
3640 (sizeof(uint64_t) * i));
3645 /* TX Priority Stats */
3646 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3647 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3649 *(uint64_t *)(((char *)hw_stats) +
3650 rte_ixgbe_txq_strings[stat].offset +
3651 (sizeof(uint64_t) * i));
3659 uint16_t size = ixgbe_xstats_calc_num();
3660 uint64_t values_copy[size];
3662 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3664 for (i = 0; i < n; i++) {
3665 if (ids[i] >= size) {
3666 PMD_INIT_LOG(ERR, "id value isn't valid");
3669 values[i] = values_copy[ids[i]];
3675 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3677 struct ixgbe_hw_stats *stats =
3678 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3679 struct ixgbe_macsec_stats *macsec_stats =
3680 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3681 dev->data->dev_private);
3683 unsigned count = ixgbe_xstats_calc_num();
3685 /* HW registers are cleared on read */
3686 ixgbe_dev_xstats_get(dev, NULL, count);
3688 /* Reset software totals */
3689 memset(stats, 0, sizeof(*stats));
3690 memset(macsec_stats, 0, sizeof(*macsec_stats));
3696 ixgbevf_update_stats(struct rte_eth_dev *dev)
3698 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3699 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3700 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3702 /* Good Rx packet, include VF loopback */
3703 UPDATE_VF_STAT(IXGBE_VFGPRC,
3704 hw_stats->last_vfgprc, hw_stats->vfgprc);
3706 /* Good Rx octets, include VF loopback */
3707 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3708 hw_stats->last_vfgorc, hw_stats->vfgorc);
3710 /* Good Tx packet, include VF loopback */
3711 UPDATE_VF_STAT(IXGBE_VFGPTC,
3712 hw_stats->last_vfgptc, hw_stats->vfgptc);
3714 /* Good Tx octets, include VF loopback */
3715 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3716 hw_stats->last_vfgotc, hw_stats->vfgotc);
3718 /* Rx Multicst Packet */
3719 UPDATE_VF_STAT(IXGBE_VFMPRC,
3720 hw_stats->last_vfmprc, hw_stats->vfmprc);
3724 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3727 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3728 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3731 if (n < IXGBEVF_NB_XSTATS)
3732 return IXGBEVF_NB_XSTATS;
3734 ixgbevf_update_stats(dev);
3739 /* Extended stats */
3740 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3742 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3743 rte_ixgbevf_stats_strings[i].offset);
3746 return IXGBEVF_NB_XSTATS;
3750 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3752 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3753 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3755 ixgbevf_update_stats(dev);
3760 stats->ipackets = hw_stats->vfgprc;
3761 stats->ibytes = hw_stats->vfgorc;
3762 stats->opackets = hw_stats->vfgptc;
3763 stats->obytes = hw_stats->vfgotc;
3768 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3770 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3771 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3773 /* Sync HW register to the last stats */
3774 ixgbevf_dev_stats_get(dev, NULL);
3776 /* reset HW current stats*/
3777 hw_stats->vfgprc = 0;
3778 hw_stats->vfgorc = 0;
3779 hw_stats->vfgptc = 0;
3780 hw_stats->vfgotc = 0;
3786 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3788 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3789 u16 eeprom_verh, eeprom_verl;
3793 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3794 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3796 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3797 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3799 ret += 1; /* add the size of '\0' */
3800 if (fw_size < (u32)ret)
3807 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3809 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3810 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3811 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3813 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3814 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3815 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3817 * When DCB/VT is off, maximum number of queues changes,
3818 * except for 82598EB, which remains constant.
3820 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3821 hw->mac.type != ixgbe_mac_82598EB)
3822 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3824 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3825 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3826 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3827 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3828 dev_info->max_vfs = pci_dev->max_vfs;
3829 if (hw->mac.type == ixgbe_mac_82598EB)
3830 dev_info->max_vmdq_pools = ETH_16_POOLS;
3832 dev_info->max_vmdq_pools = ETH_64_POOLS;
3833 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3834 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3835 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3836 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3837 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3838 dev_info->rx_queue_offload_capa);
3839 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3840 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3842 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3844 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3845 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3846 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3848 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3853 dev_info->default_txconf = (struct rte_eth_txconf) {
3855 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3856 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3857 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3859 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3860 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3864 dev_info->rx_desc_lim = rx_desc_lim;
3865 dev_info->tx_desc_lim = tx_desc_lim;
3867 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3868 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3869 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3871 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3872 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3873 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3874 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3875 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3877 if (hw->mac.type == ixgbe_mac_X540 ||
3878 hw->mac.type == ixgbe_mac_X540_vf ||
3879 hw->mac.type == ixgbe_mac_X550 ||
3880 hw->mac.type == ixgbe_mac_X550_vf) {
3881 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3883 if (hw->mac.type == ixgbe_mac_X550) {
3884 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3885 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3888 /* Driver-preferred Rx/Tx parameters */
3889 dev_info->default_rxportconf.burst_size = 32;
3890 dev_info->default_txportconf.burst_size = 32;
3891 dev_info->default_rxportconf.nb_queues = 1;
3892 dev_info->default_txportconf.nb_queues = 1;
3893 dev_info->default_rxportconf.ring_size = 256;
3894 dev_info->default_txportconf.ring_size = 256;
3899 static const uint32_t *
3900 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3902 static const uint32_t ptypes[] = {
3903 /* For non-vec functions,
3904 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3905 * for vec functions,
3906 * refers to _recv_raw_pkts_vec().
3910 RTE_PTYPE_L3_IPV4_EXT,
3912 RTE_PTYPE_L3_IPV6_EXT,
3916 RTE_PTYPE_TUNNEL_IP,
3917 RTE_PTYPE_INNER_L3_IPV6,
3918 RTE_PTYPE_INNER_L3_IPV6_EXT,
3919 RTE_PTYPE_INNER_L4_TCP,
3920 RTE_PTYPE_INNER_L4_UDP,
3924 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3925 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3926 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3927 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3930 #if defined(RTE_ARCH_X86) || defined(RTE_MACHINE_CPUFLAG_NEON)
3931 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3932 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3939 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3940 struct rte_eth_dev_info *dev_info)
3942 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3943 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3945 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3946 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3947 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3948 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3949 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3950 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3951 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3952 dev_info->max_vfs = pci_dev->max_vfs;
3953 if (hw->mac.type == ixgbe_mac_82598EB)
3954 dev_info->max_vmdq_pools = ETH_16_POOLS;
3956 dev_info->max_vmdq_pools = ETH_64_POOLS;
3957 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3958 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3959 dev_info->rx_queue_offload_capa);
3960 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3961 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3962 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3963 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3964 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3966 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3968 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3969 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3970 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3972 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3977 dev_info->default_txconf = (struct rte_eth_txconf) {
3979 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3980 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3981 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3983 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3984 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3988 dev_info->rx_desc_lim = rx_desc_lim;
3989 dev_info->tx_desc_lim = tx_desc_lim;
3995 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3996 int *link_up, int wait_to_complete)
3998 struct ixgbe_adapter *adapter = container_of(hw,
3999 struct ixgbe_adapter, hw);
4000 struct ixgbe_mbx_info *mbx = &hw->mbx;
4001 struct ixgbe_mac_info *mac = &hw->mac;
4002 uint32_t links_reg, in_msg;
4005 /* If we were hit with a reset drop the link */
4006 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4007 mac->get_link_status = true;
4009 if (!mac->get_link_status)
4012 /* if link status is down no point in checking to see if pf is up */
4013 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4014 if (!(links_reg & IXGBE_LINKS_UP))
4017 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4018 * before the link status is correct
4020 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4023 for (i = 0; i < 5; i++) {
4025 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4027 if (!(links_reg & IXGBE_LINKS_UP))
4032 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4033 case IXGBE_LINKS_SPEED_10G_82599:
4034 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4035 if (hw->mac.type >= ixgbe_mac_X550) {
4036 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4037 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4040 case IXGBE_LINKS_SPEED_1G_82599:
4041 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4043 case IXGBE_LINKS_SPEED_100_82599:
4044 *speed = IXGBE_LINK_SPEED_100_FULL;
4045 if (hw->mac.type == ixgbe_mac_X550) {
4046 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4047 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4050 case IXGBE_LINKS_SPEED_10_X550EM_A:
4051 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4052 /* Since Reserved in older MAC's */
4053 if (hw->mac.type >= ixgbe_mac_X550)
4054 *speed = IXGBE_LINK_SPEED_10_FULL;
4057 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4060 if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4061 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4062 mac->get_link_status = true;
4064 mac->get_link_status = false;
4069 /* if the read failed it could just be a mailbox collision, best wait
4070 * until we are called again and don't report an error
4072 if (mbx->ops.read(hw, &in_msg, 1, 0))
4075 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4076 /* msg is not CTS and is NACK we must have lost CTS status */
4077 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4078 mac->get_link_status = false;
4082 /* the pf is talking, if we timed out in the past we reinit */
4083 if (!mbx->timeout) {
4088 /* if we passed all the tests above then the link is up and we no
4089 * longer need to check for link
4091 mac->get_link_status = false;
4094 *link_up = !mac->get_link_status;
4099 ixgbe_dev_setup_link_alarm_handler(void *param)
4101 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4102 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4103 struct ixgbe_interrupt *intr =
4104 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4106 bool autoneg = false;
4108 speed = hw->phy.autoneg_advertised;
4110 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4112 ixgbe_setup_link(hw, speed, true);
4114 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4117 /* return 0 means link status changed, -1 means not changed */
4119 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4120 int wait_to_complete, int vf)
4122 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4123 struct rte_eth_link link;
4124 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4125 struct ixgbe_interrupt *intr =
4126 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4132 memset(&link, 0, sizeof(link));
4133 link.link_status = ETH_LINK_DOWN;
4134 link.link_speed = ETH_SPEED_NUM_NONE;
4135 link.link_duplex = ETH_LINK_HALF_DUPLEX;
4136 link.link_autoneg = ETH_LINK_AUTONEG;
4138 hw->mac.get_link_status = true;
4140 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4141 return rte_eth_linkstatus_set(dev, &link);
4143 /* check if it needs to wait to complete, if lsc interrupt is enabled */
4144 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4148 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4150 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4153 link.link_speed = ETH_SPEED_NUM_100M;
4154 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4155 return rte_eth_linkstatus_set(dev, &link);
4158 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4159 if ((esdp_reg & IXGBE_ESDP_SDP3))
4163 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4164 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4165 rte_eal_alarm_set(10,
4166 ixgbe_dev_setup_link_alarm_handler, dev);
4168 return rte_eth_linkstatus_set(dev, &link);
4171 link.link_status = ETH_LINK_UP;
4172 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4174 switch (link_speed) {
4176 case IXGBE_LINK_SPEED_UNKNOWN:
4177 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4178 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4179 link.link_speed = ETH_SPEED_NUM_10M;
4181 link.link_speed = ETH_SPEED_NUM_100M;
4184 case IXGBE_LINK_SPEED_100_FULL:
4185 link.link_speed = ETH_SPEED_NUM_100M;
4188 case IXGBE_LINK_SPEED_1GB_FULL:
4189 link.link_speed = ETH_SPEED_NUM_1G;
4192 case IXGBE_LINK_SPEED_2_5GB_FULL:
4193 link.link_speed = ETH_SPEED_NUM_2_5G;
4196 case IXGBE_LINK_SPEED_5GB_FULL:
4197 link.link_speed = ETH_SPEED_NUM_5G;
4200 case IXGBE_LINK_SPEED_10GB_FULL:
4201 link.link_speed = ETH_SPEED_NUM_10G;
4205 return rte_eth_linkstatus_set(dev, &link);
4209 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4211 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4215 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4217 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4221 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4223 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4226 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4227 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4228 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4234 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4236 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4239 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4240 fctrl &= (~IXGBE_FCTRL_UPE);
4241 if (dev->data->all_multicast == 1)
4242 fctrl |= IXGBE_FCTRL_MPE;
4244 fctrl &= (~IXGBE_FCTRL_MPE);
4245 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4251 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4253 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4256 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4257 fctrl |= IXGBE_FCTRL_MPE;
4258 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4264 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4266 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4269 if (dev->data->promiscuous == 1)
4270 return 0; /* must remain in all_multicast mode */
4272 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4273 fctrl &= (~IXGBE_FCTRL_MPE);
4274 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4280 * It clears the interrupt causes and enables the interrupt.
4281 * It will be called once only during nic initialized.
4284 * Pointer to struct rte_eth_dev.
4286 * Enable or Disable.
4289 * - On success, zero.
4290 * - On failure, a negative value.
4293 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4295 struct ixgbe_interrupt *intr =
4296 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4298 ixgbe_dev_link_status_print(dev);
4300 intr->mask |= IXGBE_EICR_LSC;
4302 intr->mask &= ~IXGBE_EICR_LSC;
4308 * It clears the interrupt causes and enables the interrupt.
4309 * It will be called once only during nic initialized.
4312 * Pointer to struct rte_eth_dev.
4315 * - On success, zero.
4316 * - On failure, a negative value.
4319 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4321 struct ixgbe_interrupt *intr =
4322 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4324 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4330 * It clears the interrupt causes and enables the interrupt.
4331 * It will be called once only during nic initialized.
4334 * Pointer to struct rte_eth_dev.
4337 * - On success, zero.
4338 * - On failure, a negative value.
4341 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4343 struct ixgbe_interrupt *intr =
4344 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4346 intr->mask |= IXGBE_EICR_LINKSEC;
4352 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4355 * Pointer to struct rte_eth_dev.
4358 * - On success, zero.
4359 * - On failure, a negative value.
4362 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4365 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4366 struct ixgbe_interrupt *intr =
4367 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4369 /* clear all cause mask */
4370 ixgbe_disable_intr(hw);
4372 /* read-on-clear nic registers here */
4373 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4374 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4378 /* set flag for async link update */
4379 if (eicr & IXGBE_EICR_LSC)
4380 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4382 if (eicr & IXGBE_EICR_MAILBOX)
4383 intr->flags |= IXGBE_FLAG_MAILBOX;
4385 if (eicr & IXGBE_EICR_LINKSEC)
4386 intr->flags |= IXGBE_FLAG_MACSEC;
4388 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4389 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4390 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4391 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4397 * It gets and then prints the link status.
4400 * Pointer to struct rte_eth_dev.
4403 * - On success, zero.
4404 * - On failure, a negative value.
4407 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4409 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4410 struct rte_eth_link link;
4412 rte_eth_linkstatus_get(dev, &link);
4414 if (link.link_status) {
4415 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4416 (int)(dev->data->port_id),
4417 (unsigned)link.link_speed,
4418 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4419 "full-duplex" : "half-duplex");
4421 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4422 (int)(dev->data->port_id));
4424 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4425 pci_dev->addr.domain,
4427 pci_dev->addr.devid,
4428 pci_dev->addr.function);
4432 * It executes link_update after knowing an interrupt occurred.
4435 * Pointer to struct rte_eth_dev.
4438 * - On success, zero.
4439 * - On failure, a negative value.
4442 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4444 struct ixgbe_interrupt *intr =
4445 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4447 struct ixgbe_hw *hw =
4448 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4450 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4452 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4453 ixgbe_pf_mbx_process(dev);
4454 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4457 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4458 ixgbe_handle_lasi(hw);
4459 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4462 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4463 struct rte_eth_link link;
4465 /* get the link status before link update, for predicting later */
4466 rte_eth_linkstatus_get(dev, &link);
4468 ixgbe_dev_link_update(dev, 0);
4471 if (!link.link_status)
4472 /* handle it 1 sec later, wait it being stable */
4473 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4474 /* likely to down */
4476 /* handle it 4 sec later, wait it being stable */
4477 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4479 ixgbe_dev_link_status_print(dev);
4480 if (rte_eal_alarm_set(timeout * 1000,
4481 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4482 PMD_DRV_LOG(ERR, "Error setting alarm");
4484 /* remember original mask */
4485 intr->mask_original = intr->mask;
4486 /* only disable lsc interrupt */
4487 intr->mask &= ~IXGBE_EIMS_LSC;
4491 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4492 ixgbe_enable_intr(dev);
4498 * Interrupt handler which shall be registered for alarm callback for delayed
4499 * handling specific interrupt to wait for the stable nic state. As the
4500 * NIC interrupt state is not stable for ixgbe after link is just down,
4501 * it needs to wait 4 seconds to get the stable status.
4504 * Pointer to interrupt handle.
4506 * The address of parameter (struct rte_eth_dev *) regsitered before.
4512 ixgbe_dev_interrupt_delayed_handler(void *param)
4514 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4515 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4516 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4517 struct ixgbe_interrupt *intr =
4518 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4519 struct ixgbe_hw *hw =
4520 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4523 ixgbe_disable_intr(hw);
4525 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4526 if (eicr & IXGBE_EICR_MAILBOX)
4527 ixgbe_pf_mbx_process(dev);
4529 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4530 ixgbe_handle_lasi(hw);
4531 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4534 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4535 ixgbe_dev_link_update(dev, 0);
4536 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4537 ixgbe_dev_link_status_print(dev);
4538 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4542 if (intr->flags & IXGBE_FLAG_MACSEC) {
4543 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4545 intr->flags &= ~IXGBE_FLAG_MACSEC;
4548 /* restore original mask */
4549 intr->mask = intr->mask_original;
4550 intr->mask_original = 0;
4552 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4553 ixgbe_enable_intr(dev);
4554 rte_intr_ack(intr_handle);
4558 * Interrupt handler triggered by NIC for handling
4559 * specific interrupt.
4562 * Pointer to interrupt handle.
4564 * The address of parameter (struct rte_eth_dev *) regsitered before.
4570 ixgbe_dev_interrupt_handler(void *param)
4572 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4574 ixgbe_dev_interrupt_get_status(dev);
4575 ixgbe_dev_interrupt_action(dev);
4579 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4581 struct ixgbe_hw *hw;
4583 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4584 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4588 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4590 struct ixgbe_hw *hw;
4592 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4593 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4597 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4599 struct ixgbe_hw *hw;
4605 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4607 fc_conf->pause_time = hw->fc.pause_time;
4608 fc_conf->high_water = hw->fc.high_water[0];
4609 fc_conf->low_water = hw->fc.low_water[0];
4610 fc_conf->send_xon = hw->fc.send_xon;
4611 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4614 * Return rx_pause status according to actual setting of
4617 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4618 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4624 * Return tx_pause status according to actual setting of
4627 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4628 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4633 if (rx_pause && tx_pause)
4634 fc_conf->mode = RTE_FC_FULL;
4636 fc_conf->mode = RTE_FC_RX_PAUSE;
4638 fc_conf->mode = RTE_FC_TX_PAUSE;
4640 fc_conf->mode = RTE_FC_NONE;
4646 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4648 struct ixgbe_hw *hw;
4650 uint32_t rx_buf_size;
4651 uint32_t max_high_water;
4653 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4660 PMD_INIT_FUNC_TRACE();
4662 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4663 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4664 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4667 * At least reserve one Ethernet frame for watermark
4668 * high_water/low_water in kilo bytes for ixgbe
4670 max_high_water = (rx_buf_size -
4671 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4672 if ((fc_conf->high_water > max_high_water) ||
4673 (fc_conf->high_water < fc_conf->low_water)) {
4674 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4675 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4679 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4680 hw->fc.pause_time = fc_conf->pause_time;
4681 hw->fc.high_water[0] = fc_conf->high_water;
4682 hw->fc.low_water[0] = fc_conf->low_water;
4683 hw->fc.send_xon = fc_conf->send_xon;
4684 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4686 err = ixgbe_fc_enable(hw);
4688 /* Not negotiated is not an error case */
4689 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4691 /* check if we want to forward MAC frames - driver doesn't have native
4692 * capability to do that, so we'll write the registers ourselves */
4694 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4696 /* set or clear MFLCN.PMCF bit depending on configuration */
4697 if (fc_conf->mac_ctrl_frame_fwd != 0)
4698 mflcn |= IXGBE_MFLCN_PMCF;
4700 mflcn &= ~IXGBE_MFLCN_PMCF;
4702 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4703 IXGBE_WRITE_FLUSH(hw);
4708 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4713 * ixgbe_pfc_enable_generic - Enable flow control
4714 * @hw: pointer to hardware structure
4715 * @tc_num: traffic class number
4716 * Enable flow control according to the current settings.
4719 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4722 uint32_t mflcn_reg, fccfg_reg;
4724 uint32_t fcrtl, fcrth;
4728 /* Validate the water mark configuration */
4729 if (!hw->fc.pause_time) {
4730 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4734 /* Low water mark of zero causes XOFF floods */
4735 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4736 /* High/Low water can not be 0 */
4737 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4738 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4739 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4743 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4744 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4745 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4749 /* Negotiate the fc mode to use */
4750 ixgbe_fc_autoneg(hw);
4752 /* Disable any previous flow control settings */
4753 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4754 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4756 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4757 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4759 switch (hw->fc.current_mode) {
4762 * If the count of enabled RX Priority Flow control >1,
4763 * and the TX pause can not be disabled
4766 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4767 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4768 if (reg & IXGBE_FCRTH_FCEN)
4772 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4774 case ixgbe_fc_rx_pause:
4776 * Rx Flow control is enabled and Tx Flow control is
4777 * disabled by software override. Since there really
4778 * isn't a way to advertise that we are capable of RX
4779 * Pause ONLY, we will advertise that we support both
4780 * symmetric and asymmetric Rx PAUSE. Later, we will
4781 * disable the adapter's ability to send PAUSE frames.
4783 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4785 * If the count of enabled RX Priority Flow control >1,
4786 * and the TX pause can not be disabled
4789 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4790 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4791 if (reg & IXGBE_FCRTH_FCEN)
4795 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4797 case ixgbe_fc_tx_pause:
4799 * Tx Flow control is enabled, and Rx Flow control is
4800 * disabled by software override.
4802 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4805 /* Flow control (both Rx and Tx) is enabled by SW override. */
4806 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4807 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4810 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4811 ret_val = IXGBE_ERR_CONFIG;
4815 /* Set 802.3x based flow control settings. */
4816 mflcn_reg |= IXGBE_MFLCN_DPF;
4817 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4818 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4820 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4821 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4822 hw->fc.high_water[tc_num]) {
4823 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4824 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4825 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4827 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4829 * In order to prevent Tx hangs when the internal Tx
4830 * switch is enabled we must set the high water mark
4831 * to the maximum FCRTH value. This allows the Tx
4832 * switch to function even under heavy Rx workloads.
4834 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4836 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4838 /* Configure pause time (2 TCs per register) */
4839 reg = hw->fc.pause_time * 0x00010001;
4840 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4841 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4843 /* Configure flow control refresh threshold value */
4844 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4851 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4853 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4854 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4856 if (hw->mac.type != ixgbe_mac_82598EB) {
4857 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4863 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4866 uint32_t rx_buf_size;
4867 uint32_t max_high_water;
4869 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4870 struct ixgbe_hw *hw =
4871 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4872 struct ixgbe_dcb_config *dcb_config =
4873 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4875 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4882 PMD_INIT_FUNC_TRACE();
4884 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4885 tc_num = map[pfc_conf->priority];
4886 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4887 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4889 * At least reserve one Ethernet frame for watermark
4890 * high_water/low_water in kilo bytes for ixgbe
4892 max_high_water = (rx_buf_size -
4893 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4894 if ((pfc_conf->fc.high_water > max_high_water) ||
4895 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4896 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4897 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4901 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4902 hw->fc.pause_time = pfc_conf->fc.pause_time;
4903 hw->fc.send_xon = pfc_conf->fc.send_xon;
4904 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4905 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4907 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4909 /* Not negotiated is not an error case */
4910 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4913 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4918 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4919 struct rte_eth_rss_reta_entry64 *reta_conf,
4922 uint16_t i, sp_reta_size;
4925 uint16_t idx, shift;
4926 struct ixgbe_adapter *adapter = dev->data->dev_private;
4927 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4930 PMD_INIT_FUNC_TRACE();
4932 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4933 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4938 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4939 if (reta_size != sp_reta_size) {
4940 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4941 "(%d) doesn't match the number hardware can supported "
4942 "(%d)", reta_size, sp_reta_size);
4946 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4947 idx = i / RTE_RETA_GROUP_SIZE;
4948 shift = i % RTE_RETA_GROUP_SIZE;
4949 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4953 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4954 if (mask == IXGBE_4_BIT_MASK)
4957 r = IXGBE_READ_REG(hw, reta_reg);
4958 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4959 if (mask & (0x1 << j))
4960 reta |= reta_conf[idx].reta[shift + j] <<
4963 reta |= r & (IXGBE_8_BIT_MASK <<
4966 IXGBE_WRITE_REG(hw, reta_reg, reta);
4968 adapter->rss_reta_updated = 1;
4974 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4975 struct rte_eth_rss_reta_entry64 *reta_conf,
4978 uint16_t i, sp_reta_size;
4981 uint16_t idx, shift;
4982 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4985 PMD_INIT_FUNC_TRACE();
4986 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4987 if (reta_size != sp_reta_size) {
4988 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4989 "(%d) doesn't match the number hardware can supported "
4990 "(%d)", reta_size, sp_reta_size);
4994 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4995 idx = i / RTE_RETA_GROUP_SIZE;
4996 shift = i % RTE_RETA_GROUP_SIZE;
4997 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5002 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5003 reta = IXGBE_READ_REG(hw, reta_reg);
5004 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5005 if (mask & (0x1 << j))
5006 reta_conf[idx].reta[shift + j] =
5007 ((reta >> (CHAR_BIT * j)) &
5016 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5017 uint32_t index, uint32_t pool)
5019 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5020 uint32_t enable_addr = 1;
5022 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5027 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5029 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5031 ixgbe_clear_rar(hw, index);
5035 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5037 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5039 ixgbe_remove_rar(dev, 0);
5040 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5046 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5048 if (strcmp(dev->device->driver->name, drv->driver.name))
5055 is_ixgbe_supported(struct rte_eth_dev *dev)
5057 return is_device_supported(dev, &rte_ixgbe_pmd);
5061 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5065 struct ixgbe_hw *hw;
5066 struct rte_eth_dev_info dev_info;
5067 uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5068 struct rte_eth_dev_data *dev_data = dev->data;
5071 ret = ixgbe_dev_info_get(dev, &dev_info);
5075 /* check that mtu is within the allowed range */
5076 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5079 /* If device is started, refuse mtu that requires the support of
5080 * scattered packets when this feature has not been enabled before.
5082 if (dev_data->dev_started && !dev_data->scattered_rx &&
5083 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5084 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5085 PMD_INIT_LOG(ERR, "Stop port first.");
5089 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5090 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5092 /* switch to jumbo mode if needed */
5093 if (frame_size > RTE_ETHER_MAX_LEN) {
5094 dev->data->dev_conf.rxmode.offloads |=
5095 DEV_RX_OFFLOAD_JUMBO_FRAME;
5096 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5098 dev->data->dev_conf.rxmode.offloads &=
5099 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5100 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5102 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5104 /* update max frame size */
5105 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5107 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5108 maxfrs &= 0x0000FFFF;
5109 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5110 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5116 * Virtual Function operations
5119 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5121 struct ixgbe_interrupt *intr =
5122 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5123 struct ixgbe_hw *hw =
5124 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5126 PMD_INIT_FUNC_TRACE();
5128 /* Clear interrupt mask to stop from interrupts being generated */
5129 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5131 IXGBE_WRITE_FLUSH(hw);
5133 /* Clear mask value. */
5138 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5140 struct ixgbe_interrupt *intr =
5141 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5142 struct ixgbe_hw *hw =
5143 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5145 PMD_INIT_FUNC_TRACE();
5147 /* VF enable interrupt autoclean */
5148 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5149 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5150 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5152 IXGBE_WRITE_FLUSH(hw);
5154 /* Save IXGBE_VTEIMS value to mask. */
5155 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5159 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5161 struct rte_eth_conf *conf = &dev->data->dev_conf;
5162 struct ixgbe_adapter *adapter = dev->data->dev_private;
5164 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5165 dev->data->port_id);
5167 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5168 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5171 * VF has no ability to enable/disable HW CRC
5172 * Keep the persistent behavior the same as Host PF
5174 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5175 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5176 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5177 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5180 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5181 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5182 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5187 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5188 * allocation or vector Rx preconditions we will reset it.
5190 adapter->rx_bulk_alloc_allowed = true;
5191 adapter->rx_vec_allowed = true;
5197 ixgbevf_dev_start(struct rte_eth_dev *dev)
5199 struct ixgbe_hw *hw =
5200 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5201 uint32_t intr_vector = 0;
5202 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5203 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5207 PMD_INIT_FUNC_TRACE();
5209 /* Stop the link setup handler before resetting the HW. */
5210 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5212 err = hw->mac.ops.reset_hw(hw);
5214 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5217 hw->mac.get_link_status = true;
5219 /* negotiate mailbox API version to use with the PF. */
5220 ixgbevf_negotiate_api(hw);
5222 ixgbevf_dev_tx_init(dev);
5224 /* This can fail when allocating mbufs for descriptor rings */
5225 err = ixgbevf_dev_rx_init(dev);
5227 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5228 ixgbe_dev_clear_queues(dev);
5233 ixgbevf_set_vfta_all(dev, 1);
5236 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5237 ETH_VLAN_EXTEND_MASK;
5238 err = ixgbevf_vlan_offload_config(dev, mask);
5240 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5241 ixgbe_dev_clear_queues(dev);
5245 ixgbevf_dev_rxtx_start(dev);
5247 /* check and configure queue intr-vector mapping */
5248 if (rte_intr_cap_multiple(intr_handle) &&
5249 dev->data->dev_conf.intr_conf.rxq) {
5250 /* According to datasheet, only vector 0/1/2 can be used,
5251 * now only one vector is used for Rx queue
5254 if (rte_intr_efd_enable(intr_handle, intr_vector))
5258 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5259 intr_handle->intr_vec =
5260 rte_zmalloc("intr_vec",
5261 dev->data->nb_rx_queues * sizeof(int), 0);
5262 if (intr_handle->intr_vec == NULL) {
5263 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5264 " intr_vec", dev->data->nb_rx_queues);
5268 ixgbevf_configure_msix(dev);
5270 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5271 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5272 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5273 * is not cleared, it will fail when following rte_intr_enable( ) tries
5274 * to map Rx queue interrupt to other VFIO vectors.
5275 * So clear uio/vfio intr/evevnfd first to avoid failure.
5277 rte_intr_disable(intr_handle);
5279 rte_intr_enable(intr_handle);
5281 /* Re-enable interrupt for VF */
5282 ixgbevf_intr_enable(dev);
5285 * Update link status right before return, because it may
5286 * start link configuration process in a separate thread.
5288 ixgbevf_dev_link_update(dev, 0);
5290 hw->adapter_stopped = false;
5296 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5298 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5299 struct ixgbe_adapter *adapter = dev->data->dev_private;
5300 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5301 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5303 if (hw->adapter_stopped)
5306 PMD_INIT_FUNC_TRACE();
5308 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5310 ixgbevf_intr_disable(dev);
5312 hw->adapter_stopped = 1;
5313 ixgbe_stop_adapter(hw);
5316 * Clear what we set, but we still keep shadow_vfta to
5317 * restore after device starts
5319 ixgbevf_set_vfta_all(dev, 0);
5321 /* Clear stored conf */
5322 dev->data->scattered_rx = 0;
5324 ixgbe_dev_clear_queues(dev);
5326 /* Clean datapath event and queue/vec mapping */
5327 rte_intr_efd_disable(intr_handle);
5328 if (intr_handle->intr_vec != NULL) {
5329 rte_free(intr_handle->intr_vec);
5330 intr_handle->intr_vec = NULL;
5333 adapter->rss_reta_updated = 0;
5337 ixgbevf_dev_close(struct rte_eth_dev *dev)
5339 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5340 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5341 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5343 PMD_INIT_FUNC_TRACE();
5347 ixgbevf_dev_stop(dev);
5349 ixgbe_dev_free_queues(dev);
5352 * Remove the VF MAC address ro ensure
5353 * that the VF traffic goes to the PF
5354 * after stop, close and detach of the VF
5356 ixgbevf_remove_mac_addr(dev, 0);
5358 dev->dev_ops = NULL;
5359 dev->rx_pkt_burst = NULL;
5360 dev->tx_pkt_burst = NULL;
5362 rte_intr_disable(intr_handle);
5363 rte_intr_callback_unregister(intr_handle,
5364 ixgbevf_dev_interrupt_handler, dev);
5371 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5375 ret = eth_ixgbevf_dev_uninit(dev);
5379 ret = eth_ixgbevf_dev_init(dev);
5384 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5386 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5387 struct ixgbe_vfta *shadow_vfta =
5388 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5389 int i = 0, j = 0, vfta = 0, mask = 1;
5391 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5392 vfta = shadow_vfta->vfta[i];
5395 for (j = 0; j < 32; j++) {
5397 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5407 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5409 struct ixgbe_hw *hw =
5410 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5411 struct ixgbe_vfta *shadow_vfta =
5412 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5413 uint32_t vid_idx = 0;
5414 uint32_t vid_bit = 0;
5417 PMD_INIT_FUNC_TRACE();
5419 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5420 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5422 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5425 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5426 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5428 /* Save what we set and retore it after device reset */
5430 shadow_vfta->vfta[vid_idx] |= vid_bit;
5432 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5438 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5440 struct ixgbe_hw *hw =
5441 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5444 PMD_INIT_FUNC_TRACE();
5446 if (queue >= hw->mac.max_rx_queues)
5449 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5451 ctrl |= IXGBE_RXDCTL_VME;
5453 ctrl &= ~IXGBE_RXDCTL_VME;
5454 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5456 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5460 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5462 struct ixgbe_rx_queue *rxq;
5466 /* VF function only support hw strip feature, others are not support */
5467 if (mask & ETH_VLAN_STRIP_MASK) {
5468 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5469 rxq = dev->data->rx_queues[i];
5470 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5471 ixgbevf_vlan_strip_queue_set(dev, i, on);
5479 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5481 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5483 ixgbevf_vlan_offload_config(dev, mask);
5489 ixgbe_vt_check(struct ixgbe_hw *hw)
5493 /* if Virtualization Technology is enabled */
5494 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5495 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5496 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5504 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5506 uint32_t vector = 0;
5508 switch (hw->mac.mc_filter_type) {
5509 case 0: /* use bits [47:36] of the address */
5510 vector = ((uc_addr->addr_bytes[4] >> 4) |
5511 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5513 case 1: /* use bits [46:35] of the address */
5514 vector = ((uc_addr->addr_bytes[4] >> 3) |
5515 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5517 case 2: /* use bits [45:34] of the address */
5518 vector = ((uc_addr->addr_bytes[4] >> 2) |
5519 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5521 case 3: /* use bits [43:32] of the address */
5522 vector = ((uc_addr->addr_bytes[4]) |
5523 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5525 default: /* Invalid mc_filter_type */
5529 /* vector can only be 12-bits or boundary will be exceeded */
5535 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5536 struct rte_ether_addr *mac_addr, uint8_t on)
5543 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5544 const uint32_t ixgbe_uta_bit_shift = 5;
5545 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5546 const uint32_t bit1 = 0x1;
5548 struct ixgbe_hw *hw =
5549 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5550 struct ixgbe_uta_info *uta_info =
5551 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5553 /* The UTA table only exists on 82599 hardware and newer */
5554 if (hw->mac.type < ixgbe_mac_82599EB)
5557 vector = ixgbe_uta_vector(hw, mac_addr);
5558 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5559 uta_shift = vector & ixgbe_uta_bit_mask;
5561 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5565 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5567 uta_info->uta_in_use++;
5568 reg_val |= (bit1 << uta_shift);
5569 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5571 uta_info->uta_in_use--;
5572 reg_val &= ~(bit1 << uta_shift);
5573 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5576 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5578 if (uta_info->uta_in_use > 0)
5579 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5580 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5582 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5588 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5591 struct ixgbe_hw *hw =
5592 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5593 struct ixgbe_uta_info *uta_info =
5594 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5596 /* The UTA table only exists on 82599 hardware and newer */
5597 if (hw->mac.type < ixgbe_mac_82599EB)
5601 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5602 uta_info->uta_shadow[i] = ~0;
5603 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5606 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5607 uta_info->uta_shadow[i] = 0;
5608 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5616 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5618 uint32_t new_val = orig_val;
5620 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5621 new_val |= IXGBE_VMOLR_AUPE;
5622 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5623 new_val |= IXGBE_VMOLR_ROMPE;
5624 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5625 new_val |= IXGBE_VMOLR_ROPE;
5626 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5627 new_val |= IXGBE_VMOLR_BAM;
5628 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5629 new_val |= IXGBE_VMOLR_MPE;
5634 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5635 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5636 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5637 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5638 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5639 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5640 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5643 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5644 struct rte_eth_mirror_conf *mirror_conf,
5645 uint8_t rule_id, uint8_t on)
5647 uint32_t mr_ctl, vlvf;
5648 uint32_t mp_lsb = 0;
5649 uint32_t mv_msb = 0;
5650 uint32_t mv_lsb = 0;
5651 uint32_t mp_msb = 0;
5654 uint64_t vlan_mask = 0;
5656 const uint8_t pool_mask_offset = 32;
5657 const uint8_t vlan_mask_offset = 32;
5658 const uint8_t dst_pool_offset = 8;
5659 const uint8_t rule_mr_offset = 4;
5660 const uint8_t mirror_rule_mask = 0x0F;
5662 struct ixgbe_mirror_info *mr_info =
5663 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5664 struct ixgbe_hw *hw =
5665 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5666 uint8_t mirror_type = 0;
5668 if (ixgbe_vt_check(hw) < 0)
5671 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5674 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5675 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5676 mirror_conf->rule_type);
5680 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5681 mirror_type |= IXGBE_MRCTL_VLME;
5682 /* Check if vlan id is valid and find conresponding VLAN ID
5685 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5686 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5687 /* search vlan id related pool vlan filter
5690 reg_index = ixgbe_find_vlvf_slot(
5692 mirror_conf->vlan.vlan_id[i],
5696 vlvf = IXGBE_READ_REG(hw,
5697 IXGBE_VLVF(reg_index));
5698 if ((vlvf & IXGBE_VLVF_VIEN) &&
5699 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5700 mirror_conf->vlan.vlan_id[i]))
5701 vlan_mask |= (1ULL << reg_index);
5708 mv_lsb = vlan_mask & 0xFFFFFFFF;
5709 mv_msb = vlan_mask >> vlan_mask_offset;
5711 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5712 mirror_conf->vlan.vlan_mask;
5713 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5714 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5715 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5716 mirror_conf->vlan.vlan_id[i];
5721 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5722 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5723 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5728 * if enable pool mirror, write related pool mask register,if disable
5729 * pool mirror, clear PFMRVM register
5731 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5732 mirror_type |= IXGBE_MRCTL_VPME;
5734 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5735 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5736 mr_info->mr_conf[rule_id].pool_mask =
5737 mirror_conf->pool_mask;
5742 mr_info->mr_conf[rule_id].pool_mask = 0;
5745 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5746 mirror_type |= IXGBE_MRCTL_UPME;
5747 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5748 mirror_type |= IXGBE_MRCTL_DPME;
5750 /* read mirror control register and recalculate it */
5751 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5754 mr_ctl |= mirror_type;
5755 mr_ctl &= mirror_rule_mask;
5756 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5758 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5761 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5762 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5764 /* write mirrror control register */
5765 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5767 /* write pool mirrror control register */
5768 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5769 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5770 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5773 /* write VLAN mirrror control register */
5774 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5775 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5776 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5784 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5787 uint32_t lsb_val = 0;
5788 uint32_t msb_val = 0;
5789 const uint8_t rule_mr_offset = 4;
5791 struct ixgbe_hw *hw =
5792 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5793 struct ixgbe_mirror_info *mr_info =
5794 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5796 if (ixgbe_vt_check(hw) < 0)
5799 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5802 memset(&mr_info->mr_conf[rule_id], 0,
5803 sizeof(struct rte_eth_mirror_conf));
5805 /* clear PFVMCTL register */
5806 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5808 /* clear pool mask register */
5809 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5810 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5812 /* clear vlan mask register */
5813 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5814 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5820 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5822 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5823 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5824 struct ixgbe_interrupt *intr =
5825 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5826 struct ixgbe_hw *hw =
5827 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5828 uint32_t vec = IXGBE_MISC_VEC_ID;
5830 if (rte_intr_allow_others(intr_handle))
5831 vec = IXGBE_RX_VEC_START;
5832 intr->mask |= (1 << vec);
5833 RTE_SET_USED(queue_id);
5834 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5836 rte_intr_ack(intr_handle);
5842 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5844 struct ixgbe_interrupt *intr =
5845 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5846 struct ixgbe_hw *hw =
5847 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5848 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5849 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5850 uint32_t vec = IXGBE_MISC_VEC_ID;
5852 if (rte_intr_allow_others(intr_handle))
5853 vec = IXGBE_RX_VEC_START;
5854 intr->mask &= ~(1 << vec);
5855 RTE_SET_USED(queue_id);
5856 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5862 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5864 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5865 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5867 struct ixgbe_hw *hw =
5868 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5869 struct ixgbe_interrupt *intr =
5870 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5872 if (queue_id < 16) {
5873 ixgbe_disable_intr(hw);
5874 intr->mask |= (1 << queue_id);
5875 ixgbe_enable_intr(dev);
5876 } else if (queue_id < 32) {
5877 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5878 mask &= (1 << queue_id);
5879 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5880 } else if (queue_id < 64) {
5881 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5882 mask &= (1 << (queue_id - 32));
5883 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5885 rte_intr_ack(intr_handle);
5891 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5894 struct ixgbe_hw *hw =
5895 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5896 struct ixgbe_interrupt *intr =
5897 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5899 if (queue_id < 16) {
5900 ixgbe_disable_intr(hw);
5901 intr->mask &= ~(1 << queue_id);
5902 ixgbe_enable_intr(dev);
5903 } else if (queue_id < 32) {
5904 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5905 mask &= ~(1 << queue_id);
5906 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5907 } else if (queue_id < 64) {
5908 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5909 mask &= ~(1 << (queue_id - 32));
5910 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5917 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5918 uint8_t queue, uint8_t msix_vector)
5922 if (direction == -1) {
5924 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5925 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5928 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5930 /* rx or tx cause */
5931 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5932 idx = ((16 * (queue & 1)) + (8 * direction));
5933 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5934 tmp &= ~(0xFF << idx);
5935 tmp |= (msix_vector << idx);
5936 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5941 * set the IVAR registers, mapping interrupt causes to vectors
5943 * pointer to ixgbe_hw struct
5945 * 0 for Rx, 1 for Tx, -1 for other causes
5947 * queue to map the corresponding interrupt to
5949 * the vector to map to the corresponding queue
5952 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5953 uint8_t queue, uint8_t msix_vector)
5957 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5958 if (hw->mac.type == ixgbe_mac_82598EB) {
5959 if (direction == -1)
5961 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5962 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5963 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5964 tmp |= (msix_vector << (8 * (queue & 0x3)));
5965 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5966 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5967 (hw->mac.type == ixgbe_mac_X540) ||
5968 (hw->mac.type == ixgbe_mac_X550) ||
5969 (hw->mac.type == ixgbe_mac_X550EM_x)) {
5970 if (direction == -1) {
5972 idx = ((queue & 1) * 8);
5973 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5974 tmp &= ~(0xFF << idx);
5975 tmp |= (msix_vector << idx);
5976 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5978 /* rx or tx causes */
5979 idx = ((16 * (queue & 1)) + (8 * direction));
5980 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5981 tmp &= ~(0xFF << idx);
5982 tmp |= (msix_vector << idx);
5983 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5989 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5991 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5992 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5993 struct ixgbe_hw *hw =
5994 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5996 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5997 uint32_t base = IXGBE_MISC_VEC_ID;
5999 /* Configure VF other cause ivar */
6000 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6002 /* won't configure msix register if no mapping is done
6003 * between intr vector and event fd.
6005 if (!rte_intr_dp_is_en(intr_handle))
6008 if (rte_intr_allow_others(intr_handle)) {
6009 base = IXGBE_RX_VEC_START;
6010 vector_idx = IXGBE_RX_VEC_START;
6013 /* Configure all RX queues of VF */
6014 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6015 /* Force all queue use vector 0,
6016 * as IXGBE_VF_MAXMSIVECOTR = 1
6018 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6019 intr_handle->intr_vec[q_idx] = vector_idx;
6020 if (vector_idx < base + intr_handle->nb_efd - 1)
6024 /* As RX queue setting above show, all queues use the vector 0.
6025 * Set only the ITR value of IXGBE_MISC_VEC_ID.
6027 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6028 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6029 | IXGBE_EITR_CNT_WDIS);
6033 * Sets up the hardware to properly generate MSI-X interrupts
6035 * board private structure
6038 ixgbe_configure_msix(struct rte_eth_dev *dev)
6040 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6041 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6042 struct ixgbe_hw *hw =
6043 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6044 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6045 uint32_t vec = IXGBE_MISC_VEC_ID;
6049 /* won't configure msix register if no mapping is done
6050 * between intr vector and event fd
6051 * but if misx has been enabled already, need to configure
6052 * auto clean, auto mask and throttling.
6054 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6055 if (!rte_intr_dp_is_en(intr_handle) &&
6056 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6059 if (rte_intr_allow_others(intr_handle))
6060 vec = base = IXGBE_RX_VEC_START;
6062 /* setup GPIE for MSI-x mode */
6063 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6064 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6065 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6066 /* auto clearing and auto setting corresponding bits in EIMS
6067 * when MSI-X interrupt is triggered
6069 if (hw->mac.type == ixgbe_mac_82598EB) {
6070 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6072 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6073 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6075 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6077 /* Populate the IVAR table and set the ITR values to the
6078 * corresponding register.
6080 if (rte_intr_dp_is_en(intr_handle)) {
6081 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6083 /* by default, 1:1 mapping */
6084 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6085 intr_handle->intr_vec[queue_id] = vec;
6086 if (vec < base + intr_handle->nb_efd - 1)
6090 switch (hw->mac.type) {
6091 case ixgbe_mac_82598EB:
6092 ixgbe_set_ivar_map(hw, -1,
6093 IXGBE_IVAR_OTHER_CAUSES_INDEX,
6096 case ixgbe_mac_82599EB:
6097 case ixgbe_mac_X540:
6098 case ixgbe_mac_X550:
6099 case ixgbe_mac_X550EM_x:
6100 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6106 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6107 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6108 | IXGBE_EITR_CNT_WDIS);
6110 /* set up to autoclear timer, and the vectors */
6111 mask = IXGBE_EIMS_ENABLE_MASK;
6112 mask &= ~(IXGBE_EIMS_OTHER |
6113 IXGBE_EIMS_MAILBOX |
6116 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6120 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6121 uint16_t queue_idx, uint16_t tx_rate)
6123 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6124 struct rte_eth_rxmode *rxmode;
6125 uint32_t rf_dec, rf_int;
6127 uint16_t link_speed = dev->data->dev_link.link_speed;
6129 if (queue_idx >= hw->mac.max_tx_queues)
6133 /* Calculate the rate factor values to set */
6134 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6135 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6136 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6138 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6139 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6140 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6141 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6146 rxmode = &dev->data->dev_conf.rxmode;
6148 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6149 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6152 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6153 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6154 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6155 IXGBE_MMW_SIZE_JUMBO_FRAME);
6157 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6158 IXGBE_MMW_SIZE_DEFAULT);
6160 /* Set RTTBCNRC of queue X */
6161 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6162 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6163 IXGBE_WRITE_FLUSH(hw);
6169 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6170 __attribute__((unused)) uint32_t index,
6171 __attribute__((unused)) uint32_t pool)
6173 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6177 * On a 82599 VF, adding again the same MAC addr is not an idempotent
6178 * operation. Trap this case to avoid exhausting the [very limited]
6179 * set of PF resources used to store VF MAC addresses.
6181 if (memcmp(hw->mac.perm_addr, mac_addr,
6182 sizeof(struct rte_ether_addr)) == 0)
6184 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6186 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6187 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6188 mac_addr->addr_bytes[0],
6189 mac_addr->addr_bytes[1],
6190 mac_addr->addr_bytes[2],
6191 mac_addr->addr_bytes[3],
6192 mac_addr->addr_bytes[4],
6193 mac_addr->addr_bytes[5],
6199 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6201 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6202 struct rte_ether_addr *perm_addr =
6203 (struct rte_ether_addr *)hw->mac.perm_addr;
6204 struct rte_ether_addr *mac_addr;
6209 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6210 * not support the deletion of a given MAC address.
6211 * Instead, it imposes to delete all MAC addresses, then to add again
6212 * all MAC addresses with the exception of the one to be deleted.
6214 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6217 * Add again all MAC addresses, with the exception of the deleted one
6218 * and of the permanent MAC address.
6220 for (i = 0, mac_addr = dev->data->mac_addrs;
6221 i < hw->mac.num_rar_entries; i++, mac_addr++) {
6222 /* Skip the deleted MAC address */
6225 /* Skip NULL MAC addresses */
6226 if (rte_is_zero_ether_addr(mac_addr))
6228 /* Skip the permanent MAC address */
6229 if (memcmp(perm_addr, mac_addr,
6230 sizeof(struct rte_ether_addr)) == 0)
6232 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6235 "Adding again MAC address "
6236 "%02x:%02x:%02x:%02x:%02x:%02x failed "
6238 mac_addr->addr_bytes[0],
6239 mac_addr->addr_bytes[1],
6240 mac_addr->addr_bytes[2],
6241 mac_addr->addr_bytes[3],
6242 mac_addr->addr_bytes[4],
6243 mac_addr->addr_bytes[5],
6249 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6250 struct rte_ether_addr *addr)
6252 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6254 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6260 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6261 struct rte_eth_syn_filter *filter,
6264 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6265 struct ixgbe_filter_info *filter_info =
6266 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6270 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6273 syn_info = filter_info->syn_info;
6276 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6278 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6279 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6281 if (filter->hig_pri)
6282 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6284 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6286 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6287 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6289 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6292 filter_info->syn_info = synqf;
6293 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6294 IXGBE_WRITE_FLUSH(hw);
6299 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6300 struct rte_eth_syn_filter *filter)
6302 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6303 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6305 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6306 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6307 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6314 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6315 enum rte_filter_op filter_op,
6318 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6321 MAC_TYPE_FILTER_SUP(hw->mac.type);
6323 if (filter_op == RTE_ETH_FILTER_NOP)
6327 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6332 switch (filter_op) {
6333 case RTE_ETH_FILTER_ADD:
6334 ret = ixgbe_syn_filter_set(dev,
6335 (struct rte_eth_syn_filter *)arg,
6338 case RTE_ETH_FILTER_DELETE:
6339 ret = ixgbe_syn_filter_set(dev,
6340 (struct rte_eth_syn_filter *)arg,
6343 case RTE_ETH_FILTER_GET:
6344 ret = ixgbe_syn_filter_get(dev,
6345 (struct rte_eth_syn_filter *)arg);
6348 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6357 static inline enum ixgbe_5tuple_protocol
6358 convert_protocol_type(uint8_t protocol_value)
6360 if (protocol_value == IPPROTO_TCP)
6361 return IXGBE_FILTER_PROTOCOL_TCP;
6362 else if (protocol_value == IPPROTO_UDP)
6363 return IXGBE_FILTER_PROTOCOL_UDP;
6364 else if (protocol_value == IPPROTO_SCTP)
6365 return IXGBE_FILTER_PROTOCOL_SCTP;
6367 return IXGBE_FILTER_PROTOCOL_NONE;
6370 /* inject a 5-tuple filter to HW */
6372 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6373 struct ixgbe_5tuple_filter *filter)
6375 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6377 uint32_t ftqf, sdpqf;
6378 uint32_t l34timir = 0;
6379 uint8_t mask = 0xff;
6383 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6384 IXGBE_SDPQF_DSTPORT_SHIFT);
6385 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6387 ftqf = (uint32_t)(filter->filter_info.proto &
6388 IXGBE_FTQF_PROTOCOL_MASK);
6389 ftqf |= (uint32_t)((filter->filter_info.priority &
6390 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6391 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6392 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6393 if (filter->filter_info.dst_ip_mask == 0)
6394 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6395 if (filter->filter_info.src_port_mask == 0)
6396 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6397 if (filter->filter_info.dst_port_mask == 0)
6398 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6399 if (filter->filter_info.proto_mask == 0)
6400 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6401 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6402 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6403 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6405 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6406 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6407 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6408 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6410 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6411 l34timir |= (uint32_t)(filter->queue <<
6412 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6413 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6417 * add a 5tuple filter
6420 * dev: Pointer to struct rte_eth_dev.
6421 * index: the index the filter allocates.
6422 * filter: ponter to the filter that will be added.
6423 * rx_queue: the queue id the filter assigned to.
6426 * - On success, zero.
6427 * - On failure, a negative value.
6430 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6431 struct ixgbe_5tuple_filter *filter)
6433 struct ixgbe_filter_info *filter_info =
6434 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6438 * look for an unused 5tuple filter index,
6439 * and insert the filter to list.
6441 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6442 idx = i / (sizeof(uint32_t) * NBBY);
6443 shift = i % (sizeof(uint32_t) * NBBY);
6444 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6445 filter_info->fivetuple_mask[idx] |= 1 << shift;
6447 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6453 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6454 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6458 ixgbe_inject_5tuple_filter(dev, filter);
6464 * remove a 5tuple filter
6467 * dev: Pointer to struct rte_eth_dev.
6468 * filter: the pointer of the filter will be removed.
6471 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6472 struct ixgbe_5tuple_filter *filter)
6474 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6475 struct ixgbe_filter_info *filter_info =
6476 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6477 uint16_t index = filter->index;
6479 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6480 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6481 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6484 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6485 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6486 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6487 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6488 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6492 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6494 struct ixgbe_hw *hw;
6495 uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6496 struct rte_eth_dev_data *dev_data = dev->data;
6498 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6500 if (mtu < RTE_ETHER_MIN_MTU ||
6501 max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6504 /* If device is started, refuse mtu that requires the support of
6505 * scattered packets when this feature has not been enabled before.
6507 if (dev_data->dev_started && !dev_data->scattered_rx &&
6508 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6509 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6510 PMD_INIT_LOG(ERR, "Stop port first.");
6515 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6516 * request of the version 2.0 of the mailbox API.
6517 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6518 * of the mailbox API.
6519 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6520 * prior to 3.11.33 which contains the following change:
6521 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6523 ixgbevf_rlpml_set_vf(hw, max_frame);
6525 /* update max frame size */
6526 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6530 static inline struct ixgbe_5tuple_filter *
6531 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6532 struct ixgbe_5tuple_filter_info *key)
6534 struct ixgbe_5tuple_filter *it;
6536 TAILQ_FOREACH(it, filter_list, entries) {
6537 if (memcmp(key, &it->filter_info,
6538 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6545 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6547 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6548 struct ixgbe_5tuple_filter_info *filter_info)
6550 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6551 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6552 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6555 switch (filter->dst_ip_mask) {
6557 filter_info->dst_ip_mask = 0;
6558 filter_info->dst_ip = filter->dst_ip;
6561 filter_info->dst_ip_mask = 1;
6564 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6568 switch (filter->src_ip_mask) {
6570 filter_info->src_ip_mask = 0;
6571 filter_info->src_ip = filter->src_ip;
6574 filter_info->src_ip_mask = 1;
6577 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6581 switch (filter->dst_port_mask) {
6583 filter_info->dst_port_mask = 0;
6584 filter_info->dst_port = filter->dst_port;
6587 filter_info->dst_port_mask = 1;
6590 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6594 switch (filter->src_port_mask) {
6596 filter_info->src_port_mask = 0;
6597 filter_info->src_port = filter->src_port;
6600 filter_info->src_port_mask = 1;
6603 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6607 switch (filter->proto_mask) {
6609 filter_info->proto_mask = 0;
6610 filter_info->proto =
6611 convert_protocol_type(filter->proto);
6614 filter_info->proto_mask = 1;
6617 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6621 filter_info->priority = (uint8_t)filter->priority;
6626 * add or delete a ntuple filter
6629 * dev: Pointer to struct rte_eth_dev.
6630 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6631 * add: if true, add filter, if false, remove filter
6634 * - On success, zero.
6635 * - On failure, a negative value.
6638 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6639 struct rte_eth_ntuple_filter *ntuple_filter,
6642 struct ixgbe_filter_info *filter_info =
6643 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6644 struct ixgbe_5tuple_filter_info filter_5tuple;
6645 struct ixgbe_5tuple_filter *filter;
6648 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6649 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6653 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6654 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6658 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6660 if (filter != NULL && add) {
6661 PMD_DRV_LOG(ERR, "filter exists.");
6664 if (filter == NULL && !add) {
6665 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6670 filter = rte_zmalloc("ixgbe_5tuple_filter",
6671 sizeof(struct ixgbe_5tuple_filter), 0);
6674 rte_memcpy(&filter->filter_info,
6676 sizeof(struct ixgbe_5tuple_filter_info));
6677 filter->queue = ntuple_filter->queue;
6678 ret = ixgbe_add_5tuple_filter(dev, filter);
6684 ixgbe_remove_5tuple_filter(dev, filter);
6690 * get a ntuple filter
6693 * dev: Pointer to struct rte_eth_dev.
6694 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6697 * - On success, zero.
6698 * - On failure, a negative value.
6701 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6702 struct rte_eth_ntuple_filter *ntuple_filter)
6704 struct ixgbe_filter_info *filter_info =
6705 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6706 struct ixgbe_5tuple_filter_info filter_5tuple;
6707 struct ixgbe_5tuple_filter *filter;
6710 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6711 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6715 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6716 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6720 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6722 if (filter == NULL) {
6723 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6726 ntuple_filter->queue = filter->queue;
6731 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6732 * @dev: pointer to rte_eth_dev structure
6733 * @filter_op:operation will be taken.
6734 * @arg: a pointer to specific structure corresponding to the filter_op
6737 * - On success, zero.
6738 * - On failure, a negative value.
6741 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6742 enum rte_filter_op filter_op,
6745 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6748 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6750 if (filter_op == RTE_ETH_FILTER_NOP)
6754 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6759 switch (filter_op) {
6760 case RTE_ETH_FILTER_ADD:
6761 ret = ixgbe_add_del_ntuple_filter(dev,
6762 (struct rte_eth_ntuple_filter *)arg,
6765 case RTE_ETH_FILTER_DELETE:
6766 ret = ixgbe_add_del_ntuple_filter(dev,
6767 (struct rte_eth_ntuple_filter *)arg,
6770 case RTE_ETH_FILTER_GET:
6771 ret = ixgbe_get_ntuple_filter(dev,
6772 (struct rte_eth_ntuple_filter *)arg);
6775 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6783 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6784 struct rte_eth_ethertype_filter *filter,
6787 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6788 struct ixgbe_filter_info *filter_info =
6789 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6793 struct ixgbe_ethertype_filter ethertype_filter;
6795 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6798 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6799 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6800 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6801 " ethertype filter.", filter->ether_type);
6805 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6806 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6809 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6810 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6814 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6815 if (ret >= 0 && add) {
6816 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6817 filter->ether_type);
6820 if (ret < 0 && !add) {
6821 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6822 filter->ether_type);
6827 etqf = IXGBE_ETQF_FILTER_EN;
6828 etqf |= (uint32_t)filter->ether_type;
6829 etqs |= (uint32_t)((filter->queue <<
6830 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6831 IXGBE_ETQS_RX_QUEUE);
6832 etqs |= IXGBE_ETQS_QUEUE_EN;
6834 ethertype_filter.ethertype = filter->ether_type;
6835 ethertype_filter.etqf = etqf;
6836 ethertype_filter.etqs = etqs;
6837 ethertype_filter.conf = FALSE;
6838 ret = ixgbe_ethertype_filter_insert(filter_info,
6841 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6845 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6849 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6850 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6851 IXGBE_WRITE_FLUSH(hw);
6857 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6858 struct rte_eth_ethertype_filter *filter)
6860 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6861 struct ixgbe_filter_info *filter_info =
6862 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6863 uint32_t etqf, etqs;
6866 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6868 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6869 filter->ether_type);
6873 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6874 if (etqf & IXGBE_ETQF_FILTER_EN) {
6875 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6876 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6878 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6879 IXGBE_ETQS_RX_QUEUE_SHIFT;
6886 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6887 * @dev: pointer to rte_eth_dev structure
6888 * @filter_op:operation will be taken.
6889 * @arg: a pointer to specific structure corresponding to the filter_op
6892 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6893 enum rte_filter_op filter_op,
6896 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6899 MAC_TYPE_FILTER_SUP(hw->mac.type);
6901 if (filter_op == RTE_ETH_FILTER_NOP)
6905 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6910 switch (filter_op) {
6911 case RTE_ETH_FILTER_ADD:
6912 ret = ixgbe_add_del_ethertype_filter(dev,
6913 (struct rte_eth_ethertype_filter *)arg,
6916 case RTE_ETH_FILTER_DELETE:
6917 ret = ixgbe_add_del_ethertype_filter(dev,
6918 (struct rte_eth_ethertype_filter *)arg,
6921 case RTE_ETH_FILTER_GET:
6922 ret = ixgbe_get_ethertype_filter(dev,
6923 (struct rte_eth_ethertype_filter *)arg);
6926 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6934 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6935 enum rte_filter_type filter_type,
6936 enum rte_filter_op filter_op,
6941 switch (filter_type) {
6942 case RTE_ETH_FILTER_NTUPLE:
6943 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6945 case RTE_ETH_FILTER_ETHERTYPE:
6946 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6948 case RTE_ETH_FILTER_SYN:
6949 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6951 case RTE_ETH_FILTER_FDIR:
6952 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6954 case RTE_ETH_FILTER_L2_TUNNEL:
6955 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6957 case RTE_ETH_FILTER_GENERIC:
6958 if (filter_op != RTE_ETH_FILTER_GET)
6960 *(const void **)arg = &ixgbe_flow_ops;
6963 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6973 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6974 u8 **mc_addr_ptr, u32 *vmdq)
6979 mc_addr = *mc_addr_ptr;
6980 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6985 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6986 struct rte_ether_addr *mc_addr_set,
6987 uint32_t nb_mc_addr)
6989 struct ixgbe_hw *hw;
6992 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6993 mc_addr_list = (u8 *)mc_addr_set;
6994 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6995 ixgbe_dev_addr_list_itr, TRUE);
6999 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
7001 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7002 uint64_t systime_cycles;
7004 switch (hw->mac.type) {
7005 case ixgbe_mac_X550:
7006 case ixgbe_mac_X550EM_x:
7007 case ixgbe_mac_X550EM_a:
7008 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
7009 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7010 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7014 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7015 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7019 return systime_cycles;
7023 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7025 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7026 uint64_t rx_tstamp_cycles;
7028 switch (hw->mac.type) {
7029 case ixgbe_mac_X550:
7030 case ixgbe_mac_X550EM_x:
7031 case ixgbe_mac_X550EM_a:
7032 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7033 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7034 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7038 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7039 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7040 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7044 return rx_tstamp_cycles;
7048 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7050 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7051 uint64_t tx_tstamp_cycles;
7053 switch (hw->mac.type) {
7054 case ixgbe_mac_X550:
7055 case ixgbe_mac_X550EM_x:
7056 case ixgbe_mac_X550EM_a:
7057 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7058 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7059 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7063 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7064 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7065 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7069 return tx_tstamp_cycles;
7073 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7075 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7076 struct ixgbe_adapter *adapter = dev->data->dev_private;
7077 struct rte_eth_link link;
7078 uint32_t incval = 0;
7081 /* Get current link speed. */
7082 ixgbe_dev_link_update(dev, 1);
7083 rte_eth_linkstatus_get(dev, &link);
7085 switch (link.link_speed) {
7086 case ETH_SPEED_NUM_100M:
7087 incval = IXGBE_INCVAL_100;
7088 shift = IXGBE_INCVAL_SHIFT_100;
7090 case ETH_SPEED_NUM_1G:
7091 incval = IXGBE_INCVAL_1GB;
7092 shift = IXGBE_INCVAL_SHIFT_1GB;
7094 case ETH_SPEED_NUM_10G:
7096 incval = IXGBE_INCVAL_10GB;
7097 shift = IXGBE_INCVAL_SHIFT_10GB;
7101 switch (hw->mac.type) {
7102 case ixgbe_mac_X550:
7103 case ixgbe_mac_X550EM_x:
7104 case ixgbe_mac_X550EM_a:
7105 /* Independent of link speed. */
7107 /* Cycles read will be interpreted as ns. */
7110 case ixgbe_mac_X540:
7111 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7113 case ixgbe_mac_82599EB:
7114 incval >>= IXGBE_INCVAL_SHIFT_82599;
7115 shift -= IXGBE_INCVAL_SHIFT_82599;
7116 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7117 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7120 /* Not supported. */
7124 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7125 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7126 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7128 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7129 adapter->systime_tc.cc_shift = shift;
7130 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7132 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7133 adapter->rx_tstamp_tc.cc_shift = shift;
7134 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7136 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7137 adapter->tx_tstamp_tc.cc_shift = shift;
7138 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7142 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7144 struct ixgbe_adapter *adapter = dev->data->dev_private;
7146 adapter->systime_tc.nsec += delta;
7147 adapter->rx_tstamp_tc.nsec += delta;
7148 adapter->tx_tstamp_tc.nsec += delta;
7154 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7157 struct ixgbe_adapter *adapter = dev->data->dev_private;
7159 ns = rte_timespec_to_ns(ts);
7160 /* Set the timecounters to a new value. */
7161 adapter->systime_tc.nsec = ns;
7162 adapter->rx_tstamp_tc.nsec = ns;
7163 adapter->tx_tstamp_tc.nsec = ns;
7169 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7171 uint64_t ns, systime_cycles;
7172 struct ixgbe_adapter *adapter = dev->data->dev_private;
7174 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7175 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7176 *ts = rte_ns_to_timespec(ns);
7182 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7184 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7188 /* Stop the timesync system time. */
7189 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7190 /* Reset the timesync system time value. */
7191 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7192 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7194 /* Enable system time for platforms where it isn't on by default. */
7195 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7196 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7197 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7199 ixgbe_start_timecounters(dev);
7201 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7202 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7203 (RTE_ETHER_TYPE_1588 |
7204 IXGBE_ETQF_FILTER_EN |
7207 /* Enable timestamping of received PTP packets. */
7208 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7209 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7210 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7212 /* Enable timestamping of transmitted PTP packets. */
7213 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7214 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7215 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7217 IXGBE_WRITE_FLUSH(hw);
7223 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7225 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7228 /* Disable timestamping of transmitted PTP packets. */
7229 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7230 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7231 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7233 /* Disable timestamping of received PTP packets. */
7234 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7235 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7236 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7238 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7239 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7241 /* Stop incrementating the System Time registers. */
7242 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7248 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7249 struct timespec *timestamp,
7250 uint32_t flags __rte_unused)
7252 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7253 struct ixgbe_adapter *adapter = dev->data->dev_private;
7254 uint32_t tsync_rxctl;
7255 uint64_t rx_tstamp_cycles;
7258 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7259 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7262 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7263 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7264 *timestamp = rte_ns_to_timespec(ns);
7270 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7271 struct timespec *timestamp)
7273 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7274 struct ixgbe_adapter *adapter = dev->data->dev_private;
7275 uint32_t tsync_txctl;
7276 uint64_t tx_tstamp_cycles;
7279 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7280 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7283 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7284 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7285 *timestamp = rte_ns_to_timespec(ns);
7291 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7293 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7296 const struct reg_info *reg_group;
7297 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7298 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7300 while ((reg_group = reg_set[g_ind++]))
7301 count += ixgbe_regs_group_count(reg_group);
7307 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7311 const struct reg_info *reg_group;
7313 while ((reg_group = ixgbevf_regs[g_ind++]))
7314 count += ixgbe_regs_group_count(reg_group);
7320 ixgbe_get_regs(struct rte_eth_dev *dev,
7321 struct rte_dev_reg_info *regs)
7323 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7324 uint32_t *data = regs->data;
7327 const struct reg_info *reg_group;
7328 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7329 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7332 regs->length = ixgbe_get_reg_length(dev);
7333 regs->width = sizeof(uint32_t);
7337 /* Support only full register dump */
7338 if ((regs->length == 0) ||
7339 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7340 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7342 while ((reg_group = reg_set[g_ind++]))
7343 count += ixgbe_read_regs_group(dev, &data[count],
7352 ixgbevf_get_regs(struct rte_eth_dev *dev,
7353 struct rte_dev_reg_info *regs)
7355 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7356 uint32_t *data = regs->data;
7359 const struct reg_info *reg_group;
7362 regs->length = ixgbevf_get_reg_length(dev);
7363 regs->width = sizeof(uint32_t);
7367 /* Support only full register dump */
7368 if ((regs->length == 0) ||
7369 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7370 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7372 while ((reg_group = ixgbevf_regs[g_ind++]))
7373 count += ixgbe_read_regs_group(dev, &data[count],
7382 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7384 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7386 /* Return unit is byte count */
7387 return hw->eeprom.word_size * 2;
7391 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7392 struct rte_dev_eeprom_info *in_eeprom)
7394 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7395 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7396 uint16_t *data = in_eeprom->data;
7399 first = in_eeprom->offset >> 1;
7400 length = in_eeprom->length >> 1;
7401 if ((first > hw->eeprom.word_size) ||
7402 ((first + length) > hw->eeprom.word_size))
7405 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7407 return eeprom->ops.read_buffer(hw, first, length, data);
7411 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7412 struct rte_dev_eeprom_info *in_eeprom)
7414 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7415 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7416 uint16_t *data = in_eeprom->data;
7419 first = in_eeprom->offset >> 1;
7420 length = in_eeprom->length >> 1;
7421 if ((first > hw->eeprom.word_size) ||
7422 ((first + length) > hw->eeprom.word_size))
7425 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7427 return eeprom->ops.write_buffer(hw, first, length, data);
7431 ixgbe_get_module_info(struct rte_eth_dev *dev,
7432 struct rte_eth_dev_module_info *modinfo)
7434 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7436 uint8_t sff8472_rev, addr_mode;
7437 bool page_swap = false;
7439 /* Check whether we support SFF-8472 or not */
7440 status = hw->phy.ops.read_i2c_eeprom(hw,
7441 IXGBE_SFF_SFF_8472_COMP,
7446 /* addressing mode is not supported */
7447 status = hw->phy.ops.read_i2c_eeprom(hw,
7448 IXGBE_SFF_SFF_8472_SWAP,
7453 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7455 "Address change required to access page 0xA2, "
7456 "but not supported. Please report the module "
7457 "type to the driver maintainers.");
7461 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7462 /* We have a SFP, but it does not support SFF-8472 */
7463 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7464 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7466 /* We have a SFP which supports a revision of SFF-8472. */
7467 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7468 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7475 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7476 struct rte_dev_eeprom_info *info)
7478 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7479 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7480 uint8_t databyte = 0xFF;
7481 uint8_t *data = info->data;
7484 if (info->length == 0)
7487 for (i = info->offset; i < info->offset + info->length; i++) {
7488 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7489 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7491 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7496 data[i - info->offset] = databyte;
7503 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7505 case ixgbe_mac_X550:
7506 case ixgbe_mac_X550EM_x:
7507 case ixgbe_mac_X550EM_a:
7508 return ETH_RSS_RETA_SIZE_512;
7509 case ixgbe_mac_X550_vf:
7510 case ixgbe_mac_X550EM_x_vf:
7511 case ixgbe_mac_X550EM_a_vf:
7512 return ETH_RSS_RETA_SIZE_64;
7513 case ixgbe_mac_X540_vf:
7514 case ixgbe_mac_82599_vf:
7517 return ETH_RSS_RETA_SIZE_128;
7522 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7524 case ixgbe_mac_X550:
7525 case ixgbe_mac_X550EM_x:
7526 case ixgbe_mac_X550EM_a:
7527 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7528 return IXGBE_RETA(reta_idx >> 2);
7530 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7531 case ixgbe_mac_X550_vf:
7532 case ixgbe_mac_X550EM_x_vf:
7533 case ixgbe_mac_X550EM_a_vf:
7534 return IXGBE_VFRETA(reta_idx >> 2);
7536 return IXGBE_RETA(reta_idx >> 2);
7541 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7543 case ixgbe_mac_X550_vf:
7544 case ixgbe_mac_X550EM_x_vf:
7545 case ixgbe_mac_X550EM_a_vf:
7546 return IXGBE_VFMRQC;
7553 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7555 case ixgbe_mac_X550_vf:
7556 case ixgbe_mac_X550EM_x_vf:
7557 case ixgbe_mac_X550EM_a_vf:
7558 return IXGBE_VFRSSRK(i);
7560 return IXGBE_RSSRK(i);
7565 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7567 case ixgbe_mac_82599_vf:
7568 case ixgbe_mac_X540_vf:
7576 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7577 struct rte_eth_dcb_info *dcb_info)
7579 struct ixgbe_dcb_config *dcb_config =
7580 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7581 struct ixgbe_dcb_tc_config *tc;
7582 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7586 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7587 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7589 dcb_info->nb_tcs = 1;
7591 tc_queue = &dcb_info->tc_queue;
7592 nb_tcs = dcb_info->nb_tcs;
7594 if (dcb_config->vt_mode) { /* vt is enabled*/
7595 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7596 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7597 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7598 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7599 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7600 for (j = 0; j < nb_tcs; j++) {
7601 tc_queue->tc_rxq[0][j].base = j;
7602 tc_queue->tc_rxq[0][j].nb_queue = 1;
7603 tc_queue->tc_txq[0][j].base = j;
7604 tc_queue->tc_txq[0][j].nb_queue = 1;
7607 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7608 for (j = 0; j < nb_tcs; j++) {
7609 tc_queue->tc_rxq[i][j].base =
7611 tc_queue->tc_rxq[i][j].nb_queue = 1;
7612 tc_queue->tc_txq[i][j].base =
7614 tc_queue->tc_txq[i][j].nb_queue = 1;
7618 } else { /* vt is disabled*/
7619 struct rte_eth_dcb_rx_conf *rx_conf =
7620 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7621 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7622 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7623 if (dcb_info->nb_tcs == ETH_4_TCS) {
7624 for (i = 0; i < dcb_info->nb_tcs; i++) {
7625 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7626 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7628 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7629 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7630 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7631 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7632 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7633 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7634 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7635 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7636 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7637 for (i = 0; i < dcb_info->nb_tcs; i++) {
7638 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7639 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7641 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7642 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7643 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7644 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7645 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7646 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7647 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7648 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7649 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7650 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7651 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7652 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7653 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7654 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7655 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7656 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7659 for (i = 0; i < dcb_info->nb_tcs; i++) {
7660 tc = &dcb_config->tc_config[i];
7661 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7666 /* Update e-tag ether type */
7668 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7669 uint16_t ether_type)
7671 uint32_t etag_etype;
7673 if (hw->mac.type != ixgbe_mac_X550 &&
7674 hw->mac.type != ixgbe_mac_X550EM_x &&
7675 hw->mac.type != ixgbe_mac_X550EM_a) {
7679 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7680 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7681 etag_etype |= ether_type;
7682 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7683 IXGBE_WRITE_FLUSH(hw);
7688 /* Config l2 tunnel ether type */
7690 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7691 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7694 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7695 struct ixgbe_l2_tn_info *l2_tn_info =
7696 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7698 if (l2_tunnel == NULL)
7701 switch (l2_tunnel->l2_tunnel_type) {
7702 case RTE_L2_TUNNEL_TYPE_E_TAG:
7703 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7704 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7707 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7715 /* Enable e-tag tunnel */
7717 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7719 uint32_t etag_etype;
7721 if (hw->mac.type != ixgbe_mac_X550 &&
7722 hw->mac.type != ixgbe_mac_X550EM_x &&
7723 hw->mac.type != ixgbe_mac_X550EM_a) {
7727 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7728 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7729 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7730 IXGBE_WRITE_FLUSH(hw);
7735 /* Enable l2 tunnel */
7737 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7738 enum rte_eth_tunnel_type l2_tunnel_type)
7741 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7742 struct ixgbe_l2_tn_info *l2_tn_info =
7743 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7745 switch (l2_tunnel_type) {
7746 case RTE_L2_TUNNEL_TYPE_E_TAG:
7747 l2_tn_info->e_tag_en = TRUE;
7748 ret = ixgbe_e_tag_enable(hw);
7751 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7759 /* Disable e-tag tunnel */
7761 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7763 uint32_t etag_etype;
7765 if (hw->mac.type != ixgbe_mac_X550 &&
7766 hw->mac.type != ixgbe_mac_X550EM_x &&
7767 hw->mac.type != ixgbe_mac_X550EM_a) {
7771 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7772 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7773 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7774 IXGBE_WRITE_FLUSH(hw);
7779 /* Disable l2 tunnel */
7781 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7782 enum rte_eth_tunnel_type l2_tunnel_type)
7785 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7786 struct ixgbe_l2_tn_info *l2_tn_info =
7787 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7789 switch (l2_tunnel_type) {
7790 case RTE_L2_TUNNEL_TYPE_E_TAG:
7791 l2_tn_info->e_tag_en = FALSE;
7792 ret = ixgbe_e_tag_disable(hw);
7795 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7804 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7805 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7808 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7809 uint32_t i, rar_entries;
7810 uint32_t rar_low, rar_high;
7812 if (hw->mac.type != ixgbe_mac_X550 &&
7813 hw->mac.type != ixgbe_mac_X550EM_x &&
7814 hw->mac.type != ixgbe_mac_X550EM_a) {
7818 rar_entries = ixgbe_get_num_rx_addrs(hw);
7820 for (i = 1; i < rar_entries; i++) {
7821 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7822 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7823 if ((rar_high & IXGBE_RAH_AV) &&
7824 (rar_high & IXGBE_RAH_ADTYPE) &&
7825 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7826 l2_tunnel->tunnel_id)) {
7827 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7828 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7830 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7840 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7841 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7844 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7845 uint32_t i, rar_entries;
7846 uint32_t rar_low, rar_high;
7848 if (hw->mac.type != ixgbe_mac_X550 &&
7849 hw->mac.type != ixgbe_mac_X550EM_x &&
7850 hw->mac.type != ixgbe_mac_X550EM_a) {
7854 /* One entry for one tunnel. Try to remove potential existing entry. */
7855 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7857 rar_entries = ixgbe_get_num_rx_addrs(hw);
7859 for (i = 1; i < rar_entries; i++) {
7860 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7861 if (rar_high & IXGBE_RAH_AV) {
7864 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7865 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7866 rar_low = l2_tunnel->tunnel_id;
7868 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7869 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7875 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7876 " Please remove a rule before adding a new one.");
7880 static inline struct ixgbe_l2_tn_filter *
7881 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7882 struct ixgbe_l2_tn_key *key)
7886 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7890 return l2_tn_info->hash_map[ret];
7894 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7895 struct ixgbe_l2_tn_filter *l2_tn_filter)
7899 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7900 &l2_tn_filter->key);
7904 "Failed to insert L2 tunnel filter"
7905 " to hash table %d!",
7910 l2_tn_info->hash_map[ret] = l2_tn_filter;
7912 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7918 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7919 struct ixgbe_l2_tn_key *key)
7922 struct ixgbe_l2_tn_filter *l2_tn_filter;
7924 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7928 "No such L2 tunnel filter to delete %d!",
7933 l2_tn_filter = l2_tn_info->hash_map[ret];
7934 l2_tn_info->hash_map[ret] = NULL;
7936 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7937 rte_free(l2_tn_filter);
7942 /* Add l2 tunnel filter */
7944 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7945 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7949 struct ixgbe_l2_tn_info *l2_tn_info =
7950 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7951 struct ixgbe_l2_tn_key key;
7952 struct ixgbe_l2_tn_filter *node;
7955 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7956 key.tn_id = l2_tunnel->tunnel_id;
7958 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7962 "The L2 tunnel filter already exists!");
7966 node = rte_zmalloc("ixgbe_l2_tn",
7967 sizeof(struct ixgbe_l2_tn_filter),
7972 rte_memcpy(&node->key,
7974 sizeof(struct ixgbe_l2_tn_key));
7975 node->pool = l2_tunnel->pool;
7976 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7983 switch (l2_tunnel->l2_tunnel_type) {
7984 case RTE_L2_TUNNEL_TYPE_E_TAG:
7985 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7988 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7993 if ((!restore) && (ret < 0))
7994 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7999 /* Delete l2 tunnel filter */
8001 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
8002 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8005 struct ixgbe_l2_tn_info *l2_tn_info =
8006 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8007 struct ixgbe_l2_tn_key key;
8009 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8010 key.tn_id = l2_tunnel->tunnel_id;
8011 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8015 switch (l2_tunnel->l2_tunnel_type) {
8016 case RTE_L2_TUNNEL_TYPE_E_TAG:
8017 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8020 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8029 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8030 * @dev: pointer to rte_eth_dev structure
8031 * @filter_op:operation will be taken.
8032 * @arg: a pointer to specific structure corresponding to the filter_op
8035 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8036 enum rte_filter_op filter_op,
8041 if (filter_op == RTE_ETH_FILTER_NOP)
8045 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8050 switch (filter_op) {
8051 case RTE_ETH_FILTER_ADD:
8052 ret = ixgbe_dev_l2_tunnel_filter_add
8054 (struct rte_eth_l2_tunnel_conf *)arg,
8057 case RTE_ETH_FILTER_DELETE:
8058 ret = ixgbe_dev_l2_tunnel_filter_del
8060 (struct rte_eth_l2_tunnel_conf *)arg);
8063 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8071 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8075 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8077 if (hw->mac.type != ixgbe_mac_X550 &&
8078 hw->mac.type != ixgbe_mac_X550EM_x &&
8079 hw->mac.type != ixgbe_mac_X550EM_a) {
8083 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8084 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8086 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8087 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8092 /* Enable l2 tunnel forwarding */
8094 ixgbe_dev_l2_tunnel_forwarding_enable
8095 (struct rte_eth_dev *dev,
8096 enum rte_eth_tunnel_type l2_tunnel_type)
8098 struct ixgbe_l2_tn_info *l2_tn_info =
8099 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8102 switch (l2_tunnel_type) {
8103 case RTE_L2_TUNNEL_TYPE_E_TAG:
8104 l2_tn_info->e_tag_fwd_en = TRUE;
8105 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8108 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8116 /* Disable l2 tunnel forwarding */
8118 ixgbe_dev_l2_tunnel_forwarding_disable
8119 (struct rte_eth_dev *dev,
8120 enum rte_eth_tunnel_type l2_tunnel_type)
8122 struct ixgbe_l2_tn_info *l2_tn_info =
8123 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8126 switch (l2_tunnel_type) {
8127 case RTE_L2_TUNNEL_TYPE_E_TAG:
8128 l2_tn_info->e_tag_fwd_en = FALSE;
8129 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8132 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8141 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8142 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8145 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8147 uint32_t vmtir, vmvir;
8148 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8150 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8152 "VF id %u should be less than %u",
8158 if (hw->mac.type != ixgbe_mac_X550 &&
8159 hw->mac.type != ixgbe_mac_X550EM_x &&
8160 hw->mac.type != ixgbe_mac_X550EM_a) {
8165 vmtir = l2_tunnel->tunnel_id;
8169 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8171 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8172 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8174 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8175 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8180 /* Enable l2 tunnel tag insertion */
8182 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8183 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8187 switch (l2_tunnel->l2_tunnel_type) {
8188 case RTE_L2_TUNNEL_TYPE_E_TAG:
8189 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8192 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8200 /* Disable l2 tunnel tag insertion */
8202 ixgbe_dev_l2_tunnel_insertion_disable
8203 (struct rte_eth_dev *dev,
8204 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8208 switch (l2_tunnel->l2_tunnel_type) {
8209 case RTE_L2_TUNNEL_TYPE_E_TAG:
8210 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8213 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8222 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8227 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8229 if (hw->mac.type != ixgbe_mac_X550 &&
8230 hw->mac.type != ixgbe_mac_X550EM_x &&
8231 hw->mac.type != ixgbe_mac_X550EM_a) {
8235 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8237 qde |= IXGBE_QDE_STRIP_TAG;
8239 qde &= ~IXGBE_QDE_STRIP_TAG;
8240 qde &= ~IXGBE_QDE_READ;
8241 qde |= IXGBE_QDE_WRITE;
8242 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8247 /* Enable l2 tunnel tag stripping */
8249 ixgbe_dev_l2_tunnel_stripping_enable
8250 (struct rte_eth_dev *dev,
8251 enum rte_eth_tunnel_type l2_tunnel_type)
8255 switch (l2_tunnel_type) {
8256 case RTE_L2_TUNNEL_TYPE_E_TAG:
8257 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8260 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8268 /* Disable l2 tunnel tag stripping */
8270 ixgbe_dev_l2_tunnel_stripping_disable
8271 (struct rte_eth_dev *dev,
8272 enum rte_eth_tunnel_type l2_tunnel_type)
8276 switch (l2_tunnel_type) {
8277 case RTE_L2_TUNNEL_TYPE_E_TAG:
8278 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8281 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8289 /* Enable/disable l2 tunnel offload functions */
8291 ixgbe_dev_l2_tunnel_offload_set
8292 (struct rte_eth_dev *dev,
8293 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8299 if (l2_tunnel == NULL)
8303 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8305 ret = ixgbe_dev_l2_tunnel_enable(
8307 l2_tunnel->l2_tunnel_type);
8309 ret = ixgbe_dev_l2_tunnel_disable(
8311 l2_tunnel->l2_tunnel_type);
8314 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8316 ret = ixgbe_dev_l2_tunnel_insertion_enable(
8320 ret = ixgbe_dev_l2_tunnel_insertion_disable(
8325 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8327 ret = ixgbe_dev_l2_tunnel_stripping_enable(
8329 l2_tunnel->l2_tunnel_type);
8331 ret = ixgbe_dev_l2_tunnel_stripping_disable(
8333 l2_tunnel->l2_tunnel_type);
8336 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8338 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8340 l2_tunnel->l2_tunnel_type);
8342 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8344 l2_tunnel->l2_tunnel_type);
8351 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8354 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8355 IXGBE_WRITE_FLUSH(hw);
8360 /* There's only one register for VxLAN UDP port.
8361 * So, we cannot add several ports. Will update it.
8364 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8368 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8372 return ixgbe_update_vxlan_port(hw, port);
8375 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8376 * UDP port, it must have a value.
8377 * So, will reset it to the original value 0.
8380 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8385 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8387 if (cur_port != port) {
8388 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8392 return ixgbe_update_vxlan_port(hw, 0);
8395 /* Add UDP tunneling port */
8397 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8398 struct rte_eth_udp_tunnel *udp_tunnel)
8401 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8403 if (hw->mac.type != ixgbe_mac_X550 &&
8404 hw->mac.type != ixgbe_mac_X550EM_x &&
8405 hw->mac.type != ixgbe_mac_X550EM_a) {
8409 if (udp_tunnel == NULL)
8412 switch (udp_tunnel->prot_type) {
8413 case RTE_TUNNEL_TYPE_VXLAN:
8414 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8417 case RTE_TUNNEL_TYPE_GENEVE:
8418 case RTE_TUNNEL_TYPE_TEREDO:
8419 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8424 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8432 /* Remove UDP tunneling port */
8434 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8435 struct rte_eth_udp_tunnel *udp_tunnel)
8438 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8440 if (hw->mac.type != ixgbe_mac_X550 &&
8441 hw->mac.type != ixgbe_mac_X550EM_x &&
8442 hw->mac.type != ixgbe_mac_X550EM_a) {
8446 if (udp_tunnel == NULL)
8449 switch (udp_tunnel->prot_type) {
8450 case RTE_TUNNEL_TYPE_VXLAN:
8451 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8453 case RTE_TUNNEL_TYPE_GENEVE:
8454 case RTE_TUNNEL_TYPE_TEREDO:
8455 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8459 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8468 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8470 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8473 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8477 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8489 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8491 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8494 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8498 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8510 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8512 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8514 int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8516 switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8520 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8532 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8534 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8537 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8541 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8552 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8554 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8557 /* peek the message first */
8558 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8560 /* PF reset VF event */
8561 if (in_msg == IXGBE_PF_CONTROL_MSG) {
8562 /* dummy mbx read to ack pf */
8563 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8565 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8571 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8574 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8575 struct ixgbe_interrupt *intr =
8576 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8577 ixgbevf_intr_disable(dev);
8579 /* read-on-clear nic registers here */
8580 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8583 /* only one misc vector supported - mailbox */
8584 eicr &= IXGBE_VTEICR_MASK;
8585 if (eicr == IXGBE_MISC_VEC_ID)
8586 intr->flags |= IXGBE_FLAG_MAILBOX;
8592 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8594 struct ixgbe_interrupt *intr =
8595 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8597 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8598 ixgbevf_mbx_process(dev);
8599 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8602 ixgbevf_intr_enable(dev);
8608 ixgbevf_dev_interrupt_handler(void *param)
8610 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8612 ixgbevf_dev_interrupt_get_status(dev);
8613 ixgbevf_dev_interrupt_action(dev);
8617 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8618 * @hw: pointer to hardware structure
8620 * Stops the transmit data path and waits for the HW to internally empty
8621 * the Tx security block
8623 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8625 #define IXGBE_MAX_SECTX_POLL 40
8630 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8631 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8632 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8633 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8634 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8635 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8637 /* Use interrupt-safe sleep just in case */
8641 /* For informational purposes only */
8642 if (i >= IXGBE_MAX_SECTX_POLL)
8643 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8644 "path fully disabled. Continuing with init.");
8646 return IXGBE_SUCCESS;
8650 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8651 * @hw: pointer to hardware structure
8653 * Enables the transmit data path.
8655 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8659 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8660 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8661 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8662 IXGBE_WRITE_FLUSH(hw);
8664 return IXGBE_SUCCESS;
8667 /* restore n-tuple filter */
8669 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8671 struct ixgbe_filter_info *filter_info =
8672 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8673 struct ixgbe_5tuple_filter *node;
8675 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8676 ixgbe_inject_5tuple_filter(dev, node);
8680 /* restore ethernet type filter */
8682 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8684 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8685 struct ixgbe_filter_info *filter_info =
8686 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8689 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8690 if (filter_info->ethertype_mask & (1 << i)) {
8691 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8692 filter_info->ethertype_filters[i].etqf);
8693 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8694 filter_info->ethertype_filters[i].etqs);
8695 IXGBE_WRITE_FLUSH(hw);
8700 /* restore SYN filter */
8702 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8704 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8705 struct ixgbe_filter_info *filter_info =
8706 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8709 synqf = filter_info->syn_info;
8711 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8712 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8713 IXGBE_WRITE_FLUSH(hw);
8717 /* restore L2 tunnel filter */
8719 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8721 struct ixgbe_l2_tn_info *l2_tn_info =
8722 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8723 struct ixgbe_l2_tn_filter *node;
8724 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8726 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8727 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8728 l2_tn_conf.tunnel_id = node->key.tn_id;
8729 l2_tn_conf.pool = node->pool;
8730 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8734 /* restore rss filter */
8736 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8738 struct ixgbe_filter_info *filter_info =
8739 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8741 if (filter_info->rss_info.conf.queue_num)
8742 ixgbe_config_rss_filter(dev,
8743 &filter_info->rss_info, TRUE);
8747 ixgbe_filter_restore(struct rte_eth_dev *dev)
8749 ixgbe_ntuple_filter_restore(dev);
8750 ixgbe_ethertype_filter_restore(dev);
8751 ixgbe_syn_filter_restore(dev);
8752 ixgbe_fdir_filter_restore(dev);
8753 ixgbe_l2_tn_filter_restore(dev);
8754 ixgbe_rss_filter_restore(dev);
8760 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8762 struct ixgbe_l2_tn_info *l2_tn_info =
8763 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8764 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8766 if (l2_tn_info->e_tag_en)
8767 (void)ixgbe_e_tag_enable(hw);
8769 if (l2_tn_info->e_tag_fwd_en)
8770 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8772 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8775 /* remove all the n-tuple filters */
8777 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8779 struct ixgbe_filter_info *filter_info =
8780 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8781 struct ixgbe_5tuple_filter *p_5tuple;
8783 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8784 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8787 /* remove all the ether type filters */
8789 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8791 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8792 struct ixgbe_filter_info *filter_info =
8793 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8796 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8797 if (filter_info->ethertype_mask & (1 << i) &&
8798 !filter_info->ethertype_filters[i].conf) {
8799 (void)ixgbe_ethertype_filter_remove(filter_info,
8801 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8802 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8803 IXGBE_WRITE_FLUSH(hw);
8808 /* remove the SYN filter */
8810 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8812 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8813 struct ixgbe_filter_info *filter_info =
8814 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8816 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8817 filter_info->syn_info = 0;
8819 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8820 IXGBE_WRITE_FLUSH(hw);
8824 /* remove all the L2 tunnel filters */
8826 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8828 struct ixgbe_l2_tn_info *l2_tn_info =
8829 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8830 struct ixgbe_l2_tn_filter *l2_tn_filter;
8831 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8834 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8835 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8836 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8837 l2_tn_conf.pool = l2_tn_filter->pool;
8838 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8847 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8848 struct ixgbe_macsec_setting *macsec_setting)
8850 struct ixgbe_macsec_setting *macsec =
8851 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8853 macsec->offload_en = macsec_setting->offload_en;
8854 macsec->encrypt_en = macsec_setting->encrypt_en;
8855 macsec->replayprotect_en = macsec_setting->replayprotect_en;
8859 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8861 struct ixgbe_macsec_setting *macsec =
8862 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8864 macsec->offload_en = 0;
8865 macsec->encrypt_en = 0;
8866 macsec->replayprotect_en = 0;
8870 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8871 struct ixgbe_macsec_setting *macsec_setting)
8873 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8875 uint8_t en = macsec_setting->encrypt_en;
8876 uint8_t rp = macsec_setting->replayprotect_en;
8880 * As no ixgbe_disable_sec_rx_path equivalent is
8881 * implemented for tx in the base code, and we are
8882 * not allowed to modify the base code in DPDK, so
8883 * just call the hand-written one directly for now.
8884 * The hardware support has been checked by
8885 * ixgbe_disable_sec_rx_path().
8887 ixgbe_disable_sec_tx_path_generic(hw);
8889 /* Enable Ethernet CRC (required by MACsec offload) */
8890 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8891 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8892 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8894 /* Enable the TX and RX crypto engines */
8895 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8896 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8897 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8899 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8900 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8901 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8903 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8904 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8906 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8908 /* Enable SA lookup */
8909 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8910 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8911 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8912 IXGBE_LSECTXCTRL_AUTH;
8913 ctrl |= IXGBE_LSECTXCTRL_AISCI;
8914 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8915 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8916 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8918 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8919 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8920 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8921 ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8923 ctrl |= IXGBE_LSECRXCTRL_RP;
8925 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8926 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8928 /* Start the data paths */
8929 ixgbe_enable_sec_rx_path(hw);
8932 * As no ixgbe_enable_sec_rx_path equivalent is
8933 * implemented for tx in the base code, and we are
8934 * not allowed to modify the base code in DPDK, so
8935 * just call the hand-written one directly for now.
8937 ixgbe_enable_sec_tx_path_generic(hw);
8941 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8943 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8948 * As no ixgbe_disable_sec_rx_path equivalent is
8949 * implemented for tx in the base code, and we are
8950 * not allowed to modify the base code in DPDK, so
8951 * just call the hand-written one directly for now.
8952 * The hardware support has been checked by
8953 * ixgbe_disable_sec_rx_path().
8955 ixgbe_disable_sec_tx_path_generic(hw);
8957 /* Disable the TX and RX crypto engines */
8958 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8959 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8960 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8962 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8963 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8964 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8966 /* Disable SA lookup */
8967 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8968 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8969 ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8970 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8972 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8973 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8974 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8975 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8977 /* Start the data paths */
8978 ixgbe_enable_sec_rx_path(hw);
8981 * As no ixgbe_enable_sec_rx_path equivalent is
8982 * implemented for tx in the base code, and we are
8983 * not allowed to modify the base code in DPDK, so
8984 * just call the hand-written one directly for now.
8986 ixgbe_enable_sec_tx_path_generic(hw);
8989 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8990 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8991 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8992 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8993 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8994 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8995 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8996 IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8998 RTE_INIT(ixgbe_init_log)
9000 ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
9001 if (ixgbe_logtype_init >= 0)
9002 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
9003 ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
9004 if (ixgbe_logtype_driver >= 0)
9005 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
9006 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
9007 ixgbe_logtype_rx = rte_log_register("pmd.net.ixgbe.rx");
9008 if (ixgbe_logtype_rx >= 0)
9009 rte_log_set_level(ixgbe_logtype_rx, RTE_LOG_DEBUG);
9012 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
9013 ixgbe_logtype_tx = rte_log_register("pmd.net.ixgbe.tx");
9014 if (ixgbe_logtype_tx >= 0)
9015 rte_log_set_level(ixgbe_logtype_tx, RTE_LOG_DEBUG);
9018 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9019 ixgbe_logtype_tx_free = rte_log_register("pmd.net.ixgbe.tx_free");
9020 if (ixgbe_logtype_tx_free >= 0)
9021 rte_log_set_level(ixgbe_logtype_tx_free, RTE_LOG_DEBUG);