1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
13 #include <netinet/in.h>
14 #include <rte_string_fns.h>
15 #include <rte_byteorder.h>
16 #include <rte_common.h>
17 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_branch_prediction.h>
25 #include <rte_memory.h>
26 #include <rte_kvargs.h>
28 #include <rte_alarm.h>
29 #include <rte_ether.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
32 #include <rte_malloc.h>
33 #include <rte_random.h>
35 #include <rte_hash_crc.h>
36 #ifdef RTE_LIBRTE_SECURITY
37 #include <rte_security_driver.h>
40 #include "ixgbe_logs.h"
41 #include "base/ixgbe_api.h"
42 #include "base/ixgbe_vf.h"
43 #include "base/ixgbe_common.h"
44 #include "ixgbe_ethdev.h"
45 #include "ixgbe_bypass.h"
46 #include "ixgbe_rxtx.h"
47 #include "base/ixgbe_type.h"
48 #include "base/ixgbe_phy.h"
49 #include "ixgbe_regs.h"
52 * High threshold controlling when to start sending XOFF frames. Must be at
53 * least 8 bytes less than receive packet buffer size. This value is in units
56 #define IXGBE_FC_HI 0x80
59 * Low threshold controlling when to start sending XON frames. This value is
60 * in units of 1024 bytes.
62 #define IXGBE_FC_LO 0x40
64 /* Timer value included in XOFF frames. */
65 #define IXGBE_FC_PAUSE 0x680
67 /*Default value of Max Rx Queue*/
68 #define IXGBE_MAX_RX_QUEUE_NUM 128
70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
71 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
72 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
74 #define IXGBE_MMW_SIZE_DEFAULT 0x4
75 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
76 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
79 * Default values for RX/TX configuration
81 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
82 #define IXGBE_DEFAULT_RX_PTHRESH 8
83 #define IXGBE_DEFAULT_RX_HTHRESH 8
84 #define IXGBE_DEFAULT_RX_WTHRESH 0
86 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
87 #define IXGBE_DEFAULT_TX_PTHRESH 32
88 #define IXGBE_DEFAULT_TX_HTHRESH 0
89 #define IXGBE_DEFAULT_TX_WTHRESH 0
90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
92 /* Bit shift and mask */
93 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
94 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
95 #define IXGBE_8_BIT_WIDTH CHAR_BIT
96 #define IXGBE_8_BIT_MASK UINT8_MAX
98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
102 /* Additional timesync values. */
103 #define NSEC_PER_SEC 1000000000L
104 #define IXGBE_INCVAL_10GB 0x66666666
105 #define IXGBE_INCVAL_1GB 0x40000000
106 #define IXGBE_INCVAL_100 0x50000000
107 #define IXGBE_INCVAL_SHIFT_10GB 28
108 #define IXGBE_INCVAL_SHIFT_1GB 24
109 #define IXGBE_INCVAL_SHIFT_100 21
110 #define IXGBE_INCVAL_SHIFT_82599 7
111 #define IXGBE_INCPER_SHIFT_82599 24
113 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
115 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
117 #define IXGBE_ETAG_ETYPE 0x00005084
118 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
119 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
120 #define IXGBE_RAH_ADTYPE 0x40000000
121 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
122 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
125 #define IXGBE_QDE_STRIP_TAG 0x00000004
126 #define IXGBE_VTEICR_MASK 0x07
128 #define IXGBE_EXVET_VET_EXT_SHIFT 16
129 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK "pflink_fullchk"
133 static const char * const ixgbevf_valid_arguments[] = {
134 IXGBEVF_DEVARG_PFLINK_FULLCHK,
138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
150 static void ixgbe_dev_close(struct rte_eth_dev *dev);
151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
157 int wait_to_complete);
158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
159 struct rte_eth_stats *stats);
160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
161 struct rte_eth_xstat *xstats, unsigned n);
162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
163 struct rte_eth_xstat *xstats, unsigned n);
165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
166 uint64_t *values, unsigned int n);
167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
170 struct rte_eth_xstat_name *xstats_names,
172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
173 struct rte_eth_xstat_name *xstats_names, unsigned limit);
174 static int ixgbe_dev_xstats_get_names_by_id(
175 struct rte_eth_dev *dev,
176 struct rte_eth_xstat_name *xstats_names,
179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
186 struct rte_eth_dev_info *dev_info);
187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
189 struct rte_eth_dev_info *dev_info);
190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
193 uint16_t vlan_id, int on);
194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
195 enum rte_vlan_type vlan_type,
197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
198 uint16_t queue, bool on);
199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
213 struct rte_eth_fc_conf *fc_conf);
214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
215 struct rte_eth_fc_conf *fc_conf);
216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
217 struct rte_eth_pfc_conf *pfc_conf);
218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
219 struct rte_eth_rss_reta_entry64 *reta_conf,
221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
222 struct rte_eth_rss_reta_entry64 *reta_conf,
224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
230 static void ixgbe_dev_interrupt_handler(void *param);
231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
234 uint32_t timeout_ms);
236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
237 struct rte_ether_addr *mac_addr,
238 uint32_t index, uint32_t pool);
239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
241 struct rte_ether_addr *mac_addr);
242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
243 static bool is_device_supported(struct rte_eth_dev *dev,
244 struct rte_pci_driver *drv);
246 /* For Virtual Function support */
247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
249 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
250 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
252 int wait_to_complete);
253 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
254 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
255 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
259 struct rte_eth_stats *stats);
260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
262 uint16_t vlan_id, int on);
263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
264 uint16_t queue, int on);
265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
273 uint8_t queue, uint8_t msix_vector);
274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
280 /* For Eth VMDQ APIs support */
281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
282 rte_ether_addr * mac_addr, uint8_t on);
283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
285 struct rte_eth_mirror_conf *mirror_conf,
286 uint8_t rule_id, uint8_t on);
287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
294 uint8_t queue, uint8_t msix_vector);
295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
298 struct rte_ether_addr *mac_addr,
299 uint32_t index, uint32_t pool);
300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
302 struct rte_ether_addr *mac_addr);
303 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
304 struct rte_eth_syn_filter *filter);
305 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
306 enum rte_filter_op filter_op,
308 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
309 struct ixgbe_5tuple_filter *filter);
310 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
311 struct ixgbe_5tuple_filter *filter);
312 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
313 enum rte_filter_op filter_op,
315 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
316 struct rte_eth_ntuple_filter *filter);
317 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
318 enum rte_filter_op filter_op,
320 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
321 struct rte_eth_ethertype_filter *filter);
322 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
323 enum rte_filter_type filter_type,
324 enum rte_filter_op filter_op,
326 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
328 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
329 struct rte_ether_addr *mc_addr_set,
330 uint32_t nb_mc_addr);
331 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
332 struct rte_eth_dcb_info *dcb_info);
334 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
335 static int ixgbe_get_regs(struct rte_eth_dev *dev,
336 struct rte_dev_reg_info *regs);
337 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
338 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
339 struct rte_dev_eeprom_info *eeprom);
340 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
341 struct rte_dev_eeprom_info *eeprom);
343 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
344 struct rte_eth_dev_module_info *modinfo);
345 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
346 struct rte_dev_eeprom_info *info);
348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
350 struct rte_dev_reg_info *regs);
352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
355 struct timespec *timestamp,
357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
358 struct timespec *timestamp);
359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
361 struct timespec *timestamp);
362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
363 const struct timespec *timestamp);
364 static void ixgbevf_dev_interrupt_handler(void *param);
366 static int ixgbe_dev_l2_tunnel_eth_type_conf
367 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
368 static int ixgbe_dev_l2_tunnel_offload_set
369 (struct rte_eth_dev *dev,
370 struct rte_eth_l2_tunnel_conf *l2_tunnel,
373 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
374 enum rte_filter_op filter_op,
377 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
378 struct rte_eth_udp_tunnel *udp_tunnel);
379 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
380 struct rte_eth_udp_tunnel *udp_tunnel);
381 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
382 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
383 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
386 * Define VF Stats MACRO for Non "cleared on read" register
388 #define UPDATE_VF_STAT(reg, last, cur) \
390 uint32_t latest = IXGBE_READ_REG(hw, reg); \
391 cur += (latest - last) & UINT_MAX; \
395 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
397 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
398 u64 new_msb = IXGBE_READ_REG(hw, msb); \
399 u64 latest = ((new_msb << 32) | new_lsb); \
400 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
404 #define IXGBE_SET_HWSTRIP(h, q) do {\
405 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
406 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
407 (h)->bitmap[idx] |= 1 << bit;\
410 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
411 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
412 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
413 (h)->bitmap[idx] &= ~(1 << bit);\
416 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
417 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
418 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
419 (r) = (h)->bitmap[idx] >> bit & 1;\
423 * The set of PCI devices this driver supports
425 static const struct rte_pci_id pci_id_ixgbe_map[] = {
426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
474 #ifdef RTE_LIBRTE_IXGBE_BYPASS
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
477 { .vendor_id = 0, /* sentinel */ },
481 * The set of PCI devices this driver supports (for 82599 VF)
483 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
484 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
486 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
487 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
488 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
489 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
490 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
491 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
492 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
493 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
494 { .vendor_id = 0, /* sentinel */ },
497 static const struct rte_eth_desc_lim rx_desc_lim = {
498 .nb_max = IXGBE_MAX_RING_DESC,
499 .nb_min = IXGBE_MIN_RING_DESC,
500 .nb_align = IXGBE_RXD_ALIGN,
503 static const struct rte_eth_desc_lim tx_desc_lim = {
504 .nb_max = IXGBE_MAX_RING_DESC,
505 .nb_min = IXGBE_MIN_RING_DESC,
506 .nb_align = IXGBE_TXD_ALIGN,
507 .nb_seg_max = IXGBE_TX_MAX_SEG,
508 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
511 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
512 .dev_configure = ixgbe_dev_configure,
513 .dev_start = ixgbe_dev_start,
514 .dev_stop = ixgbe_dev_stop,
515 .dev_set_link_up = ixgbe_dev_set_link_up,
516 .dev_set_link_down = ixgbe_dev_set_link_down,
517 .dev_close = ixgbe_dev_close,
518 .dev_reset = ixgbe_dev_reset,
519 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
520 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
521 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
522 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
523 .link_update = ixgbe_dev_link_update,
524 .stats_get = ixgbe_dev_stats_get,
525 .xstats_get = ixgbe_dev_xstats_get,
526 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
527 .stats_reset = ixgbe_dev_stats_reset,
528 .xstats_reset = ixgbe_dev_xstats_reset,
529 .xstats_get_names = ixgbe_dev_xstats_get_names,
530 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
531 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
532 .fw_version_get = ixgbe_fw_version_get,
533 .dev_infos_get = ixgbe_dev_info_get,
534 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
535 .mtu_set = ixgbe_dev_mtu_set,
536 .vlan_filter_set = ixgbe_vlan_filter_set,
537 .vlan_tpid_set = ixgbe_vlan_tpid_set,
538 .vlan_offload_set = ixgbe_vlan_offload_set,
539 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
540 .rx_queue_start = ixgbe_dev_rx_queue_start,
541 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
542 .tx_queue_start = ixgbe_dev_tx_queue_start,
543 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
544 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
545 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
546 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
547 .rx_queue_release = ixgbe_dev_rx_queue_release,
548 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
549 .tx_queue_release = ixgbe_dev_tx_queue_release,
550 .dev_led_on = ixgbe_dev_led_on,
551 .dev_led_off = ixgbe_dev_led_off,
552 .flow_ctrl_get = ixgbe_flow_ctrl_get,
553 .flow_ctrl_set = ixgbe_flow_ctrl_set,
554 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
555 .mac_addr_add = ixgbe_add_rar,
556 .mac_addr_remove = ixgbe_remove_rar,
557 .mac_addr_set = ixgbe_set_default_mac_addr,
558 .uc_hash_table_set = ixgbe_uc_hash_table_set,
559 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
560 .mirror_rule_set = ixgbe_mirror_rule_set,
561 .mirror_rule_reset = ixgbe_mirror_rule_reset,
562 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
563 .reta_update = ixgbe_dev_rss_reta_update,
564 .reta_query = ixgbe_dev_rss_reta_query,
565 .rss_hash_update = ixgbe_dev_rss_hash_update,
566 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
567 .filter_ctrl = ixgbe_dev_filter_ctrl,
568 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
569 .rxq_info_get = ixgbe_rxq_info_get,
570 .txq_info_get = ixgbe_txq_info_get,
571 .timesync_enable = ixgbe_timesync_enable,
572 .timesync_disable = ixgbe_timesync_disable,
573 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
574 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
575 .get_reg = ixgbe_get_regs,
576 .get_eeprom_length = ixgbe_get_eeprom_length,
577 .get_eeprom = ixgbe_get_eeprom,
578 .set_eeprom = ixgbe_set_eeprom,
579 .get_module_info = ixgbe_get_module_info,
580 .get_module_eeprom = ixgbe_get_module_eeprom,
581 .get_dcb_info = ixgbe_dev_get_dcb_info,
582 .timesync_adjust_time = ixgbe_timesync_adjust_time,
583 .timesync_read_time = ixgbe_timesync_read_time,
584 .timesync_write_time = ixgbe_timesync_write_time,
585 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
586 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
587 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
588 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
589 .tm_ops_get = ixgbe_tm_ops_get,
590 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup,
594 * dev_ops for virtual function, bare necessities for basic vf
595 * operation have been implemented
597 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
598 .dev_configure = ixgbevf_dev_configure,
599 .dev_start = ixgbevf_dev_start,
600 .dev_stop = ixgbevf_dev_stop,
601 .link_update = ixgbevf_dev_link_update,
602 .stats_get = ixgbevf_dev_stats_get,
603 .xstats_get = ixgbevf_dev_xstats_get,
604 .stats_reset = ixgbevf_dev_stats_reset,
605 .xstats_reset = ixgbevf_dev_stats_reset,
606 .xstats_get_names = ixgbevf_dev_xstats_get_names,
607 .dev_close = ixgbevf_dev_close,
608 .dev_reset = ixgbevf_dev_reset,
609 .promiscuous_enable = ixgbevf_dev_promiscuous_enable,
610 .promiscuous_disable = ixgbevf_dev_promiscuous_disable,
611 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
612 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
613 .dev_infos_get = ixgbevf_dev_info_get,
614 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
615 .mtu_set = ixgbevf_dev_set_mtu,
616 .vlan_filter_set = ixgbevf_vlan_filter_set,
617 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
618 .vlan_offload_set = ixgbevf_vlan_offload_set,
619 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
620 .rx_queue_release = ixgbe_dev_rx_queue_release,
621 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
622 .tx_queue_release = ixgbe_dev_tx_queue_release,
623 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
624 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
625 .mac_addr_add = ixgbevf_add_mac_addr,
626 .mac_addr_remove = ixgbevf_remove_mac_addr,
627 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
628 .rxq_info_get = ixgbe_rxq_info_get,
629 .txq_info_get = ixgbe_txq_info_get,
630 .mac_addr_set = ixgbevf_set_default_mac_addr,
631 .get_reg = ixgbevf_get_regs,
632 .reta_update = ixgbe_dev_rss_reta_update,
633 .reta_query = ixgbe_dev_rss_reta_query,
634 .rss_hash_update = ixgbe_dev_rss_hash_update,
635 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
636 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup,
639 /* store statistics names and its offset in stats structure */
640 struct rte_ixgbe_xstats_name_off {
641 char name[RTE_ETH_XSTATS_NAME_SIZE];
645 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
646 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
647 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
648 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
649 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
650 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
651 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
652 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
653 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
654 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
655 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
656 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
657 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
658 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
659 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
660 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
662 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
664 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
665 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
666 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
667 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
668 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
669 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
670 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
671 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
672 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
673 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
674 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
675 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
676 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
677 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
678 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
679 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
680 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
682 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
684 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
685 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
686 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
687 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
689 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
691 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
693 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
695 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
697 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
699 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
702 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
703 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
704 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
706 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
707 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
708 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
709 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
710 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
712 {"rx_fcoe_no_direct_data_placement_ext_buff",
713 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
715 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
717 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
719 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
721 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
723 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
726 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
727 sizeof(rte_ixgbe_stats_strings[0]))
729 /* MACsec statistics */
730 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
731 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
733 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
734 out_pkts_encrypted)},
735 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
736 out_pkts_protected)},
737 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
738 out_octets_encrypted)},
739 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
740 out_octets_protected)},
741 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
743 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
745 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
747 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
748 in_pkts_unknownsci)},
749 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
750 in_octets_decrypted)},
751 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
752 in_octets_validated)},
753 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
755 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
757 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
759 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
761 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
763 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
765 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
767 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
768 in_pkts_notusingsa)},
771 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
772 sizeof(rte_ixgbe_macsec_strings[0]))
774 /* Per-queue statistics */
775 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
776 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
777 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
778 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
779 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
782 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
783 sizeof(rte_ixgbe_rxq_strings[0]))
784 #define IXGBE_NB_RXQ_PRIO_VALUES 8
786 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
787 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
788 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
789 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
793 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
794 sizeof(rte_ixgbe_txq_strings[0]))
795 #define IXGBE_NB_TXQ_PRIO_VALUES 8
797 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
798 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
801 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
802 sizeof(rte_ixgbevf_stats_strings[0]))
805 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
808 ixgbe_is_sfp(struct ixgbe_hw *hw)
810 switch (hw->phy.type) {
811 case ixgbe_phy_sfp_avago:
812 case ixgbe_phy_sfp_ftl:
813 case ixgbe_phy_sfp_intel:
814 case ixgbe_phy_sfp_unknown:
815 case ixgbe_phy_sfp_passive_tyco:
816 case ixgbe_phy_sfp_passive_unknown:
823 static inline int32_t
824 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
829 status = ixgbe_reset_hw(hw);
831 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
832 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
833 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
834 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
835 IXGBE_WRITE_FLUSH(hw);
837 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
838 status = IXGBE_SUCCESS;
843 ixgbe_enable_intr(struct rte_eth_dev *dev)
845 struct ixgbe_interrupt *intr =
846 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
847 struct ixgbe_hw *hw =
848 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
850 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
851 IXGBE_WRITE_FLUSH(hw);
855 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
858 ixgbe_disable_intr(struct ixgbe_hw *hw)
860 PMD_INIT_FUNC_TRACE();
862 if (hw->mac.type == ixgbe_mac_82598EB) {
863 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
865 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
866 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
867 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
869 IXGBE_WRITE_FLUSH(hw);
873 * This function resets queue statistics mapping registers.
874 * From Niantic datasheet, Initialization of Statistics section:
875 * "...if software requires the queue counters, the RQSMR and TQSM registers
876 * must be re-programmed following a device reset.
879 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
883 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
884 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
885 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
891 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
896 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
897 #define NB_QMAP_FIELDS_PER_QSM_REG 4
898 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
900 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
901 struct ixgbe_stat_mapping_registers *stat_mappings =
902 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
903 uint32_t qsmr_mask = 0;
904 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
908 if ((hw->mac.type != ixgbe_mac_82599EB) &&
909 (hw->mac.type != ixgbe_mac_X540) &&
910 (hw->mac.type != ixgbe_mac_X550) &&
911 (hw->mac.type != ixgbe_mac_X550EM_x) &&
912 (hw->mac.type != ixgbe_mac_X550EM_a))
915 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
916 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
919 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
920 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
921 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
924 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
926 /* Now clear any previous stat_idx set */
927 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
929 stat_mappings->tqsm[n] &= ~clearing_mask;
931 stat_mappings->rqsmr[n] &= ~clearing_mask;
933 q_map = (uint32_t)stat_idx;
934 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
935 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
937 stat_mappings->tqsm[n] |= qsmr_mask;
939 stat_mappings->rqsmr[n] |= qsmr_mask;
941 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
942 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
944 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
945 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
947 /* Now write the mapping in the appropriate register */
949 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
950 stat_mappings->rqsmr[n], n);
951 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
953 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
954 stat_mappings->tqsm[n], n);
955 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
961 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
963 struct ixgbe_stat_mapping_registers *stat_mappings =
964 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
965 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
968 /* write whatever was in stat mapping table to the NIC */
969 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
971 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
974 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
979 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
982 struct ixgbe_dcb_tc_config *tc;
983 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
985 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
986 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
987 for (i = 0; i < dcb_max_tc; i++) {
988 tc = &dcb_config->tc_config[i];
989 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
990 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
991 (uint8_t)(100/dcb_max_tc + (i & 1));
992 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
993 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
994 (uint8_t)(100/dcb_max_tc + (i & 1));
995 tc->pfc = ixgbe_dcb_pfc_disabled;
998 /* Initialize default user to priority mapping, UPx->TC0 */
999 tc = &dcb_config->tc_config[0];
1000 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1001 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1002 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1003 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1004 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1006 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1007 dcb_config->pfc_mode_enable = false;
1008 dcb_config->vt_mode = true;
1009 dcb_config->round_robin_enable = false;
1010 /* support all DCB capabilities in 82599 */
1011 dcb_config->support.capabilities = 0xFF;
1013 /*we only support 4 Tcs for X540, X550 */
1014 if (hw->mac.type == ixgbe_mac_X540 ||
1015 hw->mac.type == ixgbe_mac_X550 ||
1016 hw->mac.type == ixgbe_mac_X550EM_x ||
1017 hw->mac.type == ixgbe_mac_X550EM_a) {
1018 dcb_config->num_tcs.pg_tcs = 4;
1019 dcb_config->num_tcs.pfc_tcs = 4;
1024 * Ensure that all locks are released before first NVM or PHY access
1027 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1032 * Phy lock should not fail in this early stage. If this is the case,
1033 * it is due to an improper exit of the application.
1034 * So force the release of the faulty lock. Release of common lock
1035 * is done automatically by swfw_sync function.
1037 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1038 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1039 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1041 ixgbe_release_swfw_semaphore(hw, mask);
1044 * These ones are more tricky since they are common to all ports; but
1045 * swfw_sync retries last long enough (1s) to be almost sure that if
1046 * lock can not be taken it is due to an improper lock of the
1049 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1050 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1051 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1053 ixgbe_release_swfw_semaphore(hw, mask);
1057 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1058 * It returns 0 on success.
1061 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1063 struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1064 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1065 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1066 struct ixgbe_hw *hw =
1067 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1068 struct ixgbe_vfta *shadow_vfta =
1069 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1070 struct ixgbe_hwstrip *hwstrip =
1071 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1072 struct ixgbe_dcb_config *dcb_config =
1073 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1074 struct ixgbe_filter_info *filter_info =
1075 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1076 struct ixgbe_bw_conf *bw_conf =
1077 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1082 PMD_INIT_FUNC_TRACE();
1084 ixgbe_dev_macsec_setting_reset(eth_dev);
1086 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1087 eth_dev->rx_queue_count = ixgbe_dev_rx_queue_count;
1088 eth_dev->rx_descriptor_done = ixgbe_dev_rx_descriptor_done;
1089 eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1090 eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1091 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1092 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1093 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1096 * For secondary processes, we don't initialise any further as primary
1097 * has already done this work. Only check we don't need a different
1098 * RX and TX function.
1100 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1101 struct ixgbe_tx_queue *txq;
1102 /* TX queue function in primary, set by last queue initialized
1103 * Tx queue may not initialized by primary process
1105 if (eth_dev->data->tx_queues) {
1106 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1107 ixgbe_set_tx_function(eth_dev, txq);
1109 /* Use default TX function if we get here */
1110 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1111 "Using default TX function.");
1114 ixgbe_set_rx_function(eth_dev);
1119 rte_atomic32_clear(&ad->link_thread_running);
1120 rte_eth_copy_pci_info(eth_dev, pci_dev);
1122 /* Vendor and Device ID need to be set before init of shared code */
1123 hw->device_id = pci_dev->id.device_id;
1124 hw->vendor_id = pci_dev->id.vendor_id;
1125 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1126 hw->allow_unsupported_sfp = 1;
1128 /* Initialize the shared code (base driver) */
1129 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1130 diag = ixgbe_bypass_init_shared_code(hw);
1132 diag = ixgbe_init_shared_code(hw);
1133 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1135 if (diag != IXGBE_SUCCESS) {
1136 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1140 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1141 PMD_INIT_LOG(ERR, "\nERROR: "
1142 "Firmware recovery mode detected. Limiting functionality.\n"
1143 "Refer to the Intel(R) Ethernet Adapters and Devices "
1144 "User Guide for details on firmware recovery mode.");
1148 /* pick up the PCI bus settings for reporting later */
1149 ixgbe_get_bus_info(hw);
1151 /* Unlock any pending hardware semaphore */
1152 ixgbe_swfw_lock_reset(hw);
1154 #ifdef RTE_LIBRTE_SECURITY
1155 /* Initialize security_ctx only for primary process*/
1156 if (ixgbe_ipsec_ctx_create(eth_dev))
1160 /* Initialize DCB configuration*/
1161 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1162 ixgbe_dcb_init(hw, dcb_config);
1163 /* Get Hardware Flow Control setting */
1164 hw->fc.requested_mode = ixgbe_fc_none;
1165 hw->fc.current_mode = ixgbe_fc_none;
1166 hw->fc.pause_time = IXGBE_FC_PAUSE;
1167 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1168 hw->fc.low_water[i] = IXGBE_FC_LO;
1169 hw->fc.high_water[i] = IXGBE_FC_HI;
1171 hw->fc.send_xon = 1;
1173 /* Make sure we have a good EEPROM before we read from it */
1174 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1175 if (diag != IXGBE_SUCCESS) {
1176 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1180 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1181 diag = ixgbe_bypass_init_hw(hw);
1183 diag = ixgbe_init_hw(hw);
1184 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1187 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1188 * is called too soon after the kernel driver unbinding/binding occurs.
1189 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1190 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1191 * also called. See ixgbe_identify_phy_82599(). The reason for the
1192 * failure is not known, and only occuts when virtualisation features
1193 * are disabled in the bios. A delay of 100ms was found to be enough by
1194 * trial-and-error, and is doubled to be safe.
1196 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1198 diag = ixgbe_init_hw(hw);
1201 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1202 diag = IXGBE_SUCCESS;
1204 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1205 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1206 "LOM. Please be aware there may be issues associated "
1207 "with your hardware.");
1208 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1209 "please contact your Intel or hardware representative "
1210 "who provided you with this hardware.");
1211 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1212 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1214 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1218 /* Reset the hw statistics */
1219 ixgbe_dev_stats_reset(eth_dev);
1221 /* disable interrupt */
1222 ixgbe_disable_intr(hw);
1224 /* reset mappings for queue statistics hw counters*/
1225 ixgbe_reset_qstat_mappings(hw);
1227 /* Allocate memory for storing MAC addresses */
1228 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1229 hw->mac.num_rar_entries, 0);
1230 if (eth_dev->data->mac_addrs == NULL) {
1232 "Failed to allocate %u bytes needed to store "
1234 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1237 /* Copy the permanent MAC address */
1238 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1239 ð_dev->data->mac_addrs[0]);
1241 /* Allocate memory for storing hash filter MAC addresses */
1242 eth_dev->data->hash_mac_addrs = rte_zmalloc(
1243 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1244 if (eth_dev->data->hash_mac_addrs == NULL) {
1246 "Failed to allocate %d bytes needed to store MAC addresses",
1247 RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1251 /* Pass the information to the rte_eth_dev_close() that it should also
1252 * release the private port resources.
1254 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1256 /* initialize the vfta */
1257 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1259 /* initialize the hw strip bitmap*/
1260 memset(hwstrip, 0, sizeof(*hwstrip));
1262 /* initialize PF if max_vfs not zero */
1263 ixgbe_pf_host_init(eth_dev);
1265 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1266 /* let hardware know driver is loaded */
1267 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1268 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1269 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1270 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1271 IXGBE_WRITE_FLUSH(hw);
1273 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1274 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1275 (int) hw->mac.type, (int) hw->phy.type,
1276 (int) hw->phy.sfp_type);
1278 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1279 (int) hw->mac.type, (int) hw->phy.type);
1281 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1282 eth_dev->data->port_id, pci_dev->id.vendor_id,
1283 pci_dev->id.device_id);
1285 rte_intr_callback_register(intr_handle,
1286 ixgbe_dev_interrupt_handler, eth_dev);
1288 /* enable uio/vfio intr/eventfd mapping */
1289 rte_intr_enable(intr_handle);
1291 /* enable support intr */
1292 ixgbe_enable_intr(eth_dev);
1294 /* initialize filter info */
1295 memset(filter_info, 0,
1296 sizeof(struct ixgbe_filter_info));
1298 /* initialize 5tuple filter list */
1299 TAILQ_INIT(&filter_info->fivetuple_list);
1301 /* initialize flow director filter list & hash */
1302 ixgbe_fdir_filter_init(eth_dev);
1304 /* initialize l2 tunnel filter list & hash */
1305 ixgbe_l2_tn_filter_init(eth_dev);
1307 /* initialize flow filter lists */
1308 ixgbe_filterlist_init();
1310 /* initialize bandwidth configuration info */
1311 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1313 /* initialize Traffic Manager configuration */
1314 ixgbe_tm_conf_init(eth_dev);
1320 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1322 PMD_INIT_FUNC_TRACE();
1324 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1327 ixgbe_dev_close(eth_dev);
1332 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1334 struct ixgbe_filter_info *filter_info =
1335 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1336 struct ixgbe_5tuple_filter *p_5tuple;
1338 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1339 TAILQ_REMOVE(&filter_info->fivetuple_list,
1344 memset(filter_info->fivetuple_mask, 0,
1345 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1350 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1352 struct ixgbe_hw_fdir_info *fdir_info =
1353 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1354 struct ixgbe_fdir_filter *fdir_filter;
1356 if (fdir_info->hash_map)
1357 rte_free(fdir_info->hash_map);
1358 if (fdir_info->hash_handle)
1359 rte_hash_free(fdir_info->hash_handle);
1361 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1362 TAILQ_REMOVE(&fdir_info->fdir_list,
1365 rte_free(fdir_filter);
1371 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1373 struct ixgbe_l2_tn_info *l2_tn_info =
1374 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1375 struct ixgbe_l2_tn_filter *l2_tn_filter;
1377 if (l2_tn_info->hash_map)
1378 rte_free(l2_tn_info->hash_map);
1379 if (l2_tn_info->hash_handle)
1380 rte_hash_free(l2_tn_info->hash_handle);
1382 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1383 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1386 rte_free(l2_tn_filter);
1392 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1394 struct ixgbe_hw_fdir_info *fdir_info =
1395 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1396 char fdir_hash_name[RTE_HASH_NAMESIZE];
1397 struct rte_hash_parameters fdir_hash_params = {
1398 .name = fdir_hash_name,
1399 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1400 .key_len = sizeof(union ixgbe_atr_input),
1401 .hash_func = rte_hash_crc,
1402 .hash_func_init_val = 0,
1403 .socket_id = rte_socket_id(),
1406 TAILQ_INIT(&fdir_info->fdir_list);
1407 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1408 "fdir_%s", eth_dev->device->name);
1409 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1410 if (!fdir_info->hash_handle) {
1411 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1414 fdir_info->hash_map = rte_zmalloc("ixgbe",
1415 sizeof(struct ixgbe_fdir_filter *) *
1416 IXGBE_MAX_FDIR_FILTER_NUM,
1418 if (!fdir_info->hash_map) {
1420 "Failed to allocate memory for fdir hash map!");
1423 fdir_info->mask_added = FALSE;
1428 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1430 struct ixgbe_l2_tn_info *l2_tn_info =
1431 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1432 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1433 struct rte_hash_parameters l2_tn_hash_params = {
1434 .name = l2_tn_hash_name,
1435 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1436 .key_len = sizeof(struct ixgbe_l2_tn_key),
1437 .hash_func = rte_hash_crc,
1438 .hash_func_init_val = 0,
1439 .socket_id = rte_socket_id(),
1442 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1443 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1444 "l2_tn_%s", eth_dev->device->name);
1445 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1446 if (!l2_tn_info->hash_handle) {
1447 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1450 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1451 sizeof(struct ixgbe_l2_tn_filter *) *
1452 IXGBE_MAX_L2_TN_FILTER_NUM,
1454 if (!l2_tn_info->hash_map) {
1456 "Failed to allocate memory for L2 TN hash map!");
1459 l2_tn_info->e_tag_en = FALSE;
1460 l2_tn_info->e_tag_fwd_en = FALSE;
1461 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1466 * Negotiate mailbox API version with the PF.
1467 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1468 * Then we try to negotiate starting with the most recent one.
1469 * If all negotiation attempts fail, then we will proceed with
1470 * the default one (ixgbe_mbox_api_10).
1473 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1477 /* start with highest supported, proceed down */
1478 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1486 i != RTE_DIM(sup_ver) &&
1487 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1493 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1497 /* Set Organizationally Unique Identifier (OUI) prefix. */
1498 mac_addr->addr_bytes[0] = 0x00;
1499 mac_addr->addr_bytes[1] = 0x09;
1500 mac_addr->addr_bytes[2] = 0xC0;
1501 /* Force indication of locally assigned MAC address. */
1502 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1503 /* Generate the last 3 bytes of the MAC address with a random number. */
1504 random = rte_rand();
1505 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1509 devarg_handle_int(__rte_unused const char *key, const char *value,
1512 uint16_t *n = extra_args;
1514 if (value == NULL || extra_args == NULL)
1517 *n = (uint16_t)strtoul(value, NULL, 0);
1518 if (*n == USHRT_MAX && errno == ERANGE)
1525 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1526 struct rte_devargs *devargs)
1528 struct rte_kvargs *kvlist;
1529 uint16_t pflink_fullchk;
1531 if (devargs == NULL)
1534 kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1538 if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1539 rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1540 devarg_handle_int, &pflink_fullchk) == 0 &&
1541 pflink_fullchk == 1)
1542 adapter->pflink_fullchk = 1;
1544 rte_kvargs_free(kvlist);
1548 * Virtual Function device init
1551 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1555 struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1556 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1557 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1558 struct ixgbe_hw *hw =
1559 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1560 struct ixgbe_vfta *shadow_vfta =
1561 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1562 struct ixgbe_hwstrip *hwstrip =
1563 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1564 struct rte_ether_addr *perm_addr =
1565 (struct rte_ether_addr *)hw->mac.perm_addr;
1567 PMD_INIT_FUNC_TRACE();
1569 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1570 eth_dev->rx_descriptor_done = ixgbe_dev_rx_descriptor_done;
1571 eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1572 eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1573 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1574 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1576 /* for secondary processes, we don't initialise any further as primary
1577 * has already done this work. Only check we don't need a different
1580 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1581 struct ixgbe_tx_queue *txq;
1582 /* TX queue function in primary, set by last queue initialized
1583 * Tx queue may not initialized by primary process
1585 if (eth_dev->data->tx_queues) {
1586 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1587 ixgbe_set_tx_function(eth_dev, txq);
1589 /* Use default TX function if we get here */
1590 PMD_INIT_LOG(NOTICE,
1591 "No TX queues configured yet. Using default TX function.");
1594 ixgbe_set_rx_function(eth_dev);
1599 rte_atomic32_clear(&ad->link_thread_running);
1600 ixgbevf_parse_devargs(eth_dev->data->dev_private,
1601 pci_dev->device.devargs);
1603 rte_eth_copy_pci_info(eth_dev, pci_dev);
1605 hw->device_id = pci_dev->id.device_id;
1606 hw->vendor_id = pci_dev->id.vendor_id;
1607 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1609 /* initialize the vfta */
1610 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1612 /* initialize the hw strip bitmap*/
1613 memset(hwstrip, 0, sizeof(*hwstrip));
1615 /* Initialize the shared code (base driver) */
1616 diag = ixgbe_init_shared_code(hw);
1617 if (diag != IXGBE_SUCCESS) {
1618 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1622 /* init_mailbox_params */
1623 hw->mbx.ops.init_params(hw);
1625 /* Reset the hw statistics */
1626 ixgbevf_dev_stats_reset(eth_dev);
1628 /* Disable the interrupts for VF */
1629 ixgbevf_intr_disable(eth_dev);
1631 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1632 diag = hw->mac.ops.reset_hw(hw);
1635 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1636 * the underlying PF driver has not assigned a MAC address to the VF.
1637 * In this case, assign a random MAC address.
1639 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1640 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1642 * This error code will be propagated to the app by
1643 * rte_eth_dev_reset, so use a public error code rather than
1644 * the internal-only IXGBE_ERR_RESET_FAILED
1649 /* negotiate mailbox API version to use with the PF. */
1650 ixgbevf_negotiate_api(hw);
1652 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1653 ixgbevf_get_queues(hw, &tcs, &tc);
1655 /* Allocate memory for storing MAC addresses */
1656 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1657 hw->mac.num_rar_entries, 0);
1658 if (eth_dev->data->mac_addrs == NULL) {
1660 "Failed to allocate %u bytes needed to store "
1662 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1666 /* Pass the information to the rte_eth_dev_close() that it should also
1667 * release the private port resources.
1669 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1671 /* Generate a random MAC address, if none was assigned by PF. */
1672 if (rte_is_zero_ether_addr(perm_addr)) {
1673 generate_random_mac_addr(perm_addr);
1674 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1676 rte_free(eth_dev->data->mac_addrs);
1677 eth_dev->data->mac_addrs = NULL;
1680 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1681 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1682 "%02x:%02x:%02x:%02x:%02x:%02x",
1683 perm_addr->addr_bytes[0],
1684 perm_addr->addr_bytes[1],
1685 perm_addr->addr_bytes[2],
1686 perm_addr->addr_bytes[3],
1687 perm_addr->addr_bytes[4],
1688 perm_addr->addr_bytes[5]);
1691 /* Copy the permanent MAC address */
1692 rte_ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1694 /* reset the hardware with the new settings */
1695 diag = hw->mac.ops.start_hw(hw);
1701 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1705 rte_intr_callback_register(intr_handle,
1706 ixgbevf_dev_interrupt_handler, eth_dev);
1707 rte_intr_enable(intr_handle);
1708 ixgbevf_intr_enable(eth_dev);
1710 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1711 eth_dev->data->port_id, pci_dev->id.vendor_id,
1712 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1717 /* Virtual Function device uninit */
1720 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1722 PMD_INIT_FUNC_TRACE();
1724 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1727 ixgbevf_dev_close(eth_dev);
1733 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1734 struct rte_pci_device *pci_dev)
1736 char name[RTE_ETH_NAME_MAX_LEN];
1737 struct rte_eth_dev *pf_ethdev;
1738 struct rte_eth_devargs eth_da;
1741 if (pci_dev->device.devargs) {
1742 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1747 memset(ð_da, 0, sizeof(eth_da));
1749 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1750 sizeof(struct ixgbe_adapter),
1751 eth_dev_pci_specific_init, pci_dev,
1752 eth_ixgbe_dev_init, NULL);
1754 if (retval || eth_da.nb_representor_ports < 1)
1757 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1758 if (pf_ethdev == NULL)
1761 /* probe VF representor ports */
1762 for (i = 0; i < eth_da.nb_representor_ports; i++) {
1763 struct ixgbe_vf_info *vfinfo;
1764 struct ixgbe_vf_representor representor;
1766 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1767 pf_ethdev->data->dev_private);
1768 if (vfinfo == NULL) {
1770 "no virtual functions supported by PF");
1774 representor.vf_id = eth_da.representor_ports[i];
1775 representor.switch_domain_id = vfinfo->switch_domain_id;
1776 representor.pf_ethdev = pf_ethdev;
1778 /* representor port net_bdf_port */
1779 snprintf(name, sizeof(name), "net_%s_representor_%d",
1780 pci_dev->device.name,
1781 eth_da.representor_ports[i]);
1783 retval = rte_eth_dev_create(&pci_dev->device, name,
1784 sizeof(struct ixgbe_vf_representor), NULL, NULL,
1785 ixgbe_vf_representor_init, &representor);
1788 PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1789 "representor %s.", name);
1795 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1797 struct rte_eth_dev *ethdev;
1799 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1803 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1804 return rte_eth_dev_pci_generic_remove(pci_dev,
1805 ixgbe_vf_representor_uninit);
1807 return rte_eth_dev_pci_generic_remove(pci_dev,
1808 eth_ixgbe_dev_uninit);
1811 static struct rte_pci_driver rte_ixgbe_pmd = {
1812 .id_table = pci_id_ixgbe_map,
1813 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1814 .probe = eth_ixgbe_pci_probe,
1815 .remove = eth_ixgbe_pci_remove,
1818 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1819 struct rte_pci_device *pci_dev)
1821 return rte_eth_dev_pci_generic_probe(pci_dev,
1822 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1825 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1827 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1831 * virtual function driver struct
1833 static struct rte_pci_driver rte_ixgbevf_pmd = {
1834 .id_table = pci_id_ixgbevf_map,
1835 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1836 .probe = eth_ixgbevf_pci_probe,
1837 .remove = eth_ixgbevf_pci_remove,
1841 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1843 struct ixgbe_hw *hw =
1844 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845 struct ixgbe_vfta *shadow_vfta =
1846 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1851 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1852 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1853 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1858 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1860 /* update local VFTA copy */
1861 shadow_vfta->vfta[vid_idx] = vfta;
1867 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1870 ixgbe_vlan_hw_strip_enable(dev, queue);
1872 ixgbe_vlan_hw_strip_disable(dev, queue);
1876 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1877 enum rte_vlan_type vlan_type,
1880 struct ixgbe_hw *hw =
1881 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1886 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1887 qinq &= IXGBE_DMATXCTL_GDV;
1889 switch (vlan_type) {
1890 case ETH_VLAN_TYPE_INNER:
1892 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1893 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1894 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1895 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1896 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1897 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1898 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1901 PMD_DRV_LOG(ERR, "Inner type is not supported"
1905 case ETH_VLAN_TYPE_OUTER:
1907 /* Only the high 16-bits is valid */
1908 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1909 IXGBE_EXVET_VET_EXT_SHIFT);
1911 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1912 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1913 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1914 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1915 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1916 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1917 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1923 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1931 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1933 struct ixgbe_hw *hw =
1934 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1937 PMD_INIT_FUNC_TRACE();
1939 /* Filter Table Disable */
1940 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1941 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1943 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1947 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1949 struct ixgbe_hw *hw =
1950 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1951 struct ixgbe_vfta *shadow_vfta =
1952 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1956 PMD_INIT_FUNC_TRACE();
1958 /* Filter Table Enable */
1959 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1960 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1961 vlnctrl |= IXGBE_VLNCTRL_VFE;
1963 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1965 /* write whatever is in local vfta copy */
1966 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1967 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1971 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1973 struct ixgbe_hwstrip *hwstrip =
1974 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1975 struct ixgbe_rx_queue *rxq;
1977 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1981 IXGBE_SET_HWSTRIP(hwstrip, queue);
1983 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1985 if (queue >= dev->data->nb_rx_queues)
1988 rxq = dev->data->rx_queues[queue];
1991 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1992 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1994 rxq->vlan_flags = PKT_RX_VLAN;
1995 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2000 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2002 struct ixgbe_hw *hw =
2003 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2006 PMD_INIT_FUNC_TRACE();
2008 if (hw->mac.type == ixgbe_mac_82598EB) {
2009 /* No queue level support */
2010 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2014 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2015 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2016 ctrl &= ~IXGBE_RXDCTL_VME;
2017 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2019 /* record those setting for HW strip per queue */
2020 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2024 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2026 struct ixgbe_hw *hw =
2027 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2030 PMD_INIT_FUNC_TRACE();
2032 if (hw->mac.type == ixgbe_mac_82598EB) {
2033 /* No queue level supported */
2034 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2038 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2039 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2040 ctrl |= IXGBE_RXDCTL_VME;
2041 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2043 /* record those setting for HW strip per queue */
2044 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2048 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2050 struct ixgbe_hw *hw =
2051 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2054 PMD_INIT_FUNC_TRACE();
2056 /* DMATXCTRL: Geric Double VLAN Disable */
2057 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2058 ctrl &= ~IXGBE_DMATXCTL_GDV;
2059 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2061 /* CTRL_EXT: Global Double VLAN Disable */
2062 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2063 ctrl &= ~IXGBE_EXTENDED_VLAN;
2064 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2069 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2071 struct ixgbe_hw *hw =
2072 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2075 PMD_INIT_FUNC_TRACE();
2077 /* DMATXCTRL: Geric Double VLAN Enable */
2078 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2079 ctrl |= IXGBE_DMATXCTL_GDV;
2080 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2082 /* CTRL_EXT: Global Double VLAN Enable */
2083 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2084 ctrl |= IXGBE_EXTENDED_VLAN;
2085 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2087 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2088 if (hw->mac.type == ixgbe_mac_X550 ||
2089 hw->mac.type == ixgbe_mac_X550EM_x ||
2090 hw->mac.type == ixgbe_mac_X550EM_a) {
2091 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2092 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2093 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2097 * VET EXT field in the EXVET register = 0x8100 by default
2098 * So no need to change. Same to VT field of DMATXCTL register
2103 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2105 struct ixgbe_hw *hw =
2106 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2107 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2110 struct ixgbe_rx_queue *rxq;
2113 PMD_INIT_FUNC_TRACE();
2115 if (hw->mac.type == ixgbe_mac_82598EB) {
2116 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2117 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2118 ctrl |= IXGBE_VLNCTRL_VME;
2119 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2121 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2122 ctrl &= ~IXGBE_VLNCTRL_VME;
2123 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2127 * Other 10G NIC, the VLAN strip can be setup
2128 * per queue in RXDCTL
2130 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2131 rxq = dev->data->rx_queues[i];
2132 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2133 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2134 ctrl |= IXGBE_RXDCTL_VME;
2137 ctrl &= ~IXGBE_RXDCTL_VME;
2140 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2142 /* record those setting for HW strip per queue */
2143 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2149 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2152 struct rte_eth_rxmode *rxmode;
2153 struct ixgbe_rx_queue *rxq;
2155 if (mask & ETH_VLAN_STRIP_MASK) {
2156 rxmode = &dev->data->dev_conf.rxmode;
2157 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2158 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2159 rxq = dev->data->rx_queues[i];
2160 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2163 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2164 rxq = dev->data->rx_queues[i];
2165 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2171 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2173 struct rte_eth_rxmode *rxmode;
2174 rxmode = &dev->data->dev_conf.rxmode;
2176 if (mask & ETH_VLAN_STRIP_MASK) {
2177 ixgbe_vlan_hw_strip_config(dev);
2180 if (mask & ETH_VLAN_FILTER_MASK) {
2181 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2182 ixgbe_vlan_hw_filter_enable(dev);
2184 ixgbe_vlan_hw_filter_disable(dev);
2187 if (mask & ETH_VLAN_EXTEND_MASK) {
2188 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2189 ixgbe_vlan_hw_extend_enable(dev);
2191 ixgbe_vlan_hw_extend_disable(dev);
2198 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2200 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2202 ixgbe_vlan_offload_config(dev, mask);
2208 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2210 struct ixgbe_hw *hw =
2211 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2212 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2213 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2215 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2216 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2220 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2222 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2227 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2230 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2236 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2237 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2238 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2239 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2244 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2246 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2247 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2248 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2249 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2251 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2252 /* check multi-queue mode */
2253 switch (dev_conf->rxmode.mq_mode) {
2254 case ETH_MQ_RX_VMDQ_DCB:
2255 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2257 case ETH_MQ_RX_VMDQ_DCB_RSS:
2258 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2259 PMD_INIT_LOG(ERR, "SRIOV active,"
2260 " unsupported mq_mode rx %d.",
2261 dev_conf->rxmode.mq_mode);
2264 case ETH_MQ_RX_VMDQ_RSS:
2265 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2266 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2267 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2268 PMD_INIT_LOG(ERR, "SRIOV is active,"
2269 " invalid queue number"
2270 " for VMDQ RSS, allowed"
2271 " value are 1, 2 or 4.");
2275 case ETH_MQ_RX_VMDQ_ONLY:
2276 case ETH_MQ_RX_NONE:
2277 /* if nothing mq mode configure, use default scheme */
2278 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2280 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2281 /* SRIOV only works in VMDq enable mode */
2282 PMD_INIT_LOG(ERR, "SRIOV is active,"
2283 " wrong mq_mode rx %d.",
2284 dev_conf->rxmode.mq_mode);
2288 switch (dev_conf->txmode.mq_mode) {
2289 case ETH_MQ_TX_VMDQ_DCB:
2290 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2291 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2293 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2294 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2298 /* check valid queue number */
2299 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2300 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2301 PMD_INIT_LOG(ERR, "SRIOV is active,"
2302 " nb_rx_q=%d nb_tx_q=%d queue number"
2303 " must be less than or equal to %d.",
2305 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2309 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2310 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2314 /* check configuration for vmdb+dcb mode */
2315 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2316 const struct rte_eth_vmdq_dcb_conf *conf;
2318 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2319 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2320 IXGBE_VMDQ_DCB_NB_QUEUES);
2323 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2324 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2325 conf->nb_queue_pools == ETH_32_POOLS)) {
2326 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2327 " nb_queue_pools must be %d or %d.",
2328 ETH_16_POOLS, ETH_32_POOLS);
2332 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2333 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2335 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2336 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2337 IXGBE_VMDQ_DCB_NB_QUEUES);
2340 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2341 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2342 conf->nb_queue_pools == ETH_32_POOLS)) {
2343 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2344 " nb_queue_pools != %d and"
2345 " nb_queue_pools != %d.",
2346 ETH_16_POOLS, ETH_32_POOLS);
2351 /* For DCB mode check our configuration before we go further */
2352 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2353 const struct rte_eth_dcb_rx_conf *conf;
2355 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2356 if (!(conf->nb_tcs == ETH_4_TCS ||
2357 conf->nb_tcs == ETH_8_TCS)) {
2358 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2359 " and nb_tcs != %d.",
2360 ETH_4_TCS, ETH_8_TCS);
2365 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2366 const struct rte_eth_dcb_tx_conf *conf;
2368 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2369 if (!(conf->nb_tcs == ETH_4_TCS ||
2370 conf->nb_tcs == ETH_8_TCS)) {
2371 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2372 " and nb_tcs != %d.",
2373 ETH_4_TCS, ETH_8_TCS);
2379 * When DCB/VT is off, maximum number of queues changes,
2380 * except for 82598EB, which remains constant.
2382 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2383 hw->mac.type != ixgbe_mac_82598EB) {
2384 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2386 "Neither VT nor DCB are enabled, "
2388 IXGBE_NONE_MODE_TX_NB_QUEUES);
2397 ixgbe_dev_configure(struct rte_eth_dev *dev)
2399 struct ixgbe_interrupt *intr =
2400 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2401 struct ixgbe_adapter *adapter = dev->data->dev_private;
2404 PMD_INIT_FUNC_TRACE();
2406 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2407 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2409 /* multipe queue mode checking */
2410 ret = ixgbe_check_mq_mode(dev);
2412 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2417 /* set flag to update link status after init */
2418 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2421 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2422 * allocation or vector Rx preconditions we will reset it.
2424 adapter->rx_bulk_alloc_allowed = true;
2425 adapter->rx_vec_allowed = true;
2431 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2433 struct ixgbe_hw *hw =
2434 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2435 struct ixgbe_interrupt *intr =
2436 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2439 /* only set up it on X550EM_X */
2440 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2441 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2442 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2443 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2444 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2445 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2450 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2451 uint16_t tx_rate, uint64_t q_msk)
2453 struct ixgbe_hw *hw;
2454 struct ixgbe_vf_info *vfinfo;
2455 struct rte_eth_link link;
2456 uint8_t nb_q_per_pool;
2457 uint32_t queue_stride;
2458 uint32_t queue_idx, idx = 0, vf_idx;
2460 uint16_t total_rate = 0;
2461 struct rte_pci_device *pci_dev;
2464 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2465 ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2469 if (vf >= pci_dev->max_vfs)
2472 if (tx_rate > link.link_speed)
2478 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2479 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2480 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2481 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2482 queue_idx = vf * queue_stride;
2483 queue_end = queue_idx + nb_q_per_pool - 1;
2484 if (queue_end >= hw->mac.max_tx_queues)
2488 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2491 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2493 total_rate += vfinfo[vf_idx].tx_rate[idx];
2499 /* Store tx_rate for this vf. */
2500 for (idx = 0; idx < nb_q_per_pool; idx++) {
2501 if (((uint64_t)0x1 << idx) & q_msk) {
2502 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2503 vfinfo[vf].tx_rate[idx] = tx_rate;
2504 total_rate += tx_rate;
2508 if (total_rate > dev->data->dev_link.link_speed) {
2509 /* Reset stored TX rate of the VF if it causes exceed
2512 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2516 /* Set RTTBCNRC of each queue/pool for vf X */
2517 for (; queue_idx <= queue_end; queue_idx++) {
2519 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2527 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2529 struct ixgbe_adapter *adapter = dev->data->dev_private;
2535 err = ixgbe_fc_enable(hw);
2537 /* Not negotiated is not an error case */
2538 if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2540 *check if we want to forward MAC frames - driver doesn't
2541 *have native capability to do that,
2542 *so we'll write the registers ourselves
2545 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2547 /* set or clear MFLCN.PMCF bit depending on configuration */
2548 if (adapter->mac_ctrl_frame_fwd != 0)
2549 mflcn |= IXGBE_MFLCN_PMCF;
2551 mflcn &= ~IXGBE_MFLCN_PMCF;
2553 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2554 IXGBE_WRITE_FLUSH(hw);
2562 * Configure device link speed and setup link.
2563 * It returns 0 on success.
2566 ixgbe_dev_start(struct rte_eth_dev *dev)
2568 struct ixgbe_hw *hw =
2569 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2570 struct ixgbe_vf_info *vfinfo =
2571 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2572 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2573 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2574 uint32_t intr_vector = 0;
2576 bool link_up = false, negotiate = 0;
2578 uint32_t allowed_speeds = 0;
2582 uint32_t *link_speeds;
2583 struct ixgbe_tm_conf *tm_conf =
2584 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2585 struct ixgbe_macsec_setting *macsec_setting =
2586 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2588 PMD_INIT_FUNC_TRACE();
2590 /* Stop the link setup handler before resetting the HW. */
2591 ixgbe_dev_wait_setup_link_complete(dev, 0);
2593 /* disable uio/vfio intr/eventfd mapping */
2594 rte_intr_disable(intr_handle);
2597 hw->adapter_stopped = 0;
2598 ixgbe_stop_adapter(hw);
2600 /* reinitialize adapter
2601 * this calls reset and start
2603 status = ixgbe_pf_reset_hw(hw);
2606 hw->mac.ops.start_hw(hw);
2607 hw->mac.get_link_status = true;
2609 /* configure PF module if SRIOV enabled */
2610 ixgbe_pf_host_configure(dev);
2612 ixgbe_dev_phy_intr_setup(dev);
2614 /* check and configure queue intr-vector mapping */
2615 if ((rte_intr_cap_multiple(intr_handle) ||
2616 !RTE_ETH_DEV_SRIOV(dev).active) &&
2617 dev->data->dev_conf.intr_conf.rxq != 0) {
2618 intr_vector = dev->data->nb_rx_queues;
2619 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2620 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2621 IXGBE_MAX_INTR_QUEUE_NUM);
2624 if (rte_intr_efd_enable(intr_handle, intr_vector))
2628 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2629 intr_handle->intr_vec =
2630 rte_zmalloc("intr_vec",
2631 dev->data->nb_rx_queues * sizeof(int), 0);
2632 if (intr_handle->intr_vec == NULL) {
2633 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2634 " intr_vec", dev->data->nb_rx_queues);
2639 /* confiugre msix for sleep until rx interrupt */
2640 ixgbe_configure_msix(dev);
2642 /* initialize transmission unit */
2643 ixgbe_dev_tx_init(dev);
2645 /* This can fail when allocating mbufs for descriptor rings */
2646 err = ixgbe_dev_rx_init(dev);
2648 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2652 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2653 ETH_VLAN_EXTEND_MASK;
2654 err = ixgbe_vlan_offload_config(dev, mask);
2656 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2660 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2661 /* Enable vlan filtering for VMDq */
2662 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2665 /* Configure DCB hw */
2666 ixgbe_configure_dcb(dev);
2668 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2669 err = ixgbe_fdir_configure(dev);
2674 /* Restore vf rate limit */
2675 if (vfinfo != NULL) {
2676 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2677 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2678 if (vfinfo[vf].tx_rate[idx] != 0)
2679 ixgbe_set_vf_rate_limit(
2681 vfinfo[vf].tx_rate[idx],
2685 ixgbe_restore_statistics_mapping(dev);
2687 err = ixgbe_flow_ctrl_enable(dev, hw);
2689 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2693 err = ixgbe_dev_rxtx_start(dev);
2695 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2699 /* Skip link setup if loopback mode is enabled. */
2700 if (dev->data->dev_conf.lpbk_mode != 0) {
2701 err = ixgbe_check_supported_loopback_mode(dev);
2703 PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2706 goto skip_link_setup;
2710 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2711 err = hw->mac.ops.setup_sfp(hw);
2716 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2717 /* Turn on the copper */
2718 ixgbe_set_phy_power(hw, true);
2720 /* Turn on the laser */
2721 ixgbe_enable_tx_laser(hw);
2724 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2727 dev->data->dev_link.link_status = link_up;
2729 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2733 switch (hw->mac.type) {
2734 case ixgbe_mac_X550:
2735 case ixgbe_mac_X550EM_x:
2736 case ixgbe_mac_X550EM_a:
2737 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2738 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G |
2740 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2741 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2742 allowed_speeds = ETH_LINK_SPEED_10M |
2743 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2746 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2750 link_speeds = &dev->data->dev_conf.link_speeds;
2752 /* Ignore autoneg flag bit and check the validity ofÂ
2755 if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2756 PMD_INIT_LOG(ERR, "Invalid link setting");
2761 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2762 switch (hw->mac.type) {
2763 case ixgbe_mac_82598EB:
2764 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2766 case ixgbe_mac_82599EB:
2767 case ixgbe_mac_X540:
2768 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2770 case ixgbe_mac_X550:
2771 case ixgbe_mac_X550EM_x:
2772 case ixgbe_mac_X550EM_a:
2773 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2776 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2779 if (*link_speeds & ETH_LINK_SPEED_10G)
2780 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2781 if (*link_speeds & ETH_LINK_SPEED_5G)
2782 speed |= IXGBE_LINK_SPEED_5GB_FULL;
2783 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2784 speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2785 if (*link_speeds & ETH_LINK_SPEED_1G)
2786 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2787 if (*link_speeds & ETH_LINK_SPEED_100M)
2788 speed |= IXGBE_LINK_SPEED_100_FULL;
2789 if (*link_speeds & ETH_LINK_SPEED_10M)
2790 speed |= IXGBE_LINK_SPEED_10_FULL;
2793 err = ixgbe_setup_link(hw, speed, link_up);
2799 if (rte_intr_allow_others(intr_handle)) {
2800 /* check if lsc interrupt is enabled */
2801 if (dev->data->dev_conf.intr_conf.lsc != 0)
2802 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2804 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2805 ixgbe_dev_macsec_interrupt_setup(dev);
2807 rte_intr_callback_unregister(intr_handle,
2808 ixgbe_dev_interrupt_handler, dev);
2809 if (dev->data->dev_conf.intr_conf.lsc != 0)
2810 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2811 " no intr multiplex");
2814 /* check if rxq interrupt is enabled */
2815 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2816 rte_intr_dp_is_en(intr_handle))
2817 ixgbe_dev_rxq_interrupt_setup(dev);
2819 /* enable uio/vfio intr/eventfd mapping */
2820 rte_intr_enable(intr_handle);
2822 /* resume enabled intr since hw reset */
2823 ixgbe_enable_intr(dev);
2824 ixgbe_l2_tunnel_conf(dev);
2825 ixgbe_filter_restore(dev);
2827 if (tm_conf->root && !tm_conf->committed)
2828 PMD_DRV_LOG(WARNING,
2829 "please call hierarchy_commit() "
2830 "before starting the port");
2832 /* wait for the controller to acquire link */
2833 err = ixgbe_wait_for_link_up(hw);
2838 * Update link status right before return, because it may
2839 * start link configuration process in a separate thread.
2841 ixgbe_dev_link_update(dev, 0);
2843 /* setup the macsec setting register */
2844 if (macsec_setting->offload_en)
2845 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2850 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2851 ixgbe_dev_clear_queues(dev);
2856 * Stop device: disable rx and tx functions to allow for reconfiguring.
2859 ixgbe_dev_stop(struct rte_eth_dev *dev)
2861 struct rte_eth_link link;
2862 struct ixgbe_adapter *adapter = dev->data->dev_private;
2863 struct ixgbe_hw *hw =
2864 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2865 struct ixgbe_vf_info *vfinfo =
2866 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2867 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2868 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2870 struct ixgbe_tm_conf *tm_conf =
2871 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2873 if (hw->adapter_stopped)
2876 PMD_INIT_FUNC_TRACE();
2878 ixgbe_dev_wait_setup_link_complete(dev, 0);
2880 /* disable interrupts */
2881 ixgbe_disable_intr(hw);
2884 ixgbe_pf_reset_hw(hw);
2885 hw->adapter_stopped = 0;
2888 ixgbe_stop_adapter(hw);
2890 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2891 vfinfo[vf].clear_to_send = false;
2893 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2894 /* Turn off the copper */
2895 ixgbe_set_phy_power(hw, false);
2897 /* Turn off the laser */
2898 ixgbe_disable_tx_laser(hw);
2901 ixgbe_dev_clear_queues(dev);
2903 /* Clear stored conf */
2904 dev->data->scattered_rx = 0;
2907 /* Clear recorded link status */
2908 memset(&link, 0, sizeof(link));
2909 rte_eth_linkstatus_set(dev, &link);
2911 if (!rte_intr_allow_others(intr_handle))
2912 /* resume to the default handler */
2913 rte_intr_callback_register(intr_handle,
2914 ixgbe_dev_interrupt_handler,
2917 /* Clean datapath event and queue/vec mapping */
2918 rte_intr_efd_disable(intr_handle);
2919 if (intr_handle->intr_vec != NULL) {
2920 rte_free(intr_handle->intr_vec);
2921 intr_handle->intr_vec = NULL;
2924 /* reset hierarchy commit */
2925 tm_conf->committed = false;
2927 adapter->rss_reta_updated = 0;
2929 hw->adapter_stopped = true;
2933 * Set device link up: enable tx.
2936 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2938 struct ixgbe_hw *hw =
2939 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2940 if (hw->mac.type == ixgbe_mac_82599EB) {
2941 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2942 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2943 /* Not suported in bypass mode */
2944 PMD_INIT_LOG(ERR, "Set link up is not supported "
2945 "by device id 0x%x", hw->device_id);
2951 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2952 /* Turn on the copper */
2953 ixgbe_set_phy_power(hw, true);
2955 /* Turn on the laser */
2956 ixgbe_enable_tx_laser(hw);
2957 ixgbe_dev_link_update(dev, 0);
2964 * Set device link down: disable tx.
2967 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2969 struct ixgbe_hw *hw =
2970 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2971 if (hw->mac.type == ixgbe_mac_82599EB) {
2972 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2973 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2974 /* Not suported in bypass mode */
2975 PMD_INIT_LOG(ERR, "Set link down is not supported "
2976 "by device id 0x%x", hw->device_id);
2982 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2983 /* Turn off the copper */
2984 ixgbe_set_phy_power(hw, false);
2986 /* Turn off the laser */
2987 ixgbe_disable_tx_laser(hw);
2988 ixgbe_dev_link_update(dev, 0);
2995 * Reset and stop device.
2998 ixgbe_dev_close(struct rte_eth_dev *dev)
3000 struct ixgbe_hw *hw =
3001 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3002 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3003 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3007 PMD_INIT_FUNC_TRACE();
3009 ixgbe_pf_reset_hw(hw);
3011 ixgbe_dev_stop(dev);
3013 ixgbe_dev_free_queues(dev);
3015 ixgbe_disable_pcie_master(hw);
3017 /* reprogram the RAR[0] in case user changed it. */
3018 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3020 dev->dev_ops = NULL;
3021 dev->rx_pkt_burst = NULL;
3022 dev->tx_pkt_burst = NULL;
3024 /* Unlock any pending hardware semaphore */
3025 ixgbe_swfw_lock_reset(hw);
3027 /* disable uio intr before callback unregister */
3028 rte_intr_disable(intr_handle);
3031 ret = rte_intr_callback_unregister(intr_handle,
3032 ixgbe_dev_interrupt_handler, dev);
3033 if (ret >= 0 || ret == -ENOENT) {
3035 } else if (ret != -EAGAIN) {
3037 "intr callback unregister failed: %d",
3041 } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3043 /* cancel the delay handler before remove dev */
3044 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3046 /* uninitialize PF if max_vfs not zero */
3047 ixgbe_pf_host_uninit(dev);
3049 /* remove all the fdir filters & hash */
3050 ixgbe_fdir_filter_uninit(dev);
3052 /* remove all the L2 tunnel filters & hash */
3053 ixgbe_l2_tn_filter_uninit(dev);
3055 /* Remove all ntuple filters of the device */
3056 ixgbe_ntuple_filter_uninit(dev);
3058 /* clear all the filters list */
3059 ixgbe_filterlist_flush();
3061 /* Remove all Traffic Manager configuration */
3062 ixgbe_tm_conf_uninit(dev);
3064 #ifdef RTE_LIBRTE_SECURITY
3065 rte_free(dev->security_ctx);
3074 ixgbe_dev_reset(struct rte_eth_dev *dev)
3078 /* When a DPDK PMD PF begin to reset PF port, it should notify all
3079 * its VF to make them align with it. The detailed notification
3080 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3081 * To avoid unexpected behavior in VF, currently reset of PF with
3082 * SR-IOV activation is not supported. It might be supported later.
3084 if (dev->data->sriov.active)
3087 ret = eth_ixgbe_dev_uninit(dev);
3091 ret = eth_ixgbe_dev_init(dev, NULL);
3097 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3098 struct ixgbe_hw_stats *hw_stats,
3099 struct ixgbe_macsec_stats *macsec_stats,
3100 uint64_t *total_missed_rx, uint64_t *total_qbrc,
3101 uint64_t *total_qprc, uint64_t *total_qprdc)
3103 uint32_t bprc, lxon, lxoff, total;
3104 uint32_t delta_gprc = 0;
3106 /* Workaround for RX byte count not including CRC bytes when CRC
3107 * strip is enabled. CRC bytes are removed from counters when crc_strip
3110 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3111 IXGBE_HLREG0_RXCRCSTRP);
3113 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3114 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3115 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3116 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3118 for (i = 0; i < 8; i++) {
3119 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3121 /* global total per queue */
3122 hw_stats->mpc[i] += mp;
3123 /* Running comprehensive total for stats display */
3124 *total_missed_rx += hw_stats->mpc[i];
3125 if (hw->mac.type == ixgbe_mac_82598EB) {
3126 hw_stats->rnbc[i] +=
3127 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3128 hw_stats->pxonrxc[i] +=
3129 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3130 hw_stats->pxoffrxc[i] +=
3131 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3133 hw_stats->pxonrxc[i] +=
3134 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3135 hw_stats->pxoffrxc[i] +=
3136 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3137 hw_stats->pxon2offc[i] +=
3138 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3140 hw_stats->pxontxc[i] +=
3141 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3142 hw_stats->pxofftxc[i] +=
3143 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3145 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3146 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3147 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3148 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3150 delta_gprc += delta_qprc;
3152 hw_stats->qprc[i] += delta_qprc;
3153 hw_stats->qptc[i] += delta_qptc;
3155 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3156 hw_stats->qbrc[i] +=
3157 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3159 hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3161 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3162 hw_stats->qbtc[i] +=
3163 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3165 hw_stats->qprdc[i] += delta_qprdc;
3166 *total_qprdc += hw_stats->qprdc[i];
3168 *total_qprc += hw_stats->qprc[i];
3169 *total_qbrc += hw_stats->qbrc[i];
3171 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3172 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3173 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3176 * An errata states that gprc actually counts good + missed packets:
3177 * Workaround to set gprc to summated queue packet receives
3179 hw_stats->gprc = *total_qprc;
3181 if (hw->mac.type != ixgbe_mac_82598EB) {
3182 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3183 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3184 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3185 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3186 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3187 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3188 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3189 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3191 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3192 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3193 /* 82598 only has a counter in the high register */
3194 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3195 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3196 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3198 uint64_t old_tpr = hw_stats->tpr;
3200 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3201 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3204 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3206 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3207 hw_stats->gptc += delta_gptc;
3208 hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3209 hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3212 * Workaround: mprc hardware is incorrectly counting
3213 * broadcasts, so for now we subtract those.
3215 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3216 hw_stats->bprc += bprc;
3217 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3218 if (hw->mac.type == ixgbe_mac_82598EB)
3219 hw_stats->mprc -= bprc;
3221 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3222 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3223 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3224 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3225 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3226 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3228 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3229 hw_stats->lxontxc += lxon;
3230 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3231 hw_stats->lxofftxc += lxoff;
3232 total = lxon + lxoff;
3234 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3235 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3236 hw_stats->gptc -= total;
3237 hw_stats->mptc -= total;
3238 hw_stats->ptc64 -= total;
3239 hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3241 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3242 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3243 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3244 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3245 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3246 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3247 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3248 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3249 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3250 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3251 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3252 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3253 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3254 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3255 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3256 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3257 /* Only read FCOE on 82599 */
3258 if (hw->mac.type != ixgbe_mac_82598EB) {
3259 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3260 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3261 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3262 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3263 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3266 /* Flow Director Stats registers */
3267 if (hw->mac.type != ixgbe_mac_82598EB) {
3268 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3269 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3270 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3271 IXGBE_FDIRUSTAT) & 0xFFFF;
3272 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3273 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3274 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3275 IXGBE_FDIRFSTAT) & 0xFFFF;
3276 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3277 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3279 /* MACsec Stats registers */
3280 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3281 macsec_stats->out_pkts_encrypted +=
3282 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3283 macsec_stats->out_pkts_protected +=
3284 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3285 macsec_stats->out_octets_encrypted +=
3286 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3287 macsec_stats->out_octets_protected +=
3288 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3289 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3290 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3291 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3292 macsec_stats->in_pkts_unknownsci +=
3293 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3294 macsec_stats->in_octets_decrypted +=
3295 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3296 macsec_stats->in_octets_validated +=
3297 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3298 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3299 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3300 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3301 for (i = 0; i < 2; i++) {
3302 macsec_stats->in_pkts_ok +=
3303 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3304 macsec_stats->in_pkts_invalid +=
3305 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3306 macsec_stats->in_pkts_notvalid +=
3307 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3309 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3310 macsec_stats->in_pkts_notusingsa +=
3311 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3315 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3318 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3320 struct ixgbe_hw *hw =
3321 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3322 struct ixgbe_hw_stats *hw_stats =
3323 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3324 struct ixgbe_macsec_stats *macsec_stats =
3325 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3326 dev->data->dev_private);
3327 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3330 total_missed_rx = 0;
3335 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3336 &total_qbrc, &total_qprc, &total_qprdc);
3341 /* Fill out the rte_eth_stats statistics structure */
3342 stats->ipackets = total_qprc;
3343 stats->ibytes = total_qbrc;
3344 stats->opackets = hw_stats->gptc;
3345 stats->obytes = hw_stats->gotc;
3347 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3348 stats->q_ipackets[i] = hw_stats->qprc[i];
3349 stats->q_opackets[i] = hw_stats->qptc[i];
3350 stats->q_ibytes[i] = hw_stats->qbrc[i];
3351 stats->q_obytes[i] = hw_stats->qbtc[i];
3352 stats->q_errors[i] = hw_stats->qprdc[i];
3356 stats->imissed = total_missed_rx;
3357 stats->ierrors = hw_stats->crcerrs +
3374 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3376 struct ixgbe_hw_stats *stats =
3377 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3379 /* HW registers are cleared on read */
3380 ixgbe_dev_stats_get(dev, NULL);
3382 /* Reset software totals */
3383 memset(stats, 0, sizeof(*stats));
3388 /* This function calculates the number of xstats based on the current config */
3390 ixgbe_xstats_calc_num(void) {
3391 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3392 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3393 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3396 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3397 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3399 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3400 unsigned stat, i, count;
3402 if (xstats_names != NULL) {
3405 /* Note: limit >= cnt_stats checked upstream
3406 * in rte_eth_xstats_names()
3409 /* Extended stats from ixgbe_hw_stats */
3410 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3411 strlcpy(xstats_names[count].name,
3412 rte_ixgbe_stats_strings[i].name,
3413 sizeof(xstats_names[count].name));
3418 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3419 strlcpy(xstats_names[count].name,
3420 rte_ixgbe_macsec_strings[i].name,
3421 sizeof(xstats_names[count].name));
3425 /* RX Priority Stats */
3426 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3427 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3428 snprintf(xstats_names[count].name,
3429 sizeof(xstats_names[count].name),
3430 "rx_priority%u_%s", i,
3431 rte_ixgbe_rxq_strings[stat].name);
3436 /* TX Priority Stats */
3437 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3438 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3439 snprintf(xstats_names[count].name,
3440 sizeof(xstats_names[count].name),
3441 "tx_priority%u_%s", i,
3442 rte_ixgbe_txq_strings[stat].name);
3450 static int ixgbe_dev_xstats_get_names_by_id(
3451 struct rte_eth_dev *dev,
3452 struct rte_eth_xstat_name *xstats_names,
3453 const uint64_t *ids,
3457 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3458 unsigned int stat, i, count;
3460 if (xstats_names != NULL) {
3463 /* Note: limit >= cnt_stats checked upstream
3464 * in rte_eth_xstats_names()
3467 /* Extended stats from ixgbe_hw_stats */
3468 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3469 strlcpy(xstats_names[count].name,
3470 rte_ixgbe_stats_strings[i].name,
3471 sizeof(xstats_names[count].name));
3476 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3477 strlcpy(xstats_names[count].name,
3478 rte_ixgbe_macsec_strings[i].name,
3479 sizeof(xstats_names[count].name));
3483 /* RX Priority Stats */
3484 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3485 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3486 snprintf(xstats_names[count].name,
3487 sizeof(xstats_names[count].name),
3488 "rx_priority%u_%s", i,
3489 rte_ixgbe_rxq_strings[stat].name);
3494 /* TX Priority Stats */
3495 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3496 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3497 snprintf(xstats_names[count].name,
3498 sizeof(xstats_names[count].name),
3499 "tx_priority%u_%s", i,
3500 rte_ixgbe_txq_strings[stat].name);
3509 uint16_t size = ixgbe_xstats_calc_num();
3510 struct rte_eth_xstat_name xstats_names_copy[size];
3512 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3515 for (i = 0; i < limit; i++) {
3516 if (ids[i] >= size) {
3517 PMD_INIT_LOG(ERR, "id value isn't valid");
3520 strcpy(xstats_names[i].name,
3521 xstats_names_copy[ids[i]].name);
3526 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3527 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3531 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3534 if (xstats_names != NULL)
3535 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3536 strlcpy(xstats_names[i].name,
3537 rte_ixgbevf_stats_strings[i].name,
3538 sizeof(xstats_names[i].name));
3539 return IXGBEVF_NB_XSTATS;
3543 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3546 struct ixgbe_hw *hw =
3547 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3548 struct ixgbe_hw_stats *hw_stats =
3549 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3550 struct ixgbe_macsec_stats *macsec_stats =
3551 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3552 dev->data->dev_private);
3553 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3554 unsigned i, stat, count = 0;
3556 count = ixgbe_xstats_calc_num();
3561 total_missed_rx = 0;
3566 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3567 &total_qbrc, &total_qprc, &total_qprdc);
3569 /* If this is a reset xstats is NULL, and we have cleared the
3570 * registers by reading them.
3575 /* Extended stats from ixgbe_hw_stats */
3577 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3578 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3579 rte_ixgbe_stats_strings[i].offset);
3580 xstats[count].id = count;
3585 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3586 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3587 rte_ixgbe_macsec_strings[i].offset);
3588 xstats[count].id = count;
3592 /* RX Priority Stats */
3593 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3594 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3595 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3596 rte_ixgbe_rxq_strings[stat].offset +
3597 (sizeof(uint64_t) * i));
3598 xstats[count].id = count;
3603 /* TX Priority Stats */
3604 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3605 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3606 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3607 rte_ixgbe_txq_strings[stat].offset +
3608 (sizeof(uint64_t) * i));
3609 xstats[count].id = count;
3617 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3618 uint64_t *values, unsigned int n)
3621 struct ixgbe_hw *hw =
3622 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3623 struct ixgbe_hw_stats *hw_stats =
3624 IXGBE_DEV_PRIVATE_TO_STATS(
3625 dev->data->dev_private);
3626 struct ixgbe_macsec_stats *macsec_stats =
3627 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3628 dev->data->dev_private);
3629 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3630 unsigned int i, stat, count = 0;
3632 count = ixgbe_xstats_calc_num();
3634 if (!ids && n < count)
3637 total_missed_rx = 0;
3642 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3643 &total_missed_rx, &total_qbrc, &total_qprc,
3646 /* If this is a reset xstats is NULL, and we have cleared the
3647 * registers by reading them.
3649 if (!ids && !values)
3652 /* Extended stats from ixgbe_hw_stats */
3654 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3655 values[count] = *(uint64_t *)(((char *)hw_stats) +
3656 rte_ixgbe_stats_strings[i].offset);
3661 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3662 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3663 rte_ixgbe_macsec_strings[i].offset);
3667 /* RX Priority Stats */
3668 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3669 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3671 *(uint64_t *)(((char *)hw_stats) +
3672 rte_ixgbe_rxq_strings[stat].offset +
3673 (sizeof(uint64_t) * i));
3678 /* TX Priority Stats */
3679 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3680 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3682 *(uint64_t *)(((char *)hw_stats) +
3683 rte_ixgbe_txq_strings[stat].offset +
3684 (sizeof(uint64_t) * i));
3692 uint16_t size = ixgbe_xstats_calc_num();
3693 uint64_t values_copy[size];
3695 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3697 for (i = 0; i < n; i++) {
3698 if (ids[i] >= size) {
3699 PMD_INIT_LOG(ERR, "id value isn't valid");
3702 values[i] = values_copy[ids[i]];
3708 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3710 struct ixgbe_hw_stats *stats =
3711 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3712 struct ixgbe_macsec_stats *macsec_stats =
3713 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3714 dev->data->dev_private);
3716 unsigned count = ixgbe_xstats_calc_num();
3718 /* HW registers are cleared on read */
3719 ixgbe_dev_xstats_get(dev, NULL, count);
3721 /* Reset software totals */
3722 memset(stats, 0, sizeof(*stats));
3723 memset(macsec_stats, 0, sizeof(*macsec_stats));
3729 ixgbevf_update_stats(struct rte_eth_dev *dev)
3731 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3732 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3733 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3735 /* Good Rx packet, include VF loopback */
3736 UPDATE_VF_STAT(IXGBE_VFGPRC,
3737 hw_stats->last_vfgprc, hw_stats->vfgprc);
3739 /* Good Rx octets, include VF loopback */
3740 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3741 hw_stats->last_vfgorc, hw_stats->vfgorc);
3743 /* Good Tx packet, include VF loopback */
3744 UPDATE_VF_STAT(IXGBE_VFGPTC,
3745 hw_stats->last_vfgptc, hw_stats->vfgptc);
3747 /* Good Tx octets, include VF loopback */
3748 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3749 hw_stats->last_vfgotc, hw_stats->vfgotc);
3751 /* Rx Multicst Packet */
3752 UPDATE_VF_STAT(IXGBE_VFMPRC,
3753 hw_stats->last_vfmprc, hw_stats->vfmprc);
3757 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3760 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3761 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3764 if (n < IXGBEVF_NB_XSTATS)
3765 return IXGBEVF_NB_XSTATS;
3767 ixgbevf_update_stats(dev);
3772 /* Extended stats */
3773 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3775 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3776 rte_ixgbevf_stats_strings[i].offset);
3779 return IXGBEVF_NB_XSTATS;
3783 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3785 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3786 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3788 ixgbevf_update_stats(dev);
3793 stats->ipackets = hw_stats->vfgprc;
3794 stats->ibytes = hw_stats->vfgorc;
3795 stats->opackets = hw_stats->vfgptc;
3796 stats->obytes = hw_stats->vfgotc;
3801 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3803 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3804 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3806 /* Sync HW register to the last stats */
3807 ixgbevf_dev_stats_get(dev, NULL);
3809 /* reset HW current stats*/
3810 hw_stats->vfgprc = 0;
3811 hw_stats->vfgorc = 0;
3812 hw_stats->vfgptc = 0;
3813 hw_stats->vfgotc = 0;
3819 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3821 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3822 u16 eeprom_verh, eeprom_verl;
3826 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3827 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3829 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3830 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3832 ret += 1; /* add the size of '\0' */
3833 if (fw_size < (u32)ret)
3840 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3842 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3843 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3844 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3846 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3847 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3848 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3850 * When DCB/VT is off, maximum number of queues changes,
3851 * except for 82598EB, which remains constant.
3853 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3854 hw->mac.type != ixgbe_mac_82598EB)
3855 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3857 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3858 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3859 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3860 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3861 dev_info->max_vfs = pci_dev->max_vfs;
3862 if (hw->mac.type == ixgbe_mac_82598EB)
3863 dev_info->max_vmdq_pools = ETH_16_POOLS;
3865 dev_info->max_vmdq_pools = ETH_64_POOLS;
3866 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3867 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3868 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3869 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3870 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3871 dev_info->rx_queue_offload_capa);
3872 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3873 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3875 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3877 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3878 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3879 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3881 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3886 dev_info->default_txconf = (struct rte_eth_txconf) {
3888 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3889 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3890 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3892 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3893 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3897 dev_info->rx_desc_lim = rx_desc_lim;
3898 dev_info->tx_desc_lim = tx_desc_lim;
3900 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3901 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3902 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3904 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3905 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3906 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3907 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3908 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3910 if (hw->mac.type == ixgbe_mac_X540 ||
3911 hw->mac.type == ixgbe_mac_X540_vf ||
3912 hw->mac.type == ixgbe_mac_X550 ||
3913 hw->mac.type == ixgbe_mac_X550_vf) {
3914 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3916 if (hw->mac.type == ixgbe_mac_X550) {
3917 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3918 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3921 /* Driver-preferred Rx/Tx parameters */
3922 dev_info->default_rxportconf.burst_size = 32;
3923 dev_info->default_txportconf.burst_size = 32;
3924 dev_info->default_rxportconf.nb_queues = 1;
3925 dev_info->default_txportconf.nb_queues = 1;
3926 dev_info->default_rxportconf.ring_size = 256;
3927 dev_info->default_txportconf.ring_size = 256;
3932 static const uint32_t *
3933 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3935 static const uint32_t ptypes[] = {
3936 /* For non-vec functions,
3937 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3938 * for vec functions,
3939 * refers to _recv_raw_pkts_vec().
3943 RTE_PTYPE_L3_IPV4_EXT,
3945 RTE_PTYPE_L3_IPV6_EXT,
3949 RTE_PTYPE_TUNNEL_IP,
3950 RTE_PTYPE_INNER_L3_IPV6,
3951 RTE_PTYPE_INNER_L3_IPV6_EXT,
3952 RTE_PTYPE_INNER_L4_TCP,
3953 RTE_PTYPE_INNER_L4_UDP,
3957 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3958 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3959 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3960 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3963 #if defined(RTE_ARCH_X86) || defined(RTE_MACHINE_CPUFLAG_NEON)
3964 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3965 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3972 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3973 struct rte_eth_dev_info *dev_info)
3975 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3976 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3978 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3979 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3980 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3981 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3982 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3983 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3984 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3985 dev_info->max_vfs = pci_dev->max_vfs;
3986 if (hw->mac.type == ixgbe_mac_82598EB)
3987 dev_info->max_vmdq_pools = ETH_16_POOLS;
3989 dev_info->max_vmdq_pools = ETH_64_POOLS;
3990 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3991 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3992 dev_info->rx_queue_offload_capa);
3993 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3994 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3995 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3996 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3997 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3999 dev_info->default_rxconf = (struct rte_eth_rxconf) {
4001 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
4002 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
4003 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
4005 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
4010 dev_info->default_txconf = (struct rte_eth_txconf) {
4012 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
4013 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
4014 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
4016 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
4017 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4021 dev_info->rx_desc_lim = rx_desc_lim;
4022 dev_info->tx_desc_lim = tx_desc_lim;
4028 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4029 bool *link_up, int wait_to_complete)
4031 struct ixgbe_adapter *adapter = container_of(hw,
4032 struct ixgbe_adapter, hw);
4033 struct ixgbe_mbx_info *mbx = &hw->mbx;
4034 struct ixgbe_mac_info *mac = &hw->mac;
4035 uint32_t links_reg, in_msg;
4038 /* If we were hit with a reset drop the link */
4039 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4040 mac->get_link_status = true;
4042 if (!mac->get_link_status)
4045 /* if link status is down no point in checking to see if pf is up */
4046 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4047 if (!(links_reg & IXGBE_LINKS_UP))
4050 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4051 * before the link status is correct
4053 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4056 for (i = 0; i < 5; i++) {
4058 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4060 if (!(links_reg & IXGBE_LINKS_UP))
4065 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4066 case IXGBE_LINKS_SPEED_10G_82599:
4067 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4068 if (hw->mac.type >= ixgbe_mac_X550) {
4069 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4070 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4073 case IXGBE_LINKS_SPEED_1G_82599:
4074 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4076 case IXGBE_LINKS_SPEED_100_82599:
4077 *speed = IXGBE_LINK_SPEED_100_FULL;
4078 if (hw->mac.type == ixgbe_mac_X550) {
4079 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4080 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4083 case IXGBE_LINKS_SPEED_10_X550EM_A:
4084 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4085 /* Since Reserved in older MAC's */
4086 if (hw->mac.type >= ixgbe_mac_X550)
4087 *speed = IXGBE_LINK_SPEED_10_FULL;
4090 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4093 if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4094 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4095 mac->get_link_status = true;
4097 mac->get_link_status = false;
4102 /* if the read failed it could just be a mailbox collision, best wait
4103 * until we are called again and don't report an error
4105 if (mbx->ops.read(hw, &in_msg, 1, 0))
4108 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4109 /* msg is not CTS and is NACK we must have lost CTS status */
4110 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4111 mac->get_link_status = false;
4115 /* the pf is talking, if we timed out in the past we reinit */
4116 if (!mbx->timeout) {
4121 /* if we passed all the tests above then the link is up and we no
4122 * longer need to check for link
4124 mac->get_link_status = false;
4127 *link_up = !mac->get_link_status;
4132 * If @timeout_ms was 0, it means that it will not return until link complete.
4133 * It returns 1 on complete, return 0 on timeout.
4136 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4138 #define WARNING_TIMEOUT 9000 /* 9s in total */
4139 struct ixgbe_adapter *ad = dev->data->dev_private;
4140 uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4142 while (rte_atomic32_read(&ad->link_thread_running)) {
4149 } else if (!timeout) {
4150 /* It will not return until link complete */
4151 timeout = WARNING_TIMEOUT;
4152 PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4160 ixgbe_dev_setup_link_thread_handler(void *param)
4162 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4163 struct ixgbe_adapter *ad = dev->data->dev_private;
4164 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4165 struct ixgbe_interrupt *intr =
4166 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4168 bool autoneg = false;
4170 pthread_detach(pthread_self());
4171 speed = hw->phy.autoneg_advertised;
4173 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4175 ixgbe_setup_link(hw, speed, true);
4177 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4178 rte_atomic32_clear(&ad->link_thread_running);
4183 * In freebsd environment, nic_uio drivers do not support interrupts,
4184 * rte_intr_callback_register() will fail to register interrupts.
4185 * We can not make link status to change from down to up by interrupt
4186 * callback. So we need to wait for the controller to acquire link
4188 * It returns 0 on link up.
4191 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4193 #ifdef RTE_EXEC_ENV_FREEBSD
4195 bool link_up = false;
4197 const int nb_iter = 25;
4199 for (i = 0; i < nb_iter; i++) {
4200 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4215 /* return 0 means link status changed, -1 means not changed */
4217 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4218 int wait_to_complete, int vf)
4220 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4221 struct ixgbe_adapter *ad = dev->data->dev_private;
4222 struct rte_eth_link link;
4223 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4224 struct ixgbe_interrupt *intr =
4225 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4231 memset(&link, 0, sizeof(link));
4232 link.link_status = ETH_LINK_DOWN;
4233 link.link_speed = ETH_SPEED_NUM_NONE;
4234 link.link_duplex = ETH_LINK_HALF_DUPLEX;
4235 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4236 ETH_LINK_SPEED_FIXED);
4238 hw->mac.get_link_status = true;
4240 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4241 return rte_eth_linkstatus_set(dev, &link);
4243 /* check if it needs to wait to complete, if lsc interrupt is enabled */
4244 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4247 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4248 #ifdef RTE_EXEC_ENV_FREEBSD
4253 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4255 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4258 link.link_speed = ETH_SPEED_NUM_100M;
4259 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4260 return rte_eth_linkstatus_set(dev, &link);
4263 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4264 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4265 if ((esdp_reg & IXGBE_ESDP_SDP3))
4270 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4271 ixgbe_dev_wait_setup_link_complete(dev, 0);
4272 if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4273 /* To avoid race condition between threads, set
4274 * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4275 * when there is no link thread running.
4277 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4278 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4279 "ixgbe-link-handler",
4281 ixgbe_dev_setup_link_thread_handler,
4284 "Create link thread failed!");
4285 rte_atomic32_clear(&ad->link_thread_running);
4289 "Other link thread is running now!");
4292 return rte_eth_linkstatus_set(dev, &link);
4295 link.link_status = ETH_LINK_UP;
4296 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4298 switch (link_speed) {
4300 case IXGBE_LINK_SPEED_UNKNOWN:
4301 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
4304 case IXGBE_LINK_SPEED_10_FULL:
4305 link.link_speed = ETH_SPEED_NUM_10M;
4308 case IXGBE_LINK_SPEED_100_FULL:
4309 link.link_speed = ETH_SPEED_NUM_100M;
4312 case IXGBE_LINK_SPEED_1GB_FULL:
4313 link.link_speed = ETH_SPEED_NUM_1G;
4316 case IXGBE_LINK_SPEED_2_5GB_FULL:
4317 link.link_speed = ETH_SPEED_NUM_2_5G;
4320 case IXGBE_LINK_SPEED_5GB_FULL:
4321 link.link_speed = ETH_SPEED_NUM_5G;
4324 case IXGBE_LINK_SPEED_10GB_FULL:
4325 link.link_speed = ETH_SPEED_NUM_10G;
4329 return rte_eth_linkstatus_set(dev, &link);
4333 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4335 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4339 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4341 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4345 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4347 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4350 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4351 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4352 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4358 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4360 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4363 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4364 fctrl &= (~IXGBE_FCTRL_UPE);
4365 if (dev->data->all_multicast == 1)
4366 fctrl |= IXGBE_FCTRL_MPE;
4368 fctrl &= (~IXGBE_FCTRL_MPE);
4369 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4375 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4377 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4380 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4381 fctrl |= IXGBE_FCTRL_MPE;
4382 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4388 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4390 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4393 if (dev->data->promiscuous == 1)
4394 return 0; /* must remain in all_multicast mode */
4396 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4397 fctrl &= (~IXGBE_FCTRL_MPE);
4398 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4404 * It clears the interrupt causes and enables the interrupt.
4405 * It will be called once only during nic initialized.
4408 * Pointer to struct rte_eth_dev.
4410 * Enable or Disable.
4413 * - On success, zero.
4414 * - On failure, a negative value.
4417 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4419 struct ixgbe_interrupt *intr =
4420 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4422 ixgbe_dev_link_status_print(dev);
4424 intr->mask |= IXGBE_EICR_LSC;
4426 intr->mask &= ~IXGBE_EICR_LSC;
4432 * It clears the interrupt causes and enables the interrupt.
4433 * It will be called once only during nic initialized.
4436 * Pointer to struct rte_eth_dev.
4439 * - On success, zero.
4440 * - On failure, a negative value.
4443 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4445 struct ixgbe_interrupt *intr =
4446 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4448 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4454 * It clears the interrupt causes and enables the interrupt.
4455 * It will be called once only during nic initialized.
4458 * Pointer to struct rte_eth_dev.
4461 * - On success, zero.
4462 * - On failure, a negative value.
4465 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4467 struct ixgbe_interrupt *intr =
4468 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4470 intr->mask |= IXGBE_EICR_LINKSEC;
4476 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4479 * Pointer to struct rte_eth_dev.
4482 * - On success, zero.
4483 * - On failure, a negative value.
4486 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4489 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4490 struct ixgbe_interrupt *intr =
4491 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4493 /* clear all cause mask */
4494 ixgbe_disable_intr(hw);
4496 /* read-on-clear nic registers here */
4497 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4498 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4502 /* set flag for async link update */
4503 if (eicr & IXGBE_EICR_LSC)
4504 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4506 if (eicr & IXGBE_EICR_MAILBOX)
4507 intr->flags |= IXGBE_FLAG_MAILBOX;
4509 if (eicr & IXGBE_EICR_LINKSEC)
4510 intr->flags |= IXGBE_FLAG_MACSEC;
4512 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4513 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4514 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4515 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4521 * It gets and then prints the link status.
4524 * Pointer to struct rte_eth_dev.
4527 * - On success, zero.
4528 * - On failure, a negative value.
4531 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4533 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4534 struct rte_eth_link link;
4536 rte_eth_linkstatus_get(dev, &link);
4538 if (link.link_status) {
4539 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4540 (int)(dev->data->port_id),
4541 (unsigned)link.link_speed,
4542 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4543 "full-duplex" : "half-duplex");
4545 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4546 (int)(dev->data->port_id));
4548 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4549 pci_dev->addr.domain,
4551 pci_dev->addr.devid,
4552 pci_dev->addr.function);
4556 * It executes link_update after knowing an interrupt occurred.
4559 * Pointer to struct rte_eth_dev.
4562 * - On success, zero.
4563 * - On failure, a negative value.
4566 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4568 struct ixgbe_interrupt *intr =
4569 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4571 struct ixgbe_hw *hw =
4572 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4574 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4576 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4577 ixgbe_pf_mbx_process(dev);
4578 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4581 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4582 ixgbe_handle_lasi(hw);
4583 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4586 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4587 struct rte_eth_link link;
4589 /* get the link status before link update, for predicting later */
4590 rte_eth_linkstatus_get(dev, &link);
4592 ixgbe_dev_link_update(dev, 0);
4595 if (!link.link_status)
4596 /* handle it 1 sec later, wait it being stable */
4597 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4598 /* likely to down */
4600 /* handle it 4 sec later, wait it being stable */
4601 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4603 ixgbe_dev_link_status_print(dev);
4604 if (rte_eal_alarm_set(timeout * 1000,
4605 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4606 PMD_DRV_LOG(ERR, "Error setting alarm");
4608 /* remember original mask */
4609 intr->mask_original = intr->mask;
4610 /* only disable lsc interrupt */
4611 intr->mask &= ~IXGBE_EIMS_LSC;
4615 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4616 ixgbe_enable_intr(dev);
4622 * Interrupt handler which shall be registered for alarm callback for delayed
4623 * handling specific interrupt to wait for the stable nic state. As the
4624 * NIC interrupt state is not stable for ixgbe after link is just down,
4625 * it needs to wait 4 seconds to get the stable status.
4628 * Pointer to interrupt handle.
4630 * The address of parameter (struct rte_eth_dev *) regsitered before.
4636 ixgbe_dev_interrupt_delayed_handler(void *param)
4638 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4639 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4640 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4641 struct ixgbe_interrupt *intr =
4642 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4643 struct ixgbe_hw *hw =
4644 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4647 ixgbe_disable_intr(hw);
4649 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4650 if (eicr & IXGBE_EICR_MAILBOX)
4651 ixgbe_pf_mbx_process(dev);
4653 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4654 ixgbe_handle_lasi(hw);
4655 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4658 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4659 ixgbe_dev_link_update(dev, 0);
4660 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4661 ixgbe_dev_link_status_print(dev);
4662 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4666 if (intr->flags & IXGBE_FLAG_MACSEC) {
4667 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4669 intr->flags &= ~IXGBE_FLAG_MACSEC;
4672 /* restore original mask */
4673 intr->mask = intr->mask_original;
4674 intr->mask_original = 0;
4676 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4677 ixgbe_enable_intr(dev);
4678 rte_intr_ack(intr_handle);
4682 * Interrupt handler triggered by NIC for handling
4683 * specific interrupt.
4686 * Pointer to interrupt handle.
4688 * The address of parameter (struct rte_eth_dev *) regsitered before.
4694 ixgbe_dev_interrupt_handler(void *param)
4696 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4698 ixgbe_dev_interrupt_get_status(dev);
4699 ixgbe_dev_interrupt_action(dev);
4703 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4705 struct ixgbe_hw *hw;
4707 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4708 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4712 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4714 struct ixgbe_hw *hw;
4716 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4717 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4721 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4723 struct ixgbe_hw *hw;
4729 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4731 fc_conf->pause_time = hw->fc.pause_time;
4732 fc_conf->high_water = hw->fc.high_water[0];
4733 fc_conf->low_water = hw->fc.low_water[0];
4734 fc_conf->send_xon = hw->fc.send_xon;
4735 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4738 * Return rx_pause status according to actual setting of
4741 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4742 if (mflcn_reg & IXGBE_MFLCN_PMCF)
4743 fc_conf->mac_ctrl_frame_fwd = 1;
4745 fc_conf->mac_ctrl_frame_fwd = 0;
4747 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4753 * Return tx_pause status according to actual setting of
4756 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4757 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4762 if (rx_pause && tx_pause)
4763 fc_conf->mode = RTE_FC_FULL;
4765 fc_conf->mode = RTE_FC_RX_PAUSE;
4767 fc_conf->mode = RTE_FC_TX_PAUSE;
4769 fc_conf->mode = RTE_FC_NONE;
4775 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4777 struct ixgbe_hw *hw;
4778 struct ixgbe_adapter *adapter = dev->data->dev_private;
4780 uint32_t rx_buf_size;
4781 uint32_t max_high_water;
4782 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4789 PMD_INIT_FUNC_TRACE();
4791 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4792 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4793 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4796 * At least reserve one Ethernet frame for watermark
4797 * high_water/low_water in kilo bytes for ixgbe
4799 max_high_water = (rx_buf_size -
4800 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4801 if ((fc_conf->high_water > max_high_water) ||
4802 (fc_conf->high_water < fc_conf->low_water)) {
4803 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4804 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4808 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4809 hw->fc.pause_time = fc_conf->pause_time;
4810 hw->fc.high_water[0] = fc_conf->high_water;
4811 hw->fc.low_water[0] = fc_conf->low_water;
4812 hw->fc.send_xon = fc_conf->send_xon;
4813 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4814 adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4816 err = ixgbe_flow_ctrl_enable(dev, hw);
4818 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4825 * ixgbe_pfc_enable_generic - Enable flow control
4826 * @hw: pointer to hardware structure
4827 * @tc_num: traffic class number
4828 * Enable flow control according to the current settings.
4831 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4834 uint32_t mflcn_reg, fccfg_reg;
4836 uint32_t fcrtl, fcrth;
4840 /* Validate the water mark configuration */
4841 if (!hw->fc.pause_time) {
4842 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4846 /* Low water mark of zero causes XOFF floods */
4847 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4848 /* High/Low water can not be 0 */
4849 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4850 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4851 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4855 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4856 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4857 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4861 /* Negotiate the fc mode to use */
4862 ixgbe_fc_autoneg(hw);
4864 /* Disable any previous flow control settings */
4865 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4866 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4868 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4869 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4871 switch (hw->fc.current_mode) {
4874 * If the count of enabled RX Priority Flow control >1,
4875 * and the TX pause can not be disabled
4878 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4879 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4880 if (reg & IXGBE_FCRTH_FCEN)
4884 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4886 case ixgbe_fc_rx_pause:
4888 * Rx Flow control is enabled and Tx Flow control is
4889 * disabled by software override. Since there really
4890 * isn't a way to advertise that we are capable of RX
4891 * Pause ONLY, we will advertise that we support both
4892 * symmetric and asymmetric Rx PAUSE. Later, we will
4893 * disable the adapter's ability to send PAUSE frames.
4895 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4897 * If the count of enabled RX Priority Flow control >1,
4898 * and the TX pause can not be disabled
4901 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4902 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4903 if (reg & IXGBE_FCRTH_FCEN)
4907 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4909 case ixgbe_fc_tx_pause:
4911 * Tx Flow control is enabled, and Rx Flow control is
4912 * disabled by software override.
4914 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4917 /* Flow control (both Rx and Tx) is enabled by SW override. */
4918 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4919 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4922 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4923 ret_val = IXGBE_ERR_CONFIG;
4927 /* Set 802.3x based flow control settings. */
4928 mflcn_reg |= IXGBE_MFLCN_DPF;
4929 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4930 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4932 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4933 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4934 hw->fc.high_water[tc_num]) {
4935 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4936 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4937 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4939 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4941 * In order to prevent Tx hangs when the internal Tx
4942 * switch is enabled we must set the high water mark
4943 * to the maximum FCRTH value. This allows the Tx
4944 * switch to function even under heavy Rx workloads.
4946 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4948 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4950 /* Configure pause time (2 TCs per register) */
4951 reg = hw->fc.pause_time * 0x00010001;
4952 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4953 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4955 /* Configure flow control refresh threshold value */
4956 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4963 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4965 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4966 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4968 if (hw->mac.type != ixgbe_mac_82598EB) {
4969 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4975 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4978 uint32_t rx_buf_size;
4979 uint32_t max_high_water;
4981 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4982 struct ixgbe_hw *hw =
4983 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4984 struct ixgbe_dcb_config *dcb_config =
4985 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4987 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4994 PMD_INIT_FUNC_TRACE();
4996 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4997 tc_num = map[pfc_conf->priority];
4998 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4999 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
5001 * At least reserve one Ethernet frame for watermark
5002 * high_water/low_water in kilo bytes for ixgbe
5004 max_high_water = (rx_buf_size -
5005 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
5006 if ((pfc_conf->fc.high_water > max_high_water) ||
5007 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
5008 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
5009 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
5013 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
5014 hw->fc.pause_time = pfc_conf->fc.pause_time;
5015 hw->fc.send_xon = pfc_conf->fc.send_xon;
5016 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
5017 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
5019 err = ixgbe_dcb_pfc_enable(dev, tc_num);
5021 /* Not negotiated is not an error case */
5022 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5025 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5030 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5031 struct rte_eth_rss_reta_entry64 *reta_conf,
5034 uint16_t i, sp_reta_size;
5037 uint16_t idx, shift;
5038 struct ixgbe_adapter *adapter = dev->data->dev_private;
5039 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5042 PMD_INIT_FUNC_TRACE();
5044 if (!ixgbe_rss_update_sp(hw->mac.type)) {
5045 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5050 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5051 if (reta_size != sp_reta_size) {
5052 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5053 "(%d) doesn't match the number hardware can supported "
5054 "(%d)", reta_size, sp_reta_size);
5058 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5059 idx = i / RTE_RETA_GROUP_SIZE;
5060 shift = i % RTE_RETA_GROUP_SIZE;
5061 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5065 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5066 if (mask == IXGBE_4_BIT_MASK)
5069 r = IXGBE_READ_REG(hw, reta_reg);
5070 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5071 if (mask & (0x1 << j))
5072 reta |= reta_conf[idx].reta[shift + j] <<
5075 reta |= r & (IXGBE_8_BIT_MASK <<
5078 IXGBE_WRITE_REG(hw, reta_reg, reta);
5080 adapter->rss_reta_updated = 1;
5086 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5087 struct rte_eth_rss_reta_entry64 *reta_conf,
5090 uint16_t i, sp_reta_size;
5093 uint16_t idx, shift;
5094 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5097 PMD_INIT_FUNC_TRACE();
5098 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5099 if (reta_size != sp_reta_size) {
5100 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5101 "(%d) doesn't match the number hardware can supported "
5102 "(%d)", reta_size, sp_reta_size);
5106 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5107 idx = i / RTE_RETA_GROUP_SIZE;
5108 shift = i % RTE_RETA_GROUP_SIZE;
5109 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5114 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5115 reta = IXGBE_READ_REG(hw, reta_reg);
5116 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5117 if (mask & (0x1 << j))
5118 reta_conf[idx].reta[shift + j] =
5119 ((reta >> (CHAR_BIT * j)) &
5128 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5129 uint32_t index, uint32_t pool)
5131 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5132 uint32_t enable_addr = 1;
5134 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5139 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5141 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5143 ixgbe_clear_rar(hw, index);
5147 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5149 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5151 ixgbe_remove_rar(dev, 0);
5152 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5158 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5160 if (strcmp(dev->device->driver->name, drv->driver.name))
5167 is_ixgbe_supported(struct rte_eth_dev *dev)
5169 return is_device_supported(dev, &rte_ixgbe_pmd);
5173 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5177 struct ixgbe_hw *hw;
5178 struct rte_eth_dev_info dev_info;
5179 uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5180 struct rte_eth_dev_data *dev_data = dev->data;
5183 ret = ixgbe_dev_info_get(dev, &dev_info);
5187 /* check that mtu is within the allowed range */
5188 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5191 /* If device is started, refuse mtu that requires the support of
5192 * scattered packets when this feature has not been enabled before.
5194 if (dev_data->dev_started && !dev_data->scattered_rx &&
5195 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5196 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5197 PMD_INIT_LOG(ERR, "Stop port first.");
5201 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5202 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5204 /* switch to jumbo mode if needed */
5205 if (frame_size > RTE_ETHER_MAX_LEN) {
5206 dev->data->dev_conf.rxmode.offloads |=
5207 DEV_RX_OFFLOAD_JUMBO_FRAME;
5208 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5210 dev->data->dev_conf.rxmode.offloads &=
5211 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5212 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5214 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5216 /* update max frame size */
5217 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5219 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5220 maxfrs &= 0x0000FFFF;
5221 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5222 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5228 * Virtual Function operations
5231 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5233 struct ixgbe_interrupt *intr =
5234 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5235 struct ixgbe_hw *hw =
5236 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5238 PMD_INIT_FUNC_TRACE();
5240 /* Clear interrupt mask to stop from interrupts being generated */
5241 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5243 IXGBE_WRITE_FLUSH(hw);
5245 /* Clear mask value. */
5250 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5252 struct ixgbe_interrupt *intr =
5253 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5254 struct ixgbe_hw *hw =
5255 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5257 PMD_INIT_FUNC_TRACE();
5259 /* VF enable interrupt autoclean */
5260 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5261 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5262 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5264 IXGBE_WRITE_FLUSH(hw);
5266 /* Save IXGBE_VTEIMS value to mask. */
5267 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5271 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5273 struct rte_eth_conf *conf = &dev->data->dev_conf;
5274 struct ixgbe_adapter *adapter = dev->data->dev_private;
5276 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5277 dev->data->port_id);
5279 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5280 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5283 * VF has no ability to enable/disable HW CRC
5284 * Keep the persistent behavior the same as Host PF
5286 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5287 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5288 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5289 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5292 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5293 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5294 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5299 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5300 * allocation or vector Rx preconditions we will reset it.
5302 adapter->rx_bulk_alloc_allowed = true;
5303 adapter->rx_vec_allowed = true;
5309 ixgbevf_dev_start(struct rte_eth_dev *dev)
5311 struct ixgbe_hw *hw =
5312 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5313 uint32_t intr_vector = 0;
5314 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5315 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5319 PMD_INIT_FUNC_TRACE();
5321 /* Stop the link setup handler before resetting the HW. */
5322 ixgbe_dev_wait_setup_link_complete(dev, 0);
5324 err = hw->mac.ops.reset_hw(hw);
5326 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5329 hw->mac.get_link_status = true;
5331 /* negotiate mailbox API version to use with the PF. */
5332 ixgbevf_negotiate_api(hw);
5334 ixgbevf_dev_tx_init(dev);
5336 /* This can fail when allocating mbufs for descriptor rings */
5337 err = ixgbevf_dev_rx_init(dev);
5339 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5340 ixgbe_dev_clear_queues(dev);
5345 ixgbevf_set_vfta_all(dev, 1);
5348 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5349 ETH_VLAN_EXTEND_MASK;
5350 err = ixgbevf_vlan_offload_config(dev, mask);
5352 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5353 ixgbe_dev_clear_queues(dev);
5357 ixgbevf_dev_rxtx_start(dev);
5359 /* check and configure queue intr-vector mapping */
5360 if (rte_intr_cap_multiple(intr_handle) &&
5361 dev->data->dev_conf.intr_conf.rxq) {
5362 /* According to datasheet, only vector 0/1/2 can be used,
5363 * now only one vector is used for Rx queue
5366 if (rte_intr_efd_enable(intr_handle, intr_vector))
5370 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5371 intr_handle->intr_vec =
5372 rte_zmalloc("intr_vec",
5373 dev->data->nb_rx_queues * sizeof(int), 0);
5374 if (intr_handle->intr_vec == NULL) {
5375 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5376 " intr_vec", dev->data->nb_rx_queues);
5380 ixgbevf_configure_msix(dev);
5382 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5383 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5384 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5385 * is not cleared, it will fail when following rte_intr_enable( ) tries
5386 * to map Rx queue interrupt to other VFIO vectors.
5387 * So clear uio/vfio intr/evevnfd first to avoid failure.
5389 rte_intr_disable(intr_handle);
5391 rte_intr_enable(intr_handle);
5393 /* Re-enable interrupt for VF */
5394 ixgbevf_intr_enable(dev);
5397 * Update link status right before return, because it may
5398 * start link configuration process in a separate thread.
5400 ixgbevf_dev_link_update(dev, 0);
5402 hw->adapter_stopped = false;
5408 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5410 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5411 struct ixgbe_adapter *adapter = dev->data->dev_private;
5412 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5413 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5415 if (hw->adapter_stopped)
5418 PMD_INIT_FUNC_TRACE();
5420 ixgbe_dev_wait_setup_link_complete(dev, 0);
5422 ixgbevf_intr_disable(dev);
5424 hw->adapter_stopped = 1;
5425 ixgbe_stop_adapter(hw);
5428 * Clear what we set, but we still keep shadow_vfta to
5429 * restore after device starts
5431 ixgbevf_set_vfta_all(dev, 0);
5433 /* Clear stored conf */
5434 dev->data->scattered_rx = 0;
5436 ixgbe_dev_clear_queues(dev);
5438 /* Clean datapath event and queue/vec mapping */
5439 rte_intr_efd_disable(intr_handle);
5440 if (intr_handle->intr_vec != NULL) {
5441 rte_free(intr_handle->intr_vec);
5442 intr_handle->intr_vec = NULL;
5445 adapter->rss_reta_updated = 0;
5449 ixgbevf_dev_close(struct rte_eth_dev *dev)
5451 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5452 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5453 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5455 PMD_INIT_FUNC_TRACE();
5459 ixgbevf_dev_stop(dev);
5461 ixgbe_dev_free_queues(dev);
5464 * Remove the VF MAC address ro ensure
5465 * that the VF traffic goes to the PF
5466 * after stop, close and detach of the VF
5468 ixgbevf_remove_mac_addr(dev, 0);
5470 dev->dev_ops = NULL;
5471 dev->rx_pkt_burst = NULL;
5472 dev->tx_pkt_burst = NULL;
5474 rte_intr_disable(intr_handle);
5475 rte_intr_callback_unregister(intr_handle,
5476 ixgbevf_dev_interrupt_handler, dev);
5483 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5487 ret = eth_ixgbevf_dev_uninit(dev);
5491 ret = eth_ixgbevf_dev_init(dev);
5496 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5498 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5499 struct ixgbe_vfta *shadow_vfta =
5500 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5501 int i = 0, j = 0, vfta = 0, mask = 1;
5503 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5504 vfta = shadow_vfta->vfta[i];
5507 for (j = 0; j < 32; j++) {
5509 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5519 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5521 struct ixgbe_hw *hw =
5522 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5523 struct ixgbe_vfta *shadow_vfta =
5524 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5525 uint32_t vid_idx = 0;
5526 uint32_t vid_bit = 0;
5529 PMD_INIT_FUNC_TRACE();
5531 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5532 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5534 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5537 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5538 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5540 /* Save what we set and retore it after device reset */
5542 shadow_vfta->vfta[vid_idx] |= vid_bit;
5544 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5550 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5552 struct ixgbe_hw *hw =
5553 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5556 PMD_INIT_FUNC_TRACE();
5558 if (queue >= hw->mac.max_rx_queues)
5561 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5563 ctrl |= IXGBE_RXDCTL_VME;
5565 ctrl &= ~IXGBE_RXDCTL_VME;
5566 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5568 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5572 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5574 struct ixgbe_rx_queue *rxq;
5578 /* VF function only support hw strip feature, others are not support */
5579 if (mask & ETH_VLAN_STRIP_MASK) {
5580 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5581 rxq = dev->data->rx_queues[i];
5582 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5583 ixgbevf_vlan_strip_queue_set(dev, i, on);
5591 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5593 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5595 ixgbevf_vlan_offload_config(dev, mask);
5601 ixgbe_vt_check(struct ixgbe_hw *hw)
5605 /* if Virtualization Technology is enabled */
5606 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5607 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5608 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5616 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5618 uint32_t vector = 0;
5620 switch (hw->mac.mc_filter_type) {
5621 case 0: /* use bits [47:36] of the address */
5622 vector = ((uc_addr->addr_bytes[4] >> 4) |
5623 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5625 case 1: /* use bits [46:35] of the address */
5626 vector = ((uc_addr->addr_bytes[4] >> 3) |
5627 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5629 case 2: /* use bits [45:34] of the address */
5630 vector = ((uc_addr->addr_bytes[4] >> 2) |
5631 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5633 case 3: /* use bits [43:32] of the address */
5634 vector = ((uc_addr->addr_bytes[4]) |
5635 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5637 default: /* Invalid mc_filter_type */
5641 /* vector can only be 12-bits or boundary will be exceeded */
5647 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5648 struct rte_ether_addr *mac_addr, uint8_t on)
5655 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5656 const uint32_t ixgbe_uta_bit_shift = 5;
5657 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5658 const uint32_t bit1 = 0x1;
5660 struct ixgbe_hw *hw =
5661 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5662 struct ixgbe_uta_info *uta_info =
5663 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5665 /* The UTA table only exists on 82599 hardware and newer */
5666 if (hw->mac.type < ixgbe_mac_82599EB)
5669 vector = ixgbe_uta_vector(hw, mac_addr);
5670 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5671 uta_shift = vector & ixgbe_uta_bit_mask;
5673 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5677 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5679 uta_info->uta_in_use++;
5680 reg_val |= (bit1 << uta_shift);
5681 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5683 uta_info->uta_in_use--;
5684 reg_val &= ~(bit1 << uta_shift);
5685 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5688 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5690 if (uta_info->uta_in_use > 0)
5691 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5692 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5694 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5700 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5703 struct ixgbe_hw *hw =
5704 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5705 struct ixgbe_uta_info *uta_info =
5706 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5708 /* The UTA table only exists on 82599 hardware and newer */
5709 if (hw->mac.type < ixgbe_mac_82599EB)
5713 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5714 uta_info->uta_shadow[i] = ~0;
5715 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5718 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5719 uta_info->uta_shadow[i] = 0;
5720 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5728 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5730 uint32_t new_val = orig_val;
5732 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5733 new_val |= IXGBE_VMOLR_AUPE;
5734 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5735 new_val |= IXGBE_VMOLR_ROMPE;
5736 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5737 new_val |= IXGBE_VMOLR_ROPE;
5738 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5739 new_val |= IXGBE_VMOLR_BAM;
5740 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5741 new_val |= IXGBE_VMOLR_MPE;
5746 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5747 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5748 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5749 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5750 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5751 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5752 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5755 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5756 struct rte_eth_mirror_conf *mirror_conf,
5757 uint8_t rule_id, uint8_t on)
5759 uint32_t mr_ctl, vlvf;
5760 uint32_t mp_lsb = 0;
5761 uint32_t mv_msb = 0;
5762 uint32_t mv_lsb = 0;
5763 uint32_t mp_msb = 0;
5766 uint64_t vlan_mask = 0;
5768 const uint8_t pool_mask_offset = 32;
5769 const uint8_t vlan_mask_offset = 32;
5770 const uint8_t dst_pool_offset = 8;
5771 const uint8_t rule_mr_offset = 4;
5772 const uint8_t mirror_rule_mask = 0x0F;
5774 struct ixgbe_mirror_info *mr_info =
5775 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5776 struct ixgbe_hw *hw =
5777 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5778 uint8_t mirror_type = 0;
5780 if (ixgbe_vt_check(hw) < 0)
5783 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5786 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5787 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5788 mirror_conf->rule_type);
5792 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5793 mirror_type |= IXGBE_MRCTL_VLME;
5794 /* Check if vlan id is valid and find conresponding VLAN ID
5797 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5798 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5799 /* search vlan id related pool vlan filter
5802 reg_index = ixgbe_find_vlvf_slot(
5804 mirror_conf->vlan.vlan_id[i],
5808 vlvf = IXGBE_READ_REG(hw,
5809 IXGBE_VLVF(reg_index));
5810 if ((vlvf & IXGBE_VLVF_VIEN) &&
5811 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5812 mirror_conf->vlan.vlan_id[i]))
5813 vlan_mask |= (1ULL << reg_index);
5820 mv_lsb = vlan_mask & 0xFFFFFFFF;
5821 mv_msb = vlan_mask >> vlan_mask_offset;
5823 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5824 mirror_conf->vlan.vlan_mask;
5825 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5826 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5827 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5828 mirror_conf->vlan.vlan_id[i];
5833 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5834 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5835 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5840 * if enable pool mirror, write related pool mask register,if disable
5841 * pool mirror, clear PFMRVM register
5843 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5844 mirror_type |= IXGBE_MRCTL_VPME;
5846 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5847 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5848 mr_info->mr_conf[rule_id].pool_mask =
5849 mirror_conf->pool_mask;
5854 mr_info->mr_conf[rule_id].pool_mask = 0;
5857 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5858 mirror_type |= IXGBE_MRCTL_UPME;
5859 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5860 mirror_type |= IXGBE_MRCTL_DPME;
5862 /* read mirror control register and recalculate it */
5863 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5866 mr_ctl |= mirror_type;
5867 mr_ctl &= mirror_rule_mask;
5868 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5870 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5873 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5874 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5876 /* write mirrror control register */
5877 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5879 /* write pool mirrror control register */
5880 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5881 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5882 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5885 /* write VLAN mirrror control register */
5886 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5887 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5888 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5896 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5899 uint32_t lsb_val = 0;
5900 uint32_t msb_val = 0;
5901 const uint8_t rule_mr_offset = 4;
5903 struct ixgbe_hw *hw =
5904 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5905 struct ixgbe_mirror_info *mr_info =
5906 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5908 if (ixgbe_vt_check(hw) < 0)
5911 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5914 memset(&mr_info->mr_conf[rule_id], 0,
5915 sizeof(struct rte_eth_mirror_conf));
5917 /* clear PFVMCTL register */
5918 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5920 /* clear pool mask register */
5921 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5922 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5924 /* clear vlan mask register */
5925 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5926 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5932 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5934 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5935 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5936 struct ixgbe_interrupt *intr =
5937 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5938 struct ixgbe_hw *hw =
5939 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5940 uint32_t vec = IXGBE_MISC_VEC_ID;
5942 if (rte_intr_allow_others(intr_handle))
5943 vec = IXGBE_RX_VEC_START;
5944 intr->mask |= (1 << vec);
5945 RTE_SET_USED(queue_id);
5946 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5948 rte_intr_ack(intr_handle);
5954 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5956 struct ixgbe_interrupt *intr =
5957 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5958 struct ixgbe_hw *hw =
5959 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5960 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5961 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5962 uint32_t vec = IXGBE_MISC_VEC_ID;
5964 if (rte_intr_allow_others(intr_handle))
5965 vec = IXGBE_RX_VEC_START;
5966 intr->mask &= ~(1 << vec);
5967 RTE_SET_USED(queue_id);
5968 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5974 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5976 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5977 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5979 struct ixgbe_hw *hw =
5980 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5981 struct ixgbe_interrupt *intr =
5982 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5984 if (queue_id < 16) {
5985 ixgbe_disable_intr(hw);
5986 intr->mask |= (1 << queue_id);
5987 ixgbe_enable_intr(dev);
5988 } else if (queue_id < 32) {
5989 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5990 mask &= (1 << queue_id);
5991 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5992 } else if (queue_id < 64) {
5993 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5994 mask &= (1 << (queue_id - 32));
5995 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5997 rte_intr_ack(intr_handle);
6003 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
6006 struct ixgbe_hw *hw =
6007 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6008 struct ixgbe_interrupt *intr =
6009 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
6011 if (queue_id < 16) {
6012 ixgbe_disable_intr(hw);
6013 intr->mask &= ~(1 << queue_id);
6014 ixgbe_enable_intr(dev);
6015 } else if (queue_id < 32) {
6016 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6017 mask &= ~(1 << queue_id);
6018 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6019 } else if (queue_id < 64) {
6020 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6021 mask &= ~(1 << (queue_id - 32));
6022 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6029 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6030 uint8_t queue, uint8_t msix_vector)
6034 if (direction == -1) {
6036 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6037 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6040 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6042 /* rx or tx cause */
6043 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6044 idx = ((16 * (queue & 1)) + (8 * direction));
6045 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6046 tmp &= ~(0xFF << idx);
6047 tmp |= (msix_vector << idx);
6048 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6053 * set the IVAR registers, mapping interrupt causes to vectors
6055 * pointer to ixgbe_hw struct
6057 * 0 for Rx, 1 for Tx, -1 for other causes
6059 * queue to map the corresponding interrupt to
6061 * the vector to map to the corresponding queue
6064 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6065 uint8_t queue, uint8_t msix_vector)
6069 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6070 if (hw->mac.type == ixgbe_mac_82598EB) {
6071 if (direction == -1)
6073 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6074 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6075 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6076 tmp |= (msix_vector << (8 * (queue & 0x3)));
6077 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6078 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6079 (hw->mac.type == ixgbe_mac_X540) ||
6080 (hw->mac.type == ixgbe_mac_X550) ||
6081 (hw->mac.type == ixgbe_mac_X550EM_x)) {
6082 if (direction == -1) {
6084 idx = ((queue & 1) * 8);
6085 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6086 tmp &= ~(0xFF << idx);
6087 tmp |= (msix_vector << idx);
6088 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6090 /* rx or tx causes */
6091 idx = ((16 * (queue & 1)) + (8 * direction));
6092 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6093 tmp &= ~(0xFF << idx);
6094 tmp |= (msix_vector << idx);
6095 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6101 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6103 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6104 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6105 struct ixgbe_hw *hw =
6106 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6108 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6109 uint32_t base = IXGBE_MISC_VEC_ID;
6111 /* Configure VF other cause ivar */
6112 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6114 /* won't configure msix register if no mapping is done
6115 * between intr vector and event fd.
6117 if (!rte_intr_dp_is_en(intr_handle))
6120 if (rte_intr_allow_others(intr_handle)) {
6121 base = IXGBE_RX_VEC_START;
6122 vector_idx = IXGBE_RX_VEC_START;
6125 /* Configure all RX queues of VF */
6126 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6127 /* Force all queue use vector 0,
6128 * as IXGBE_VF_MAXMSIVECOTR = 1
6130 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6131 intr_handle->intr_vec[q_idx] = vector_idx;
6132 if (vector_idx < base + intr_handle->nb_efd - 1)
6136 /* As RX queue setting above show, all queues use the vector 0.
6137 * Set only the ITR value of IXGBE_MISC_VEC_ID.
6139 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6140 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6141 | IXGBE_EITR_CNT_WDIS);
6145 * Sets up the hardware to properly generate MSI-X interrupts
6147 * board private structure
6150 ixgbe_configure_msix(struct rte_eth_dev *dev)
6152 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6153 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6154 struct ixgbe_hw *hw =
6155 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6156 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6157 uint32_t vec = IXGBE_MISC_VEC_ID;
6161 /* won't configure msix register if no mapping is done
6162 * between intr vector and event fd
6163 * but if misx has been enabled already, need to configure
6164 * auto clean, auto mask and throttling.
6166 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6167 if (!rte_intr_dp_is_en(intr_handle) &&
6168 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6171 if (rte_intr_allow_others(intr_handle))
6172 vec = base = IXGBE_RX_VEC_START;
6174 /* setup GPIE for MSI-x mode */
6175 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6176 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6177 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6178 /* auto clearing and auto setting corresponding bits in EIMS
6179 * when MSI-X interrupt is triggered
6181 if (hw->mac.type == ixgbe_mac_82598EB) {
6182 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6184 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6185 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6187 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6189 /* Populate the IVAR table and set the ITR values to the
6190 * corresponding register.
6192 if (rte_intr_dp_is_en(intr_handle)) {
6193 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6195 /* by default, 1:1 mapping */
6196 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6197 intr_handle->intr_vec[queue_id] = vec;
6198 if (vec < base + intr_handle->nb_efd - 1)
6202 switch (hw->mac.type) {
6203 case ixgbe_mac_82598EB:
6204 ixgbe_set_ivar_map(hw, -1,
6205 IXGBE_IVAR_OTHER_CAUSES_INDEX,
6208 case ixgbe_mac_82599EB:
6209 case ixgbe_mac_X540:
6210 case ixgbe_mac_X550:
6211 case ixgbe_mac_X550EM_x:
6212 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6218 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6219 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6220 | IXGBE_EITR_CNT_WDIS);
6222 /* set up to autoclear timer, and the vectors */
6223 mask = IXGBE_EIMS_ENABLE_MASK;
6224 mask &= ~(IXGBE_EIMS_OTHER |
6225 IXGBE_EIMS_MAILBOX |
6228 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6232 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6233 uint16_t queue_idx, uint16_t tx_rate)
6235 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6236 struct rte_eth_rxmode *rxmode;
6237 uint32_t rf_dec, rf_int;
6239 uint16_t link_speed = dev->data->dev_link.link_speed;
6241 if (queue_idx >= hw->mac.max_tx_queues)
6245 /* Calculate the rate factor values to set */
6246 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6247 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6248 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6250 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6251 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6252 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6253 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6258 rxmode = &dev->data->dev_conf.rxmode;
6260 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6261 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6264 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6265 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6266 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6267 IXGBE_MMW_SIZE_JUMBO_FRAME);
6269 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6270 IXGBE_MMW_SIZE_DEFAULT);
6272 /* Set RTTBCNRC of queue X */
6273 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6274 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6275 IXGBE_WRITE_FLUSH(hw);
6281 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6282 __rte_unused uint32_t index,
6283 __rte_unused uint32_t pool)
6285 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6289 * On a 82599 VF, adding again the same MAC addr is not an idempotent
6290 * operation. Trap this case to avoid exhausting the [very limited]
6291 * set of PF resources used to store VF MAC addresses.
6293 if (memcmp(hw->mac.perm_addr, mac_addr,
6294 sizeof(struct rte_ether_addr)) == 0)
6296 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6298 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6299 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6300 mac_addr->addr_bytes[0],
6301 mac_addr->addr_bytes[1],
6302 mac_addr->addr_bytes[2],
6303 mac_addr->addr_bytes[3],
6304 mac_addr->addr_bytes[4],
6305 mac_addr->addr_bytes[5],
6311 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6313 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6314 struct rte_ether_addr *perm_addr =
6315 (struct rte_ether_addr *)hw->mac.perm_addr;
6316 struct rte_ether_addr *mac_addr;
6321 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6322 * not support the deletion of a given MAC address.
6323 * Instead, it imposes to delete all MAC addresses, then to add again
6324 * all MAC addresses with the exception of the one to be deleted.
6326 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6329 * Add again all MAC addresses, with the exception of the deleted one
6330 * and of the permanent MAC address.
6332 for (i = 0, mac_addr = dev->data->mac_addrs;
6333 i < hw->mac.num_rar_entries; i++, mac_addr++) {
6334 /* Skip the deleted MAC address */
6337 /* Skip NULL MAC addresses */
6338 if (rte_is_zero_ether_addr(mac_addr))
6340 /* Skip the permanent MAC address */
6341 if (memcmp(perm_addr, mac_addr,
6342 sizeof(struct rte_ether_addr)) == 0)
6344 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6347 "Adding again MAC address "
6348 "%02x:%02x:%02x:%02x:%02x:%02x failed "
6350 mac_addr->addr_bytes[0],
6351 mac_addr->addr_bytes[1],
6352 mac_addr->addr_bytes[2],
6353 mac_addr->addr_bytes[3],
6354 mac_addr->addr_bytes[4],
6355 mac_addr->addr_bytes[5],
6361 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6362 struct rte_ether_addr *addr)
6364 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6366 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6372 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6373 struct rte_eth_syn_filter *filter,
6376 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6377 struct ixgbe_filter_info *filter_info =
6378 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6382 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6385 syn_info = filter_info->syn_info;
6388 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6390 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6391 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6393 if (filter->hig_pri)
6394 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6396 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6398 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6399 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6401 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6404 filter_info->syn_info = synqf;
6405 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6406 IXGBE_WRITE_FLUSH(hw);
6411 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6412 struct rte_eth_syn_filter *filter)
6414 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6415 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6417 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6418 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6419 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6426 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6427 enum rte_filter_op filter_op,
6430 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6433 MAC_TYPE_FILTER_SUP(hw->mac.type);
6435 if (filter_op == RTE_ETH_FILTER_NOP)
6439 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6444 switch (filter_op) {
6445 case RTE_ETH_FILTER_ADD:
6446 ret = ixgbe_syn_filter_set(dev,
6447 (struct rte_eth_syn_filter *)arg,
6450 case RTE_ETH_FILTER_DELETE:
6451 ret = ixgbe_syn_filter_set(dev,
6452 (struct rte_eth_syn_filter *)arg,
6455 case RTE_ETH_FILTER_GET:
6456 ret = ixgbe_syn_filter_get(dev,
6457 (struct rte_eth_syn_filter *)arg);
6460 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6469 static inline enum ixgbe_5tuple_protocol
6470 convert_protocol_type(uint8_t protocol_value)
6472 if (protocol_value == IPPROTO_TCP)
6473 return IXGBE_FILTER_PROTOCOL_TCP;
6474 else if (protocol_value == IPPROTO_UDP)
6475 return IXGBE_FILTER_PROTOCOL_UDP;
6476 else if (protocol_value == IPPROTO_SCTP)
6477 return IXGBE_FILTER_PROTOCOL_SCTP;
6479 return IXGBE_FILTER_PROTOCOL_NONE;
6482 /* inject a 5-tuple filter to HW */
6484 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6485 struct ixgbe_5tuple_filter *filter)
6487 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6489 uint32_t ftqf, sdpqf;
6490 uint32_t l34timir = 0;
6491 uint8_t mask = 0xff;
6495 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6496 IXGBE_SDPQF_DSTPORT_SHIFT);
6497 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6499 ftqf = (uint32_t)(filter->filter_info.proto &
6500 IXGBE_FTQF_PROTOCOL_MASK);
6501 ftqf |= (uint32_t)((filter->filter_info.priority &
6502 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6503 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6504 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6505 if (filter->filter_info.dst_ip_mask == 0)
6506 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6507 if (filter->filter_info.src_port_mask == 0)
6508 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6509 if (filter->filter_info.dst_port_mask == 0)
6510 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6511 if (filter->filter_info.proto_mask == 0)
6512 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6513 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6514 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6515 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6517 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6518 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6519 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6520 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6522 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6523 l34timir |= (uint32_t)(filter->queue <<
6524 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6525 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6529 * add a 5tuple filter
6532 * dev: Pointer to struct rte_eth_dev.
6533 * index: the index the filter allocates.
6534 * filter: ponter to the filter that will be added.
6535 * rx_queue: the queue id the filter assigned to.
6538 * - On success, zero.
6539 * - On failure, a negative value.
6542 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6543 struct ixgbe_5tuple_filter *filter)
6545 struct ixgbe_filter_info *filter_info =
6546 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6550 * look for an unused 5tuple filter index,
6551 * and insert the filter to list.
6553 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6554 idx = i / (sizeof(uint32_t) * NBBY);
6555 shift = i % (sizeof(uint32_t) * NBBY);
6556 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6557 filter_info->fivetuple_mask[idx] |= 1 << shift;
6559 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6565 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6566 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6570 ixgbe_inject_5tuple_filter(dev, filter);
6576 * remove a 5tuple filter
6579 * dev: Pointer to struct rte_eth_dev.
6580 * filter: the pointer of the filter will be removed.
6583 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6584 struct ixgbe_5tuple_filter *filter)
6586 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6587 struct ixgbe_filter_info *filter_info =
6588 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6589 uint16_t index = filter->index;
6591 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6592 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6593 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6596 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6597 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6598 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6599 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6600 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6604 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6606 struct ixgbe_hw *hw;
6607 uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6608 struct rte_eth_dev_data *dev_data = dev->data;
6610 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6612 if (mtu < RTE_ETHER_MIN_MTU ||
6613 max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6616 /* If device is started, refuse mtu that requires the support of
6617 * scattered packets when this feature has not been enabled before.
6619 if (dev_data->dev_started && !dev_data->scattered_rx &&
6620 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6621 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6622 PMD_INIT_LOG(ERR, "Stop port first.");
6627 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6628 * request of the version 2.0 of the mailbox API.
6629 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6630 * of the mailbox API.
6631 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6632 * prior to 3.11.33 which contains the following change:
6633 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6635 ixgbevf_rlpml_set_vf(hw, max_frame);
6637 /* update max frame size */
6638 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6642 static inline struct ixgbe_5tuple_filter *
6643 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6644 struct ixgbe_5tuple_filter_info *key)
6646 struct ixgbe_5tuple_filter *it;
6648 TAILQ_FOREACH(it, filter_list, entries) {
6649 if (memcmp(key, &it->filter_info,
6650 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6657 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6659 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6660 struct ixgbe_5tuple_filter_info *filter_info)
6662 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6663 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6664 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6667 switch (filter->dst_ip_mask) {
6669 filter_info->dst_ip_mask = 0;
6670 filter_info->dst_ip = filter->dst_ip;
6673 filter_info->dst_ip_mask = 1;
6676 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6680 switch (filter->src_ip_mask) {
6682 filter_info->src_ip_mask = 0;
6683 filter_info->src_ip = filter->src_ip;
6686 filter_info->src_ip_mask = 1;
6689 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6693 switch (filter->dst_port_mask) {
6695 filter_info->dst_port_mask = 0;
6696 filter_info->dst_port = filter->dst_port;
6699 filter_info->dst_port_mask = 1;
6702 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6706 switch (filter->src_port_mask) {
6708 filter_info->src_port_mask = 0;
6709 filter_info->src_port = filter->src_port;
6712 filter_info->src_port_mask = 1;
6715 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6719 switch (filter->proto_mask) {
6721 filter_info->proto_mask = 0;
6722 filter_info->proto =
6723 convert_protocol_type(filter->proto);
6726 filter_info->proto_mask = 1;
6729 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6733 filter_info->priority = (uint8_t)filter->priority;
6738 * add or delete a ntuple filter
6741 * dev: Pointer to struct rte_eth_dev.
6742 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6743 * add: if true, add filter, if false, remove filter
6746 * - On success, zero.
6747 * - On failure, a negative value.
6750 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6751 struct rte_eth_ntuple_filter *ntuple_filter,
6754 struct ixgbe_filter_info *filter_info =
6755 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6756 struct ixgbe_5tuple_filter_info filter_5tuple;
6757 struct ixgbe_5tuple_filter *filter;
6760 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6761 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6765 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6766 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6770 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6772 if (filter != NULL && add) {
6773 PMD_DRV_LOG(ERR, "filter exists.");
6776 if (filter == NULL && !add) {
6777 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6782 filter = rte_zmalloc("ixgbe_5tuple_filter",
6783 sizeof(struct ixgbe_5tuple_filter), 0);
6786 rte_memcpy(&filter->filter_info,
6788 sizeof(struct ixgbe_5tuple_filter_info));
6789 filter->queue = ntuple_filter->queue;
6790 ret = ixgbe_add_5tuple_filter(dev, filter);
6796 ixgbe_remove_5tuple_filter(dev, filter);
6802 * get a ntuple filter
6805 * dev: Pointer to struct rte_eth_dev.
6806 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6809 * - On success, zero.
6810 * - On failure, a negative value.
6813 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6814 struct rte_eth_ntuple_filter *ntuple_filter)
6816 struct ixgbe_filter_info *filter_info =
6817 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6818 struct ixgbe_5tuple_filter_info filter_5tuple;
6819 struct ixgbe_5tuple_filter *filter;
6822 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6823 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6827 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6828 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6832 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6834 if (filter == NULL) {
6835 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6838 ntuple_filter->queue = filter->queue;
6843 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6844 * @dev: pointer to rte_eth_dev structure
6845 * @filter_op:operation will be taken.
6846 * @arg: a pointer to specific structure corresponding to the filter_op
6849 * - On success, zero.
6850 * - On failure, a negative value.
6853 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6854 enum rte_filter_op filter_op,
6857 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6860 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6862 if (filter_op == RTE_ETH_FILTER_NOP)
6866 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6871 switch (filter_op) {
6872 case RTE_ETH_FILTER_ADD:
6873 ret = ixgbe_add_del_ntuple_filter(dev,
6874 (struct rte_eth_ntuple_filter *)arg,
6877 case RTE_ETH_FILTER_DELETE:
6878 ret = ixgbe_add_del_ntuple_filter(dev,
6879 (struct rte_eth_ntuple_filter *)arg,
6882 case RTE_ETH_FILTER_GET:
6883 ret = ixgbe_get_ntuple_filter(dev,
6884 (struct rte_eth_ntuple_filter *)arg);
6887 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6895 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6896 struct rte_eth_ethertype_filter *filter,
6899 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6900 struct ixgbe_filter_info *filter_info =
6901 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6905 struct ixgbe_ethertype_filter ethertype_filter;
6907 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6910 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6911 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6912 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6913 " ethertype filter.", filter->ether_type);
6917 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6918 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6921 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6922 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6926 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6927 if (ret >= 0 && add) {
6928 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6929 filter->ether_type);
6932 if (ret < 0 && !add) {
6933 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6934 filter->ether_type);
6939 etqf = IXGBE_ETQF_FILTER_EN;
6940 etqf |= (uint32_t)filter->ether_type;
6941 etqs |= (uint32_t)((filter->queue <<
6942 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6943 IXGBE_ETQS_RX_QUEUE);
6944 etqs |= IXGBE_ETQS_QUEUE_EN;
6946 ethertype_filter.ethertype = filter->ether_type;
6947 ethertype_filter.etqf = etqf;
6948 ethertype_filter.etqs = etqs;
6949 ethertype_filter.conf = FALSE;
6950 ret = ixgbe_ethertype_filter_insert(filter_info,
6953 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6957 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6961 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6962 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6963 IXGBE_WRITE_FLUSH(hw);
6969 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6970 struct rte_eth_ethertype_filter *filter)
6972 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6973 struct ixgbe_filter_info *filter_info =
6974 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6975 uint32_t etqf, etqs;
6978 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6980 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6981 filter->ether_type);
6985 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6986 if (etqf & IXGBE_ETQF_FILTER_EN) {
6987 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6988 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6990 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6991 IXGBE_ETQS_RX_QUEUE_SHIFT;
6998 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6999 * @dev: pointer to rte_eth_dev structure
7000 * @filter_op:operation will be taken.
7001 * @arg: a pointer to specific structure corresponding to the filter_op
7004 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
7005 enum rte_filter_op filter_op,
7008 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7011 MAC_TYPE_FILTER_SUP(hw->mac.type);
7013 if (filter_op == RTE_ETH_FILTER_NOP)
7017 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7022 switch (filter_op) {
7023 case RTE_ETH_FILTER_ADD:
7024 ret = ixgbe_add_del_ethertype_filter(dev,
7025 (struct rte_eth_ethertype_filter *)arg,
7028 case RTE_ETH_FILTER_DELETE:
7029 ret = ixgbe_add_del_ethertype_filter(dev,
7030 (struct rte_eth_ethertype_filter *)arg,
7033 case RTE_ETH_FILTER_GET:
7034 ret = ixgbe_get_ethertype_filter(dev,
7035 (struct rte_eth_ethertype_filter *)arg);
7038 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7046 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
7047 enum rte_filter_type filter_type,
7048 enum rte_filter_op filter_op,
7053 switch (filter_type) {
7054 case RTE_ETH_FILTER_NTUPLE:
7055 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
7057 case RTE_ETH_FILTER_ETHERTYPE:
7058 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
7060 case RTE_ETH_FILTER_SYN:
7061 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
7063 case RTE_ETH_FILTER_FDIR:
7064 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
7066 case RTE_ETH_FILTER_L2_TUNNEL:
7067 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
7069 case RTE_ETH_FILTER_GENERIC:
7070 if (filter_op != RTE_ETH_FILTER_GET)
7072 *(const void **)arg = &ixgbe_flow_ops;
7075 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7085 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
7086 u8 **mc_addr_ptr, u32 *vmdq)
7091 mc_addr = *mc_addr_ptr;
7092 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
7097 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
7098 struct rte_ether_addr *mc_addr_set,
7099 uint32_t nb_mc_addr)
7101 struct ixgbe_hw *hw;
7104 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7105 mc_addr_list = (u8 *)mc_addr_set;
7106 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
7107 ixgbe_dev_addr_list_itr, TRUE);
7111 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
7113 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7114 uint64_t systime_cycles;
7116 switch (hw->mac.type) {
7117 case ixgbe_mac_X550:
7118 case ixgbe_mac_X550EM_x:
7119 case ixgbe_mac_X550EM_a:
7120 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
7121 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7122 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7126 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7127 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7131 return systime_cycles;
7135 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7137 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7138 uint64_t rx_tstamp_cycles;
7140 switch (hw->mac.type) {
7141 case ixgbe_mac_X550:
7142 case ixgbe_mac_X550EM_x:
7143 case ixgbe_mac_X550EM_a:
7144 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7145 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7146 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7150 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7151 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7152 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7156 return rx_tstamp_cycles;
7160 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7162 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7163 uint64_t tx_tstamp_cycles;
7165 switch (hw->mac.type) {
7166 case ixgbe_mac_X550:
7167 case ixgbe_mac_X550EM_x:
7168 case ixgbe_mac_X550EM_a:
7169 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7170 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7171 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7175 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7176 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7177 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7181 return tx_tstamp_cycles;
7185 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7187 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7188 struct ixgbe_adapter *adapter = dev->data->dev_private;
7189 struct rte_eth_link link;
7190 uint32_t incval = 0;
7193 /* Get current link speed. */
7194 ixgbe_dev_link_update(dev, 1);
7195 rte_eth_linkstatus_get(dev, &link);
7197 switch (link.link_speed) {
7198 case ETH_SPEED_NUM_100M:
7199 incval = IXGBE_INCVAL_100;
7200 shift = IXGBE_INCVAL_SHIFT_100;
7202 case ETH_SPEED_NUM_1G:
7203 incval = IXGBE_INCVAL_1GB;
7204 shift = IXGBE_INCVAL_SHIFT_1GB;
7206 case ETH_SPEED_NUM_10G:
7208 incval = IXGBE_INCVAL_10GB;
7209 shift = IXGBE_INCVAL_SHIFT_10GB;
7213 switch (hw->mac.type) {
7214 case ixgbe_mac_X550:
7215 case ixgbe_mac_X550EM_x:
7216 case ixgbe_mac_X550EM_a:
7217 /* Independent of link speed. */
7219 /* Cycles read will be interpreted as ns. */
7222 case ixgbe_mac_X540:
7223 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7225 case ixgbe_mac_82599EB:
7226 incval >>= IXGBE_INCVAL_SHIFT_82599;
7227 shift -= IXGBE_INCVAL_SHIFT_82599;
7228 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7229 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7232 /* Not supported. */
7236 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7237 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7238 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7240 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7241 adapter->systime_tc.cc_shift = shift;
7242 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7244 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7245 adapter->rx_tstamp_tc.cc_shift = shift;
7246 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7248 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7249 adapter->tx_tstamp_tc.cc_shift = shift;
7250 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7254 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7256 struct ixgbe_adapter *adapter = dev->data->dev_private;
7258 adapter->systime_tc.nsec += delta;
7259 adapter->rx_tstamp_tc.nsec += delta;
7260 adapter->tx_tstamp_tc.nsec += delta;
7266 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7269 struct ixgbe_adapter *adapter = dev->data->dev_private;
7271 ns = rte_timespec_to_ns(ts);
7272 /* Set the timecounters to a new value. */
7273 adapter->systime_tc.nsec = ns;
7274 adapter->rx_tstamp_tc.nsec = ns;
7275 adapter->tx_tstamp_tc.nsec = ns;
7281 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7283 uint64_t ns, systime_cycles;
7284 struct ixgbe_adapter *adapter = dev->data->dev_private;
7286 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7287 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7288 *ts = rte_ns_to_timespec(ns);
7294 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7296 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7300 /* Stop the timesync system time. */
7301 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7302 /* Reset the timesync system time value. */
7303 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7304 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7306 /* Enable system time for platforms where it isn't on by default. */
7307 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7308 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7309 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7311 ixgbe_start_timecounters(dev);
7313 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7314 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7315 (RTE_ETHER_TYPE_1588 |
7316 IXGBE_ETQF_FILTER_EN |
7319 /* Enable timestamping of received PTP packets. */
7320 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7321 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7322 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7324 /* Enable timestamping of transmitted PTP packets. */
7325 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7326 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7327 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7329 IXGBE_WRITE_FLUSH(hw);
7335 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7337 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7340 /* Disable timestamping of transmitted PTP packets. */
7341 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7342 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7343 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7345 /* Disable timestamping of received PTP packets. */
7346 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7347 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7348 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7350 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7351 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7353 /* Stop incrementating the System Time registers. */
7354 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7360 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7361 struct timespec *timestamp,
7362 uint32_t flags __rte_unused)
7364 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7365 struct ixgbe_adapter *adapter = dev->data->dev_private;
7366 uint32_t tsync_rxctl;
7367 uint64_t rx_tstamp_cycles;
7370 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7371 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7374 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7375 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7376 *timestamp = rte_ns_to_timespec(ns);
7382 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7383 struct timespec *timestamp)
7385 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7386 struct ixgbe_adapter *adapter = dev->data->dev_private;
7387 uint32_t tsync_txctl;
7388 uint64_t tx_tstamp_cycles;
7391 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7392 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7395 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7396 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7397 *timestamp = rte_ns_to_timespec(ns);
7403 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7405 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7408 const struct reg_info *reg_group;
7409 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7410 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7412 while ((reg_group = reg_set[g_ind++]))
7413 count += ixgbe_regs_group_count(reg_group);
7419 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7423 const struct reg_info *reg_group;
7425 while ((reg_group = ixgbevf_regs[g_ind++]))
7426 count += ixgbe_regs_group_count(reg_group);
7432 ixgbe_get_regs(struct rte_eth_dev *dev,
7433 struct rte_dev_reg_info *regs)
7435 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7436 uint32_t *data = regs->data;
7439 const struct reg_info *reg_group;
7440 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7441 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7444 regs->length = ixgbe_get_reg_length(dev);
7445 regs->width = sizeof(uint32_t);
7449 /* Support only full register dump */
7450 if ((regs->length == 0) ||
7451 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7452 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7454 while ((reg_group = reg_set[g_ind++]))
7455 count += ixgbe_read_regs_group(dev, &data[count],
7464 ixgbevf_get_regs(struct rte_eth_dev *dev,
7465 struct rte_dev_reg_info *regs)
7467 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7468 uint32_t *data = regs->data;
7471 const struct reg_info *reg_group;
7474 regs->length = ixgbevf_get_reg_length(dev);
7475 regs->width = sizeof(uint32_t);
7479 /* Support only full register dump */
7480 if ((regs->length == 0) ||
7481 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7482 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7484 while ((reg_group = ixgbevf_regs[g_ind++]))
7485 count += ixgbe_read_regs_group(dev, &data[count],
7494 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7496 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7498 /* Return unit is byte count */
7499 return hw->eeprom.word_size * 2;
7503 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7504 struct rte_dev_eeprom_info *in_eeprom)
7506 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7507 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7508 uint16_t *data = in_eeprom->data;
7511 first = in_eeprom->offset >> 1;
7512 length = in_eeprom->length >> 1;
7513 if ((first > hw->eeprom.word_size) ||
7514 ((first + length) > hw->eeprom.word_size))
7517 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7519 return eeprom->ops.read_buffer(hw, first, length, data);
7523 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7524 struct rte_dev_eeprom_info *in_eeprom)
7526 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7527 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7528 uint16_t *data = in_eeprom->data;
7531 first = in_eeprom->offset >> 1;
7532 length = in_eeprom->length >> 1;
7533 if ((first > hw->eeprom.word_size) ||
7534 ((first + length) > hw->eeprom.word_size))
7537 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7539 return eeprom->ops.write_buffer(hw, first, length, data);
7543 ixgbe_get_module_info(struct rte_eth_dev *dev,
7544 struct rte_eth_dev_module_info *modinfo)
7546 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7548 uint8_t sff8472_rev, addr_mode;
7549 bool page_swap = false;
7551 /* Check whether we support SFF-8472 or not */
7552 status = hw->phy.ops.read_i2c_eeprom(hw,
7553 IXGBE_SFF_SFF_8472_COMP,
7558 /* addressing mode is not supported */
7559 status = hw->phy.ops.read_i2c_eeprom(hw,
7560 IXGBE_SFF_SFF_8472_SWAP,
7565 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7567 "Address change required to access page 0xA2, "
7568 "but not supported. Please report the module "
7569 "type to the driver maintainers.");
7573 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7574 /* We have a SFP, but it does not support SFF-8472 */
7575 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7576 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7578 /* We have a SFP which supports a revision of SFF-8472. */
7579 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7580 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7587 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7588 struct rte_dev_eeprom_info *info)
7590 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7591 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7592 uint8_t databyte = 0xFF;
7593 uint8_t *data = info->data;
7596 if (info->length == 0)
7599 for (i = info->offset; i < info->offset + info->length; i++) {
7600 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7601 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7603 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7608 data[i - info->offset] = databyte;
7615 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7617 case ixgbe_mac_X550:
7618 case ixgbe_mac_X550EM_x:
7619 case ixgbe_mac_X550EM_a:
7620 return ETH_RSS_RETA_SIZE_512;
7621 case ixgbe_mac_X550_vf:
7622 case ixgbe_mac_X550EM_x_vf:
7623 case ixgbe_mac_X550EM_a_vf:
7624 return ETH_RSS_RETA_SIZE_64;
7625 case ixgbe_mac_X540_vf:
7626 case ixgbe_mac_82599_vf:
7629 return ETH_RSS_RETA_SIZE_128;
7634 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7636 case ixgbe_mac_X550:
7637 case ixgbe_mac_X550EM_x:
7638 case ixgbe_mac_X550EM_a:
7639 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7640 return IXGBE_RETA(reta_idx >> 2);
7642 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7643 case ixgbe_mac_X550_vf:
7644 case ixgbe_mac_X550EM_x_vf:
7645 case ixgbe_mac_X550EM_a_vf:
7646 return IXGBE_VFRETA(reta_idx >> 2);
7648 return IXGBE_RETA(reta_idx >> 2);
7653 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7655 case ixgbe_mac_X550_vf:
7656 case ixgbe_mac_X550EM_x_vf:
7657 case ixgbe_mac_X550EM_a_vf:
7658 return IXGBE_VFMRQC;
7665 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7667 case ixgbe_mac_X550_vf:
7668 case ixgbe_mac_X550EM_x_vf:
7669 case ixgbe_mac_X550EM_a_vf:
7670 return IXGBE_VFRSSRK(i);
7672 return IXGBE_RSSRK(i);
7677 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7679 case ixgbe_mac_82599_vf:
7680 case ixgbe_mac_X540_vf:
7688 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7689 struct rte_eth_dcb_info *dcb_info)
7691 struct ixgbe_dcb_config *dcb_config =
7692 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7693 struct ixgbe_dcb_tc_config *tc;
7694 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7698 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7699 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7701 dcb_info->nb_tcs = 1;
7703 tc_queue = &dcb_info->tc_queue;
7704 nb_tcs = dcb_info->nb_tcs;
7706 if (dcb_config->vt_mode) { /* vt is enabled*/
7707 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7708 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7709 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7710 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7711 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7712 for (j = 0; j < nb_tcs; j++) {
7713 tc_queue->tc_rxq[0][j].base = j;
7714 tc_queue->tc_rxq[0][j].nb_queue = 1;
7715 tc_queue->tc_txq[0][j].base = j;
7716 tc_queue->tc_txq[0][j].nb_queue = 1;
7719 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7720 for (j = 0; j < nb_tcs; j++) {
7721 tc_queue->tc_rxq[i][j].base =
7723 tc_queue->tc_rxq[i][j].nb_queue = 1;
7724 tc_queue->tc_txq[i][j].base =
7726 tc_queue->tc_txq[i][j].nb_queue = 1;
7730 } else { /* vt is disabled*/
7731 struct rte_eth_dcb_rx_conf *rx_conf =
7732 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7733 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7734 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7735 if (dcb_info->nb_tcs == ETH_4_TCS) {
7736 for (i = 0; i < dcb_info->nb_tcs; i++) {
7737 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7738 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7740 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7741 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7742 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7743 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7744 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7745 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7746 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7747 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7748 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7749 for (i = 0; i < dcb_info->nb_tcs; i++) {
7750 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7751 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7753 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7754 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7755 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7756 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7757 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7758 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7759 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7760 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7761 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7762 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7763 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7764 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7765 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7766 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7767 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7768 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7771 for (i = 0; i < dcb_info->nb_tcs; i++) {
7772 tc = &dcb_config->tc_config[i];
7773 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7778 /* Update e-tag ether type */
7780 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7781 uint16_t ether_type)
7783 uint32_t etag_etype;
7785 if (hw->mac.type != ixgbe_mac_X550 &&
7786 hw->mac.type != ixgbe_mac_X550EM_x &&
7787 hw->mac.type != ixgbe_mac_X550EM_a) {
7791 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7792 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7793 etag_etype |= ether_type;
7794 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7795 IXGBE_WRITE_FLUSH(hw);
7800 /* Config l2 tunnel ether type */
7802 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7803 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7806 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7807 struct ixgbe_l2_tn_info *l2_tn_info =
7808 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7810 if (l2_tunnel == NULL)
7813 switch (l2_tunnel->l2_tunnel_type) {
7814 case RTE_L2_TUNNEL_TYPE_E_TAG:
7815 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7816 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7819 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7827 /* Enable e-tag tunnel */
7829 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7831 uint32_t etag_etype;
7833 if (hw->mac.type != ixgbe_mac_X550 &&
7834 hw->mac.type != ixgbe_mac_X550EM_x &&
7835 hw->mac.type != ixgbe_mac_X550EM_a) {
7839 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7840 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7841 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7842 IXGBE_WRITE_FLUSH(hw);
7847 /* Enable l2 tunnel */
7849 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7850 enum rte_eth_tunnel_type l2_tunnel_type)
7853 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7854 struct ixgbe_l2_tn_info *l2_tn_info =
7855 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7857 switch (l2_tunnel_type) {
7858 case RTE_L2_TUNNEL_TYPE_E_TAG:
7859 l2_tn_info->e_tag_en = TRUE;
7860 ret = ixgbe_e_tag_enable(hw);
7863 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7871 /* Disable e-tag tunnel */
7873 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7875 uint32_t etag_etype;
7877 if (hw->mac.type != ixgbe_mac_X550 &&
7878 hw->mac.type != ixgbe_mac_X550EM_x &&
7879 hw->mac.type != ixgbe_mac_X550EM_a) {
7883 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7884 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7885 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7886 IXGBE_WRITE_FLUSH(hw);
7891 /* Disable l2 tunnel */
7893 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7894 enum rte_eth_tunnel_type l2_tunnel_type)
7897 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7898 struct ixgbe_l2_tn_info *l2_tn_info =
7899 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7901 switch (l2_tunnel_type) {
7902 case RTE_L2_TUNNEL_TYPE_E_TAG:
7903 l2_tn_info->e_tag_en = FALSE;
7904 ret = ixgbe_e_tag_disable(hw);
7907 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7916 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7917 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7920 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7921 uint32_t i, rar_entries;
7922 uint32_t rar_low, rar_high;
7924 if (hw->mac.type != ixgbe_mac_X550 &&
7925 hw->mac.type != ixgbe_mac_X550EM_x &&
7926 hw->mac.type != ixgbe_mac_X550EM_a) {
7930 rar_entries = ixgbe_get_num_rx_addrs(hw);
7932 for (i = 1; i < rar_entries; i++) {
7933 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7934 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7935 if ((rar_high & IXGBE_RAH_AV) &&
7936 (rar_high & IXGBE_RAH_ADTYPE) &&
7937 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7938 l2_tunnel->tunnel_id)) {
7939 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7940 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7942 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7952 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7953 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7956 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7957 uint32_t i, rar_entries;
7958 uint32_t rar_low, rar_high;
7960 if (hw->mac.type != ixgbe_mac_X550 &&
7961 hw->mac.type != ixgbe_mac_X550EM_x &&
7962 hw->mac.type != ixgbe_mac_X550EM_a) {
7966 /* One entry for one tunnel. Try to remove potential existing entry. */
7967 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7969 rar_entries = ixgbe_get_num_rx_addrs(hw);
7971 for (i = 1; i < rar_entries; i++) {
7972 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7973 if (rar_high & IXGBE_RAH_AV) {
7976 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7977 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7978 rar_low = l2_tunnel->tunnel_id;
7980 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7981 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7987 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7988 " Please remove a rule before adding a new one.");
7992 static inline struct ixgbe_l2_tn_filter *
7993 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7994 struct ixgbe_l2_tn_key *key)
7998 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
8002 return l2_tn_info->hash_map[ret];
8006 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8007 struct ixgbe_l2_tn_filter *l2_tn_filter)
8011 ret = rte_hash_add_key(l2_tn_info->hash_handle,
8012 &l2_tn_filter->key);
8016 "Failed to insert L2 tunnel filter"
8017 " to hash table %d!",
8022 l2_tn_info->hash_map[ret] = l2_tn_filter;
8024 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8030 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8031 struct ixgbe_l2_tn_key *key)
8034 struct ixgbe_l2_tn_filter *l2_tn_filter;
8036 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
8040 "No such L2 tunnel filter to delete %d!",
8045 l2_tn_filter = l2_tn_info->hash_map[ret];
8046 l2_tn_info->hash_map[ret] = NULL;
8048 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8049 rte_free(l2_tn_filter);
8054 /* Add l2 tunnel filter */
8056 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
8057 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8061 struct ixgbe_l2_tn_info *l2_tn_info =
8062 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8063 struct ixgbe_l2_tn_key key;
8064 struct ixgbe_l2_tn_filter *node;
8067 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8068 key.tn_id = l2_tunnel->tunnel_id;
8070 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
8074 "The L2 tunnel filter already exists!");
8078 node = rte_zmalloc("ixgbe_l2_tn",
8079 sizeof(struct ixgbe_l2_tn_filter),
8084 rte_memcpy(&node->key,
8086 sizeof(struct ixgbe_l2_tn_key));
8087 node->pool = l2_tunnel->pool;
8088 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
8095 switch (l2_tunnel->l2_tunnel_type) {
8096 case RTE_L2_TUNNEL_TYPE_E_TAG:
8097 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
8100 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8105 if ((!restore) && (ret < 0))
8106 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8111 /* Delete l2 tunnel filter */
8113 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
8114 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8117 struct ixgbe_l2_tn_info *l2_tn_info =
8118 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8119 struct ixgbe_l2_tn_key key;
8121 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8122 key.tn_id = l2_tunnel->tunnel_id;
8123 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8127 switch (l2_tunnel->l2_tunnel_type) {
8128 case RTE_L2_TUNNEL_TYPE_E_TAG:
8129 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8132 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8141 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8142 * @dev: pointer to rte_eth_dev structure
8143 * @filter_op:operation will be taken.
8144 * @arg: a pointer to specific structure corresponding to the filter_op
8147 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8148 enum rte_filter_op filter_op,
8153 if (filter_op == RTE_ETH_FILTER_NOP)
8157 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8162 switch (filter_op) {
8163 case RTE_ETH_FILTER_ADD:
8164 ret = ixgbe_dev_l2_tunnel_filter_add
8166 (struct rte_eth_l2_tunnel_conf *)arg,
8169 case RTE_ETH_FILTER_DELETE:
8170 ret = ixgbe_dev_l2_tunnel_filter_del
8172 (struct rte_eth_l2_tunnel_conf *)arg);
8175 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8183 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8187 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8189 if (hw->mac.type != ixgbe_mac_X550 &&
8190 hw->mac.type != ixgbe_mac_X550EM_x &&
8191 hw->mac.type != ixgbe_mac_X550EM_a) {
8195 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8196 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8198 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8199 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8204 /* Enable l2 tunnel forwarding */
8206 ixgbe_dev_l2_tunnel_forwarding_enable
8207 (struct rte_eth_dev *dev,
8208 enum rte_eth_tunnel_type l2_tunnel_type)
8210 struct ixgbe_l2_tn_info *l2_tn_info =
8211 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8214 switch (l2_tunnel_type) {
8215 case RTE_L2_TUNNEL_TYPE_E_TAG:
8216 l2_tn_info->e_tag_fwd_en = TRUE;
8217 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8220 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8228 /* Disable l2 tunnel forwarding */
8230 ixgbe_dev_l2_tunnel_forwarding_disable
8231 (struct rte_eth_dev *dev,
8232 enum rte_eth_tunnel_type l2_tunnel_type)
8234 struct ixgbe_l2_tn_info *l2_tn_info =
8235 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8238 switch (l2_tunnel_type) {
8239 case RTE_L2_TUNNEL_TYPE_E_TAG:
8240 l2_tn_info->e_tag_fwd_en = FALSE;
8241 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8244 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8253 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8254 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8257 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8259 uint32_t vmtir, vmvir;
8260 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8262 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8264 "VF id %u should be less than %u",
8270 if (hw->mac.type != ixgbe_mac_X550 &&
8271 hw->mac.type != ixgbe_mac_X550EM_x &&
8272 hw->mac.type != ixgbe_mac_X550EM_a) {
8277 vmtir = l2_tunnel->tunnel_id;
8281 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8283 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8284 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8286 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8287 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8292 /* Enable l2 tunnel tag insertion */
8294 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8295 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8299 switch (l2_tunnel->l2_tunnel_type) {
8300 case RTE_L2_TUNNEL_TYPE_E_TAG:
8301 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8304 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8312 /* Disable l2 tunnel tag insertion */
8314 ixgbe_dev_l2_tunnel_insertion_disable
8315 (struct rte_eth_dev *dev,
8316 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8320 switch (l2_tunnel->l2_tunnel_type) {
8321 case RTE_L2_TUNNEL_TYPE_E_TAG:
8322 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8325 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8334 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8339 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8341 if (hw->mac.type != ixgbe_mac_X550 &&
8342 hw->mac.type != ixgbe_mac_X550EM_x &&
8343 hw->mac.type != ixgbe_mac_X550EM_a) {
8347 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8349 qde |= IXGBE_QDE_STRIP_TAG;
8351 qde &= ~IXGBE_QDE_STRIP_TAG;
8352 qde &= ~IXGBE_QDE_READ;
8353 qde |= IXGBE_QDE_WRITE;
8354 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8359 /* Enable l2 tunnel tag stripping */
8361 ixgbe_dev_l2_tunnel_stripping_enable
8362 (struct rte_eth_dev *dev,
8363 enum rte_eth_tunnel_type l2_tunnel_type)
8367 switch (l2_tunnel_type) {
8368 case RTE_L2_TUNNEL_TYPE_E_TAG:
8369 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8372 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8380 /* Disable l2 tunnel tag stripping */
8382 ixgbe_dev_l2_tunnel_stripping_disable
8383 (struct rte_eth_dev *dev,
8384 enum rte_eth_tunnel_type l2_tunnel_type)
8388 switch (l2_tunnel_type) {
8389 case RTE_L2_TUNNEL_TYPE_E_TAG:
8390 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8393 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8401 /* Enable/disable l2 tunnel offload functions */
8403 ixgbe_dev_l2_tunnel_offload_set
8404 (struct rte_eth_dev *dev,
8405 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8411 if (l2_tunnel == NULL)
8415 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8417 ret = ixgbe_dev_l2_tunnel_enable(
8419 l2_tunnel->l2_tunnel_type);
8421 ret = ixgbe_dev_l2_tunnel_disable(
8423 l2_tunnel->l2_tunnel_type);
8426 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8428 ret = ixgbe_dev_l2_tunnel_insertion_enable(
8432 ret = ixgbe_dev_l2_tunnel_insertion_disable(
8437 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8439 ret = ixgbe_dev_l2_tunnel_stripping_enable(
8441 l2_tunnel->l2_tunnel_type);
8443 ret = ixgbe_dev_l2_tunnel_stripping_disable(
8445 l2_tunnel->l2_tunnel_type);
8448 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8450 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8452 l2_tunnel->l2_tunnel_type);
8454 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8456 l2_tunnel->l2_tunnel_type);
8463 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8466 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8467 IXGBE_WRITE_FLUSH(hw);
8472 /* There's only one register for VxLAN UDP port.
8473 * So, we cannot add several ports. Will update it.
8476 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8480 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8484 return ixgbe_update_vxlan_port(hw, port);
8487 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8488 * UDP port, it must have a value.
8489 * So, will reset it to the original value 0.
8492 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8497 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8499 if (cur_port != port) {
8500 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8504 return ixgbe_update_vxlan_port(hw, 0);
8507 /* Add UDP tunneling port */
8509 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8510 struct rte_eth_udp_tunnel *udp_tunnel)
8513 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8515 if (hw->mac.type != ixgbe_mac_X550 &&
8516 hw->mac.type != ixgbe_mac_X550EM_x &&
8517 hw->mac.type != ixgbe_mac_X550EM_a) {
8521 if (udp_tunnel == NULL)
8524 switch (udp_tunnel->prot_type) {
8525 case RTE_TUNNEL_TYPE_VXLAN:
8526 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8529 case RTE_TUNNEL_TYPE_GENEVE:
8530 case RTE_TUNNEL_TYPE_TEREDO:
8531 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8536 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8544 /* Remove UDP tunneling port */
8546 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8547 struct rte_eth_udp_tunnel *udp_tunnel)
8550 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8552 if (hw->mac.type != ixgbe_mac_X550 &&
8553 hw->mac.type != ixgbe_mac_X550EM_x &&
8554 hw->mac.type != ixgbe_mac_X550EM_a) {
8558 if (udp_tunnel == NULL)
8561 switch (udp_tunnel->prot_type) {
8562 case RTE_TUNNEL_TYPE_VXLAN:
8563 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8565 case RTE_TUNNEL_TYPE_GENEVE:
8566 case RTE_TUNNEL_TYPE_TEREDO:
8567 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8571 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8580 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8582 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8585 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8589 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8601 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8603 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8606 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8610 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8622 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8624 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8626 int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8628 switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8632 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8644 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8646 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8649 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8653 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8664 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8666 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8669 /* peek the message first */
8670 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8672 /* PF reset VF event */
8673 if (in_msg == IXGBE_PF_CONTROL_MSG) {
8674 /* dummy mbx read to ack pf */
8675 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8677 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8683 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8686 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8687 struct ixgbe_interrupt *intr =
8688 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8689 ixgbevf_intr_disable(dev);
8691 /* read-on-clear nic registers here */
8692 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8695 /* only one misc vector supported - mailbox */
8696 eicr &= IXGBE_VTEICR_MASK;
8697 if (eicr == IXGBE_MISC_VEC_ID)
8698 intr->flags |= IXGBE_FLAG_MAILBOX;
8704 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8706 struct ixgbe_interrupt *intr =
8707 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8709 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8710 ixgbevf_mbx_process(dev);
8711 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8714 ixgbevf_intr_enable(dev);
8720 ixgbevf_dev_interrupt_handler(void *param)
8722 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8724 ixgbevf_dev_interrupt_get_status(dev);
8725 ixgbevf_dev_interrupt_action(dev);
8729 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8730 * @hw: pointer to hardware structure
8732 * Stops the transmit data path and waits for the HW to internally empty
8733 * the Tx security block
8735 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8737 #define IXGBE_MAX_SECTX_POLL 40
8742 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8743 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8744 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8745 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8746 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8747 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8749 /* Use interrupt-safe sleep just in case */
8753 /* For informational purposes only */
8754 if (i >= IXGBE_MAX_SECTX_POLL)
8755 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8756 "path fully disabled. Continuing with init.");
8758 return IXGBE_SUCCESS;
8762 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8763 * @hw: pointer to hardware structure
8765 * Enables the transmit data path.
8767 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8771 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8772 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8773 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8774 IXGBE_WRITE_FLUSH(hw);
8776 return IXGBE_SUCCESS;
8779 /* restore n-tuple filter */
8781 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8783 struct ixgbe_filter_info *filter_info =
8784 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8785 struct ixgbe_5tuple_filter *node;
8787 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8788 ixgbe_inject_5tuple_filter(dev, node);
8792 /* restore ethernet type filter */
8794 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8796 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8797 struct ixgbe_filter_info *filter_info =
8798 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8801 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8802 if (filter_info->ethertype_mask & (1 << i)) {
8803 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8804 filter_info->ethertype_filters[i].etqf);
8805 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8806 filter_info->ethertype_filters[i].etqs);
8807 IXGBE_WRITE_FLUSH(hw);
8812 /* restore SYN filter */
8814 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8816 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8817 struct ixgbe_filter_info *filter_info =
8818 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8821 synqf = filter_info->syn_info;
8823 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8824 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8825 IXGBE_WRITE_FLUSH(hw);
8829 /* restore L2 tunnel filter */
8831 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8833 struct ixgbe_l2_tn_info *l2_tn_info =
8834 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8835 struct ixgbe_l2_tn_filter *node;
8836 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8838 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8839 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8840 l2_tn_conf.tunnel_id = node->key.tn_id;
8841 l2_tn_conf.pool = node->pool;
8842 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8846 /* restore rss filter */
8848 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8850 struct ixgbe_filter_info *filter_info =
8851 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8853 if (filter_info->rss_info.conf.queue_num)
8854 ixgbe_config_rss_filter(dev,
8855 &filter_info->rss_info, TRUE);
8859 ixgbe_filter_restore(struct rte_eth_dev *dev)
8861 ixgbe_ntuple_filter_restore(dev);
8862 ixgbe_ethertype_filter_restore(dev);
8863 ixgbe_syn_filter_restore(dev);
8864 ixgbe_fdir_filter_restore(dev);
8865 ixgbe_l2_tn_filter_restore(dev);
8866 ixgbe_rss_filter_restore(dev);
8872 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8874 struct ixgbe_l2_tn_info *l2_tn_info =
8875 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8876 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8878 if (l2_tn_info->e_tag_en)
8879 (void)ixgbe_e_tag_enable(hw);
8881 if (l2_tn_info->e_tag_fwd_en)
8882 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8884 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8887 /* remove all the n-tuple filters */
8889 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8891 struct ixgbe_filter_info *filter_info =
8892 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8893 struct ixgbe_5tuple_filter *p_5tuple;
8895 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8896 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8899 /* remove all the ether type filters */
8901 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8903 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8904 struct ixgbe_filter_info *filter_info =
8905 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8908 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8909 if (filter_info->ethertype_mask & (1 << i) &&
8910 !filter_info->ethertype_filters[i].conf) {
8911 (void)ixgbe_ethertype_filter_remove(filter_info,
8913 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8914 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8915 IXGBE_WRITE_FLUSH(hw);
8920 /* remove the SYN filter */
8922 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8924 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8925 struct ixgbe_filter_info *filter_info =
8926 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8928 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8929 filter_info->syn_info = 0;
8931 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8932 IXGBE_WRITE_FLUSH(hw);
8936 /* remove all the L2 tunnel filters */
8938 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8940 struct ixgbe_l2_tn_info *l2_tn_info =
8941 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8942 struct ixgbe_l2_tn_filter *l2_tn_filter;
8943 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8946 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8947 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8948 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8949 l2_tn_conf.pool = l2_tn_filter->pool;
8950 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8959 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8960 struct ixgbe_macsec_setting *macsec_setting)
8962 struct ixgbe_macsec_setting *macsec =
8963 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8965 macsec->offload_en = macsec_setting->offload_en;
8966 macsec->encrypt_en = macsec_setting->encrypt_en;
8967 macsec->replayprotect_en = macsec_setting->replayprotect_en;
8971 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8973 struct ixgbe_macsec_setting *macsec =
8974 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8976 macsec->offload_en = 0;
8977 macsec->encrypt_en = 0;
8978 macsec->replayprotect_en = 0;
8982 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8983 struct ixgbe_macsec_setting *macsec_setting)
8985 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8987 uint8_t en = macsec_setting->encrypt_en;
8988 uint8_t rp = macsec_setting->replayprotect_en;
8992 * As no ixgbe_disable_sec_rx_path equivalent is
8993 * implemented for tx in the base code, and we are
8994 * not allowed to modify the base code in DPDK, so
8995 * just call the hand-written one directly for now.
8996 * The hardware support has been checked by
8997 * ixgbe_disable_sec_rx_path().
8999 ixgbe_disable_sec_tx_path_generic(hw);
9001 /* Enable Ethernet CRC (required by MACsec offload) */
9002 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
9003 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
9004 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
9006 /* Enable the TX and RX crypto engines */
9007 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9008 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
9009 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9011 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9012 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
9013 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9015 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
9016 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
9018 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
9020 /* Enable SA lookup */
9021 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9022 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9023 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
9024 IXGBE_LSECTXCTRL_AUTH;
9025 ctrl |= IXGBE_LSECTXCTRL_AISCI;
9026 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9027 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9028 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9030 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9031 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9032 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
9033 ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
9035 ctrl |= IXGBE_LSECRXCTRL_RP;
9037 ctrl &= ~IXGBE_LSECRXCTRL_RP;
9038 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9040 /* Start the data paths */
9041 ixgbe_enable_sec_rx_path(hw);
9044 * As no ixgbe_enable_sec_rx_path equivalent is
9045 * implemented for tx in the base code, and we are
9046 * not allowed to modify the base code in DPDK, so
9047 * just call the hand-written one directly for now.
9049 ixgbe_enable_sec_tx_path_generic(hw);
9053 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
9055 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9060 * As no ixgbe_disable_sec_rx_path equivalent is
9061 * implemented for tx in the base code, and we are
9062 * not allowed to modify the base code in DPDK, so
9063 * just call the hand-written one directly for now.
9064 * The hardware support has been checked by
9065 * ixgbe_disable_sec_rx_path().
9067 ixgbe_disable_sec_tx_path_generic(hw);
9069 /* Disable the TX and RX crypto engines */
9070 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9071 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
9072 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9074 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9075 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
9076 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9078 /* Disable SA lookup */
9079 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9080 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9081 ctrl |= IXGBE_LSECTXCTRL_DISABLE;
9082 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9084 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9085 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9086 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
9087 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9089 /* Start the data paths */
9090 ixgbe_enable_sec_rx_path(hw);
9093 * As no ixgbe_enable_sec_rx_path equivalent is
9094 * implemented for tx in the base code, and we are
9095 * not allowed to modify the base code in DPDK, so
9096 * just call the hand-written one directly for now.
9098 ixgbe_enable_sec_tx_path_generic(hw);
9101 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
9102 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
9103 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
9104 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
9105 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
9106 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
9107 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
9108 IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
9110 RTE_LOG_REGISTER(ixgbe_logtype_init, pmd.net.ixgbe.init, NOTICE);
9111 RTE_LOG_REGISTER(ixgbe_logtype_driver, pmd.net.ixgbe.driver, NOTICE);
9113 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
9114 RTE_LOG_REGISTER(ixgbe_logtype_rx, pmd.net.ixgbe.rx, DEBUG);
9116 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
9117 RTE_LOG_REGISTER(ixgbe_logtype_tx, pmd.net.ixgbe.tx, DEBUG);
9119 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9120 RTE_LOG_REGISTER(ixgbe_logtype_tx_free, pmd.net.ixgbe.tx_free, DEBUG);