1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
13 #include <netinet/in.h>
14 #include <rte_byteorder.h>
15 #include <rte_common.h>
16 #include <rte_cycles.h>
18 #include <rte_interrupts.h>
20 #include <rte_debug.h>
22 #include <rte_bus_pci.h>
23 #include <rte_atomic.h>
24 #include <rte_branch_prediction.h>
25 #include <rte_memory.h>
27 #include <rte_alarm.h>
28 #include <rte_ether.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_ethdev_pci.h>
31 #include <rte_malloc.h>
32 #include <rte_random.h>
34 #include <rte_hash_crc.h>
35 #ifdef RTE_LIBRTE_SECURITY
36 #include <rte_security_driver.h>
39 #include "ixgbe_logs.h"
40 #include "base/ixgbe_api.h"
41 #include "base/ixgbe_vf.h"
42 #include "base/ixgbe_common.h"
43 #include "ixgbe_ethdev.h"
44 #include "ixgbe_bypass.h"
45 #include "ixgbe_rxtx.h"
46 #include "base/ixgbe_type.h"
47 #include "base/ixgbe_phy.h"
48 #include "ixgbe_regs.h"
51 * High threshold controlling when to start sending XOFF frames. Must be at
52 * least 8 bytes less than receive packet buffer size. This value is in units
55 #define IXGBE_FC_HI 0x80
58 * Low threshold controlling when to start sending XON frames. This value is
59 * in units of 1024 bytes.
61 #define IXGBE_FC_LO 0x40
63 /* Default minimum inter-interrupt interval for EITR configuration */
64 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
66 /* Timer value included in XOFF frames. */
67 #define IXGBE_FC_PAUSE 0x680
69 /*Default value of Max Rx Queue*/
70 #define IXGBE_MAX_RX_QUEUE_NUM 128
72 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
73 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
74 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
76 #define IXGBE_MMW_SIZE_DEFAULT 0x4
77 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
78 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
81 * Default values for RX/TX configuration
83 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
84 #define IXGBE_DEFAULT_RX_PTHRESH 8
85 #define IXGBE_DEFAULT_RX_HTHRESH 8
86 #define IXGBE_DEFAULT_RX_WTHRESH 0
88 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
89 #define IXGBE_DEFAULT_TX_PTHRESH 32
90 #define IXGBE_DEFAULT_TX_HTHRESH 0
91 #define IXGBE_DEFAULT_TX_WTHRESH 0
92 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
94 /* Bit shift and mask */
95 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
96 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
97 #define IXGBE_8_BIT_WIDTH CHAR_BIT
98 #define IXGBE_8_BIT_MASK UINT8_MAX
100 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
102 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
104 #define IXGBE_HKEY_MAX_INDEX 10
106 /* Additional timesync values. */
107 #define NSEC_PER_SEC 1000000000L
108 #define IXGBE_INCVAL_10GB 0x66666666
109 #define IXGBE_INCVAL_1GB 0x40000000
110 #define IXGBE_INCVAL_100 0x50000000
111 #define IXGBE_INCVAL_SHIFT_10GB 28
112 #define IXGBE_INCVAL_SHIFT_1GB 24
113 #define IXGBE_INCVAL_SHIFT_100 21
114 #define IXGBE_INCVAL_SHIFT_82599 7
115 #define IXGBE_INCPER_SHIFT_82599 24
117 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
119 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
120 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
121 #define DEFAULT_ETAG_ETYPE 0x893f
122 #define IXGBE_ETAG_ETYPE 0x00005084
123 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
124 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
125 #define IXGBE_RAH_ADTYPE 0x40000000
126 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
127 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
128 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
129 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
130 #define IXGBE_QDE_STRIP_TAG 0x00000004
131 #define IXGBE_VTEICR_MASK 0x07
133 #define IXGBE_EXVET_VET_EXT_SHIFT 16
134 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
136 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
137 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
138 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
139 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
140 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
141 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
142 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
143 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
144 static int ixgbe_dev_start(struct rte_eth_dev *dev);
145 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
146 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
147 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
148 static void ixgbe_dev_close(struct rte_eth_dev *dev);
149 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
150 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
151 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
152 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
153 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
154 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
155 int wait_to_complete);
156 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
157 struct rte_eth_stats *stats);
158 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
159 struct rte_eth_xstat *xstats, unsigned n);
160 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
161 struct rte_eth_xstat *xstats, unsigned n);
163 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
164 uint64_t *values, unsigned int n);
165 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
166 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
167 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
168 struct rte_eth_xstat_name *xstats_names,
170 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
171 struct rte_eth_xstat_name *xstats_names, unsigned limit);
172 static int ixgbe_dev_xstats_get_names_by_id(
173 struct rte_eth_dev *dev,
174 struct rte_eth_xstat_name *xstats_names,
177 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
181 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
183 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
184 struct rte_eth_dev_info *dev_info);
185 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
186 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
187 struct rte_eth_dev_info *dev_info);
188 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
190 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
191 uint16_t vlan_id, int on);
192 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
193 enum rte_vlan_type vlan_type,
195 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
196 uint16_t queue, bool on);
197 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
199 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
200 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
201 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
202 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
203 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
205 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
206 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
207 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
208 struct rte_eth_fc_conf *fc_conf);
209 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
210 struct rte_eth_fc_conf *fc_conf);
211 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
212 struct rte_eth_pfc_conf *pfc_conf);
213 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
214 struct rte_eth_rss_reta_entry64 *reta_conf,
216 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
217 struct rte_eth_rss_reta_entry64 *reta_conf,
219 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
220 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
221 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
222 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
223 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
224 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
225 struct rte_intr_handle *handle);
226 static void ixgbe_dev_interrupt_handler(void *param);
227 static void ixgbe_dev_interrupt_delayed_handler(void *param);
228 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
229 uint32_t index, uint32_t pool);
230 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
231 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
232 struct ether_addr *mac_addr);
233 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
234 static bool is_device_supported(struct rte_eth_dev *dev,
235 struct rte_pci_driver *drv);
237 /* For Virtual Function support */
238 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
239 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
240 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
241 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
242 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
243 int wait_to_complete);
244 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
245 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
246 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
247 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
248 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
249 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
250 struct rte_eth_stats *stats);
251 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
252 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
253 uint16_t vlan_id, int on);
254 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
255 uint16_t queue, int on);
256 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
257 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
258 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
260 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
262 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
263 uint8_t queue, uint8_t msix_vector);
264 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
265 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
266 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
268 /* For Eth VMDQ APIs support */
269 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
270 ether_addr * mac_addr, uint8_t on);
271 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
272 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
273 struct rte_eth_mirror_conf *mirror_conf,
274 uint8_t rule_id, uint8_t on);
275 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
277 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
279 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
281 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
282 uint8_t queue, uint8_t msix_vector);
283 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
285 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
286 struct ether_addr *mac_addr,
287 uint32_t index, uint32_t pool);
288 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
289 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
290 struct ether_addr *mac_addr);
291 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
292 struct rte_eth_syn_filter *filter);
293 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
294 enum rte_filter_op filter_op,
296 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
297 struct ixgbe_5tuple_filter *filter);
298 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
299 struct ixgbe_5tuple_filter *filter);
300 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
301 enum rte_filter_op filter_op,
303 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
304 struct rte_eth_ntuple_filter *filter);
305 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
306 enum rte_filter_op filter_op,
308 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
309 struct rte_eth_ethertype_filter *filter);
310 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
311 enum rte_filter_type filter_type,
312 enum rte_filter_op filter_op,
314 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
316 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
317 struct ether_addr *mc_addr_set,
318 uint32_t nb_mc_addr);
319 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
320 struct rte_eth_dcb_info *dcb_info);
322 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
323 static int ixgbe_get_regs(struct rte_eth_dev *dev,
324 struct rte_dev_reg_info *regs);
325 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
326 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
327 struct rte_dev_eeprom_info *eeprom);
328 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
329 struct rte_dev_eeprom_info *eeprom);
331 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
332 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
333 struct rte_dev_reg_info *regs);
335 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
336 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
337 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
338 struct timespec *timestamp,
340 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
341 struct timespec *timestamp);
342 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
343 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
344 struct timespec *timestamp);
345 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
346 const struct timespec *timestamp);
347 static void ixgbevf_dev_interrupt_handler(void *param);
349 static int ixgbe_dev_l2_tunnel_eth_type_conf
350 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
351 static int ixgbe_dev_l2_tunnel_offload_set
352 (struct rte_eth_dev *dev,
353 struct rte_eth_l2_tunnel_conf *l2_tunnel,
356 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
357 enum rte_filter_op filter_op,
360 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
361 struct rte_eth_udp_tunnel *udp_tunnel);
362 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
363 struct rte_eth_udp_tunnel *udp_tunnel);
364 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
365 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
368 * Define VF Stats MACRO for Non "cleared on read" register
370 #define UPDATE_VF_STAT(reg, last, cur) \
372 uint32_t latest = IXGBE_READ_REG(hw, reg); \
373 cur += (latest - last) & UINT_MAX; \
377 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
379 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
380 u64 new_msb = IXGBE_READ_REG(hw, msb); \
381 u64 latest = ((new_msb << 32) | new_lsb); \
382 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
386 #define IXGBE_SET_HWSTRIP(h, q) do {\
387 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
388 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
389 (h)->bitmap[idx] |= 1 << bit;\
392 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
393 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
394 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
395 (h)->bitmap[idx] &= ~(1 << bit);\
398 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
399 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
400 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
401 (r) = (h)->bitmap[idx] >> bit & 1;\
404 int ixgbe_logtype_init;
405 int ixgbe_logtype_driver;
408 * The set of PCI devices this driver supports
410 static const struct rte_pci_id pci_id_ixgbe_map[] = {
411 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
412 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
413 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
414 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
415 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
416 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
417 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
418 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
419 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
420 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
421 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
422 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
423 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
424 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
425 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
459 #ifdef RTE_LIBRTE_IXGBE_BYPASS
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
462 { .vendor_id = 0, /* sentinel */ },
466 * The set of PCI devices this driver supports (for 82599 VF)
468 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
479 { .vendor_id = 0, /* sentinel */ },
482 static const struct rte_eth_desc_lim rx_desc_lim = {
483 .nb_max = IXGBE_MAX_RING_DESC,
484 .nb_min = IXGBE_MIN_RING_DESC,
485 .nb_align = IXGBE_RXD_ALIGN,
488 static const struct rte_eth_desc_lim tx_desc_lim = {
489 .nb_max = IXGBE_MAX_RING_DESC,
490 .nb_min = IXGBE_MIN_RING_DESC,
491 .nb_align = IXGBE_TXD_ALIGN,
492 .nb_seg_max = IXGBE_TX_MAX_SEG,
493 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
496 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
497 .dev_configure = ixgbe_dev_configure,
498 .dev_start = ixgbe_dev_start,
499 .dev_stop = ixgbe_dev_stop,
500 .dev_set_link_up = ixgbe_dev_set_link_up,
501 .dev_set_link_down = ixgbe_dev_set_link_down,
502 .dev_close = ixgbe_dev_close,
503 .dev_reset = ixgbe_dev_reset,
504 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
505 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
506 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
507 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
508 .link_update = ixgbe_dev_link_update,
509 .stats_get = ixgbe_dev_stats_get,
510 .xstats_get = ixgbe_dev_xstats_get,
511 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
512 .stats_reset = ixgbe_dev_stats_reset,
513 .xstats_reset = ixgbe_dev_xstats_reset,
514 .xstats_get_names = ixgbe_dev_xstats_get_names,
515 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
516 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
517 .fw_version_get = ixgbe_fw_version_get,
518 .dev_infos_get = ixgbe_dev_info_get,
519 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
520 .mtu_set = ixgbe_dev_mtu_set,
521 .vlan_filter_set = ixgbe_vlan_filter_set,
522 .vlan_tpid_set = ixgbe_vlan_tpid_set,
523 .vlan_offload_set = ixgbe_vlan_offload_set,
524 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
525 .rx_queue_start = ixgbe_dev_rx_queue_start,
526 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
527 .tx_queue_start = ixgbe_dev_tx_queue_start,
528 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
529 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
530 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
531 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
532 .rx_queue_release = ixgbe_dev_rx_queue_release,
533 .rx_queue_count = ixgbe_dev_rx_queue_count,
534 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
535 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
536 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
537 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
538 .tx_queue_release = ixgbe_dev_tx_queue_release,
539 .dev_led_on = ixgbe_dev_led_on,
540 .dev_led_off = ixgbe_dev_led_off,
541 .flow_ctrl_get = ixgbe_flow_ctrl_get,
542 .flow_ctrl_set = ixgbe_flow_ctrl_set,
543 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
544 .mac_addr_add = ixgbe_add_rar,
545 .mac_addr_remove = ixgbe_remove_rar,
546 .mac_addr_set = ixgbe_set_default_mac_addr,
547 .uc_hash_table_set = ixgbe_uc_hash_table_set,
548 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
549 .mirror_rule_set = ixgbe_mirror_rule_set,
550 .mirror_rule_reset = ixgbe_mirror_rule_reset,
551 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
552 .reta_update = ixgbe_dev_rss_reta_update,
553 .reta_query = ixgbe_dev_rss_reta_query,
554 .rss_hash_update = ixgbe_dev_rss_hash_update,
555 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
556 .filter_ctrl = ixgbe_dev_filter_ctrl,
557 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
558 .rxq_info_get = ixgbe_rxq_info_get,
559 .txq_info_get = ixgbe_txq_info_get,
560 .timesync_enable = ixgbe_timesync_enable,
561 .timesync_disable = ixgbe_timesync_disable,
562 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
563 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
564 .get_reg = ixgbe_get_regs,
565 .get_eeprom_length = ixgbe_get_eeprom_length,
566 .get_eeprom = ixgbe_get_eeprom,
567 .set_eeprom = ixgbe_set_eeprom,
568 .get_dcb_info = ixgbe_dev_get_dcb_info,
569 .timesync_adjust_time = ixgbe_timesync_adjust_time,
570 .timesync_read_time = ixgbe_timesync_read_time,
571 .timesync_write_time = ixgbe_timesync_write_time,
572 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
573 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
574 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
575 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
576 .tm_ops_get = ixgbe_tm_ops_get,
580 * dev_ops for virtual function, bare necessities for basic vf
581 * operation have been implemented
583 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
584 .dev_configure = ixgbevf_dev_configure,
585 .dev_start = ixgbevf_dev_start,
586 .dev_stop = ixgbevf_dev_stop,
587 .link_update = ixgbevf_dev_link_update,
588 .stats_get = ixgbevf_dev_stats_get,
589 .xstats_get = ixgbevf_dev_xstats_get,
590 .stats_reset = ixgbevf_dev_stats_reset,
591 .xstats_reset = ixgbevf_dev_stats_reset,
592 .xstats_get_names = ixgbevf_dev_xstats_get_names,
593 .dev_close = ixgbevf_dev_close,
594 .dev_reset = ixgbevf_dev_reset,
595 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
596 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
597 .dev_infos_get = ixgbevf_dev_info_get,
598 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
599 .mtu_set = ixgbevf_dev_set_mtu,
600 .vlan_filter_set = ixgbevf_vlan_filter_set,
601 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
602 .vlan_offload_set = ixgbevf_vlan_offload_set,
603 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
604 .rx_queue_release = ixgbe_dev_rx_queue_release,
605 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
606 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
607 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
608 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
609 .tx_queue_release = ixgbe_dev_tx_queue_release,
610 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
611 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
612 .mac_addr_add = ixgbevf_add_mac_addr,
613 .mac_addr_remove = ixgbevf_remove_mac_addr,
614 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
615 .rxq_info_get = ixgbe_rxq_info_get,
616 .txq_info_get = ixgbe_txq_info_get,
617 .mac_addr_set = ixgbevf_set_default_mac_addr,
618 .get_reg = ixgbevf_get_regs,
619 .reta_update = ixgbe_dev_rss_reta_update,
620 .reta_query = ixgbe_dev_rss_reta_query,
621 .rss_hash_update = ixgbe_dev_rss_hash_update,
622 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
625 /* store statistics names and its offset in stats structure */
626 struct rte_ixgbe_xstats_name_off {
627 char name[RTE_ETH_XSTATS_NAME_SIZE];
631 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
632 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
633 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
634 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
635 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
636 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
637 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
638 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
639 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
640 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
641 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
642 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
643 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
644 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
645 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
646 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
648 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
650 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
651 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
652 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
653 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
654 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
655 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
656 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
657 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
658 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
659 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
660 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
661 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
662 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
663 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
664 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
665 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
666 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
668 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
670 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
671 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
672 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
673 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
675 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
677 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
679 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
681 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
683 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
685 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
688 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
689 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
690 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
692 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
693 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
694 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
695 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
696 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
698 {"rx_fcoe_no_direct_data_placement_ext_buff",
699 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
701 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
703 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
705 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
707 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
709 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
712 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
713 sizeof(rte_ixgbe_stats_strings[0]))
715 /* MACsec statistics */
716 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
717 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
719 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
720 out_pkts_encrypted)},
721 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
722 out_pkts_protected)},
723 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
724 out_octets_encrypted)},
725 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
726 out_octets_protected)},
727 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
729 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
731 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
733 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
734 in_pkts_unknownsci)},
735 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
736 in_octets_decrypted)},
737 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
738 in_octets_validated)},
739 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
741 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
743 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
745 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
747 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
749 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
751 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
753 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
754 in_pkts_notusingsa)},
757 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
758 sizeof(rte_ixgbe_macsec_strings[0]))
760 /* Per-queue statistics */
761 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
762 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
763 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
764 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
765 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
768 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
769 sizeof(rte_ixgbe_rxq_strings[0]))
770 #define IXGBE_NB_RXQ_PRIO_VALUES 8
772 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
773 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
774 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
775 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
779 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
780 sizeof(rte_ixgbe_txq_strings[0]))
781 #define IXGBE_NB_TXQ_PRIO_VALUES 8
783 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
784 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
787 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
788 sizeof(rte_ixgbevf_stats_strings[0]))
791 * Atomically reads the link status information from global
792 * structure rte_eth_dev.
795 * - Pointer to the structure rte_eth_dev to read from.
796 * - Pointer to the buffer to be saved with the link status.
799 * - On success, zero.
800 * - On failure, negative value.
803 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
804 struct rte_eth_link *link)
806 struct rte_eth_link *dst = link;
807 struct rte_eth_link *src = &(dev->data->dev_link);
809 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
810 *(uint64_t *)src) == 0)
817 * Atomically writes the link status information into global
818 * structure rte_eth_dev.
821 * - Pointer to the structure rte_eth_dev to read from.
822 * - Pointer to the buffer to be saved with the link status.
825 * - On success, zero.
826 * - On failure, negative value.
829 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
830 struct rte_eth_link *link)
832 struct rte_eth_link *dst = &(dev->data->dev_link);
833 struct rte_eth_link *src = link;
835 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
836 *(uint64_t *)src) == 0)
843 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
846 ixgbe_is_sfp(struct ixgbe_hw *hw)
848 switch (hw->phy.type) {
849 case ixgbe_phy_sfp_avago:
850 case ixgbe_phy_sfp_ftl:
851 case ixgbe_phy_sfp_intel:
852 case ixgbe_phy_sfp_unknown:
853 case ixgbe_phy_sfp_passive_tyco:
854 case ixgbe_phy_sfp_passive_unknown:
861 static inline int32_t
862 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
867 status = ixgbe_reset_hw(hw);
869 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
870 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
871 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
872 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
873 IXGBE_WRITE_FLUSH(hw);
875 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
876 status = IXGBE_SUCCESS;
881 ixgbe_enable_intr(struct rte_eth_dev *dev)
883 struct ixgbe_interrupt *intr =
884 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
885 struct ixgbe_hw *hw =
886 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
888 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
889 IXGBE_WRITE_FLUSH(hw);
893 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
896 ixgbe_disable_intr(struct ixgbe_hw *hw)
898 PMD_INIT_FUNC_TRACE();
900 if (hw->mac.type == ixgbe_mac_82598EB) {
901 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
903 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
904 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
905 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
907 IXGBE_WRITE_FLUSH(hw);
911 * This function resets queue statistics mapping registers.
912 * From Niantic datasheet, Initialization of Statistics section:
913 * "...if software requires the queue counters, the RQSMR and TQSM registers
914 * must be re-programmed following a device reset.
917 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
921 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
922 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
923 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
929 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
934 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
935 #define NB_QMAP_FIELDS_PER_QSM_REG 4
936 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
938 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
939 struct ixgbe_stat_mapping_registers *stat_mappings =
940 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
941 uint32_t qsmr_mask = 0;
942 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
946 if ((hw->mac.type != ixgbe_mac_82599EB) &&
947 (hw->mac.type != ixgbe_mac_X540) &&
948 (hw->mac.type != ixgbe_mac_X550) &&
949 (hw->mac.type != ixgbe_mac_X550EM_x) &&
950 (hw->mac.type != ixgbe_mac_X550EM_a))
953 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
954 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
957 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
958 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
959 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
962 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
964 /* Now clear any previous stat_idx set */
965 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
967 stat_mappings->tqsm[n] &= ~clearing_mask;
969 stat_mappings->rqsmr[n] &= ~clearing_mask;
971 q_map = (uint32_t)stat_idx;
972 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
973 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
975 stat_mappings->tqsm[n] |= qsmr_mask;
977 stat_mappings->rqsmr[n] |= qsmr_mask;
979 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
980 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
982 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
983 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
985 /* Now write the mapping in the appropriate register */
987 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
988 stat_mappings->rqsmr[n], n);
989 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
991 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
992 stat_mappings->tqsm[n], n);
993 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
999 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1001 struct ixgbe_stat_mapping_registers *stat_mappings =
1002 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1003 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1006 /* write whatever was in stat mapping table to the NIC */
1007 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1009 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1012 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1017 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1020 struct ixgbe_dcb_tc_config *tc;
1021 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1023 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1024 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1025 for (i = 0; i < dcb_max_tc; i++) {
1026 tc = &dcb_config->tc_config[i];
1027 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1028 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1029 (uint8_t)(100/dcb_max_tc + (i & 1));
1030 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1031 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1032 (uint8_t)(100/dcb_max_tc + (i & 1));
1033 tc->pfc = ixgbe_dcb_pfc_disabled;
1036 /* Initialize default user to priority mapping, UPx->TC0 */
1037 tc = &dcb_config->tc_config[0];
1038 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1039 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1040 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1041 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1042 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1044 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1045 dcb_config->pfc_mode_enable = false;
1046 dcb_config->vt_mode = true;
1047 dcb_config->round_robin_enable = false;
1048 /* support all DCB capabilities in 82599 */
1049 dcb_config->support.capabilities = 0xFF;
1051 /*we only support 4 Tcs for X540, X550 */
1052 if (hw->mac.type == ixgbe_mac_X540 ||
1053 hw->mac.type == ixgbe_mac_X550 ||
1054 hw->mac.type == ixgbe_mac_X550EM_x ||
1055 hw->mac.type == ixgbe_mac_X550EM_a) {
1056 dcb_config->num_tcs.pg_tcs = 4;
1057 dcb_config->num_tcs.pfc_tcs = 4;
1062 * Ensure that all locks are released before first NVM or PHY access
1065 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1070 * Phy lock should not fail in this early stage. If this is the case,
1071 * it is due to an improper exit of the application.
1072 * So force the release of the faulty lock. Release of common lock
1073 * is done automatically by swfw_sync function.
1075 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1076 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1077 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1079 ixgbe_release_swfw_semaphore(hw, mask);
1082 * These ones are more tricky since they are common to all ports; but
1083 * swfw_sync retries last long enough (1s) to be almost sure that if
1084 * lock can not be taken it is due to an improper lock of the
1087 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1088 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1089 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1091 ixgbe_release_swfw_semaphore(hw, mask);
1095 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1096 * It returns 0 on success.
1099 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1101 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1102 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1103 struct ixgbe_hw *hw =
1104 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1105 struct ixgbe_vfta *shadow_vfta =
1106 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1107 struct ixgbe_hwstrip *hwstrip =
1108 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1109 struct ixgbe_dcb_config *dcb_config =
1110 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1111 struct ixgbe_filter_info *filter_info =
1112 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1113 struct ixgbe_bw_conf *bw_conf =
1114 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1119 PMD_INIT_FUNC_TRACE();
1121 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1122 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1123 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1124 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1127 * For secondary processes, we don't initialise any further as primary
1128 * has already done this work. Only check we don't need a different
1129 * RX and TX function.
1131 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1132 struct ixgbe_tx_queue *txq;
1133 /* TX queue function in primary, set by last queue initialized
1134 * Tx queue may not initialized by primary process
1136 if (eth_dev->data->tx_queues) {
1137 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1138 ixgbe_set_tx_function(eth_dev, txq);
1140 /* Use default TX function if we get here */
1141 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1142 "Using default TX function.");
1145 ixgbe_set_rx_function(eth_dev);
1150 rte_eth_copy_pci_info(eth_dev, pci_dev);
1152 /* Vendor and Device ID need to be set before init of shared code */
1153 hw->device_id = pci_dev->id.device_id;
1154 hw->vendor_id = pci_dev->id.vendor_id;
1155 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1156 hw->allow_unsupported_sfp = 1;
1158 /* Initialize the shared code (base driver) */
1159 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1160 diag = ixgbe_bypass_init_shared_code(hw);
1162 diag = ixgbe_init_shared_code(hw);
1163 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1165 if (diag != IXGBE_SUCCESS) {
1166 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1170 /* pick up the PCI bus settings for reporting later */
1171 ixgbe_get_bus_info(hw);
1173 /* Unlock any pending hardware semaphore */
1174 ixgbe_swfw_lock_reset(hw);
1176 #ifdef RTE_LIBRTE_SECURITY
1177 /* Initialize security_ctx only for primary process*/
1178 if (ixgbe_ipsec_ctx_create(eth_dev))
1182 /* Initialize DCB configuration*/
1183 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1184 ixgbe_dcb_init(hw, dcb_config);
1185 /* Get Hardware Flow Control setting */
1186 hw->fc.requested_mode = ixgbe_fc_full;
1187 hw->fc.current_mode = ixgbe_fc_full;
1188 hw->fc.pause_time = IXGBE_FC_PAUSE;
1189 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1190 hw->fc.low_water[i] = IXGBE_FC_LO;
1191 hw->fc.high_water[i] = IXGBE_FC_HI;
1193 hw->fc.send_xon = 1;
1195 /* Make sure we have a good EEPROM before we read from it */
1196 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1197 if (diag != IXGBE_SUCCESS) {
1198 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1202 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1203 diag = ixgbe_bypass_init_hw(hw);
1205 diag = ixgbe_init_hw(hw);
1206 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1209 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1210 * is called too soon after the kernel driver unbinding/binding occurs.
1211 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1212 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1213 * also called. See ixgbe_identify_phy_82599(). The reason for the
1214 * failure is not known, and only occuts when virtualisation features
1215 * are disabled in the bios. A delay of 100ms was found to be enough by
1216 * trial-and-error, and is doubled to be safe.
1218 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1220 diag = ixgbe_init_hw(hw);
1223 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1224 diag = IXGBE_SUCCESS;
1226 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1227 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1228 "LOM. Please be aware there may be issues associated "
1229 "with your hardware.");
1230 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1231 "please contact your Intel or hardware representative "
1232 "who provided you with this hardware.");
1233 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1234 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1236 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1240 /* Reset the hw statistics */
1241 ixgbe_dev_stats_reset(eth_dev);
1243 /* disable interrupt */
1244 ixgbe_disable_intr(hw);
1246 /* reset mappings for queue statistics hw counters*/
1247 ixgbe_reset_qstat_mappings(hw);
1249 /* Allocate memory for storing MAC addresses */
1250 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1251 hw->mac.num_rar_entries, 0);
1252 if (eth_dev->data->mac_addrs == NULL) {
1254 "Failed to allocate %u bytes needed to store "
1256 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1259 /* Copy the permanent MAC address */
1260 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1261 ð_dev->data->mac_addrs[0]);
1263 /* Allocate memory for storing hash filter MAC addresses */
1264 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1265 IXGBE_VMDQ_NUM_UC_MAC, 0);
1266 if (eth_dev->data->hash_mac_addrs == NULL) {
1268 "Failed to allocate %d bytes needed to store MAC addresses",
1269 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1273 /* initialize the vfta */
1274 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1276 /* initialize the hw strip bitmap*/
1277 memset(hwstrip, 0, sizeof(*hwstrip));
1279 /* initialize PF if max_vfs not zero */
1280 ixgbe_pf_host_init(eth_dev);
1282 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1283 /* let hardware know driver is loaded */
1284 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1285 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1286 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1287 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1288 IXGBE_WRITE_FLUSH(hw);
1290 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1291 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1292 (int) hw->mac.type, (int) hw->phy.type,
1293 (int) hw->phy.sfp_type);
1295 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1296 (int) hw->mac.type, (int) hw->phy.type);
1298 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1299 eth_dev->data->port_id, pci_dev->id.vendor_id,
1300 pci_dev->id.device_id);
1302 rte_intr_callback_register(intr_handle,
1303 ixgbe_dev_interrupt_handler, eth_dev);
1305 /* enable uio/vfio intr/eventfd mapping */
1306 rte_intr_enable(intr_handle);
1308 /* enable support intr */
1309 ixgbe_enable_intr(eth_dev);
1311 /* initialize filter info */
1312 memset(filter_info, 0,
1313 sizeof(struct ixgbe_filter_info));
1315 /* initialize 5tuple filter list */
1316 TAILQ_INIT(&filter_info->fivetuple_list);
1318 /* initialize flow director filter list & hash */
1319 ixgbe_fdir_filter_init(eth_dev);
1321 /* initialize l2 tunnel filter list & hash */
1322 ixgbe_l2_tn_filter_init(eth_dev);
1324 /* initialize flow filter lists */
1325 ixgbe_filterlist_init();
1327 /* initialize bandwidth configuration info */
1328 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1330 /* initialize Traffic Manager configuration */
1331 ixgbe_tm_conf_init(eth_dev);
1337 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1339 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1340 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1341 struct ixgbe_hw *hw;
1343 PMD_INIT_FUNC_TRACE();
1345 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1348 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1350 if (hw->adapter_stopped == 0)
1351 ixgbe_dev_close(eth_dev);
1353 eth_dev->dev_ops = NULL;
1354 eth_dev->rx_pkt_burst = NULL;
1355 eth_dev->tx_pkt_burst = NULL;
1357 /* Unlock any pending hardware semaphore */
1358 ixgbe_swfw_lock_reset(hw);
1360 /* disable uio intr before callback unregister */
1361 rte_intr_disable(intr_handle);
1362 rte_intr_callback_unregister(intr_handle,
1363 ixgbe_dev_interrupt_handler, eth_dev);
1365 /* uninitialize PF if max_vfs not zero */
1366 ixgbe_pf_host_uninit(eth_dev);
1368 rte_free(eth_dev->data->mac_addrs);
1369 eth_dev->data->mac_addrs = NULL;
1371 rte_free(eth_dev->data->hash_mac_addrs);
1372 eth_dev->data->hash_mac_addrs = NULL;
1374 /* remove all the fdir filters & hash */
1375 ixgbe_fdir_filter_uninit(eth_dev);
1377 /* remove all the L2 tunnel filters & hash */
1378 ixgbe_l2_tn_filter_uninit(eth_dev);
1380 /* Remove all ntuple filters of the device */
1381 ixgbe_ntuple_filter_uninit(eth_dev);
1383 /* clear all the filters list */
1384 ixgbe_filterlist_flush();
1386 /* Remove all Traffic Manager configuration */
1387 ixgbe_tm_conf_uninit(eth_dev);
1389 #ifdef RTE_LIBRTE_SECURITY
1390 rte_free(eth_dev->security_ctx);
1396 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1398 struct ixgbe_filter_info *filter_info =
1399 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1400 struct ixgbe_5tuple_filter *p_5tuple;
1402 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1403 TAILQ_REMOVE(&filter_info->fivetuple_list,
1408 memset(filter_info->fivetuple_mask, 0,
1409 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1414 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1416 struct ixgbe_hw_fdir_info *fdir_info =
1417 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1418 struct ixgbe_fdir_filter *fdir_filter;
1420 if (fdir_info->hash_map)
1421 rte_free(fdir_info->hash_map);
1422 if (fdir_info->hash_handle)
1423 rte_hash_free(fdir_info->hash_handle);
1425 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1426 TAILQ_REMOVE(&fdir_info->fdir_list,
1429 rte_free(fdir_filter);
1435 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1437 struct ixgbe_l2_tn_info *l2_tn_info =
1438 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1439 struct ixgbe_l2_tn_filter *l2_tn_filter;
1441 if (l2_tn_info->hash_map)
1442 rte_free(l2_tn_info->hash_map);
1443 if (l2_tn_info->hash_handle)
1444 rte_hash_free(l2_tn_info->hash_handle);
1446 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1447 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1450 rte_free(l2_tn_filter);
1456 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1458 struct ixgbe_hw_fdir_info *fdir_info =
1459 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1460 char fdir_hash_name[RTE_HASH_NAMESIZE];
1461 struct rte_hash_parameters fdir_hash_params = {
1462 .name = fdir_hash_name,
1463 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1464 .key_len = sizeof(union ixgbe_atr_input),
1465 .hash_func = rte_hash_crc,
1466 .hash_func_init_val = 0,
1467 .socket_id = rte_socket_id(),
1470 TAILQ_INIT(&fdir_info->fdir_list);
1471 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1472 "fdir_%s", eth_dev->device->name);
1473 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1474 if (!fdir_info->hash_handle) {
1475 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1478 fdir_info->hash_map = rte_zmalloc("ixgbe",
1479 sizeof(struct ixgbe_fdir_filter *) *
1480 IXGBE_MAX_FDIR_FILTER_NUM,
1482 if (!fdir_info->hash_map) {
1484 "Failed to allocate memory for fdir hash map!");
1487 fdir_info->mask_added = FALSE;
1492 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1494 struct ixgbe_l2_tn_info *l2_tn_info =
1495 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1496 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1497 struct rte_hash_parameters l2_tn_hash_params = {
1498 .name = l2_tn_hash_name,
1499 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1500 .key_len = sizeof(struct ixgbe_l2_tn_key),
1501 .hash_func = rte_hash_crc,
1502 .hash_func_init_val = 0,
1503 .socket_id = rte_socket_id(),
1506 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1507 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1508 "l2_tn_%s", eth_dev->device->name);
1509 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1510 if (!l2_tn_info->hash_handle) {
1511 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1514 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1515 sizeof(struct ixgbe_l2_tn_filter *) *
1516 IXGBE_MAX_L2_TN_FILTER_NUM,
1518 if (!l2_tn_info->hash_map) {
1520 "Failed to allocate memory for L2 TN hash map!");
1523 l2_tn_info->e_tag_en = FALSE;
1524 l2_tn_info->e_tag_fwd_en = FALSE;
1525 l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1530 * Negotiate mailbox API version with the PF.
1531 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1532 * Then we try to negotiate starting with the most recent one.
1533 * If all negotiation attempts fail, then we will proceed with
1534 * the default one (ixgbe_mbox_api_10).
1537 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1541 /* start with highest supported, proceed down */
1542 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1549 i != RTE_DIM(sup_ver) &&
1550 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1556 generate_random_mac_addr(struct ether_addr *mac_addr)
1560 /* Set Organizationally Unique Identifier (OUI) prefix. */
1561 mac_addr->addr_bytes[0] = 0x00;
1562 mac_addr->addr_bytes[1] = 0x09;
1563 mac_addr->addr_bytes[2] = 0xC0;
1564 /* Force indication of locally assigned MAC address. */
1565 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1566 /* Generate the last 3 bytes of the MAC address with a random number. */
1567 random = rte_rand();
1568 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1572 * Virtual Function device init
1575 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1579 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1580 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1581 struct ixgbe_hw *hw =
1582 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1583 struct ixgbe_vfta *shadow_vfta =
1584 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1585 struct ixgbe_hwstrip *hwstrip =
1586 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1587 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1589 PMD_INIT_FUNC_TRACE();
1591 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1592 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1593 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1595 /* for secondary processes, we don't initialise any further as primary
1596 * has already done this work. Only check we don't need a different
1599 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1600 struct ixgbe_tx_queue *txq;
1601 /* TX queue function in primary, set by last queue initialized
1602 * Tx queue may not initialized by primary process
1604 if (eth_dev->data->tx_queues) {
1605 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1606 ixgbe_set_tx_function(eth_dev, txq);
1608 /* Use default TX function if we get here */
1609 PMD_INIT_LOG(NOTICE,
1610 "No TX queues configured yet. Using default TX function.");
1613 ixgbe_set_rx_function(eth_dev);
1618 rte_eth_copy_pci_info(eth_dev, pci_dev);
1620 hw->device_id = pci_dev->id.device_id;
1621 hw->vendor_id = pci_dev->id.vendor_id;
1622 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1624 /* initialize the vfta */
1625 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1627 /* initialize the hw strip bitmap*/
1628 memset(hwstrip, 0, sizeof(*hwstrip));
1630 /* Initialize the shared code (base driver) */
1631 diag = ixgbe_init_shared_code(hw);
1632 if (diag != IXGBE_SUCCESS) {
1633 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1637 /* init_mailbox_params */
1638 hw->mbx.ops.init_params(hw);
1640 /* Reset the hw statistics */
1641 ixgbevf_dev_stats_reset(eth_dev);
1643 /* Disable the interrupts for VF */
1644 ixgbevf_intr_disable(hw);
1646 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1647 diag = hw->mac.ops.reset_hw(hw);
1650 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1651 * the underlying PF driver has not assigned a MAC address to the VF.
1652 * In this case, assign a random MAC address.
1654 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1655 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1659 /* negotiate mailbox API version to use with the PF. */
1660 ixgbevf_negotiate_api(hw);
1662 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1663 ixgbevf_get_queues(hw, &tcs, &tc);
1665 /* Allocate memory for storing MAC addresses */
1666 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1667 hw->mac.num_rar_entries, 0);
1668 if (eth_dev->data->mac_addrs == NULL) {
1670 "Failed to allocate %u bytes needed to store "
1672 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1676 /* Generate a random MAC address, if none was assigned by PF. */
1677 if (is_zero_ether_addr(perm_addr)) {
1678 generate_random_mac_addr(perm_addr);
1679 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1681 rte_free(eth_dev->data->mac_addrs);
1682 eth_dev->data->mac_addrs = NULL;
1685 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1686 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1687 "%02x:%02x:%02x:%02x:%02x:%02x",
1688 perm_addr->addr_bytes[0],
1689 perm_addr->addr_bytes[1],
1690 perm_addr->addr_bytes[2],
1691 perm_addr->addr_bytes[3],
1692 perm_addr->addr_bytes[4],
1693 perm_addr->addr_bytes[5]);
1696 /* Copy the permanent MAC address */
1697 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1699 /* reset the hardware with the new settings */
1700 diag = hw->mac.ops.start_hw(hw);
1706 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1710 rte_intr_callback_register(intr_handle,
1711 ixgbevf_dev_interrupt_handler, eth_dev);
1712 rte_intr_enable(intr_handle);
1713 ixgbevf_intr_enable(hw);
1715 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1716 eth_dev->data->port_id, pci_dev->id.vendor_id,
1717 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1722 /* Virtual Function device uninit */
1725 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1727 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1728 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1729 struct ixgbe_hw *hw;
1731 PMD_INIT_FUNC_TRACE();
1733 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1736 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1738 if (hw->adapter_stopped == 0)
1739 ixgbevf_dev_close(eth_dev);
1741 eth_dev->dev_ops = NULL;
1742 eth_dev->rx_pkt_burst = NULL;
1743 eth_dev->tx_pkt_burst = NULL;
1745 /* Disable the interrupts for VF */
1746 ixgbevf_intr_disable(hw);
1748 rte_free(eth_dev->data->mac_addrs);
1749 eth_dev->data->mac_addrs = NULL;
1751 rte_intr_disable(intr_handle);
1752 rte_intr_callback_unregister(intr_handle,
1753 ixgbevf_dev_interrupt_handler, eth_dev);
1758 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1759 struct rte_pci_device *pci_dev)
1761 return rte_eth_dev_pci_generic_probe(pci_dev,
1762 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1765 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1767 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1770 static struct rte_pci_driver rte_ixgbe_pmd = {
1771 .id_table = pci_id_ixgbe_map,
1772 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1773 RTE_PCI_DRV_IOVA_AS_VA,
1774 .probe = eth_ixgbe_pci_probe,
1775 .remove = eth_ixgbe_pci_remove,
1778 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1779 struct rte_pci_device *pci_dev)
1781 return rte_eth_dev_pci_generic_probe(pci_dev,
1782 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1785 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1787 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1791 * virtual function driver struct
1793 static struct rte_pci_driver rte_ixgbevf_pmd = {
1794 .id_table = pci_id_ixgbevf_map,
1795 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1796 .probe = eth_ixgbevf_pci_probe,
1797 .remove = eth_ixgbevf_pci_remove,
1801 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1803 struct ixgbe_hw *hw =
1804 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1805 struct ixgbe_vfta *shadow_vfta =
1806 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1811 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1812 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1813 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1818 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1820 /* update local VFTA copy */
1821 shadow_vfta->vfta[vid_idx] = vfta;
1827 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1830 ixgbe_vlan_hw_strip_enable(dev, queue);
1832 ixgbe_vlan_hw_strip_disable(dev, queue);
1836 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1837 enum rte_vlan_type vlan_type,
1840 struct ixgbe_hw *hw =
1841 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1846 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1847 qinq &= IXGBE_DMATXCTL_GDV;
1849 switch (vlan_type) {
1850 case ETH_VLAN_TYPE_INNER:
1852 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1853 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1854 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1855 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1856 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1857 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1858 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1861 PMD_DRV_LOG(ERR, "Inner type is not supported"
1865 case ETH_VLAN_TYPE_OUTER:
1867 /* Only the high 16-bits is valid */
1868 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1869 IXGBE_EXVET_VET_EXT_SHIFT);
1871 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1872 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1873 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1874 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1875 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1876 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1877 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1883 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1891 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1893 struct ixgbe_hw *hw =
1894 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1897 PMD_INIT_FUNC_TRACE();
1899 /* Filter Table Disable */
1900 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1901 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1903 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1907 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1909 struct ixgbe_hw *hw =
1910 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1911 struct ixgbe_vfta *shadow_vfta =
1912 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1916 PMD_INIT_FUNC_TRACE();
1918 /* Filter Table Enable */
1919 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1920 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1921 vlnctrl |= IXGBE_VLNCTRL_VFE;
1923 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1925 /* write whatever is in local vfta copy */
1926 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1927 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1931 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1933 struct ixgbe_hwstrip *hwstrip =
1934 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1935 struct ixgbe_rx_queue *rxq;
1937 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1941 IXGBE_SET_HWSTRIP(hwstrip, queue);
1943 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1945 if (queue >= dev->data->nb_rx_queues)
1948 rxq = dev->data->rx_queues[queue];
1951 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1953 rxq->vlan_flags = PKT_RX_VLAN;
1957 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1959 struct ixgbe_hw *hw =
1960 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1963 PMD_INIT_FUNC_TRACE();
1965 if (hw->mac.type == ixgbe_mac_82598EB) {
1966 /* No queue level support */
1967 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1971 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1972 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1973 ctrl &= ~IXGBE_RXDCTL_VME;
1974 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1976 /* record those setting for HW strip per queue */
1977 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1981 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1983 struct ixgbe_hw *hw =
1984 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1987 PMD_INIT_FUNC_TRACE();
1989 if (hw->mac.type == ixgbe_mac_82598EB) {
1990 /* No queue level supported */
1991 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1995 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1996 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1997 ctrl |= IXGBE_RXDCTL_VME;
1998 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2000 /* record those setting for HW strip per queue */
2001 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2005 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2007 struct ixgbe_hw *hw =
2008 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2011 struct ixgbe_rx_queue *rxq;
2013 PMD_INIT_FUNC_TRACE();
2015 if (hw->mac.type == ixgbe_mac_82598EB) {
2016 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2017 ctrl &= ~IXGBE_VLNCTRL_VME;
2018 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2020 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2021 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2022 rxq = dev->data->rx_queues[i];
2023 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2024 ctrl &= ~IXGBE_RXDCTL_VME;
2025 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2027 /* record those setting for HW strip per queue */
2028 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2034 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2036 struct ixgbe_hw *hw =
2037 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2040 struct ixgbe_rx_queue *rxq;
2042 PMD_INIT_FUNC_TRACE();
2044 if (hw->mac.type == ixgbe_mac_82598EB) {
2045 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2046 ctrl |= IXGBE_VLNCTRL_VME;
2047 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2049 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2050 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2051 rxq = dev->data->rx_queues[i];
2052 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2053 ctrl |= IXGBE_RXDCTL_VME;
2054 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2056 /* record those setting for HW strip per queue */
2057 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2063 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2065 struct ixgbe_hw *hw =
2066 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2069 PMD_INIT_FUNC_TRACE();
2071 /* DMATXCTRL: Geric Double VLAN Disable */
2072 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2073 ctrl &= ~IXGBE_DMATXCTL_GDV;
2074 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2076 /* CTRL_EXT: Global Double VLAN Disable */
2077 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2078 ctrl &= ~IXGBE_EXTENDED_VLAN;
2079 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2084 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2086 struct ixgbe_hw *hw =
2087 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2090 PMD_INIT_FUNC_TRACE();
2092 /* DMATXCTRL: Geric Double VLAN Enable */
2093 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2094 ctrl |= IXGBE_DMATXCTL_GDV;
2095 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2097 /* CTRL_EXT: Global Double VLAN Enable */
2098 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2099 ctrl |= IXGBE_EXTENDED_VLAN;
2100 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2102 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2103 if (hw->mac.type == ixgbe_mac_X550 ||
2104 hw->mac.type == ixgbe_mac_X550EM_x ||
2105 hw->mac.type == ixgbe_mac_X550EM_a) {
2106 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2107 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2108 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2112 * VET EXT field in the EXVET register = 0x8100 by default
2113 * So no need to change. Same to VT field of DMATXCTL register
2118 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2120 if (mask & ETH_VLAN_STRIP_MASK) {
2121 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2122 ixgbe_vlan_hw_strip_enable_all(dev);
2124 ixgbe_vlan_hw_strip_disable_all(dev);
2127 if (mask & ETH_VLAN_FILTER_MASK) {
2128 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2129 ixgbe_vlan_hw_filter_enable(dev);
2131 ixgbe_vlan_hw_filter_disable(dev);
2134 if (mask & ETH_VLAN_EXTEND_MASK) {
2135 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2136 ixgbe_vlan_hw_extend_enable(dev);
2138 ixgbe_vlan_hw_extend_disable(dev);
2145 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2147 struct ixgbe_hw *hw =
2148 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2149 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2150 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2152 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2153 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2157 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2159 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2164 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2167 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2173 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2174 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2175 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2176 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2181 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2183 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2184 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2185 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2186 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2188 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2189 /* check multi-queue mode */
2190 switch (dev_conf->rxmode.mq_mode) {
2191 case ETH_MQ_RX_VMDQ_DCB:
2192 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2194 case ETH_MQ_RX_VMDQ_DCB_RSS:
2195 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2196 PMD_INIT_LOG(ERR, "SRIOV active,"
2197 " unsupported mq_mode rx %d.",
2198 dev_conf->rxmode.mq_mode);
2201 case ETH_MQ_RX_VMDQ_RSS:
2202 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2203 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2204 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2205 PMD_INIT_LOG(ERR, "SRIOV is active,"
2206 " invalid queue number"
2207 " for VMDQ RSS, allowed"
2208 " value are 1, 2 or 4.");
2212 case ETH_MQ_RX_VMDQ_ONLY:
2213 case ETH_MQ_RX_NONE:
2214 /* if nothing mq mode configure, use default scheme */
2215 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2217 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2218 /* SRIOV only works in VMDq enable mode */
2219 PMD_INIT_LOG(ERR, "SRIOV is active,"
2220 " wrong mq_mode rx %d.",
2221 dev_conf->rxmode.mq_mode);
2225 switch (dev_conf->txmode.mq_mode) {
2226 case ETH_MQ_TX_VMDQ_DCB:
2227 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2228 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2230 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2231 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2235 /* check valid queue number */
2236 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2237 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2238 PMD_INIT_LOG(ERR, "SRIOV is active,"
2239 " nb_rx_q=%d nb_tx_q=%d queue number"
2240 " must be less than or equal to %d.",
2242 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2246 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2247 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2251 /* check configuration for vmdb+dcb mode */
2252 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2253 const struct rte_eth_vmdq_dcb_conf *conf;
2255 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2256 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2257 IXGBE_VMDQ_DCB_NB_QUEUES);
2260 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2261 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2262 conf->nb_queue_pools == ETH_32_POOLS)) {
2263 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2264 " nb_queue_pools must be %d or %d.",
2265 ETH_16_POOLS, ETH_32_POOLS);
2269 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2270 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2272 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2273 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2274 IXGBE_VMDQ_DCB_NB_QUEUES);
2277 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2278 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2279 conf->nb_queue_pools == ETH_32_POOLS)) {
2280 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2281 " nb_queue_pools != %d and"
2282 " nb_queue_pools != %d.",
2283 ETH_16_POOLS, ETH_32_POOLS);
2288 /* For DCB mode check our configuration before we go further */
2289 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2290 const struct rte_eth_dcb_rx_conf *conf;
2292 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2293 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2294 IXGBE_DCB_NB_QUEUES);
2297 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2298 if (!(conf->nb_tcs == ETH_4_TCS ||
2299 conf->nb_tcs == ETH_8_TCS)) {
2300 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2301 " and nb_tcs != %d.",
2302 ETH_4_TCS, ETH_8_TCS);
2307 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2308 const struct rte_eth_dcb_tx_conf *conf;
2310 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2311 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2312 IXGBE_DCB_NB_QUEUES);
2315 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2316 if (!(conf->nb_tcs == ETH_4_TCS ||
2317 conf->nb_tcs == ETH_8_TCS)) {
2318 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2319 " and nb_tcs != %d.",
2320 ETH_4_TCS, ETH_8_TCS);
2326 * When DCB/VT is off, maximum number of queues changes,
2327 * except for 82598EB, which remains constant.
2329 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2330 hw->mac.type != ixgbe_mac_82598EB) {
2331 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2333 "Neither VT nor DCB are enabled, "
2335 IXGBE_NONE_MODE_TX_NB_QUEUES);
2344 ixgbe_dev_configure(struct rte_eth_dev *dev)
2346 struct ixgbe_interrupt *intr =
2347 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2348 struct ixgbe_adapter *adapter =
2349 (struct ixgbe_adapter *)dev->data->dev_private;
2352 PMD_INIT_FUNC_TRACE();
2353 /* multipe queue mode checking */
2354 ret = ixgbe_check_mq_mode(dev);
2356 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2361 /* set flag to update link status after init */
2362 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2365 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2366 * allocation or vector Rx preconditions we will reset it.
2368 adapter->rx_bulk_alloc_allowed = true;
2369 adapter->rx_vec_allowed = true;
2375 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2377 struct ixgbe_hw *hw =
2378 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2379 struct ixgbe_interrupt *intr =
2380 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2383 /* only set up it on X550EM_X */
2384 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2385 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2386 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2387 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2388 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2389 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2394 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2395 uint16_t tx_rate, uint64_t q_msk)
2397 struct ixgbe_hw *hw;
2398 struct ixgbe_vf_info *vfinfo;
2399 struct rte_eth_link link;
2400 uint8_t nb_q_per_pool;
2401 uint32_t queue_stride;
2402 uint32_t queue_idx, idx = 0, vf_idx;
2404 uint16_t total_rate = 0;
2405 struct rte_pci_device *pci_dev;
2407 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2408 rte_eth_link_get_nowait(dev->data->port_id, &link);
2410 if (vf >= pci_dev->max_vfs)
2413 if (tx_rate > link.link_speed)
2419 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2420 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2421 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2422 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2423 queue_idx = vf * queue_stride;
2424 queue_end = queue_idx + nb_q_per_pool - 1;
2425 if (queue_end >= hw->mac.max_tx_queues)
2429 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2432 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2434 total_rate += vfinfo[vf_idx].tx_rate[idx];
2440 /* Store tx_rate for this vf. */
2441 for (idx = 0; idx < nb_q_per_pool; idx++) {
2442 if (((uint64_t)0x1 << idx) & q_msk) {
2443 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2444 vfinfo[vf].tx_rate[idx] = tx_rate;
2445 total_rate += tx_rate;
2449 if (total_rate > dev->data->dev_link.link_speed) {
2450 /* Reset stored TX rate of the VF if it causes exceed
2453 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2457 /* Set RTTBCNRC of each queue/pool for vf X */
2458 for (; queue_idx <= queue_end; queue_idx++) {
2460 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2468 * Configure device link speed and setup link.
2469 * It returns 0 on success.
2472 ixgbe_dev_start(struct rte_eth_dev *dev)
2474 struct ixgbe_hw *hw =
2475 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2476 struct ixgbe_vf_info *vfinfo =
2477 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2478 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2479 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2480 uint32_t intr_vector = 0;
2481 int err, link_up = 0, negotiate = 0;
2486 uint32_t *link_speeds;
2487 struct ixgbe_tm_conf *tm_conf =
2488 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2490 PMD_INIT_FUNC_TRACE();
2492 /* IXGBE devices don't support:
2493 * - half duplex (checked afterwards for valid speeds)
2494 * - fixed speed: TODO implement
2496 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2498 "Invalid link_speeds for port %u, fix speed not supported",
2499 dev->data->port_id);
2503 /* disable uio/vfio intr/eventfd mapping */
2504 rte_intr_disable(intr_handle);
2507 hw->adapter_stopped = 0;
2508 ixgbe_stop_adapter(hw);
2510 /* reinitialize adapter
2511 * this calls reset and start
2513 status = ixgbe_pf_reset_hw(hw);
2516 hw->mac.ops.start_hw(hw);
2517 hw->mac.get_link_status = true;
2519 /* configure PF module if SRIOV enabled */
2520 ixgbe_pf_host_configure(dev);
2522 ixgbe_dev_phy_intr_setup(dev);
2524 /* check and configure queue intr-vector mapping */
2525 if ((rte_intr_cap_multiple(intr_handle) ||
2526 !RTE_ETH_DEV_SRIOV(dev).active) &&
2527 dev->data->dev_conf.intr_conf.rxq != 0) {
2528 intr_vector = dev->data->nb_rx_queues;
2529 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2530 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2531 IXGBE_MAX_INTR_QUEUE_NUM);
2534 if (rte_intr_efd_enable(intr_handle, intr_vector))
2538 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2539 intr_handle->intr_vec =
2540 rte_zmalloc("intr_vec",
2541 dev->data->nb_rx_queues * sizeof(int), 0);
2542 if (intr_handle->intr_vec == NULL) {
2543 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2544 " intr_vec", dev->data->nb_rx_queues);
2549 /* confiugre msix for sleep until rx interrupt */
2550 ixgbe_configure_msix(dev);
2552 /* initialize transmission unit */
2553 ixgbe_dev_tx_init(dev);
2555 /* This can fail when allocating mbufs for descriptor rings */
2556 err = ixgbe_dev_rx_init(dev);
2558 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2562 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2563 ETH_VLAN_EXTEND_MASK;
2564 err = ixgbe_vlan_offload_set(dev, mask);
2566 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2570 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2571 /* Enable vlan filtering for VMDq */
2572 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2575 /* Configure DCB hw */
2576 ixgbe_configure_dcb(dev);
2578 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2579 err = ixgbe_fdir_configure(dev);
2584 /* Restore vf rate limit */
2585 if (vfinfo != NULL) {
2586 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2587 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2588 if (vfinfo[vf].tx_rate[idx] != 0)
2589 ixgbe_set_vf_rate_limit(
2591 vfinfo[vf].tx_rate[idx],
2595 ixgbe_restore_statistics_mapping(dev);
2597 err = ixgbe_dev_rxtx_start(dev);
2599 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2603 /* Skip link setup if loopback mode is enabled for 82599. */
2604 if (hw->mac.type == ixgbe_mac_82599EB &&
2605 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2606 goto skip_link_setup;
2608 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2609 err = hw->mac.ops.setup_sfp(hw);
2614 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2615 /* Turn on the copper */
2616 ixgbe_set_phy_power(hw, true);
2618 /* Turn on the laser */
2619 ixgbe_enable_tx_laser(hw);
2622 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2625 dev->data->dev_link.link_status = link_up;
2627 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2631 link_speeds = &dev->data->dev_conf.link_speeds;
2632 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2633 ETH_LINK_SPEED_10G)) {
2634 PMD_INIT_LOG(ERR, "Invalid link setting");
2639 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2640 switch (hw->mac.type) {
2641 case ixgbe_mac_82598EB:
2642 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2644 case ixgbe_mac_82599EB:
2645 case ixgbe_mac_X540:
2646 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2648 case ixgbe_mac_X550:
2649 case ixgbe_mac_X550EM_x:
2650 case ixgbe_mac_X550EM_a:
2651 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2654 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2657 if (*link_speeds & ETH_LINK_SPEED_10G)
2658 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2659 if (*link_speeds & ETH_LINK_SPEED_1G)
2660 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2661 if (*link_speeds & ETH_LINK_SPEED_100M)
2662 speed |= IXGBE_LINK_SPEED_100_FULL;
2665 err = ixgbe_setup_link(hw, speed, link_up);
2671 if (rte_intr_allow_others(intr_handle)) {
2672 /* check if lsc interrupt is enabled */
2673 if (dev->data->dev_conf.intr_conf.lsc != 0)
2674 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2676 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2677 ixgbe_dev_macsec_interrupt_setup(dev);
2679 rte_intr_callback_unregister(intr_handle,
2680 ixgbe_dev_interrupt_handler, dev);
2681 if (dev->data->dev_conf.intr_conf.lsc != 0)
2682 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2683 " no intr multiplex");
2686 /* check if rxq interrupt is enabled */
2687 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2688 rte_intr_dp_is_en(intr_handle))
2689 ixgbe_dev_rxq_interrupt_setup(dev);
2691 /* enable uio/vfio intr/eventfd mapping */
2692 rte_intr_enable(intr_handle);
2694 /* resume enabled intr since hw reset */
2695 ixgbe_enable_intr(dev);
2696 ixgbe_l2_tunnel_conf(dev);
2697 ixgbe_filter_restore(dev);
2699 if (tm_conf->root && !tm_conf->committed)
2700 PMD_DRV_LOG(WARNING,
2701 "please call hierarchy_commit() "
2702 "before starting the port");
2707 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2708 ixgbe_dev_clear_queues(dev);
2713 * Stop device: disable rx and tx functions to allow for reconfiguring.
2716 ixgbe_dev_stop(struct rte_eth_dev *dev)
2718 struct rte_eth_link link;
2719 struct ixgbe_hw *hw =
2720 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2721 struct ixgbe_vf_info *vfinfo =
2722 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2723 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2724 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2726 struct ixgbe_tm_conf *tm_conf =
2727 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2729 PMD_INIT_FUNC_TRACE();
2731 /* disable interrupts */
2732 ixgbe_disable_intr(hw);
2735 ixgbe_pf_reset_hw(hw);
2736 hw->adapter_stopped = 0;
2739 ixgbe_stop_adapter(hw);
2741 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2742 vfinfo[vf].clear_to_send = false;
2744 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2745 /* Turn off the copper */
2746 ixgbe_set_phy_power(hw, false);
2748 /* Turn off the laser */
2749 ixgbe_disable_tx_laser(hw);
2752 ixgbe_dev_clear_queues(dev);
2754 /* Clear stored conf */
2755 dev->data->scattered_rx = 0;
2758 /* Clear recorded link status */
2759 memset(&link, 0, sizeof(link));
2760 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2762 if (!rte_intr_allow_others(intr_handle))
2763 /* resume to the default handler */
2764 rte_intr_callback_register(intr_handle,
2765 ixgbe_dev_interrupt_handler,
2768 /* Clean datapath event and queue/vec mapping */
2769 rte_intr_efd_disable(intr_handle);
2770 if (intr_handle->intr_vec != NULL) {
2771 rte_free(intr_handle->intr_vec);
2772 intr_handle->intr_vec = NULL;
2775 /* reset hierarchy commit */
2776 tm_conf->committed = false;
2780 * Set device link up: enable tx.
2783 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2785 struct ixgbe_hw *hw =
2786 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2787 if (hw->mac.type == ixgbe_mac_82599EB) {
2788 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2789 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2790 /* Not suported in bypass mode */
2791 PMD_INIT_LOG(ERR, "Set link up is not supported "
2792 "by device id 0x%x", hw->device_id);
2798 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2799 /* Turn on the copper */
2800 ixgbe_set_phy_power(hw, true);
2802 /* Turn on the laser */
2803 ixgbe_enable_tx_laser(hw);
2810 * Set device link down: disable tx.
2813 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2815 struct ixgbe_hw *hw =
2816 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2817 if (hw->mac.type == ixgbe_mac_82599EB) {
2818 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2819 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2820 /* Not suported in bypass mode */
2821 PMD_INIT_LOG(ERR, "Set link down is not supported "
2822 "by device id 0x%x", hw->device_id);
2828 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2829 /* Turn off the copper */
2830 ixgbe_set_phy_power(hw, false);
2832 /* Turn off the laser */
2833 ixgbe_disable_tx_laser(hw);
2840 * Reset and stop device.
2843 ixgbe_dev_close(struct rte_eth_dev *dev)
2845 struct ixgbe_hw *hw =
2846 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2848 PMD_INIT_FUNC_TRACE();
2850 ixgbe_pf_reset_hw(hw);
2852 ixgbe_dev_stop(dev);
2853 hw->adapter_stopped = 1;
2855 ixgbe_dev_free_queues(dev);
2857 ixgbe_disable_pcie_master(hw);
2859 /* reprogram the RAR[0] in case user changed it. */
2860 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2867 ixgbe_dev_reset(struct rte_eth_dev *dev)
2871 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2872 * its VF to make them align with it. The detailed notification
2873 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2874 * To avoid unexpected behavior in VF, currently reset of PF with
2875 * SR-IOV activation is not supported. It might be supported later.
2877 if (dev->data->sriov.active)
2880 ret = eth_ixgbe_dev_uninit(dev);
2884 ret = eth_ixgbe_dev_init(dev);
2890 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2891 struct ixgbe_hw_stats *hw_stats,
2892 struct ixgbe_macsec_stats *macsec_stats,
2893 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2894 uint64_t *total_qprc, uint64_t *total_qprdc)
2896 uint32_t bprc, lxon, lxoff, total;
2897 uint32_t delta_gprc = 0;
2899 /* Workaround for RX byte count not including CRC bytes when CRC
2900 * strip is enabled. CRC bytes are removed from counters when crc_strip
2903 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2904 IXGBE_HLREG0_RXCRCSTRP);
2906 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2907 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2908 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2909 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2911 for (i = 0; i < 8; i++) {
2912 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2914 /* global total per queue */
2915 hw_stats->mpc[i] += mp;
2916 /* Running comprehensive total for stats display */
2917 *total_missed_rx += hw_stats->mpc[i];
2918 if (hw->mac.type == ixgbe_mac_82598EB) {
2919 hw_stats->rnbc[i] +=
2920 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2921 hw_stats->pxonrxc[i] +=
2922 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2923 hw_stats->pxoffrxc[i] +=
2924 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2926 hw_stats->pxonrxc[i] +=
2927 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2928 hw_stats->pxoffrxc[i] +=
2929 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2930 hw_stats->pxon2offc[i] +=
2931 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2933 hw_stats->pxontxc[i] +=
2934 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2935 hw_stats->pxofftxc[i] +=
2936 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2938 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2939 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2940 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2941 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2943 delta_gprc += delta_qprc;
2945 hw_stats->qprc[i] += delta_qprc;
2946 hw_stats->qptc[i] += delta_qptc;
2948 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2949 hw_stats->qbrc[i] +=
2950 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2952 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2954 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2955 hw_stats->qbtc[i] +=
2956 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2958 hw_stats->qprdc[i] += delta_qprdc;
2959 *total_qprdc += hw_stats->qprdc[i];
2961 *total_qprc += hw_stats->qprc[i];
2962 *total_qbrc += hw_stats->qbrc[i];
2964 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2965 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2966 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2969 * An errata states that gprc actually counts good + missed packets:
2970 * Workaround to set gprc to summated queue packet receives
2972 hw_stats->gprc = *total_qprc;
2974 if (hw->mac.type != ixgbe_mac_82598EB) {
2975 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2976 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2977 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2978 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2979 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2980 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2981 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2982 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2984 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2985 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2986 /* 82598 only has a counter in the high register */
2987 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2988 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2989 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2991 uint64_t old_tpr = hw_stats->tpr;
2993 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2994 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2997 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2999 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3000 hw_stats->gptc += delta_gptc;
3001 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3002 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3005 * Workaround: mprc hardware is incorrectly counting
3006 * broadcasts, so for now we subtract those.
3008 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3009 hw_stats->bprc += bprc;
3010 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3011 if (hw->mac.type == ixgbe_mac_82598EB)
3012 hw_stats->mprc -= bprc;
3014 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3015 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3016 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3017 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3018 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3019 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3021 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3022 hw_stats->lxontxc += lxon;
3023 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3024 hw_stats->lxofftxc += lxoff;
3025 total = lxon + lxoff;
3027 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3028 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3029 hw_stats->gptc -= total;
3030 hw_stats->mptc -= total;
3031 hw_stats->ptc64 -= total;
3032 hw_stats->gotc -= total * ETHER_MIN_LEN;
3034 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3035 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3036 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3037 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3038 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3039 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3040 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3041 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3042 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3043 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3044 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3045 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3046 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3047 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3048 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3049 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3050 /* Only read FCOE on 82599 */
3051 if (hw->mac.type != ixgbe_mac_82598EB) {
3052 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3053 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3054 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3055 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3056 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3059 /* Flow Director Stats registers */
3060 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3061 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3063 /* MACsec Stats registers */
3064 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3065 macsec_stats->out_pkts_encrypted +=
3066 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3067 macsec_stats->out_pkts_protected +=
3068 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3069 macsec_stats->out_octets_encrypted +=
3070 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3071 macsec_stats->out_octets_protected +=
3072 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3073 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3074 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3075 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3076 macsec_stats->in_pkts_unknownsci +=
3077 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3078 macsec_stats->in_octets_decrypted +=
3079 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3080 macsec_stats->in_octets_validated +=
3081 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3082 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3083 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3084 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3085 for (i = 0; i < 2; i++) {
3086 macsec_stats->in_pkts_ok +=
3087 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3088 macsec_stats->in_pkts_invalid +=
3089 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3090 macsec_stats->in_pkts_notvalid +=
3091 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3093 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3094 macsec_stats->in_pkts_notusingsa +=
3095 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3099 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3102 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3104 struct ixgbe_hw *hw =
3105 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3106 struct ixgbe_hw_stats *hw_stats =
3107 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3108 struct ixgbe_macsec_stats *macsec_stats =
3109 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3110 dev->data->dev_private);
3111 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3114 total_missed_rx = 0;
3119 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3120 &total_qbrc, &total_qprc, &total_qprdc);
3125 /* Fill out the rte_eth_stats statistics structure */
3126 stats->ipackets = total_qprc;
3127 stats->ibytes = total_qbrc;
3128 stats->opackets = hw_stats->gptc;
3129 stats->obytes = hw_stats->gotc;
3131 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3132 stats->q_ipackets[i] = hw_stats->qprc[i];
3133 stats->q_opackets[i] = hw_stats->qptc[i];
3134 stats->q_ibytes[i] = hw_stats->qbrc[i];
3135 stats->q_obytes[i] = hw_stats->qbtc[i];
3136 stats->q_errors[i] = hw_stats->qprdc[i];
3140 stats->imissed = total_missed_rx;
3141 stats->ierrors = hw_stats->crcerrs +
3158 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3160 struct ixgbe_hw_stats *stats =
3161 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3163 /* HW registers are cleared on read */
3164 ixgbe_dev_stats_get(dev, NULL);
3166 /* Reset software totals */
3167 memset(stats, 0, sizeof(*stats));
3170 /* This function calculates the number of xstats based on the current config */
3172 ixgbe_xstats_calc_num(void) {
3173 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3174 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3175 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3178 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3179 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3181 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3182 unsigned stat, i, count;
3184 if (xstats_names != NULL) {
3187 /* Note: limit >= cnt_stats checked upstream
3188 * in rte_eth_xstats_names()
3191 /* Extended stats from ixgbe_hw_stats */
3192 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3193 snprintf(xstats_names[count].name,
3194 sizeof(xstats_names[count].name),
3196 rte_ixgbe_stats_strings[i].name);
3201 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3202 snprintf(xstats_names[count].name,
3203 sizeof(xstats_names[count].name),
3205 rte_ixgbe_macsec_strings[i].name);
3209 /* RX Priority Stats */
3210 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3211 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3212 snprintf(xstats_names[count].name,
3213 sizeof(xstats_names[count].name),
3214 "rx_priority%u_%s", i,
3215 rte_ixgbe_rxq_strings[stat].name);
3220 /* TX Priority Stats */
3221 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3222 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3223 snprintf(xstats_names[count].name,
3224 sizeof(xstats_names[count].name),
3225 "tx_priority%u_%s", i,
3226 rte_ixgbe_txq_strings[stat].name);
3234 static int ixgbe_dev_xstats_get_names_by_id(
3235 struct rte_eth_dev *dev,
3236 struct rte_eth_xstat_name *xstats_names,
3237 const uint64_t *ids,
3241 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3242 unsigned int stat, i, count;
3244 if (xstats_names != NULL) {
3247 /* Note: limit >= cnt_stats checked upstream
3248 * in rte_eth_xstats_names()
3251 /* Extended stats from ixgbe_hw_stats */
3252 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3253 snprintf(xstats_names[count].name,
3254 sizeof(xstats_names[count].name),
3256 rte_ixgbe_stats_strings[i].name);
3261 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3262 snprintf(xstats_names[count].name,
3263 sizeof(xstats_names[count].name),
3265 rte_ixgbe_macsec_strings[i].name);
3269 /* RX Priority Stats */
3270 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3271 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3272 snprintf(xstats_names[count].name,
3273 sizeof(xstats_names[count].name),
3274 "rx_priority%u_%s", i,
3275 rte_ixgbe_rxq_strings[stat].name);
3280 /* TX Priority Stats */
3281 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3282 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3283 snprintf(xstats_names[count].name,
3284 sizeof(xstats_names[count].name),
3285 "tx_priority%u_%s", i,
3286 rte_ixgbe_txq_strings[stat].name);
3295 uint16_t size = ixgbe_xstats_calc_num();
3296 struct rte_eth_xstat_name xstats_names_copy[size];
3298 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3301 for (i = 0; i < limit; i++) {
3302 if (ids[i] >= size) {
3303 PMD_INIT_LOG(ERR, "id value isn't valid");
3306 strcpy(xstats_names[i].name,
3307 xstats_names_copy[ids[i]].name);
3312 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3313 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3317 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3320 if (xstats_names != NULL)
3321 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3322 snprintf(xstats_names[i].name,
3323 sizeof(xstats_names[i].name),
3324 "%s", rte_ixgbevf_stats_strings[i].name);
3325 return IXGBEVF_NB_XSTATS;
3329 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3332 struct ixgbe_hw *hw =
3333 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3334 struct ixgbe_hw_stats *hw_stats =
3335 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3336 struct ixgbe_macsec_stats *macsec_stats =
3337 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3338 dev->data->dev_private);
3339 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3340 unsigned i, stat, count = 0;
3342 count = ixgbe_xstats_calc_num();
3347 total_missed_rx = 0;
3352 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3353 &total_qbrc, &total_qprc, &total_qprdc);
3355 /* If this is a reset xstats is NULL, and we have cleared the
3356 * registers by reading them.
3361 /* Extended stats from ixgbe_hw_stats */
3363 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3364 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3365 rte_ixgbe_stats_strings[i].offset);
3366 xstats[count].id = count;
3371 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3372 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3373 rte_ixgbe_macsec_strings[i].offset);
3374 xstats[count].id = count;
3378 /* RX Priority Stats */
3379 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3380 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3381 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3382 rte_ixgbe_rxq_strings[stat].offset +
3383 (sizeof(uint64_t) * i));
3384 xstats[count].id = count;
3389 /* TX Priority Stats */
3390 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3391 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3392 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3393 rte_ixgbe_txq_strings[stat].offset +
3394 (sizeof(uint64_t) * i));
3395 xstats[count].id = count;
3403 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3404 uint64_t *values, unsigned int n)
3407 struct ixgbe_hw *hw =
3408 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3409 struct ixgbe_hw_stats *hw_stats =
3410 IXGBE_DEV_PRIVATE_TO_STATS(
3411 dev->data->dev_private);
3412 struct ixgbe_macsec_stats *macsec_stats =
3413 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3414 dev->data->dev_private);
3415 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3416 unsigned int i, stat, count = 0;
3418 count = ixgbe_xstats_calc_num();
3420 if (!ids && n < count)
3423 total_missed_rx = 0;
3428 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3429 &total_missed_rx, &total_qbrc, &total_qprc,
3432 /* If this is a reset xstats is NULL, and we have cleared the
3433 * registers by reading them.
3435 if (!ids && !values)
3438 /* Extended stats from ixgbe_hw_stats */
3440 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3441 values[count] = *(uint64_t *)(((char *)hw_stats) +
3442 rte_ixgbe_stats_strings[i].offset);
3447 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3448 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3449 rte_ixgbe_macsec_strings[i].offset);
3453 /* RX Priority Stats */
3454 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3455 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3457 *(uint64_t *)(((char *)hw_stats) +
3458 rte_ixgbe_rxq_strings[stat].offset +
3459 (sizeof(uint64_t) * i));
3464 /* TX Priority Stats */
3465 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3466 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3468 *(uint64_t *)(((char *)hw_stats) +
3469 rte_ixgbe_txq_strings[stat].offset +
3470 (sizeof(uint64_t) * i));
3478 uint16_t size = ixgbe_xstats_calc_num();
3479 uint64_t values_copy[size];
3481 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3483 for (i = 0; i < n; i++) {
3484 if (ids[i] >= size) {
3485 PMD_INIT_LOG(ERR, "id value isn't valid");
3488 values[i] = values_copy[ids[i]];
3494 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3496 struct ixgbe_hw_stats *stats =
3497 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3498 struct ixgbe_macsec_stats *macsec_stats =
3499 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3500 dev->data->dev_private);
3502 unsigned count = ixgbe_xstats_calc_num();
3504 /* HW registers are cleared on read */
3505 ixgbe_dev_xstats_get(dev, NULL, count);
3507 /* Reset software totals */
3508 memset(stats, 0, sizeof(*stats));
3509 memset(macsec_stats, 0, sizeof(*macsec_stats));
3513 ixgbevf_update_stats(struct rte_eth_dev *dev)
3515 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3516 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3517 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3519 /* Good Rx packet, include VF loopback */
3520 UPDATE_VF_STAT(IXGBE_VFGPRC,
3521 hw_stats->last_vfgprc, hw_stats->vfgprc);
3523 /* Good Rx octets, include VF loopback */
3524 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3525 hw_stats->last_vfgorc, hw_stats->vfgorc);
3527 /* Good Tx packet, include VF loopback */
3528 UPDATE_VF_STAT(IXGBE_VFGPTC,
3529 hw_stats->last_vfgptc, hw_stats->vfgptc);
3531 /* Good Tx octets, include VF loopback */
3532 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3533 hw_stats->last_vfgotc, hw_stats->vfgotc);
3535 /* Rx Multicst Packet */
3536 UPDATE_VF_STAT(IXGBE_VFMPRC,
3537 hw_stats->last_vfmprc, hw_stats->vfmprc);
3541 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3544 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3545 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3548 if (n < IXGBEVF_NB_XSTATS)
3549 return IXGBEVF_NB_XSTATS;
3551 ixgbevf_update_stats(dev);
3556 /* Extended stats */
3557 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3559 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3560 rte_ixgbevf_stats_strings[i].offset);
3563 return IXGBEVF_NB_XSTATS;
3567 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3569 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3570 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3572 ixgbevf_update_stats(dev);
3577 stats->ipackets = hw_stats->vfgprc;
3578 stats->ibytes = hw_stats->vfgorc;
3579 stats->opackets = hw_stats->vfgptc;
3580 stats->obytes = hw_stats->vfgotc;
3585 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3587 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3588 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3590 /* Sync HW register to the last stats */
3591 ixgbevf_dev_stats_get(dev, NULL);
3593 /* reset HW current stats*/
3594 hw_stats->vfgprc = 0;
3595 hw_stats->vfgorc = 0;
3596 hw_stats->vfgptc = 0;
3597 hw_stats->vfgotc = 0;
3601 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3603 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3604 u16 eeprom_verh, eeprom_verl;
3608 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3609 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3611 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3612 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3614 ret += 1; /* add the size of '\0' */
3615 if (fw_size < (u32)ret)
3622 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3624 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3625 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3626 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3628 dev_info->pci_dev = pci_dev;
3629 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3630 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3631 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3633 * When DCB/VT is off, maximum number of queues changes,
3634 * except for 82598EB, which remains constant.
3636 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3637 hw->mac.type != ixgbe_mac_82598EB)
3638 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3640 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3641 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3642 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3643 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3644 dev_info->max_vfs = pci_dev->max_vfs;
3645 if (hw->mac.type == ixgbe_mac_82598EB)
3646 dev_info->max_vmdq_pools = ETH_16_POOLS;
3648 dev_info->max_vmdq_pools = ETH_64_POOLS;
3649 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3650 dev_info->rx_offload_capa =
3651 DEV_RX_OFFLOAD_VLAN_STRIP |
3652 DEV_RX_OFFLOAD_IPV4_CKSUM |
3653 DEV_RX_OFFLOAD_UDP_CKSUM |
3654 DEV_RX_OFFLOAD_TCP_CKSUM;
3657 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3660 if ((hw->mac.type == ixgbe_mac_82599EB ||
3661 hw->mac.type == ixgbe_mac_X540) &&
3662 !RTE_ETH_DEV_SRIOV(dev).active)
3663 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3665 if (hw->mac.type == ixgbe_mac_82599EB ||
3666 hw->mac.type == ixgbe_mac_X540)
3667 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3669 if (hw->mac.type == ixgbe_mac_X550 ||
3670 hw->mac.type == ixgbe_mac_X550EM_x ||
3671 hw->mac.type == ixgbe_mac_X550EM_a)
3672 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3674 dev_info->tx_offload_capa =
3675 DEV_TX_OFFLOAD_VLAN_INSERT |
3676 DEV_TX_OFFLOAD_IPV4_CKSUM |
3677 DEV_TX_OFFLOAD_UDP_CKSUM |
3678 DEV_TX_OFFLOAD_TCP_CKSUM |
3679 DEV_TX_OFFLOAD_SCTP_CKSUM |
3680 DEV_TX_OFFLOAD_TCP_TSO;
3682 if (hw->mac.type == ixgbe_mac_82599EB ||
3683 hw->mac.type == ixgbe_mac_X540)
3684 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3686 if (hw->mac.type == ixgbe_mac_X550 ||
3687 hw->mac.type == ixgbe_mac_X550EM_x ||
3688 hw->mac.type == ixgbe_mac_X550EM_a)
3689 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3691 #ifdef RTE_LIBRTE_SECURITY
3692 if (dev->security_ctx) {
3693 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
3694 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
3698 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3700 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3701 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3702 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3704 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3708 dev_info->default_txconf = (struct rte_eth_txconf) {
3710 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3711 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3712 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3714 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3715 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3716 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3717 ETH_TXQ_FLAGS_NOOFFLOADS,
3720 dev_info->rx_desc_lim = rx_desc_lim;
3721 dev_info->tx_desc_lim = tx_desc_lim;
3723 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3724 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3725 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3727 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3728 if (hw->mac.type == ixgbe_mac_X540 ||
3729 hw->mac.type == ixgbe_mac_X540_vf ||
3730 hw->mac.type == ixgbe_mac_X550 ||
3731 hw->mac.type == ixgbe_mac_X550_vf) {
3732 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3734 if (hw->mac.type == ixgbe_mac_X550) {
3735 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3736 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3740 static const uint32_t *
3741 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3743 static const uint32_t ptypes[] = {
3744 /* For non-vec functions,
3745 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3746 * for vec functions,
3747 * refers to _recv_raw_pkts_vec().
3751 RTE_PTYPE_L3_IPV4_EXT,
3753 RTE_PTYPE_L3_IPV6_EXT,
3757 RTE_PTYPE_TUNNEL_IP,
3758 RTE_PTYPE_INNER_L3_IPV6,
3759 RTE_PTYPE_INNER_L3_IPV6_EXT,
3760 RTE_PTYPE_INNER_L4_TCP,
3761 RTE_PTYPE_INNER_L4_UDP,
3765 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3766 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3767 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3768 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3771 #if defined(RTE_ARCH_X86)
3772 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3773 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3780 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3781 struct rte_eth_dev_info *dev_info)
3783 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3784 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3786 dev_info->pci_dev = pci_dev;
3787 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3788 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3789 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3790 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3791 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3792 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3793 dev_info->max_vfs = pci_dev->max_vfs;
3794 if (hw->mac.type == ixgbe_mac_82598EB)
3795 dev_info->max_vmdq_pools = ETH_16_POOLS;
3797 dev_info->max_vmdq_pools = ETH_64_POOLS;
3798 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3799 DEV_RX_OFFLOAD_IPV4_CKSUM |
3800 DEV_RX_OFFLOAD_UDP_CKSUM |
3801 DEV_RX_OFFLOAD_TCP_CKSUM;
3802 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3803 DEV_TX_OFFLOAD_IPV4_CKSUM |
3804 DEV_TX_OFFLOAD_UDP_CKSUM |
3805 DEV_TX_OFFLOAD_TCP_CKSUM |
3806 DEV_TX_OFFLOAD_SCTP_CKSUM |
3807 DEV_TX_OFFLOAD_TCP_TSO;
3809 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3811 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3812 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3813 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3815 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3819 dev_info->default_txconf = (struct rte_eth_txconf) {
3821 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3822 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3823 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3825 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3826 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3827 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3828 ETH_TXQ_FLAGS_NOOFFLOADS,
3831 dev_info->rx_desc_lim = rx_desc_lim;
3832 dev_info->tx_desc_lim = tx_desc_lim;
3836 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3837 int *link_up, int wait_to_complete)
3840 * for a quick link status checking, wait_to_compelet == 0,
3841 * skip PF link status checking
3843 bool no_pflink_check = wait_to_complete == 0;
3844 struct ixgbe_mbx_info *mbx = &hw->mbx;
3845 struct ixgbe_mac_info *mac = &hw->mac;
3846 uint32_t links_reg, in_msg;
3849 /* If we were hit with a reset drop the link */
3850 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3851 mac->get_link_status = true;
3853 if (!mac->get_link_status)
3856 /* if link status is down no point in checking to see if pf is up */
3857 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3858 if (!(links_reg & IXGBE_LINKS_UP))
3861 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3862 * before the link status is correct
3864 if (mac->type == ixgbe_mac_82599_vf) {
3867 for (i = 0; i < 5; i++) {
3869 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3871 if (!(links_reg & IXGBE_LINKS_UP))
3876 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3877 case IXGBE_LINKS_SPEED_10G_82599:
3878 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3879 if (hw->mac.type >= ixgbe_mac_X550) {
3880 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3881 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3884 case IXGBE_LINKS_SPEED_1G_82599:
3885 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3887 case IXGBE_LINKS_SPEED_100_82599:
3888 *speed = IXGBE_LINK_SPEED_100_FULL;
3889 if (hw->mac.type == ixgbe_mac_X550) {
3890 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3891 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3894 case IXGBE_LINKS_SPEED_10_X550EM_A:
3895 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3896 /* Since Reserved in older MAC's */
3897 if (hw->mac.type >= ixgbe_mac_X550)
3898 *speed = IXGBE_LINK_SPEED_10_FULL;
3901 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3904 if (no_pflink_check) {
3905 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3906 mac->get_link_status = true;
3908 mac->get_link_status = false;
3912 /* if the read failed it could just be a mailbox collision, best wait
3913 * until we are called again and don't report an error
3915 if (mbx->ops.read(hw, &in_msg, 1, 0))
3918 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3919 /* msg is not CTS and is NACK we must have lost CTS status */
3920 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3925 /* the pf is talking, if we timed out in the past we reinit */
3926 if (!mbx->timeout) {
3931 /* if we passed all the tests above then the link is up and we no
3932 * longer need to check for link
3934 mac->get_link_status = false;
3937 *link_up = !mac->get_link_status;
3941 /* return 0 means link status changed, -1 means not changed */
3943 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3944 int wait_to_complete, int vf)
3946 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3947 struct rte_eth_link link, old;
3948 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3949 struct ixgbe_interrupt *intr =
3950 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3955 bool autoneg = false;
3957 link.link_status = ETH_LINK_DOWN;
3958 link.link_speed = 0;
3959 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3960 link.link_autoneg = ETH_LINK_AUTONEG;
3961 memset(&old, 0, sizeof(old));
3962 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3964 hw->mac.get_link_status = true;
3966 if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3967 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3968 speed = hw->phy.autoneg_advertised;
3970 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3971 ixgbe_setup_link(hw, speed, true);
3974 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3975 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3979 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3981 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3984 link.link_speed = ETH_SPEED_NUM_100M;
3985 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3986 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3987 if (link.link_status == old.link_status)
3993 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3994 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3995 if (link.link_status == old.link_status)
3999 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4000 link.link_status = ETH_LINK_UP;
4001 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4003 switch (link_speed) {
4005 case IXGBE_LINK_SPEED_UNKNOWN:
4006 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4007 link.link_speed = ETH_SPEED_NUM_100M;
4010 case IXGBE_LINK_SPEED_100_FULL:
4011 link.link_speed = ETH_SPEED_NUM_100M;
4014 case IXGBE_LINK_SPEED_1GB_FULL:
4015 link.link_speed = ETH_SPEED_NUM_1G;
4018 case IXGBE_LINK_SPEED_2_5GB_FULL:
4019 link.link_speed = ETH_SPEED_NUM_2_5G;
4022 case IXGBE_LINK_SPEED_5GB_FULL:
4023 link.link_speed = ETH_SPEED_NUM_5G;
4026 case IXGBE_LINK_SPEED_10GB_FULL:
4027 link.link_speed = ETH_SPEED_NUM_10G;
4030 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4032 if (link.link_status == old.link_status)
4039 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4041 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4045 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4047 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4051 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4053 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4056 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4057 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4058 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4062 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4064 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4067 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4068 fctrl &= (~IXGBE_FCTRL_UPE);
4069 if (dev->data->all_multicast == 1)
4070 fctrl |= IXGBE_FCTRL_MPE;
4072 fctrl &= (~IXGBE_FCTRL_MPE);
4073 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4077 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4079 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4082 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4083 fctrl |= IXGBE_FCTRL_MPE;
4084 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4088 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4090 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4093 if (dev->data->promiscuous == 1)
4094 return; /* must remain in all_multicast mode */
4096 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4097 fctrl &= (~IXGBE_FCTRL_MPE);
4098 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4102 * It clears the interrupt causes and enables the interrupt.
4103 * It will be called once only during nic initialized.
4106 * Pointer to struct rte_eth_dev.
4108 * Enable or Disable.
4111 * - On success, zero.
4112 * - On failure, a negative value.
4115 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4117 struct ixgbe_interrupt *intr =
4118 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4120 ixgbe_dev_link_status_print(dev);
4122 intr->mask |= IXGBE_EICR_LSC;
4124 intr->mask &= ~IXGBE_EICR_LSC;
4130 * It clears the interrupt causes and enables the interrupt.
4131 * It will be called once only during nic initialized.
4134 * Pointer to struct rte_eth_dev.
4137 * - On success, zero.
4138 * - On failure, a negative value.
4141 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4143 struct ixgbe_interrupt *intr =
4144 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4146 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4152 * It clears the interrupt causes and enables the interrupt.
4153 * It will be called once only during nic initialized.
4156 * Pointer to struct rte_eth_dev.
4159 * - On success, zero.
4160 * - On failure, a negative value.
4163 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4165 struct ixgbe_interrupt *intr =
4166 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4168 intr->mask |= IXGBE_EICR_LINKSEC;
4174 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4177 * Pointer to struct rte_eth_dev.
4180 * - On success, zero.
4181 * - On failure, a negative value.
4184 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4187 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4188 struct ixgbe_interrupt *intr =
4189 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4191 /* clear all cause mask */
4192 ixgbe_disable_intr(hw);
4194 /* read-on-clear nic registers here */
4195 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4196 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4200 /* set flag for async link update */
4201 if (eicr & IXGBE_EICR_LSC)
4202 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4204 if (eicr & IXGBE_EICR_MAILBOX)
4205 intr->flags |= IXGBE_FLAG_MAILBOX;
4207 if (eicr & IXGBE_EICR_LINKSEC)
4208 intr->flags |= IXGBE_FLAG_MACSEC;
4210 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4211 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4212 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4213 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4219 * It gets and then prints the link status.
4222 * Pointer to struct rte_eth_dev.
4225 * - On success, zero.
4226 * - On failure, a negative value.
4229 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4231 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4232 struct rte_eth_link link;
4234 memset(&link, 0, sizeof(link));
4235 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4236 if (link.link_status) {
4237 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4238 (int)(dev->data->port_id),
4239 (unsigned)link.link_speed,
4240 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4241 "full-duplex" : "half-duplex");
4243 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4244 (int)(dev->data->port_id));
4246 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4247 pci_dev->addr.domain,
4249 pci_dev->addr.devid,
4250 pci_dev->addr.function);
4254 * It executes link_update after knowing an interrupt occurred.
4257 * Pointer to struct rte_eth_dev.
4260 * - On success, zero.
4261 * - On failure, a negative value.
4264 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4265 struct rte_intr_handle *intr_handle)
4267 struct ixgbe_interrupt *intr =
4268 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4270 struct rte_eth_link link;
4271 struct ixgbe_hw *hw =
4272 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4274 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4276 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4277 ixgbe_pf_mbx_process(dev);
4278 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4281 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4282 ixgbe_handle_lasi(hw);
4283 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4286 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4287 /* get the link status before link update, for predicting later */
4288 memset(&link, 0, sizeof(link));
4289 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4291 ixgbe_dev_link_update(dev, 0);
4294 if (!link.link_status)
4295 /* handle it 1 sec later, wait it being stable */
4296 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4297 /* likely to down */
4299 /* handle it 4 sec later, wait it being stable */
4300 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4302 ixgbe_dev_link_status_print(dev);
4303 if (rte_eal_alarm_set(timeout * 1000,
4304 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4305 PMD_DRV_LOG(ERR, "Error setting alarm");
4307 /* remember original mask */
4308 intr->mask_original = intr->mask;
4309 /* only disable lsc interrupt */
4310 intr->mask &= ~IXGBE_EIMS_LSC;
4314 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4315 ixgbe_enable_intr(dev);
4316 rte_intr_enable(intr_handle);
4322 * Interrupt handler which shall be registered for alarm callback for delayed
4323 * handling specific interrupt to wait for the stable nic state. As the
4324 * NIC interrupt state is not stable for ixgbe after link is just down,
4325 * it needs to wait 4 seconds to get the stable status.
4328 * Pointer to interrupt handle.
4330 * The address of parameter (struct rte_eth_dev *) regsitered before.
4336 ixgbe_dev_interrupt_delayed_handler(void *param)
4338 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4339 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4340 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4341 struct ixgbe_interrupt *intr =
4342 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4343 struct ixgbe_hw *hw =
4344 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4347 ixgbe_disable_intr(hw);
4349 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4350 if (eicr & IXGBE_EICR_MAILBOX)
4351 ixgbe_pf_mbx_process(dev);
4353 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4354 ixgbe_handle_lasi(hw);
4355 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4358 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4359 ixgbe_dev_link_update(dev, 0);
4360 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4361 ixgbe_dev_link_status_print(dev);
4362 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4366 if (intr->flags & IXGBE_FLAG_MACSEC) {
4367 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4369 intr->flags &= ~IXGBE_FLAG_MACSEC;
4372 /* restore original mask */
4373 intr->mask = intr->mask_original;
4374 intr->mask_original = 0;
4376 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4377 ixgbe_enable_intr(dev);
4378 rte_intr_enable(intr_handle);
4382 * Interrupt handler triggered by NIC for handling
4383 * specific interrupt.
4386 * Pointer to interrupt handle.
4388 * The address of parameter (struct rte_eth_dev *) regsitered before.
4394 ixgbe_dev_interrupt_handler(void *param)
4396 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4398 ixgbe_dev_interrupt_get_status(dev);
4399 ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4403 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4405 struct ixgbe_hw *hw;
4407 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4408 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4412 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4414 struct ixgbe_hw *hw;
4416 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4417 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4421 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4423 struct ixgbe_hw *hw;
4429 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4431 fc_conf->pause_time = hw->fc.pause_time;
4432 fc_conf->high_water = hw->fc.high_water[0];
4433 fc_conf->low_water = hw->fc.low_water[0];
4434 fc_conf->send_xon = hw->fc.send_xon;
4435 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4438 * Return rx_pause status according to actual setting of
4441 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4442 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4448 * Return tx_pause status according to actual setting of
4451 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4452 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4457 if (rx_pause && tx_pause)
4458 fc_conf->mode = RTE_FC_FULL;
4460 fc_conf->mode = RTE_FC_RX_PAUSE;
4462 fc_conf->mode = RTE_FC_TX_PAUSE;
4464 fc_conf->mode = RTE_FC_NONE;
4470 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4472 struct ixgbe_hw *hw;
4474 uint32_t rx_buf_size;
4475 uint32_t max_high_water;
4477 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4484 PMD_INIT_FUNC_TRACE();
4486 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4487 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4488 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4491 * At least reserve one Ethernet frame for watermark
4492 * high_water/low_water in kilo bytes for ixgbe
4494 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4495 if ((fc_conf->high_water > max_high_water) ||
4496 (fc_conf->high_water < fc_conf->low_water)) {
4497 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4498 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4502 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4503 hw->fc.pause_time = fc_conf->pause_time;
4504 hw->fc.high_water[0] = fc_conf->high_water;
4505 hw->fc.low_water[0] = fc_conf->low_water;
4506 hw->fc.send_xon = fc_conf->send_xon;
4507 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4509 err = ixgbe_fc_enable(hw);
4511 /* Not negotiated is not an error case */
4512 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4514 /* check if we want to forward MAC frames - driver doesn't have native
4515 * capability to do that, so we'll write the registers ourselves */
4517 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4519 /* set or clear MFLCN.PMCF bit depending on configuration */
4520 if (fc_conf->mac_ctrl_frame_fwd != 0)
4521 mflcn |= IXGBE_MFLCN_PMCF;
4523 mflcn &= ~IXGBE_MFLCN_PMCF;
4525 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4526 IXGBE_WRITE_FLUSH(hw);
4531 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4536 * ixgbe_pfc_enable_generic - Enable flow control
4537 * @hw: pointer to hardware structure
4538 * @tc_num: traffic class number
4539 * Enable flow control according to the current settings.
4542 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4545 uint32_t mflcn_reg, fccfg_reg;
4547 uint32_t fcrtl, fcrth;
4551 /* Validate the water mark configuration */
4552 if (!hw->fc.pause_time) {
4553 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4557 /* Low water mark of zero causes XOFF floods */
4558 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4559 /* High/Low water can not be 0 */
4560 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4561 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4562 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4566 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4567 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4568 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4572 /* Negotiate the fc mode to use */
4573 ixgbe_fc_autoneg(hw);
4575 /* Disable any previous flow control settings */
4576 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4577 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4579 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4580 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4582 switch (hw->fc.current_mode) {
4585 * If the count of enabled RX Priority Flow control >1,
4586 * and the TX pause can not be disabled
4589 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4590 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4591 if (reg & IXGBE_FCRTH_FCEN)
4595 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4597 case ixgbe_fc_rx_pause:
4599 * Rx Flow control is enabled and Tx Flow control is
4600 * disabled by software override. Since there really
4601 * isn't a way to advertise that we are capable of RX
4602 * Pause ONLY, we will advertise that we support both
4603 * symmetric and asymmetric Rx PAUSE. Later, we will
4604 * disable the adapter's ability to send PAUSE frames.
4606 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4608 * If the count of enabled RX Priority Flow control >1,
4609 * and the TX pause can not be disabled
4612 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4613 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4614 if (reg & IXGBE_FCRTH_FCEN)
4618 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4620 case ixgbe_fc_tx_pause:
4622 * Tx Flow control is enabled, and Rx Flow control is
4623 * disabled by software override.
4625 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4628 /* Flow control (both Rx and Tx) is enabled by SW override. */
4629 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4630 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4633 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4634 ret_val = IXGBE_ERR_CONFIG;
4638 /* Set 802.3x based flow control settings. */
4639 mflcn_reg |= IXGBE_MFLCN_DPF;
4640 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4641 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4643 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4644 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4645 hw->fc.high_water[tc_num]) {
4646 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4647 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4648 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4650 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4652 * In order to prevent Tx hangs when the internal Tx
4653 * switch is enabled we must set the high water mark
4654 * to the maximum FCRTH value. This allows the Tx
4655 * switch to function even under heavy Rx workloads.
4657 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4659 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4661 /* Configure pause time (2 TCs per register) */
4662 reg = hw->fc.pause_time * 0x00010001;
4663 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4664 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4666 /* Configure flow control refresh threshold value */
4667 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4674 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4676 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4677 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4679 if (hw->mac.type != ixgbe_mac_82598EB) {
4680 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4686 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4689 uint32_t rx_buf_size;
4690 uint32_t max_high_water;
4692 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4693 struct ixgbe_hw *hw =
4694 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4695 struct ixgbe_dcb_config *dcb_config =
4696 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4698 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4705 PMD_INIT_FUNC_TRACE();
4707 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4708 tc_num = map[pfc_conf->priority];
4709 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4710 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4712 * At least reserve one Ethernet frame for watermark
4713 * high_water/low_water in kilo bytes for ixgbe
4715 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4716 if ((pfc_conf->fc.high_water > max_high_water) ||
4717 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4718 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4719 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4723 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4724 hw->fc.pause_time = pfc_conf->fc.pause_time;
4725 hw->fc.send_xon = pfc_conf->fc.send_xon;
4726 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4727 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4729 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4731 /* Not negotiated is not an error case */
4732 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4735 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4740 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4741 struct rte_eth_rss_reta_entry64 *reta_conf,
4744 uint16_t i, sp_reta_size;
4747 uint16_t idx, shift;
4748 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4751 PMD_INIT_FUNC_TRACE();
4753 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4754 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4759 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4760 if (reta_size != sp_reta_size) {
4761 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4762 "(%d) doesn't match the number hardware can supported "
4763 "(%d)", reta_size, sp_reta_size);
4767 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4768 idx = i / RTE_RETA_GROUP_SIZE;
4769 shift = i % RTE_RETA_GROUP_SIZE;
4770 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4774 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4775 if (mask == IXGBE_4_BIT_MASK)
4778 r = IXGBE_READ_REG(hw, reta_reg);
4779 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4780 if (mask & (0x1 << j))
4781 reta |= reta_conf[idx].reta[shift + j] <<
4784 reta |= r & (IXGBE_8_BIT_MASK <<
4787 IXGBE_WRITE_REG(hw, reta_reg, reta);
4794 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4795 struct rte_eth_rss_reta_entry64 *reta_conf,
4798 uint16_t i, sp_reta_size;
4801 uint16_t idx, shift;
4802 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4805 PMD_INIT_FUNC_TRACE();
4806 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4807 if (reta_size != sp_reta_size) {
4808 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4809 "(%d) doesn't match the number hardware can supported "
4810 "(%d)", reta_size, sp_reta_size);
4814 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4815 idx = i / RTE_RETA_GROUP_SIZE;
4816 shift = i % RTE_RETA_GROUP_SIZE;
4817 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4822 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4823 reta = IXGBE_READ_REG(hw, reta_reg);
4824 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4825 if (mask & (0x1 << j))
4826 reta_conf[idx].reta[shift + j] =
4827 ((reta >> (CHAR_BIT * j)) &
4836 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4837 uint32_t index, uint32_t pool)
4839 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4840 uint32_t enable_addr = 1;
4842 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4847 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4849 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4851 ixgbe_clear_rar(hw, index);
4855 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4857 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4859 ixgbe_remove_rar(dev, 0);
4861 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4865 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4867 if (strcmp(dev->device->driver->name, drv->driver.name))
4874 is_ixgbe_supported(struct rte_eth_dev *dev)
4876 return is_device_supported(dev, &rte_ixgbe_pmd);
4880 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4884 struct ixgbe_hw *hw;
4885 struct rte_eth_dev_info dev_info;
4886 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4887 struct rte_eth_dev_data *dev_data = dev->data;
4889 ixgbe_dev_info_get(dev, &dev_info);
4891 /* check that mtu is within the allowed range */
4892 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4895 /* If device is started, refuse mtu that requires the support of
4896 * scattered packets when this feature has not been enabled before.
4898 if (dev_data->dev_started && !dev_data->scattered_rx &&
4899 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4900 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4901 PMD_INIT_LOG(ERR, "Stop port first.");
4905 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4906 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4908 /* switch to jumbo mode if needed */
4909 if (frame_size > ETHER_MAX_LEN) {
4910 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4911 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4913 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4914 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4916 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4918 /* update max frame size */
4919 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4921 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4922 maxfrs &= 0x0000FFFF;
4923 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4924 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4930 * Virtual Function operations
4933 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4935 PMD_INIT_FUNC_TRACE();
4937 /* Clear interrupt mask to stop from interrupts being generated */
4938 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4940 IXGBE_WRITE_FLUSH(hw);
4944 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4946 PMD_INIT_FUNC_TRACE();
4948 /* VF enable interrupt autoclean */
4949 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4950 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4951 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4953 IXGBE_WRITE_FLUSH(hw);
4957 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4959 struct rte_eth_conf *conf = &dev->data->dev_conf;
4960 struct ixgbe_adapter *adapter =
4961 (struct ixgbe_adapter *)dev->data->dev_private;
4963 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4964 dev->data->port_id);
4967 * VF has no ability to enable/disable HW CRC
4968 * Keep the persistent behavior the same as Host PF
4970 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4971 if (!conf->rxmode.hw_strip_crc) {
4972 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4973 conf->rxmode.hw_strip_crc = 1;
4976 if (conf->rxmode.hw_strip_crc) {
4977 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4978 conf->rxmode.hw_strip_crc = 0;
4983 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4984 * allocation or vector Rx preconditions we will reset it.
4986 adapter->rx_bulk_alloc_allowed = true;
4987 adapter->rx_vec_allowed = true;
4993 ixgbevf_dev_start(struct rte_eth_dev *dev)
4995 struct ixgbe_hw *hw =
4996 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4997 uint32_t intr_vector = 0;
4998 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4999 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5003 PMD_INIT_FUNC_TRACE();
5005 hw->mac.ops.reset_hw(hw);
5006 hw->mac.get_link_status = true;
5008 /* negotiate mailbox API version to use with the PF. */
5009 ixgbevf_negotiate_api(hw);
5011 ixgbevf_dev_tx_init(dev);
5013 /* This can fail when allocating mbufs for descriptor rings */
5014 err = ixgbevf_dev_rx_init(dev);
5016 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5017 ixgbe_dev_clear_queues(dev);
5022 ixgbevf_set_vfta_all(dev, 1);
5025 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5026 ETH_VLAN_EXTEND_MASK;
5027 err = ixgbevf_vlan_offload_set(dev, mask);
5029 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5030 ixgbe_dev_clear_queues(dev);
5034 ixgbevf_dev_rxtx_start(dev);
5036 /* check and configure queue intr-vector mapping */
5037 if (rte_intr_cap_multiple(intr_handle) &&
5038 dev->data->dev_conf.intr_conf.rxq) {
5039 /* According to datasheet, only vector 0/1/2 can be used,
5040 * now only one vector is used for Rx queue
5043 if (rte_intr_efd_enable(intr_handle, intr_vector))
5047 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5048 intr_handle->intr_vec =
5049 rte_zmalloc("intr_vec",
5050 dev->data->nb_rx_queues * sizeof(int), 0);
5051 if (intr_handle->intr_vec == NULL) {
5052 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5053 " intr_vec", dev->data->nb_rx_queues);
5057 ixgbevf_configure_msix(dev);
5059 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5060 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5061 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5062 * is not cleared, it will fail when following rte_intr_enable( ) tries
5063 * to map Rx queue interrupt to other VFIO vectors.
5064 * So clear uio/vfio intr/evevnfd first to avoid failure.
5066 rte_intr_disable(intr_handle);
5068 rte_intr_enable(intr_handle);
5070 /* Re-enable interrupt for VF */
5071 ixgbevf_intr_enable(hw);
5077 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5079 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5080 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5081 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5083 PMD_INIT_FUNC_TRACE();
5085 ixgbevf_intr_disable(hw);
5087 hw->adapter_stopped = 1;
5088 ixgbe_stop_adapter(hw);
5091 * Clear what we set, but we still keep shadow_vfta to
5092 * restore after device starts
5094 ixgbevf_set_vfta_all(dev, 0);
5096 /* Clear stored conf */
5097 dev->data->scattered_rx = 0;
5099 ixgbe_dev_clear_queues(dev);
5101 /* Clean datapath event and queue/vec mapping */
5102 rte_intr_efd_disable(intr_handle);
5103 if (intr_handle->intr_vec != NULL) {
5104 rte_free(intr_handle->intr_vec);
5105 intr_handle->intr_vec = NULL;
5110 ixgbevf_dev_close(struct rte_eth_dev *dev)
5112 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5114 PMD_INIT_FUNC_TRACE();
5118 ixgbevf_dev_stop(dev);
5120 ixgbe_dev_free_queues(dev);
5123 * Remove the VF MAC address ro ensure
5124 * that the VF traffic goes to the PF
5125 * after stop, close and detach of the VF
5127 ixgbevf_remove_mac_addr(dev, 0);
5134 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5138 ret = eth_ixgbevf_dev_uninit(dev);
5142 ret = eth_ixgbevf_dev_init(dev);
5147 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5149 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5150 struct ixgbe_vfta *shadow_vfta =
5151 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5152 int i = 0, j = 0, vfta = 0, mask = 1;
5154 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5155 vfta = shadow_vfta->vfta[i];
5158 for (j = 0; j < 32; j++) {
5160 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5170 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5172 struct ixgbe_hw *hw =
5173 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5174 struct ixgbe_vfta *shadow_vfta =
5175 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5176 uint32_t vid_idx = 0;
5177 uint32_t vid_bit = 0;
5180 PMD_INIT_FUNC_TRACE();
5182 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5183 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5185 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5188 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5189 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5191 /* Save what we set and retore it after device reset */
5193 shadow_vfta->vfta[vid_idx] |= vid_bit;
5195 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5201 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5203 struct ixgbe_hw *hw =
5204 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5207 PMD_INIT_FUNC_TRACE();
5209 if (queue >= hw->mac.max_rx_queues)
5212 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5214 ctrl |= IXGBE_RXDCTL_VME;
5216 ctrl &= ~IXGBE_RXDCTL_VME;
5217 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5219 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5223 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5225 struct ixgbe_hw *hw =
5226 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5230 /* VF function only support hw strip feature, others are not support */
5231 if (mask & ETH_VLAN_STRIP_MASK) {
5232 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5234 for (i = 0; i < hw->mac.max_rx_queues; i++)
5235 ixgbevf_vlan_strip_queue_set(dev, i, on);
5242 ixgbe_vt_check(struct ixgbe_hw *hw)
5246 /* if Virtualization Technology is enabled */
5247 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5248 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5249 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5257 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5259 uint32_t vector = 0;
5261 switch (hw->mac.mc_filter_type) {
5262 case 0: /* use bits [47:36] of the address */
5263 vector = ((uc_addr->addr_bytes[4] >> 4) |
5264 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5266 case 1: /* use bits [46:35] of the address */
5267 vector = ((uc_addr->addr_bytes[4] >> 3) |
5268 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5270 case 2: /* use bits [45:34] of the address */
5271 vector = ((uc_addr->addr_bytes[4] >> 2) |
5272 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5274 case 3: /* use bits [43:32] of the address */
5275 vector = ((uc_addr->addr_bytes[4]) |
5276 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5278 default: /* Invalid mc_filter_type */
5282 /* vector can only be 12-bits or boundary will be exceeded */
5288 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5296 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5297 const uint32_t ixgbe_uta_bit_shift = 5;
5298 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5299 const uint32_t bit1 = 0x1;
5301 struct ixgbe_hw *hw =
5302 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5303 struct ixgbe_uta_info *uta_info =
5304 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5306 /* The UTA table only exists on 82599 hardware and newer */
5307 if (hw->mac.type < ixgbe_mac_82599EB)
5310 vector = ixgbe_uta_vector(hw, mac_addr);
5311 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5312 uta_shift = vector & ixgbe_uta_bit_mask;
5314 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5318 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5320 uta_info->uta_in_use++;
5321 reg_val |= (bit1 << uta_shift);
5322 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5324 uta_info->uta_in_use--;
5325 reg_val &= ~(bit1 << uta_shift);
5326 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5329 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5331 if (uta_info->uta_in_use > 0)
5332 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5333 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5335 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5341 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5344 struct ixgbe_hw *hw =
5345 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5346 struct ixgbe_uta_info *uta_info =
5347 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5349 /* The UTA table only exists on 82599 hardware and newer */
5350 if (hw->mac.type < ixgbe_mac_82599EB)
5354 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5355 uta_info->uta_shadow[i] = ~0;
5356 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5359 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5360 uta_info->uta_shadow[i] = 0;
5361 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5369 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5371 uint32_t new_val = orig_val;
5373 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5374 new_val |= IXGBE_VMOLR_AUPE;
5375 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5376 new_val |= IXGBE_VMOLR_ROMPE;
5377 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5378 new_val |= IXGBE_VMOLR_ROPE;
5379 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5380 new_val |= IXGBE_VMOLR_BAM;
5381 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5382 new_val |= IXGBE_VMOLR_MPE;
5387 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5388 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5389 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5390 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5391 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5392 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5393 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5396 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5397 struct rte_eth_mirror_conf *mirror_conf,
5398 uint8_t rule_id, uint8_t on)
5400 uint32_t mr_ctl, vlvf;
5401 uint32_t mp_lsb = 0;
5402 uint32_t mv_msb = 0;
5403 uint32_t mv_lsb = 0;
5404 uint32_t mp_msb = 0;
5407 uint64_t vlan_mask = 0;
5409 const uint8_t pool_mask_offset = 32;
5410 const uint8_t vlan_mask_offset = 32;
5411 const uint8_t dst_pool_offset = 8;
5412 const uint8_t rule_mr_offset = 4;
5413 const uint8_t mirror_rule_mask = 0x0F;
5415 struct ixgbe_mirror_info *mr_info =
5416 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5417 struct ixgbe_hw *hw =
5418 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5419 uint8_t mirror_type = 0;
5421 if (ixgbe_vt_check(hw) < 0)
5424 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5427 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5428 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5429 mirror_conf->rule_type);
5433 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5434 mirror_type |= IXGBE_MRCTL_VLME;
5435 /* Check if vlan id is valid and find conresponding VLAN ID
5438 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5439 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5440 /* search vlan id related pool vlan filter
5443 reg_index = ixgbe_find_vlvf_slot(
5445 mirror_conf->vlan.vlan_id[i],
5449 vlvf = IXGBE_READ_REG(hw,
5450 IXGBE_VLVF(reg_index));
5451 if ((vlvf & IXGBE_VLVF_VIEN) &&
5452 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5453 mirror_conf->vlan.vlan_id[i]))
5454 vlan_mask |= (1ULL << reg_index);
5461 mv_lsb = vlan_mask & 0xFFFFFFFF;
5462 mv_msb = vlan_mask >> vlan_mask_offset;
5464 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5465 mirror_conf->vlan.vlan_mask;
5466 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5467 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5468 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5469 mirror_conf->vlan.vlan_id[i];
5474 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5475 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5476 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5481 * if enable pool mirror, write related pool mask register,if disable
5482 * pool mirror, clear PFMRVM register
5484 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5485 mirror_type |= IXGBE_MRCTL_VPME;
5487 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5488 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5489 mr_info->mr_conf[rule_id].pool_mask =
5490 mirror_conf->pool_mask;
5495 mr_info->mr_conf[rule_id].pool_mask = 0;
5498 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5499 mirror_type |= IXGBE_MRCTL_UPME;
5500 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5501 mirror_type |= IXGBE_MRCTL_DPME;
5503 /* read mirror control register and recalculate it */
5504 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5507 mr_ctl |= mirror_type;
5508 mr_ctl &= mirror_rule_mask;
5509 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5511 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5514 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5515 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5517 /* write mirrror control register */
5518 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5520 /* write pool mirrror control register */
5521 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5522 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5523 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5526 /* write VLAN mirrror control register */
5527 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5528 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5529 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5537 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5540 uint32_t lsb_val = 0;
5541 uint32_t msb_val = 0;
5542 const uint8_t rule_mr_offset = 4;
5544 struct ixgbe_hw *hw =
5545 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5546 struct ixgbe_mirror_info *mr_info =
5547 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5549 if (ixgbe_vt_check(hw) < 0)
5552 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5555 memset(&mr_info->mr_conf[rule_id], 0,
5556 sizeof(struct rte_eth_mirror_conf));
5558 /* clear PFVMCTL register */
5559 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5561 /* clear pool mask register */
5562 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5563 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5565 /* clear vlan mask register */
5566 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5567 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5573 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5575 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5576 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5578 struct ixgbe_hw *hw =
5579 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5580 uint32_t vec = IXGBE_MISC_VEC_ID;
5582 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5583 if (rte_intr_allow_others(intr_handle))
5584 vec = IXGBE_RX_VEC_START;
5586 RTE_SET_USED(queue_id);
5587 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5589 rte_intr_enable(intr_handle);
5595 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5598 struct ixgbe_hw *hw =
5599 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5600 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5601 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5602 uint32_t vec = IXGBE_MISC_VEC_ID;
5604 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5605 if (rte_intr_allow_others(intr_handle))
5606 vec = IXGBE_RX_VEC_START;
5607 mask &= ~(1 << vec);
5608 RTE_SET_USED(queue_id);
5609 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5615 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5617 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5618 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5620 struct ixgbe_hw *hw =
5621 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5622 struct ixgbe_interrupt *intr =
5623 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5625 if (queue_id < 16) {
5626 ixgbe_disable_intr(hw);
5627 intr->mask |= (1 << queue_id);
5628 ixgbe_enable_intr(dev);
5629 } else if (queue_id < 32) {
5630 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5631 mask &= (1 << queue_id);
5632 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5633 } else if (queue_id < 64) {
5634 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5635 mask &= (1 << (queue_id - 32));
5636 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5638 rte_intr_enable(intr_handle);
5644 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5647 struct ixgbe_hw *hw =
5648 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5649 struct ixgbe_interrupt *intr =
5650 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5652 if (queue_id < 16) {
5653 ixgbe_disable_intr(hw);
5654 intr->mask &= ~(1 << queue_id);
5655 ixgbe_enable_intr(dev);
5656 } else if (queue_id < 32) {
5657 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5658 mask &= ~(1 << queue_id);
5659 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5660 } else if (queue_id < 64) {
5661 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5662 mask &= ~(1 << (queue_id - 32));
5663 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5670 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5671 uint8_t queue, uint8_t msix_vector)
5675 if (direction == -1) {
5677 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5678 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5681 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5683 /* rx or tx cause */
5684 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5685 idx = ((16 * (queue & 1)) + (8 * direction));
5686 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5687 tmp &= ~(0xFF << idx);
5688 tmp |= (msix_vector << idx);
5689 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5694 * set the IVAR registers, mapping interrupt causes to vectors
5696 * pointer to ixgbe_hw struct
5698 * 0 for Rx, 1 for Tx, -1 for other causes
5700 * queue to map the corresponding interrupt to
5702 * the vector to map to the corresponding queue
5705 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5706 uint8_t queue, uint8_t msix_vector)
5710 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5711 if (hw->mac.type == ixgbe_mac_82598EB) {
5712 if (direction == -1)
5714 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5715 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5716 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5717 tmp |= (msix_vector << (8 * (queue & 0x3)));
5718 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5719 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5720 (hw->mac.type == ixgbe_mac_X540) ||
5721 (hw->mac.type == ixgbe_mac_X550)) {
5722 if (direction == -1) {
5724 idx = ((queue & 1) * 8);
5725 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5726 tmp &= ~(0xFF << idx);
5727 tmp |= (msix_vector << idx);
5728 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5730 /* rx or tx causes */
5731 idx = ((16 * (queue & 1)) + (8 * direction));
5732 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5733 tmp &= ~(0xFF << idx);
5734 tmp |= (msix_vector << idx);
5735 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5741 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5743 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5744 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5745 struct ixgbe_hw *hw =
5746 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5748 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5749 uint32_t base = IXGBE_MISC_VEC_ID;
5751 /* Configure VF other cause ivar */
5752 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5754 /* won't configure msix register if no mapping is done
5755 * between intr vector and event fd.
5757 if (!rte_intr_dp_is_en(intr_handle))
5760 if (rte_intr_allow_others(intr_handle)) {
5761 base = IXGBE_RX_VEC_START;
5762 vector_idx = IXGBE_RX_VEC_START;
5765 /* Configure all RX queues of VF */
5766 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5767 /* Force all queue use vector 0,
5768 * as IXGBE_VF_MAXMSIVECOTR = 1
5770 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5771 intr_handle->intr_vec[q_idx] = vector_idx;
5772 if (vector_idx < base + intr_handle->nb_efd - 1)
5778 * Sets up the hardware to properly generate MSI-X interrupts
5780 * board private structure
5783 ixgbe_configure_msix(struct rte_eth_dev *dev)
5785 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5786 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5787 struct ixgbe_hw *hw =
5788 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5789 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5790 uint32_t vec = IXGBE_MISC_VEC_ID;
5794 /* won't configure msix register if no mapping is done
5795 * between intr vector and event fd
5797 if (!rte_intr_dp_is_en(intr_handle))
5800 if (rte_intr_allow_others(intr_handle))
5801 vec = base = IXGBE_RX_VEC_START;
5803 /* setup GPIE for MSI-x mode */
5804 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5805 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5806 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5807 /* auto clearing and auto setting corresponding bits in EIMS
5808 * when MSI-X interrupt is triggered
5810 if (hw->mac.type == ixgbe_mac_82598EB) {
5811 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5813 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5814 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5816 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5818 /* Populate the IVAR table and set the ITR values to the
5819 * corresponding register.
5821 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5823 /* by default, 1:1 mapping */
5824 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5825 intr_handle->intr_vec[queue_id] = vec;
5826 if (vec < base + intr_handle->nb_efd - 1)
5830 switch (hw->mac.type) {
5831 case ixgbe_mac_82598EB:
5832 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5835 case ixgbe_mac_82599EB:
5836 case ixgbe_mac_X540:
5837 case ixgbe_mac_X550:
5838 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5843 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5844 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5846 /* set up to autoclear timer, and the vectors */
5847 mask = IXGBE_EIMS_ENABLE_MASK;
5848 mask &= ~(IXGBE_EIMS_OTHER |
5849 IXGBE_EIMS_MAILBOX |
5852 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5856 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5857 uint16_t queue_idx, uint16_t tx_rate)
5859 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5860 uint32_t rf_dec, rf_int;
5862 uint16_t link_speed = dev->data->dev_link.link_speed;
5864 if (queue_idx >= hw->mac.max_tx_queues)
5868 /* Calculate the rate factor values to set */
5869 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5870 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5871 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5873 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5874 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5875 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5876 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5882 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5883 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5886 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5887 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5888 IXGBE_MAX_JUMBO_FRAME_SIZE))
5889 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5890 IXGBE_MMW_SIZE_JUMBO_FRAME);
5892 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5893 IXGBE_MMW_SIZE_DEFAULT);
5895 /* Set RTTBCNRC of queue X */
5896 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5897 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5898 IXGBE_WRITE_FLUSH(hw);
5904 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5905 __attribute__((unused)) uint32_t index,
5906 __attribute__((unused)) uint32_t pool)
5908 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5912 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5913 * operation. Trap this case to avoid exhausting the [very limited]
5914 * set of PF resources used to store VF MAC addresses.
5916 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5918 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5920 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5921 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5922 mac_addr->addr_bytes[0],
5923 mac_addr->addr_bytes[1],
5924 mac_addr->addr_bytes[2],
5925 mac_addr->addr_bytes[3],
5926 mac_addr->addr_bytes[4],
5927 mac_addr->addr_bytes[5],
5933 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5935 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5936 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5937 struct ether_addr *mac_addr;
5942 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5943 * not support the deletion of a given MAC address.
5944 * Instead, it imposes to delete all MAC addresses, then to add again
5945 * all MAC addresses with the exception of the one to be deleted.
5947 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5950 * Add again all MAC addresses, with the exception of the deleted one
5951 * and of the permanent MAC address.
5953 for (i = 0, mac_addr = dev->data->mac_addrs;
5954 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5955 /* Skip the deleted MAC address */
5958 /* Skip NULL MAC addresses */
5959 if (is_zero_ether_addr(mac_addr))
5961 /* Skip the permanent MAC address */
5962 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5964 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5967 "Adding again MAC address "
5968 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5970 mac_addr->addr_bytes[0],
5971 mac_addr->addr_bytes[1],
5972 mac_addr->addr_bytes[2],
5973 mac_addr->addr_bytes[3],
5974 mac_addr->addr_bytes[4],
5975 mac_addr->addr_bytes[5],
5981 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5983 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5985 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5989 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5990 struct rte_eth_syn_filter *filter,
5993 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5994 struct ixgbe_filter_info *filter_info =
5995 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5999 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6002 syn_info = filter_info->syn_info;
6005 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6007 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6008 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6010 if (filter->hig_pri)
6011 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6013 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6015 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6016 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6018 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6021 filter_info->syn_info = synqf;
6022 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6023 IXGBE_WRITE_FLUSH(hw);
6028 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6029 struct rte_eth_syn_filter *filter)
6031 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6032 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6034 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6035 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6036 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6043 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6044 enum rte_filter_op filter_op,
6047 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6050 MAC_TYPE_FILTER_SUP(hw->mac.type);
6052 if (filter_op == RTE_ETH_FILTER_NOP)
6056 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6061 switch (filter_op) {
6062 case RTE_ETH_FILTER_ADD:
6063 ret = ixgbe_syn_filter_set(dev,
6064 (struct rte_eth_syn_filter *)arg,
6067 case RTE_ETH_FILTER_DELETE:
6068 ret = ixgbe_syn_filter_set(dev,
6069 (struct rte_eth_syn_filter *)arg,
6072 case RTE_ETH_FILTER_GET:
6073 ret = ixgbe_syn_filter_get(dev,
6074 (struct rte_eth_syn_filter *)arg);
6077 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6086 static inline enum ixgbe_5tuple_protocol
6087 convert_protocol_type(uint8_t protocol_value)
6089 if (protocol_value == IPPROTO_TCP)
6090 return IXGBE_FILTER_PROTOCOL_TCP;
6091 else if (protocol_value == IPPROTO_UDP)
6092 return IXGBE_FILTER_PROTOCOL_UDP;
6093 else if (protocol_value == IPPROTO_SCTP)
6094 return IXGBE_FILTER_PROTOCOL_SCTP;
6096 return IXGBE_FILTER_PROTOCOL_NONE;
6099 /* inject a 5-tuple filter to HW */
6101 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6102 struct ixgbe_5tuple_filter *filter)
6104 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6106 uint32_t ftqf, sdpqf;
6107 uint32_t l34timir = 0;
6108 uint8_t mask = 0xff;
6112 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6113 IXGBE_SDPQF_DSTPORT_SHIFT);
6114 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6116 ftqf = (uint32_t)(filter->filter_info.proto &
6117 IXGBE_FTQF_PROTOCOL_MASK);
6118 ftqf |= (uint32_t)((filter->filter_info.priority &
6119 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6120 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6121 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6122 if (filter->filter_info.dst_ip_mask == 0)
6123 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6124 if (filter->filter_info.src_port_mask == 0)
6125 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6126 if (filter->filter_info.dst_port_mask == 0)
6127 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6128 if (filter->filter_info.proto_mask == 0)
6129 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6130 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6131 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6132 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6134 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6135 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6136 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6137 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6139 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6140 l34timir |= (uint32_t)(filter->queue <<
6141 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6142 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6146 * add a 5tuple filter
6149 * dev: Pointer to struct rte_eth_dev.
6150 * index: the index the filter allocates.
6151 * filter: ponter to the filter that will be added.
6152 * rx_queue: the queue id the filter assigned to.
6155 * - On success, zero.
6156 * - On failure, a negative value.
6159 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6160 struct ixgbe_5tuple_filter *filter)
6162 struct ixgbe_filter_info *filter_info =
6163 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6167 * look for an unused 5tuple filter index,
6168 * and insert the filter to list.
6170 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6171 idx = i / (sizeof(uint32_t) * NBBY);
6172 shift = i % (sizeof(uint32_t) * NBBY);
6173 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6174 filter_info->fivetuple_mask[idx] |= 1 << shift;
6176 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6182 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6183 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6187 ixgbe_inject_5tuple_filter(dev, filter);
6193 * remove a 5tuple filter
6196 * dev: Pointer to struct rte_eth_dev.
6197 * filter: the pointer of the filter will be removed.
6200 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6201 struct ixgbe_5tuple_filter *filter)
6203 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6204 struct ixgbe_filter_info *filter_info =
6205 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6206 uint16_t index = filter->index;
6208 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6209 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6210 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6213 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6214 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6215 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6216 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6217 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6221 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6223 struct ixgbe_hw *hw;
6224 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6225 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6227 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6229 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6232 /* refuse mtu that requires the support of scattered packets when this
6233 * feature has not been enabled before.
6235 if (!rx_conf->enable_scatter &&
6236 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6237 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6241 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6242 * request of the version 2.0 of the mailbox API.
6243 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6244 * of the mailbox API.
6245 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6246 * prior to 3.11.33 which contains the following change:
6247 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6249 ixgbevf_rlpml_set_vf(hw, max_frame);
6251 /* update max frame size */
6252 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6256 static inline struct ixgbe_5tuple_filter *
6257 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6258 struct ixgbe_5tuple_filter_info *key)
6260 struct ixgbe_5tuple_filter *it;
6262 TAILQ_FOREACH(it, filter_list, entries) {
6263 if (memcmp(key, &it->filter_info,
6264 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6271 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6273 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6274 struct ixgbe_5tuple_filter_info *filter_info)
6276 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6277 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6278 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6281 switch (filter->dst_ip_mask) {
6283 filter_info->dst_ip_mask = 0;
6284 filter_info->dst_ip = filter->dst_ip;
6287 filter_info->dst_ip_mask = 1;
6290 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6294 switch (filter->src_ip_mask) {
6296 filter_info->src_ip_mask = 0;
6297 filter_info->src_ip = filter->src_ip;
6300 filter_info->src_ip_mask = 1;
6303 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6307 switch (filter->dst_port_mask) {
6309 filter_info->dst_port_mask = 0;
6310 filter_info->dst_port = filter->dst_port;
6313 filter_info->dst_port_mask = 1;
6316 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6320 switch (filter->src_port_mask) {
6322 filter_info->src_port_mask = 0;
6323 filter_info->src_port = filter->src_port;
6326 filter_info->src_port_mask = 1;
6329 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6333 switch (filter->proto_mask) {
6335 filter_info->proto_mask = 0;
6336 filter_info->proto =
6337 convert_protocol_type(filter->proto);
6340 filter_info->proto_mask = 1;
6343 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6347 filter_info->priority = (uint8_t)filter->priority;
6352 * add or delete a ntuple filter
6355 * dev: Pointer to struct rte_eth_dev.
6356 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6357 * add: if true, add filter, if false, remove filter
6360 * - On success, zero.
6361 * - On failure, a negative value.
6364 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6365 struct rte_eth_ntuple_filter *ntuple_filter,
6368 struct ixgbe_filter_info *filter_info =
6369 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6370 struct ixgbe_5tuple_filter_info filter_5tuple;
6371 struct ixgbe_5tuple_filter *filter;
6374 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6375 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6379 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6380 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6384 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6386 if (filter != NULL && add) {
6387 PMD_DRV_LOG(ERR, "filter exists.");
6390 if (filter == NULL && !add) {
6391 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6396 filter = rte_zmalloc("ixgbe_5tuple_filter",
6397 sizeof(struct ixgbe_5tuple_filter), 0);
6400 rte_memcpy(&filter->filter_info,
6402 sizeof(struct ixgbe_5tuple_filter_info));
6403 filter->queue = ntuple_filter->queue;
6404 ret = ixgbe_add_5tuple_filter(dev, filter);
6410 ixgbe_remove_5tuple_filter(dev, filter);
6416 * get a ntuple filter
6419 * dev: Pointer to struct rte_eth_dev.
6420 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6423 * - On success, zero.
6424 * - On failure, a negative value.
6427 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6428 struct rte_eth_ntuple_filter *ntuple_filter)
6430 struct ixgbe_filter_info *filter_info =
6431 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6432 struct ixgbe_5tuple_filter_info filter_5tuple;
6433 struct ixgbe_5tuple_filter *filter;
6436 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6437 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6441 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6442 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6446 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6448 if (filter == NULL) {
6449 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6452 ntuple_filter->queue = filter->queue;
6457 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6458 * @dev: pointer to rte_eth_dev structure
6459 * @filter_op:operation will be taken.
6460 * @arg: a pointer to specific structure corresponding to the filter_op
6463 * - On success, zero.
6464 * - On failure, a negative value.
6467 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6468 enum rte_filter_op filter_op,
6471 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6474 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6476 if (filter_op == RTE_ETH_FILTER_NOP)
6480 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6485 switch (filter_op) {
6486 case RTE_ETH_FILTER_ADD:
6487 ret = ixgbe_add_del_ntuple_filter(dev,
6488 (struct rte_eth_ntuple_filter *)arg,
6491 case RTE_ETH_FILTER_DELETE:
6492 ret = ixgbe_add_del_ntuple_filter(dev,
6493 (struct rte_eth_ntuple_filter *)arg,
6496 case RTE_ETH_FILTER_GET:
6497 ret = ixgbe_get_ntuple_filter(dev,
6498 (struct rte_eth_ntuple_filter *)arg);
6501 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6509 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6510 struct rte_eth_ethertype_filter *filter,
6513 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6514 struct ixgbe_filter_info *filter_info =
6515 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6519 struct ixgbe_ethertype_filter ethertype_filter;
6521 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6524 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6525 filter->ether_type == ETHER_TYPE_IPv6) {
6526 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6527 " ethertype filter.", filter->ether_type);
6531 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6532 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6535 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6536 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6540 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6541 if (ret >= 0 && add) {
6542 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6543 filter->ether_type);
6546 if (ret < 0 && !add) {
6547 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6548 filter->ether_type);
6553 etqf = IXGBE_ETQF_FILTER_EN;
6554 etqf |= (uint32_t)filter->ether_type;
6555 etqs |= (uint32_t)((filter->queue <<
6556 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6557 IXGBE_ETQS_RX_QUEUE);
6558 etqs |= IXGBE_ETQS_QUEUE_EN;
6560 ethertype_filter.ethertype = filter->ether_type;
6561 ethertype_filter.etqf = etqf;
6562 ethertype_filter.etqs = etqs;
6563 ethertype_filter.conf = FALSE;
6564 ret = ixgbe_ethertype_filter_insert(filter_info,
6567 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6571 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6575 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6576 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6577 IXGBE_WRITE_FLUSH(hw);
6583 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6584 struct rte_eth_ethertype_filter *filter)
6586 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6587 struct ixgbe_filter_info *filter_info =
6588 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6589 uint32_t etqf, etqs;
6592 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6594 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6595 filter->ether_type);
6599 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6600 if (etqf & IXGBE_ETQF_FILTER_EN) {
6601 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6602 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6604 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6605 IXGBE_ETQS_RX_QUEUE_SHIFT;
6612 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6613 * @dev: pointer to rte_eth_dev structure
6614 * @filter_op:operation will be taken.
6615 * @arg: a pointer to specific structure corresponding to the filter_op
6618 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6619 enum rte_filter_op filter_op,
6622 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6625 MAC_TYPE_FILTER_SUP(hw->mac.type);
6627 if (filter_op == RTE_ETH_FILTER_NOP)
6631 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6636 switch (filter_op) {
6637 case RTE_ETH_FILTER_ADD:
6638 ret = ixgbe_add_del_ethertype_filter(dev,
6639 (struct rte_eth_ethertype_filter *)arg,
6642 case RTE_ETH_FILTER_DELETE:
6643 ret = ixgbe_add_del_ethertype_filter(dev,
6644 (struct rte_eth_ethertype_filter *)arg,
6647 case RTE_ETH_FILTER_GET:
6648 ret = ixgbe_get_ethertype_filter(dev,
6649 (struct rte_eth_ethertype_filter *)arg);
6652 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6660 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6661 enum rte_filter_type filter_type,
6662 enum rte_filter_op filter_op,
6667 switch (filter_type) {
6668 case RTE_ETH_FILTER_NTUPLE:
6669 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6671 case RTE_ETH_FILTER_ETHERTYPE:
6672 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6674 case RTE_ETH_FILTER_SYN:
6675 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6677 case RTE_ETH_FILTER_FDIR:
6678 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6680 case RTE_ETH_FILTER_L2_TUNNEL:
6681 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6683 case RTE_ETH_FILTER_GENERIC:
6684 if (filter_op != RTE_ETH_FILTER_GET)
6686 *(const void **)arg = &ixgbe_flow_ops;
6689 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6699 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6700 u8 **mc_addr_ptr, u32 *vmdq)
6705 mc_addr = *mc_addr_ptr;
6706 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6711 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6712 struct ether_addr *mc_addr_set,
6713 uint32_t nb_mc_addr)
6715 struct ixgbe_hw *hw;
6718 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6719 mc_addr_list = (u8 *)mc_addr_set;
6720 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6721 ixgbe_dev_addr_list_itr, TRUE);
6725 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6727 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6728 uint64_t systime_cycles;
6730 switch (hw->mac.type) {
6731 case ixgbe_mac_X550:
6732 case ixgbe_mac_X550EM_x:
6733 case ixgbe_mac_X550EM_a:
6734 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6735 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6736 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6740 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6741 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6745 return systime_cycles;
6749 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6751 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6752 uint64_t rx_tstamp_cycles;
6754 switch (hw->mac.type) {
6755 case ixgbe_mac_X550:
6756 case ixgbe_mac_X550EM_x:
6757 case ixgbe_mac_X550EM_a:
6758 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6759 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6760 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6764 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6765 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6766 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6770 return rx_tstamp_cycles;
6774 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6776 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6777 uint64_t tx_tstamp_cycles;
6779 switch (hw->mac.type) {
6780 case ixgbe_mac_X550:
6781 case ixgbe_mac_X550EM_x:
6782 case ixgbe_mac_X550EM_a:
6783 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6784 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6785 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6789 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6790 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6791 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6795 return tx_tstamp_cycles;
6799 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6801 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6802 struct ixgbe_adapter *adapter =
6803 (struct ixgbe_adapter *)dev->data->dev_private;
6804 struct rte_eth_link link;
6805 uint32_t incval = 0;
6808 /* Get current link speed. */
6809 memset(&link, 0, sizeof(link));
6810 ixgbe_dev_link_update(dev, 1);
6811 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6813 switch (link.link_speed) {
6814 case ETH_SPEED_NUM_100M:
6815 incval = IXGBE_INCVAL_100;
6816 shift = IXGBE_INCVAL_SHIFT_100;
6818 case ETH_SPEED_NUM_1G:
6819 incval = IXGBE_INCVAL_1GB;
6820 shift = IXGBE_INCVAL_SHIFT_1GB;
6822 case ETH_SPEED_NUM_10G:
6824 incval = IXGBE_INCVAL_10GB;
6825 shift = IXGBE_INCVAL_SHIFT_10GB;
6829 switch (hw->mac.type) {
6830 case ixgbe_mac_X550:
6831 case ixgbe_mac_X550EM_x:
6832 case ixgbe_mac_X550EM_a:
6833 /* Independent of link speed. */
6835 /* Cycles read will be interpreted as ns. */
6838 case ixgbe_mac_X540:
6839 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6841 case ixgbe_mac_82599EB:
6842 incval >>= IXGBE_INCVAL_SHIFT_82599;
6843 shift -= IXGBE_INCVAL_SHIFT_82599;
6844 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6845 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6848 /* Not supported. */
6852 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6853 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6854 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6856 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6857 adapter->systime_tc.cc_shift = shift;
6858 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6860 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6861 adapter->rx_tstamp_tc.cc_shift = shift;
6862 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6864 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6865 adapter->tx_tstamp_tc.cc_shift = shift;
6866 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6870 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6872 struct ixgbe_adapter *adapter =
6873 (struct ixgbe_adapter *)dev->data->dev_private;
6875 adapter->systime_tc.nsec += delta;
6876 adapter->rx_tstamp_tc.nsec += delta;
6877 adapter->tx_tstamp_tc.nsec += delta;
6883 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6886 struct ixgbe_adapter *adapter =
6887 (struct ixgbe_adapter *)dev->data->dev_private;
6889 ns = rte_timespec_to_ns(ts);
6890 /* Set the timecounters to a new value. */
6891 adapter->systime_tc.nsec = ns;
6892 adapter->rx_tstamp_tc.nsec = ns;
6893 adapter->tx_tstamp_tc.nsec = ns;
6899 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6901 uint64_t ns, systime_cycles;
6902 struct ixgbe_adapter *adapter =
6903 (struct ixgbe_adapter *)dev->data->dev_private;
6905 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6906 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6907 *ts = rte_ns_to_timespec(ns);
6913 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6915 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6919 /* Stop the timesync system time. */
6920 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6921 /* Reset the timesync system time value. */
6922 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6923 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6925 /* Enable system time for platforms where it isn't on by default. */
6926 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6927 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6928 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6930 ixgbe_start_timecounters(dev);
6932 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6933 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6935 IXGBE_ETQF_FILTER_EN |
6938 /* Enable timestamping of received PTP packets. */
6939 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6940 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6941 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6943 /* Enable timestamping of transmitted PTP packets. */
6944 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6945 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6946 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6948 IXGBE_WRITE_FLUSH(hw);
6954 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6956 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6959 /* Disable timestamping of transmitted PTP packets. */
6960 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6961 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6962 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6964 /* Disable timestamping of received PTP packets. */
6965 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6966 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6967 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6969 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6970 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6972 /* Stop incrementating the System Time registers. */
6973 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6979 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6980 struct timespec *timestamp,
6981 uint32_t flags __rte_unused)
6983 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6984 struct ixgbe_adapter *adapter =
6985 (struct ixgbe_adapter *)dev->data->dev_private;
6986 uint32_t tsync_rxctl;
6987 uint64_t rx_tstamp_cycles;
6990 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6991 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6994 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6995 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6996 *timestamp = rte_ns_to_timespec(ns);
7002 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7003 struct timespec *timestamp)
7005 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7006 struct ixgbe_adapter *adapter =
7007 (struct ixgbe_adapter *)dev->data->dev_private;
7008 uint32_t tsync_txctl;
7009 uint64_t tx_tstamp_cycles;
7012 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7013 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7016 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7017 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7018 *timestamp = rte_ns_to_timespec(ns);
7024 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7026 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7029 const struct reg_info *reg_group;
7030 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7031 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7033 while ((reg_group = reg_set[g_ind++]))
7034 count += ixgbe_regs_group_count(reg_group);
7040 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7044 const struct reg_info *reg_group;
7046 while ((reg_group = ixgbevf_regs[g_ind++]))
7047 count += ixgbe_regs_group_count(reg_group);
7053 ixgbe_get_regs(struct rte_eth_dev *dev,
7054 struct rte_dev_reg_info *regs)
7056 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7057 uint32_t *data = regs->data;
7060 const struct reg_info *reg_group;
7061 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7062 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7065 regs->length = ixgbe_get_reg_length(dev);
7066 regs->width = sizeof(uint32_t);
7070 /* Support only full register dump */
7071 if ((regs->length == 0) ||
7072 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7073 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7075 while ((reg_group = reg_set[g_ind++]))
7076 count += ixgbe_read_regs_group(dev, &data[count],
7085 ixgbevf_get_regs(struct rte_eth_dev *dev,
7086 struct rte_dev_reg_info *regs)
7088 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7089 uint32_t *data = regs->data;
7092 const struct reg_info *reg_group;
7095 regs->length = ixgbevf_get_reg_length(dev);
7096 regs->width = sizeof(uint32_t);
7100 /* Support only full register dump */
7101 if ((regs->length == 0) ||
7102 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7103 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7105 while ((reg_group = ixgbevf_regs[g_ind++]))
7106 count += ixgbe_read_regs_group(dev, &data[count],
7115 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7117 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7119 /* Return unit is byte count */
7120 return hw->eeprom.word_size * 2;
7124 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7125 struct rte_dev_eeprom_info *in_eeprom)
7127 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7128 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7129 uint16_t *data = in_eeprom->data;
7132 first = in_eeprom->offset >> 1;
7133 length = in_eeprom->length >> 1;
7134 if ((first > hw->eeprom.word_size) ||
7135 ((first + length) > hw->eeprom.word_size))
7138 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7140 return eeprom->ops.read_buffer(hw, first, length, data);
7144 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7145 struct rte_dev_eeprom_info *in_eeprom)
7147 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7148 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7149 uint16_t *data = in_eeprom->data;
7152 first = in_eeprom->offset >> 1;
7153 length = in_eeprom->length >> 1;
7154 if ((first > hw->eeprom.word_size) ||
7155 ((first + length) > hw->eeprom.word_size))
7158 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7160 return eeprom->ops.write_buffer(hw, first, length, data);
7164 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7166 case ixgbe_mac_X550:
7167 case ixgbe_mac_X550EM_x:
7168 case ixgbe_mac_X550EM_a:
7169 return ETH_RSS_RETA_SIZE_512;
7170 case ixgbe_mac_X550_vf:
7171 case ixgbe_mac_X550EM_x_vf:
7172 case ixgbe_mac_X550EM_a_vf:
7173 return ETH_RSS_RETA_SIZE_64;
7175 return ETH_RSS_RETA_SIZE_128;
7180 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7182 case ixgbe_mac_X550:
7183 case ixgbe_mac_X550EM_x:
7184 case ixgbe_mac_X550EM_a:
7185 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7186 return IXGBE_RETA(reta_idx >> 2);
7188 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7189 case ixgbe_mac_X550_vf:
7190 case ixgbe_mac_X550EM_x_vf:
7191 case ixgbe_mac_X550EM_a_vf:
7192 return IXGBE_VFRETA(reta_idx >> 2);
7194 return IXGBE_RETA(reta_idx >> 2);
7199 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7201 case ixgbe_mac_X550_vf:
7202 case ixgbe_mac_X550EM_x_vf:
7203 case ixgbe_mac_X550EM_a_vf:
7204 return IXGBE_VFMRQC;
7211 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7213 case ixgbe_mac_X550_vf:
7214 case ixgbe_mac_X550EM_x_vf:
7215 case ixgbe_mac_X550EM_a_vf:
7216 return IXGBE_VFRSSRK(i);
7218 return IXGBE_RSSRK(i);
7223 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7225 case ixgbe_mac_82599_vf:
7226 case ixgbe_mac_X540_vf:
7234 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7235 struct rte_eth_dcb_info *dcb_info)
7237 struct ixgbe_dcb_config *dcb_config =
7238 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7239 struct ixgbe_dcb_tc_config *tc;
7240 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7244 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7245 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7247 dcb_info->nb_tcs = 1;
7249 tc_queue = &dcb_info->tc_queue;
7250 nb_tcs = dcb_info->nb_tcs;
7252 if (dcb_config->vt_mode) { /* vt is enabled*/
7253 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7254 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7255 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7256 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7257 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7258 for (j = 0; j < nb_tcs; j++) {
7259 tc_queue->tc_rxq[0][j].base = j;
7260 tc_queue->tc_rxq[0][j].nb_queue = 1;
7261 tc_queue->tc_txq[0][j].base = j;
7262 tc_queue->tc_txq[0][j].nb_queue = 1;
7265 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7266 for (j = 0; j < nb_tcs; j++) {
7267 tc_queue->tc_rxq[i][j].base =
7269 tc_queue->tc_rxq[i][j].nb_queue = 1;
7270 tc_queue->tc_txq[i][j].base =
7272 tc_queue->tc_txq[i][j].nb_queue = 1;
7276 } else { /* vt is disabled*/
7277 struct rte_eth_dcb_rx_conf *rx_conf =
7278 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7279 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7280 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7281 if (dcb_info->nb_tcs == ETH_4_TCS) {
7282 for (i = 0; i < dcb_info->nb_tcs; i++) {
7283 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7284 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7286 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7287 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7288 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7289 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7290 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7291 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7292 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7293 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7294 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7295 for (i = 0; i < dcb_info->nb_tcs; i++) {
7296 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7297 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7299 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7300 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7301 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7302 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7303 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7304 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7305 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7306 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7307 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7308 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7309 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7310 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7311 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7312 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7313 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7314 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7317 for (i = 0; i < dcb_info->nb_tcs; i++) {
7318 tc = &dcb_config->tc_config[i];
7319 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7324 /* Update e-tag ether type */
7326 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7327 uint16_t ether_type)
7329 uint32_t etag_etype;
7331 if (hw->mac.type != ixgbe_mac_X550 &&
7332 hw->mac.type != ixgbe_mac_X550EM_x &&
7333 hw->mac.type != ixgbe_mac_X550EM_a) {
7337 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7338 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7339 etag_etype |= ether_type;
7340 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7341 IXGBE_WRITE_FLUSH(hw);
7346 /* Config l2 tunnel ether type */
7348 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7349 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7352 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7353 struct ixgbe_l2_tn_info *l2_tn_info =
7354 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7356 if (l2_tunnel == NULL)
7359 switch (l2_tunnel->l2_tunnel_type) {
7360 case RTE_L2_TUNNEL_TYPE_E_TAG:
7361 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7362 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7365 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7373 /* Enable e-tag tunnel */
7375 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7377 uint32_t etag_etype;
7379 if (hw->mac.type != ixgbe_mac_X550 &&
7380 hw->mac.type != ixgbe_mac_X550EM_x &&
7381 hw->mac.type != ixgbe_mac_X550EM_a) {
7385 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7386 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7387 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7388 IXGBE_WRITE_FLUSH(hw);
7393 /* Enable l2 tunnel */
7395 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7396 enum rte_eth_tunnel_type l2_tunnel_type)
7399 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7400 struct ixgbe_l2_tn_info *l2_tn_info =
7401 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7403 switch (l2_tunnel_type) {
7404 case RTE_L2_TUNNEL_TYPE_E_TAG:
7405 l2_tn_info->e_tag_en = TRUE;
7406 ret = ixgbe_e_tag_enable(hw);
7409 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7417 /* Disable e-tag tunnel */
7419 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7421 uint32_t etag_etype;
7423 if (hw->mac.type != ixgbe_mac_X550 &&
7424 hw->mac.type != ixgbe_mac_X550EM_x &&
7425 hw->mac.type != ixgbe_mac_X550EM_a) {
7429 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7430 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7431 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7432 IXGBE_WRITE_FLUSH(hw);
7437 /* Disable l2 tunnel */
7439 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7440 enum rte_eth_tunnel_type l2_tunnel_type)
7443 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7444 struct ixgbe_l2_tn_info *l2_tn_info =
7445 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7447 switch (l2_tunnel_type) {
7448 case RTE_L2_TUNNEL_TYPE_E_TAG:
7449 l2_tn_info->e_tag_en = FALSE;
7450 ret = ixgbe_e_tag_disable(hw);
7453 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7462 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7463 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7466 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7467 uint32_t i, rar_entries;
7468 uint32_t rar_low, rar_high;
7470 if (hw->mac.type != ixgbe_mac_X550 &&
7471 hw->mac.type != ixgbe_mac_X550EM_x &&
7472 hw->mac.type != ixgbe_mac_X550EM_a) {
7476 rar_entries = ixgbe_get_num_rx_addrs(hw);
7478 for (i = 1; i < rar_entries; i++) {
7479 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7480 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7481 if ((rar_high & IXGBE_RAH_AV) &&
7482 (rar_high & IXGBE_RAH_ADTYPE) &&
7483 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7484 l2_tunnel->tunnel_id)) {
7485 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7486 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7488 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7498 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7499 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7502 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7503 uint32_t i, rar_entries;
7504 uint32_t rar_low, rar_high;
7506 if (hw->mac.type != ixgbe_mac_X550 &&
7507 hw->mac.type != ixgbe_mac_X550EM_x &&
7508 hw->mac.type != ixgbe_mac_X550EM_a) {
7512 /* One entry for one tunnel. Try to remove potential existing entry. */
7513 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7515 rar_entries = ixgbe_get_num_rx_addrs(hw);
7517 for (i = 1; i < rar_entries; i++) {
7518 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7519 if (rar_high & IXGBE_RAH_AV) {
7522 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7523 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7524 rar_low = l2_tunnel->tunnel_id;
7526 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7527 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7533 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7534 " Please remove a rule before adding a new one.");
7538 static inline struct ixgbe_l2_tn_filter *
7539 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7540 struct ixgbe_l2_tn_key *key)
7544 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7548 return l2_tn_info->hash_map[ret];
7552 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7553 struct ixgbe_l2_tn_filter *l2_tn_filter)
7557 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7558 &l2_tn_filter->key);
7562 "Failed to insert L2 tunnel filter"
7563 " to hash table %d!",
7568 l2_tn_info->hash_map[ret] = l2_tn_filter;
7570 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7576 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7577 struct ixgbe_l2_tn_key *key)
7580 struct ixgbe_l2_tn_filter *l2_tn_filter;
7582 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7586 "No such L2 tunnel filter to delete %d!",
7591 l2_tn_filter = l2_tn_info->hash_map[ret];
7592 l2_tn_info->hash_map[ret] = NULL;
7594 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7595 rte_free(l2_tn_filter);
7600 /* Add l2 tunnel filter */
7602 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7603 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7607 struct ixgbe_l2_tn_info *l2_tn_info =
7608 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7609 struct ixgbe_l2_tn_key key;
7610 struct ixgbe_l2_tn_filter *node;
7613 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7614 key.tn_id = l2_tunnel->tunnel_id;
7616 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7620 "The L2 tunnel filter already exists!");
7624 node = rte_zmalloc("ixgbe_l2_tn",
7625 sizeof(struct ixgbe_l2_tn_filter),
7630 rte_memcpy(&node->key,
7632 sizeof(struct ixgbe_l2_tn_key));
7633 node->pool = l2_tunnel->pool;
7634 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7641 switch (l2_tunnel->l2_tunnel_type) {
7642 case RTE_L2_TUNNEL_TYPE_E_TAG:
7643 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7646 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7651 if ((!restore) && (ret < 0))
7652 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7657 /* Delete l2 tunnel filter */
7659 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7660 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7663 struct ixgbe_l2_tn_info *l2_tn_info =
7664 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7665 struct ixgbe_l2_tn_key key;
7667 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7668 key.tn_id = l2_tunnel->tunnel_id;
7669 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7673 switch (l2_tunnel->l2_tunnel_type) {
7674 case RTE_L2_TUNNEL_TYPE_E_TAG:
7675 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7678 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7687 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7688 * @dev: pointer to rte_eth_dev structure
7689 * @filter_op:operation will be taken.
7690 * @arg: a pointer to specific structure corresponding to the filter_op
7693 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7694 enum rte_filter_op filter_op,
7699 if (filter_op == RTE_ETH_FILTER_NOP)
7703 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7708 switch (filter_op) {
7709 case RTE_ETH_FILTER_ADD:
7710 ret = ixgbe_dev_l2_tunnel_filter_add
7712 (struct rte_eth_l2_tunnel_conf *)arg,
7715 case RTE_ETH_FILTER_DELETE:
7716 ret = ixgbe_dev_l2_tunnel_filter_del
7718 (struct rte_eth_l2_tunnel_conf *)arg);
7721 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7729 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7733 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7735 if (hw->mac.type != ixgbe_mac_X550 &&
7736 hw->mac.type != ixgbe_mac_X550EM_x &&
7737 hw->mac.type != ixgbe_mac_X550EM_a) {
7741 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7742 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7744 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7745 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7750 /* Enable l2 tunnel forwarding */
7752 ixgbe_dev_l2_tunnel_forwarding_enable
7753 (struct rte_eth_dev *dev,
7754 enum rte_eth_tunnel_type l2_tunnel_type)
7756 struct ixgbe_l2_tn_info *l2_tn_info =
7757 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7760 switch (l2_tunnel_type) {
7761 case RTE_L2_TUNNEL_TYPE_E_TAG:
7762 l2_tn_info->e_tag_fwd_en = TRUE;
7763 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7766 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7774 /* Disable l2 tunnel forwarding */
7776 ixgbe_dev_l2_tunnel_forwarding_disable
7777 (struct rte_eth_dev *dev,
7778 enum rte_eth_tunnel_type l2_tunnel_type)
7780 struct ixgbe_l2_tn_info *l2_tn_info =
7781 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7784 switch (l2_tunnel_type) {
7785 case RTE_L2_TUNNEL_TYPE_E_TAG:
7786 l2_tn_info->e_tag_fwd_en = FALSE;
7787 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7790 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7799 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7800 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7803 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7805 uint32_t vmtir, vmvir;
7806 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7808 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7810 "VF id %u should be less than %u",
7816 if (hw->mac.type != ixgbe_mac_X550 &&
7817 hw->mac.type != ixgbe_mac_X550EM_x &&
7818 hw->mac.type != ixgbe_mac_X550EM_a) {
7823 vmtir = l2_tunnel->tunnel_id;
7827 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7829 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7830 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7832 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7833 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7838 /* Enable l2 tunnel tag insertion */
7840 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7841 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7845 switch (l2_tunnel->l2_tunnel_type) {
7846 case RTE_L2_TUNNEL_TYPE_E_TAG:
7847 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7850 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7858 /* Disable l2 tunnel tag insertion */
7860 ixgbe_dev_l2_tunnel_insertion_disable
7861 (struct rte_eth_dev *dev,
7862 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7866 switch (l2_tunnel->l2_tunnel_type) {
7867 case RTE_L2_TUNNEL_TYPE_E_TAG:
7868 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7871 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7880 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7885 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7887 if (hw->mac.type != ixgbe_mac_X550 &&
7888 hw->mac.type != ixgbe_mac_X550EM_x &&
7889 hw->mac.type != ixgbe_mac_X550EM_a) {
7893 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7895 qde |= IXGBE_QDE_STRIP_TAG;
7897 qde &= ~IXGBE_QDE_STRIP_TAG;
7898 qde &= ~IXGBE_QDE_READ;
7899 qde |= IXGBE_QDE_WRITE;
7900 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7905 /* Enable l2 tunnel tag stripping */
7907 ixgbe_dev_l2_tunnel_stripping_enable
7908 (struct rte_eth_dev *dev,
7909 enum rte_eth_tunnel_type l2_tunnel_type)
7913 switch (l2_tunnel_type) {
7914 case RTE_L2_TUNNEL_TYPE_E_TAG:
7915 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7918 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7926 /* Disable l2 tunnel tag stripping */
7928 ixgbe_dev_l2_tunnel_stripping_disable
7929 (struct rte_eth_dev *dev,
7930 enum rte_eth_tunnel_type l2_tunnel_type)
7934 switch (l2_tunnel_type) {
7935 case RTE_L2_TUNNEL_TYPE_E_TAG:
7936 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7939 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7947 /* Enable/disable l2 tunnel offload functions */
7949 ixgbe_dev_l2_tunnel_offload_set
7950 (struct rte_eth_dev *dev,
7951 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7957 if (l2_tunnel == NULL)
7961 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7963 ret = ixgbe_dev_l2_tunnel_enable(
7965 l2_tunnel->l2_tunnel_type);
7967 ret = ixgbe_dev_l2_tunnel_disable(
7969 l2_tunnel->l2_tunnel_type);
7972 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7974 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7978 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7983 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7985 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7987 l2_tunnel->l2_tunnel_type);
7989 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7991 l2_tunnel->l2_tunnel_type);
7994 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7996 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7998 l2_tunnel->l2_tunnel_type);
8000 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8002 l2_tunnel->l2_tunnel_type);
8009 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8012 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8013 IXGBE_WRITE_FLUSH(hw);
8018 /* There's only one register for VxLAN UDP port.
8019 * So, we cannot add several ports. Will update it.
8022 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8026 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8030 return ixgbe_update_vxlan_port(hw, port);
8033 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8034 * UDP port, it must have a value.
8035 * So, will reset it to the original value 0.
8038 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8043 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8045 if (cur_port != port) {
8046 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8050 return ixgbe_update_vxlan_port(hw, 0);
8053 /* Add UDP tunneling port */
8055 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8056 struct rte_eth_udp_tunnel *udp_tunnel)
8059 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8061 if (hw->mac.type != ixgbe_mac_X550 &&
8062 hw->mac.type != ixgbe_mac_X550EM_x &&
8063 hw->mac.type != ixgbe_mac_X550EM_a) {
8067 if (udp_tunnel == NULL)
8070 switch (udp_tunnel->prot_type) {
8071 case RTE_TUNNEL_TYPE_VXLAN:
8072 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8075 case RTE_TUNNEL_TYPE_GENEVE:
8076 case RTE_TUNNEL_TYPE_TEREDO:
8077 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8082 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8090 /* Remove UDP tunneling port */
8092 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8093 struct rte_eth_udp_tunnel *udp_tunnel)
8096 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8098 if (hw->mac.type != ixgbe_mac_X550 &&
8099 hw->mac.type != ixgbe_mac_X550EM_x &&
8100 hw->mac.type != ixgbe_mac_X550EM_a) {
8104 if (udp_tunnel == NULL)
8107 switch (udp_tunnel->prot_type) {
8108 case RTE_TUNNEL_TYPE_VXLAN:
8109 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8111 case RTE_TUNNEL_TYPE_GENEVE:
8112 case RTE_TUNNEL_TYPE_TEREDO:
8113 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8117 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8126 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8128 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8130 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8134 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8136 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8138 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8141 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8143 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8146 /* peek the message first */
8147 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8149 /* PF reset VF event */
8150 if (in_msg == IXGBE_PF_CONTROL_MSG) {
8151 /* dummy mbx read to ack pf */
8152 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8154 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8160 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8163 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8164 struct ixgbe_interrupt *intr =
8165 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8166 ixgbevf_intr_disable(hw);
8168 /* read-on-clear nic registers here */
8169 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8172 /* only one misc vector supported - mailbox */
8173 eicr &= IXGBE_VTEICR_MASK;
8174 if (eicr == IXGBE_MISC_VEC_ID)
8175 intr->flags |= IXGBE_FLAG_MAILBOX;
8181 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8183 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8184 struct ixgbe_interrupt *intr =
8185 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8187 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8188 ixgbevf_mbx_process(dev);
8189 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8192 ixgbevf_intr_enable(hw);
8198 ixgbevf_dev_interrupt_handler(void *param)
8200 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8202 ixgbevf_dev_interrupt_get_status(dev);
8203 ixgbevf_dev_interrupt_action(dev);
8207 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8208 * @hw: pointer to hardware structure
8210 * Stops the transmit data path and waits for the HW to internally empty
8211 * the Tx security block
8213 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8215 #define IXGBE_MAX_SECTX_POLL 40
8220 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8221 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8222 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8223 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8224 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8225 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8227 /* Use interrupt-safe sleep just in case */
8231 /* For informational purposes only */
8232 if (i >= IXGBE_MAX_SECTX_POLL)
8233 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8234 "path fully disabled. Continuing with init.");
8236 return IXGBE_SUCCESS;
8240 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8241 * @hw: pointer to hardware structure
8243 * Enables the transmit data path.
8245 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8249 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8250 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8251 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8252 IXGBE_WRITE_FLUSH(hw);
8254 return IXGBE_SUCCESS;
8257 /* restore n-tuple filter */
8259 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8261 struct ixgbe_filter_info *filter_info =
8262 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8263 struct ixgbe_5tuple_filter *node;
8265 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8266 ixgbe_inject_5tuple_filter(dev, node);
8270 /* restore ethernet type filter */
8272 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8274 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8275 struct ixgbe_filter_info *filter_info =
8276 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8279 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8280 if (filter_info->ethertype_mask & (1 << i)) {
8281 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8282 filter_info->ethertype_filters[i].etqf);
8283 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8284 filter_info->ethertype_filters[i].etqs);
8285 IXGBE_WRITE_FLUSH(hw);
8290 /* restore SYN filter */
8292 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8294 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8295 struct ixgbe_filter_info *filter_info =
8296 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8299 synqf = filter_info->syn_info;
8301 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8302 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8303 IXGBE_WRITE_FLUSH(hw);
8307 /* restore L2 tunnel filter */
8309 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8311 struct ixgbe_l2_tn_info *l2_tn_info =
8312 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8313 struct ixgbe_l2_tn_filter *node;
8314 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8316 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8317 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8318 l2_tn_conf.tunnel_id = node->key.tn_id;
8319 l2_tn_conf.pool = node->pool;
8320 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8324 /* restore rss filter */
8326 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8328 struct ixgbe_filter_info *filter_info =
8329 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8331 if (filter_info->rss_info.num)
8332 ixgbe_config_rss_filter(dev,
8333 &filter_info->rss_info, TRUE);
8337 ixgbe_filter_restore(struct rte_eth_dev *dev)
8339 ixgbe_ntuple_filter_restore(dev);
8340 ixgbe_ethertype_filter_restore(dev);
8341 ixgbe_syn_filter_restore(dev);
8342 ixgbe_fdir_filter_restore(dev);
8343 ixgbe_l2_tn_filter_restore(dev);
8344 ixgbe_rss_filter_restore(dev);
8350 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8352 struct ixgbe_l2_tn_info *l2_tn_info =
8353 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8354 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8356 if (l2_tn_info->e_tag_en)
8357 (void)ixgbe_e_tag_enable(hw);
8359 if (l2_tn_info->e_tag_fwd_en)
8360 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8362 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8365 /* remove all the n-tuple filters */
8367 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8369 struct ixgbe_filter_info *filter_info =
8370 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8371 struct ixgbe_5tuple_filter *p_5tuple;
8373 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8374 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8377 /* remove all the ether type filters */
8379 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8381 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8382 struct ixgbe_filter_info *filter_info =
8383 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8386 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8387 if (filter_info->ethertype_mask & (1 << i) &&
8388 !filter_info->ethertype_filters[i].conf) {
8389 (void)ixgbe_ethertype_filter_remove(filter_info,
8391 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8392 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8393 IXGBE_WRITE_FLUSH(hw);
8398 /* remove the SYN filter */
8400 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8402 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8403 struct ixgbe_filter_info *filter_info =
8404 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8406 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8407 filter_info->syn_info = 0;
8409 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8410 IXGBE_WRITE_FLUSH(hw);
8414 /* remove all the L2 tunnel filters */
8416 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8418 struct ixgbe_l2_tn_info *l2_tn_info =
8419 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8420 struct ixgbe_l2_tn_filter *l2_tn_filter;
8421 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8424 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8425 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8426 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8427 l2_tn_conf.pool = l2_tn_filter->pool;
8428 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8436 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8437 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8438 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8439 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8440 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8441 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8443 RTE_INIT(ixgbe_init_log);
8445 ixgbe_init_log(void)
8447 ixgbe_logtype_init = rte_log_register("pmd.ixgbe.init");
8448 if (ixgbe_logtype_init >= 0)
8449 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8450 ixgbe_logtype_driver = rte_log_register("pmd.ixgbe.driver");
8451 if (ixgbe_logtype_driver >= 0)
8452 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);