drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_atomic.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_eal.h>
  27 #include <rte_alarm.h>
  28 #include <rte_ether.h>
  29 #include <rte_ethdev.h>
  30 #include <rte_ethdev_pci.h>
  31 #include <rte_malloc.h>
  32 #include <rte_random.h>
  33 #include <rte_dev.h>
  34 #include <rte_hash_crc.h>
  35 #ifdef RTE_LIBRTE_SECURITY
  36 #include <rte_security_driver.h>
  37 #endif
  38
  39 #include "ixgbe_logs.h"
  40 #include "base/ixgbe_api.h"
  41 #include "base/ixgbe_vf.h"
  42 #include "base/ixgbe_common.h"
  43 #include "ixgbe_ethdev.h"
  44 #include "ixgbe_bypass.h"
  45 #include "ixgbe_rxtx.h"
  46 #include "base/ixgbe_type.h"
  47 #include "base/ixgbe_phy.h"
  48 #include "ixgbe_regs.h"
  49
  50 /*
  51  * High threshold controlling when to start sending XOFF frames. Must be at
  52  * least 8 bytes less than receive packet buffer size. This value is in units
  53  * of 1024 bytes.
  54  */
  55 #define IXGBE_FC_HI    0x80
  56
  57 /*
  58  * Low threshold controlling when to start sending XON frames. This value is
  59  * in units of 1024 bytes.
  60  */
  61 #define IXGBE_FC_LO    0x40
  62
  63 /* Default minimum inter-interrupt interval for EITR configuration */
  64 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  65
  66 /* Timer value included in XOFF frames. */
  67 #define IXGBE_FC_PAUSE 0x680
  68
  69 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  70 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  71 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  72
  73 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  74 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  75 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  76
  77 /*
  78  *  Default values for RX/TX configuration
  79  */
  80 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  81 #define IXGBE_DEFAULT_RX_PTHRESH      8
  82 #define IXGBE_DEFAULT_RX_HTHRESH      8
  83 #define IXGBE_DEFAULT_RX_WTHRESH      0
  84
  85 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  86 #define IXGBE_DEFAULT_TX_PTHRESH      32
  87 #define IXGBE_DEFAULT_TX_HTHRESH      0
  88 #define IXGBE_DEFAULT_TX_WTHRESH      0
  89 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  90
  91 /* Bit shift and mask */
  92 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  93 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  94 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  95 #define IXGBE_8_BIT_MASK   UINT8_MAX
  96
  97 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  98
  99 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 100
 101 #define IXGBE_HKEY_MAX_INDEX 10
 102
 103 /* Additional timesync values. */
 104 #define NSEC_PER_SEC             1000000000L
 105 #define IXGBE_INCVAL_10GB        0x66666666
 106 #define IXGBE_INCVAL_1GB         0x40000000
 107 #define IXGBE_INCVAL_100         0x50000000
 108 #define IXGBE_INCVAL_SHIFT_10GB  28
 109 #define IXGBE_INCVAL_SHIFT_1GB   24
 110 #define IXGBE_INCVAL_SHIFT_100   21
 111 #define IXGBE_INCVAL_SHIFT_82599 7
 112 #define IXGBE_INCPER_SHIFT_82599 24
 113
 114 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 115
 116 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 117 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 118 #define DEFAULT_ETAG_ETYPE                     0x893f
 119 #define IXGBE_ETAG_ETYPE                       0x00005084
 120 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 121 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 122 #define IXGBE_RAH_ADTYPE                       0x40000000
 123 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 124 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 125 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 126 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 127 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 128 #define IXGBE_VTEICR_MASK                      0x07
 129
 130 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 131 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 132
 133 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 134 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 135 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 136 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 137 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 138 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 139 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 140 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 141 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 142 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 143 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 144 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 148 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 149 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 152                                 int wait_to_complete);
 153 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 154                                 struct rte_eth_stats *stats);
 155 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 156                                 struct rte_eth_xstat *xstats, unsigned n);
 157 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 158                                   struct rte_eth_xstat *xstats, unsigned n);
 159 static int
 160 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 161                 uint64_t *values, unsigned int n);
 162 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 163 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 164 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 165         struct rte_eth_xstat_name *xstats_names,
 166         unsigned int size);
 167 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 168         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 169 static int ixgbe_dev_xstats_get_names_by_id(
 170         struct rte_eth_dev *dev,
 171         struct rte_eth_xstat_name *xstats_names,
 172         const uint64_t *ids,
 173         unsigned int limit);
 174 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 175                                              uint16_t queue_id,
 176                                              uint8_t stat_idx,
 177                                              uint8_t is_rx);
 178 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 179                                  size_t fw_size);
 180 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 181                                struct rte_eth_dev_info *dev_info);
 182 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 183 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 184                                  struct rte_eth_dev_info *dev_info);
 185 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 186
 187 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 188                 uint16_t vlan_id, int on);
 189 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 190                                enum rte_vlan_type vlan_type,
 191                                uint16_t tpid_id);
 192 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 193                 uint16_t queue, bool on);
 194 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 195                 int on);
 196 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 197 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 199 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 200 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 201
 202 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 203 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 204 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 205                                struct rte_eth_fc_conf *fc_conf);
 206 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 207                                struct rte_eth_fc_conf *fc_conf);
 208 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 209                 struct rte_eth_pfc_conf *pfc_conf);
 210 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 211                         struct rte_eth_rss_reta_entry64 *reta_conf,
 212                         uint16_t reta_size);
 213 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 214                         struct rte_eth_rss_reta_entry64 *reta_conf,
 215                         uint16_t reta_size);
 216 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 217 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 218 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 221 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 222                                       struct rte_intr_handle *handle);
 223 static void ixgbe_dev_interrupt_handler(void *param);
 224 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 225 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 226                          uint32_t index, uint32_t pool);
 227 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 228 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 229                                            struct ether_addr *mac_addr);
 230 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 231 static bool is_device_supported(struct rte_eth_dev *dev,
 232                                 struct rte_pci_driver *drv);
 233
 234 /* For Virtual Function support */
 235 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 236 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 237 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 238 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 239 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 240                                    int wait_to_complete);
 241 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 242 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 243 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 244 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 245 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 246 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 247                 struct rte_eth_stats *stats);
 248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 250                 uint16_t vlan_id, int on);
 251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 252                 uint16_t queue, int on);
 253 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 254 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 255 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 256                                             uint16_t queue_id);
 257 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 258                                              uint16_t queue_id);
 259 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 260                                  uint8_t queue, uint8_t msix_vector);
 261 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 262 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 264
 265 /* For Eth VMDQ APIs support */
 266 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 267                 ether_addr * mac_addr, uint8_t on);
 268 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 269 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 270                 struct rte_eth_mirror_conf *mirror_conf,
 271                 uint8_t rule_id, uint8_t on);
 272 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 273                 uint8_t rule_id);
 274 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 275                                           uint16_t queue_id);
 276 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 277                                            uint16_t queue_id);
 278 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 279                                uint8_t queue, uint8_t msix_vector);
 280 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 281
 282 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 283                                 struct ether_addr *mac_addr,
 284                                 uint32_t index, uint32_t pool);
 285 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 286 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 287                                              struct ether_addr *mac_addr);
 288 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 289                         struct rte_eth_syn_filter *filter);
 290 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 291                         enum rte_filter_op filter_op,
 292                         void *arg);
 293 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 294                         struct ixgbe_5tuple_filter *filter);
 295 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 296                         struct ixgbe_5tuple_filter *filter);
 297 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 298                                 enum rte_filter_op filter_op,
 299                                 void *arg);
 300 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 301                         struct rte_eth_ntuple_filter *filter);
 302 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 303                                 enum rte_filter_op filter_op,
 304                                 void *arg);
 305 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 306                         struct rte_eth_ethertype_filter *filter);
 307 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 308                      enum rte_filter_type filter_type,
 309                      enum rte_filter_op filter_op,
 310                      void *arg);
 311 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 312
 313 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 314                                       struct ether_addr *mc_addr_set,
 315                                       uint32_t nb_mc_addr);
 316 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 317                                    struct rte_eth_dcb_info *dcb_info);
 318
 319 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 320 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 321                             struct rte_dev_reg_info *regs);
 322 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 323 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 324                                 struct rte_dev_eeprom_info *eeprom);
 325 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 326                                 struct rte_dev_eeprom_info *eeprom);
 327
 328 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 329 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 330                                 struct rte_dev_reg_info *regs);
 331
 332 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 333 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 334 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 335                                             struct timespec *timestamp,
 336                                             uint32_t flags);
 337 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 338                                             struct timespec *timestamp);
 339 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 340 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 341                                    struct timespec *timestamp);
 342 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 343                                    const struct timespec *timestamp);
 344 static void ixgbevf_dev_interrupt_handler(void *param);
 345
 346 static int ixgbe_dev_l2_tunnel_eth_type_conf
 347         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 348 static int ixgbe_dev_l2_tunnel_offload_set
 349         (struct rte_eth_dev *dev,
 350          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 351          uint32_t mask,
 352          uint8_t en);
 353 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 354                                              enum rte_filter_op filter_op,
 355                                              void *arg);
 356
 357 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 358                                          struct rte_eth_udp_tunnel *udp_tunnel);
 359 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 360                                          struct rte_eth_udp_tunnel *udp_tunnel);
 361 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 362 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 363
 364 /*
 365  * Define VF Stats MACRO for Non "cleared on read" register
 366  */
 367 #define UPDATE_VF_STAT(reg, last, cur)                          \
 368 {                                                               \
 369         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 370         cur += (latest - last) & UINT_MAX;                      \
 371         last = latest;                                          \
 372 }
 373
 374 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 375 {                                                                \
 376         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 377         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 378         u64 latest = ((new_msb << 32) | new_lsb);                \
 379         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 380         last = latest;                                           \
 381 }
 382
 383 #define IXGBE_SET_HWSTRIP(h, q) do {\
 384                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 385                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 386                 (h)->bitmap[idx] |= 1 << bit;\
 387         } while (0)
 388
 389 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 390                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 391                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 392                 (h)->bitmap[idx] &= ~(1 << bit);\
 393         } while (0)
 394
 395 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 396                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 397                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 398                 (r) = (h)->bitmap[idx] >> bit & 1;\
 399         } while (0)
 400
 401 /*
 402  * The set of PCI devices this driver supports
 403  */
 404 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 405         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 406         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 407         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 408         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 409         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 410         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 453 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 455 #endif
 456         { .vendor_id = 0, /* sentinel */ },
 457 };
 458
 459 /*
 460  * The set of PCI devices this driver supports (for 82599 VF)
 461  */
 462 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 473         { .vendor_id = 0, /* sentinel */ },
 474 };
 475
 476 static const struct rte_eth_desc_lim rx_desc_lim = {
 477         .nb_max = IXGBE_MAX_RING_DESC,
 478         .nb_min = IXGBE_MIN_RING_DESC,
 479         .nb_align = IXGBE_RXD_ALIGN,
 480 };
 481
 482 static const struct rte_eth_desc_lim tx_desc_lim = {
 483         .nb_max = IXGBE_MAX_RING_DESC,
 484         .nb_min = IXGBE_MIN_RING_DESC,
 485         .nb_align = IXGBE_TXD_ALIGN,
 486         .nb_seg_max = IXGBE_TX_MAX_SEG,
 487         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 488 };
 489
 490 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 491         .dev_configure        = ixgbe_dev_configure,
 492         .dev_start            = ixgbe_dev_start,
 493         .dev_stop             = ixgbe_dev_stop,
 494         .dev_set_link_up    = ixgbe_dev_set_link_up,
 495         .dev_set_link_down  = ixgbe_dev_set_link_down,
 496         .dev_close            = ixgbe_dev_close,
 497         .dev_reset            = ixgbe_dev_reset,
 498         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 499         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 500         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 501         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 502         .link_update          = ixgbe_dev_link_update,
 503         .stats_get            = ixgbe_dev_stats_get,
 504         .xstats_get           = ixgbe_dev_xstats_get,
 505         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 506         .stats_reset          = ixgbe_dev_stats_reset,
 507         .xstats_reset         = ixgbe_dev_xstats_reset,
 508         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 509         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 510         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 511         .fw_version_get       = ixgbe_fw_version_get,
 512         .dev_infos_get        = ixgbe_dev_info_get,
 513         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 514         .mtu_set              = ixgbe_dev_mtu_set,
 515         .vlan_filter_set      = ixgbe_vlan_filter_set,
 516         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 517         .vlan_offload_set     = ixgbe_vlan_offload_set,
 518         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 519         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 520         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 521         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 522         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 523         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 524         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 525         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 526         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 527         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 528         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 529         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 530         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 531         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 532         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 533         .dev_led_on           = ixgbe_dev_led_on,
 534         .dev_led_off          = ixgbe_dev_led_off,
 535         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 536         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 537         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 538         .mac_addr_add         = ixgbe_add_rar,
 539         .mac_addr_remove      = ixgbe_remove_rar,
 540         .mac_addr_set         = ixgbe_set_default_mac_addr,
 541         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 542         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 543         .mirror_rule_set      = ixgbe_mirror_rule_set,
 544         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 545         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 546         .reta_update          = ixgbe_dev_rss_reta_update,
 547         .reta_query           = ixgbe_dev_rss_reta_query,
 548         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 549         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 550         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 551         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 552         .rxq_info_get         = ixgbe_rxq_info_get,
 553         .txq_info_get         = ixgbe_txq_info_get,
 554         .timesync_enable      = ixgbe_timesync_enable,
 555         .timesync_disable     = ixgbe_timesync_disable,
 556         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 557         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 558         .get_reg              = ixgbe_get_regs,
 559         .get_eeprom_length    = ixgbe_get_eeprom_length,
 560         .get_eeprom           = ixgbe_get_eeprom,
 561         .set_eeprom           = ixgbe_set_eeprom,
 562         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 563         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 564         .timesync_read_time   = ixgbe_timesync_read_time,
 565         .timesync_write_time  = ixgbe_timesync_write_time,
 566         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 567         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 568         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 569         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 570         .tm_ops_get           = ixgbe_tm_ops_get,
 571 };
 572
 573 /*
 574  * dev_ops for virtual function, bare necessities for basic vf
 575  * operation have been implemented
 576  */
 577 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 578         .dev_configure        = ixgbevf_dev_configure,
 579         .dev_start            = ixgbevf_dev_start,
 580         .dev_stop             = ixgbevf_dev_stop,
 581         .link_update          = ixgbevf_dev_link_update,
 582         .stats_get            = ixgbevf_dev_stats_get,
 583         .xstats_get           = ixgbevf_dev_xstats_get,
 584         .stats_reset          = ixgbevf_dev_stats_reset,
 585         .xstats_reset         = ixgbevf_dev_stats_reset,
 586         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 587         .dev_close            = ixgbevf_dev_close,
 588         .dev_reset            = ixgbevf_dev_reset,
 589         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 590         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 591         .dev_infos_get        = ixgbevf_dev_info_get,
 592         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 593         .mtu_set              = ixgbevf_dev_set_mtu,
 594         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 595         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 596         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 597         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 598         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 599         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 600         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 601         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 602         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 603         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 604         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 605         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 606         .mac_addr_add         = ixgbevf_add_mac_addr,
 607         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 608         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 609         .rxq_info_get         = ixgbe_rxq_info_get,
 610         .txq_info_get         = ixgbe_txq_info_get,
 611         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 612         .get_reg              = ixgbevf_get_regs,
 613         .reta_update          = ixgbe_dev_rss_reta_update,
 614         .reta_query           = ixgbe_dev_rss_reta_query,
 615         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 616         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 617 };
 618
 619 /* store statistics names and its offset in stats structure */
 620 struct rte_ixgbe_xstats_name_off {
 621         char name[RTE_ETH_XSTATS_NAME_SIZE];
 622         unsigned offset;
 623 };
 624
 625 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 626         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 627         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 628         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 629         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 630         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 631         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 632         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 633         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 634         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 635         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 636         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 637         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 638         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 639         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 640         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 641                 prc1023)},
 642         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 643                 prc1522)},
 644         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 645         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 646         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 647         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 648         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 649         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 650         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 651         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 652         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 653         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 654         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 655         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 656         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 657         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 658         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 659         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 660         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 661                 ptc1023)},
 662         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 663                 ptc1522)},
 664         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 665         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 666         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 667         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 668
 669         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 670                 fdirustat_add)},
 671         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 672                 fdirustat_remove)},
 673         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 674                 fdirfstat_fadd)},
 675         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 676                 fdirfstat_fremove)},
 677         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 678                 fdirmatch)},
 679         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 680                 fdirmiss)},
 681
 682         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 683         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 684         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 685                 fclast)},
 686         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 687         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 688         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 689         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 690         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 691                 fcoe_noddp)},
 692         {"rx_fcoe_no_direct_data_placement_ext_buff",
 693                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 694
 695         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 696                 lxontxc)},
 697         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 698                 lxonrxc)},
 699         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 700                 lxofftxc)},
 701         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 702                 lxoffrxc)},
 703         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 704 };
 705
 706 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 707                            sizeof(rte_ixgbe_stats_strings[0]))
 708
 709 /* MACsec statistics */
 710 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 711         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 712                 out_pkts_untagged)},
 713         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 714                 out_pkts_encrypted)},
 715         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 716                 out_pkts_protected)},
 717         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 718                 out_octets_encrypted)},
 719         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 720                 out_octets_protected)},
 721         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 722                 in_pkts_untagged)},
 723         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 724                 in_pkts_badtag)},
 725         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 726                 in_pkts_nosci)},
 727         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 728                 in_pkts_unknownsci)},
 729         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 730                 in_octets_decrypted)},
 731         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 732                 in_octets_validated)},
 733         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 734                 in_pkts_unchecked)},
 735         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 736                 in_pkts_delayed)},
 737         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 738                 in_pkts_late)},
 739         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 740                 in_pkts_ok)},
 741         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 742                 in_pkts_invalid)},
 743         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 744                 in_pkts_notvalid)},
 745         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 746                 in_pkts_unusedsa)},
 747         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_notusingsa)},
 749 };
 750
 751 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 752                            sizeof(rte_ixgbe_macsec_strings[0]))
 753
 754 /* Per-queue statistics */
 755 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 756         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 757         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 758         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 759         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 760 };
 761
 762 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 763                            sizeof(rte_ixgbe_rxq_strings[0]))
 764 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 765
 766 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 767         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 768         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 769         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 770                 pxon2offc)},
 771 };
 772
 773 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 774                            sizeof(rte_ixgbe_txq_strings[0]))
 775 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 776
 777 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 778         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 779 };
 780
 781 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 782                 sizeof(rte_ixgbevf_stats_strings[0]))
 783
 784 /**
 785  * Atomically reads the link status information from global
 786  * structure rte_eth_dev.
 787  *
 788  * @param dev
 789  *   - Pointer to the structure rte_eth_dev to read from.
 790  *   - Pointer to the buffer to be saved with the link status.
 791  *
 792  * @return
 793  *   - On success, zero.
 794  *   - On failure, negative value.
 795  */
 796 static inline int
 797 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 798                                 struct rte_eth_link *link)
 799 {
 800         struct rte_eth_link *dst = link;
 801         struct rte_eth_link *src = &(dev->data->dev_link);
 802
 803         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 804                                         *(uint64_t *)src) == 0)
 805                 return -1;
 806
 807         return 0;
 808 }
 809
 810 /**
 811  * Atomically writes the link status information into global
 812  * structure rte_eth_dev.
 813  *
 814  * @param dev
 815  *   - Pointer to the structure rte_eth_dev to read from.
 816  *   - Pointer to the buffer to be saved with the link status.
 817  *
 818  * @return
 819  *   - On success, zero.
 820  *   - On failure, negative value.
 821  */
 822 static inline int
 823 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 824                                 struct rte_eth_link *link)
 825 {
 826         struct rte_eth_link *dst = &(dev->data->dev_link);
 827         struct rte_eth_link *src = link;
 828
 829         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 830                                         *(uint64_t *)src) == 0)
 831                 return -1;
 832
 833         return 0;
 834 }
 835
 836 /*
 837  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 838  */
 839 static inline int
 840 ixgbe_is_sfp(struct ixgbe_hw *hw)
 841 {
 842         switch (hw->phy.type) {
 843         case ixgbe_phy_sfp_avago:
 844         case ixgbe_phy_sfp_ftl:
 845         case ixgbe_phy_sfp_intel:
 846         case ixgbe_phy_sfp_unknown:
 847         case ixgbe_phy_sfp_passive_tyco:
 848         case ixgbe_phy_sfp_passive_unknown:
 849                 return 1;
 850         default:
 851                 return 0;
 852         }
 853 }
 854
 855 static inline int32_t
 856 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 857 {
 858         uint32_t ctrl_ext;
 859         int32_t status;
 860
 861         status = ixgbe_reset_hw(hw);
 862
 863         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 864         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 865         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 866         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 867         IXGBE_WRITE_FLUSH(hw);
 868
 869         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 870                 status = IXGBE_SUCCESS;
 871         return status;
 872 }
 873
 874 static inline void
 875 ixgbe_enable_intr(struct rte_eth_dev *dev)
 876 {
 877         struct ixgbe_interrupt *intr =
 878                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 879         struct ixgbe_hw *hw =
 880                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 881
 882         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 883         IXGBE_WRITE_FLUSH(hw);
 884 }
 885
 886 /*
 887  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 888  */
 889 static void
 890 ixgbe_disable_intr(struct ixgbe_hw *hw)
 891 {
 892         PMD_INIT_FUNC_TRACE();
 893
 894         if (hw->mac.type == ixgbe_mac_82598EB) {
 895                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 896         } else {
 897                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 898                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 899                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 900         }
 901         IXGBE_WRITE_FLUSH(hw);
 902 }
 903
 904 /*
 905  * This function resets queue statistics mapping registers.
 906  * From Niantic datasheet, Initialization of Statistics section:
 907  * "...if software requires the queue counters, the RQSMR and TQSM registers
 908  * must be re-programmed following a device reset.
 909  */
 910 static void
 911 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 912 {
 913         uint32_t i;
 914
 915         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 916                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 917                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 918         }
 919 }
 920
 921
 922 static int
 923 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 924                                   uint16_t queue_id,
 925                                   uint8_t stat_idx,
 926                                   uint8_t is_rx)
 927 {
 928 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 929 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 930 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 931
 932         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 933         struct ixgbe_stat_mapping_registers *stat_mappings =
 934                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 935         uint32_t qsmr_mask = 0;
 936         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 937         uint32_t q_map;
 938         uint8_t n, offset;
 939
 940         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 941                 (hw->mac.type != ixgbe_mac_X540) &&
 942                 (hw->mac.type != ixgbe_mac_X550) &&
 943                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 944                 (hw->mac.type != ixgbe_mac_X550EM_a))
 945                 return -ENOSYS;
 946
 947         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 948                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 949                      queue_id, stat_idx);
 950
 951         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 952         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 953                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 954                 return -EIO;
 955         }
 956         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 957
 958         /* Now clear any previous stat_idx set */
 959         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 960         if (!is_rx)
 961                 stat_mappings->tqsm[n] &= ~clearing_mask;
 962         else
 963                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 964
 965         q_map = (uint32_t)stat_idx;
 966         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 967         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 968         if (!is_rx)
 969                 stat_mappings->tqsm[n] |= qsmr_mask;
 970         else
 971                 stat_mappings->rqsmr[n] |= qsmr_mask;
 972
 973         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 974                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 975                      queue_id, stat_idx);
 976         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 977                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 978
 979         /* Now write the mapping in the appropriate register */
 980         if (is_rx) {
 981                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 982                              stat_mappings->rqsmr[n], n);
 983                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 984         } else {
 985                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 986                              stat_mappings->tqsm[n], n);
 987                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 988         }
 989         return 0;
 990 }
 991
 992 static void
 993 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 994 {
 995         struct ixgbe_stat_mapping_registers *stat_mappings =
 996                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 997         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 998         int i;
 999
1000         /* write whatever was in stat mapping table to the NIC */
1001         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1002                 /* rx */
1003                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1004
1005                 /* tx */
1006                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1007         }
1008 }
1009
1010 static void
1011 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1012 {
1013         uint8_t i;
1014         struct ixgbe_dcb_tc_config *tc;
1015         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1016
1017         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1018         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1019         for (i = 0; i < dcb_max_tc; i++) {
1020                 tc = &dcb_config->tc_config[i];
1021                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1022                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1023                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1024                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1025                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1026                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1027                 tc->pfc = ixgbe_dcb_pfc_disabled;
1028         }
1029
1030         /* Initialize default user to priority mapping, UPx->TC0 */
1031         tc = &dcb_config->tc_config[0];
1032         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1033         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1034         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1035                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1036                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1037         }
1038         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1039         dcb_config->pfc_mode_enable = false;
1040         dcb_config->vt_mode = true;
1041         dcb_config->round_robin_enable = false;
1042         /* support all DCB capabilities in 82599 */
1043         dcb_config->support.capabilities = 0xFF;
1044
1045         /*we only support 4 Tcs for X540, X550 */
1046         if (hw->mac.type == ixgbe_mac_X540 ||
1047                 hw->mac.type == ixgbe_mac_X550 ||
1048                 hw->mac.type == ixgbe_mac_X550EM_x ||
1049                 hw->mac.type == ixgbe_mac_X550EM_a) {
1050                 dcb_config->num_tcs.pg_tcs = 4;
1051                 dcb_config->num_tcs.pfc_tcs = 4;
1052         }
1053 }
1054
1055 /*
1056  * Ensure that all locks are released before first NVM or PHY access
1057  */
1058 static void
1059 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1060 {
1061         uint16_t mask;
1062
1063         /*
1064          * Phy lock should not fail in this early stage. If this is the case,
1065          * it is due to an improper exit of the application.
1066          * So force the release of the faulty lock. Release of common lock
1067          * is done automatically by swfw_sync function.
1068          */
1069         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1070         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1071                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1072         }
1073         ixgbe_release_swfw_semaphore(hw, mask);
1074
1075         /*
1076          * These ones are more tricky since they are common to all ports; but
1077          * swfw_sync retries last long enough (1s) to be almost sure that if
1078          * lock can not be taken it is due to an improper lock of the
1079          * semaphore.
1080          */
1081         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1082         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1083                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1084         }
1085         ixgbe_release_swfw_semaphore(hw, mask);
1086 }
1087
1088 /*
1089  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1090  * It returns 0 on success.
1091  */
1092 static int
1093 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1094 {
1095         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1096         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1097         struct ixgbe_hw *hw =
1098                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1099         struct ixgbe_vfta *shadow_vfta =
1100                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1101         struct ixgbe_hwstrip *hwstrip =
1102                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1103         struct ixgbe_dcb_config *dcb_config =
1104                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1105         struct ixgbe_filter_info *filter_info =
1106                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1107         struct ixgbe_bw_conf *bw_conf =
1108                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1109         uint32_t ctrl_ext;
1110         uint16_t csum;
1111         int diag, i;
1112
1113         PMD_INIT_FUNC_TRACE();
1114
1115         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1116         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1117         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1118         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1119
1120         /*
1121          * For secondary processes, we don't initialise any further as primary
1122          * has already done this work. Only check we don't need a different
1123          * RX and TX function.
1124          */
1125         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1126                 struct ixgbe_tx_queue *txq;
1127                 /* TX queue function in primary, set by last queue initialized
1128                  * Tx queue may not initialized by primary process
1129                  */
1130                 if (eth_dev->data->tx_queues) {
1131                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1132                         ixgbe_set_tx_function(eth_dev, txq);
1133                 } else {
1134                         /* Use default TX function if we get here */
1135                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1136                                      "Using default TX function.");
1137                 }
1138
1139                 ixgbe_set_rx_function(eth_dev);
1140
1141                 return 0;
1142         }
1143
1144 #ifdef RTE_LIBRTE_SECURITY
1145         /* Initialize security_ctx only for primary process*/
1146         eth_dev->security_ctx = ixgbe_ipsec_ctx_create(eth_dev);
1147         if (eth_dev->security_ctx == NULL)
1148                 return -ENOMEM;
1149 #endif
1150
1151         rte_eth_copy_pci_info(eth_dev, pci_dev);
1152
1153         /* Vendor and Device ID need to be set before init of shared code */
1154         hw->device_id = pci_dev->id.device_id;
1155         hw->vendor_id = pci_dev->id.vendor_id;
1156         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1157         hw->allow_unsupported_sfp = 1;
1158
1159         /* Initialize the shared code (base driver) */
1160 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1161         diag = ixgbe_bypass_init_shared_code(hw);
1162 #else
1163         diag = ixgbe_init_shared_code(hw);
1164 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1165
1166         if (diag != IXGBE_SUCCESS) {
1167                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1168                 return -EIO;
1169         }
1170
1171         /* pick up the PCI bus settings for reporting later */
1172         ixgbe_get_bus_info(hw);
1173
1174         /* Unlock any pending hardware semaphore */
1175         ixgbe_swfw_lock_reset(hw);
1176
1177         /* Initialize DCB configuration*/
1178         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1179         ixgbe_dcb_init(hw, dcb_config);
1180         /* Get Hardware Flow Control setting */
1181         hw->fc.requested_mode = ixgbe_fc_full;
1182         hw->fc.current_mode = ixgbe_fc_full;
1183         hw->fc.pause_time = IXGBE_FC_PAUSE;
1184         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1185                 hw->fc.low_water[i] = IXGBE_FC_LO;
1186                 hw->fc.high_water[i] = IXGBE_FC_HI;
1187         }
1188         hw->fc.send_xon = 1;
1189
1190         /* Make sure we have a good EEPROM before we read from it */
1191         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1192         if (diag != IXGBE_SUCCESS) {
1193                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1194                 return -EIO;
1195         }
1196
1197 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1198         diag = ixgbe_bypass_init_hw(hw);
1199 #else
1200         diag = ixgbe_init_hw(hw);
1201 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1202
1203         /*
1204          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1205          * is called too soon after the kernel driver unbinding/binding occurs.
1206          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1207          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1208          * also called. See ixgbe_identify_phy_82599(). The reason for the
1209          * failure is not known, and only occuts when virtualisation features
1210          * are disabled in the bios. A delay of 100ms  was found to be enough by
1211          * trial-and-error, and is doubled to be safe.
1212          */
1213         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1214                 rte_delay_ms(200);
1215                 diag = ixgbe_init_hw(hw);
1216         }
1217
1218         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1219                 diag = IXGBE_SUCCESS;
1220
1221         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1222                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1223                              "LOM.  Please be aware there may be issues associated "
1224                              "with your hardware.");
1225                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1226                              "please contact your Intel or hardware representative "
1227                              "who provided you with this hardware.");
1228         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1229                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1230         if (diag) {
1231                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1232                 return -EIO;
1233         }
1234
1235         /* Reset the hw statistics */
1236         ixgbe_dev_stats_reset(eth_dev);
1237
1238         /* disable interrupt */
1239         ixgbe_disable_intr(hw);
1240
1241         /* reset mappings for queue statistics hw counters*/
1242         ixgbe_reset_qstat_mappings(hw);
1243
1244         /* Allocate memory for storing MAC addresses */
1245         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1246                                                hw->mac.num_rar_entries, 0);
1247         if (eth_dev->data->mac_addrs == NULL) {
1248                 PMD_INIT_LOG(ERR,
1249                              "Failed to allocate %u bytes needed to store "
1250                              "MAC addresses",
1251                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1252                 return -ENOMEM;
1253         }
1254         /* Copy the permanent MAC address */
1255         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1256                         &eth_dev->data->mac_addrs[0]);
1257
1258         /* Allocate memory for storing hash filter MAC addresses */
1259         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1260                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1261         if (eth_dev->data->hash_mac_addrs == NULL) {
1262                 PMD_INIT_LOG(ERR,
1263                              "Failed to allocate %d bytes needed to store MAC addresses",
1264                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1265                 return -ENOMEM;
1266         }
1267
1268         /* initialize the vfta */
1269         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1270
1271         /* initialize the hw strip bitmap*/
1272         memset(hwstrip, 0, sizeof(*hwstrip));
1273
1274         /* initialize PF if max_vfs not zero */
1275         ixgbe_pf_host_init(eth_dev);
1276
1277         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1278         /* let hardware know driver is loaded */
1279         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1280         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1281         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1282         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1283         IXGBE_WRITE_FLUSH(hw);
1284
1285         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1286                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1287                              (int) hw->mac.type, (int) hw->phy.type,
1288                              (int) hw->phy.sfp_type);
1289         else
1290                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1291                              (int) hw->mac.type, (int) hw->phy.type);
1292
1293         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1294                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1295                      pci_dev->id.device_id);
1296
1297         rte_intr_callback_register(intr_handle,
1298                                    ixgbe_dev_interrupt_handler, eth_dev);
1299
1300         /* enable uio/vfio intr/eventfd mapping */
1301         rte_intr_enable(intr_handle);
1302
1303         /* enable support intr */
1304         ixgbe_enable_intr(eth_dev);
1305
1306         /* initialize filter info */
1307         memset(filter_info, 0,
1308                sizeof(struct ixgbe_filter_info));
1309
1310         /* initialize 5tuple filter list */
1311         TAILQ_INIT(&filter_info->fivetuple_list);
1312
1313         /* initialize flow director filter list & hash */
1314         ixgbe_fdir_filter_init(eth_dev);
1315
1316         /* initialize l2 tunnel filter list & hash */
1317         ixgbe_l2_tn_filter_init(eth_dev);
1318
1319         /* initialize flow filter lists */
1320         ixgbe_filterlist_init();
1321
1322         /* initialize bandwidth configuration info */
1323         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1324
1325         /* initialize Traffic Manager configuration */
1326         ixgbe_tm_conf_init(eth_dev);
1327
1328         return 0;
1329 }
1330
1331 static int
1332 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1333 {
1334         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1335         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1336         struct ixgbe_hw *hw;
1337
1338         PMD_INIT_FUNC_TRACE();
1339
1340         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1341                 return -EPERM;
1342
1343         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1344
1345         if (hw->adapter_stopped == 0)
1346                 ixgbe_dev_close(eth_dev);
1347
1348         eth_dev->dev_ops = NULL;
1349         eth_dev->rx_pkt_burst = NULL;
1350         eth_dev->tx_pkt_burst = NULL;
1351
1352         /* Unlock any pending hardware semaphore */
1353         ixgbe_swfw_lock_reset(hw);
1354
1355         /* disable uio intr before callback unregister */
1356         rte_intr_disable(intr_handle);
1357         rte_intr_callback_unregister(intr_handle,
1358                                      ixgbe_dev_interrupt_handler, eth_dev);
1359
1360         /* uninitialize PF if max_vfs not zero */
1361         ixgbe_pf_host_uninit(eth_dev);
1362
1363         rte_free(eth_dev->data->mac_addrs);
1364         eth_dev->data->mac_addrs = NULL;
1365
1366         rte_free(eth_dev->data->hash_mac_addrs);
1367         eth_dev->data->hash_mac_addrs = NULL;
1368
1369         /* remove all the fdir filters & hash */
1370         ixgbe_fdir_filter_uninit(eth_dev);
1371
1372         /* remove all the L2 tunnel filters & hash */
1373         ixgbe_l2_tn_filter_uninit(eth_dev);
1374
1375         /* Remove all ntuple filters of the device */
1376         ixgbe_ntuple_filter_uninit(eth_dev);
1377
1378         /* clear all the filters list */
1379         ixgbe_filterlist_flush();
1380
1381         /* Remove all Traffic Manager configuration */
1382         ixgbe_tm_conf_uninit(eth_dev);
1383
1384 #ifdef RTE_LIBRTE_SECURITY
1385         rte_free(eth_dev->security_ctx);
1386 #endif
1387
1388         return 0;
1389 }
1390
1391 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1392 {
1393         struct ixgbe_filter_info *filter_info =
1394                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1395         struct ixgbe_5tuple_filter *p_5tuple;
1396
1397         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1398                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1399                              p_5tuple,
1400                              entries);
1401                 rte_free(p_5tuple);
1402         }
1403         memset(filter_info->fivetuple_mask, 0,
1404                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1405
1406         return 0;
1407 }
1408
1409 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1410 {
1411         struct ixgbe_hw_fdir_info *fdir_info =
1412                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1413         struct ixgbe_fdir_filter *fdir_filter;
1414
1415                 if (fdir_info->hash_map)
1416                 rte_free(fdir_info->hash_map);
1417         if (fdir_info->hash_handle)
1418                 rte_hash_free(fdir_info->hash_handle);
1419
1420         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1421                 TAILQ_REMOVE(&fdir_info->fdir_list,
1422                              fdir_filter,
1423                              entries);
1424                 rte_free(fdir_filter);
1425         }
1426
1427         return 0;
1428 }
1429
1430 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1431 {
1432         struct ixgbe_l2_tn_info *l2_tn_info =
1433                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1434         struct ixgbe_l2_tn_filter *l2_tn_filter;
1435
1436         if (l2_tn_info->hash_map)
1437                 rte_free(l2_tn_info->hash_map);
1438         if (l2_tn_info->hash_handle)
1439                 rte_hash_free(l2_tn_info->hash_handle);
1440
1441         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1442                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1443                              l2_tn_filter,
1444                              entries);
1445                 rte_free(l2_tn_filter);
1446         }
1447
1448         return 0;
1449 }
1450
1451 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1452 {
1453         struct ixgbe_hw_fdir_info *fdir_info =
1454                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1455         char fdir_hash_name[RTE_HASH_NAMESIZE];
1456         struct rte_hash_parameters fdir_hash_params = {
1457                 .name = fdir_hash_name,
1458                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1459                 .key_len = sizeof(union ixgbe_atr_input),
1460                 .hash_func = rte_hash_crc,
1461                 .hash_func_init_val = 0,
1462                 .socket_id = rte_socket_id(),
1463         };
1464
1465         TAILQ_INIT(&fdir_info->fdir_list);
1466         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1467                  "fdir_%s", eth_dev->device->name);
1468         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1469         if (!fdir_info->hash_handle) {
1470                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1471                 return -EINVAL;
1472         }
1473         fdir_info->hash_map = rte_zmalloc("ixgbe",
1474                                           sizeof(struct ixgbe_fdir_filter *) *
1475                                           IXGBE_MAX_FDIR_FILTER_NUM,
1476                                           0);
1477         if (!fdir_info->hash_map) {
1478                 PMD_INIT_LOG(ERR,
1479                              "Failed to allocate memory for fdir hash map!");
1480                 return -ENOMEM;
1481         }
1482         fdir_info->mask_added = FALSE;
1483
1484         return 0;
1485 }
1486
1487 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1488 {
1489         struct ixgbe_l2_tn_info *l2_tn_info =
1490                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1491         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1492         struct rte_hash_parameters l2_tn_hash_params = {
1493                 .name = l2_tn_hash_name,
1494                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1495                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1496                 .hash_func = rte_hash_crc,
1497                 .hash_func_init_val = 0,
1498                 .socket_id = rte_socket_id(),
1499         };
1500
1501         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1502         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1503                  "l2_tn_%s", eth_dev->device->name);
1504         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1505         if (!l2_tn_info->hash_handle) {
1506                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1507                 return -EINVAL;
1508         }
1509         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1510                                    sizeof(struct ixgbe_l2_tn_filter *) *
1511                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1512                                    0);
1513         if (!l2_tn_info->hash_map) {
1514                 PMD_INIT_LOG(ERR,
1515                         "Failed to allocate memory for L2 TN hash map!");
1516                 return -ENOMEM;
1517         }
1518         l2_tn_info->e_tag_en = FALSE;
1519         l2_tn_info->e_tag_fwd_en = FALSE;
1520         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1521
1522         return 0;
1523 }
1524 /*
1525  * Negotiate mailbox API version with the PF.
1526  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1527  * Then we try to negotiate starting with the most recent one.
1528  * If all negotiation attempts fail, then we will proceed with
1529  * the default one (ixgbe_mbox_api_10).
1530  */
1531 static void
1532 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1533 {
1534         int32_t i;
1535
1536         /* start with highest supported, proceed down */
1537         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1538                 ixgbe_mbox_api_12,
1539                 ixgbe_mbox_api_11,
1540                 ixgbe_mbox_api_10,
1541         };
1542
1543         for (i = 0;
1544                         i != RTE_DIM(sup_ver) &&
1545                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1546                         i++)
1547                 ;
1548 }
1549
1550 static void
1551 generate_random_mac_addr(struct ether_addr *mac_addr)
1552 {
1553         uint64_t random;
1554
1555         /* Set Organizationally Unique Identifier (OUI) prefix. */
1556         mac_addr->addr_bytes[0] = 0x00;
1557         mac_addr->addr_bytes[1] = 0x09;
1558         mac_addr->addr_bytes[2] = 0xC0;
1559         /* Force indication of locally assigned MAC address. */
1560         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1561         /* Generate the last 3 bytes of the MAC address with a random number. */
1562         random = rte_rand();
1563         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1564 }
1565
1566 /*
1567  * Virtual Function device init
1568  */
1569 static int
1570 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1571 {
1572         int diag;
1573         uint32_t tc, tcs;
1574         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1575         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1576         struct ixgbe_hw *hw =
1577                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1578         struct ixgbe_vfta *shadow_vfta =
1579                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1580         struct ixgbe_hwstrip *hwstrip =
1581                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1582         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1583
1584         PMD_INIT_FUNC_TRACE();
1585
1586         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1587         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1588         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1589
1590         /* for secondary processes, we don't initialise any further as primary
1591          * has already done this work. Only check we don't need a different
1592          * RX function
1593          */
1594         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1595                 struct ixgbe_tx_queue *txq;
1596                 /* TX queue function in primary, set by last queue initialized
1597                  * Tx queue may not initialized by primary process
1598                  */
1599                 if (eth_dev->data->tx_queues) {
1600                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1601                         ixgbe_set_tx_function(eth_dev, txq);
1602                 } else {
1603                         /* Use default TX function if we get here */
1604                         PMD_INIT_LOG(NOTICE,
1605                                      "No TX queues configured yet. Using default TX function.");
1606                 }
1607
1608                 ixgbe_set_rx_function(eth_dev);
1609
1610                 return 0;
1611         }
1612
1613         rte_eth_copy_pci_info(eth_dev, pci_dev);
1614
1615         hw->device_id = pci_dev->id.device_id;
1616         hw->vendor_id = pci_dev->id.vendor_id;
1617         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1618
1619         /* initialize the vfta */
1620         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1621
1622         /* initialize the hw strip bitmap*/
1623         memset(hwstrip, 0, sizeof(*hwstrip));
1624
1625         /* Initialize the shared code (base driver) */
1626         diag = ixgbe_init_shared_code(hw);
1627         if (diag != IXGBE_SUCCESS) {
1628                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1629                 return -EIO;
1630         }
1631
1632         /* init_mailbox_params */
1633         hw->mbx.ops.init_params(hw);
1634
1635         /* Reset the hw statistics */
1636         ixgbevf_dev_stats_reset(eth_dev);
1637
1638         /* Disable the interrupts for VF */
1639         ixgbevf_intr_disable(hw);
1640
1641         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1642         diag = hw->mac.ops.reset_hw(hw);
1643
1644         /*
1645          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1646          * the underlying PF driver has not assigned a MAC address to the VF.
1647          * In this case, assign a random MAC address.
1648          */
1649         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1650                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1651                 return diag;
1652         }
1653
1654         /* negotiate mailbox API version to use with the PF. */
1655         ixgbevf_negotiate_api(hw);
1656
1657         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1658         ixgbevf_get_queues(hw, &tcs, &tc);
1659
1660         /* Allocate memory for storing MAC addresses */
1661         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1662                                                hw->mac.num_rar_entries, 0);
1663         if (eth_dev->data->mac_addrs == NULL) {
1664                 PMD_INIT_LOG(ERR,
1665                              "Failed to allocate %u bytes needed to store "
1666                              "MAC addresses",
1667                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1668                 return -ENOMEM;
1669         }
1670
1671         /* Generate a random MAC address, if none was assigned by PF. */
1672         if (is_zero_ether_addr(perm_addr)) {
1673                 generate_random_mac_addr(perm_addr);
1674                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1675                 if (diag) {
1676                         rte_free(eth_dev->data->mac_addrs);
1677                         eth_dev->data->mac_addrs = NULL;
1678                         return diag;
1679                 }
1680                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1681                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1682                              "%02x:%02x:%02x:%02x:%02x:%02x",
1683                              perm_addr->addr_bytes[0],
1684                              perm_addr->addr_bytes[1],
1685                              perm_addr->addr_bytes[2],
1686                              perm_addr->addr_bytes[3],
1687                              perm_addr->addr_bytes[4],
1688                              perm_addr->addr_bytes[5]);
1689         }
1690
1691         /* Copy the permanent MAC address */
1692         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1693
1694         /* reset the hardware with the new settings */
1695         diag = hw->mac.ops.start_hw(hw);
1696         switch (diag) {
1697         case  0:
1698                 break;
1699
1700         default:
1701                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1702                 return -EIO;
1703         }
1704
1705         rte_intr_callback_register(intr_handle,
1706                                    ixgbevf_dev_interrupt_handler, eth_dev);
1707         rte_intr_enable(intr_handle);
1708         ixgbevf_intr_enable(hw);
1709
1710         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1711                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1712                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1713
1714         return 0;
1715 }
1716
1717 /* Virtual Function device uninit */
1718
1719 static int
1720 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1721 {
1722         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1723         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1724         struct ixgbe_hw *hw;
1725
1726         PMD_INIT_FUNC_TRACE();
1727
1728         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1729                 return -EPERM;
1730
1731         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1732
1733         if (hw->adapter_stopped == 0)
1734                 ixgbevf_dev_close(eth_dev);
1735
1736         eth_dev->dev_ops = NULL;
1737         eth_dev->rx_pkt_burst = NULL;
1738         eth_dev->tx_pkt_burst = NULL;
1739
1740         /* Disable the interrupts for VF */
1741         ixgbevf_intr_disable(hw);
1742
1743         rte_free(eth_dev->data->mac_addrs);
1744         eth_dev->data->mac_addrs = NULL;
1745
1746         rte_intr_disable(intr_handle);
1747         rte_intr_callback_unregister(intr_handle,
1748                                      ixgbevf_dev_interrupt_handler, eth_dev);
1749
1750         return 0;
1751 }
1752
1753 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1754         struct rte_pci_device *pci_dev)
1755 {
1756         return rte_eth_dev_pci_generic_probe(pci_dev,
1757                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1758 }
1759
1760 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1761 {
1762         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1763 }
1764
1765 static struct rte_pci_driver rte_ixgbe_pmd = {
1766         .id_table = pci_id_ixgbe_map,
1767         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1768                      RTE_PCI_DRV_IOVA_AS_VA,
1769         .probe = eth_ixgbe_pci_probe,
1770         .remove = eth_ixgbe_pci_remove,
1771 };
1772
1773 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1774         struct rte_pci_device *pci_dev)
1775 {
1776         return rte_eth_dev_pci_generic_probe(pci_dev,
1777                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1778 }
1779
1780 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1781 {
1782         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1783 }
1784
1785 /*
1786  * virtual function driver struct
1787  */
1788 static struct rte_pci_driver rte_ixgbevf_pmd = {
1789         .id_table = pci_id_ixgbevf_map,
1790         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1791         .probe = eth_ixgbevf_pci_probe,
1792         .remove = eth_ixgbevf_pci_remove,
1793 };
1794
1795 static int
1796 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1797 {
1798         struct ixgbe_hw *hw =
1799                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1800         struct ixgbe_vfta *shadow_vfta =
1801                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1802         uint32_t vfta;
1803         uint32_t vid_idx;
1804         uint32_t vid_bit;
1805
1806         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1807         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1808         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1809         if (on)
1810                 vfta |= vid_bit;
1811         else
1812                 vfta &= ~vid_bit;
1813         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1814
1815         /* update local VFTA copy */
1816         shadow_vfta->vfta[vid_idx] = vfta;
1817
1818         return 0;
1819 }
1820
1821 static void
1822 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1823 {
1824         if (on)
1825                 ixgbe_vlan_hw_strip_enable(dev, queue);
1826         else
1827                 ixgbe_vlan_hw_strip_disable(dev, queue);
1828 }
1829
1830 static int
1831 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1832                     enum rte_vlan_type vlan_type,
1833                     uint16_t tpid)
1834 {
1835         struct ixgbe_hw *hw =
1836                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1837         int ret = 0;
1838         uint32_t reg;
1839         uint32_t qinq;
1840
1841         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1842         qinq &= IXGBE_DMATXCTL_GDV;
1843
1844         switch (vlan_type) {
1845         case ETH_VLAN_TYPE_INNER:
1846                 if (qinq) {
1847                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1848                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1849                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1850                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1851                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1852                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1853                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1854                 } else {
1855                         ret = -ENOTSUP;
1856                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1857                                     " by single VLAN");
1858                 }
1859                 break;
1860         case ETH_VLAN_TYPE_OUTER:
1861                 if (qinq) {
1862                         /* Only the high 16-bits is valid */
1863                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1864                                         IXGBE_EXVET_VET_EXT_SHIFT);
1865                 } else {
1866                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1867                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1868                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1869                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1870                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1871                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1872                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1873                 }
1874
1875                 break;
1876         default:
1877                 ret = -EINVAL;
1878                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1879                 break;
1880         }
1881
1882         return ret;
1883 }
1884
1885 void
1886 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1887 {
1888         struct ixgbe_hw *hw =
1889                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1890         uint32_t vlnctrl;
1891
1892         PMD_INIT_FUNC_TRACE();
1893
1894         /* Filter Table Disable */
1895         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1896         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1897
1898         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1899 }
1900
1901 void
1902 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1903 {
1904         struct ixgbe_hw *hw =
1905                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1906         struct ixgbe_vfta *shadow_vfta =
1907                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1908         uint32_t vlnctrl;
1909         uint16_t i;
1910
1911         PMD_INIT_FUNC_TRACE();
1912
1913         /* Filter Table Enable */
1914         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1915         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1916         vlnctrl |= IXGBE_VLNCTRL_VFE;
1917
1918         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1919
1920         /* write whatever is in local vfta copy */
1921         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1922                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1923 }
1924
1925 static void
1926 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1927 {
1928         struct ixgbe_hwstrip *hwstrip =
1929                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1930         struct ixgbe_rx_queue *rxq;
1931
1932         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1933                 return;
1934
1935         if (on)
1936                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1937         else
1938                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1939
1940         if (queue >= dev->data->nb_rx_queues)
1941                 return;
1942
1943         rxq = dev->data->rx_queues[queue];
1944
1945         if (on)
1946                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1947         else
1948                 rxq->vlan_flags = PKT_RX_VLAN;
1949 }
1950
1951 static void
1952 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1953 {
1954         struct ixgbe_hw *hw =
1955                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1956         uint32_t ctrl;
1957
1958         PMD_INIT_FUNC_TRACE();
1959
1960         if (hw->mac.type == ixgbe_mac_82598EB) {
1961                 /* No queue level support */
1962                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1963                 return;
1964         }
1965
1966         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1967         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1968         ctrl &= ~IXGBE_RXDCTL_VME;
1969         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1970
1971         /* record those setting for HW strip per queue */
1972         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1973 }
1974
1975 static void
1976 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1977 {
1978         struct ixgbe_hw *hw =
1979                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1980         uint32_t ctrl;
1981
1982         PMD_INIT_FUNC_TRACE();
1983
1984         if (hw->mac.type == ixgbe_mac_82598EB) {
1985                 /* No queue level supported */
1986                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1987                 return;
1988         }
1989
1990         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1991         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1992         ctrl |= IXGBE_RXDCTL_VME;
1993         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1994
1995         /* record those setting for HW strip per queue */
1996         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1997 }
1998
1999 void
2000 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2001 {
2002         struct ixgbe_hw *hw =
2003                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2004         uint32_t ctrl;
2005         uint16_t i;
2006         struct ixgbe_rx_queue *rxq;
2007
2008         PMD_INIT_FUNC_TRACE();
2009
2010         if (hw->mac.type == ixgbe_mac_82598EB) {
2011                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2012                 ctrl &= ~IXGBE_VLNCTRL_VME;
2013                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2014         } else {
2015                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2016                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2017                         rxq = dev->data->rx_queues[i];
2018                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2019                         ctrl &= ~IXGBE_RXDCTL_VME;
2020                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2021
2022                         /* record those setting for HW strip per queue */
2023                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2024                 }
2025         }
2026 }
2027
2028 void
2029 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2030 {
2031         struct ixgbe_hw *hw =
2032                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2033         uint32_t ctrl;
2034         uint16_t i;
2035         struct ixgbe_rx_queue *rxq;
2036
2037         PMD_INIT_FUNC_TRACE();
2038
2039         if (hw->mac.type == ixgbe_mac_82598EB) {
2040                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2041                 ctrl |= IXGBE_VLNCTRL_VME;
2042                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2043         } else {
2044                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2045                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2046                         rxq = dev->data->rx_queues[i];
2047                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2048                         ctrl |= IXGBE_RXDCTL_VME;
2049                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2050
2051                         /* record those setting for HW strip per queue */
2052                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2053                 }
2054         }
2055 }
2056
2057 static void
2058 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2059 {
2060         struct ixgbe_hw *hw =
2061                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2062         uint32_t ctrl;
2063
2064         PMD_INIT_FUNC_TRACE();
2065
2066         /* DMATXCTRL: Geric Double VLAN Disable */
2067         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2068         ctrl &= ~IXGBE_DMATXCTL_GDV;
2069         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2070
2071         /* CTRL_EXT: Global Double VLAN Disable */
2072         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2073         ctrl &= ~IXGBE_EXTENDED_VLAN;
2074         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2075
2076 }
2077
2078 static void
2079 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2080 {
2081         struct ixgbe_hw *hw =
2082                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2083         uint32_t ctrl;
2084
2085         PMD_INIT_FUNC_TRACE();
2086
2087         /* DMATXCTRL: Geric Double VLAN Enable */
2088         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2089         ctrl |= IXGBE_DMATXCTL_GDV;
2090         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2091
2092         /* CTRL_EXT: Global Double VLAN Enable */
2093         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2094         ctrl |= IXGBE_EXTENDED_VLAN;
2095         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2096
2097         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2098         if (hw->mac.type == ixgbe_mac_X550 ||
2099             hw->mac.type == ixgbe_mac_X550EM_x ||
2100             hw->mac.type == ixgbe_mac_X550EM_a) {
2101                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2102                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2103                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2104         }
2105
2106         /*
2107          * VET EXT field in the EXVET register = 0x8100 by default
2108          * So no need to change. Same to VT field of DMATXCTL register
2109          */
2110 }
2111
2112 static int
2113 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2114 {
2115         if (mask & ETH_VLAN_STRIP_MASK) {
2116                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2117                         ixgbe_vlan_hw_strip_enable_all(dev);
2118                 else
2119                         ixgbe_vlan_hw_strip_disable_all(dev);
2120         }
2121
2122         if (mask & ETH_VLAN_FILTER_MASK) {
2123                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2124                         ixgbe_vlan_hw_filter_enable(dev);
2125                 else
2126                         ixgbe_vlan_hw_filter_disable(dev);
2127         }
2128
2129         if (mask & ETH_VLAN_EXTEND_MASK) {
2130                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2131                         ixgbe_vlan_hw_extend_enable(dev);
2132                 else
2133                         ixgbe_vlan_hw_extend_disable(dev);
2134         }
2135
2136         return 0;
2137 }
2138
2139 static void
2140 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2141 {
2142         struct ixgbe_hw *hw =
2143                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2144         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2145         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2146
2147         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2148         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2149 }
2150
2151 static int
2152 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2153 {
2154         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2155
2156         switch (nb_rx_q) {
2157         case 1:
2158         case 2:
2159                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2160                 break;
2161         case 4:
2162                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2163                 break;
2164         default:
2165                 return -EINVAL;
2166         }
2167
2168         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2169         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2170
2171         return 0;
2172 }
2173
2174 static int
2175 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2176 {
2177         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2178         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2179         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2180         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2181
2182         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2183                 /* check multi-queue mode */
2184                 switch (dev_conf->rxmode.mq_mode) {
2185                 case ETH_MQ_RX_VMDQ_DCB:
2186                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2187                         break;
2188                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2189                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2190                         PMD_INIT_LOG(ERR, "SRIOV active,"
2191                                         " unsupported mq_mode rx %d.",
2192                                         dev_conf->rxmode.mq_mode);
2193                         return -EINVAL;
2194                 case ETH_MQ_RX_RSS:
2195                 case ETH_MQ_RX_VMDQ_RSS:
2196                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2197                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2198                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2199                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2200                                                 " invalid queue number"
2201                                                 " for VMDQ RSS, allowed"
2202                                                 " value are 1, 2 or 4.");
2203                                         return -EINVAL;
2204                                 }
2205                         break;
2206                 case ETH_MQ_RX_VMDQ_ONLY:
2207                 case ETH_MQ_RX_NONE:
2208                         /* if nothing mq mode configure, use default scheme */
2209                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2210                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2211                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2212                         break;
2213                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2214                         /* SRIOV only works in VMDq enable mode */
2215                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2216                                         " wrong mq_mode rx %d.",
2217                                         dev_conf->rxmode.mq_mode);
2218                         return -EINVAL;
2219                 }
2220
2221                 switch (dev_conf->txmode.mq_mode) {
2222                 case ETH_MQ_TX_VMDQ_DCB:
2223                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2224                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2225                         break;
2226                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2227                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2228                         break;
2229                 }
2230
2231                 /* check valid queue number */
2232                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2233                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2234                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2235                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2236                                         " must be less than or equal to %d.",
2237                                         nb_rx_q, nb_tx_q,
2238                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2239                         return -EINVAL;
2240                 }
2241         } else {
2242                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2243                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2244                                           " not supported.");
2245                         return -EINVAL;
2246                 }
2247                 /* check configuration for vmdb+dcb mode */
2248                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2249                         const struct rte_eth_vmdq_dcb_conf *conf;
2250
2251                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2252                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2253                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2254                                 return -EINVAL;
2255                         }
2256                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2257                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2258                                conf->nb_queue_pools == ETH_32_POOLS)) {
2259                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2260                                                 " nb_queue_pools must be %d or %d.",
2261                                                 ETH_16_POOLS, ETH_32_POOLS);
2262                                 return -EINVAL;
2263                         }
2264                 }
2265                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2266                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2267
2268                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2269                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2270                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2271                                 return -EINVAL;
2272                         }
2273                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2274                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2275                                conf->nb_queue_pools == ETH_32_POOLS)) {
2276                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2277                                                 " nb_queue_pools != %d and"
2278                                                 " nb_queue_pools != %d.",
2279                                                 ETH_16_POOLS, ETH_32_POOLS);
2280                                 return -EINVAL;
2281                         }
2282                 }
2283
2284                 /* For DCB mode check our configuration before we go further */
2285                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2286                         const struct rte_eth_dcb_rx_conf *conf;
2287
2288                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2289                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2290                                                  IXGBE_DCB_NB_QUEUES);
2291                                 return -EINVAL;
2292                         }
2293                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2294                         if (!(conf->nb_tcs == ETH_4_TCS ||
2295                                conf->nb_tcs == ETH_8_TCS)) {
2296                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2297                                                 " and nb_tcs != %d.",
2298                                                 ETH_4_TCS, ETH_8_TCS);
2299                                 return -EINVAL;
2300                         }
2301                 }
2302
2303                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2304                         const struct rte_eth_dcb_tx_conf *conf;
2305
2306                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2307                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2308                                                  IXGBE_DCB_NB_QUEUES);
2309                                 return -EINVAL;
2310                         }
2311                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2312                         if (!(conf->nb_tcs == ETH_4_TCS ||
2313                                conf->nb_tcs == ETH_8_TCS)) {
2314                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2315                                                 " and nb_tcs != %d.",
2316                                                 ETH_4_TCS, ETH_8_TCS);
2317                                 return -EINVAL;
2318                         }
2319                 }
2320
2321                 /*
2322                  * When DCB/VT is off, maximum number of queues changes,
2323                  * except for 82598EB, which remains constant.
2324                  */
2325                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2326                                 hw->mac.type != ixgbe_mac_82598EB) {
2327                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2328                                 PMD_INIT_LOG(ERR,
2329                                              "Neither VT nor DCB are enabled, "
2330                                              "nb_tx_q > %d.",
2331                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2332                                 return -EINVAL;
2333                         }
2334                 }
2335         }
2336         return 0;
2337 }
2338
2339 static int
2340 ixgbe_dev_configure(struct rte_eth_dev *dev)
2341 {
2342         struct ixgbe_interrupt *intr =
2343                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2344         struct ixgbe_adapter *adapter =
2345                 (struct ixgbe_adapter *)dev->data->dev_private;
2346         int ret;
2347
2348         PMD_INIT_FUNC_TRACE();
2349         /* multipe queue mode checking */
2350         ret  = ixgbe_check_mq_mode(dev);
2351         if (ret != 0) {
2352                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2353                             ret);
2354                 return ret;
2355         }
2356
2357         /* set flag to update link status after init */
2358         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2359
2360         /*
2361          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2362          * allocation or vector Rx preconditions we will reset it.
2363          */
2364         adapter->rx_bulk_alloc_allowed = true;
2365         adapter->rx_vec_allowed = true;
2366
2367         return 0;
2368 }
2369
2370 static void
2371 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2372 {
2373         struct ixgbe_hw *hw =
2374                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2375         struct ixgbe_interrupt *intr =
2376                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2377         uint32_t gpie;
2378
2379         /* only set up it on X550EM_X */
2380         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2381                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2382                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2383                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2384                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2385                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2386         }
2387 }
2388
2389 int
2390 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2391                         uint16_t tx_rate, uint64_t q_msk)
2392 {
2393         struct ixgbe_hw *hw;
2394         struct ixgbe_vf_info *vfinfo;
2395         struct rte_eth_link link;
2396         uint8_t  nb_q_per_pool;
2397         uint32_t queue_stride;
2398         uint32_t queue_idx, idx = 0, vf_idx;
2399         uint32_t queue_end;
2400         uint16_t total_rate = 0;
2401         struct rte_pci_device *pci_dev;
2402
2403         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2404         rte_eth_link_get_nowait(dev->data->port_id, &link);
2405
2406         if (vf >= pci_dev->max_vfs)
2407                 return -EINVAL;
2408
2409         if (tx_rate > link.link_speed)
2410                 return -EINVAL;
2411
2412         if (q_msk == 0)
2413                 return 0;
2414
2415         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2416         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2417         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2418         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2419         queue_idx = vf * queue_stride;
2420         queue_end = queue_idx + nb_q_per_pool - 1;
2421         if (queue_end >= hw->mac.max_tx_queues)
2422                 return -EINVAL;
2423
2424         if (vfinfo) {
2425                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2426                         if (vf_idx == vf)
2427                                 continue;
2428                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2429                                 idx++)
2430                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2431                 }
2432         } else {
2433                 return -EINVAL;
2434         }
2435
2436         /* Store tx_rate for this vf. */
2437         for (idx = 0; idx < nb_q_per_pool; idx++) {
2438                 if (((uint64_t)0x1 << idx) & q_msk) {
2439                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2440                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2441                         total_rate += tx_rate;
2442                 }
2443         }
2444
2445         if (total_rate > dev->data->dev_link.link_speed) {
2446                 /* Reset stored TX rate of the VF if it causes exceed
2447                  * link speed.
2448                  */
2449                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2450                 return -EINVAL;
2451         }
2452
2453         /* Set RTTBCNRC of each queue/pool for vf X  */
2454         for (; queue_idx <= queue_end; queue_idx++) {
2455                 if (0x1 & q_msk)
2456                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2457                 q_msk = q_msk >> 1;
2458         }
2459
2460         return 0;
2461 }
2462
2463 /*
2464  * Configure device link speed and setup link.
2465  * It returns 0 on success.
2466  */
2467 static int
2468 ixgbe_dev_start(struct rte_eth_dev *dev)
2469 {
2470         struct ixgbe_hw *hw =
2471                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2472         struct ixgbe_vf_info *vfinfo =
2473                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2474         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2475         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2476         uint32_t intr_vector = 0;
2477         int err, link_up = 0, negotiate = 0;
2478         uint32_t speed = 0;
2479         int mask = 0;
2480         int status;
2481         uint16_t vf, idx;
2482         uint32_t *link_speeds;
2483         struct ixgbe_tm_conf *tm_conf =
2484                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2485
2486         PMD_INIT_FUNC_TRACE();
2487
2488         /* IXGBE devices don't support:
2489         *    - half duplex (checked afterwards for valid speeds)
2490         *    - fixed speed: TODO implement
2491         */
2492         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2493                 PMD_INIT_LOG(ERR,
2494                 "Invalid link_speeds for port %u, fix speed not supported",
2495                                 dev->data->port_id);
2496                 return -EINVAL;
2497         }
2498
2499         /* disable uio/vfio intr/eventfd mapping */
2500         rte_intr_disable(intr_handle);
2501
2502         /* stop adapter */
2503         hw->adapter_stopped = 0;
2504         ixgbe_stop_adapter(hw);
2505
2506         /* reinitialize adapter
2507          * this calls reset and start
2508          */
2509         status = ixgbe_pf_reset_hw(hw);
2510         if (status != 0)
2511                 return -1;
2512         hw->mac.ops.start_hw(hw);
2513         hw->mac.get_link_status = true;
2514
2515         /* configure PF module if SRIOV enabled */
2516         ixgbe_pf_host_configure(dev);
2517
2518         ixgbe_dev_phy_intr_setup(dev);
2519
2520         /* check and configure queue intr-vector mapping */
2521         if ((rte_intr_cap_multiple(intr_handle) ||
2522              !RTE_ETH_DEV_SRIOV(dev).active) &&
2523             dev->data->dev_conf.intr_conf.rxq != 0) {
2524                 intr_vector = dev->data->nb_rx_queues;
2525                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2526                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2527                                         IXGBE_MAX_INTR_QUEUE_NUM);
2528                         return -ENOTSUP;
2529                 }
2530                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2531                         return -1;
2532         }
2533
2534         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2535                 intr_handle->intr_vec =
2536                         rte_zmalloc("intr_vec",
2537                                     dev->data->nb_rx_queues * sizeof(int), 0);
2538                 if (intr_handle->intr_vec == NULL) {
2539                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2540                                      " intr_vec", dev->data->nb_rx_queues);
2541                         return -ENOMEM;
2542                 }
2543         }
2544
2545         /* confiugre msix for sleep until rx interrupt */
2546         ixgbe_configure_msix(dev);
2547
2548         /* initialize transmission unit */
2549         ixgbe_dev_tx_init(dev);
2550
2551         /* This can fail when allocating mbufs for descriptor rings */
2552         err = ixgbe_dev_rx_init(dev);
2553         if (err) {
2554                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2555                 goto error;
2556         }
2557
2558         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2559                 ETH_VLAN_EXTEND_MASK;
2560         err = ixgbe_vlan_offload_set(dev, mask);
2561         if (err) {
2562                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2563                 goto error;
2564         }
2565
2566         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2567                 /* Enable vlan filtering for VMDq */
2568                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2569         }
2570
2571         /* Configure DCB hw */
2572         ixgbe_configure_dcb(dev);
2573
2574         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2575                 err = ixgbe_fdir_configure(dev);
2576                 if (err)
2577                         goto error;
2578         }
2579
2580         /* Restore vf rate limit */
2581         if (vfinfo != NULL) {
2582                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2583                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2584                                 if (vfinfo[vf].tx_rate[idx] != 0)
2585                                         ixgbe_set_vf_rate_limit(
2586                                                 dev, vf,
2587                                                 vfinfo[vf].tx_rate[idx],
2588                                                 1 << idx);
2589         }
2590
2591         ixgbe_restore_statistics_mapping(dev);
2592
2593         err = ixgbe_dev_rxtx_start(dev);
2594         if (err < 0) {
2595                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2596                 goto error;
2597         }
2598
2599         /* Skip link setup if loopback mode is enabled for 82599. */
2600         if (hw->mac.type == ixgbe_mac_82599EB &&
2601                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2602                 goto skip_link_setup;
2603
2604         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2605                 err = hw->mac.ops.setup_sfp(hw);
2606                 if (err)
2607                         goto error;
2608         }
2609
2610         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2611                 /* Turn on the copper */
2612                 ixgbe_set_phy_power(hw, true);
2613         } else {
2614                 /* Turn on the laser */
2615                 ixgbe_enable_tx_laser(hw);
2616         }
2617
2618         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2619         if (err)
2620                 goto error;
2621         dev->data->dev_link.link_status = link_up;
2622
2623         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2624         if (err)
2625                 goto error;
2626
2627         link_speeds = &dev->data->dev_conf.link_speeds;
2628         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2629                         ETH_LINK_SPEED_10G)) {
2630                 PMD_INIT_LOG(ERR, "Invalid link setting");
2631                 goto error;
2632         }
2633
2634         speed = 0x0;
2635         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2636                 switch (hw->mac.type) {
2637                 case ixgbe_mac_82598EB:
2638                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2639                         break;
2640                 case ixgbe_mac_82599EB:
2641                 case ixgbe_mac_X540:
2642                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2643                         break;
2644                 case ixgbe_mac_X550:
2645                 case ixgbe_mac_X550EM_x:
2646                 case ixgbe_mac_X550EM_a:
2647                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2648                         break;
2649                 default:
2650                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2651                 }
2652         } else {
2653                 if (*link_speeds & ETH_LINK_SPEED_10G)
2654                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2655                 if (*link_speeds & ETH_LINK_SPEED_1G)
2656                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2657                 if (*link_speeds & ETH_LINK_SPEED_100M)
2658                         speed |= IXGBE_LINK_SPEED_100_FULL;
2659         }
2660
2661         err = ixgbe_setup_link(hw, speed, link_up);
2662         if (err)
2663                 goto error;
2664
2665 skip_link_setup:
2666
2667         if (rte_intr_allow_others(intr_handle)) {
2668                 /* check if lsc interrupt is enabled */
2669                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2670                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2671                 else
2672                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2673                 ixgbe_dev_macsec_interrupt_setup(dev);
2674         } else {
2675                 rte_intr_callback_unregister(intr_handle,
2676                                              ixgbe_dev_interrupt_handler, dev);
2677                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2678                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2679                                      " no intr multiplex");
2680         }
2681
2682         /* check if rxq interrupt is enabled */
2683         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2684             rte_intr_dp_is_en(intr_handle))
2685                 ixgbe_dev_rxq_interrupt_setup(dev);
2686
2687         /* enable uio/vfio intr/eventfd mapping */
2688         rte_intr_enable(intr_handle);
2689
2690         /* resume enabled intr since hw reset */
2691         ixgbe_enable_intr(dev);
2692         ixgbe_l2_tunnel_conf(dev);
2693         ixgbe_filter_restore(dev);
2694
2695         if (tm_conf->root && !tm_conf->committed)
2696                 PMD_DRV_LOG(WARNING,
2697                             "please call hierarchy_commit() "
2698                             "before starting the port");
2699
2700         return 0;
2701
2702 error:
2703         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2704         ixgbe_dev_clear_queues(dev);
2705         return -EIO;
2706 }
2707
2708 /*
2709  * Stop device: disable rx and tx functions to allow for reconfiguring.
2710  */
2711 static void
2712 ixgbe_dev_stop(struct rte_eth_dev *dev)
2713 {
2714         struct rte_eth_link link;
2715         struct ixgbe_hw *hw =
2716                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2717         struct ixgbe_vf_info *vfinfo =
2718                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2719         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2720         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2721         int vf;
2722         struct ixgbe_tm_conf *tm_conf =
2723                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2724
2725         PMD_INIT_FUNC_TRACE();
2726
2727         /* disable interrupts */
2728         ixgbe_disable_intr(hw);
2729
2730         /* reset the NIC */
2731         ixgbe_pf_reset_hw(hw);
2732         hw->adapter_stopped = 0;
2733
2734         /* stop adapter */
2735         ixgbe_stop_adapter(hw);
2736
2737         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2738                 vfinfo[vf].clear_to_send = false;
2739
2740         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2741                 /* Turn off the copper */
2742                 ixgbe_set_phy_power(hw, false);
2743         } else {
2744                 /* Turn off the laser */
2745                 ixgbe_disable_tx_laser(hw);
2746         }
2747
2748         ixgbe_dev_clear_queues(dev);
2749
2750         /* Clear stored conf */
2751         dev->data->scattered_rx = 0;
2752         dev->data->lro = 0;
2753
2754         /* Clear recorded link status */
2755         memset(&link, 0, sizeof(link));
2756         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2757
2758         if (!rte_intr_allow_others(intr_handle))
2759                 /* resume to the default handler */
2760                 rte_intr_callback_register(intr_handle,
2761                                            ixgbe_dev_interrupt_handler,
2762                                            (void *)dev);
2763
2764         /* Clean datapath event and queue/vec mapping */
2765         rte_intr_efd_disable(intr_handle);
2766         if (intr_handle->intr_vec != NULL) {
2767                 rte_free(intr_handle->intr_vec);
2768                 intr_handle->intr_vec = NULL;
2769         }
2770
2771         /* reset hierarchy commit */
2772         tm_conf->committed = false;
2773 }
2774
2775 /*
2776  * Set device link up: enable tx.
2777  */
2778 static int
2779 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2780 {
2781         struct ixgbe_hw *hw =
2782                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2783         if (hw->mac.type == ixgbe_mac_82599EB) {
2784 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2785                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2786                         /* Not suported in bypass mode */
2787                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2788                                      "by device id 0x%x", hw->device_id);
2789                         return -ENOTSUP;
2790                 }
2791 #endif
2792         }
2793
2794         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2795                 /* Turn on the copper */
2796                 ixgbe_set_phy_power(hw, true);
2797         } else {
2798                 /* Turn on the laser */
2799                 ixgbe_enable_tx_laser(hw);
2800         }
2801
2802         return 0;
2803 }
2804
2805 /*
2806  * Set device link down: disable tx.
2807  */
2808 static int
2809 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2810 {
2811         struct ixgbe_hw *hw =
2812                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2813         if (hw->mac.type == ixgbe_mac_82599EB) {
2814 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2815                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2816                         /* Not suported in bypass mode */
2817                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2818                                      "by device id 0x%x", hw->device_id);
2819                         return -ENOTSUP;
2820                 }
2821 #endif
2822         }
2823
2824         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2825                 /* Turn off the copper */
2826                 ixgbe_set_phy_power(hw, false);
2827         } else {
2828                 /* Turn off the laser */
2829                 ixgbe_disable_tx_laser(hw);
2830         }
2831
2832         return 0;
2833 }
2834
2835 /*
2836  * Reset and stop device.
2837  */
2838 static void
2839 ixgbe_dev_close(struct rte_eth_dev *dev)
2840 {
2841         struct ixgbe_hw *hw =
2842                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2843
2844         PMD_INIT_FUNC_TRACE();
2845
2846         ixgbe_pf_reset_hw(hw);
2847
2848         ixgbe_dev_stop(dev);
2849         hw->adapter_stopped = 1;
2850
2851         ixgbe_dev_free_queues(dev);
2852
2853         ixgbe_disable_pcie_master(hw);
2854
2855         /* reprogram the RAR[0] in case user changed it. */
2856         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2857 }
2858
2859 /*
2860  * Reset PF device.
2861  */
2862 static int
2863 ixgbe_dev_reset(struct rte_eth_dev *dev)
2864 {
2865         int ret;
2866
2867         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2868          * its VF to make them align with it. The detailed notification
2869          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2870          * To avoid unexpected behavior in VF, currently reset of PF with
2871          * SR-IOV activation is not supported. It might be supported later.
2872          */
2873         if (dev->data->sriov.active)
2874                 return -ENOTSUP;
2875
2876         ret = eth_ixgbe_dev_uninit(dev);
2877         if (ret)
2878                 return ret;
2879
2880         ret = eth_ixgbe_dev_init(dev);
2881
2882         return ret;
2883 }
2884
2885 static void
2886 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2887                            struct ixgbe_hw_stats *hw_stats,
2888                            struct ixgbe_macsec_stats *macsec_stats,
2889                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2890                            uint64_t *total_qprc, uint64_t *total_qprdc)
2891 {
2892         uint32_t bprc, lxon, lxoff, total;
2893         uint32_t delta_gprc = 0;
2894         unsigned i;
2895         /* Workaround for RX byte count not including CRC bytes when CRC
2896          * strip is enabled. CRC bytes are removed from counters when crc_strip
2897          * is disabled.
2898          */
2899         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2900                         IXGBE_HLREG0_RXCRCSTRP);
2901
2902         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2903         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2904         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2905         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2906
2907         for (i = 0; i < 8; i++) {
2908                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2909
2910                 /* global total per queue */
2911                 hw_stats->mpc[i] += mp;
2912                 /* Running comprehensive total for stats display */
2913                 *total_missed_rx += hw_stats->mpc[i];
2914                 if (hw->mac.type == ixgbe_mac_82598EB) {
2915                         hw_stats->rnbc[i] +=
2916                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2917                         hw_stats->pxonrxc[i] +=
2918                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2919                         hw_stats->pxoffrxc[i] +=
2920                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2921                 } else {
2922                         hw_stats->pxonrxc[i] +=
2923                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2924                         hw_stats->pxoffrxc[i] +=
2925                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2926                         hw_stats->pxon2offc[i] +=
2927                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2928                 }
2929                 hw_stats->pxontxc[i] +=
2930                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2931                 hw_stats->pxofftxc[i] +=
2932                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2933         }
2934         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2935                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2936                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2937                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2938
2939                 delta_gprc += delta_qprc;
2940
2941                 hw_stats->qprc[i] += delta_qprc;
2942                 hw_stats->qptc[i] += delta_qptc;
2943
2944                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2945                 hw_stats->qbrc[i] +=
2946                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2947                 if (crc_strip == 0)
2948                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2949
2950                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2951                 hw_stats->qbtc[i] +=
2952                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2953
2954                 hw_stats->qprdc[i] += delta_qprdc;
2955                 *total_qprdc += hw_stats->qprdc[i];
2956
2957                 *total_qprc += hw_stats->qprc[i];
2958                 *total_qbrc += hw_stats->qbrc[i];
2959         }
2960         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2961         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2962         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2963
2964         /*
2965          * An errata states that gprc actually counts good + missed packets:
2966          * Workaround to set gprc to summated queue packet receives
2967          */
2968         hw_stats->gprc = *total_qprc;
2969
2970         if (hw->mac.type != ixgbe_mac_82598EB) {
2971                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2972                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2973                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2974                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2975                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2976                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2977                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2978                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2979         } else {
2980                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2981                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2982                 /* 82598 only has a counter in the high register */
2983                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2984                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2985                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2986         }
2987         uint64_t old_tpr = hw_stats->tpr;
2988
2989         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2990         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2991
2992         if (crc_strip == 0)
2993                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2994
2995         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2996         hw_stats->gptc += delta_gptc;
2997         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2998         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2999
3000         /*
3001          * Workaround: mprc hardware is incorrectly counting
3002          * broadcasts, so for now we subtract those.
3003          */
3004         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3005         hw_stats->bprc += bprc;
3006         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3007         if (hw->mac.type == ixgbe_mac_82598EB)
3008                 hw_stats->mprc -= bprc;
3009
3010         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3011         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3012         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3013         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3014         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3015         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3016
3017         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3018         hw_stats->lxontxc += lxon;
3019         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3020         hw_stats->lxofftxc += lxoff;
3021         total = lxon + lxoff;
3022
3023         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3024         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3025         hw_stats->gptc -= total;
3026         hw_stats->mptc -= total;
3027         hw_stats->ptc64 -= total;
3028         hw_stats->gotc -= total * ETHER_MIN_LEN;
3029
3030         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3031         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3032         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3033         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3034         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3035         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3036         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3037         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3038         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3039         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3040         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3041         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3042         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3043         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3044         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3045         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3046         /* Only read FCOE on 82599 */
3047         if (hw->mac.type != ixgbe_mac_82598EB) {
3048                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3049                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3050                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3051                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3052                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3053         }
3054
3055         /* Flow Director Stats registers */
3056         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3057         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3058
3059         /* MACsec Stats registers */
3060         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3061         macsec_stats->out_pkts_encrypted +=
3062                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3063         macsec_stats->out_pkts_protected +=
3064                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3065         macsec_stats->out_octets_encrypted +=
3066                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3067         macsec_stats->out_octets_protected +=
3068                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3069         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3070         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3071         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3072         macsec_stats->in_pkts_unknownsci +=
3073                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3074         macsec_stats->in_octets_decrypted +=
3075                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3076         macsec_stats->in_octets_validated +=
3077                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3078         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3079         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3080         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3081         for (i = 0; i < 2; i++) {
3082                 macsec_stats->in_pkts_ok +=
3083                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3084                 macsec_stats->in_pkts_invalid +=
3085                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3086                 macsec_stats->in_pkts_notvalid +=
3087                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3088         }
3089         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3090         macsec_stats->in_pkts_notusingsa +=
3091                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3092 }
3093
3094 /*
3095  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3096  */
3097 static int
3098 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3099 {
3100         struct ixgbe_hw *hw =
3101                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3102         struct ixgbe_hw_stats *hw_stats =
3103                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3104         struct ixgbe_macsec_stats *macsec_stats =
3105                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3106                                 dev->data->dev_private);
3107         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3108         unsigned i;
3109
3110         total_missed_rx = 0;
3111         total_qbrc = 0;
3112         total_qprc = 0;
3113         total_qprdc = 0;
3114
3115         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3116                         &total_qbrc, &total_qprc, &total_qprdc);
3117
3118         if (stats == NULL)
3119                 return -EINVAL;
3120
3121         /* Fill out the rte_eth_stats statistics structure */
3122         stats->ipackets = total_qprc;
3123         stats->ibytes = total_qbrc;
3124         stats->opackets = hw_stats->gptc;
3125         stats->obytes = hw_stats->gotc;
3126
3127         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3128                 stats->q_ipackets[i] = hw_stats->qprc[i];
3129                 stats->q_opackets[i] = hw_stats->qptc[i];
3130                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3131                 stats->q_obytes[i] = hw_stats->qbtc[i];
3132                 stats->q_errors[i] = hw_stats->qprdc[i];
3133         }
3134
3135         /* Rx Errors */
3136         stats->imissed  = total_missed_rx;
3137         stats->ierrors  = hw_stats->crcerrs +
3138                           hw_stats->mspdc +
3139                           hw_stats->rlec +
3140                           hw_stats->ruc +
3141                           hw_stats->roc +
3142                           hw_stats->illerrc +
3143                           hw_stats->errbc +
3144                           hw_stats->rfc +
3145                           hw_stats->fccrc +
3146                           hw_stats->fclast;
3147
3148         /* Tx Errors */
3149         stats->oerrors  = 0;
3150         return 0;
3151 }
3152
3153 static void
3154 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3155 {
3156         struct ixgbe_hw_stats *stats =
3157                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3158
3159         /* HW registers are cleared on read */
3160         ixgbe_dev_stats_get(dev, NULL);
3161
3162         /* Reset software totals */
3163         memset(stats, 0, sizeof(*stats));
3164 }
3165
3166 /* This function calculates the number of xstats based on the current config */
3167 static unsigned
3168 ixgbe_xstats_calc_num(void) {
3169         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3170                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3171                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3172 }
3173
3174 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3175         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3176 {
3177         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3178         unsigned stat, i, count;
3179
3180         if (xstats_names != NULL) {
3181                 count = 0;
3182
3183                 /* Note: limit >= cnt_stats checked upstream
3184                  * in rte_eth_xstats_names()
3185                  */
3186
3187                 /* Extended stats from ixgbe_hw_stats */
3188                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3189                         snprintf(xstats_names[count].name,
3190                                 sizeof(xstats_names[count].name),
3191                                 "%s",
3192                                 rte_ixgbe_stats_strings[i].name);
3193                         count++;
3194                 }
3195
3196                 /* MACsec Stats */
3197                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3198                         snprintf(xstats_names[count].name,
3199                                 sizeof(xstats_names[count].name),
3200                                 "%s",
3201                                 rte_ixgbe_macsec_strings[i].name);
3202                         count++;
3203                 }
3204
3205                 /* RX Priority Stats */
3206                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3207                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3208                                 snprintf(xstats_names[count].name,
3209                                         sizeof(xstats_names[count].name),
3210                                         "rx_priority%u_%s", i,
3211                                         rte_ixgbe_rxq_strings[stat].name);
3212                                 count++;
3213                         }
3214                 }
3215
3216                 /* TX Priority Stats */
3217                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3218                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3219                                 snprintf(xstats_names[count].name,
3220                                         sizeof(xstats_names[count].name),
3221                                         "tx_priority%u_%s", i,
3222                                         rte_ixgbe_txq_strings[stat].name);
3223                                 count++;
3224                         }
3225                 }
3226         }
3227         return cnt_stats;
3228 }
3229
3230 static int ixgbe_dev_xstats_get_names_by_id(
3231         struct rte_eth_dev *dev,
3232         struct rte_eth_xstat_name *xstats_names,
3233         const uint64_t *ids,
3234         unsigned int limit)
3235 {
3236         if (!ids) {
3237                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3238                 unsigned int stat, i, count;
3239
3240                 if (xstats_names != NULL) {
3241                         count = 0;
3242
3243                         /* Note: limit >= cnt_stats checked upstream
3244                          * in rte_eth_xstats_names()
3245                          */
3246
3247                         /* Extended stats from ixgbe_hw_stats */
3248                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3249                                 snprintf(xstats_names[count].name,
3250                                         sizeof(xstats_names[count].name),
3251                                         "%s",
3252                                         rte_ixgbe_stats_strings[i].name);
3253                                 count++;
3254                         }
3255
3256                         /* MACsec Stats */
3257                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3258                                 snprintf(xstats_names[count].name,
3259                                         sizeof(xstats_names[count].name),
3260                                         "%s",
3261                                         rte_ixgbe_macsec_strings[i].name);
3262                                 count++;
3263                         }
3264
3265                         /* RX Priority Stats */
3266                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3267                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3268                                         snprintf(xstats_names[count].name,
3269                                             sizeof(xstats_names[count].name),
3270                                             "rx_priority%u_%s", i,
3271                                             rte_ixgbe_rxq_strings[stat].name);
3272                                         count++;
3273                                 }
3274                         }
3275
3276                         /* TX Priority Stats */
3277                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3278                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3279                                         snprintf(xstats_names[count].name,
3280                                             sizeof(xstats_names[count].name),
3281                                             "tx_priority%u_%s", i,
3282                                             rte_ixgbe_txq_strings[stat].name);
3283                                         count++;
3284                                 }
3285                         }
3286                 }
3287                 return cnt_stats;
3288         }
3289
3290         uint16_t i;
3291         uint16_t size = ixgbe_xstats_calc_num();
3292         struct rte_eth_xstat_name xstats_names_copy[size];
3293
3294         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3295                         size);
3296
3297         for (i = 0; i < limit; i++) {
3298                 if (ids[i] >= size) {
3299                         PMD_INIT_LOG(ERR, "id value isn't valid");
3300                         return -1;
3301                 }
3302                 strcpy(xstats_names[i].name,
3303                                 xstats_names_copy[ids[i]].name);
3304         }
3305         return limit;
3306 }
3307
3308 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3309         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3310 {
3311         unsigned i;
3312
3313         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3314                 return -ENOMEM;
3315
3316         if (xstats_names != NULL)
3317                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3318                         snprintf(xstats_names[i].name,
3319                                 sizeof(xstats_names[i].name),
3320                                 "%s", rte_ixgbevf_stats_strings[i].name);
3321         return IXGBEVF_NB_XSTATS;
3322 }
3323
3324 static int
3325 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3326                                          unsigned n)
3327 {
3328         struct ixgbe_hw *hw =
3329                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3330         struct ixgbe_hw_stats *hw_stats =
3331                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3332         struct ixgbe_macsec_stats *macsec_stats =
3333                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3334                                 dev->data->dev_private);
3335         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3336         unsigned i, stat, count = 0;
3337
3338         count = ixgbe_xstats_calc_num();
3339
3340         if (n < count)
3341                 return count;
3342
3343         total_missed_rx = 0;
3344         total_qbrc = 0;
3345         total_qprc = 0;
3346         total_qprdc = 0;
3347
3348         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3349                         &total_qbrc, &total_qprc, &total_qprdc);
3350
3351         /* If this is a reset xstats is NULL, and we have cleared the
3352          * registers by reading them.
3353          */
3354         if (!xstats)
3355                 return 0;
3356
3357         /* Extended stats from ixgbe_hw_stats */
3358         count = 0;
3359         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3360                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3361                                 rte_ixgbe_stats_strings[i].offset);
3362                 xstats[count].id = count;
3363                 count++;
3364         }
3365
3366         /* MACsec Stats */
3367         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3368                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3369                                 rte_ixgbe_macsec_strings[i].offset);
3370                 xstats[count].id = count;
3371                 count++;
3372         }
3373
3374         /* RX Priority Stats */
3375         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3376                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3377                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3378                                         rte_ixgbe_rxq_strings[stat].offset +
3379                                         (sizeof(uint64_t) * i));
3380                         xstats[count].id = count;
3381                         count++;
3382                 }
3383         }
3384
3385         /* TX Priority Stats */
3386         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3387                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3388                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3389                                         rte_ixgbe_txq_strings[stat].offset +
3390                                         (sizeof(uint64_t) * i));
3391                         xstats[count].id = count;
3392                         count++;
3393                 }
3394         }
3395         return count;
3396 }
3397
3398 static int
3399 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3400                 uint64_t *values, unsigned int n)
3401 {
3402         if (!ids) {
3403                 struct ixgbe_hw *hw =
3404                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3405                 struct ixgbe_hw_stats *hw_stats =
3406                                 IXGBE_DEV_PRIVATE_TO_STATS(
3407                                                 dev->data->dev_private);
3408                 struct ixgbe_macsec_stats *macsec_stats =
3409                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3410                                         dev->data->dev_private);
3411                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3412                 unsigned int i, stat, count = 0;
3413
3414                 count = ixgbe_xstats_calc_num();
3415
3416                 if (!ids && n < count)
3417                         return count;
3418
3419                 total_missed_rx = 0;
3420                 total_qbrc = 0;
3421                 total_qprc = 0;
3422                 total_qprdc = 0;
3423
3424                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3425                                 &total_missed_rx, &total_qbrc, &total_qprc,
3426                                 &total_qprdc);
3427
3428                 /* If this is a reset xstats is NULL, and we have cleared the
3429                  * registers by reading them.
3430                  */
3431                 if (!ids && !values)
3432                         return 0;
3433
3434                 /* Extended stats from ixgbe_hw_stats */
3435                 count = 0;
3436                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3437                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3438                                         rte_ixgbe_stats_strings[i].offset);
3439                         count++;
3440                 }
3441
3442                 /* MACsec Stats */
3443                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3444                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3445                                         rte_ixgbe_macsec_strings[i].offset);
3446                         count++;
3447                 }
3448
3449                 /* RX Priority Stats */
3450                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3451                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3452                                 values[count] =
3453                                         *(uint64_t *)(((char *)hw_stats) +
3454                                         rte_ixgbe_rxq_strings[stat].offset +
3455                                         (sizeof(uint64_t) * i));
3456                                 count++;
3457                         }
3458                 }
3459
3460                 /* TX Priority Stats */
3461                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3462                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3463                                 values[count] =
3464                                         *(uint64_t *)(((char *)hw_stats) +
3465                                         rte_ixgbe_txq_strings[stat].offset +
3466                                         (sizeof(uint64_t) * i));
3467                                 count++;
3468                         }
3469                 }
3470                 return count;
3471         }
3472
3473         uint16_t i;
3474         uint16_t size = ixgbe_xstats_calc_num();
3475         uint64_t values_copy[size];
3476
3477         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3478
3479         for (i = 0; i < n; i++) {
3480                 if (ids[i] >= size) {
3481                         PMD_INIT_LOG(ERR, "id value isn't valid");
3482                         return -1;
3483                 }
3484                 values[i] = values_copy[ids[i]];
3485         }
3486         return n;
3487 }
3488
3489 static void
3490 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3491 {
3492         struct ixgbe_hw_stats *stats =
3493                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3494         struct ixgbe_macsec_stats *macsec_stats =
3495                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3496                                 dev->data->dev_private);
3497
3498         unsigned count = ixgbe_xstats_calc_num();
3499
3500         /* HW registers are cleared on read */
3501         ixgbe_dev_xstats_get(dev, NULL, count);
3502
3503         /* Reset software totals */
3504         memset(stats, 0, sizeof(*stats));
3505         memset(macsec_stats, 0, sizeof(*macsec_stats));
3506 }
3507
3508 static void
3509 ixgbevf_update_stats(struct rte_eth_dev *dev)
3510 {
3511         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3512         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3513                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3514
3515         /* Good Rx packet, include VF loopback */
3516         UPDATE_VF_STAT(IXGBE_VFGPRC,
3517             hw_stats->last_vfgprc, hw_stats->vfgprc);
3518
3519         /* Good Rx octets, include VF loopback */
3520         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3521             hw_stats->last_vfgorc, hw_stats->vfgorc);
3522
3523         /* Good Tx packet, include VF loopback */
3524         UPDATE_VF_STAT(IXGBE_VFGPTC,
3525             hw_stats->last_vfgptc, hw_stats->vfgptc);
3526
3527         /* Good Tx octets, include VF loopback */
3528         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3529             hw_stats->last_vfgotc, hw_stats->vfgotc);
3530
3531         /* Rx Multicst Packet */
3532         UPDATE_VF_STAT(IXGBE_VFMPRC,
3533             hw_stats->last_vfmprc, hw_stats->vfmprc);
3534 }
3535
3536 static int
3537 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3538                        unsigned n)
3539 {
3540         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3541                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3542         unsigned i;
3543
3544         if (n < IXGBEVF_NB_XSTATS)
3545                 return IXGBEVF_NB_XSTATS;
3546
3547         ixgbevf_update_stats(dev);
3548
3549         if (!xstats)
3550                 return 0;
3551
3552         /* Extended stats */
3553         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3554                 xstats[i].id = i;
3555                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3556                         rte_ixgbevf_stats_strings[i].offset);
3557         }
3558
3559         return IXGBEVF_NB_XSTATS;
3560 }
3561
3562 static int
3563 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3564 {
3565         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3566                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3567
3568         ixgbevf_update_stats(dev);
3569
3570         if (stats == NULL)
3571                 return -EINVAL;
3572
3573         stats->ipackets = hw_stats->vfgprc;
3574         stats->ibytes = hw_stats->vfgorc;
3575         stats->opackets = hw_stats->vfgptc;
3576         stats->obytes = hw_stats->vfgotc;
3577         return 0;
3578 }
3579
3580 static void
3581 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3582 {
3583         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3584                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3585
3586         /* Sync HW register to the last stats */
3587         ixgbevf_dev_stats_get(dev, NULL);
3588
3589         /* reset HW current stats*/
3590         hw_stats->vfgprc = 0;
3591         hw_stats->vfgorc = 0;
3592         hw_stats->vfgptc = 0;
3593         hw_stats->vfgotc = 0;
3594 }
3595
3596 static int
3597 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3598 {
3599         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3600         u16 eeprom_verh, eeprom_verl;
3601         u32 etrack_id;
3602         int ret;
3603
3604         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3605         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3606
3607         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3608         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3609
3610         ret += 1; /* add the size of '\0' */
3611         if (fw_size < (u32)ret)
3612                 return ret;
3613         else
3614                 return 0;
3615 }
3616
3617 static void
3618 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3619 {
3620         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3621         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3622         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3623
3624         dev_info->pci_dev = pci_dev;
3625         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3626         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3627         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3628                 /*
3629                  * When DCB/VT is off, maximum number of queues changes,
3630                  * except for 82598EB, which remains constant.
3631                  */
3632                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3633                                 hw->mac.type != ixgbe_mac_82598EB)
3634                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3635         }
3636         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3637         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3638         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3639         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3640         dev_info->max_vfs = pci_dev->max_vfs;
3641         if (hw->mac.type == ixgbe_mac_82598EB)
3642                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3643         else
3644                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3645         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3646         dev_info->rx_offload_capa =
3647                 DEV_RX_OFFLOAD_VLAN_STRIP |
3648                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3649                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3650                 DEV_RX_OFFLOAD_TCP_CKSUM;
3651
3652         /*
3653          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3654          * mode.
3655          */
3656         if ((hw->mac.type == ixgbe_mac_82599EB ||
3657              hw->mac.type == ixgbe_mac_X540) &&
3658             !RTE_ETH_DEV_SRIOV(dev).active)
3659                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3660
3661         if (hw->mac.type == ixgbe_mac_82599EB ||
3662             hw->mac.type == ixgbe_mac_X540)
3663                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3664
3665         if (hw->mac.type == ixgbe_mac_X550 ||
3666             hw->mac.type == ixgbe_mac_X550EM_x ||
3667             hw->mac.type == ixgbe_mac_X550EM_a)
3668                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3669
3670         dev_info->tx_offload_capa =
3671                 DEV_TX_OFFLOAD_VLAN_INSERT |
3672                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3673                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3674                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3675                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3676                 DEV_TX_OFFLOAD_TCP_TSO;
3677
3678         if (hw->mac.type == ixgbe_mac_82599EB ||
3679             hw->mac.type == ixgbe_mac_X540)
3680                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3681
3682         if (hw->mac.type == ixgbe_mac_X550 ||
3683             hw->mac.type == ixgbe_mac_X550EM_x ||
3684             hw->mac.type == ixgbe_mac_X550EM_a)
3685                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3686
3687 #ifdef RTE_LIBRTE_SECURITY
3688         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
3689         dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
3690 #endif
3691
3692         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3693                 .rx_thresh = {
3694                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3695                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3696                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3697                 },
3698                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3699                 .rx_drop_en = 0,
3700         };
3701
3702         dev_info->default_txconf = (struct rte_eth_txconf) {
3703                 .tx_thresh = {
3704                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3705                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3706                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3707                 },
3708                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3709                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3710                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3711                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3712         };
3713
3714         dev_info->rx_desc_lim = rx_desc_lim;
3715         dev_info->tx_desc_lim = tx_desc_lim;
3716
3717         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3718         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3719         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3720
3721         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3722         if (hw->mac.type == ixgbe_mac_X540 ||
3723             hw->mac.type == ixgbe_mac_X540_vf ||
3724             hw->mac.type == ixgbe_mac_X550 ||
3725             hw->mac.type == ixgbe_mac_X550_vf) {
3726                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3727         }
3728         if (hw->mac.type == ixgbe_mac_X550) {
3729                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3730                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3731         }
3732 }
3733
3734 static const uint32_t *
3735 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3736 {
3737         static const uint32_t ptypes[] = {
3738                 /* For non-vec functions,
3739                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3740                  * for vec functions,
3741                  * refers to _recv_raw_pkts_vec().
3742                  */
3743                 RTE_PTYPE_L2_ETHER,
3744                 RTE_PTYPE_L3_IPV4,
3745                 RTE_PTYPE_L3_IPV4_EXT,
3746                 RTE_PTYPE_L3_IPV6,
3747                 RTE_PTYPE_L3_IPV6_EXT,
3748                 RTE_PTYPE_L4_SCTP,
3749                 RTE_PTYPE_L4_TCP,
3750                 RTE_PTYPE_L4_UDP,
3751                 RTE_PTYPE_TUNNEL_IP,
3752                 RTE_PTYPE_INNER_L3_IPV6,
3753                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3754                 RTE_PTYPE_INNER_L4_TCP,
3755                 RTE_PTYPE_INNER_L4_UDP,
3756                 RTE_PTYPE_UNKNOWN
3757         };
3758
3759         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3760             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3761             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3762             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3763                 return ptypes;
3764
3765 #if defined(RTE_ARCH_X86)
3766         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3767             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3768                 return ptypes;
3769 #endif
3770         return NULL;
3771 }
3772
3773 static void
3774 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3775                      struct rte_eth_dev_info *dev_info)
3776 {
3777         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3778         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3779
3780         dev_info->pci_dev = pci_dev;
3781         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3782         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3783         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3784         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3785         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3786         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3787         dev_info->max_vfs = pci_dev->max_vfs;
3788         if (hw->mac.type == ixgbe_mac_82598EB)
3789                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3790         else
3791                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3792         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3793                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3794                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3795                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3796         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3797                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3798                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3799                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3800                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3801                                 DEV_TX_OFFLOAD_TCP_TSO;
3802
3803         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3804                 .rx_thresh = {
3805                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3806                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3807                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3808                 },
3809                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3810                 .rx_drop_en = 0,
3811         };
3812
3813         dev_info->default_txconf = (struct rte_eth_txconf) {
3814                 .tx_thresh = {
3815                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3816                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3817                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3818                 },
3819                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3820                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3821                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3822                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3823         };
3824
3825         dev_info->rx_desc_lim = rx_desc_lim;
3826         dev_info->tx_desc_lim = tx_desc_lim;
3827 }
3828
3829 static int
3830 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3831                    int *link_up, int wait_to_complete)
3832 {
3833         /**
3834          * for a quick link status checking, wait_to_compelet == 0,
3835          * skip PF link status checking
3836          */
3837         bool no_pflink_check = wait_to_complete == 0;
3838         struct ixgbe_mbx_info *mbx = &hw->mbx;
3839         struct ixgbe_mac_info *mac = &hw->mac;
3840         uint32_t links_reg, in_msg;
3841         int ret_val = 0;
3842
3843         /* If we were hit with a reset drop the link */
3844         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3845                 mac->get_link_status = true;
3846
3847         if (!mac->get_link_status)
3848                 goto out;
3849
3850         /* if link status is down no point in checking to see if pf is up */
3851         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3852         if (!(links_reg & IXGBE_LINKS_UP))
3853                 goto out;
3854
3855         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3856          * before the link status is correct
3857          */
3858         if (mac->type == ixgbe_mac_82599_vf) {
3859                 int i;
3860
3861                 for (i = 0; i < 5; i++) {
3862                         rte_delay_us(100);
3863                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3864
3865                         if (!(links_reg & IXGBE_LINKS_UP))
3866                                 goto out;
3867                 }
3868         }
3869
3870         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3871         case IXGBE_LINKS_SPEED_10G_82599:
3872                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3873                 if (hw->mac.type >= ixgbe_mac_X550) {
3874                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3875                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3876                 }
3877                 break;
3878         case IXGBE_LINKS_SPEED_1G_82599:
3879                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3880                 break;
3881         case IXGBE_LINKS_SPEED_100_82599:
3882                 *speed = IXGBE_LINK_SPEED_100_FULL;
3883                 if (hw->mac.type == ixgbe_mac_X550) {
3884                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3885                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3886                 }
3887                 break;
3888         case IXGBE_LINKS_SPEED_10_X550EM_A:
3889                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3890                 /* Since Reserved in older MAC's */
3891                 if (hw->mac.type >= ixgbe_mac_X550)
3892                         *speed = IXGBE_LINK_SPEED_10_FULL;
3893                 break;
3894         default:
3895                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3896         }
3897
3898         if (no_pflink_check) {
3899                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3900                         mac->get_link_status = true;
3901                 else
3902                         mac->get_link_status = false;
3903
3904                 goto out;
3905         }
3906         /* if the read failed it could just be a mailbox collision, best wait
3907          * until we are called again and don't report an error
3908          */
3909         if (mbx->ops.read(hw, &in_msg, 1, 0))
3910                 goto out;
3911
3912         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3913                 /* msg is not CTS and is NACK we must have lost CTS status */
3914                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3915                         ret_val = -1;
3916                 goto out;
3917         }
3918
3919         /* the pf is talking, if we timed out in the past we reinit */
3920         if (!mbx->timeout) {
3921                 ret_val = -1;
3922                 goto out;
3923         }
3924
3925         /* if we passed all the tests above then the link is up and we no
3926          * longer need to check for link
3927          */
3928         mac->get_link_status = false;
3929
3930 out:
3931         *link_up = !mac->get_link_status;
3932         return ret_val;
3933 }
3934
3935 /* return 0 means link status changed, -1 means not changed */
3936 static int
3937 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3938                             int wait_to_complete, int vf)
3939 {
3940         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3941         struct rte_eth_link link, old;
3942         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3943         struct ixgbe_interrupt *intr =
3944                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3945         int link_up;
3946         int diag;
3947         u32 speed = 0;
3948         int wait = 1;
3949         bool autoneg = false;
3950
3951         link.link_status = ETH_LINK_DOWN;
3952         link.link_speed = 0;
3953         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3954         link.link_autoneg = ETH_LINK_AUTONEG;
3955         memset(&old, 0, sizeof(old));
3956         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3957
3958         hw->mac.get_link_status = true;
3959
3960         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3961                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3962                 speed = hw->phy.autoneg_advertised;
3963                 if (!speed)
3964                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3965                 ixgbe_setup_link(hw, speed, true);
3966         }
3967
3968         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3969         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3970                 wait = 0;
3971
3972         if (vf)
3973                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3974         else
3975                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3976
3977         if (diag != 0) {
3978                 link.link_speed = ETH_SPEED_NUM_100M;
3979                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3980                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3981                 if (link.link_status == old.link_status)
3982                         return -1;
3983                 return 0;
3984         }
3985
3986         if (link_up == 0) {
3987                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3988                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3989                 if (link.link_status == old.link_status)
3990                         return -1;
3991                 return 0;
3992         }
3993         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3994         link.link_status = ETH_LINK_UP;
3995         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3996
3997         switch (link_speed) {
3998         default:
3999         case IXGBE_LINK_SPEED_UNKNOWN:
4000                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4001                 link.link_speed = ETH_SPEED_NUM_100M;
4002                 break;
4003
4004         case IXGBE_LINK_SPEED_100_FULL:
4005                 link.link_speed = ETH_SPEED_NUM_100M;
4006                 break;
4007
4008         case IXGBE_LINK_SPEED_1GB_FULL:
4009                 link.link_speed = ETH_SPEED_NUM_1G;
4010                 break;
4011
4012         case IXGBE_LINK_SPEED_2_5GB_FULL:
4013                 link.link_speed = ETH_SPEED_NUM_2_5G;
4014                 break;
4015
4016         case IXGBE_LINK_SPEED_5GB_FULL:
4017                 link.link_speed = ETH_SPEED_NUM_5G;
4018                 break;
4019
4020         case IXGBE_LINK_SPEED_10GB_FULL:
4021                 link.link_speed = ETH_SPEED_NUM_10G;
4022                 break;
4023         }
4024         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4025
4026         if (link.link_status == old.link_status)
4027                 return -1;
4028
4029         return 0;
4030 }
4031
4032 static int
4033 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4034 {
4035         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4036 }
4037
4038 static int
4039 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4040 {
4041         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4042 }
4043
4044 static void
4045 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4046 {
4047         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4048         uint32_t fctrl;
4049
4050         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4051         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4052         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4053 }
4054
4055 static void
4056 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4057 {
4058         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4059         uint32_t fctrl;
4060
4061         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4062         fctrl &= (~IXGBE_FCTRL_UPE);
4063         if (dev->data->all_multicast == 1)
4064                 fctrl |= IXGBE_FCTRL_MPE;
4065         else
4066                 fctrl &= (~IXGBE_FCTRL_MPE);
4067         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4068 }
4069
4070 static void
4071 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4072 {
4073         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4074         uint32_t fctrl;
4075
4076         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4077         fctrl |= IXGBE_FCTRL_MPE;
4078         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4079 }
4080
4081 static void
4082 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4083 {
4084         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4085         uint32_t fctrl;
4086
4087         if (dev->data->promiscuous == 1)
4088                 return; /* must remain in all_multicast mode */
4089
4090         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4091         fctrl &= (~IXGBE_FCTRL_MPE);
4092         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4093 }
4094
4095 /**
4096  * It clears the interrupt causes and enables the interrupt.
4097  * It will be called once only during nic initialized.
4098  *
4099  * @param dev
4100  *  Pointer to struct rte_eth_dev.
4101  * @param on
4102  *  Enable or Disable.
4103  *
4104  * @return
4105  *  - On success, zero.
4106  *  - On failure, a negative value.
4107  */
4108 static int
4109 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4110 {
4111         struct ixgbe_interrupt *intr =
4112                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4113
4114         ixgbe_dev_link_status_print(dev);
4115         if (on)
4116                 intr->mask |= IXGBE_EICR_LSC;
4117         else
4118                 intr->mask &= ~IXGBE_EICR_LSC;
4119
4120         return 0;
4121 }
4122
4123 /**
4124  * It clears the interrupt causes and enables the interrupt.
4125  * It will be called once only during nic initialized.
4126  *
4127  * @param dev
4128  *  Pointer to struct rte_eth_dev.
4129  *
4130  * @return
4131  *  - On success, zero.
4132  *  - On failure, a negative value.
4133  */
4134 static int
4135 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4136 {
4137         struct ixgbe_interrupt *intr =
4138                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4139
4140         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4141
4142         return 0;
4143 }
4144
4145 /**
4146  * It clears the interrupt causes and enables the interrupt.
4147  * It will be called once only during nic initialized.
4148  *
4149  * @param dev
4150  *  Pointer to struct rte_eth_dev.
4151  *
4152  * @return
4153  *  - On success, zero.
4154  *  - On failure, a negative value.
4155  */
4156 static int
4157 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4158 {
4159         struct ixgbe_interrupt *intr =
4160                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4161
4162         intr->mask |= IXGBE_EICR_LINKSEC;
4163
4164         return 0;
4165 }
4166
4167 /*
4168  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4169  *
4170  * @param dev
4171  *  Pointer to struct rte_eth_dev.
4172  *
4173  * @return
4174  *  - On success, zero.
4175  *  - On failure, a negative value.
4176  */
4177 static int
4178 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4179 {
4180         uint32_t eicr;
4181         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4182         struct ixgbe_interrupt *intr =
4183                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4184
4185         /* clear all cause mask */
4186         ixgbe_disable_intr(hw);
4187
4188         /* read-on-clear nic registers here */
4189         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4190         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4191
4192         intr->flags = 0;
4193
4194         /* set flag for async link update */
4195         if (eicr & IXGBE_EICR_LSC)
4196                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4197
4198         if (eicr & IXGBE_EICR_MAILBOX)
4199                 intr->flags |= IXGBE_FLAG_MAILBOX;
4200
4201         if (eicr & IXGBE_EICR_LINKSEC)
4202                 intr->flags |= IXGBE_FLAG_MACSEC;
4203
4204         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4205             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4206             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4207                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4208
4209         return 0;
4210 }
4211
4212 /**
4213  * It gets and then prints the link status.
4214  *
4215  * @param dev
4216  *  Pointer to struct rte_eth_dev.
4217  *
4218  * @return
4219  *  - On success, zero.
4220  *  - On failure, a negative value.
4221  */
4222 static void
4223 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4224 {
4225         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4226         struct rte_eth_link link;
4227
4228         memset(&link, 0, sizeof(link));
4229         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4230         if (link.link_status) {
4231                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4232                                         (int)(dev->data->port_id),
4233                                         (unsigned)link.link_speed,
4234                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4235                                         "full-duplex" : "half-duplex");
4236         } else {
4237                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4238                                 (int)(dev->data->port_id));
4239         }
4240         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4241                                 pci_dev->addr.domain,
4242                                 pci_dev->addr.bus,
4243                                 pci_dev->addr.devid,
4244                                 pci_dev->addr.function);
4245 }
4246
4247 /*
4248  * It executes link_update after knowing an interrupt occurred.
4249  *
4250  * @param dev
4251  *  Pointer to struct rte_eth_dev.
4252  *
4253  * @return
4254  *  - On success, zero.
4255  *  - On failure, a negative value.
4256  */
4257 static int
4258 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4259                            struct rte_intr_handle *intr_handle)
4260 {
4261         struct ixgbe_interrupt *intr =
4262                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4263         int64_t timeout;
4264         struct rte_eth_link link;
4265         struct ixgbe_hw *hw =
4266                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4267
4268         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4269
4270         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4271                 ixgbe_pf_mbx_process(dev);
4272                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4273         }
4274
4275         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4276                 ixgbe_handle_lasi(hw);
4277                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4278         }
4279
4280         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4281                 /* get the link status before link update, for predicting later */
4282                 memset(&link, 0, sizeof(link));
4283                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4284
4285                 ixgbe_dev_link_update(dev, 0);
4286
4287                 /* likely to up */
4288                 if (!link.link_status)
4289                         /* handle it 1 sec later, wait it being stable */
4290                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4291                 /* likely to down */
4292                 else
4293                         /* handle it 4 sec later, wait it being stable */
4294                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4295
4296                 ixgbe_dev_link_status_print(dev);
4297                 if (rte_eal_alarm_set(timeout * 1000,
4298                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4299                         PMD_DRV_LOG(ERR, "Error setting alarm");
4300                 else {
4301                         /* remember original mask */
4302                         intr->mask_original = intr->mask;
4303                         /* only disable lsc interrupt */
4304                         intr->mask &= ~IXGBE_EIMS_LSC;
4305                 }
4306         }
4307
4308         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4309         ixgbe_enable_intr(dev);
4310         rte_intr_enable(intr_handle);
4311
4312         return 0;
4313 }
4314
4315 /**
4316  * Interrupt handler which shall be registered for alarm callback for delayed
4317  * handling specific interrupt to wait for the stable nic state. As the
4318  * NIC interrupt state is not stable for ixgbe after link is just down,
4319  * it needs to wait 4 seconds to get the stable status.
4320  *
4321  * @param handle
4322  *  Pointer to interrupt handle.
4323  * @param param
4324  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4325  *
4326  * @return
4327  *  void
4328  */
4329 static void
4330 ixgbe_dev_interrupt_delayed_handler(void *param)
4331 {
4332         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4333         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4334         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4335         struct ixgbe_interrupt *intr =
4336                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4337         struct ixgbe_hw *hw =
4338                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4339         uint32_t eicr;
4340
4341         ixgbe_disable_intr(hw);
4342
4343         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4344         if (eicr & IXGBE_EICR_MAILBOX)
4345                 ixgbe_pf_mbx_process(dev);
4346
4347         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4348                 ixgbe_handle_lasi(hw);
4349                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4350         }
4351
4352         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4353                 ixgbe_dev_link_update(dev, 0);
4354                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4355                 ixgbe_dev_link_status_print(dev);
4356                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4357                                               NULL, NULL);
4358         }
4359
4360         if (intr->flags & IXGBE_FLAG_MACSEC) {
4361                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4362                                               NULL, NULL);
4363                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4364         }
4365
4366         /* restore original mask */
4367         intr->mask = intr->mask_original;
4368         intr->mask_original = 0;
4369
4370         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4371         ixgbe_enable_intr(dev);
4372         rte_intr_enable(intr_handle);
4373 }
4374
4375 /**
4376  * Interrupt handler triggered by NIC  for handling
4377  * specific interrupt.
4378  *
4379  * @param handle
4380  *  Pointer to interrupt handle.
4381  * @param param
4382  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4383  *
4384  * @return
4385  *  void
4386  */
4387 static void
4388 ixgbe_dev_interrupt_handler(void *param)
4389 {
4390         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4391
4392         ixgbe_dev_interrupt_get_status(dev);
4393         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4394 }
4395
4396 static int
4397 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4398 {
4399         struct ixgbe_hw *hw;
4400
4401         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4402         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4403 }
4404
4405 static int
4406 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4407 {
4408         struct ixgbe_hw *hw;
4409
4410         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4411         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4412 }
4413
4414 static int
4415 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4416 {
4417         struct ixgbe_hw *hw;
4418         uint32_t mflcn_reg;
4419         uint32_t fccfg_reg;
4420         int rx_pause;
4421         int tx_pause;
4422
4423         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4424
4425         fc_conf->pause_time = hw->fc.pause_time;
4426         fc_conf->high_water = hw->fc.high_water[0];
4427         fc_conf->low_water = hw->fc.low_water[0];
4428         fc_conf->send_xon = hw->fc.send_xon;
4429         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4430
4431         /*
4432          * Return rx_pause status according to actual setting of
4433          * MFLCN register.
4434          */
4435         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4436         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4437                 rx_pause = 1;
4438         else
4439                 rx_pause = 0;
4440
4441         /*
4442          * Return tx_pause status according to actual setting of
4443          * FCCFG register.
4444          */
4445         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4446         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4447                 tx_pause = 1;
4448         else
4449                 tx_pause = 0;
4450
4451         if (rx_pause && tx_pause)
4452                 fc_conf->mode = RTE_FC_FULL;
4453         else if (rx_pause)
4454                 fc_conf->mode = RTE_FC_RX_PAUSE;
4455         else if (tx_pause)
4456                 fc_conf->mode = RTE_FC_TX_PAUSE;
4457         else
4458                 fc_conf->mode = RTE_FC_NONE;
4459
4460         return 0;
4461 }
4462
4463 static int
4464 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4465 {
4466         struct ixgbe_hw *hw;
4467         int err;
4468         uint32_t rx_buf_size;
4469         uint32_t max_high_water;
4470         uint32_t mflcn;
4471         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4472                 ixgbe_fc_none,
4473                 ixgbe_fc_rx_pause,
4474                 ixgbe_fc_tx_pause,
4475                 ixgbe_fc_full
4476         };
4477
4478         PMD_INIT_FUNC_TRACE();
4479
4480         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4481         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4482         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4483
4484         /*
4485          * At least reserve one Ethernet frame for watermark
4486          * high_water/low_water in kilo bytes for ixgbe
4487          */
4488         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4489         if ((fc_conf->high_water > max_high_water) ||
4490                 (fc_conf->high_water < fc_conf->low_water)) {
4491                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4492                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4493                 return -EINVAL;
4494         }
4495
4496         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4497         hw->fc.pause_time     = fc_conf->pause_time;
4498         hw->fc.high_water[0]  = fc_conf->high_water;
4499         hw->fc.low_water[0]   = fc_conf->low_water;
4500         hw->fc.send_xon       = fc_conf->send_xon;
4501         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4502
4503         err = ixgbe_fc_enable(hw);
4504
4505         /* Not negotiated is not an error case */
4506         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4507
4508                 /* check if we want to forward MAC frames - driver doesn't have native
4509                  * capability to do that, so we'll write the registers ourselves */
4510
4511                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4512
4513                 /* set or clear MFLCN.PMCF bit depending on configuration */
4514                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4515                         mflcn |= IXGBE_MFLCN_PMCF;
4516                 else
4517                         mflcn &= ~IXGBE_MFLCN_PMCF;
4518
4519                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4520                 IXGBE_WRITE_FLUSH(hw);
4521
4522                 return 0;
4523         }
4524
4525         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4526         return -EIO;
4527 }
4528
4529 /**
4530  *  ixgbe_pfc_enable_generic - Enable flow control
4531  *  @hw: pointer to hardware structure
4532  *  @tc_num: traffic class number
4533  *  Enable flow control according to the current settings.
4534  */
4535 static int
4536 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4537 {
4538         int ret_val = 0;
4539         uint32_t mflcn_reg, fccfg_reg;
4540         uint32_t reg;
4541         uint32_t fcrtl, fcrth;
4542         uint8_t i;
4543         uint8_t nb_rx_en;
4544
4545         /* Validate the water mark configuration */
4546         if (!hw->fc.pause_time) {
4547                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4548                 goto out;
4549         }
4550
4551         /* Low water mark of zero causes XOFF floods */
4552         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4553                  /* High/Low water can not be 0 */
4554                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4555                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4556                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4557                         goto out;
4558                 }
4559
4560                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4561                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4562                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4563                         goto out;
4564                 }
4565         }
4566         /* Negotiate the fc mode to use */
4567         ixgbe_fc_autoneg(hw);
4568
4569         /* Disable any previous flow control settings */
4570         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4571         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4572
4573         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4574         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4575
4576         switch (hw->fc.current_mode) {
4577         case ixgbe_fc_none:
4578                 /*
4579                  * If the count of enabled RX Priority Flow control >1,
4580                  * and the TX pause can not be disabled
4581                  */
4582                 nb_rx_en = 0;
4583                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4584                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4585                         if (reg & IXGBE_FCRTH_FCEN)
4586                                 nb_rx_en++;
4587                 }
4588                 if (nb_rx_en > 1)
4589                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4590                 break;
4591         case ixgbe_fc_rx_pause:
4592                 /*
4593                  * Rx Flow control is enabled and Tx Flow control is
4594                  * disabled by software override. Since there really
4595                  * isn't a way to advertise that we are capable of RX
4596                  * Pause ONLY, we will advertise that we support both
4597                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4598                  * disable the adapter's ability to send PAUSE frames.
4599                  */
4600                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4601                 /*
4602                  * If the count of enabled RX Priority Flow control >1,
4603                  * and the TX pause can not be disabled
4604                  */
4605                 nb_rx_en = 0;
4606                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4607                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4608                         if (reg & IXGBE_FCRTH_FCEN)
4609                                 nb_rx_en++;
4610                 }
4611                 if (nb_rx_en > 1)
4612                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4613                 break;
4614         case ixgbe_fc_tx_pause:
4615                 /*
4616                  * Tx Flow control is enabled, and Rx Flow control is
4617                  * disabled by software override.
4618                  */
4619                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4620                 break;
4621         case ixgbe_fc_full:
4622                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4623                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4624                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4625                 break;
4626         default:
4627                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4628                 ret_val = IXGBE_ERR_CONFIG;
4629                 goto out;
4630         }
4631
4632         /* Set 802.3x based flow control settings. */
4633         mflcn_reg |= IXGBE_MFLCN_DPF;
4634         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4635         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4636
4637         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4638         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4639                 hw->fc.high_water[tc_num]) {
4640                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4641                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4642                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4643         } else {
4644                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4645                 /*
4646                  * In order to prevent Tx hangs when the internal Tx
4647                  * switch is enabled we must set the high water mark
4648                  * to the maximum FCRTH value.  This allows the Tx
4649                  * switch to function even under heavy Rx workloads.
4650                  */
4651                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4652         }
4653         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4654
4655         /* Configure pause time (2 TCs per register) */
4656         reg = hw->fc.pause_time * 0x00010001;
4657         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4658                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4659
4660         /* Configure flow control refresh threshold value */
4661         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4662
4663 out:
4664         return ret_val;
4665 }
4666
4667 static int
4668 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4669 {
4670         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4671         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4672
4673         if (hw->mac.type != ixgbe_mac_82598EB) {
4674                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4675         }
4676         return ret_val;
4677 }
4678
4679 static int
4680 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4681 {
4682         int err;
4683         uint32_t rx_buf_size;
4684         uint32_t max_high_water;
4685         uint8_t tc_num;
4686         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4687         struct ixgbe_hw *hw =
4688                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4689         struct ixgbe_dcb_config *dcb_config =
4690                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4691
4692         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4693                 ixgbe_fc_none,
4694                 ixgbe_fc_rx_pause,
4695                 ixgbe_fc_tx_pause,
4696                 ixgbe_fc_full
4697         };
4698
4699         PMD_INIT_FUNC_TRACE();
4700
4701         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4702         tc_num = map[pfc_conf->priority];
4703         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4704         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4705         /*
4706          * At least reserve one Ethernet frame for watermark
4707          * high_water/low_water in kilo bytes for ixgbe
4708          */
4709         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4710         if ((pfc_conf->fc.high_water > max_high_water) ||
4711             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4712                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4713                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4714                 return -EINVAL;
4715         }
4716
4717         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4718         hw->fc.pause_time = pfc_conf->fc.pause_time;
4719         hw->fc.send_xon = pfc_conf->fc.send_xon;
4720         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4721         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4722
4723         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4724
4725         /* Not negotiated is not an error case */
4726         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4727                 return 0;
4728
4729         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4730         return -EIO;
4731 }
4732
4733 static int
4734 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4735                           struct rte_eth_rss_reta_entry64 *reta_conf,
4736                           uint16_t reta_size)
4737 {
4738         uint16_t i, sp_reta_size;
4739         uint8_t j, mask;
4740         uint32_t reta, r;
4741         uint16_t idx, shift;
4742         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4743         uint32_t reta_reg;
4744
4745         PMD_INIT_FUNC_TRACE();
4746
4747         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4748                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4749                         "NIC.");
4750                 return -ENOTSUP;
4751         }
4752
4753         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4754         if (reta_size != sp_reta_size) {
4755                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4756                         "(%d) doesn't match the number hardware can supported "
4757                         "(%d)", reta_size, sp_reta_size);
4758                 return -EINVAL;
4759         }
4760
4761         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4762                 idx = i / RTE_RETA_GROUP_SIZE;
4763                 shift = i % RTE_RETA_GROUP_SIZE;
4764                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4765                                                 IXGBE_4_BIT_MASK);
4766                 if (!mask)
4767                         continue;
4768                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4769                 if (mask == IXGBE_4_BIT_MASK)
4770                         r = 0;
4771                 else
4772                         r = IXGBE_READ_REG(hw, reta_reg);
4773                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4774                         if (mask & (0x1 << j))
4775                                 reta |= reta_conf[idx].reta[shift + j] <<
4776                                                         (CHAR_BIT * j);
4777                         else
4778                                 reta |= r & (IXGBE_8_BIT_MASK <<
4779                                                 (CHAR_BIT * j));
4780                 }
4781                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4782         }
4783
4784         return 0;
4785 }
4786
4787 static int
4788 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4789                          struct rte_eth_rss_reta_entry64 *reta_conf,
4790                          uint16_t reta_size)
4791 {
4792         uint16_t i, sp_reta_size;
4793         uint8_t j, mask;
4794         uint32_t reta;
4795         uint16_t idx, shift;
4796         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4797         uint32_t reta_reg;
4798
4799         PMD_INIT_FUNC_TRACE();
4800         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4801         if (reta_size != sp_reta_size) {
4802                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4803                         "(%d) doesn't match the number hardware can supported "
4804                         "(%d)", reta_size, sp_reta_size);
4805                 return -EINVAL;
4806         }
4807
4808         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4809                 idx = i / RTE_RETA_GROUP_SIZE;
4810                 shift = i % RTE_RETA_GROUP_SIZE;
4811                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4812                                                 IXGBE_4_BIT_MASK);
4813                 if (!mask)
4814                         continue;
4815
4816                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4817                 reta = IXGBE_READ_REG(hw, reta_reg);
4818                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4819                         if (mask & (0x1 << j))
4820                                 reta_conf[idx].reta[shift + j] =
4821                                         ((reta >> (CHAR_BIT * j)) &
4822                                                 IXGBE_8_BIT_MASK);
4823                 }
4824         }
4825
4826         return 0;
4827 }
4828
4829 static int
4830 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4831                                 uint32_t index, uint32_t pool)
4832 {
4833         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4834         uint32_t enable_addr = 1;
4835
4836         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4837                              pool, enable_addr);
4838 }
4839
4840 static void
4841 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4842 {
4843         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4844
4845         ixgbe_clear_rar(hw, index);
4846 }
4847
4848 static void
4849 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4850 {
4851         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4852
4853         ixgbe_remove_rar(dev, 0);
4854
4855         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4856 }
4857
4858 static bool
4859 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4860 {
4861         if (strcmp(dev->device->driver->name, drv->driver.name))
4862                 return false;
4863
4864         return true;
4865 }
4866
4867 bool
4868 is_ixgbe_supported(struct rte_eth_dev *dev)
4869 {
4870         return is_device_supported(dev, &rte_ixgbe_pmd);
4871 }
4872
4873 static int
4874 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4875 {
4876         uint32_t hlreg0;
4877         uint32_t maxfrs;
4878         struct ixgbe_hw *hw;
4879         struct rte_eth_dev_info dev_info;
4880         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4881         struct rte_eth_dev_data *dev_data = dev->data;
4882
4883         ixgbe_dev_info_get(dev, &dev_info);
4884
4885         /* check that mtu is within the allowed range */
4886         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4887                 return -EINVAL;
4888
4889         /* If device is started, refuse mtu that requires the support of
4890          * scattered packets when this feature has not been enabled before.
4891          */
4892         if (dev_data->dev_started && !dev_data->scattered_rx &&
4893             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4894              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4895                 PMD_INIT_LOG(ERR, "Stop port first.");
4896                 return -EINVAL;
4897         }
4898
4899         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4900         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4901
4902         /* switch to jumbo mode if needed */
4903         if (frame_size > ETHER_MAX_LEN) {
4904                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4905                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4906         } else {
4907                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4908                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4909         }
4910         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4911
4912         /* update max frame size */
4913         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4914
4915         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4916         maxfrs &= 0x0000FFFF;
4917         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4918         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4919
4920         return 0;
4921 }
4922
4923 /*
4924  * Virtual Function operations
4925  */
4926 static void
4927 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4928 {
4929         PMD_INIT_FUNC_TRACE();
4930
4931         /* Clear interrupt mask to stop from interrupts being generated */
4932         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4933
4934         IXGBE_WRITE_FLUSH(hw);
4935 }
4936
4937 static void
4938 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4939 {
4940         PMD_INIT_FUNC_TRACE();
4941
4942         /* VF enable interrupt autoclean */
4943         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4944         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4945         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4946
4947         IXGBE_WRITE_FLUSH(hw);
4948 }
4949
4950 static int
4951 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4952 {
4953         struct rte_eth_conf *conf = &dev->data->dev_conf;
4954         struct ixgbe_adapter *adapter =
4955                         (struct ixgbe_adapter *)dev->data->dev_private;
4956
4957         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4958                      dev->data->port_id);
4959
4960         /*
4961          * VF has no ability to enable/disable HW CRC
4962          * Keep the persistent behavior the same as Host PF
4963          */
4964 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4965         if (!conf->rxmode.hw_strip_crc) {
4966                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4967                 conf->rxmode.hw_strip_crc = 1;
4968         }
4969 #else
4970         if (conf->rxmode.hw_strip_crc) {
4971                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4972                 conf->rxmode.hw_strip_crc = 0;
4973         }
4974 #endif
4975
4976         /*
4977          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4978          * allocation or vector Rx preconditions we will reset it.
4979          */
4980         adapter->rx_bulk_alloc_allowed = true;
4981         adapter->rx_vec_allowed = true;
4982
4983         return 0;
4984 }
4985
4986 static int
4987 ixgbevf_dev_start(struct rte_eth_dev *dev)
4988 {
4989         struct ixgbe_hw *hw =
4990                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4991         uint32_t intr_vector = 0;
4992         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4993         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4994
4995         int err, mask = 0;
4996
4997         PMD_INIT_FUNC_TRACE();
4998
4999         hw->mac.ops.reset_hw(hw);
5000         hw->mac.get_link_status = true;
5001
5002         /* negotiate mailbox API version to use with the PF. */
5003         ixgbevf_negotiate_api(hw);
5004
5005         ixgbevf_dev_tx_init(dev);
5006
5007         /* This can fail when allocating mbufs for descriptor rings */
5008         err = ixgbevf_dev_rx_init(dev);
5009         if (err) {
5010                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5011                 ixgbe_dev_clear_queues(dev);
5012                 return err;
5013         }
5014
5015         /* Set vfta */
5016         ixgbevf_set_vfta_all(dev, 1);
5017
5018         /* Set HW strip */
5019         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5020                 ETH_VLAN_EXTEND_MASK;
5021         err = ixgbevf_vlan_offload_set(dev, mask);
5022         if (err) {
5023                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5024                 ixgbe_dev_clear_queues(dev);
5025                 return err;
5026         }
5027
5028         ixgbevf_dev_rxtx_start(dev);
5029
5030         /* check and configure queue intr-vector mapping */
5031         if (dev->data->dev_conf.intr_conf.rxq != 0) {
5032                 /* According to datasheet, only vector 0/1/2 can be used,
5033                  * now only one vector is used for Rx queue
5034                  */
5035                 intr_vector = 1;
5036                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5037                         return -1;
5038         }
5039
5040         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5041                 intr_handle->intr_vec =
5042                         rte_zmalloc("intr_vec",
5043                                     dev->data->nb_rx_queues * sizeof(int), 0);
5044                 if (intr_handle->intr_vec == NULL) {
5045                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5046                                      " intr_vec", dev->data->nb_rx_queues);
5047                         return -ENOMEM;
5048                 }
5049         }
5050         ixgbevf_configure_msix(dev);
5051
5052         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5053          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5054          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5055          * is not cleared, it will fail when following rte_intr_enable( ) tries
5056          * to map Rx queue interrupt to other VFIO vectors.
5057          * So clear uio/vfio intr/evevnfd first to avoid failure.
5058          */
5059         rte_intr_disable(intr_handle);
5060
5061         rte_intr_enable(intr_handle);
5062
5063         /* Re-enable interrupt for VF */
5064         ixgbevf_intr_enable(hw);
5065
5066         return 0;
5067 }
5068
5069 static void
5070 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5071 {
5072         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5073         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5074         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5075
5076         PMD_INIT_FUNC_TRACE();
5077
5078         ixgbevf_intr_disable(hw);
5079
5080         hw->adapter_stopped = 1;
5081         ixgbe_stop_adapter(hw);
5082
5083         /*
5084           * Clear what we set, but we still keep shadow_vfta to
5085           * restore after device starts
5086           */
5087         ixgbevf_set_vfta_all(dev, 0);
5088
5089         /* Clear stored conf */
5090         dev->data->scattered_rx = 0;
5091
5092         ixgbe_dev_clear_queues(dev);
5093
5094         /* Clean datapath event and queue/vec mapping */
5095         rte_intr_efd_disable(intr_handle);
5096         if (intr_handle->intr_vec != NULL) {
5097                 rte_free(intr_handle->intr_vec);
5098                 intr_handle->intr_vec = NULL;
5099         }
5100 }
5101
5102 static void
5103 ixgbevf_dev_close(struct rte_eth_dev *dev)
5104 {
5105         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5106
5107         PMD_INIT_FUNC_TRACE();
5108
5109         ixgbe_reset_hw(hw);
5110
5111         ixgbevf_dev_stop(dev);
5112
5113         ixgbe_dev_free_queues(dev);
5114
5115         /**
5116          * Remove the VF MAC address ro ensure
5117          * that the VF traffic goes to the PF
5118          * after stop, close and detach of the VF
5119          **/
5120         ixgbevf_remove_mac_addr(dev, 0);
5121 }
5122
5123 /*
5124  * Reset VF device
5125  */
5126 static int
5127 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5128 {
5129         int ret;
5130
5131         ret = eth_ixgbevf_dev_uninit(dev);
5132         if (ret)
5133                 return ret;
5134
5135         ret = eth_ixgbevf_dev_init(dev);
5136
5137         return ret;
5138 }
5139
5140 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5141 {
5142         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5143         struct ixgbe_vfta *shadow_vfta =
5144                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5145         int i = 0, j = 0, vfta = 0, mask = 1;
5146
5147         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5148                 vfta = shadow_vfta->vfta[i];
5149                 if (vfta) {
5150                         mask = 1;
5151                         for (j = 0; j < 32; j++) {
5152                                 if (vfta & mask)
5153                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5154                                                        on, false);
5155                                 mask <<= 1;
5156                         }
5157                 }
5158         }
5159
5160 }
5161
5162 static int
5163 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5164 {
5165         struct ixgbe_hw *hw =
5166                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5167         struct ixgbe_vfta *shadow_vfta =
5168                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5169         uint32_t vid_idx = 0;
5170         uint32_t vid_bit = 0;
5171         int ret = 0;
5172
5173         PMD_INIT_FUNC_TRACE();
5174
5175         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5176         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5177         if (ret) {
5178                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5179                 return ret;
5180         }
5181         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5182         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5183
5184         /* Save what we set and retore it after device reset */
5185         if (on)
5186                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5187         else
5188                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5189
5190         return 0;
5191 }
5192
5193 static void
5194 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5195 {
5196         struct ixgbe_hw *hw =
5197                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5198         uint32_t ctrl;
5199
5200         PMD_INIT_FUNC_TRACE();
5201
5202         if (queue >= hw->mac.max_rx_queues)
5203                 return;
5204
5205         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5206         if (on)
5207                 ctrl |= IXGBE_RXDCTL_VME;
5208         else
5209                 ctrl &= ~IXGBE_RXDCTL_VME;
5210         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5211
5212         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5213 }
5214
5215 static int
5216 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5217 {
5218         struct ixgbe_hw *hw =
5219                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5220         uint16_t i;
5221         int on = 0;
5222
5223         /* VF function only support hw strip feature, others are not support */
5224         if (mask & ETH_VLAN_STRIP_MASK) {
5225                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5226
5227                 for (i = 0; i < hw->mac.max_rx_queues; i++)
5228                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5229         }
5230
5231         return 0;
5232 }
5233
5234 int
5235 ixgbe_vt_check(struct ixgbe_hw *hw)
5236 {
5237         uint32_t reg_val;
5238
5239         /* if Virtualization Technology is enabled */
5240         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5241         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5242                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5243                 return -1;
5244         }
5245
5246         return 0;
5247 }
5248
5249 static uint32_t
5250 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5251 {
5252         uint32_t vector = 0;
5253
5254         switch (hw->mac.mc_filter_type) {
5255         case 0:   /* use bits [47:36] of the address */
5256                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5257                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5258                 break;
5259         case 1:   /* use bits [46:35] of the address */
5260                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5261                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5262                 break;
5263         case 2:   /* use bits [45:34] of the address */
5264                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5265                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5266                 break;
5267         case 3:   /* use bits [43:32] of the address */
5268                 vector = ((uc_addr->addr_bytes[4]) |
5269                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5270                 break;
5271         default:  /* Invalid mc_filter_type */
5272                 break;
5273         }
5274
5275         /* vector can only be 12-bits or boundary will be exceeded */
5276         vector &= 0xFFF;
5277         return vector;
5278 }
5279
5280 static int
5281 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5282                         uint8_t on)
5283 {
5284         uint32_t vector;
5285         uint32_t uta_idx;
5286         uint32_t reg_val;
5287         uint32_t uta_shift;
5288         uint32_t rc;
5289         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5290         const uint32_t ixgbe_uta_bit_shift = 5;
5291         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5292         const uint32_t bit1 = 0x1;
5293
5294         struct ixgbe_hw *hw =
5295                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5296         struct ixgbe_uta_info *uta_info =
5297                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5298
5299         /* The UTA table only exists on 82599 hardware and newer */
5300         if (hw->mac.type < ixgbe_mac_82599EB)
5301                 return -ENOTSUP;
5302
5303         vector = ixgbe_uta_vector(hw, mac_addr);
5304         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5305         uta_shift = vector & ixgbe_uta_bit_mask;
5306
5307         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5308         if (rc == on)
5309                 return 0;
5310
5311         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5312         if (on) {
5313                 uta_info->uta_in_use++;
5314                 reg_val |= (bit1 << uta_shift);
5315                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5316         } else {
5317                 uta_info->uta_in_use--;
5318                 reg_val &= ~(bit1 << uta_shift);
5319                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5320         }
5321
5322         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5323
5324         if (uta_info->uta_in_use > 0)
5325                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5326                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5327         else
5328                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5329
5330         return 0;
5331 }
5332
5333 static int
5334 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5335 {
5336         int i;
5337         struct ixgbe_hw *hw =
5338                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5339         struct ixgbe_uta_info *uta_info =
5340                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5341
5342         /* The UTA table only exists on 82599 hardware and newer */
5343         if (hw->mac.type < ixgbe_mac_82599EB)
5344                 return -ENOTSUP;
5345
5346         if (on) {
5347                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5348                         uta_info->uta_shadow[i] = ~0;
5349                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5350                 }
5351         } else {
5352                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5353                         uta_info->uta_shadow[i] = 0;
5354                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5355                 }
5356         }
5357         return 0;
5358
5359 }
5360
5361 uint32_t
5362 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5363 {
5364         uint32_t new_val = orig_val;
5365
5366         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5367                 new_val |= IXGBE_VMOLR_AUPE;
5368         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5369                 new_val |= IXGBE_VMOLR_ROMPE;
5370         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5371                 new_val |= IXGBE_VMOLR_ROPE;
5372         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5373                 new_val |= IXGBE_VMOLR_BAM;
5374         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5375                 new_val |= IXGBE_VMOLR_MPE;
5376
5377         return new_val;
5378 }
5379
5380 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5381 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5382 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5383 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5384 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5385         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5386         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5387
5388 static int
5389 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5390                       struct rte_eth_mirror_conf *mirror_conf,
5391                       uint8_t rule_id, uint8_t on)
5392 {
5393         uint32_t mr_ctl, vlvf;
5394         uint32_t mp_lsb = 0;
5395         uint32_t mv_msb = 0;
5396         uint32_t mv_lsb = 0;
5397         uint32_t mp_msb = 0;
5398         uint8_t i = 0;
5399         int reg_index = 0;
5400         uint64_t vlan_mask = 0;
5401
5402         const uint8_t pool_mask_offset = 32;
5403         const uint8_t vlan_mask_offset = 32;
5404         const uint8_t dst_pool_offset = 8;
5405         const uint8_t rule_mr_offset  = 4;
5406         const uint8_t mirror_rule_mask = 0x0F;
5407
5408         struct ixgbe_mirror_info *mr_info =
5409                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5410         struct ixgbe_hw *hw =
5411                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5412         uint8_t mirror_type = 0;
5413
5414         if (ixgbe_vt_check(hw) < 0)
5415                 return -ENOTSUP;
5416
5417         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5418                 return -EINVAL;
5419
5420         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5421                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5422                             mirror_conf->rule_type);
5423                 return -EINVAL;
5424         }
5425
5426         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5427                 mirror_type |= IXGBE_MRCTL_VLME;
5428                 /* Check if vlan id is valid and find conresponding VLAN ID
5429                  * index in VLVF
5430                  */
5431                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5432                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5433                                 /* search vlan id related pool vlan filter
5434                                  * index
5435                                  */
5436                                 reg_index = ixgbe_find_vlvf_slot(
5437                                                 hw,
5438                                                 mirror_conf->vlan.vlan_id[i],
5439                                                 false);
5440                                 if (reg_index < 0)
5441                                         return -EINVAL;
5442                                 vlvf = IXGBE_READ_REG(hw,
5443                                                       IXGBE_VLVF(reg_index));
5444                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5445                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5446                                       mirror_conf->vlan.vlan_id[i]))
5447                                         vlan_mask |= (1ULL << reg_index);
5448                                 else
5449                                         return -EINVAL;
5450                         }
5451                 }
5452
5453                 if (on) {
5454                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5455                         mv_msb = vlan_mask >> vlan_mask_offset;
5456
5457                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5458                                                 mirror_conf->vlan.vlan_mask;
5459                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5460                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5461                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5462                                                 mirror_conf->vlan.vlan_id[i];
5463                         }
5464                 } else {
5465                         mv_lsb = 0;
5466                         mv_msb = 0;
5467                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5468                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5469                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5470                 }
5471         }
5472
5473         /**
5474          * if enable pool mirror, write related pool mask register,if disable
5475          * pool mirror, clear PFMRVM register
5476          */
5477         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5478                 mirror_type |= IXGBE_MRCTL_VPME;
5479                 if (on) {
5480                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5481                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5482                         mr_info->mr_conf[rule_id].pool_mask =
5483                                         mirror_conf->pool_mask;
5484
5485                 } else {
5486                         mp_lsb = 0;
5487                         mp_msb = 0;
5488                         mr_info->mr_conf[rule_id].pool_mask = 0;
5489                 }
5490         }
5491         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5492                 mirror_type |= IXGBE_MRCTL_UPME;
5493         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5494                 mirror_type |= IXGBE_MRCTL_DPME;
5495
5496         /* read  mirror control register and recalculate it */
5497         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5498
5499         if (on) {
5500                 mr_ctl |= mirror_type;
5501                 mr_ctl &= mirror_rule_mask;
5502                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5503         } else {
5504                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5505         }
5506
5507         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5508         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5509
5510         /* write mirrror control  register */
5511         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5512
5513         /* write pool mirrror control  register */
5514         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5515                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5516                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5517                                 mp_msb);
5518         }
5519         /* write VLAN mirrror control  register */
5520         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5521                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5522                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5523                                 mv_msb);
5524         }
5525
5526         return 0;
5527 }
5528
5529 static int
5530 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5531 {
5532         int mr_ctl = 0;
5533         uint32_t lsb_val = 0;
5534         uint32_t msb_val = 0;
5535         const uint8_t rule_mr_offset = 4;
5536
5537         struct ixgbe_hw *hw =
5538                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5539         struct ixgbe_mirror_info *mr_info =
5540                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5541
5542         if (ixgbe_vt_check(hw) < 0)
5543                 return -ENOTSUP;
5544
5545         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5546                 return -EINVAL;
5547
5548         memset(&mr_info->mr_conf[rule_id], 0,
5549                sizeof(struct rte_eth_mirror_conf));
5550
5551         /* clear PFVMCTL register */
5552         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5553
5554         /* clear pool mask register */
5555         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5556         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5557
5558         /* clear vlan mask register */
5559         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5560         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5561
5562         return 0;
5563 }
5564
5565 static int
5566 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5567 {
5568         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5569         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5570         uint32_t mask;
5571         struct ixgbe_hw *hw =
5572                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5573         uint32_t vec = IXGBE_MISC_VEC_ID;
5574
5575         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5576         if (rte_intr_allow_others(intr_handle))
5577                 vec = IXGBE_RX_VEC_START;
5578         mask |= (1 << vec);
5579         RTE_SET_USED(queue_id);
5580         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5581
5582         rte_intr_enable(intr_handle);
5583
5584         return 0;
5585 }
5586
5587 static int
5588 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5589 {
5590         uint32_t mask;
5591         struct ixgbe_hw *hw =
5592                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5593         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5594         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5595         uint32_t vec = IXGBE_MISC_VEC_ID;
5596
5597         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5598         if (rte_intr_allow_others(intr_handle))
5599                 vec = IXGBE_RX_VEC_START;
5600         mask &= ~(1 << vec);
5601         RTE_SET_USED(queue_id);
5602         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5603
5604         return 0;
5605 }
5606
5607 static int
5608 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5609 {
5610         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5611         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5612         uint32_t mask;
5613         struct ixgbe_hw *hw =
5614                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5615         struct ixgbe_interrupt *intr =
5616                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5617
5618         if (queue_id < 16) {
5619                 ixgbe_disable_intr(hw);
5620                 intr->mask |= (1 << queue_id);
5621                 ixgbe_enable_intr(dev);
5622         } else if (queue_id < 32) {
5623                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5624                 mask &= (1 << queue_id);
5625                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5626         } else if (queue_id < 64) {
5627                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5628                 mask &= (1 << (queue_id - 32));
5629                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5630         }
5631         rte_intr_enable(intr_handle);
5632
5633         return 0;
5634 }
5635
5636 static int
5637 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5638 {
5639         uint32_t mask;
5640         struct ixgbe_hw *hw =
5641                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5642         struct ixgbe_interrupt *intr =
5643                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5644
5645         if (queue_id < 16) {
5646                 ixgbe_disable_intr(hw);
5647                 intr->mask &= ~(1 << queue_id);
5648                 ixgbe_enable_intr(dev);
5649         } else if (queue_id < 32) {
5650                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5651                 mask &= ~(1 << queue_id);
5652                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5653         } else if (queue_id < 64) {
5654                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5655                 mask &= ~(1 << (queue_id - 32));
5656                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5657         }
5658
5659         return 0;
5660 }
5661
5662 static void
5663 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5664                      uint8_t queue, uint8_t msix_vector)
5665 {
5666         uint32_t tmp, idx;
5667
5668         if (direction == -1) {
5669                 /* other causes */
5670                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5671                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5672                 tmp &= ~0xFF;
5673                 tmp |= msix_vector;
5674                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5675         } else {
5676                 /* rx or tx cause */
5677                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5678                 idx = ((16 * (queue & 1)) + (8 * direction));
5679                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5680                 tmp &= ~(0xFF << idx);
5681                 tmp |= (msix_vector << idx);
5682                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5683         }
5684 }
5685
5686 /**
5687  * set the IVAR registers, mapping interrupt causes to vectors
5688  * @param hw
5689  *  pointer to ixgbe_hw struct
5690  * @direction
5691  *  0 for Rx, 1 for Tx, -1 for other causes
5692  * @queue
5693  *  queue to map the corresponding interrupt to
5694  * @msix_vector
5695  *  the vector to map to the corresponding queue
5696  */
5697 static void
5698 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5699                    uint8_t queue, uint8_t msix_vector)
5700 {
5701         uint32_t tmp, idx;
5702
5703         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5704         if (hw->mac.type == ixgbe_mac_82598EB) {
5705                 if (direction == -1)
5706                         direction = 0;
5707                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5708                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5709                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5710                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5711                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5712         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5713                         (hw->mac.type == ixgbe_mac_X540) ||
5714                         (hw->mac.type == ixgbe_mac_X550)) {
5715                 if (direction == -1) {
5716                         /* other causes */
5717                         idx = ((queue & 1) * 8);
5718                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5719                         tmp &= ~(0xFF << idx);
5720                         tmp |= (msix_vector << idx);
5721                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5722                 } else {
5723                         /* rx or tx causes */
5724                         idx = ((16 * (queue & 1)) + (8 * direction));
5725                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5726                         tmp &= ~(0xFF << idx);
5727                         tmp |= (msix_vector << idx);
5728                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5729                 }
5730         }
5731 }
5732
5733 static void
5734 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5735 {
5736         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5737         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5738         struct ixgbe_hw *hw =
5739                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5740         uint32_t q_idx;
5741         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5742         uint32_t base = IXGBE_MISC_VEC_ID;
5743
5744         /* Configure VF other cause ivar */
5745         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5746
5747         /* won't configure msix register if no mapping is done
5748          * between intr vector and event fd.
5749          */
5750         if (!rte_intr_dp_is_en(intr_handle))
5751                 return;
5752
5753         if (rte_intr_allow_others(intr_handle)) {
5754                 base = IXGBE_RX_VEC_START;
5755                 vector_idx = IXGBE_RX_VEC_START;
5756         }
5757
5758         /* Configure all RX queues of VF */
5759         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5760                 /* Force all queue use vector 0,
5761                  * as IXGBE_VF_MAXMSIVECOTR = 1
5762                  */
5763                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5764                 intr_handle->intr_vec[q_idx] = vector_idx;
5765                 if (vector_idx < base + intr_handle->nb_efd - 1)
5766                         vector_idx++;
5767         }
5768 }
5769
5770 /**
5771  * Sets up the hardware to properly generate MSI-X interrupts
5772  * @hw
5773  *  board private structure
5774  */
5775 static void
5776 ixgbe_configure_msix(struct rte_eth_dev *dev)
5777 {
5778         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5779         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5780         struct ixgbe_hw *hw =
5781                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5782         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5783         uint32_t vec = IXGBE_MISC_VEC_ID;
5784         uint32_t mask;
5785         uint32_t gpie;
5786
5787         /* won't configure msix register if no mapping is done
5788          * between intr vector and event fd
5789          */
5790         if (!rte_intr_dp_is_en(intr_handle))
5791                 return;
5792
5793         if (rte_intr_allow_others(intr_handle))
5794                 vec = base = IXGBE_RX_VEC_START;
5795
5796         /* setup GPIE for MSI-x mode */
5797         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5798         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5799                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5800         /* auto clearing and auto setting corresponding bits in EIMS
5801          * when MSI-X interrupt is triggered
5802          */
5803         if (hw->mac.type == ixgbe_mac_82598EB) {
5804                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5805         } else {
5806                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5807                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5808         }
5809         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5810
5811         /* Populate the IVAR table and set the ITR values to the
5812          * corresponding register.
5813          */
5814         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5815              queue_id++) {
5816                 /* by default, 1:1 mapping */
5817                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5818                 intr_handle->intr_vec[queue_id] = vec;
5819                 if (vec < base + intr_handle->nb_efd - 1)
5820                         vec++;
5821         }
5822
5823         switch (hw->mac.type) {
5824         case ixgbe_mac_82598EB:
5825                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5826                                    IXGBE_MISC_VEC_ID);
5827                 break;
5828         case ixgbe_mac_82599EB:
5829         case ixgbe_mac_X540:
5830         case ixgbe_mac_X550:
5831                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5832                 break;
5833         default:
5834                 break;
5835         }
5836         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5837                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5838
5839         /* set up to autoclear timer, and the vectors */
5840         mask = IXGBE_EIMS_ENABLE_MASK;
5841         mask &= ~(IXGBE_EIMS_OTHER |
5842                   IXGBE_EIMS_MAILBOX |
5843                   IXGBE_EIMS_LSC);
5844
5845         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5846 }
5847
5848 int
5849 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5850                            uint16_t queue_idx, uint16_t tx_rate)
5851 {
5852         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5853         uint32_t rf_dec, rf_int;
5854         uint32_t bcnrc_val;
5855         uint16_t link_speed = dev->data->dev_link.link_speed;
5856
5857         if (queue_idx >= hw->mac.max_tx_queues)
5858                 return -EINVAL;
5859
5860         if (tx_rate != 0) {
5861                 /* Calculate the rate factor values to set */
5862                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5863                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5864                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5865
5866                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5867                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5868                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5869                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5870         } else {
5871                 bcnrc_val = 0;
5872         }
5873
5874         /*
5875          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5876          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5877          * set as 0x4.
5878          */
5879         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5880                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5881                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5882                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5883                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5884         else
5885                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5886                         IXGBE_MMW_SIZE_DEFAULT);
5887
5888         /* Set RTTBCNRC of queue X */
5889         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5890         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5891         IXGBE_WRITE_FLUSH(hw);
5892
5893         return 0;
5894 }
5895
5896 static int
5897 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5898                      __attribute__((unused)) uint32_t index,
5899                      __attribute__((unused)) uint32_t pool)
5900 {
5901         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5902         int diag;
5903
5904         /*
5905          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5906          * operation. Trap this case to avoid exhausting the [very limited]
5907          * set of PF resources used to store VF MAC addresses.
5908          */
5909         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5910                 return -1;
5911         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5912         if (diag != 0)
5913                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5914                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5915                             mac_addr->addr_bytes[0],
5916                             mac_addr->addr_bytes[1],
5917                             mac_addr->addr_bytes[2],
5918                             mac_addr->addr_bytes[3],
5919                             mac_addr->addr_bytes[4],
5920                             mac_addr->addr_bytes[5],
5921                             diag);
5922         return diag;
5923 }
5924
5925 static void
5926 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5927 {
5928         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5929         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5930         struct ether_addr *mac_addr;
5931         uint32_t i;
5932         int diag;
5933
5934         /*
5935          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5936          * not support the deletion of a given MAC address.
5937          * Instead, it imposes to delete all MAC addresses, then to add again
5938          * all MAC addresses with the exception of the one to be deleted.
5939          */
5940         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5941
5942         /*
5943          * Add again all MAC addresses, with the exception of the deleted one
5944          * and of the permanent MAC address.
5945          */
5946         for (i = 0, mac_addr = dev->data->mac_addrs;
5947              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5948                 /* Skip the deleted MAC address */
5949                 if (i == index)
5950                         continue;
5951                 /* Skip NULL MAC addresses */
5952                 if (is_zero_ether_addr(mac_addr))
5953                         continue;
5954                 /* Skip the permanent MAC address */
5955                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5956                         continue;
5957                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5958                 if (diag != 0)
5959                         PMD_DRV_LOG(ERR,
5960                                     "Adding again MAC address "
5961                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5962                                     "diag=%d",
5963                                     mac_addr->addr_bytes[0],
5964                                     mac_addr->addr_bytes[1],
5965                                     mac_addr->addr_bytes[2],
5966                                     mac_addr->addr_bytes[3],
5967                                     mac_addr->addr_bytes[4],
5968                                     mac_addr->addr_bytes[5],
5969                                     diag);
5970         }
5971 }
5972
5973 static void
5974 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5975 {
5976         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5977
5978         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5979 }
5980
5981 int
5982 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5983                         struct rte_eth_syn_filter *filter,
5984                         bool add)
5985 {
5986         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5987         struct ixgbe_filter_info *filter_info =
5988                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5989         uint32_t syn_info;
5990         uint32_t synqf;
5991
5992         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5993                 return -EINVAL;
5994
5995         syn_info = filter_info->syn_info;
5996
5997         if (add) {
5998                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5999                         return -EINVAL;
6000                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6001                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6002
6003                 if (filter->hig_pri)
6004                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6005                 else
6006                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6007         } else {
6008                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6009                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6010                         return -ENOENT;
6011                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6012         }
6013
6014         filter_info->syn_info = synqf;
6015         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6016         IXGBE_WRITE_FLUSH(hw);
6017         return 0;
6018 }
6019
6020 static int
6021 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6022                         struct rte_eth_syn_filter *filter)
6023 {
6024         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6025         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6026
6027         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6028                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6029                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6030                 return 0;
6031         }
6032         return -ENOENT;
6033 }
6034
6035 static int
6036 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6037                         enum rte_filter_op filter_op,
6038                         void *arg)
6039 {
6040         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6041         int ret;
6042
6043         MAC_TYPE_FILTER_SUP(hw->mac.type);
6044
6045         if (filter_op == RTE_ETH_FILTER_NOP)
6046                 return 0;
6047
6048         if (arg == NULL) {
6049                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6050                             filter_op);
6051                 return -EINVAL;
6052         }
6053
6054         switch (filter_op) {
6055         case RTE_ETH_FILTER_ADD:
6056                 ret = ixgbe_syn_filter_set(dev,
6057                                 (struct rte_eth_syn_filter *)arg,
6058                                 TRUE);
6059                 break;
6060         case RTE_ETH_FILTER_DELETE:
6061                 ret = ixgbe_syn_filter_set(dev,
6062                                 (struct rte_eth_syn_filter *)arg,
6063                                 FALSE);
6064                 break;
6065         case RTE_ETH_FILTER_GET:
6066                 ret = ixgbe_syn_filter_get(dev,
6067                                 (struct rte_eth_syn_filter *)arg);
6068                 break;
6069         default:
6070                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6071                 ret = -EINVAL;
6072                 break;
6073         }
6074
6075         return ret;
6076 }
6077
6078
6079 static inline enum ixgbe_5tuple_protocol
6080 convert_protocol_type(uint8_t protocol_value)
6081 {
6082         if (protocol_value == IPPROTO_TCP)
6083                 return IXGBE_FILTER_PROTOCOL_TCP;
6084         else if (protocol_value == IPPROTO_UDP)
6085                 return IXGBE_FILTER_PROTOCOL_UDP;
6086         else if (protocol_value == IPPROTO_SCTP)
6087                 return IXGBE_FILTER_PROTOCOL_SCTP;
6088         else
6089                 return IXGBE_FILTER_PROTOCOL_NONE;
6090 }
6091
6092 /* inject a 5-tuple filter to HW */
6093 static inline void
6094 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6095                            struct ixgbe_5tuple_filter *filter)
6096 {
6097         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6098         int i;
6099         uint32_t ftqf, sdpqf;
6100         uint32_t l34timir = 0;
6101         uint8_t mask = 0xff;
6102
6103         i = filter->index;
6104
6105         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6106                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6107         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6108
6109         ftqf = (uint32_t)(filter->filter_info.proto &
6110                 IXGBE_FTQF_PROTOCOL_MASK);
6111         ftqf |= (uint32_t)((filter->filter_info.priority &
6112                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6113         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6114                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6115         if (filter->filter_info.dst_ip_mask == 0)
6116                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6117         if (filter->filter_info.src_port_mask == 0)
6118                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6119         if (filter->filter_info.dst_port_mask == 0)
6120                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6121         if (filter->filter_info.proto_mask == 0)
6122                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6123         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6124         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6125         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6126
6127         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6128         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6129         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6130         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6131
6132         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6133         l34timir |= (uint32_t)(filter->queue <<
6134                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6135         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6136 }
6137
6138 /*
6139  * add a 5tuple filter
6140  *
6141  * @param
6142  * dev: Pointer to struct rte_eth_dev.
6143  * index: the index the filter allocates.
6144  * filter: ponter to the filter that will be added.
6145  * rx_queue: the queue id the filter assigned to.
6146  *
6147  * @return
6148  *    - On success, zero.
6149  *    - On failure, a negative value.
6150  */
6151 static int
6152 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6153                         struct ixgbe_5tuple_filter *filter)
6154 {
6155         struct ixgbe_filter_info *filter_info =
6156                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6157         int i, idx, shift;
6158
6159         /*
6160          * look for an unused 5tuple filter index,
6161          * and insert the filter to list.
6162          */
6163         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6164                 idx = i / (sizeof(uint32_t) * NBBY);
6165                 shift = i % (sizeof(uint32_t) * NBBY);
6166                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6167                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6168                         filter->index = i;
6169                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6170                                           filter,
6171                                           entries);
6172                         break;
6173                 }
6174         }
6175         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6176                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6177                 return -ENOSYS;
6178         }
6179
6180         ixgbe_inject_5tuple_filter(dev, filter);
6181
6182         return 0;
6183 }
6184
6185 /*
6186  * remove a 5tuple filter
6187  *
6188  * @param
6189  * dev: Pointer to struct rte_eth_dev.
6190  * filter: the pointer of the filter will be removed.
6191  */
6192 static void
6193 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6194                         struct ixgbe_5tuple_filter *filter)
6195 {
6196         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6197         struct ixgbe_filter_info *filter_info =
6198                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6199         uint16_t index = filter->index;
6200
6201         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6202                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6203         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6204         rte_free(filter);
6205
6206         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6207         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6208         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6209         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6210         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6211 }
6212
6213 static int
6214 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6215 {
6216         struct ixgbe_hw *hw;
6217         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6218         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6219
6220         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6221
6222         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6223                 return -EINVAL;
6224
6225         /* refuse mtu that requires the support of scattered packets when this
6226          * feature has not been enabled before.
6227          */
6228         if (!rx_conf->enable_scatter &&
6229             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6230              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6231                 return -EINVAL;
6232
6233         /*
6234          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6235          * request of the version 2.0 of the mailbox API.
6236          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6237          * of the mailbox API.
6238          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6239          * prior to 3.11.33 which contains the following change:
6240          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6241          */
6242         ixgbevf_rlpml_set_vf(hw, max_frame);
6243
6244         /* update max frame size */
6245         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6246         return 0;
6247 }
6248
6249 static inline struct ixgbe_5tuple_filter *
6250 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6251                         struct ixgbe_5tuple_filter_info *key)
6252 {
6253         struct ixgbe_5tuple_filter *it;
6254
6255         TAILQ_FOREACH(it, filter_list, entries) {
6256                 if (memcmp(key, &it->filter_info,
6257                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6258                         return it;
6259                 }
6260         }
6261         return NULL;
6262 }
6263
6264 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6265 static inline int
6266 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6267                         struct ixgbe_5tuple_filter_info *filter_info)
6268 {
6269         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6270                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6271                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6272                 return -EINVAL;
6273
6274         switch (filter->dst_ip_mask) {
6275         case UINT32_MAX:
6276                 filter_info->dst_ip_mask = 0;
6277                 filter_info->dst_ip = filter->dst_ip;
6278                 break;
6279         case 0:
6280                 filter_info->dst_ip_mask = 1;
6281                 break;
6282         default:
6283                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6284                 return -EINVAL;
6285         }
6286
6287         switch (filter->src_ip_mask) {
6288         case UINT32_MAX:
6289                 filter_info->src_ip_mask = 0;
6290                 filter_info->src_ip = filter->src_ip;
6291                 break;
6292         case 0:
6293                 filter_info->src_ip_mask = 1;
6294                 break;
6295         default:
6296                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6297                 return -EINVAL;
6298         }
6299
6300         switch (filter->dst_port_mask) {
6301         case UINT16_MAX:
6302                 filter_info->dst_port_mask = 0;
6303                 filter_info->dst_port = filter->dst_port;
6304                 break;
6305         case 0:
6306                 filter_info->dst_port_mask = 1;
6307                 break;
6308         default:
6309                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6310                 return -EINVAL;
6311         }
6312
6313         switch (filter->src_port_mask) {
6314         case UINT16_MAX:
6315                 filter_info->src_port_mask = 0;
6316                 filter_info->src_port = filter->src_port;
6317                 break;
6318         case 0:
6319                 filter_info->src_port_mask = 1;
6320                 break;
6321         default:
6322                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6323                 return -EINVAL;
6324         }
6325
6326         switch (filter->proto_mask) {
6327         case UINT8_MAX:
6328                 filter_info->proto_mask = 0;
6329                 filter_info->proto =
6330                         convert_protocol_type(filter->proto);
6331                 break;
6332         case 0:
6333                 filter_info->proto_mask = 1;
6334                 break;
6335         default:
6336                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6337                 return -EINVAL;
6338         }
6339
6340         filter_info->priority = (uint8_t)filter->priority;
6341         return 0;
6342 }
6343
6344 /*
6345  * add or delete a ntuple filter
6346  *
6347  * @param
6348  * dev: Pointer to struct rte_eth_dev.
6349  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6350  * add: if true, add filter, if false, remove filter
6351  *
6352  * @return
6353  *    - On success, zero.
6354  *    - On failure, a negative value.
6355  */
6356 int
6357 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6358                         struct rte_eth_ntuple_filter *ntuple_filter,
6359                         bool add)
6360 {
6361         struct ixgbe_filter_info *filter_info =
6362                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6363         struct ixgbe_5tuple_filter_info filter_5tuple;
6364         struct ixgbe_5tuple_filter *filter;
6365         int ret;
6366
6367         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6368                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6369                 return -EINVAL;
6370         }
6371
6372         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6373         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6374         if (ret < 0)
6375                 return ret;
6376
6377         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6378                                          &filter_5tuple);
6379         if (filter != NULL && add) {
6380                 PMD_DRV_LOG(ERR, "filter exists.");
6381                 return -EEXIST;
6382         }
6383         if (filter == NULL && !add) {
6384                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6385                 return -ENOENT;
6386         }
6387
6388         if (add) {
6389                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6390                                 sizeof(struct ixgbe_5tuple_filter), 0);
6391                 if (filter == NULL)
6392                         return -ENOMEM;
6393                 rte_memcpy(&filter->filter_info,
6394                                  &filter_5tuple,
6395                                  sizeof(struct ixgbe_5tuple_filter_info));
6396                 filter->queue = ntuple_filter->queue;
6397                 ret = ixgbe_add_5tuple_filter(dev, filter);
6398                 if (ret < 0) {
6399                         rte_free(filter);
6400                         return ret;
6401                 }
6402         } else
6403                 ixgbe_remove_5tuple_filter(dev, filter);
6404
6405         return 0;
6406 }
6407
6408 /*
6409  * get a ntuple filter
6410  *
6411  * @param
6412  * dev: Pointer to struct rte_eth_dev.
6413  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6414  *
6415  * @return
6416  *    - On success, zero.
6417  *    - On failure, a negative value.
6418  */
6419 static int
6420 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6421                         struct rte_eth_ntuple_filter *ntuple_filter)
6422 {
6423         struct ixgbe_filter_info *filter_info =
6424                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6425         struct ixgbe_5tuple_filter_info filter_5tuple;
6426         struct ixgbe_5tuple_filter *filter;
6427         int ret;
6428
6429         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6430                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6431                 return -EINVAL;
6432         }
6433
6434         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6435         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6436         if (ret < 0)
6437                 return ret;
6438
6439         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6440                                          &filter_5tuple);
6441         if (filter == NULL) {
6442                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6443                 return -ENOENT;
6444         }
6445         ntuple_filter->queue = filter->queue;
6446         return 0;
6447 }
6448
6449 /*
6450  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6451  * @dev: pointer to rte_eth_dev structure
6452  * @filter_op:operation will be taken.
6453  * @arg: a pointer to specific structure corresponding to the filter_op
6454  *
6455  * @return
6456  *    - On success, zero.
6457  *    - On failure, a negative value.
6458  */
6459 static int
6460 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6461                                 enum rte_filter_op filter_op,
6462                                 void *arg)
6463 {
6464         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6465         int ret;
6466
6467         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6468
6469         if (filter_op == RTE_ETH_FILTER_NOP)
6470                 return 0;
6471
6472         if (arg == NULL) {
6473                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6474                             filter_op);
6475                 return -EINVAL;
6476         }
6477
6478         switch (filter_op) {
6479         case RTE_ETH_FILTER_ADD:
6480                 ret = ixgbe_add_del_ntuple_filter(dev,
6481                         (struct rte_eth_ntuple_filter *)arg,
6482                         TRUE);
6483                 break;
6484         case RTE_ETH_FILTER_DELETE:
6485                 ret = ixgbe_add_del_ntuple_filter(dev,
6486                         (struct rte_eth_ntuple_filter *)arg,
6487                         FALSE);
6488                 break;
6489         case RTE_ETH_FILTER_GET:
6490                 ret = ixgbe_get_ntuple_filter(dev,
6491                         (struct rte_eth_ntuple_filter *)arg);
6492                 break;
6493         default:
6494                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6495                 ret = -EINVAL;
6496                 break;
6497         }
6498         return ret;
6499 }
6500
6501 int
6502 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6503                         struct rte_eth_ethertype_filter *filter,
6504                         bool add)
6505 {
6506         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6507         struct ixgbe_filter_info *filter_info =
6508                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6509         uint32_t etqf = 0;
6510         uint32_t etqs = 0;
6511         int ret;
6512         struct ixgbe_ethertype_filter ethertype_filter;
6513
6514         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6515                 return -EINVAL;
6516
6517         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6518                 filter->ether_type == ETHER_TYPE_IPv6) {
6519                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6520                         " ethertype filter.", filter->ether_type);
6521                 return -EINVAL;
6522         }
6523
6524         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6525                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6526                 return -EINVAL;
6527         }
6528         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6529                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6530                 return -EINVAL;
6531         }
6532
6533         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6534         if (ret >= 0 && add) {
6535                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6536                             filter->ether_type);
6537                 return -EEXIST;
6538         }
6539         if (ret < 0 && !add) {
6540                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6541                             filter->ether_type);
6542                 return -ENOENT;
6543         }
6544
6545         if (add) {
6546                 etqf = IXGBE_ETQF_FILTER_EN;
6547                 etqf |= (uint32_t)filter->ether_type;
6548                 etqs |= (uint32_t)((filter->queue <<
6549                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6550                                     IXGBE_ETQS_RX_QUEUE);
6551                 etqs |= IXGBE_ETQS_QUEUE_EN;
6552
6553                 ethertype_filter.ethertype = filter->ether_type;
6554                 ethertype_filter.etqf = etqf;
6555                 ethertype_filter.etqs = etqs;
6556                 ethertype_filter.conf = FALSE;
6557                 ret = ixgbe_ethertype_filter_insert(filter_info,
6558                                                     &ethertype_filter);
6559                 if (ret < 0) {
6560                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6561                         return -ENOSPC;
6562                 }
6563         } else {
6564                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6565                 if (ret < 0)
6566                         return -ENOSYS;
6567         }
6568         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6569         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6570         IXGBE_WRITE_FLUSH(hw);
6571
6572         return 0;
6573 }
6574
6575 static int
6576 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6577                         struct rte_eth_ethertype_filter *filter)
6578 {
6579         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6580         struct ixgbe_filter_info *filter_info =
6581                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6582         uint32_t etqf, etqs;
6583         int ret;
6584
6585         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6586         if (ret < 0) {
6587                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6588                             filter->ether_type);
6589                 return -ENOENT;
6590         }
6591
6592         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6593         if (etqf & IXGBE_ETQF_FILTER_EN) {
6594                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6595                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6596                 filter->flags = 0;
6597                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6598                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6599                 return 0;
6600         }
6601         return -ENOENT;
6602 }
6603
6604 /*
6605  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6606  * @dev: pointer to rte_eth_dev structure
6607  * @filter_op:operation will be taken.
6608  * @arg: a pointer to specific structure corresponding to the filter_op
6609  */
6610 static int
6611 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6612                                 enum rte_filter_op filter_op,
6613                                 void *arg)
6614 {
6615         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6616         int ret;
6617
6618         MAC_TYPE_FILTER_SUP(hw->mac.type);
6619
6620         if (filter_op == RTE_ETH_FILTER_NOP)
6621                 return 0;
6622
6623         if (arg == NULL) {
6624                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6625                             filter_op);
6626                 return -EINVAL;
6627         }
6628
6629         switch (filter_op) {
6630         case RTE_ETH_FILTER_ADD:
6631                 ret = ixgbe_add_del_ethertype_filter(dev,
6632                         (struct rte_eth_ethertype_filter *)arg,
6633                         TRUE);
6634                 break;
6635         case RTE_ETH_FILTER_DELETE:
6636                 ret = ixgbe_add_del_ethertype_filter(dev,
6637                         (struct rte_eth_ethertype_filter *)arg,
6638                         FALSE);
6639                 break;
6640         case RTE_ETH_FILTER_GET:
6641                 ret = ixgbe_get_ethertype_filter(dev,
6642                         (struct rte_eth_ethertype_filter *)arg);
6643                 break;
6644         default:
6645                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6646                 ret = -EINVAL;
6647                 break;
6648         }
6649         return ret;
6650 }
6651
6652 static int
6653 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6654                      enum rte_filter_type filter_type,
6655                      enum rte_filter_op filter_op,
6656                      void *arg)
6657 {
6658         int ret = 0;
6659
6660         switch (filter_type) {
6661         case RTE_ETH_FILTER_NTUPLE:
6662                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6663                 break;
6664         case RTE_ETH_FILTER_ETHERTYPE:
6665                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6666                 break;
6667         case RTE_ETH_FILTER_SYN:
6668                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6669                 break;
6670         case RTE_ETH_FILTER_FDIR:
6671                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6672                 break;
6673         case RTE_ETH_FILTER_L2_TUNNEL:
6674                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6675                 break;
6676         case RTE_ETH_FILTER_GENERIC:
6677                 if (filter_op != RTE_ETH_FILTER_GET)
6678                         return -EINVAL;
6679                 *(const void **)arg = &ixgbe_flow_ops;
6680                 break;
6681         default:
6682                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6683                                                         filter_type);
6684                 ret = -EINVAL;
6685                 break;
6686         }
6687
6688         return ret;
6689 }
6690
6691 static u8 *
6692 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6693                         u8 **mc_addr_ptr, u32 *vmdq)
6694 {
6695         u8 *mc_addr;
6696
6697         *vmdq = 0;
6698         mc_addr = *mc_addr_ptr;
6699         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6700         return mc_addr;
6701 }
6702
6703 static int
6704 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6705                           struct ether_addr *mc_addr_set,
6706                           uint32_t nb_mc_addr)
6707 {
6708         struct ixgbe_hw *hw;
6709         u8 *mc_addr_list;
6710
6711         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6712         mc_addr_list = (u8 *)mc_addr_set;
6713         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6714                                          ixgbe_dev_addr_list_itr, TRUE);
6715 }
6716
6717 static uint64_t
6718 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6719 {
6720         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6721         uint64_t systime_cycles;
6722
6723         switch (hw->mac.type) {
6724         case ixgbe_mac_X550:
6725         case ixgbe_mac_X550EM_x:
6726         case ixgbe_mac_X550EM_a:
6727                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6728                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6729                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6730                                 * NSEC_PER_SEC;
6731                 break;
6732         default:
6733                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6734                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6735                                 << 32;
6736         }
6737
6738         return systime_cycles;
6739 }
6740
6741 static uint64_t
6742 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6743 {
6744         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6745         uint64_t rx_tstamp_cycles;
6746
6747         switch (hw->mac.type) {
6748         case ixgbe_mac_X550:
6749         case ixgbe_mac_X550EM_x:
6750         case ixgbe_mac_X550EM_a:
6751                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6752                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6753                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6754                                 * NSEC_PER_SEC;
6755                 break;
6756         default:
6757                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6758                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6759                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6760                                 << 32;
6761         }
6762
6763         return rx_tstamp_cycles;
6764 }
6765
6766 static uint64_t
6767 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6768 {
6769         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6770         uint64_t tx_tstamp_cycles;
6771
6772         switch (hw->mac.type) {
6773         case ixgbe_mac_X550:
6774         case ixgbe_mac_X550EM_x:
6775         case ixgbe_mac_X550EM_a:
6776                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6777                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6778                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6779                                 * NSEC_PER_SEC;
6780                 break;
6781         default:
6782                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6783                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6784                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6785                                 << 32;
6786         }
6787
6788         return tx_tstamp_cycles;
6789 }
6790
6791 static void
6792 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6793 {
6794         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6795         struct ixgbe_adapter *adapter =
6796                 (struct ixgbe_adapter *)dev->data->dev_private;
6797         struct rte_eth_link link;
6798         uint32_t incval = 0;
6799         uint32_t shift = 0;
6800
6801         /* Get current link speed. */
6802         memset(&link, 0, sizeof(link));
6803         ixgbe_dev_link_update(dev, 1);
6804         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6805
6806         switch (link.link_speed) {
6807         case ETH_SPEED_NUM_100M:
6808                 incval = IXGBE_INCVAL_100;
6809                 shift = IXGBE_INCVAL_SHIFT_100;
6810                 break;
6811         case ETH_SPEED_NUM_1G:
6812                 incval = IXGBE_INCVAL_1GB;
6813                 shift = IXGBE_INCVAL_SHIFT_1GB;
6814                 break;
6815         case ETH_SPEED_NUM_10G:
6816         default:
6817                 incval = IXGBE_INCVAL_10GB;
6818                 shift = IXGBE_INCVAL_SHIFT_10GB;
6819                 break;
6820         }
6821
6822         switch (hw->mac.type) {
6823         case ixgbe_mac_X550:
6824         case ixgbe_mac_X550EM_x:
6825         case ixgbe_mac_X550EM_a:
6826                 /* Independent of link speed. */
6827                 incval = 1;
6828                 /* Cycles read will be interpreted as ns. */
6829                 shift = 0;
6830                 /* Fall-through */
6831         case ixgbe_mac_X540:
6832                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6833                 break;
6834         case ixgbe_mac_82599EB:
6835                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6836                 shift -= IXGBE_INCVAL_SHIFT_82599;
6837                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6838                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6839                 break;
6840         default:
6841                 /* Not supported. */
6842                 return;
6843         }
6844
6845         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6846         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6847         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6848
6849         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6850         adapter->systime_tc.cc_shift = shift;
6851         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6852
6853         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6854         adapter->rx_tstamp_tc.cc_shift = shift;
6855         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6856
6857         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6858         adapter->tx_tstamp_tc.cc_shift = shift;
6859         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6860 }
6861
6862 static int
6863 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6864 {
6865         struct ixgbe_adapter *adapter =
6866                         (struct ixgbe_adapter *)dev->data->dev_private;
6867
6868         adapter->systime_tc.nsec += delta;
6869         adapter->rx_tstamp_tc.nsec += delta;
6870         adapter->tx_tstamp_tc.nsec += delta;
6871
6872         return 0;
6873 }
6874
6875 static int
6876 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6877 {
6878         uint64_t ns;
6879         struct ixgbe_adapter *adapter =
6880                         (struct ixgbe_adapter *)dev->data->dev_private;
6881
6882         ns = rte_timespec_to_ns(ts);
6883         /* Set the timecounters to a new value. */
6884         adapter->systime_tc.nsec = ns;
6885         adapter->rx_tstamp_tc.nsec = ns;
6886         adapter->tx_tstamp_tc.nsec = ns;
6887
6888         return 0;
6889 }
6890
6891 static int
6892 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6893 {
6894         uint64_t ns, systime_cycles;
6895         struct ixgbe_adapter *adapter =
6896                         (struct ixgbe_adapter *)dev->data->dev_private;
6897
6898         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6899         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6900         *ts = rte_ns_to_timespec(ns);
6901
6902         return 0;
6903 }
6904
6905 static int
6906 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6907 {
6908         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6909         uint32_t tsync_ctl;
6910         uint32_t tsauxc;
6911
6912         /* Stop the timesync system time. */
6913         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6914         /* Reset the timesync system time value. */
6915         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6916         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6917
6918         /* Enable system time for platforms where it isn't on by default. */
6919         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6920         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6921         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6922
6923         ixgbe_start_timecounters(dev);
6924
6925         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6926         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6927                         (ETHER_TYPE_1588 |
6928                          IXGBE_ETQF_FILTER_EN |
6929                          IXGBE_ETQF_1588));
6930
6931         /* Enable timestamping of received PTP packets. */
6932         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6933         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6934         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6935
6936         /* Enable timestamping of transmitted PTP packets. */
6937         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6938         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6939         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6940
6941         IXGBE_WRITE_FLUSH(hw);
6942
6943         return 0;
6944 }
6945
6946 static int
6947 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6948 {
6949         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6950         uint32_t tsync_ctl;
6951
6952         /* Disable timestamping of transmitted PTP packets. */
6953         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6954         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6955         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6956
6957         /* Disable timestamping of received PTP packets. */
6958         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6959         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6960         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6961
6962         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6963         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6964
6965         /* Stop incrementating the System Time registers. */
6966         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6967
6968         return 0;
6969 }
6970
6971 static int
6972 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6973                                  struct timespec *timestamp,
6974                                  uint32_t flags __rte_unused)
6975 {
6976         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6977         struct ixgbe_adapter *adapter =
6978                 (struct ixgbe_adapter *)dev->data->dev_private;
6979         uint32_t tsync_rxctl;
6980         uint64_t rx_tstamp_cycles;
6981         uint64_t ns;
6982
6983         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6984         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6985                 return -EINVAL;
6986
6987         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6988         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6989         *timestamp = rte_ns_to_timespec(ns);
6990
6991         return  0;
6992 }
6993
6994 static int
6995 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6996                                  struct timespec *timestamp)
6997 {
6998         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6999         struct ixgbe_adapter *adapter =
7000                 (struct ixgbe_adapter *)dev->data->dev_private;
7001         uint32_t tsync_txctl;
7002         uint64_t tx_tstamp_cycles;
7003         uint64_t ns;
7004
7005         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7006         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7007                 return -EINVAL;
7008
7009         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7010         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7011         *timestamp = rte_ns_to_timespec(ns);
7012
7013         return 0;
7014 }
7015
7016 static int
7017 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7018 {
7019         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7020         int count = 0;
7021         int g_ind = 0;
7022         const struct reg_info *reg_group;
7023         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7024                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7025
7026         while ((reg_group = reg_set[g_ind++]))
7027                 count += ixgbe_regs_group_count(reg_group);
7028
7029         return count;
7030 }
7031
7032 static int
7033 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7034 {
7035         int count = 0;
7036         int g_ind = 0;
7037         const struct reg_info *reg_group;
7038
7039         while ((reg_group = ixgbevf_regs[g_ind++]))
7040                 count += ixgbe_regs_group_count(reg_group);
7041
7042         return count;
7043 }
7044
7045 static int
7046 ixgbe_get_regs(struct rte_eth_dev *dev,
7047               struct rte_dev_reg_info *regs)
7048 {
7049         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7050         uint32_t *data = regs->data;
7051         int g_ind = 0;
7052         int count = 0;
7053         const struct reg_info *reg_group;
7054         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7055                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7056
7057         if (data == NULL) {
7058                 regs->length = ixgbe_get_reg_length(dev);
7059                 regs->width = sizeof(uint32_t);
7060                 return 0;
7061         }
7062
7063         /* Support only full register dump */
7064         if ((regs->length == 0) ||
7065             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7066                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7067                         hw->device_id;
7068                 while ((reg_group = reg_set[g_ind++]))
7069                         count += ixgbe_read_regs_group(dev, &data[count],
7070                                 reg_group);
7071                 return 0;
7072         }
7073
7074         return -ENOTSUP;
7075 }
7076
7077 static int
7078 ixgbevf_get_regs(struct rte_eth_dev *dev,
7079                 struct rte_dev_reg_info *regs)
7080 {
7081         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7082         uint32_t *data = regs->data;
7083         int g_ind = 0;
7084         int count = 0;
7085         const struct reg_info *reg_group;
7086
7087         if (data == NULL) {
7088                 regs->length = ixgbevf_get_reg_length(dev);
7089                 regs->width = sizeof(uint32_t);
7090                 return 0;
7091         }
7092
7093         /* Support only full register dump */
7094         if ((regs->length == 0) ||
7095             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7096                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7097                         hw->device_id;
7098                 while ((reg_group = ixgbevf_regs[g_ind++]))
7099                         count += ixgbe_read_regs_group(dev, &data[count],
7100                                                       reg_group);
7101                 return 0;
7102         }
7103
7104         return -ENOTSUP;
7105 }
7106
7107 static int
7108 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7109 {
7110         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7111
7112         /* Return unit is byte count */
7113         return hw->eeprom.word_size * 2;
7114 }
7115
7116 static int
7117 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7118                 struct rte_dev_eeprom_info *in_eeprom)
7119 {
7120         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7121         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7122         uint16_t *data = in_eeprom->data;
7123         int first, length;
7124
7125         first = in_eeprom->offset >> 1;
7126         length = in_eeprom->length >> 1;
7127         if ((first > hw->eeprom.word_size) ||
7128             ((first + length) > hw->eeprom.word_size))
7129                 return -EINVAL;
7130
7131         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7132
7133         return eeprom->ops.read_buffer(hw, first, length, data);
7134 }
7135
7136 static int
7137 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7138                 struct rte_dev_eeprom_info *in_eeprom)
7139 {
7140         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7141         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7142         uint16_t *data = in_eeprom->data;
7143         int first, length;
7144
7145         first = in_eeprom->offset >> 1;
7146         length = in_eeprom->length >> 1;
7147         if ((first > hw->eeprom.word_size) ||
7148             ((first + length) > hw->eeprom.word_size))
7149                 return -EINVAL;
7150
7151         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7152
7153         return eeprom->ops.write_buffer(hw,  first, length, data);
7154 }
7155
7156 uint16_t
7157 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7158         switch (mac_type) {
7159         case ixgbe_mac_X550:
7160         case ixgbe_mac_X550EM_x:
7161         case ixgbe_mac_X550EM_a:
7162                 return ETH_RSS_RETA_SIZE_512;
7163         case ixgbe_mac_X550_vf:
7164         case ixgbe_mac_X550EM_x_vf:
7165         case ixgbe_mac_X550EM_a_vf:
7166                 return ETH_RSS_RETA_SIZE_64;
7167         default:
7168                 return ETH_RSS_RETA_SIZE_128;
7169         }
7170 }
7171
7172 uint32_t
7173 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7174         switch (mac_type) {
7175         case ixgbe_mac_X550:
7176         case ixgbe_mac_X550EM_x:
7177         case ixgbe_mac_X550EM_a:
7178                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7179                         return IXGBE_RETA(reta_idx >> 2);
7180                 else
7181                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7182         case ixgbe_mac_X550_vf:
7183         case ixgbe_mac_X550EM_x_vf:
7184         case ixgbe_mac_X550EM_a_vf:
7185                 return IXGBE_VFRETA(reta_idx >> 2);
7186         default:
7187                 return IXGBE_RETA(reta_idx >> 2);
7188         }
7189 }
7190
7191 uint32_t
7192 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7193         switch (mac_type) {
7194         case ixgbe_mac_X550_vf:
7195         case ixgbe_mac_X550EM_x_vf:
7196         case ixgbe_mac_X550EM_a_vf:
7197                 return IXGBE_VFMRQC;
7198         default:
7199                 return IXGBE_MRQC;
7200         }
7201 }
7202
7203 uint32_t
7204 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7205         switch (mac_type) {
7206         case ixgbe_mac_X550_vf:
7207         case ixgbe_mac_X550EM_x_vf:
7208         case ixgbe_mac_X550EM_a_vf:
7209                 return IXGBE_VFRSSRK(i);
7210         default:
7211                 return IXGBE_RSSRK(i);
7212         }
7213 }
7214
7215 bool
7216 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7217         switch (mac_type) {
7218         case ixgbe_mac_82599_vf:
7219         case ixgbe_mac_X540_vf:
7220                 return 0;
7221         default:
7222                 return 1;
7223         }
7224 }
7225
7226 static int
7227 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7228                         struct rte_eth_dcb_info *dcb_info)
7229 {
7230         struct ixgbe_dcb_config *dcb_config =
7231                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7232         struct ixgbe_dcb_tc_config *tc;
7233         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7234         uint8_t nb_tcs;
7235         uint8_t i, j;
7236
7237         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7238                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7239         else
7240                 dcb_info->nb_tcs = 1;
7241
7242         tc_queue = &dcb_info->tc_queue;
7243         nb_tcs = dcb_info->nb_tcs;
7244
7245         if (dcb_config->vt_mode) { /* vt is enabled*/
7246                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7247                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7248                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7249                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7250                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7251                         for (j = 0; j < nb_tcs; j++) {
7252                                 tc_queue->tc_rxq[0][j].base = j;
7253                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7254                                 tc_queue->tc_txq[0][j].base = j;
7255                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7256                         }
7257                 } else {
7258                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7259                                 for (j = 0; j < nb_tcs; j++) {
7260                                         tc_queue->tc_rxq[i][j].base =
7261                                                 i * nb_tcs + j;
7262                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7263                                         tc_queue->tc_txq[i][j].base =
7264                                                 i * nb_tcs + j;
7265                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7266                                 }
7267                         }
7268                 }
7269         } else { /* vt is disabled*/
7270                 struct rte_eth_dcb_rx_conf *rx_conf =
7271                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7272                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7273                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7274                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7275                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7276                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7277                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7278                         }
7279                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7280                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7281                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7282                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7283                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7284                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7285                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7286                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7287                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7288                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7289                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7290                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7291                         }
7292                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7293                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7294                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7295                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7296                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7297                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7298                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7299                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7300                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7301                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7302                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7303                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7304                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7305                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7306                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7307                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7308                 }
7309         }
7310         for (i = 0; i < dcb_info->nb_tcs; i++) {
7311                 tc = &dcb_config->tc_config[i];
7312                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7313         }
7314         return 0;
7315 }
7316
7317 /* Update e-tag ether type */
7318 static int
7319 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7320                             uint16_t ether_type)
7321 {
7322         uint32_t etag_etype;
7323
7324         if (hw->mac.type != ixgbe_mac_X550 &&
7325             hw->mac.type != ixgbe_mac_X550EM_x &&
7326             hw->mac.type != ixgbe_mac_X550EM_a) {
7327                 return -ENOTSUP;
7328         }
7329
7330         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7331         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7332         etag_etype |= ether_type;
7333         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7334         IXGBE_WRITE_FLUSH(hw);
7335
7336         return 0;
7337 }
7338
7339 /* Config l2 tunnel ether type */
7340 static int
7341 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7342                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7343 {
7344         int ret = 0;
7345         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7346         struct ixgbe_l2_tn_info *l2_tn_info =
7347                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7348
7349         if (l2_tunnel == NULL)
7350                 return -EINVAL;
7351
7352         switch (l2_tunnel->l2_tunnel_type) {
7353         case RTE_L2_TUNNEL_TYPE_E_TAG:
7354                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7355                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7356                 break;
7357         default:
7358                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7359                 ret = -EINVAL;
7360                 break;
7361         }
7362
7363         return ret;
7364 }
7365
7366 /* Enable e-tag tunnel */
7367 static int
7368 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7369 {
7370         uint32_t etag_etype;
7371
7372         if (hw->mac.type != ixgbe_mac_X550 &&
7373             hw->mac.type != ixgbe_mac_X550EM_x &&
7374             hw->mac.type != ixgbe_mac_X550EM_a) {
7375                 return -ENOTSUP;
7376         }
7377
7378         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7379         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7380         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7381         IXGBE_WRITE_FLUSH(hw);
7382
7383         return 0;
7384 }
7385
7386 /* Enable l2 tunnel */
7387 static int
7388 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7389                            enum rte_eth_tunnel_type l2_tunnel_type)
7390 {
7391         int ret = 0;
7392         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7393         struct ixgbe_l2_tn_info *l2_tn_info =
7394                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7395
7396         switch (l2_tunnel_type) {
7397         case RTE_L2_TUNNEL_TYPE_E_TAG:
7398                 l2_tn_info->e_tag_en = TRUE;
7399                 ret = ixgbe_e_tag_enable(hw);
7400                 break;
7401         default:
7402                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7403                 ret = -EINVAL;
7404                 break;
7405         }
7406
7407         return ret;
7408 }
7409
7410 /* Disable e-tag tunnel */
7411 static int
7412 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7413 {
7414         uint32_t etag_etype;
7415
7416         if (hw->mac.type != ixgbe_mac_X550 &&
7417             hw->mac.type != ixgbe_mac_X550EM_x &&
7418             hw->mac.type != ixgbe_mac_X550EM_a) {
7419                 return -ENOTSUP;
7420         }
7421
7422         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7423         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7424         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7425         IXGBE_WRITE_FLUSH(hw);
7426
7427         return 0;
7428 }
7429
7430 /* Disable l2 tunnel */
7431 static int
7432 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7433                             enum rte_eth_tunnel_type l2_tunnel_type)
7434 {
7435         int ret = 0;
7436         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7437         struct ixgbe_l2_tn_info *l2_tn_info =
7438                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7439
7440         switch (l2_tunnel_type) {
7441         case RTE_L2_TUNNEL_TYPE_E_TAG:
7442                 l2_tn_info->e_tag_en = FALSE;
7443                 ret = ixgbe_e_tag_disable(hw);
7444                 break;
7445         default:
7446                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7447                 ret = -EINVAL;
7448                 break;
7449         }
7450
7451         return ret;
7452 }
7453
7454 static int
7455 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7456                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7457 {
7458         int ret = 0;
7459         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7460         uint32_t i, rar_entries;
7461         uint32_t rar_low, rar_high;
7462
7463         if (hw->mac.type != ixgbe_mac_X550 &&
7464             hw->mac.type != ixgbe_mac_X550EM_x &&
7465             hw->mac.type != ixgbe_mac_X550EM_a) {
7466                 return -ENOTSUP;
7467         }
7468
7469         rar_entries = ixgbe_get_num_rx_addrs(hw);
7470
7471         for (i = 1; i < rar_entries; i++) {
7472                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7473                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7474                 if ((rar_high & IXGBE_RAH_AV) &&
7475                     (rar_high & IXGBE_RAH_ADTYPE) &&
7476                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7477                      l2_tunnel->tunnel_id)) {
7478                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7479                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7480
7481                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7482
7483                         return ret;
7484                 }
7485         }
7486
7487         return ret;
7488 }
7489
7490 static int
7491 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7492                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7493 {
7494         int ret = 0;
7495         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7496         uint32_t i, rar_entries;
7497         uint32_t rar_low, rar_high;
7498
7499         if (hw->mac.type != ixgbe_mac_X550 &&
7500             hw->mac.type != ixgbe_mac_X550EM_x &&
7501             hw->mac.type != ixgbe_mac_X550EM_a) {
7502                 return -ENOTSUP;
7503         }
7504
7505         /* One entry for one tunnel. Try to remove potential existing entry. */
7506         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7507
7508         rar_entries = ixgbe_get_num_rx_addrs(hw);
7509
7510         for (i = 1; i < rar_entries; i++) {
7511                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7512                 if (rar_high & IXGBE_RAH_AV) {
7513                         continue;
7514                 } else {
7515                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7516                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7517                         rar_low = l2_tunnel->tunnel_id;
7518
7519                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7520                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7521
7522                         return ret;
7523                 }
7524         }
7525
7526         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7527                      " Please remove a rule before adding a new one.");
7528         return -EINVAL;
7529 }
7530
7531 static inline struct ixgbe_l2_tn_filter *
7532 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7533                           struct ixgbe_l2_tn_key *key)
7534 {
7535         int ret;
7536
7537         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7538         if (ret < 0)
7539                 return NULL;
7540
7541         return l2_tn_info->hash_map[ret];
7542 }
7543
7544 static inline int
7545 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7546                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7547 {
7548         int ret;
7549
7550         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7551                                &l2_tn_filter->key);
7552
7553         if (ret < 0) {
7554                 PMD_DRV_LOG(ERR,
7555                             "Failed to insert L2 tunnel filter"
7556                             " to hash table %d!",
7557                             ret);
7558                 return ret;
7559         }
7560
7561         l2_tn_info->hash_map[ret] = l2_tn_filter;
7562
7563         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7564
7565         return 0;
7566 }
7567
7568 static inline int
7569 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7570                           struct ixgbe_l2_tn_key *key)
7571 {
7572         int ret;
7573         struct ixgbe_l2_tn_filter *l2_tn_filter;
7574
7575         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7576
7577         if (ret < 0) {
7578                 PMD_DRV_LOG(ERR,
7579                             "No such L2 tunnel filter to delete %d!",
7580                             ret);
7581                 return ret;
7582         }
7583
7584         l2_tn_filter = l2_tn_info->hash_map[ret];
7585         l2_tn_info->hash_map[ret] = NULL;
7586
7587         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7588         rte_free(l2_tn_filter);
7589
7590         return 0;
7591 }
7592
7593 /* Add l2 tunnel filter */
7594 int
7595 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7596                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7597                                bool restore)
7598 {
7599         int ret;
7600         struct ixgbe_l2_tn_info *l2_tn_info =
7601                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7602         struct ixgbe_l2_tn_key key;
7603         struct ixgbe_l2_tn_filter *node;
7604
7605         if (!restore) {
7606                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7607                 key.tn_id = l2_tunnel->tunnel_id;
7608
7609                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7610
7611                 if (node) {
7612                         PMD_DRV_LOG(ERR,
7613                                     "The L2 tunnel filter already exists!");
7614                         return -EINVAL;
7615                 }
7616
7617                 node = rte_zmalloc("ixgbe_l2_tn",
7618                                    sizeof(struct ixgbe_l2_tn_filter),
7619                                    0);
7620                 if (!node)
7621                         return -ENOMEM;
7622
7623                 rte_memcpy(&node->key,
7624                                  &key,
7625                                  sizeof(struct ixgbe_l2_tn_key));
7626                 node->pool = l2_tunnel->pool;
7627                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7628                 if (ret < 0) {
7629                         rte_free(node);
7630                         return ret;
7631                 }
7632         }
7633
7634         switch (l2_tunnel->l2_tunnel_type) {
7635         case RTE_L2_TUNNEL_TYPE_E_TAG:
7636                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7637                 break;
7638         default:
7639                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7640                 ret = -EINVAL;
7641                 break;
7642         }
7643
7644         if ((!restore) && (ret < 0))
7645                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7646
7647         return ret;
7648 }
7649
7650 /* Delete l2 tunnel filter */
7651 int
7652 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7653                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7654 {
7655         int ret;
7656         struct ixgbe_l2_tn_info *l2_tn_info =
7657                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7658         struct ixgbe_l2_tn_key key;
7659
7660         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7661         key.tn_id = l2_tunnel->tunnel_id;
7662         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7663         if (ret < 0)
7664                 return ret;
7665
7666         switch (l2_tunnel->l2_tunnel_type) {
7667         case RTE_L2_TUNNEL_TYPE_E_TAG:
7668                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7669                 break;
7670         default:
7671                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7672                 ret = -EINVAL;
7673                 break;
7674         }
7675
7676         return ret;
7677 }
7678
7679 /**
7680  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7681  * @dev: pointer to rte_eth_dev structure
7682  * @filter_op:operation will be taken.
7683  * @arg: a pointer to specific structure corresponding to the filter_op
7684  */
7685 static int
7686 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7687                                   enum rte_filter_op filter_op,
7688                                   void *arg)
7689 {
7690         int ret;
7691
7692         if (filter_op == RTE_ETH_FILTER_NOP)
7693                 return 0;
7694
7695         if (arg == NULL) {
7696                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7697                             filter_op);
7698                 return -EINVAL;
7699         }
7700
7701         switch (filter_op) {
7702         case RTE_ETH_FILTER_ADD:
7703                 ret = ixgbe_dev_l2_tunnel_filter_add
7704                         (dev,
7705                          (struct rte_eth_l2_tunnel_conf *)arg,
7706                          FALSE);
7707                 break;
7708         case RTE_ETH_FILTER_DELETE:
7709                 ret = ixgbe_dev_l2_tunnel_filter_del
7710                         (dev,
7711                          (struct rte_eth_l2_tunnel_conf *)arg);
7712                 break;
7713         default:
7714                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7715                 ret = -EINVAL;
7716                 break;
7717         }
7718         return ret;
7719 }
7720
7721 static int
7722 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7723 {
7724         int ret = 0;
7725         uint32_t ctrl;
7726         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7727
7728         if (hw->mac.type != ixgbe_mac_X550 &&
7729             hw->mac.type != ixgbe_mac_X550EM_x &&
7730             hw->mac.type != ixgbe_mac_X550EM_a) {
7731                 return -ENOTSUP;
7732         }
7733
7734         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7735         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7736         if (en)
7737                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7738         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7739
7740         return ret;
7741 }
7742
7743 /* Enable l2 tunnel forwarding */
7744 static int
7745 ixgbe_dev_l2_tunnel_forwarding_enable
7746         (struct rte_eth_dev *dev,
7747          enum rte_eth_tunnel_type l2_tunnel_type)
7748 {
7749         struct ixgbe_l2_tn_info *l2_tn_info =
7750                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7751         int ret = 0;
7752
7753         switch (l2_tunnel_type) {
7754         case RTE_L2_TUNNEL_TYPE_E_TAG:
7755                 l2_tn_info->e_tag_fwd_en = TRUE;
7756                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7757                 break;
7758         default:
7759                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7760                 ret = -EINVAL;
7761                 break;
7762         }
7763
7764         return ret;
7765 }
7766
7767 /* Disable l2 tunnel forwarding */
7768 static int
7769 ixgbe_dev_l2_tunnel_forwarding_disable
7770         (struct rte_eth_dev *dev,
7771          enum rte_eth_tunnel_type l2_tunnel_type)
7772 {
7773         struct ixgbe_l2_tn_info *l2_tn_info =
7774                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7775         int ret = 0;
7776
7777         switch (l2_tunnel_type) {
7778         case RTE_L2_TUNNEL_TYPE_E_TAG:
7779                 l2_tn_info->e_tag_fwd_en = FALSE;
7780                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7781                 break;
7782         default:
7783                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7784                 ret = -EINVAL;
7785                 break;
7786         }
7787
7788         return ret;
7789 }
7790
7791 static int
7792 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7793                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7794                              bool en)
7795 {
7796         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7797         int ret = 0;
7798         uint32_t vmtir, vmvir;
7799         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7800
7801         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7802                 PMD_DRV_LOG(ERR,
7803                             "VF id %u should be less than %u",
7804                             l2_tunnel->vf_id,
7805                             pci_dev->max_vfs);
7806                 return -EINVAL;
7807         }
7808
7809         if (hw->mac.type != ixgbe_mac_X550 &&
7810             hw->mac.type != ixgbe_mac_X550EM_x &&
7811             hw->mac.type != ixgbe_mac_X550EM_a) {
7812                 return -ENOTSUP;
7813         }
7814
7815         if (en)
7816                 vmtir = l2_tunnel->tunnel_id;
7817         else
7818                 vmtir = 0;
7819
7820         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7821
7822         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7823         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7824         if (en)
7825                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7826         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7827
7828         return ret;
7829 }
7830
7831 /* Enable l2 tunnel tag insertion */
7832 static int
7833 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7834                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7835 {
7836         int ret = 0;
7837
7838         switch (l2_tunnel->l2_tunnel_type) {
7839         case RTE_L2_TUNNEL_TYPE_E_TAG:
7840                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7841                 break;
7842         default:
7843                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7844                 ret = -EINVAL;
7845                 break;
7846         }
7847
7848         return ret;
7849 }
7850
7851 /* Disable l2 tunnel tag insertion */
7852 static int
7853 ixgbe_dev_l2_tunnel_insertion_disable
7854         (struct rte_eth_dev *dev,
7855          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7856 {
7857         int ret = 0;
7858
7859         switch (l2_tunnel->l2_tunnel_type) {
7860         case RTE_L2_TUNNEL_TYPE_E_TAG:
7861                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7862                 break;
7863         default:
7864                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7865                 ret = -EINVAL;
7866                 break;
7867         }
7868
7869         return ret;
7870 }
7871
7872 static int
7873 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7874                              bool en)
7875 {
7876         int ret = 0;
7877         uint32_t qde;
7878         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7879
7880         if (hw->mac.type != ixgbe_mac_X550 &&
7881             hw->mac.type != ixgbe_mac_X550EM_x &&
7882             hw->mac.type != ixgbe_mac_X550EM_a) {
7883                 return -ENOTSUP;
7884         }
7885
7886         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7887         if (en)
7888                 qde |= IXGBE_QDE_STRIP_TAG;
7889         else
7890                 qde &= ~IXGBE_QDE_STRIP_TAG;
7891         qde &= ~IXGBE_QDE_READ;
7892         qde |= IXGBE_QDE_WRITE;
7893         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7894
7895         return ret;
7896 }
7897
7898 /* Enable l2 tunnel tag stripping */
7899 static int
7900 ixgbe_dev_l2_tunnel_stripping_enable
7901         (struct rte_eth_dev *dev,
7902          enum rte_eth_tunnel_type l2_tunnel_type)
7903 {
7904         int ret = 0;
7905
7906         switch (l2_tunnel_type) {
7907         case RTE_L2_TUNNEL_TYPE_E_TAG:
7908                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7909                 break;
7910         default:
7911                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7912                 ret = -EINVAL;
7913                 break;
7914         }
7915
7916         return ret;
7917 }
7918
7919 /* Disable l2 tunnel tag stripping */
7920 static int
7921 ixgbe_dev_l2_tunnel_stripping_disable
7922         (struct rte_eth_dev *dev,
7923          enum rte_eth_tunnel_type l2_tunnel_type)
7924 {
7925         int ret = 0;
7926
7927         switch (l2_tunnel_type) {
7928         case RTE_L2_TUNNEL_TYPE_E_TAG:
7929                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7930                 break;
7931         default:
7932                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7933                 ret = -EINVAL;
7934                 break;
7935         }
7936
7937         return ret;
7938 }
7939
7940 /* Enable/disable l2 tunnel offload functions */
7941 static int
7942 ixgbe_dev_l2_tunnel_offload_set
7943         (struct rte_eth_dev *dev,
7944          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7945          uint32_t mask,
7946          uint8_t en)
7947 {
7948         int ret = 0;
7949
7950         if (l2_tunnel == NULL)
7951                 return -EINVAL;
7952
7953         ret = -EINVAL;
7954         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7955                 if (en)
7956                         ret = ixgbe_dev_l2_tunnel_enable(
7957                                 dev,
7958                                 l2_tunnel->l2_tunnel_type);
7959                 else
7960                         ret = ixgbe_dev_l2_tunnel_disable(
7961                                 dev,
7962                                 l2_tunnel->l2_tunnel_type);
7963         }
7964
7965         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7966                 if (en)
7967                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7968                                 dev,
7969                                 l2_tunnel);
7970                 else
7971                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7972                                 dev,
7973                                 l2_tunnel);
7974         }
7975
7976         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7977                 if (en)
7978                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7979                                 dev,
7980                                 l2_tunnel->l2_tunnel_type);
7981                 else
7982                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7983                                 dev,
7984                                 l2_tunnel->l2_tunnel_type);
7985         }
7986
7987         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7988                 if (en)
7989                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7990                                 dev,
7991                                 l2_tunnel->l2_tunnel_type);
7992                 else
7993                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7994                                 dev,
7995                                 l2_tunnel->l2_tunnel_type);
7996         }
7997
7998         return ret;
7999 }
8000
8001 static int
8002 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8003                         uint16_t port)
8004 {
8005         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8006         IXGBE_WRITE_FLUSH(hw);
8007
8008         return 0;
8009 }
8010
8011 /* There's only one register for VxLAN UDP port.
8012  * So, we cannot add several ports. Will update it.
8013  */
8014 static int
8015 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8016                      uint16_t port)
8017 {
8018         if (port == 0) {
8019                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8020                 return -EINVAL;
8021         }
8022
8023         return ixgbe_update_vxlan_port(hw, port);
8024 }
8025
8026 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8027  * UDP port, it must have a value.
8028  * So, will reset it to the original value 0.
8029  */
8030 static int
8031 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8032                      uint16_t port)
8033 {
8034         uint16_t cur_port;
8035
8036         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8037
8038         if (cur_port != port) {
8039                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8040                 return -EINVAL;
8041         }
8042
8043         return ixgbe_update_vxlan_port(hw, 0);
8044 }
8045
8046 /* Add UDP tunneling port */
8047 static int
8048 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8049                               struct rte_eth_udp_tunnel *udp_tunnel)
8050 {
8051         int ret = 0;
8052         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8053
8054         if (hw->mac.type != ixgbe_mac_X550 &&
8055             hw->mac.type != ixgbe_mac_X550EM_x &&
8056             hw->mac.type != ixgbe_mac_X550EM_a) {
8057                 return -ENOTSUP;
8058         }
8059
8060         if (udp_tunnel == NULL)
8061                 return -EINVAL;
8062
8063         switch (udp_tunnel->prot_type) {
8064         case RTE_TUNNEL_TYPE_VXLAN:
8065                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8066                 break;
8067
8068         case RTE_TUNNEL_TYPE_GENEVE:
8069         case RTE_TUNNEL_TYPE_TEREDO:
8070                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8071                 ret = -EINVAL;
8072                 break;
8073
8074         default:
8075                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8076                 ret = -EINVAL;
8077                 break;
8078         }
8079
8080         return ret;
8081 }
8082
8083 /* Remove UDP tunneling port */
8084 static int
8085 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8086                               struct rte_eth_udp_tunnel *udp_tunnel)
8087 {
8088         int ret = 0;
8089         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8090
8091         if (hw->mac.type != ixgbe_mac_X550 &&
8092             hw->mac.type != ixgbe_mac_X550EM_x &&
8093             hw->mac.type != ixgbe_mac_X550EM_a) {
8094                 return -ENOTSUP;
8095         }
8096
8097         if (udp_tunnel == NULL)
8098                 return -EINVAL;
8099
8100         switch (udp_tunnel->prot_type) {
8101         case RTE_TUNNEL_TYPE_VXLAN:
8102                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8103                 break;
8104         case RTE_TUNNEL_TYPE_GENEVE:
8105         case RTE_TUNNEL_TYPE_TEREDO:
8106                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8107                 ret = -EINVAL;
8108                 break;
8109         default:
8110                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8111                 ret = -EINVAL;
8112                 break;
8113         }
8114
8115         return ret;
8116 }
8117
8118 static void
8119 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8120 {
8121         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8122
8123         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8124 }
8125
8126 static void
8127 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8128 {
8129         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8130
8131         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8132 }
8133
8134 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8135 {
8136         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8137         u32 in_msg = 0;
8138
8139         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8140                 return;
8141
8142         /* PF reset VF event */
8143         if (in_msg == IXGBE_PF_CONTROL_MSG)
8144                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8145                                               NULL, NULL);
8146 }
8147
8148 static int
8149 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8150 {
8151         uint32_t eicr;
8152         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8153         struct ixgbe_interrupt *intr =
8154                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8155         ixgbevf_intr_disable(hw);
8156
8157         /* read-on-clear nic registers here */
8158         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8159         intr->flags = 0;
8160
8161         /* only one misc vector supported - mailbox */
8162         eicr &= IXGBE_VTEICR_MASK;
8163         if (eicr == IXGBE_MISC_VEC_ID)
8164                 intr->flags |= IXGBE_FLAG_MAILBOX;
8165
8166         return 0;
8167 }
8168
8169 static int
8170 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8171 {
8172         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8173         struct ixgbe_interrupt *intr =
8174                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8175
8176         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8177                 ixgbevf_mbx_process(dev);
8178                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8179         }
8180
8181         ixgbevf_intr_enable(hw);
8182
8183         return 0;
8184 }
8185
8186 static void
8187 ixgbevf_dev_interrupt_handler(void *param)
8188 {
8189         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8190
8191         ixgbevf_dev_interrupt_get_status(dev);
8192         ixgbevf_dev_interrupt_action(dev);
8193 }
8194
8195 /**
8196  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8197  *  @hw: pointer to hardware structure
8198  *
8199  *  Stops the transmit data path and waits for the HW to internally empty
8200  *  the Tx security block
8201  **/
8202 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8203 {
8204 #define IXGBE_MAX_SECTX_POLL 40
8205
8206         int i;
8207         int sectxreg;
8208
8209         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8210         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8211         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8212         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8213                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8214                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8215                         break;
8216                 /* Use interrupt-safe sleep just in case */
8217                 usec_delay(1000);
8218         }
8219
8220         /* For informational purposes only */
8221         if (i >= IXGBE_MAX_SECTX_POLL)
8222                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8223                          "path fully disabled.  Continuing with init.");
8224
8225         return IXGBE_SUCCESS;
8226 }
8227
8228 /**
8229  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8230  *  @hw: pointer to hardware structure
8231  *
8232  *  Enables the transmit data path.
8233  **/
8234 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8235 {
8236         uint32_t sectxreg;
8237
8238         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8239         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8240         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8241         IXGBE_WRITE_FLUSH(hw);
8242
8243         return IXGBE_SUCCESS;
8244 }
8245
8246 /* restore n-tuple filter */
8247 static inline void
8248 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8249 {
8250         struct ixgbe_filter_info *filter_info =
8251                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8252         struct ixgbe_5tuple_filter *node;
8253
8254         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8255                 ixgbe_inject_5tuple_filter(dev, node);
8256         }
8257 }
8258
8259 /* restore ethernet type filter */
8260 static inline void
8261 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8262 {
8263         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8264         struct ixgbe_filter_info *filter_info =
8265                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8266         int i;
8267
8268         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8269                 if (filter_info->ethertype_mask & (1 << i)) {
8270                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8271                                         filter_info->ethertype_filters[i].etqf);
8272                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8273                                         filter_info->ethertype_filters[i].etqs);
8274                         IXGBE_WRITE_FLUSH(hw);
8275                 }
8276         }
8277 }
8278
8279 /* restore SYN filter */
8280 static inline void
8281 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8282 {
8283         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8284         struct ixgbe_filter_info *filter_info =
8285                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8286         uint32_t synqf;
8287
8288         synqf = filter_info->syn_info;
8289
8290         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8291                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8292                 IXGBE_WRITE_FLUSH(hw);
8293         }
8294 }
8295
8296 /* restore L2 tunnel filter */
8297 static inline void
8298 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8299 {
8300         struct ixgbe_l2_tn_info *l2_tn_info =
8301                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8302         struct ixgbe_l2_tn_filter *node;
8303         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8304
8305         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8306                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8307                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8308                 l2_tn_conf.pool           = node->pool;
8309                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8310         }
8311 }
8312
8313 static int
8314 ixgbe_filter_restore(struct rte_eth_dev *dev)
8315 {
8316         ixgbe_ntuple_filter_restore(dev);
8317         ixgbe_ethertype_filter_restore(dev);
8318         ixgbe_syn_filter_restore(dev);
8319         ixgbe_fdir_filter_restore(dev);
8320         ixgbe_l2_tn_filter_restore(dev);
8321
8322         return 0;
8323 }
8324
8325 static void
8326 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8327 {
8328         struct ixgbe_l2_tn_info *l2_tn_info =
8329                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8330         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8331
8332         if (l2_tn_info->e_tag_en)
8333                 (void)ixgbe_e_tag_enable(hw);
8334
8335         if (l2_tn_info->e_tag_fwd_en)
8336                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8337
8338         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8339 }
8340
8341 /* remove all the n-tuple filters */
8342 void
8343 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8344 {
8345         struct ixgbe_filter_info *filter_info =
8346                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8347         struct ixgbe_5tuple_filter *p_5tuple;
8348
8349         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8350                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8351 }
8352
8353 /* remove all the ether type filters */
8354 void
8355 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8356 {
8357         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8358         struct ixgbe_filter_info *filter_info =
8359                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8360         int i;
8361
8362         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8363                 if (filter_info->ethertype_mask & (1 << i) &&
8364                     !filter_info->ethertype_filters[i].conf) {
8365                         (void)ixgbe_ethertype_filter_remove(filter_info,
8366                                                             (uint8_t)i);
8367                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8368                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8369                         IXGBE_WRITE_FLUSH(hw);
8370                 }
8371         }
8372 }
8373
8374 /* remove the SYN filter */
8375 void
8376 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8377 {
8378         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8379         struct ixgbe_filter_info *filter_info =
8380                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8381
8382         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8383                 filter_info->syn_info = 0;
8384
8385                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8386                 IXGBE_WRITE_FLUSH(hw);
8387         }
8388 }
8389
8390 /* remove all the L2 tunnel filters */
8391 int
8392 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8393 {
8394         struct ixgbe_l2_tn_info *l2_tn_info =
8395                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8396         struct ixgbe_l2_tn_filter *l2_tn_filter;
8397         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8398         int ret = 0;
8399
8400         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8401                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8402                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8403                 l2_tn_conf.pool           = l2_tn_filter->pool;
8404                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8405                 if (ret < 0)
8406                         return ret;
8407         }
8408
8409         return 0;
8410 }
8411
8412 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8413 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8414 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8415 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8416 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8417 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");