drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIB_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static int ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
 234                                               uint32_t timeout_ms);
 235
 236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 237                         struct rte_ether_addr *mac_addr,
 238                         uint32_t index, uint32_t pool);
 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 241                                            struct rte_ether_addr *mac_addr);
 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 243 static bool is_device_supported(struct rte_eth_dev *dev,
 244                                 struct rte_pci_driver *drv);
 245
 246 /* For Virtual Function support */
 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 250 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 252                                    int wait_to_complete);
 253 static int ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static int ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 259                 struct rte_eth_stats *stats);
 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 262                 uint16_t vlan_id, int on);
 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 264                 uint16_t queue, int on);
 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id);
 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 271                                              uint16_t queue_id);
 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 273                                  uint8_t queue, uint8_t msix_vector);
 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 rte_ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 285                 struct rte_eth_mirror_conf *mirror_conf,
 286                 uint8_t rule_id, uint8_t on);
 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 288                 uint8_t rule_id);
 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 290                                           uint16_t queue_id);
 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 292                                            uint16_t queue_id);
 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 294                                uint8_t queue, uint8_t msix_vector);
 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 296
 297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 298                                 struct rte_ether_addr *mac_addr,
 299                                 uint32_t index, uint32_t pool);
 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 302                                              struct rte_ether_addr *mac_addr);
 303 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 304                         struct ixgbe_5tuple_filter *filter);
 305 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 306                         struct ixgbe_5tuple_filter *filter);
 307 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 308                      enum rte_filter_type filter_type,
 309                      enum rte_filter_op filter_op,
 310                      void *arg);
 311 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 312
 313 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 314                                       struct rte_ether_addr *mc_addr_set,
 315                                       uint32_t nb_mc_addr);
 316 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 317                                    struct rte_eth_dcb_info *dcb_info);
 318
 319 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 320 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 321                             struct rte_dev_reg_info *regs);
 322 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 323 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 324                                 struct rte_dev_eeprom_info *eeprom);
 325 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 326                                 struct rte_dev_eeprom_info *eeprom);
 327
 328 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 329                                  struct rte_eth_dev_module_info *modinfo);
 330 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 331                                    struct rte_dev_eeprom_info *info);
 332
 333 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 334 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 335                                 struct rte_dev_reg_info *regs);
 336
 337 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 338 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 339 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 340                                             struct timespec *timestamp,
 341                                             uint32_t flags);
 342 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 343                                             struct timespec *timestamp);
 344 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 345 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 346                                    struct timespec *timestamp);
 347 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 348                                    const struct timespec *timestamp);
 349 static void ixgbevf_dev_interrupt_handler(void *param);
 350
 351 static int ixgbe_dev_l2_tunnel_eth_type_conf
 352         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 353 static int ixgbe_dev_l2_tunnel_offload_set
 354         (struct rte_eth_dev *dev,
 355          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 356          uint32_t mask,
 357          uint8_t en);
 358 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 359                                              enum rte_filter_op filter_op,
 360                                              void *arg);
 361
 362 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 363                                          struct rte_eth_udp_tunnel *udp_tunnel);
 364 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 365                                          struct rte_eth_udp_tunnel *udp_tunnel);
 366 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 367 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 368 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 369
 370 /*
 371  * Define VF Stats MACRO for Non "cleared on read" register
 372  */
 373 #define UPDATE_VF_STAT(reg, last, cur)                          \
 374 {                                                               \
 375         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 376         cur += (latest - last) & UINT_MAX;                      \
 377         last = latest;                                          \
 378 }
 379
 380 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 381 {                                                                \
 382         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 383         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 384         u64 latest = ((new_msb << 32) | new_lsb);                \
 385         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 386         last = latest;                                           \
 387 }
 388
 389 #define IXGBE_SET_HWSTRIP(h, q) do {\
 390                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 391                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 392                 (h)->bitmap[idx] |= 1 << bit;\
 393         } while (0)
 394
 395 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 396                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 397                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 398                 (h)->bitmap[idx] &= ~(1 << bit);\
 399         } while (0)
 400
 401 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 402                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 403                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 404                 (r) = (h)->bitmap[idx] >> bit & 1;\
 405         } while (0)
 406
 407 /*
 408  * The set of PCI devices this driver supports
 409  */
 410 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 459 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 461 #endif
 462         { .vendor_id = 0, /* sentinel */ },
 463 };
 464
 465 /*
 466  * The set of PCI devices this driver supports (for 82599 VF)
 467  */
 468 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 479         { .vendor_id = 0, /* sentinel */ },
 480 };
 481
 482 static const struct rte_eth_desc_lim rx_desc_lim = {
 483         .nb_max = IXGBE_MAX_RING_DESC,
 484         .nb_min = IXGBE_MIN_RING_DESC,
 485         .nb_align = IXGBE_RXD_ALIGN,
 486 };
 487
 488 static const struct rte_eth_desc_lim tx_desc_lim = {
 489         .nb_max = IXGBE_MAX_RING_DESC,
 490         .nb_min = IXGBE_MIN_RING_DESC,
 491         .nb_align = IXGBE_TXD_ALIGN,
 492         .nb_seg_max = IXGBE_TX_MAX_SEG,
 493         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 494 };
 495
 496 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 497         .dev_configure        = ixgbe_dev_configure,
 498         .dev_start            = ixgbe_dev_start,
 499         .dev_stop             = ixgbe_dev_stop,
 500         .dev_set_link_up    = ixgbe_dev_set_link_up,
 501         .dev_set_link_down  = ixgbe_dev_set_link_down,
 502         .dev_close            = ixgbe_dev_close,
 503         .dev_reset            = ixgbe_dev_reset,
 504         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 505         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 506         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 507         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 508         .link_update          = ixgbe_dev_link_update,
 509         .stats_get            = ixgbe_dev_stats_get,
 510         .xstats_get           = ixgbe_dev_xstats_get,
 511         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 512         .stats_reset          = ixgbe_dev_stats_reset,
 513         .xstats_reset         = ixgbe_dev_xstats_reset,
 514         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 515         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 516         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 517         .fw_version_get       = ixgbe_fw_version_get,
 518         .dev_infos_get        = ixgbe_dev_info_get,
 519         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 520         .mtu_set              = ixgbe_dev_mtu_set,
 521         .vlan_filter_set      = ixgbe_vlan_filter_set,
 522         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 523         .vlan_offload_set     = ixgbe_vlan_offload_set,
 524         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 525         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 526         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 527         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 528         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 529         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 530         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 531         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 532         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 533         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 534         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 535         .dev_led_on           = ixgbe_dev_led_on,
 536         .dev_led_off          = ixgbe_dev_led_off,
 537         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 538         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 539         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 540         .mac_addr_add         = ixgbe_add_rar,
 541         .mac_addr_remove      = ixgbe_remove_rar,
 542         .mac_addr_set         = ixgbe_set_default_mac_addr,
 543         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 544         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 545         .mirror_rule_set      = ixgbe_mirror_rule_set,
 546         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 547         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 548         .reta_update          = ixgbe_dev_rss_reta_update,
 549         .reta_query           = ixgbe_dev_rss_reta_query,
 550         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 551         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 552         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 553         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 554         .rxq_info_get         = ixgbe_rxq_info_get,
 555         .txq_info_get         = ixgbe_txq_info_get,
 556         .timesync_enable      = ixgbe_timesync_enable,
 557         .timesync_disable     = ixgbe_timesync_disable,
 558         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 559         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 560         .get_reg              = ixgbe_get_regs,
 561         .get_eeprom_length    = ixgbe_get_eeprom_length,
 562         .get_eeprom           = ixgbe_get_eeprom,
 563         .set_eeprom           = ixgbe_set_eeprom,
 564         .get_module_info      = ixgbe_get_module_info,
 565         .get_module_eeprom    = ixgbe_get_module_eeprom,
 566         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 567         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 568         .timesync_read_time   = ixgbe_timesync_read_time,
 569         .timesync_write_time  = ixgbe_timesync_write_time,
 570         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 571         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 572         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 573         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 574         .tm_ops_get           = ixgbe_tm_ops_get,
 575         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 576 };
 577
 578 /*
 579  * dev_ops for virtual function, bare necessities for basic vf
 580  * operation have been implemented
 581  */
 582 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 583         .dev_configure        = ixgbevf_dev_configure,
 584         .dev_start            = ixgbevf_dev_start,
 585         .dev_stop             = ixgbevf_dev_stop,
 586         .link_update          = ixgbevf_dev_link_update,
 587         .stats_get            = ixgbevf_dev_stats_get,
 588         .xstats_get           = ixgbevf_dev_xstats_get,
 589         .stats_reset          = ixgbevf_dev_stats_reset,
 590         .xstats_reset         = ixgbevf_dev_stats_reset,
 591         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 592         .dev_close            = ixgbevf_dev_close,
 593         .dev_reset            = ixgbevf_dev_reset,
 594         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 595         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 596         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 597         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 598         .dev_infos_get        = ixgbevf_dev_info_get,
 599         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 600         .mtu_set              = ixgbevf_dev_set_mtu,
 601         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 602         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 603         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 604         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 605         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 606         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 607         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 608         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 609         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 610         .mac_addr_add         = ixgbevf_add_mac_addr,
 611         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 612         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 613         .rxq_info_get         = ixgbe_rxq_info_get,
 614         .txq_info_get         = ixgbe_txq_info_get,
 615         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 616         .get_reg              = ixgbevf_get_regs,
 617         .reta_update          = ixgbe_dev_rss_reta_update,
 618         .reta_query           = ixgbe_dev_rss_reta_query,
 619         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 620         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 621         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 622 };
 623
 624 /* store statistics names and its offset in stats structure */
 625 struct rte_ixgbe_xstats_name_off {
 626         char name[RTE_ETH_XSTATS_NAME_SIZE];
 627         unsigned offset;
 628 };
 629
 630 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 631         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 632         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 633         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 634         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 635         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 636         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 637         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 638         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 639         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 640         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 641         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 642         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 643         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 644         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 645         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 646                 prc1023)},
 647         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 648                 prc1522)},
 649         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 650         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 651         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 652         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 653         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 654         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 655         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 656         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 657         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 658         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 659         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 660         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 661         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 662         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 663         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 664         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 665         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 666                 ptc1023)},
 667         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 668                 ptc1522)},
 669         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 670         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 671         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 672         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 673
 674         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 675                 fdirustat_add)},
 676         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 677                 fdirustat_remove)},
 678         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 679                 fdirfstat_fadd)},
 680         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 681                 fdirfstat_fremove)},
 682         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 683                 fdirmatch)},
 684         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 685                 fdirmiss)},
 686
 687         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 688         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 689         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 690                 fclast)},
 691         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 692         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 693         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 694         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 695         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 696                 fcoe_noddp)},
 697         {"rx_fcoe_no_direct_data_placement_ext_buff",
 698                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 699
 700         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 701                 lxontxc)},
 702         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 703                 lxonrxc)},
 704         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 705                 lxofftxc)},
 706         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 707                 lxoffrxc)},
 708         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 709 };
 710
 711 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 712                            sizeof(rte_ixgbe_stats_strings[0]))
 713
 714 /* MACsec statistics */
 715 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 716         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 717                 out_pkts_untagged)},
 718         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 719                 out_pkts_encrypted)},
 720         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 721                 out_pkts_protected)},
 722         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 723                 out_octets_encrypted)},
 724         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 725                 out_octets_protected)},
 726         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 727                 in_pkts_untagged)},
 728         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 729                 in_pkts_badtag)},
 730         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 731                 in_pkts_nosci)},
 732         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 733                 in_pkts_unknownsci)},
 734         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 735                 in_octets_decrypted)},
 736         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 737                 in_octets_validated)},
 738         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 739                 in_pkts_unchecked)},
 740         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 741                 in_pkts_delayed)},
 742         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 743                 in_pkts_late)},
 744         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 745                 in_pkts_ok)},
 746         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 747                 in_pkts_invalid)},
 748         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_notvalid)},
 750         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_unusedsa)},
 752         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_notusingsa)},
 754 };
 755
 756 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 757                            sizeof(rte_ixgbe_macsec_strings[0]))
 758
 759 /* Per-queue statistics */
 760 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 761         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 762         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 763         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 764         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 765 };
 766
 767 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 768                            sizeof(rte_ixgbe_rxq_strings[0]))
 769 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 770
 771 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 772         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 773         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 774         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 775                 pxon2offc)},
 776 };
 777
 778 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 779                            sizeof(rte_ixgbe_txq_strings[0]))
 780 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 781
 782 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 783         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 784 };
 785
 786 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 787                 sizeof(rte_ixgbevf_stats_strings[0]))
 788
 789 /*
 790  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 791  */
 792 static inline int
 793 ixgbe_is_sfp(struct ixgbe_hw *hw)
 794 {
 795         switch (hw->phy.type) {
 796         case ixgbe_phy_sfp_avago:
 797         case ixgbe_phy_sfp_ftl:
 798         case ixgbe_phy_sfp_intel:
 799         case ixgbe_phy_sfp_unknown:
 800         case ixgbe_phy_sfp_passive_tyco:
 801         case ixgbe_phy_sfp_passive_unknown:
 802                 return 1;
 803         default:
 804                 return 0;
 805         }
 806 }
 807
 808 static inline int32_t
 809 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 810 {
 811         uint32_t ctrl_ext;
 812         int32_t status;
 813
 814         status = ixgbe_reset_hw(hw);
 815
 816         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 817         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 818         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 819         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 820         IXGBE_WRITE_FLUSH(hw);
 821
 822         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 823                 status = IXGBE_SUCCESS;
 824         return status;
 825 }
 826
 827 static inline void
 828 ixgbe_enable_intr(struct rte_eth_dev *dev)
 829 {
 830         struct ixgbe_interrupt *intr =
 831                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 832         struct ixgbe_hw *hw =
 833                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 834
 835         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 836         IXGBE_WRITE_FLUSH(hw);
 837 }
 838
 839 /*
 840  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 841  */
 842 static void
 843 ixgbe_disable_intr(struct ixgbe_hw *hw)
 844 {
 845         PMD_INIT_FUNC_TRACE();
 846
 847         if (hw->mac.type == ixgbe_mac_82598EB) {
 848                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 849         } else {
 850                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 851                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 852                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 853         }
 854         IXGBE_WRITE_FLUSH(hw);
 855 }
 856
 857 /*
 858  * This function resets queue statistics mapping registers.
 859  * From Niantic datasheet, Initialization of Statistics section:
 860  * "...if software requires the queue counters, the RQSMR and TQSM registers
 861  * must be re-programmed following a device reset.
 862  */
 863 static void
 864 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 865 {
 866         uint32_t i;
 867
 868         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 869                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 870                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 871         }
 872 }
 873
 874
 875 static int
 876 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 877                                   uint16_t queue_id,
 878                                   uint8_t stat_idx,
 879                                   uint8_t is_rx)
 880 {
 881 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 882 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 883 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 884
 885         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 886         struct ixgbe_stat_mapping_registers *stat_mappings =
 887                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 888         uint32_t qsmr_mask = 0;
 889         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 890         uint32_t q_map;
 891         uint8_t n, offset;
 892
 893         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 894                 (hw->mac.type != ixgbe_mac_X540) &&
 895                 (hw->mac.type != ixgbe_mac_X550) &&
 896                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 897                 (hw->mac.type != ixgbe_mac_X550EM_a))
 898                 return -ENOSYS;
 899
 900         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 901                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 902                      queue_id, stat_idx);
 903
 904         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 905         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 906                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 907                 return -EIO;
 908         }
 909         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 910
 911         /* Now clear any previous stat_idx set */
 912         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 913         if (!is_rx)
 914                 stat_mappings->tqsm[n] &= ~clearing_mask;
 915         else
 916                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 917
 918         q_map = (uint32_t)stat_idx;
 919         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 920         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 921         if (!is_rx)
 922                 stat_mappings->tqsm[n] |= qsmr_mask;
 923         else
 924                 stat_mappings->rqsmr[n] |= qsmr_mask;
 925
 926         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 927                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 928                      queue_id, stat_idx);
 929         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 930                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 931
 932         /* Now write the mapping in the appropriate register */
 933         if (is_rx) {
 934                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 935                              stat_mappings->rqsmr[n], n);
 936                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 937         } else {
 938                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 939                              stat_mappings->tqsm[n], n);
 940                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 941         }
 942         return 0;
 943 }
 944
 945 static void
 946 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 947 {
 948         struct ixgbe_stat_mapping_registers *stat_mappings =
 949                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 950         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 951         int i;
 952
 953         /* write whatever was in stat mapping table to the NIC */
 954         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 955                 /* rx */
 956                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 957
 958                 /* tx */
 959                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 960         }
 961 }
 962
 963 static void
 964 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 965 {
 966         uint8_t i;
 967         struct ixgbe_dcb_tc_config *tc;
 968         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 969
 970         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 971         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 972         for (i = 0; i < dcb_max_tc; i++) {
 973                 tc = &dcb_config->tc_config[i];
 974                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 975                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 976                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 977                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 978                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 979                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 980                 tc->pfc = ixgbe_dcb_pfc_disabled;
 981         }
 982
 983         /* Initialize default user to priority mapping, UPx->TC0 */
 984         tc = &dcb_config->tc_config[0];
 985         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 986         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 987         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 988                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 989                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 990         }
 991         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 992         dcb_config->pfc_mode_enable = false;
 993         dcb_config->vt_mode = true;
 994         dcb_config->round_robin_enable = false;
 995         /* support all DCB capabilities in 82599 */
 996         dcb_config->support.capabilities = 0xFF;
 997
 998         /*we only support 4 Tcs for X540, X550 */
 999         if (hw->mac.type == ixgbe_mac_X540 ||
1000                 hw->mac.type == ixgbe_mac_X550 ||
1001                 hw->mac.type == ixgbe_mac_X550EM_x ||
1002                 hw->mac.type == ixgbe_mac_X550EM_a) {
1003                 dcb_config->num_tcs.pg_tcs = 4;
1004                 dcb_config->num_tcs.pfc_tcs = 4;
1005         }
1006 }
1007
1008 /*
1009  * Ensure that all locks are released before first NVM or PHY access
1010  */
1011 static void
1012 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1013 {
1014         uint16_t mask;
1015
1016         /*
1017          * Phy lock should not fail in this early stage. If this is the case,
1018          * it is due to an improper exit of the application.
1019          * So force the release of the faulty lock. Release of common lock
1020          * is done automatically by swfw_sync function.
1021          */
1022         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1023         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1024                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1025         }
1026         ixgbe_release_swfw_semaphore(hw, mask);
1027
1028         /*
1029          * These ones are more tricky since they are common to all ports; but
1030          * swfw_sync retries last long enough (1s) to be almost sure that if
1031          * lock can not be taken it is due to an improper lock of the
1032          * semaphore.
1033          */
1034         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1035         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1036                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1037         }
1038         ixgbe_release_swfw_semaphore(hw, mask);
1039 }
1040
1041 /*
1042  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1043  * It returns 0 on success.
1044  */
1045 static int
1046 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1047 {
1048         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1049         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1050         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1051         struct ixgbe_hw *hw =
1052                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1053         struct ixgbe_vfta *shadow_vfta =
1054                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1055         struct ixgbe_hwstrip *hwstrip =
1056                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1057         struct ixgbe_dcb_config *dcb_config =
1058                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1059         struct ixgbe_filter_info *filter_info =
1060                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1061         struct ixgbe_bw_conf *bw_conf =
1062                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1063         uint32_t ctrl_ext;
1064         uint16_t csum;
1065         int diag, i, ret;
1066
1067         PMD_INIT_FUNC_TRACE();
1068
1069         ixgbe_dev_macsec_setting_reset(eth_dev);
1070
1071         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1072         eth_dev->rx_queue_count       = ixgbe_dev_rx_queue_count;
1073         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1074         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1075         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1076         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1077         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1078         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1079
1080         /*
1081          * For secondary processes, we don't initialise any further as primary
1082          * has already done this work. Only check we don't need a different
1083          * RX and TX function.
1084          */
1085         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1086                 struct ixgbe_tx_queue *txq;
1087                 /* TX queue function in primary, set by last queue initialized
1088                  * Tx queue may not initialized by primary process
1089                  */
1090                 if (eth_dev->data->tx_queues) {
1091                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1092                         ixgbe_set_tx_function(eth_dev, txq);
1093                 } else {
1094                         /* Use default TX function if we get here */
1095                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1096                                      "Using default TX function.");
1097                 }
1098
1099                 ixgbe_set_rx_function(eth_dev);
1100
1101                 return 0;
1102         }
1103
1104         rte_atomic32_clear(&ad->link_thread_running);
1105         rte_eth_copy_pci_info(eth_dev, pci_dev);
1106         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1107
1108         /* Vendor and Device ID need to be set before init of shared code */
1109         hw->device_id = pci_dev->id.device_id;
1110         hw->vendor_id = pci_dev->id.vendor_id;
1111         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1112         hw->allow_unsupported_sfp = 1;
1113
1114         /* Initialize the shared code (base driver) */
1115 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1116         diag = ixgbe_bypass_init_shared_code(hw);
1117 #else
1118         diag = ixgbe_init_shared_code(hw);
1119 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1120
1121         if (diag != IXGBE_SUCCESS) {
1122                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1123                 return -EIO;
1124         }
1125
1126         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1127                 PMD_INIT_LOG(ERR, "\nERROR: "
1128                         "Firmware recovery mode detected. Limiting functionality.\n"
1129                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1130                         "User Guide for details on firmware recovery mode.");
1131                 return -EIO;
1132         }
1133
1134         /* pick up the PCI bus settings for reporting later */
1135         ixgbe_get_bus_info(hw);
1136
1137         /* Unlock any pending hardware semaphore */
1138         ixgbe_swfw_lock_reset(hw);
1139
1140 #ifdef RTE_LIB_SECURITY
1141         /* Initialize security_ctx only for primary process*/
1142         if (ixgbe_ipsec_ctx_create(eth_dev))
1143                 return -ENOMEM;
1144 #endif
1145
1146         /* Initialize DCB configuration*/
1147         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1148         ixgbe_dcb_init(hw, dcb_config);
1149         /* Get Hardware Flow Control setting */
1150         hw->fc.requested_mode = ixgbe_fc_none;
1151         hw->fc.current_mode = ixgbe_fc_none;
1152         hw->fc.pause_time = IXGBE_FC_PAUSE;
1153         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1154                 hw->fc.low_water[i] = IXGBE_FC_LO;
1155                 hw->fc.high_water[i] = IXGBE_FC_HI;
1156         }
1157         hw->fc.send_xon = 1;
1158
1159         /* Make sure we have a good EEPROM before we read from it */
1160         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1161         if (diag != IXGBE_SUCCESS) {
1162                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1163                 return -EIO;
1164         }
1165
1166 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1167         diag = ixgbe_bypass_init_hw(hw);
1168 #else
1169         diag = ixgbe_init_hw(hw);
1170 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1171
1172         /*
1173          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1174          * is called too soon after the kernel driver unbinding/binding occurs.
1175          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1176          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1177          * also called. See ixgbe_identify_phy_82599(). The reason for the
1178          * failure is not known, and only occuts when virtualisation features
1179          * are disabled in the bios. A delay of 100ms  was found to be enough by
1180          * trial-and-error, and is doubled to be safe.
1181          */
1182         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1183                 rte_delay_ms(200);
1184                 diag = ixgbe_init_hw(hw);
1185         }
1186
1187         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1188                 diag = IXGBE_SUCCESS;
1189
1190         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1191                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1192                              "LOM.  Please be aware there may be issues associated "
1193                              "with your hardware.");
1194                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1195                              "please contact your Intel or hardware representative "
1196                              "who provided you with this hardware.");
1197         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1198                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1199         if (diag) {
1200                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1201                 return -EIO;
1202         }
1203
1204         /* Reset the hw statistics */
1205         ixgbe_dev_stats_reset(eth_dev);
1206
1207         /* disable interrupt */
1208         ixgbe_disable_intr(hw);
1209
1210         /* reset mappings for queue statistics hw counters*/
1211         ixgbe_reset_qstat_mappings(hw);
1212
1213         /* Allocate memory for storing MAC addresses */
1214         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1215                                                hw->mac.num_rar_entries, 0);
1216         if (eth_dev->data->mac_addrs == NULL) {
1217                 PMD_INIT_LOG(ERR,
1218                              "Failed to allocate %u bytes needed to store "
1219                              "MAC addresses",
1220                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1221                 return -ENOMEM;
1222         }
1223         /* Copy the permanent MAC address */
1224         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1225                         &eth_dev->data->mac_addrs[0]);
1226
1227         /* Allocate memory for storing hash filter MAC addresses */
1228         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1229                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1230         if (eth_dev->data->hash_mac_addrs == NULL) {
1231                 PMD_INIT_LOG(ERR,
1232                              "Failed to allocate %d bytes needed to store MAC addresses",
1233                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1234                 return -ENOMEM;
1235         }
1236
1237         /* initialize the vfta */
1238         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1239
1240         /* initialize the hw strip bitmap*/
1241         memset(hwstrip, 0, sizeof(*hwstrip));
1242
1243         /* initialize PF if max_vfs not zero */
1244         ret = ixgbe_pf_host_init(eth_dev);
1245         if (ret) {
1246                 rte_free(eth_dev->data->mac_addrs);
1247                 eth_dev->data->mac_addrs = NULL;
1248                 rte_free(eth_dev->data->hash_mac_addrs);
1249                 eth_dev->data->hash_mac_addrs = NULL;
1250                 return ret;
1251         }
1252
1253         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1254         /* let hardware know driver is loaded */
1255         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1256         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1257         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1258         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1259         IXGBE_WRITE_FLUSH(hw);
1260
1261         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1262                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1263                              (int) hw->mac.type, (int) hw->phy.type,
1264                              (int) hw->phy.sfp_type);
1265         else
1266                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1267                              (int) hw->mac.type, (int) hw->phy.type);
1268
1269         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1270                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1271                      pci_dev->id.device_id);
1272
1273         rte_intr_callback_register(intr_handle,
1274                                    ixgbe_dev_interrupt_handler, eth_dev);
1275
1276         /* enable uio/vfio intr/eventfd mapping */
1277         rte_intr_enable(intr_handle);
1278
1279         /* enable support intr */
1280         ixgbe_enable_intr(eth_dev);
1281
1282         /* initialize filter info */
1283         memset(filter_info, 0,
1284                sizeof(struct ixgbe_filter_info));
1285
1286         /* initialize 5tuple filter list */
1287         TAILQ_INIT(&filter_info->fivetuple_list);
1288
1289         /* initialize flow director filter list & hash */
1290         ixgbe_fdir_filter_init(eth_dev);
1291
1292         /* initialize l2 tunnel filter list & hash */
1293         ixgbe_l2_tn_filter_init(eth_dev);
1294
1295         /* initialize flow filter lists */
1296         ixgbe_filterlist_init();
1297
1298         /* initialize bandwidth configuration info */
1299         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1300
1301         /* initialize Traffic Manager configuration */
1302         ixgbe_tm_conf_init(eth_dev);
1303
1304         return 0;
1305 }
1306
1307 static int
1308 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1309 {
1310         PMD_INIT_FUNC_TRACE();
1311
1312         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1313                 return 0;
1314
1315         ixgbe_dev_close(eth_dev);
1316
1317         return 0;
1318 }
1319
1320 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1321 {
1322         struct ixgbe_filter_info *filter_info =
1323                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1324         struct ixgbe_5tuple_filter *p_5tuple;
1325
1326         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1327                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1328                              p_5tuple,
1329                              entries);
1330                 rte_free(p_5tuple);
1331         }
1332         memset(filter_info->fivetuple_mask, 0,
1333                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1334
1335         return 0;
1336 }
1337
1338 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1339 {
1340         struct ixgbe_hw_fdir_info *fdir_info =
1341                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1342         struct ixgbe_fdir_filter *fdir_filter;
1343
1344                 if (fdir_info->hash_map)
1345                 rte_free(fdir_info->hash_map);
1346         if (fdir_info->hash_handle)
1347                 rte_hash_free(fdir_info->hash_handle);
1348
1349         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1350                 TAILQ_REMOVE(&fdir_info->fdir_list,
1351                              fdir_filter,
1352                              entries);
1353                 rte_free(fdir_filter);
1354         }
1355
1356         return 0;
1357 }
1358
1359 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1360 {
1361         struct ixgbe_l2_tn_info *l2_tn_info =
1362                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1363         struct ixgbe_l2_tn_filter *l2_tn_filter;
1364
1365         if (l2_tn_info->hash_map)
1366                 rte_free(l2_tn_info->hash_map);
1367         if (l2_tn_info->hash_handle)
1368                 rte_hash_free(l2_tn_info->hash_handle);
1369
1370         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1371                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1372                              l2_tn_filter,
1373                              entries);
1374                 rte_free(l2_tn_filter);
1375         }
1376
1377         return 0;
1378 }
1379
1380 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1381 {
1382         struct ixgbe_hw_fdir_info *fdir_info =
1383                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1384         char fdir_hash_name[RTE_HASH_NAMESIZE];
1385         struct rte_hash_parameters fdir_hash_params = {
1386                 .name = fdir_hash_name,
1387                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1388                 .key_len = sizeof(union ixgbe_atr_input),
1389                 .hash_func = rte_hash_crc,
1390                 .hash_func_init_val = 0,
1391                 .socket_id = rte_socket_id(),
1392         };
1393
1394         TAILQ_INIT(&fdir_info->fdir_list);
1395         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1396                  "fdir_%s", eth_dev->device->name);
1397         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1398         if (!fdir_info->hash_handle) {
1399                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1400                 return -EINVAL;
1401         }
1402         fdir_info->hash_map = rte_zmalloc("ixgbe",
1403                                           sizeof(struct ixgbe_fdir_filter *) *
1404                                           IXGBE_MAX_FDIR_FILTER_NUM,
1405                                           0);
1406         if (!fdir_info->hash_map) {
1407                 PMD_INIT_LOG(ERR,
1408                              "Failed to allocate memory for fdir hash map!");
1409                 return -ENOMEM;
1410         }
1411         fdir_info->mask_added = FALSE;
1412
1413         return 0;
1414 }
1415
1416 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1417 {
1418         struct ixgbe_l2_tn_info *l2_tn_info =
1419                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1420         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1421         struct rte_hash_parameters l2_tn_hash_params = {
1422                 .name = l2_tn_hash_name,
1423                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1424                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1425                 .hash_func = rte_hash_crc,
1426                 .hash_func_init_val = 0,
1427                 .socket_id = rte_socket_id(),
1428         };
1429
1430         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1431         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1432                  "l2_tn_%s", eth_dev->device->name);
1433         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1434         if (!l2_tn_info->hash_handle) {
1435                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1436                 return -EINVAL;
1437         }
1438         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1439                                    sizeof(struct ixgbe_l2_tn_filter *) *
1440                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1441                                    0);
1442         if (!l2_tn_info->hash_map) {
1443                 PMD_INIT_LOG(ERR,
1444                         "Failed to allocate memory for L2 TN hash map!");
1445                 return -ENOMEM;
1446         }
1447         l2_tn_info->e_tag_en = FALSE;
1448         l2_tn_info->e_tag_fwd_en = FALSE;
1449         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1450
1451         return 0;
1452 }
1453 /*
1454  * Negotiate mailbox API version with the PF.
1455  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1456  * Then we try to negotiate starting with the most recent one.
1457  * If all negotiation attempts fail, then we will proceed with
1458  * the default one (ixgbe_mbox_api_10).
1459  */
1460 static void
1461 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1462 {
1463         int32_t i;
1464
1465         /* start with highest supported, proceed down */
1466         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1467                 ixgbe_mbox_api_13,
1468                 ixgbe_mbox_api_12,
1469                 ixgbe_mbox_api_11,
1470                 ixgbe_mbox_api_10,
1471         };
1472
1473         for (i = 0;
1474                         i != RTE_DIM(sup_ver) &&
1475                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1476                         i++)
1477                 ;
1478 }
1479
1480 static void
1481 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1482 {
1483         uint64_t random;
1484
1485         /* Set Organizationally Unique Identifier (OUI) prefix. */
1486         mac_addr->addr_bytes[0] = 0x00;
1487         mac_addr->addr_bytes[1] = 0x09;
1488         mac_addr->addr_bytes[2] = 0xC0;
1489         /* Force indication of locally assigned MAC address. */
1490         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1491         /* Generate the last 3 bytes of the MAC address with a random number. */
1492         random = rte_rand();
1493         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1494 }
1495
1496 static int
1497 devarg_handle_int(__rte_unused const char *key, const char *value,
1498                   void *extra_args)
1499 {
1500         uint16_t *n = extra_args;
1501
1502         if (value == NULL || extra_args == NULL)
1503                 return -EINVAL;
1504
1505         *n = (uint16_t)strtoul(value, NULL, 0);
1506         if (*n == USHRT_MAX && errno == ERANGE)
1507                 return -1;
1508
1509         return 0;
1510 }
1511
1512 static void
1513 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1514                       struct rte_devargs *devargs)
1515 {
1516         struct rte_kvargs *kvlist;
1517         uint16_t pflink_fullchk;
1518
1519         if (devargs == NULL)
1520                 return;
1521
1522         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1523         if (kvlist == NULL)
1524                 return;
1525
1526         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1527             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1528                                devarg_handle_int, &pflink_fullchk) == 0 &&
1529             pflink_fullchk == 1)
1530                 adapter->pflink_fullchk = 1;
1531
1532         rte_kvargs_free(kvlist);
1533 }
1534
1535 /*
1536  * Virtual Function device init
1537  */
1538 static int
1539 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1540 {
1541         int diag;
1542         uint32_t tc, tcs;
1543         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1544         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1545         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1546         struct ixgbe_hw *hw =
1547                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1548         struct ixgbe_vfta *shadow_vfta =
1549                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1550         struct ixgbe_hwstrip *hwstrip =
1551                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1552         struct rte_ether_addr *perm_addr =
1553                 (struct rte_ether_addr *)hw->mac.perm_addr;
1554
1555         PMD_INIT_FUNC_TRACE();
1556
1557         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1558         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1559         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1560         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1561         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1562         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1563
1564         /* for secondary processes, we don't initialise any further as primary
1565          * has already done this work. Only check we don't need a different
1566          * RX function
1567          */
1568         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1569                 struct ixgbe_tx_queue *txq;
1570                 /* TX queue function in primary, set by last queue initialized
1571                  * Tx queue may not initialized by primary process
1572                  */
1573                 if (eth_dev->data->tx_queues) {
1574                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1575                         ixgbe_set_tx_function(eth_dev, txq);
1576                 } else {
1577                         /* Use default TX function if we get here */
1578                         PMD_INIT_LOG(NOTICE,
1579                                      "No TX queues configured yet. Using default TX function.");
1580                 }
1581
1582                 ixgbe_set_rx_function(eth_dev);
1583
1584                 return 0;
1585         }
1586
1587         rte_atomic32_clear(&ad->link_thread_running);
1588         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1589                               pci_dev->device.devargs);
1590
1591         rte_eth_copy_pci_info(eth_dev, pci_dev);
1592         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1593
1594         hw->device_id = pci_dev->id.device_id;
1595         hw->vendor_id = pci_dev->id.vendor_id;
1596         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1597
1598         /* initialize the vfta */
1599         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1600
1601         /* initialize the hw strip bitmap*/
1602         memset(hwstrip, 0, sizeof(*hwstrip));
1603
1604         /* Initialize the shared code (base driver) */
1605         diag = ixgbe_init_shared_code(hw);
1606         if (diag != IXGBE_SUCCESS) {
1607                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1608                 return -EIO;
1609         }
1610
1611         /* init_mailbox_params */
1612         hw->mbx.ops.init_params(hw);
1613
1614         /* Reset the hw statistics */
1615         ixgbevf_dev_stats_reset(eth_dev);
1616
1617         /* Disable the interrupts for VF */
1618         ixgbevf_intr_disable(eth_dev);
1619
1620         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1621         diag = hw->mac.ops.reset_hw(hw);
1622
1623         /*
1624          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1625          * the underlying PF driver has not assigned a MAC address to the VF.
1626          * In this case, assign a random MAC address.
1627          */
1628         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1629                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1630                 /*
1631                  * This error code will be propagated to the app by
1632                  * rte_eth_dev_reset, so use a public error code rather than
1633                  * the internal-only IXGBE_ERR_RESET_FAILED
1634                  */
1635                 return -EAGAIN;
1636         }
1637
1638         /* negotiate mailbox API version to use with the PF. */
1639         ixgbevf_negotiate_api(hw);
1640
1641         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1642         ixgbevf_get_queues(hw, &tcs, &tc);
1643
1644         /* Allocate memory for storing MAC addresses */
1645         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1646                                                hw->mac.num_rar_entries, 0);
1647         if (eth_dev->data->mac_addrs == NULL) {
1648                 PMD_INIT_LOG(ERR,
1649                              "Failed to allocate %u bytes needed to store "
1650                              "MAC addresses",
1651                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1652                 return -ENOMEM;
1653         }
1654
1655         /* Generate a random MAC address, if none was assigned by PF. */
1656         if (rte_is_zero_ether_addr(perm_addr)) {
1657                 generate_random_mac_addr(perm_addr);
1658                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1659                 if (diag) {
1660                         rte_free(eth_dev->data->mac_addrs);
1661                         eth_dev->data->mac_addrs = NULL;
1662                         return diag;
1663                 }
1664                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1665                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1666                              "%02x:%02x:%02x:%02x:%02x:%02x",
1667                              perm_addr->addr_bytes[0],
1668                              perm_addr->addr_bytes[1],
1669                              perm_addr->addr_bytes[2],
1670                              perm_addr->addr_bytes[3],
1671                              perm_addr->addr_bytes[4],
1672                              perm_addr->addr_bytes[5]);
1673         }
1674
1675         /* Copy the permanent MAC address */
1676         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1677
1678         /* reset the hardware with the new settings */
1679         diag = hw->mac.ops.start_hw(hw);
1680         switch (diag) {
1681         case  0:
1682                 break;
1683
1684         default:
1685                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1686                 return -EIO;
1687         }
1688
1689         rte_intr_callback_register(intr_handle,
1690                                    ixgbevf_dev_interrupt_handler, eth_dev);
1691         rte_intr_enable(intr_handle);
1692         ixgbevf_intr_enable(eth_dev);
1693
1694         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1695                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1696                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1697
1698         return 0;
1699 }
1700
1701 /* Virtual Function device uninit */
1702
1703 static int
1704 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1705 {
1706         PMD_INIT_FUNC_TRACE();
1707
1708         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1709                 return 0;
1710
1711         ixgbevf_dev_close(eth_dev);
1712
1713         return 0;
1714 }
1715
1716 static int
1717 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1718                 struct rte_pci_device *pci_dev)
1719 {
1720         char name[RTE_ETH_NAME_MAX_LEN];
1721         struct rte_eth_dev *pf_ethdev;
1722         struct rte_eth_devargs eth_da;
1723         int i, retval;
1724
1725         if (pci_dev->device.devargs) {
1726                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1727                                 &eth_da);
1728                 if (retval)
1729                         return retval;
1730         } else
1731                 memset(&eth_da, 0, sizeof(eth_da));
1732
1733         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1734                 sizeof(struct ixgbe_adapter),
1735                 eth_dev_pci_specific_init, pci_dev,
1736                 eth_ixgbe_dev_init, NULL);
1737
1738         if (retval || eth_da.nb_representor_ports < 1)
1739                 return retval;
1740
1741         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1742         if (pf_ethdev == NULL)
1743                 return -ENODEV;
1744
1745         /* probe VF representor ports */
1746         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1747                 struct ixgbe_vf_info *vfinfo;
1748                 struct ixgbe_vf_representor representor;
1749
1750                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1751                         pf_ethdev->data->dev_private);
1752                 if (vfinfo == NULL) {
1753                         PMD_DRV_LOG(ERR,
1754                                 "no virtual functions supported by PF");
1755                         break;
1756                 }
1757
1758                 representor.vf_id = eth_da.representor_ports[i];
1759                 representor.switch_domain_id = vfinfo->switch_domain_id;
1760                 representor.pf_ethdev = pf_ethdev;
1761
1762                 /* representor port net_bdf_port */
1763                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1764                         pci_dev->device.name,
1765                         eth_da.representor_ports[i]);
1766
1767                 retval = rte_eth_dev_create(&pci_dev->device, name,
1768                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1769                         ixgbe_vf_representor_init, &representor);
1770
1771                 if (retval)
1772                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1773                                 "representor %s.", name);
1774         }
1775
1776         return 0;
1777 }
1778
1779 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1780 {
1781         struct rte_eth_dev *ethdev;
1782
1783         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1784         if (!ethdev)
1785                 return 0;
1786
1787         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1788                 return rte_eth_dev_pci_generic_remove(pci_dev,
1789                                         ixgbe_vf_representor_uninit);
1790         else
1791                 return rte_eth_dev_pci_generic_remove(pci_dev,
1792                                                 eth_ixgbe_dev_uninit);
1793 }
1794
1795 static struct rte_pci_driver rte_ixgbe_pmd = {
1796         .id_table = pci_id_ixgbe_map,
1797         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1798         .probe = eth_ixgbe_pci_probe,
1799         .remove = eth_ixgbe_pci_remove,
1800 };
1801
1802 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1803         struct rte_pci_device *pci_dev)
1804 {
1805         return rte_eth_dev_pci_generic_probe(pci_dev,
1806                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1807 }
1808
1809 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1810 {
1811         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1812 }
1813
1814 /*
1815  * virtual function driver struct
1816  */
1817 static struct rte_pci_driver rte_ixgbevf_pmd = {
1818         .id_table = pci_id_ixgbevf_map,
1819         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1820         .probe = eth_ixgbevf_pci_probe,
1821         .remove = eth_ixgbevf_pci_remove,
1822 };
1823
1824 static int
1825 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1826 {
1827         struct ixgbe_hw *hw =
1828                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1829         struct ixgbe_vfta *shadow_vfta =
1830                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1831         uint32_t vfta;
1832         uint32_t vid_idx;
1833         uint32_t vid_bit;
1834
1835         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1836         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1837         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1838         if (on)
1839                 vfta |= vid_bit;
1840         else
1841                 vfta &= ~vid_bit;
1842         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1843
1844         /* update local VFTA copy */
1845         shadow_vfta->vfta[vid_idx] = vfta;
1846
1847         return 0;
1848 }
1849
1850 static void
1851 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1852 {
1853         if (on)
1854                 ixgbe_vlan_hw_strip_enable(dev, queue);
1855         else
1856                 ixgbe_vlan_hw_strip_disable(dev, queue);
1857 }
1858
1859 static int
1860 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1861                     enum rte_vlan_type vlan_type,
1862                     uint16_t tpid)
1863 {
1864         struct ixgbe_hw *hw =
1865                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1866         int ret = 0;
1867         uint32_t reg;
1868         uint32_t qinq;
1869
1870         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1871         qinq &= IXGBE_DMATXCTL_GDV;
1872
1873         switch (vlan_type) {
1874         case ETH_VLAN_TYPE_INNER:
1875                 if (qinq) {
1876                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1877                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1878                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1879                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1880                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1881                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1882                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1883                 } else {
1884                         ret = -ENOTSUP;
1885                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1886                                     " by single VLAN");
1887                 }
1888                 break;
1889         case ETH_VLAN_TYPE_OUTER:
1890                 if (qinq) {
1891                         /* Only the high 16-bits is valid */
1892                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1893                                         IXGBE_EXVET_VET_EXT_SHIFT);
1894                 } else {
1895                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1896                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1897                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1898                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1899                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1900                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1901                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1902                 }
1903
1904                 break;
1905         default:
1906                 ret = -EINVAL;
1907                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1908                 break;
1909         }
1910
1911         return ret;
1912 }
1913
1914 void
1915 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1916 {
1917         struct ixgbe_hw *hw =
1918                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1919         uint32_t vlnctrl;
1920
1921         PMD_INIT_FUNC_TRACE();
1922
1923         /* Filter Table Disable */
1924         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1925         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1926
1927         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1928 }
1929
1930 void
1931 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1932 {
1933         struct ixgbe_hw *hw =
1934                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1935         struct ixgbe_vfta *shadow_vfta =
1936                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1937         uint32_t vlnctrl;
1938         uint16_t i;
1939
1940         PMD_INIT_FUNC_TRACE();
1941
1942         /* Filter Table Enable */
1943         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1944         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1945         vlnctrl |= IXGBE_VLNCTRL_VFE;
1946
1947         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1948
1949         /* write whatever is in local vfta copy */
1950         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1951                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1952 }
1953
1954 static void
1955 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1956 {
1957         struct ixgbe_hwstrip *hwstrip =
1958                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1959         struct ixgbe_rx_queue *rxq;
1960
1961         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1962                 return;
1963
1964         if (on)
1965                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1966         else
1967                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1968
1969         if (queue >= dev->data->nb_rx_queues)
1970                 return;
1971
1972         rxq = dev->data->rx_queues[queue];
1973
1974         if (on) {
1975                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1976                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1977         } else {
1978                 rxq->vlan_flags = PKT_RX_VLAN;
1979                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1980         }
1981 }
1982
1983 static void
1984 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1985 {
1986         struct ixgbe_hw *hw =
1987                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1988         uint32_t ctrl;
1989
1990         PMD_INIT_FUNC_TRACE();
1991
1992         if (hw->mac.type == ixgbe_mac_82598EB) {
1993                 /* No queue level support */
1994                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1995                 return;
1996         }
1997
1998         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1999         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2000         ctrl &= ~IXGBE_RXDCTL_VME;
2001         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2002
2003         /* record those setting for HW strip per queue */
2004         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2005 }
2006
2007 static void
2008 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2009 {
2010         struct ixgbe_hw *hw =
2011                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2012         uint32_t ctrl;
2013
2014         PMD_INIT_FUNC_TRACE();
2015
2016         if (hw->mac.type == ixgbe_mac_82598EB) {
2017                 /* No queue level supported */
2018                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2019                 return;
2020         }
2021
2022         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2023         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2024         ctrl |= IXGBE_RXDCTL_VME;
2025         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2026
2027         /* record those setting for HW strip per queue */
2028         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2029 }
2030
2031 static void
2032 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2033 {
2034         struct ixgbe_hw *hw =
2035                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2036         uint32_t ctrl;
2037
2038         PMD_INIT_FUNC_TRACE();
2039
2040         /* DMATXCTRL: Geric Double VLAN Disable */
2041         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2042         ctrl &= ~IXGBE_DMATXCTL_GDV;
2043         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2044
2045         /* CTRL_EXT: Global Double VLAN Disable */
2046         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2047         ctrl &= ~IXGBE_EXTENDED_VLAN;
2048         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2049
2050 }
2051
2052 static void
2053 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2054 {
2055         struct ixgbe_hw *hw =
2056                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2057         uint32_t ctrl;
2058
2059         PMD_INIT_FUNC_TRACE();
2060
2061         /* DMATXCTRL: Geric Double VLAN Enable */
2062         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2063         ctrl |= IXGBE_DMATXCTL_GDV;
2064         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2065
2066         /* CTRL_EXT: Global Double VLAN Enable */
2067         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2068         ctrl |= IXGBE_EXTENDED_VLAN;
2069         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2070
2071         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2072         if (hw->mac.type == ixgbe_mac_X550 ||
2073             hw->mac.type == ixgbe_mac_X550EM_x ||
2074             hw->mac.type == ixgbe_mac_X550EM_a) {
2075                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2076                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2077                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2078         }
2079
2080         /*
2081          * VET EXT field in the EXVET register = 0x8100 by default
2082          * So no need to change. Same to VT field of DMATXCTL register
2083          */
2084 }
2085
2086 void
2087 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2088 {
2089         struct ixgbe_hw *hw =
2090                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2091         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2092         uint32_t ctrl;
2093         uint16_t i;
2094         struct ixgbe_rx_queue *rxq;
2095         bool on;
2096
2097         PMD_INIT_FUNC_TRACE();
2098
2099         if (hw->mac.type == ixgbe_mac_82598EB) {
2100                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2101                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2102                         ctrl |= IXGBE_VLNCTRL_VME;
2103                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2104                 } else {
2105                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2106                         ctrl &= ~IXGBE_VLNCTRL_VME;
2107                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2108                 }
2109         } else {
2110                 /*
2111                  * Other 10G NIC, the VLAN strip can be setup
2112                  * per queue in RXDCTL
2113                  */
2114                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2115                         rxq = dev->data->rx_queues[i];
2116                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2117                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2118                                 ctrl |= IXGBE_RXDCTL_VME;
2119                                 on = TRUE;
2120                         } else {
2121                                 ctrl &= ~IXGBE_RXDCTL_VME;
2122                                 on = FALSE;
2123                         }
2124                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2125
2126                         /* record those setting for HW strip per queue */
2127                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2128                 }
2129         }
2130 }
2131
2132 static void
2133 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2134 {
2135         uint16_t i;
2136         struct rte_eth_rxmode *rxmode;
2137         struct ixgbe_rx_queue *rxq;
2138
2139         if (mask & ETH_VLAN_STRIP_MASK) {
2140                 rxmode = &dev->data->dev_conf.rxmode;
2141                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2142                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2143                                 rxq = dev->data->rx_queues[i];
2144                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2145                         }
2146                 else
2147                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2148                                 rxq = dev->data->rx_queues[i];
2149                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2150                         }
2151         }
2152 }
2153
2154 static int
2155 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2156 {
2157         struct rte_eth_rxmode *rxmode;
2158         rxmode = &dev->data->dev_conf.rxmode;
2159
2160         if (mask & ETH_VLAN_STRIP_MASK) {
2161                 ixgbe_vlan_hw_strip_config(dev);
2162         }
2163
2164         if (mask & ETH_VLAN_FILTER_MASK) {
2165                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2166                         ixgbe_vlan_hw_filter_enable(dev);
2167                 else
2168                         ixgbe_vlan_hw_filter_disable(dev);
2169         }
2170
2171         if (mask & ETH_VLAN_EXTEND_MASK) {
2172                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2173                         ixgbe_vlan_hw_extend_enable(dev);
2174                 else
2175                         ixgbe_vlan_hw_extend_disable(dev);
2176         }
2177
2178         return 0;
2179 }
2180
2181 static int
2182 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2183 {
2184         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2185
2186         ixgbe_vlan_offload_config(dev, mask);
2187
2188         return 0;
2189 }
2190
2191 static void
2192 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2193 {
2194         struct ixgbe_hw *hw =
2195                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2196         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2197         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2198
2199         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2200         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2201 }
2202
2203 static int
2204 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2205 {
2206         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2207
2208         switch (nb_rx_q) {
2209         case 1:
2210         case 2:
2211                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2212                 break;
2213         case 4:
2214                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2215                 break;
2216         default:
2217                 return -EINVAL;
2218         }
2219
2220         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2221                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2222         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2223                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2224         return 0;
2225 }
2226
2227 static int
2228 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2229 {
2230         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2231         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2232         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2233         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2234
2235         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2236                 /* check multi-queue mode */
2237                 switch (dev_conf->rxmode.mq_mode) {
2238                 case ETH_MQ_RX_VMDQ_DCB:
2239                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2240                         break;
2241                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2242                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2243                         PMD_INIT_LOG(ERR, "SRIOV active,"
2244                                         " unsupported mq_mode rx %d.",
2245                                         dev_conf->rxmode.mq_mode);
2246                         return -EINVAL;
2247                 case ETH_MQ_RX_RSS:
2248                 case ETH_MQ_RX_VMDQ_RSS:
2249                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2250                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2251                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2252                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2253                                                 " invalid queue number"
2254                                                 " for VMDQ RSS, allowed"
2255                                                 " value are 1, 2 or 4.");
2256                                         return -EINVAL;
2257                                 }
2258                         break;
2259                 case ETH_MQ_RX_VMDQ_ONLY:
2260                 case ETH_MQ_RX_NONE:
2261                         /* if nothing mq mode configure, use default scheme */
2262                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2263                         break;
2264                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2265                         /* SRIOV only works in VMDq enable mode */
2266                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2267                                         " wrong mq_mode rx %d.",
2268                                         dev_conf->rxmode.mq_mode);
2269                         return -EINVAL;
2270                 }
2271
2272                 switch (dev_conf->txmode.mq_mode) {
2273                 case ETH_MQ_TX_VMDQ_DCB:
2274                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2275                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2276                         break;
2277                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2278                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2279                         break;
2280                 }
2281
2282                 /* check valid queue number */
2283                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2284                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2285                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2286                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2287                                         " must be less than or equal to %d.",
2288                                         nb_rx_q, nb_tx_q,
2289                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2290                         return -EINVAL;
2291                 }
2292         } else {
2293                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2294                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2295                                           " not supported.");
2296                         return -EINVAL;
2297                 }
2298                 /* check configuration for vmdb+dcb mode */
2299                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2300                         const struct rte_eth_vmdq_dcb_conf *conf;
2301
2302                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2303                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2304                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2305                                 return -EINVAL;
2306                         }
2307                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2308                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2309                                conf->nb_queue_pools == ETH_32_POOLS)) {
2310                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2311                                                 " nb_queue_pools must be %d or %d.",
2312                                                 ETH_16_POOLS, ETH_32_POOLS);
2313                                 return -EINVAL;
2314                         }
2315                 }
2316                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2317                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2318
2319                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2320                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2321                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2322                                 return -EINVAL;
2323                         }
2324                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2325                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2326                                conf->nb_queue_pools == ETH_32_POOLS)) {
2327                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2328                                                 " nb_queue_pools != %d and"
2329                                                 " nb_queue_pools != %d.",
2330                                                 ETH_16_POOLS, ETH_32_POOLS);
2331                                 return -EINVAL;
2332                         }
2333                 }
2334
2335                 /* For DCB mode check our configuration before we go further */
2336                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2337                         const struct rte_eth_dcb_rx_conf *conf;
2338
2339                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2340                         if (!(conf->nb_tcs == ETH_4_TCS ||
2341                                conf->nb_tcs == ETH_8_TCS)) {
2342                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2343                                                 " and nb_tcs != %d.",
2344                                                 ETH_4_TCS, ETH_8_TCS);
2345                                 return -EINVAL;
2346                         }
2347                 }
2348
2349                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2350                         const struct rte_eth_dcb_tx_conf *conf;
2351
2352                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2353                         if (!(conf->nb_tcs == ETH_4_TCS ||
2354                                conf->nb_tcs == ETH_8_TCS)) {
2355                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2356                                                 " and nb_tcs != %d.",
2357                                                 ETH_4_TCS, ETH_8_TCS);
2358                                 return -EINVAL;
2359                         }
2360                 }
2361
2362                 /*
2363                  * When DCB/VT is off, maximum number of queues changes,
2364                  * except for 82598EB, which remains constant.
2365                  */
2366                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2367                                 hw->mac.type != ixgbe_mac_82598EB) {
2368                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2369                                 PMD_INIT_LOG(ERR,
2370                                              "Neither VT nor DCB are enabled, "
2371                                              "nb_tx_q > %d.",
2372                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2373                                 return -EINVAL;
2374                         }
2375                 }
2376         }
2377         return 0;
2378 }
2379
2380 static int
2381 ixgbe_dev_configure(struct rte_eth_dev *dev)
2382 {
2383         struct ixgbe_interrupt *intr =
2384                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2385         struct ixgbe_adapter *adapter = dev->data->dev_private;
2386         int ret;
2387
2388         PMD_INIT_FUNC_TRACE();
2389
2390         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2391                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2392
2393         /* multipe queue mode checking */
2394         ret  = ixgbe_check_mq_mode(dev);
2395         if (ret != 0) {
2396                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2397                             ret);
2398                 return ret;
2399         }
2400
2401         /* set flag to update link status after init */
2402         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2403
2404         /*
2405          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2406          * allocation or vector Rx preconditions we will reset it.
2407          */
2408         adapter->rx_bulk_alloc_allowed = true;
2409         adapter->rx_vec_allowed = true;
2410
2411         return 0;
2412 }
2413
2414 static void
2415 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2416 {
2417         struct ixgbe_hw *hw =
2418                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2419         struct ixgbe_interrupt *intr =
2420                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2421         uint32_t gpie;
2422
2423         /* only set up it on X550EM_X */
2424         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2425                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2426                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2427                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2428                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2429                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2430         }
2431 }
2432
2433 int
2434 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2435                         uint16_t tx_rate, uint64_t q_msk)
2436 {
2437         struct ixgbe_hw *hw;
2438         struct ixgbe_vf_info *vfinfo;
2439         struct rte_eth_link link;
2440         uint8_t  nb_q_per_pool;
2441         uint32_t queue_stride;
2442         uint32_t queue_idx, idx = 0, vf_idx;
2443         uint32_t queue_end;
2444         uint16_t total_rate = 0;
2445         struct rte_pci_device *pci_dev;
2446         int ret;
2447
2448         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2449         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2450         if (ret < 0)
2451                 return ret;
2452
2453         if (vf >= pci_dev->max_vfs)
2454                 return -EINVAL;
2455
2456         if (tx_rate > link.link_speed)
2457                 return -EINVAL;
2458
2459         if (q_msk == 0)
2460                 return 0;
2461
2462         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2463         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2464         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2465         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2466         queue_idx = vf * queue_stride;
2467         queue_end = queue_idx + nb_q_per_pool - 1;
2468         if (queue_end >= hw->mac.max_tx_queues)
2469                 return -EINVAL;
2470
2471         if (vfinfo) {
2472                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2473                         if (vf_idx == vf)
2474                                 continue;
2475                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2476                                 idx++)
2477                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2478                 }
2479         } else {
2480                 return -EINVAL;
2481         }
2482
2483         /* Store tx_rate for this vf. */
2484         for (idx = 0; idx < nb_q_per_pool; idx++) {
2485                 if (((uint64_t)0x1 << idx) & q_msk) {
2486                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2487                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2488                         total_rate += tx_rate;
2489                 }
2490         }
2491
2492         if (total_rate > dev->data->dev_link.link_speed) {
2493                 /* Reset stored TX rate of the VF if it causes exceed
2494                  * link speed.
2495                  */
2496                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2497                 return -EINVAL;
2498         }
2499
2500         /* Set RTTBCNRC of each queue/pool for vf X  */
2501         for (; queue_idx <= queue_end; queue_idx++) {
2502                 if (0x1 & q_msk)
2503                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2504                 q_msk = q_msk >> 1;
2505         }
2506
2507         return 0;
2508 }
2509
2510 static int
2511 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2512 {
2513         struct ixgbe_adapter *adapter = dev->data->dev_private;
2514         int err;
2515         uint32_t mflcn;
2516
2517         ixgbe_setup_fc(hw);
2518
2519         err = ixgbe_fc_enable(hw);
2520
2521         /* Not negotiated is not an error case */
2522         if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2523                 /*
2524                  *check if we want to forward MAC frames - driver doesn't
2525                  *have native capability to do that,
2526                  *so we'll write the registers ourselves
2527                  */
2528
2529                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2530
2531                 /* set or clear MFLCN.PMCF bit depending on configuration */
2532                 if (adapter->mac_ctrl_frame_fwd != 0)
2533                         mflcn |= IXGBE_MFLCN_PMCF;
2534                 else
2535                         mflcn &= ~IXGBE_MFLCN_PMCF;
2536
2537                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2538                 IXGBE_WRITE_FLUSH(hw);
2539
2540                 return 0;
2541         }
2542         return err;
2543 }
2544
2545 /*
2546  * Configure device link speed and setup link.
2547  * It returns 0 on success.
2548  */
2549 static int
2550 ixgbe_dev_start(struct rte_eth_dev *dev)
2551 {
2552         struct ixgbe_hw *hw =
2553                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2554         struct ixgbe_vf_info *vfinfo =
2555                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2556         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2557         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2558         uint32_t intr_vector = 0;
2559         int err;
2560         bool link_up = false, negotiate = 0;
2561         uint32_t speed = 0;
2562         uint32_t allowed_speeds = 0;
2563         int mask = 0;
2564         int status;
2565         uint16_t vf, idx;
2566         uint32_t *link_speeds;
2567         struct ixgbe_tm_conf *tm_conf =
2568                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2569         struct ixgbe_macsec_setting *macsec_setting =
2570                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2571
2572         PMD_INIT_FUNC_TRACE();
2573
2574         /* Stop the link setup handler before resetting the HW. */
2575         ixgbe_dev_wait_setup_link_complete(dev, 0);
2576
2577         /* disable uio/vfio intr/eventfd mapping */
2578         rte_intr_disable(intr_handle);
2579
2580         /* stop adapter */
2581         hw->adapter_stopped = 0;
2582         ixgbe_stop_adapter(hw);
2583
2584         /* reinitialize adapter
2585          * this calls reset and start
2586          */
2587         status = ixgbe_pf_reset_hw(hw);
2588         if (status != 0)
2589                 return -1;
2590         hw->mac.ops.start_hw(hw);
2591         hw->mac.get_link_status = true;
2592
2593         /* configure PF module if SRIOV enabled */
2594         ixgbe_pf_host_configure(dev);
2595
2596         ixgbe_dev_phy_intr_setup(dev);
2597
2598         /* check and configure queue intr-vector mapping */
2599         if ((rte_intr_cap_multiple(intr_handle) ||
2600              !RTE_ETH_DEV_SRIOV(dev).active) &&
2601             dev->data->dev_conf.intr_conf.rxq != 0) {
2602                 intr_vector = dev->data->nb_rx_queues;
2603                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2604                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2605                                         IXGBE_MAX_INTR_QUEUE_NUM);
2606                         return -ENOTSUP;
2607                 }
2608                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2609                         return -1;
2610         }
2611
2612         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2613                 intr_handle->intr_vec =
2614                         rte_zmalloc("intr_vec",
2615                                     dev->data->nb_rx_queues * sizeof(int), 0);
2616                 if (intr_handle->intr_vec == NULL) {
2617                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2618                                      " intr_vec", dev->data->nb_rx_queues);
2619                         return -ENOMEM;
2620                 }
2621         }
2622
2623         /* confiugre msix for sleep until rx interrupt */
2624         ixgbe_configure_msix(dev);
2625
2626         /* initialize transmission unit */
2627         ixgbe_dev_tx_init(dev);
2628
2629         /* This can fail when allocating mbufs for descriptor rings */
2630         err = ixgbe_dev_rx_init(dev);
2631         if (err) {
2632                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2633                 goto error;
2634         }
2635
2636         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2637                 ETH_VLAN_EXTEND_MASK;
2638         err = ixgbe_vlan_offload_config(dev, mask);
2639         if (err) {
2640                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2641                 goto error;
2642         }
2643
2644         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2645                 /* Enable vlan filtering for VMDq */
2646                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2647         }
2648
2649         /* Configure DCB hw */
2650         ixgbe_configure_dcb(dev);
2651
2652         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2653                 err = ixgbe_fdir_configure(dev);
2654                 if (err)
2655                         goto error;
2656         }
2657
2658         /* Restore vf rate limit */
2659         if (vfinfo != NULL) {
2660                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2661                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2662                                 if (vfinfo[vf].tx_rate[idx] != 0)
2663                                         ixgbe_set_vf_rate_limit(
2664                                                 dev, vf,
2665                                                 vfinfo[vf].tx_rate[idx],
2666                                                 1 << idx);
2667         }
2668
2669         ixgbe_restore_statistics_mapping(dev);
2670
2671         err = ixgbe_flow_ctrl_enable(dev, hw);
2672         if (err < 0) {
2673                 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2674                 goto error;
2675         }
2676
2677         err = ixgbe_dev_rxtx_start(dev);
2678         if (err < 0) {
2679                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2680                 goto error;
2681         }
2682
2683         /* Skip link setup if loopback mode is enabled. */
2684         if (dev->data->dev_conf.lpbk_mode != 0) {
2685                 err = ixgbe_check_supported_loopback_mode(dev);
2686                 if (err < 0) {
2687                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2688                         goto error;
2689                 } else {
2690                         goto skip_link_setup;
2691                 }
2692         }
2693
2694         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2695                 err = hw->mac.ops.setup_sfp(hw);
2696                 if (err)
2697                         goto error;
2698         }
2699
2700         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2701                 /* Turn on the copper */
2702                 ixgbe_set_phy_power(hw, true);
2703         } else {
2704                 /* Turn on the laser */
2705                 ixgbe_enable_tx_laser(hw);
2706         }
2707
2708         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2709         if (err)
2710                 goto error;
2711         dev->data->dev_link.link_status = link_up;
2712
2713         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2714         if (err)
2715                 goto error;
2716
2717         switch (hw->mac.type) {
2718         case ixgbe_mac_X550:
2719         case ixgbe_mac_X550EM_x:
2720         case ixgbe_mac_X550EM_a:
2721                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2722                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2723                         ETH_LINK_SPEED_10G;
2724                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2725                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2726                         allowed_speeds = ETH_LINK_SPEED_10M |
2727                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2728                 break;
2729         default:
2730                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2731                         ETH_LINK_SPEED_10G;
2732         }
2733
2734         link_speeds = &dev->data->dev_conf.link_speeds;
2735
2736         /* Ignore autoneg flag bit and check the validity of
2737          * link_speed
2738          */
2739         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2740                 PMD_INIT_LOG(ERR, "Invalid link setting");
2741                 goto error;
2742         }
2743
2744         speed = 0x0;
2745         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2746                 switch (hw->mac.type) {
2747                 case ixgbe_mac_82598EB:
2748                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2749                         break;
2750                 case ixgbe_mac_82599EB:
2751                 case ixgbe_mac_X540:
2752                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2753                         break;
2754                 case ixgbe_mac_X550:
2755                 case ixgbe_mac_X550EM_x:
2756                 case ixgbe_mac_X550EM_a:
2757                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2758                         break;
2759                 default:
2760                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2761                 }
2762         } else {
2763                 if (*link_speeds & ETH_LINK_SPEED_10G)
2764                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2765                 if (*link_speeds & ETH_LINK_SPEED_5G)
2766                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2767                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2768                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2769                 if (*link_speeds & ETH_LINK_SPEED_1G)
2770                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2771                 if (*link_speeds & ETH_LINK_SPEED_100M)
2772                         speed |= IXGBE_LINK_SPEED_100_FULL;
2773                 if (*link_speeds & ETH_LINK_SPEED_10M)
2774                         speed |= IXGBE_LINK_SPEED_10_FULL;
2775         }
2776
2777         err = ixgbe_setup_link(hw, speed, link_up);
2778         if (err)
2779                 goto error;
2780
2781 skip_link_setup:
2782
2783         if (rte_intr_allow_others(intr_handle)) {
2784                 /* check if lsc interrupt is enabled */
2785                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2786                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2787                 else
2788                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2789                 ixgbe_dev_macsec_interrupt_setup(dev);
2790         } else {
2791                 rte_intr_callback_unregister(intr_handle,
2792                                              ixgbe_dev_interrupt_handler, dev);
2793                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2794                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2795                                      " no intr multiplex");
2796         }
2797
2798         /* check if rxq interrupt is enabled */
2799         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2800             rte_intr_dp_is_en(intr_handle))
2801                 ixgbe_dev_rxq_interrupt_setup(dev);
2802
2803         /* enable uio/vfio intr/eventfd mapping */
2804         rte_intr_enable(intr_handle);
2805
2806         /* resume enabled intr since hw reset */
2807         ixgbe_enable_intr(dev);
2808         ixgbe_l2_tunnel_conf(dev);
2809         ixgbe_filter_restore(dev);
2810
2811         if (tm_conf->root && !tm_conf->committed)
2812                 PMD_DRV_LOG(WARNING,
2813                             "please call hierarchy_commit() "
2814                             "before starting the port");
2815
2816         /* wait for the controller to acquire link */
2817         err = ixgbe_wait_for_link_up(hw);
2818         if (err)
2819                 goto error;
2820
2821         /*
2822          * Update link status right before return, because it may
2823          * start link configuration process in a separate thread.
2824          */
2825         ixgbe_dev_link_update(dev, 0);
2826
2827         /* setup the macsec setting register */
2828         if (macsec_setting->offload_en)
2829                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2830
2831         return 0;
2832
2833 error:
2834         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2835         ixgbe_dev_clear_queues(dev);
2836         return -EIO;
2837 }
2838
2839 /*
2840  * Stop device: disable rx and tx functions to allow for reconfiguring.
2841  */
2842 static int
2843 ixgbe_dev_stop(struct rte_eth_dev *dev)
2844 {
2845         struct rte_eth_link link;
2846         struct ixgbe_adapter *adapter = dev->data->dev_private;
2847         struct ixgbe_hw *hw =
2848                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2849         struct ixgbe_vf_info *vfinfo =
2850                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2851         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2852         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2853         int vf;
2854         struct ixgbe_tm_conf *tm_conf =
2855                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2856
2857         if (hw->adapter_stopped)
2858                 return 0;
2859
2860         PMD_INIT_FUNC_TRACE();
2861
2862         ixgbe_dev_wait_setup_link_complete(dev, 0);
2863
2864         /* disable interrupts */
2865         ixgbe_disable_intr(hw);
2866
2867         /* reset the NIC */
2868         ixgbe_pf_reset_hw(hw);
2869         hw->adapter_stopped = 0;
2870
2871         /* stop adapter */
2872         ixgbe_stop_adapter(hw);
2873
2874         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2875                 vfinfo[vf].clear_to_send = false;
2876
2877         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2878                 /* Turn off the copper */
2879                 ixgbe_set_phy_power(hw, false);
2880         } else {
2881                 /* Turn off the laser */
2882                 ixgbe_disable_tx_laser(hw);
2883         }
2884
2885         ixgbe_dev_clear_queues(dev);
2886
2887         /* Clear stored conf */
2888         dev->data->scattered_rx = 0;
2889         dev->data->lro = 0;
2890
2891         /* Clear recorded link status */
2892         memset(&link, 0, sizeof(link));
2893         rte_eth_linkstatus_set(dev, &link);
2894
2895         if (!rte_intr_allow_others(intr_handle))
2896                 /* resume to the default handler */
2897                 rte_intr_callback_register(intr_handle,
2898                                            ixgbe_dev_interrupt_handler,
2899                                            (void *)dev);
2900
2901         /* Clean datapath event and queue/vec mapping */
2902         rte_intr_efd_disable(intr_handle);
2903         if (intr_handle->intr_vec != NULL) {
2904                 rte_free(intr_handle->intr_vec);
2905                 intr_handle->intr_vec = NULL;
2906         }
2907
2908         /* reset hierarchy commit */
2909         tm_conf->committed = false;
2910
2911         adapter->rss_reta_updated = 0;
2912
2913         hw->adapter_stopped = true;
2914         dev->data->dev_started = 0;
2915
2916         return 0;
2917 }
2918
2919 /*
2920  * Set device link up: enable tx.
2921  */
2922 static int
2923 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2924 {
2925         struct ixgbe_hw *hw =
2926                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2927         if (hw->mac.type == ixgbe_mac_82599EB) {
2928 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2929                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2930                         /* Not suported in bypass mode */
2931                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2932                                      "by device id 0x%x", hw->device_id);
2933                         return -ENOTSUP;
2934                 }
2935 #endif
2936         }
2937
2938         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2939                 /* Turn on the copper */
2940                 ixgbe_set_phy_power(hw, true);
2941         } else {
2942                 /* Turn on the laser */
2943                 ixgbe_enable_tx_laser(hw);
2944                 ixgbe_dev_link_update(dev, 0);
2945         }
2946
2947         return 0;
2948 }
2949
2950 /*
2951  * Set device link down: disable tx.
2952  */
2953 static int
2954 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2955 {
2956         struct ixgbe_hw *hw =
2957                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2958         if (hw->mac.type == ixgbe_mac_82599EB) {
2959 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2960                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2961                         /* Not suported in bypass mode */
2962                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2963                                      "by device id 0x%x", hw->device_id);
2964                         return -ENOTSUP;
2965                 }
2966 #endif
2967         }
2968
2969         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2970                 /* Turn off the copper */
2971                 ixgbe_set_phy_power(hw, false);
2972         } else {
2973                 /* Turn off the laser */
2974                 ixgbe_disable_tx_laser(hw);
2975                 ixgbe_dev_link_update(dev, 0);
2976         }
2977
2978         return 0;
2979 }
2980
2981 /*
2982  * Reset and stop device.
2983  */
2984 static int
2985 ixgbe_dev_close(struct rte_eth_dev *dev)
2986 {
2987         struct ixgbe_hw *hw =
2988                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2989         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2990         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2991         int retries = 0;
2992         int ret;
2993
2994         PMD_INIT_FUNC_TRACE();
2995         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2996                 return 0;
2997
2998         ixgbe_pf_reset_hw(hw);
2999
3000         ret = ixgbe_dev_stop(dev);
3001
3002         ixgbe_dev_free_queues(dev);
3003
3004         ixgbe_disable_pcie_master(hw);
3005
3006         /* reprogram the RAR[0] in case user changed it. */
3007         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3008
3009         /* Unlock any pending hardware semaphore */
3010         ixgbe_swfw_lock_reset(hw);
3011
3012         /* disable uio intr before callback unregister */
3013         rte_intr_disable(intr_handle);
3014
3015         do {
3016                 ret = rte_intr_callback_unregister(intr_handle,
3017                                 ixgbe_dev_interrupt_handler, dev);
3018                 if (ret >= 0 || ret == -ENOENT) {
3019                         break;
3020                 } else if (ret != -EAGAIN) {
3021                         PMD_INIT_LOG(ERR,
3022                                 "intr callback unregister failed: %d",
3023                                 ret);
3024                 }
3025                 rte_delay_ms(100);
3026         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3027
3028         /* cancel the delay handler before remove dev */
3029         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3030
3031         /* uninitialize PF if max_vfs not zero */
3032         ixgbe_pf_host_uninit(dev);
3033
3034         /* remove all the fdir filters & hash */
3035         ixgbe_fdir_filter_uninit(dev);
3036
3037         /* remove all the L2 tunnel filters & hash */
3038         ixgbe_l2_tn_filter_uninit(dev);
3039
3040         /* Remove all ntuple filters of the device */
3041         ixgbe_ntuple_filter_uninit(dev);
3042
3043         /* clear all the filters list */
3044         ixgbe_filterlist_flush();
3045
3046         /* Remove all Traffic Manager configuration */
3047         ixgbe_tm_conf_uninit(dev);
3048
3049 #ifdef RTE_LIB_SECURITY
3050         rte_free(dev->security_ctx);
3051 #endif
3052
3053         return ret;
3054 }
3055
3056 /*
3057  * Reset PF device.
3058  */
3059 static int
3060 ixgbe_dev_reset(struct rte_eth_dev *dev)
3061 {
3062         int ret;
3063
3064         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3065          * its VF to make them align with it. The detailed notification
3066          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3067          * To avoid unexpected behavior in VF, currently reset of PF with
3068          * SR-IOV activation is not supported. It might be supported later.
3069          */
3070         if (dev->data->sriov.active)
3071                 return -ENOTSUP;
3072
3073         ret = eth_ixgbe_dev_uninit(dev);
3074         if (ret)
3075                 return ret;
3076
3077         ret = eth_ixgbe_dev_init(dev, NULL);
3078
3079         return ret;
3080 }
3081
3082 static void
3083 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3084                            struct ixgbe_hw_stats *hw_stats,
3085                            struct ixgbe_macsec_stats *macsec_stats,
3086                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3087                            uint64_t *total_qprc, uint64_t *total_qprdc)
3088 {
3089         uint32_t bprc, lxon, lxoff, total;
3090         uint32_t delta_gprc = 0;
3091         unsigned i;
3092         /* Workaround for RX byte count not including CRC bytes when CRC
3093          * strip is enabled. CRC bytes are removed from counters when crc_strip
3094          * is disabled.
3095          */
3096         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3097                         IXGBE_HLREG0_RXCRCSTRP);
3098
3099         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3100         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3101         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3102         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3103
3104         for (i = 0; i < 8; i++) {
3105                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3106
3107                 /* global total per queue */
3108                 hw_stats->mpc[i] += mp;
3109                 /* Running comprehensive total for stats display */
3110                 *total_missed_rx += hw_stats->mpc[i];
3111                 if (hw->mac.type == ixgbe_mac_82598EB) {
3112                         hw_stats->rnbc[i] +=
3113                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3114                         hw_stats->pxonrxc[i] +=
3115                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3116                         hw_stats->pxoffrxc[i] +=
3117                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3118                 } else {
3119                         hw_stats->pxonrxc[i] +=
3120                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3121                         hw_stats->pxoffrxc[i] +=
3122                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3123                         hw_stats->pxon2offc[i] +=
3124                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3125                 }
3126                 hw_stats->pxontxc[i] +=
3127                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3128                 hw_stats->pxofftxc[i] +=
3129                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3130         }
3131         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3132                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3133                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3134                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3135
3136                 delta_gprc += delta_qprc;
3137
3138                 hw_stats->qprc[i] += delta_qprc;
3139                 hw_stats->qptc[i] += delta_qptc;
3140
3141                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3142                 hw_stats->qbrc[i] +=
3143                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3144                 if (crc_strip == 0)
3145                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3146
3147                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3148                 hw_stats->qbtc[i] +=
3149                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3150
3151                 hw_stats->qprdc[i] += delta_qprdc;
3152                 *total_qprdc += hw_stats->qprdc[i];
3153
3154                 *total_qprc += hw_stats->qprc[i];
3155                 *total_qbrc += hw_stats->qbrc[i];
3156         }
3157         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3158         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3159         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3160
3161         /*
3162          * An errata states that gprc actually counts good + missed packets:
3163          * Workaround to set gprc to summated queue packet receives
3164          */
3165         hw_stats->gprc = *total_qprc;
3166
3167         if (hw->mac.type != ixgbe_mac_82598EB) {
3168                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3169                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3170                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3171                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3172                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3173                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3174                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3175                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3176         } else {
3177                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3178                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3179                 /* 82598 only has a counter in the high register */
3180                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3181                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3182                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3183         }
3184         uint64_t old_tpr = hw_stats->tpr;
3185
3186         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3187         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3188
3189         if (crc_strip == 0)
3190                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3191
3192         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3193         hw_stats->gptc += delta_gptc;
3194         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3195         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3196
3197         /*
3198          * Workaround: mprc hardware is incorrectly counting
3199          * broadcasts, so for now we subtract those.
3200          */
3201         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3202         hw_stats->bprc += bprc;
3203         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3204         if (hw->mac.type == ixgbe_mac_82598EB)
3205                 hw_stats->mprc -= bprc;
3206
3207         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3208         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3209         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3210         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3211         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3212         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3213
3214         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3215         hw_stats->lxontxc += lxon;
3216         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3217         hw_stats->lxofftxc += lxoff;
3218         total = lxon + lxoff;
3219
3220         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3221         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3222         hw_stats->gptc -= total;
3223         hw_stats->mptc -= total;
3224         hw_stats->ptc64 -= total;
3225         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3226
3227         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3228         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3229         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3230         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3231         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3232         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3233         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3234         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3235         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3236         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3237         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3238         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3239         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3240         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3241         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3242         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3243         /* Only read FCOE on 82599 */
3244         if (hw->mac.type != ixgbe_mac_82598EB) {
3245                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3246                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3247                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3248                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3249                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3250         }
3251
3252         /* Flow Director Stats registers */
3253         if (hw->mac.type != ixgbe_mac_82598EB) {
3254                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3255                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3256                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3257                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3258                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3259                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3260                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3261                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3262                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3263                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3264         }
3265         /* MACsec Stats registers */
3266         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3267         macsec_stats->out_pkts_encrypted +=
3268                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3269         macsec_stats->out_pkts_protected +=
3270                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3271         macsec_stats->out_octets_encrypted +=
3272                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3273         macsec_stats->out_octets_protected +=
3274                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3275         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3276         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3277         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3278         macsec_stats->in_pkts_unknownsci +=
3279                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3280         macsec_stats->in_octets_decrypted +=
3281                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3282         macsec_stats->in_octets_validated +=
3283                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3284         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3285         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3286         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3287         for (i = 0; i < 2; i++) {
3288                 macsec_stats->in_pkts_ok +=
3289                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3290                 macsec_stats->in_pkts_invalid +=
3291                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3292                 macsec_stats->in_pkts_notvalid +=
3293                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3294         }
3295         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3296         macsec_stats->in_pkts_notusingsa +=
3297                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3298 }
3299
3300 /*
3301  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3302  */
3303 static int
3304 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3305 {
3306         struct ixgbe_hw *hw =
3307                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3308         struct ixgbe_hw_stats *hw_stats =
3309                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3310         struct ixgbe_macsec_stats *macsec_stats =
3311                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3312                                 dev->data->dev_private);
3313         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3314         unsigned i;
3315
3316         total_missed_rx = 0;
3317         total_qbrc = 0;
3318         total_qprc = 0;
3319         total_qprdc = 0;
3320
3321         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3322                         &total_qbrc, &total_qprc, &total_qprdc);
3323
3324         if (stats == NULL)
3325                 return -EINVAL;
3326
3327         /* Fill out the rte_eth_stats statistics structure */
3328         stats->ipackets = total_qprc;
3329         stats->ibytes = total_qbrc;
3330         stats->opackets = hw_stats->gptc;
3331         stats->obytes = hw_stats->gotc;
3332
3333         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3334                 stats->q_ipackets[i] = hw_stats->qprc[i];
3335                 stats->q_opackets[i] = hw_stats->qptc[i];
3336                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3337                 stats->q_obytes[i] = hw_stats->qbtc[i];
3338                 stats->q_errors[i] = hw_stats->qprdc[i];
3339         }
3340
3341         /* Rx Errors */
3342         stats->imissed  = total_missed_rx;
3343         stats->ierrors  = hw_stats->crcerrs +
3344                           hw_stats->mspdc +
3345                           hw_stats->rlec +
3346                           hw_stats->ruc +
3347                           hw_stats->roc +
3348                           hw_stats->illerrc +
3349                           hw_stats->errbc +
3350                           hw_stats->rfc +
3351                           hw_stats->fccrc +
3352                           hw_stats->fclast;
3353
3354         /* Tx Errors */
3355         stats->oerrors  = 0;
3356         return 0;
3357 }
3358
3359 static int
3360 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3361 {
3362         struct ixgbe_hw_stats *stats =
3363                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3364
3365         /* HW registers are cleared on read */
3366         ixgbe_dev_stats_get(dev, NULL);
3367
3368         /* Reset software totals */
3369         memset(stats, 0, sizeof(*stats));
3370
3371         return 0;
3372 }
3373
3374 /* This function calculates the number of xstats based on the current config */
3375 static unsigned
3376 ixgbe_xstats_calc_num(void) {
3377         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3378                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3379                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3380 }
3381
3382 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3383         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3384 {
3385         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3386         unsigned stat, i, count;
3387
3388         if (xstats_names != NULL) {
3389                 count = 0;
3390
3391                 /* Note: limit >= cnt_stats checked upstream
3392                  * in rte_eth_xstats_names()
3393                  */
3394
3395                 /* Extended stats from ixgbe_hw_stats */
3396                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3397                         strlcpy(xstats_names[count].name,
3398                                 rte_ixgbe_stats_strings[i].name,
3399                                 sizeof(xstats_names[count].name));
3400                         count++;
3401                 }
3402
3403                 /* MACsec Stats */
3404                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3405                         strlcpy(xstats_names[count].name,
3406                                 rte_ixgbe_macsec_strings[i].name,
3407                                 sizeof(xstats_names[count].name));
3408                         count++;
3409                 }
3410
3411                 /* RX Priority Stats */
3412                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3413                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3414                                 snprintf(xstats_names[count].name,
3415                                         sizeof(xstats_names[count].name),
3416                                         "rx_priority%u_%s", i,
3417                                         rte_ixgbe_rxq_strings[stat].name);
3418                                 count++;
3419                         }
3420                 }
3421
3422                 /* TX Priority Stats */
3423                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3424                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3425                                 snprintf(xstats_names[count].name,
3426                                         sizeof(xstats_names[count].name),
3427                                         "tx_priority%u_%s", i,
3428                                         rte_ixgbe_txq_strings[stat].name);
3429                                 count++;
3430                         }
3431                 }
3432         }
3433         return cnt_stats;
3434 }
3435
3436 static int ixgbe_dev_xstats_get_names_by_id(
3437         struct rte_eth_dev *dev,
3438         struct rte_eth_xstat_name *xstats_names,
3439         const uint64_t *ids,
3440         unsigned int limit)
3441 {
3442         if (!ids) {
3443                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3444                 unsigned int stat, i, count;
3445
3446                 if (xstats_names != NULL) {
3447                         count = 0;
3448
3449                         /* Note: limit >= cnt_stats checked upstream
3450                          * in rte_eth_xstats_names()
3451                          */
3452
3453                         /* Extended stats from ixgbe_hw_stats */
3454                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3455                                 strlcpy(xstats_names[count].name,
3456                                         rte_ixgbe_stats_strings[i].name,
3457                                         sizeof(xstats_names[count].name));
3458                                 count++;
3459                         }
3460
3461                         /* MACsec Stats */
3462                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3463                                 strlcpy(xstats_names[count].name,
3464                                         rte_ixgbe_macsec_strings[i].name,
3465                                         sizeof(xstats_names[count].name));
3466                                 count++;
3467                         }
3468
3469                         /* RX Priority Stats */
3470                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3471                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3472                                         snprintf(xstats_names[count].name,
3473                                             sizeof(xstats_names[count].name),
3474                                             "rx_priority%u_%s", i,
3475                                             rte_ixgbe_rxq_strings[stat].name);
3476                                         count++;
3477                                 }
3478                         }
3479
3480                         /* TX Priority Stats */
3481                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3482                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3483                                         snprintf(xstats_names[count].name,
3484                                             sizeof(xstats_names[count].name),
3485                                             "tx_priority%u_%s", i,
3486                                             rte_ixgbe_txq_strings[stat].name);
3487                                         count++;
3488                                 }
3489                         }
3490                 }
3491                 return cnt_stats;
3492         }
3493
3494         uint16_t i;
3495         uint16_t size = ixgbe_xstats_calc_num();
3496         struct rte_eth_xstat_name xstats_names_copy[size];
3497
3498         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3499                         size);
3500
3501         for (i = 0; i < limit; i++) {
3502                 if (ids[i] >= size) {
3503                         PMD_INIT_LOG(ERR, "id value isn't valid");
3504                         return -1;
3505                 }
3506                 strcpy(xstats_names[i].name,
3507                                 xstats_names_copy[ids[i]].name);
3508         }
3509         return limit;
3510 }
3511
3512 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3513         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3514 {
3515         unsigned i;
3516
3517         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3518                 return -ENOMEM;
3519
3520         if (xstats_names != NULL)
3521                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3522                         strlcpy(xstats_names[i].name,
3523                                 rte_ixgbevf_stats_strings[i].name,
3524                                 sizeof(xstats_names[i].name));
3525         return IXGBEVF_NB_XSTATS;
3526 }
3527
3528 static int
3529 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3530                                          unsigned n)
3531 {
3532         struct ixgbe_hw *hw =
3533                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3534         struct ixgbe_hw_stats *hw_stats =
3535                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3536         struct ixgbe_macsec_stats *macsec_stats =
3537                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3538                                 dev->data->dev_private);
3539         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3540         unsigned i, stat, count = 0;
3541
3542         count = ixgbe_xstats_calc_num();
3543
3544         if (n < count)
3545                 return count;
3546
3547         total_missed_rx = 0;
3548         total_qbrc = 0;
3549         total_qprc = 0;
3550         total_qprdc = 0;
3551
3552         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3553                         &total_qbrc, &total_qprc, &total_qprdc);
3554
3555         /* If this is a reset xstats is NULL, and we have cleared the
3556          * registers by reading them.
3557          */
3558         if (!xstats)
3559                 return 0;
3560
3561         /* Extended stats from ixgbe_hw_stats */
3562         count = 0;
3563         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3564                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3565                                 rte_ixgbe_stats_strings[i].offset);
3566                 xstats[count].id = count;
3567                 count++;
3568         }
3569
3570         /* MACsec Stats */
3571         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3572                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3573                                 rte_ixgbe_macsec_strings[i].offset);
3574                 xstats[count].id = count;
3575                 count++;
3576         }
3577
3578         /* RX Priority Stats */
3579         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3580                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3581                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3582                                         rte_ixgbe_rxq_strings[stat].offset +
3583                                         (sizeof(uint64_t) * i));
3584                         xstats[count].id = count;
3585                         count++;
3586                 }
3587         }
3588
3589         /* TX Priority Stats */
3590         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3591                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3592                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3593                                         rte_ixgbe_txq_strings[stat].offset +
3594                                         (sizeof(uint64_t) * i));
3595                         xstats[count].id = count;
3596                         count++;
3597                 }
3598         }
3599         return count;
3600 }
3601
3602 static int
3603 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3604                 uint64_t *values, unsigned int n)
3605 {
3606         if (!ids) {
3607                 struct ixgbe_hw *hw =
3608                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3609                 struct ixgbe_hw_stats *hw_stats =
3610                                 IXGBE_DEV_PRIVATE_TO_STATS(
3611                                                 dev->data->dev_private);
3612                 struct ixgbe_macsec_stats *macsec_stats =
3613                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3614                                         dev->data->dev_private);
3615                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3616                 unsigned int i, stat, count = 0;
3617
3618                 count = ixgbe_xstats_calc_num();
3619
3620                 if (!ids && n < count)
3621                         return count;
3622
3623                 total_missed_rx = 0;
3624                 total_qbrc = 0;
3625                 total_qprc = 0;
3626                 total_qprdc = 0;
3627
3628                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3629                                 &total_missed_rx, &total_qbrc, &total_qprc,
3630                                 &total_qprdc);
3631
3632                 /* If this is a reset xstats is NULL, and we have cleared the
3633                  * registers by reading them.
3634                  */
3635                 if (!ids && !values)
3636                         return 0;
3637
3638                 /* Extended stats from ixgbe_hw_stats */
3639                 count = 0;
3640                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3641                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3642                                         rte_ixgbe_stats_strings[i].offset);
3643                         count++;
3644                 }
3645
3646                 /* MACsec Stats */
3647                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3648                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3649                                         rte_ixgbe_macsec_strings[i].offset);
3650                         count++;
3651                 }
3652
3653                 /* RX Priority Stats */
3654                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3655                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3656                                 values[count] =
3657                                         *(uint64_t *)(((char *)hw_stats) +
3658                                         rte_ixgbe_rxq_strings[stat].offset +
3659                                         (sizeof(uint64_t) * i));
3660                                 count++;
3661                         }
3662                 }
3663
3664                 /* TX Priority Stats */
3665                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3666                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3667                                 values[count] =
3668                                         *(uint64_t *)(((char *)hw_stats) +
3669                                         rte_ixgbe_txq_strings[stat].offset +
3670                                         (sizeof(uint64_t) * i));
3671                                 count++;
3672                         }
3673                 }
3674                 return count;
3675         }
3676
3677         uint16_t i;
3678         uint16_t size = ixgbe_xstats_calc_num();
3679         uint64_t values_copy[size];
3680
3681         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3682
3683         for (i = 0; i < n; i++) {
3684                 if (ids[i] >= size) {
3685                         PMD_INIT_LOG(ERR, "id value isn't valid");
3686                         return -1;
3687                 }
3688                 values[i] = values_copy[ids[i]];
3689         }
3690         return n;
3691 }
3692
3693 static int
3694 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3695 {
3696         struct ixgbe_hw_stats *stats =
3697                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3698         struct ixgbe_macsec_stats *macsec_stats =
3699                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3700                                 dev->data->dev_private);
3701
3702         unsigned count = ixgbe_xstats_calc_num();
3703
3704         /* HW registers are cleared on read */
3705         ixgbe_dev_xstats_get(dev, NULL, count);
3706
3707         /* Reset software totals */
3708         memset(stats, 0, sizeof(*stats));
3709         memset(macsec_stats, 0, sizeof(*macsec_stats));
3710
3711         return 0;
3712 }
3713
3714 static void
3715 ixgbevf_update_stats(struct rte_eth_dev *dev)
3716 {
3717         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3718         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3719                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3720
3721         /* Good Rx packet, include VF loopback */
3722         UPDATE_VF_STAT(IXGBE_VFGPRC,
3723             hw_stats->last_vfgprc, hw_stats->vfgprc);
3724
3725         /* Good Rx octets, include VF loopback */
3726         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3727             hw_stats->last_vfgorc, hw_stats->vfgorc);
3728
3729         /* Good Tx packet, include VF loopback */
3730         UPDATE_VF_STAT(IXGBE_VFGPTC,
3731             hw_stats->last_vfgptc, hw_stats->vfgptc);
3732
3733         /* Good Tx octets, include VF loopback */
3734         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3735             hw_stats->last_vfgotc, hw_stats->vfgotc);
3736
3737         /* Rx Multicst Packet */
3738         UPDATE_VF_STAT(IXGBE_VFMPRC,
3739             hw_stats->last_vfmprc, hw_stats->vfmprc);
3740 }
3741
3742 static int
3743 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3744                        unsigned n)
3745 {
3746         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3747                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3748         unsigned i;
3749
3750         if (n < IXGBEVF_NB_XSTATS)
3751                 return IXGBEVF_NB_XSTATS;
3752
3753         ixgbevf_update_stats(dev);
3754
3755         if (!xstats)
3756                 return 0;
3757
3758         /* Extended stats */
3759         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3760                 xstats[i].id = i;
3761                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3762                         rte_ixgbevf_stats_strings[i].offset);
3763         }
3764
3765         return IXGBEVF_NB_XSTATS;
3766 }
3767
3768 static int
3769 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3770 {
3771         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3772                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3773
3774         ixgbevf_update_stats(dev);
3775
3776         if (stats == NULL)
3777                 return -EINVAL;
3778
3779         stats->ipackets = hw_stats->vfgprc;
3780         stats->ibytes = hw_stats->vfgorc;
3781         stats->opackets = hw_stats->vfgptc;
3782         stats->obytes = hw_stats->vfgotc;
3783         return 0;
3784 }
3785
3786 static int
3787 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3788 {
3789         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3790                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3791
3792         /* Sync HW register to the last stats */
3793         ixgbevf_dev_stats_get(dev, NULL);
3794
3795         /* reset HW current stats*/
3796         hw_stats->vfgprc = 0;
3797         hw_stats->vfgorc = 0;
3798         hw_stats->vfgptc = 0;
3799         hw_stats->vfgotc = 0;
3800
3801         return 0;
3802 }
3803
3804 static int
3805 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3806 {
3807         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3808         u16 eeprom_verh, eeprom_verl;
3809         u32 etrack_id;
3810         int ret;
3811
3812         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3813         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3814
3815         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3816         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3817
3818         ret += 1; /* add the size of '\0' */
3819         if (fw_size < (u32)ret)
3820                 return ret;
3821         else
3822                 return 0;
3823 }
3824
3825 static int
3826 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3827 {
3828         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3829         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3830         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3831
3832         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3833         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3834         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3835                 /*
3836                  * When DCB/VT is off, maximum number of queues changes,
3837                  * except for 82598EB, which remains constant.
3838                  */
3839                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3840                                 hw->mac.type != ixgbe_mac_82598EB)
3841                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3842         }
3843         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3844         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3845         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3846         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3847         dev_info->max_vfs = pci_dev->max_vfs;
3848         if (hw->mac.type == ixgbe_mac_82598EB)
3849                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3850         else
3851                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3852         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3853         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3854         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3855         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3856         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3857                                      dev_info->rx_queue_offload_capa);
3858         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3859         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3860
3861         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3862                 .rx_thresh = {
3863                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3864                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3865                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3866                 },
3867                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3868                 .rx_drop_en = 0,
3869                 .offloads = 0,
3870         };
3871
3872         dev_info->default_txconf = (struct rte_eth_txconf) {
3873                 .tx_thresh = {
3874                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3875                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3876                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3877                 },
3878                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3879                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3880                 .offloads = 0,
3881         };
3882
3883         dev_info->rx_desc_lim = rx_desc_lim;
3884         dev_info->tx_desc_lim = tx_desc_lim;
3885
3886         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3887         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3888         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3889
3890         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3891         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3892                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3893                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3894                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3895
3896         if (hw->mac.type == ixgbe_mac_X540 ||
3897             hw->mac.type == ixgbe_mac_X540_vf ||
3898             hw->mac.type == ixgbe_mac_X550 ||
3899             hw->mac.type == ixgbe_mac_X550_vf) {
3900                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3901         }
3902         if (hw->mac.type == ixgbe_mac_X550) {
3903                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3904                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3905         }
3906
3907         /* Driver-preferred Rx/Tx parameters */
3908         dev_info->default_rxportconf.burst_size = 32;
3909         dev_info->default_txportconf.burst_size = 32;
3910         dev_info->default_rxportconf.nb_queues = 1;
3911         dev_info->default_txportconf.nb_queues = 1;
3912         dev_info->default_rxportconf.ring_size = 256;
3913         dev_info->default_txportconf.ring_size = 256;
3914
3915         return 0;
3916 }
3917
3918 static const uint32_t *
3919 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3920 {
3921         static const uint32_t ptypes[] = {
3922                 /* For non-vec functions,
3923                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3924                  * for vec functions,
3925                  * refers to _recv_raw_pkts_vec().
3926                  */
3927                 RTE_PTYPE_L2_ETHER,
3928                 RTE_PTYPE_L3_IPV4,
3929                 RTE_PTYPE_L3_IPV4_EXT,
3930                 RTE_PTYPE_L3_IPV6,
3931                 RTE_PTYPE_L3_IPV6_EXT,
3932                 RTE_PTYPE_L4_SCTP,
3933                 RTE_PTYPE_L4_TCP,
3934                 RTE_PTYPE_L4_UDP,
3935                 RTE_PTYPE_TUNNEL_IP,
3936                 RTE_PTYPE_INNER_L3_IPV6,
3937                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3938                 RTE_PTYPE_INNER_L4_TCP,
3939                 RTE_PTYPE_INNER_L4_UDP,
3940                 RTE_PTYPE_UNKNOWN
3941         };
3942
3943         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3944             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3945             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3946             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3947                 return ptypes;
3948
3949 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON)
3950         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3951             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3952                 return ptypes;
3953 #endif
3954         return NULL;
3955 }
3956
3957 static int
3958 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3959                      struct rte_eth_dev_info *dev_info)
3960 {
3961         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3962         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3963
3964         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3965         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3966         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3967         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3968         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3969         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3970         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3971         dev_info->max_vfs = pci_dev->max_vfs;
3972         if (hw->mac.type == ixgbe_mac_82598EB)
3973                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3974         else
3975                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3976         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3977         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3978                                      dev_info->rx_queue_offload_capa);
3979         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3980         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3981         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3982         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3983         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3984
3985         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3986                 .rx_thresh = {
3987                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3988                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3989                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3990                 },
3991                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3992                 .rx_drop_en = 0,
3993                 .offloads = 0,
3994         };
3995
3996         dev_info->default_txconf = (struct rte_eth_txconf) {
3997                 .tx_thresh = {
3998                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3999                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
4000                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
4001                 },
4002                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
4003                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4004                 .offloads = 0,
4005         };
4006
4007         dev_info->rx_desc_lim = rx_desc_lim;
4008         dev_info->tx_desc_lim = tx_desc_lim;
4009
4010         return 0;
4011 }
4012
4013 static int
4014 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4015                    bool *link_up, int wait_to_complete)
4016 {
4017         struct ixgbe_adapter *adapter = container_of(hw,
4018                                                      struct ixgbe_adapter, hw);
4019         struct ixgbe_mbx_info *mbx = &hw->mbx;
4020         struct ixgbe_mac_info *mac = &hw->mac;
4021         uint32_t links_reg, in_msg;
4022         int ret_val = 0;
4023
4024         /* If we were hit with a reset drop the link */
4025         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4026                 mac->get_link_status = true;
4027
4028         if (!mac->get_link_status)
4029                 goto out;
4030
4031         /* if link status is down no point in checking to see if pf is up */
4032         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4033         if (!(links_reg & IXGBE_LINKS_UP))
4034                 goto out;
4035
4036         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4037          * before the link status is correct
4038          */
4039         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4040                 int i;
4041
4042                 for (i = 0; i < 5; i++) {
4043                         rte_delay_us(100);
4044                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4045
4046                         if (!(links_reg & IXGBE_LINKS_UP))
4047                                 goto out;
4048                 }
4049         }
4050
4051         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4052         case IXGBE_LINKS_SPEED_10G_82599:
4053                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4054                 if (hw->mac.type >= ixgbe_mac_X550) {
4055                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4056                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4057                 }
4058                 break;
4059         case IXGBE_LINKS_SPEED_1G_82599:
4060                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4061                 break;
4062         case IXGBE_LINKS_SPEED_100_82599:
4063                 *speed = IXGBE_LINK_SPEED_100_FULL;
4064                 if (hw->mac.type == ixgbe_mac_X550) {
4065                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4066                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4067                 }
4068                 break;
4069         case IXGBE_LINKS_SPEED_10_X550EM_A:
4070                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4071                 /* Since Reserved in older MAC's */
4072                 if (hw->mac.type >= ixgbe_mac_X550)
4073                         *speed = IXGBE_LINK_SPEED_10_FULL;
4074                 break;
4075         default:
4076                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4077         }
4078
4079         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4080                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4081                         mac->get_link_status = true;
4082                 else
4083                         mac->get_link_status = false;
4084
4085                 goto out;
4086         }
4087
4088         /* if the read failed it could just be a mailbox collision, best wait
4089          * until we are called again and don't report an error
4090          */
4091         if (mbx->ops.read(hw, &in_msg, 1, 0))
4092                 goto out;
4093
4094         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4095                 /* msg is not CTS and is NACK we must have lost CTS status */
4096                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4097                         mac->get_link_status = false;
4098                 goto out;
4099         }
4100
4101         /* the pf is talking, if we timed out in the past we reinit */
4102         if (!mbx->timeout) {
4103                 ret_val = -1;
4104                 goto out;
4105         }
4106
4107         /* if we passed all the tests above then the link is up and we no
4108          * longer need to check for link
4109          */
4110         mac->get_link_status = false;
4111
4112 out:
4113         *link_up = !mac->get_link_status;
4114         return ret_val;
4115 }
4116
4117 /*
4118  * If @timeout_ms was 0, it means that it will not return until link complete.
4119  * It returns 1 on complete, return 0 on timeout.
4120  */
4121 static int
4122 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4123 {
4124 #define WARNING_TIMEOUT    9000 /* 9s  in total */
4125         struct ixgbe_adapter *ad = dev->data->dev_private;
4126         uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4127
4128         while (rte_atomic32_read(&ad->link_thread_running)) {
4129                 msec_delay(1);
4130                 timeout--;
4131
4132                 if (timeout_ms) {
4133                         if (!timeout)
4134                                 return 0;
4135                 } else if (!timeout) {
4136                         /* It will not return until link complete */
4137                         timeout = WARNING_TIMEOUT;
4138                         PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4139                 }
4140         }
4141
4142         return 1;
4143 }
4144
4145 static void *
4146 ixgbe_dev_setup_link_thread_handler(void *param)
4147 {
4148         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4149         struct ixgbe_adapter *ad = dev->data->dev_private;
4150         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4151         struct ixgbe_interrupt *intr =
4152                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4153         u32 speed;
4154         bool autoneg = false;
4155
4156         pthread_detach(pthread_self());
4157         speed = hw->phy.autoneg_advertised;
4158         if (!speed)
4159                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4160
4161         ixgbe_setup_link(hw, speed, true);
4162
4163         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4164         rte_atomic32_clear(&ad->link_thread_running);
4165         return NULL;
4166 }
4167
4168 /*
4169  * In freebsd environment, nic_uio drivers do not support interrupts,
4170  * rte_intr_callback_register() will fail to register interrupts.
4171  * We can not make link status to change from down to up by interrupt
4172  * callback. So we need to wait for the controller to acquire link
4173  * when ports start.
4174  * It returns 0 on link up.
4175  */
4176 static int
4177 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4178 {
4179 #ifdef RTE_EXEC_ENV_FREEBSD
4180         int err, i;
4181         bool link_up = false;
4182         uint32_t speed = 0;
4183         const int nb_iter = 25;
4184
4185         for (i = 0; i < nb_iter; i++) {
4186                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4187                 if (err)
4188                         return err;
4189                 if (link_up)
4190                         return 0;
4191                 msec_delay(200);
4192         }
4193
4194         return 0;
4195 #else
4196         RTE_SET_USED(hw);
4197         return 0;
4198 #endif
4199 }
4200
4201 /* return 0 means link status changed, -1 means not changed */
4202 int
4203 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4204                             int wait_to_complete, int vf)
4205 {
4206         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4207         struct ixgbe_adapter *ad = dev->data->dev_private;
4208         struct rte_eth_link link;
4209         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4210         struct ixgbe_interrupt *intr =
4211                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4212         bool link_up;
4213         int diag;
4214         int wait = 1;
4215         u32 esdp_reg;
4216
4217         memset(&link, 0, sizeof(link));
4218         link.link_status = ETH_LINK_DOWN;
4219         link.link_speed = ETH_SPEED_NUM_NONE;
4220         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4221         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4222                         ETH_LINK_SPEED_FIXED);
4223
4224         hw->mac.get_link_status = true;
4225
4226         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4227                 return rte_eth_linkstatus_set(dev, &link);
4228
4229         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4230         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4231                 wait = 0;
4232
4233 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4234 #ifdef RTE_EXEC_ENV_FREEBSD
4235         wait = 1;
4236 #endif
4237
4238         if (vf)
4239                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4240         else
4241                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4242
4243         if (diag != 0) {
4244                 link.link_speed = ETH_SPEED_NUM_100M;
4245                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4246                 return rte_eth_linkstatus_set(dev, &link);
4247         }
4248
4249         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4250                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4251                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4252                         link_up = 0;
4253         }
4254
4255         if (link_up == 0) {
4256                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4257                         ixgbe_dev_wait_setup_link_complete(dev, 0);
4258                         if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4259                                 /* To avoid race condition between threads, set
4260                                  * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4261                                  * when there is no link thread running.
4262                                  */
4263                                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4264                                 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4265                                         "ixgbe-link-handler",
4266                                         NULL,
4267                                         ixgbe_dev_setup_link_thread_handler,
4268                                         dev) < 0) {
4269                                         PMD_DRV_LOG(ERR,
4270                                                 "Create link thread failed!");
4271                                         rte_atomic32_clear(&ad->link_thread_running);
4272                                 }
4273                         } else {
4274                                 PMD_DRV_LOG(ERR,
4275                                         "Other link thread is running now!");
4276                         }
4277                 }
4278                 return rte_eth_linkstatus_set(dev, &link);
4279         }
4280
4281         link.link_status = ETH_LINK_UP;
4282         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4283
4284         switch (link_speed) {
4285         default:
4286         case IXGBE_LINK_SPEED_UNKNOWN:
4287                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
4288                 break;
4289
4290         case IXGBE_LINK_SPEED_10_FULL:
4291                 link.link_speed = ETH_SPEED_NUM_10M;
4292                 break;
4293
4294         case IXGBE_LINK_SPEED_100_FULL:
4295                 link.link_speed = ETH_SPEED_NUM_100M;
4296                 break;
4297
4298         case IXGBE_LINK_SPEED_1GB_FULL:
4299                 link.link_speed = ETH_SPEED_NUM_1G;
4300                 break;
4301
4302         case IXGBE_LINK_SPEED_2_5GB_FULL:
4303                 link.link_speed = ETH_SPEED_NUM_2_5G;
4304                 break;
4305
4306         case IXGBE_LINK_SPEED_5GB_FULL:
4307                 link.link_speed = ETH_SPEED_NUM_5G;
4308                 break;
4309
4310         case IXGBE_LINK_SPEED_10GB_FULL:
4311                 link.link_speed = ETH_SPEED_NUM_10G;
4312                 break;
4313         }
4314
4315         return rte_eth_linkstatus_set(dev, &link);
4316 }
4317
4318 static int
4319 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4320 {
4321         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4322 }
4323
4324 static int
4325 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4326 {
4327         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4328 }
4329
4330 static int
4331 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4332 {
4333         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4334         uint32_t fctrl;
4335
4336         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4337         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4338         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4339
4340         return 0;
4341 }
4342
4343 static int
4344 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4345 {
4346         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4347         uint32_t fctrl;
4348
4349         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4350         fctrl &= (~IXGBE_FCTRL_UPE);
4351         if (dev->data->all_multicast == 1)
4352                 fctrl |= IXGBE_FCTRL_MPE;
4353         else
4354                 fctrl &= (~IXGBE_FCTRL_MPE);
4355         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4356
4357         return 0;
4358 }
4359
4360 static int
4361 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4362 {
4363         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4364         uint32_t fctrl;
4365
4366         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4367         fctrl |= IXGBE_FCTRL_MPE;
4368         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4369
4370         return 0;
4371 }
4372
4373 static int
4374 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4375 {
4376         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4377         uint32_t fctrl;
4378
4379         if (dev->data->promiscuous == 1)
4380                 return 0; /* must remain in all_multicast mode */
4381
4382         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4383         fctrl &= (~IXGBE_FCTRL_MPE);
4384         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4385
4386         return 0;
4387 }
4388
4389 /**
4390  * It clears the interrupt causes and enables the interrupt.
4391  * It will be called once only during nic initialized.
4392  *
4393  * @param dev
4394  *  Pointer to struct rte_eth_dev.
4395  * @param on
4396  *  Enable or Disable.
4397  *
4398  * @return
4399  *  - On success, zero.
4400  *  - On failure, a negative value.
4401  */
4402 static int
4403 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4404 {
4405         struct ixgbe_interrupt *intr =
4406                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4407
4408         ixgbe_dev_link_status_print(dev);
4409         if (on)
4410                 intr->mask |= IXGBE_EICR_LSC;
4411         else
4412                 intr->mask &= ~IXGBE_EICR_LSC;
4413
4414         return 0;
4415 }
4416
4417 /**
4418  * It clears the interrupt causes and enables the interrupt.
4419  * It will be called once only during nic initialized.
4420  *
4421  * @param dev
4422  *  Pointer to struct rte_eth_dev.
4423  *
4424  * @return
4425  *  - On success, zero.
4426  *  - On failure, a negative value.
4427  */
4428 static int
4429 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4430 {
4431         struct ixgbe_interrupt *intr =
4432                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4433
4434         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4435
4436         return 0;
4437 }
4438
4439 /**
4440  * It clears the interrupt causes and enables the interrupt.
4441  * It will be called once only during nic initialized.
4442  *
4443  * @param dev
4444  *  Pointer to struct rte_eth_dev.
4445  *
4446  * @return
4447  *  - On success, zero.
4448  *  - On failure, a negative value.
4449  */
4450 static int
4451 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4452 {
4453         struct ixgbe_interrupt *intr =
4454                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4455
4456         intr->mask |= IXGBE_EICR_LINKSEC;
4457
4458         return 0;
4459 }
4460
4461 /*
4462  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4463  *
4464  * @param dev
4465  *  Pointer to struct rte_eth_dev.
4466  *
4467  * @return
4468  *  - On success, zero.
4469  *  - On failure, a negative value.
4470  */
4471 static int
4472 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4473 {
4474         uint32_t eicr;
4475         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4476         struct ixgbe_interrupt *intr =
4477                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4478
4479         /* clear all cause mask */
4480         ixgbe_disable_intr(hw);
4481
4482         /* read-on-clear nic registers here */
4483         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4484         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4485
4486         intr->flags = 0;
4487
4488         /* set flag for async link update */
4489         if (eicr & IXGBE_EICR_LSC)
4490                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4491
4492         if (eicr & IXGBE_EICR_MAILBOX)
4493                 intr->flags |= IXGBE_FLAG_MAILBOX;
4494
4495         if (eicr & IXGBE_EICR_LINKSEC)
4496                 intr->flags |= IXGBE_FLAG_MACSEC;
4497
4498         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4499             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4500             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4501                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4502
4503         return 0;
4504 }
4505
4506 /**
4507  * It gets and then prints the link status.
4508  *
4509  * @param dev
4510  *  Pointer to struct rte_eth_dev.
4511  *
4512  * @return
4513  *  - On success, zero.
4514  *  - On failure, a negative value.
4515  */
4516 static void
4517 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4518 {
4519         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4520         struct rte_eth_link link;
4521
4522         rte_eth_linkstatus_get(dev, &link);
4523
4524         if (link.link_status) {
4525                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4526                                         (int)(dev->data->port_id),
4527                                         (unsigned)link.link_speed,
4528                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4529                                         "full-duplex" : "half-duplex");
4530         } else {
4531                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4532                                 (int)(dev->data->port_id));
4533         }
4534         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4535                                 pci_dev->addr.domain,
4536                                 pci_dev->addr.bus,
4537                                 pci_dev->addr.devid,
4538                                 pci_dev->addr.function);
4539 }
4540
4541 /*
4542  * It executes link_update after knowing an interrupt occurred.
4543  *
4544  * @param dev
4545  *  Pointer to struct rte_eth_dev.
4546  *
4547  * @return
4548  *  - On success, zero.
4549  *  - On failure, a negative value.
4550  */
4551 static int
4552 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4553 {
4554         struct ixgbe_interrupt *intr =
4555                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4556         int64_t timeout;
4557         struct ixgbe_hw *hw =
4558                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4559
4560         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4561
4562         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4563                 ixgbe_pf_mbx_process(dev);
4564                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4565         }
4566
4567         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4568                 ixgbe_handle_lasi(hw);
4569                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4570         }
4571
4572         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4573                 struct rte_eth_link link;
4574
4575                 /* get the link status before link update, for predicting later */
4576                 rte_eth_linkstatus_get(dev, &link);
4577
4578                 ixgbe_dev_link_update(dev, 0);
4579
4580                 /* likely to up */
4581                 if (!link.link_status)
4582                         /* handle it 1 sec later, wait it being stable */
4583                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4584                 /* likely to down */
4585                 else
4586                         /* handle it 4 sec later, wait it being stable */
4587                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4588
4589                 ixgbe_dev_link_status_print(dev);
4590                 if (rte_eal_alarm_set(timeout * 1000,
4591                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4592                         PMD_DRV_LOG(ERR, "Error setting alarm");
4593                 else {
4594                         /* remember original mask */
4595                         intr->mask_original = intr->mask;
4596                         /* only disable lsc interrupt */
4597                         intr->mask &= ~IXGBE_EIMS_LSC;
4598                 }
4599         }
4600
4601         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4602         ixgbe_enable_intr(dev);
4603
4604         return 0;
4605 }
4606
4607 /**
4608  * Interrupt handler which shall be registered for alarm callback for delayed
4609  * handling specific interrupt to wait for the stable nic state. As the
4610  * NIC interrupt state is not stable for ixgbe after link is just down,
4611  * it needs to wait 4 seconds to get the stable status.
4612  *
4613  * @param handle
4614  *  Pointer to interrupt handle.
4615  * @param param
4616  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4617  *
4618  * @return
4619  *  void
4620  */
4621 static void
4622 ixgbe_dev_interrupt_delayed_handler(void *param)
4623 {
4624         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4625         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4626         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4627         struct ixgbe_interrupt *intr =
4628                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4629         struct ixgbe_hw *hw =
4630                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4631         uint32_t eicr;
4632
4633         ixgbe_disable_intr(hw);
4634
4635         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4636         if (eicr & IXGBE_EICR_MAILBOX)
4637                 ixgbe_pf_mbx_process(dev);
4638
4639         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4640                 ixgbe_handle_lasi(hw);
4641                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4642         }
4643
4644         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4645                 ixgbe_dev_link_update(dev, 0);
4646                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4647                 ixgbe_dev_link_status_print(dev);
4648                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4649         }
4650
4651         if (intr->flags & IXGBE_FLAG_MACSEC) {
4652                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL);
4653                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4654         }
4655
4656         /* restore original mask */
4657         intr->mask = intr->mask_original;
4658         intr->mask_original = 0;
4659
4660         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4661         ixgbe_enable_intr(dev);
4662         rte_intr_ack(intr_handle);
4663 }
4664
4665 /**
4666  * Interrupt handler triggered by NIC  for handling
4667  * specific interrupt.
4668  *
4669  * @param handle
4670  *  Pointer to interrupt handle.
4671  * @param param
4672  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4673  *
4674  * @return
4675  *  void
4676  */
4677 static void
4678 ixgbe_dev_interrupt_handler(void *param)
4679 {
4680         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4681
4682         ixgbe_dev_interrupt_get_status(dev);
4683         ixgbe_dev_interrupt_action(dev);
4684 }
4685
4686 static int
4687 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4688 {
4689         struct ixgbe_hw *hw;
4690
4691         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4692         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4693 }
4694
4695 static int
4696 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4697 {
4698         struct ixgbe_hw *hw;
4699
4700         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4701         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4702 }
4703
4704 static int
4705 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4706 {
4707         struct ixgbe_hw *hw;
4708         uint32_t mflcn_reg;
4709         uint32_t fccfg_reg;
4710         int rx_pause;
4711         int tx_pause;
4712
4713         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4714
4715         fc_conf->pause_time = hw->fc.pause_time;
4716         fc_conf->high_water = hw->fc.high_water[0];
4717         fc_conf->low_water = hw->fc.low_water[0];
4718         fc_conf->send_xon = hw->fc.send_xon;
4719         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4720
4721         /*
4722          * Return rx_pause status according to actual setting of
4723          * MFLCN register.
4724          */
4725         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4726         if (mflcn_reg & IXGBE_MFLCN_PMCF)
4727                 fc_conf->mac_ctrl_frame_fwd = 1;
4728         else
4729                 fc_conf->mac_ctrl_frame_fwd = 0;
4730
4731         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4732                 rx_pause = 1;
4733         else
4734                 rx_pause = 0;
4735
4736         /*
4737          * Return tx_pause status according to actual setting of
4738          * FCCFG register.
4739          */
4740         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4741         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4742                 tx_pause = 1;
4743         else
4744                 tx_pause = 0;
4745
4746         if (rx_pause && tx_pause)
4747                 fc_conf->mode = RTE_FC_FULL;
4748         else if (rx_pause)
4749                 fc_conf->mode = RTE_FC_RX_PAUSE;
4750         else if (tx_pause)
4751                 fc_conf->mode = RTE_FC_TX_PAUSE;
4752         else
4753                 fc_conf->mode = RTE_FC_NONE;
4754
4755         return 0;
4756 }
4757
4758 static int
4759 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4760 {
4761         struct ixgbe_hw *hw;
4762         struct ixgbe_adapter *adapter = dev->data->dev_private;
4763         int err;
4764         uint32_t rx_buf_size;
4765         uint32_t max_high_water;
4766         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4767                 ixgbe_fc_none,
4768                 ixgbe_fc_rx_pause,
4769                 ixgbe_fc_tx_pause,
4770                 ixgbe_fc_full
4771         };
4772
4773         PMD_INIT_FUNC_TRACE();
4774
4775         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4776         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4777         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4778
4779         /*
4780          * At least reserve one Ethernet frame for watermark
4781          * high_water/low_water in kilo bytes for ixgbe
4782          */
4783         max_high_water = (rx_buf_size -
4784                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4785         if ((fc_conf->high_water > max_high_water) ||
4786                 (fc_conf->high_water < fc_conf->low_water)) {
4787                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4788                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4789                 return -EINVAL;
4790         }
4791
4792         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4793         hw->fc.pause_time     = fc_conf->pause_time;
4794         hw->fc.high_water[0]  = fc_conf->high_water;
4795         hw->fc.low_water[0]   = fc_conf->low_water;
4796         hw->fc.send_xon       = fc_conf->send_xon;
4797         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4798         adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4799
4800         err = ixgbe_flow_ctrl_enable(dev, hw);
4801         if (err < 0) {
4802                 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4803                 return -EIO;
4804         }
4805         return err;
4806 }
4807
4808 /**
4809  *  ixgbe_pfc_enable_generic - Enable flow control
4810  *  @hw: pointer to hardware structure
4811  *  @tc_num: traffic class number
4812  *  Enable flow control according to the current settings.
4813  */
4814 static int
4815 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4816 {
4817         int ret_val = 0;
4818         uint32_t mflcn_reg, fccfg_reg;
4819         uint32_t reg;
4820         uint32_t fcrtl, fcrth;
4821         uint8_t i;
4822         uint8_t nb_rx_en;
4823
4824         /* Validate the water mark configuration */
4825         if (!hw->fc.pause_time) {
4826                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4827                 goto out;
4828         }
4829
4830         /* Low water mark of zero causes XOFF floods */
4831         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4832                  /* High/Low water can not be 0 */
4833                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4834                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4835                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4836                         goto out;
4837                 }
4838
4839                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4840                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4841                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4842                         goto out;
4843                 }
4844         }
4845         /* Negotiate the fc mode to use */
4846         ixgbe_fc_autoneg(hw);
4847
4848         /* Disable any previous flow control settings */
4849         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4850         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4851
4852         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4853         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4854
4855         switch (hw->fc.current_mode) {
4856         case ixgbe_fc_none:
4857                 /*
4858                  * If the count of enabled RX Priority Flow control >1,
4859                  * and the TX pause can not be disabled
4860                  */
4861                 nb_rx_en = 0;
4862                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4863                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4864                         if (reg & IXGBE_FCRTH_FCEN)
4865                                 nb_rx_en++;
4866                 }
4867                 if (nb_rx_en > 1)
4868                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4869                 break;
4870         case ixgbe_fc_rx_pause:
4871                 /*
4872                  * Rx Flow control is enabled and Tx Flow control is
4873                  * disabled by software override. Since there really
4874                  * isn't a way to advertise that we are capable of RX
4875                  * Pause ONLY, we will advertise that we support both
4876                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4877                  * disable the adapter's ability to send PAUSE frames.
4878                  */
4879                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4880                 /*
4881                  * If the count of enabled RX Priority Flow control >1,
4882                  * and the TX pause can not be disabled
4883                  */
4884                 nb_rx_en = 0;
4885                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4886                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4887                         if (reg & IXGBE_FCRTH_FCEN)
4888                                 nb_rx_en++;
4889                 }
4890                 if (nb_rx_en > 1)
4891                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4892                 break;
4893         case ixgbe_fc_tx_pause:
4894                 /*
4895                  * Tx Flow control is enabled, and Rx Flow control is
4896                  * disabled by software override.
4897                  */
4898                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4899                 break;
4900         case ixgbe_fc_full:
4901                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4902                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4903                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4904                 break;
4905         default:
4906                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4907                 ret_val = IXGBE_ERR_CONFIG;
4908                 goto out;
4909         }
4910
4911         /* Set 802.3x based flow control settings. */
4912         mflcn_reg |= IXGBE_MFLCN_DPF;
4913         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4914         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4915
4916         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4917         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4918                 hw->fc.high_water[tc_num]) {
4919                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4920                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4921                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4922         } else {
4923                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4924                 /*
4925                  * In order to prevent Tx hangs when the internal Tx
4926                  * switch is enabled we must set the high water mark
4927                  * to the maximum FCRTH value.  This allows the Tx
4928                  * switch to function even under heavy Rx workloads.
4929                  */
4930                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4931         }
4932         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4933
4934         /* Configure pause time (2 TCs per register) */
4935         reg = hw->fc.pause_time * 0x00010001;
4936         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4937                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4938
4939         /* Configure flow control refresh threshold value */
4940         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4941
4942 out:
4943         return ret_val;
4944 }
4945
4946 static int
4947 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4948 {
4949         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4950         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4951
4952         if (hw->mac.type != ixgbe_mac_82598EB) {
4953                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4954         }
4955         return ret_val;
4956 }
4957
4958 static int
4959 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4960 {
4961         int err;
4962         uint32_t rx_buf_size;
4963         uint32_t max_high_water;
4964         uint8_t tc_num;
4965         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4966         struct ixgbe_hw *hw =
4967                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4968         struct ixgbe_dcb_config *dcb_config =
4969                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4970
4971         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4972                 ixgbe_fc_none,
4973                 ixgbe_fc_rx_pause,
4974                 ixgbe_fc_tx_pause,
4975                 ixgbe_fc_full
4976         };
4977
4978         PMD_INIT_FUNC_TRACE();
4979
4980         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4981         tc_num = map[pfc_conf->priority];
4982         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4983         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4984         /*
4985          * At least reserve one Ethernet frame for watermark
4986          * high_water/low_water in kilo bytes for ixgbe
4987          */
4988         max_high_water = (rx_buf_size -
4989                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4990         if ((pfc_conf->fc.high_water > max_high_water) ||
4991             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4992                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4993                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4994                 return -EINVAL;
4995         }
4996
4997         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4998         hw->fc.pause_time = pfc_conf->fc.pause_time;
4999         hw->fc.send_xon = pfc_conf->fc.send_xon;
5000         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
5001         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
5002
5003         err = ixgbe_dcb_pfc_enable(dev, tc_num);
5004
5005         /* Not negotiated is not an error case */
5006         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5007                 return 0;
5008
5009         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5010         return -EIO;
5011 }
5012
5013 static int
5014 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5015                           struct rte_eth_rss_reta_entry64 *reta_conf,
5016                           uint16_t reta_size)
5017 {
5018         uint16_t i, sp_reta_size;
5019         uint8_t j, mask;
5020         uint32_t reta, r;
5021         uint16_t idx, shift;
5022         struct ixgbe_adapter *adapter = dev->data->dev_private;
5023         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5024         uint32_t reta_reg;
5025
5026         PMD_INIT_FUNC_TRACE();
5027
5028         if (!ixgbe_rss_update_sp(hw->mac.type)) {
5029                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5030                         "NIC.");
5031                 return -ENOTSUP;
5032         }
5033
5034         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5035         if (reta_size != sp_reta_size) {
5036                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5037                         "(%d) doesn't match the number hardware can supported "
5038                         "(%d)", reta_size, sp_reta_size);
5039                 return -EINVAL;
5040         }
5041
5042         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5043                 idx = i / RTE_RETA_GROUP_SIZE;
5044                 shift = i % RTE_RETA_GROUP_SIZE;
5045                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5046                                                 IXGBE_4_BIT_MASK);
5047                 if (!mask)
5048                         continue;
5049                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5050                 if (mask == IXGBE_4_BIT_MASK)
5051                         r = 0;
5052                 else
5053                         r = IXGBE_READ_REG(hw, reta_reg);
5054                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5055                         if (mask & (0x1 << j))
5056                                 reta |= reta_conf[idx].reta[shift + j] <<
5057                                                         (CHAR_BIT * j);
5058                         else
5059                                 reta |= r & (IXGBE_8_BIT_MASK <<
5060                                                 (CHAR_BIT * j));
5061                 }
5062                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5063         }
5064         adapter->rss_reta_updated = 1;
5065
5066         return 0;
5067 }
5068
5069 static int
5070 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5071                          struct rte_eth_rss_reta_entry64 *reta_conf,
5072                          uint16_t reta_size)
5073 {
5074         uint16_t i, sp_reta_size;
5075         uint8_t j, mask;
5076         uint32_t reta;
5077         uint16_t idx, shift;
5078         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5079         uint32_t reta_reg;
5080
5081         PMD_INIT_FUNC_TRACE();
5082         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5083         if (reta_size != sp_reta_size) {
5084                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5085                         "(%d) doesn't match the number hardware can supported "
5086                         "(%d)", reta_size, sp_reta_size);
5087                 return -EINVAL;
5088         }
5089
5090         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5091                 idx = i / RTE_RETA_GROUP_SIZE;
5092                 shift = i % RTE_RETA_GROUP_SIZE;
5093                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5094                                                 IXGBE_4_BIT_MASK);
5095                 if (!mask)
5096                         continue;
5097
5098                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5099                 reta = IXGBE_READ_REG(hw, reta_reg);
5100                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5101                         if (mask & (0x1 << j))
5102                                 reta_conf[idx].reta[shift + j] =
5103                                         ((reta >> (CHAR_BIT * j)) &
5104                                                 IXGBE_8_BIT_MASK);
5105                 }
5106         }
5107
5108         return 0;
5109 }
5110
5111 static int
5112 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5113                                 uint32_t index, uint32_t pool)
5114 {
5115         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5116         uint32_t enable_addr = 1;
5117
5118         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5119                              pool, enable_addr);
5120 }
5121
5122 static void
5123 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5124 {
5125         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5126
5127         ixgbe_clear_rar(hw, index);
5128 }
5129
5130 static int
5131 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5132 {
5133         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5134
5135         ixgbe_remove_rar(dev, 0);
5136         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5137
5138         return 0;
5139 }
5140
5141 static bool
5142 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5143 {
5144         if (strcmp(dev->device->driver->name, drv->driver.name))
5145                 return false;
5146
5147         return true;
5148 }
5149
5150 bool
5151 is_ixgbe_supported(struct rte_eth_dev *dev)
5152 {
5153         return is_device_supported(dev, &rte_ixgbe_pmd);
5154 }
5155
5156 static int
5157 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5158 {
5159         uint32_t hlreg0;
5160         uint32_t maxfrs;
5161         struct ixgbe_hw *hw;
5162         struct rte_eth_dev_info dev_info;
5163         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5164         struct rte_eth_dev_data *dev_data = dev->data;
5165         int ret;
5166
5167         ret = ixgbe_dev_info_get(dev, &dev_info);
5168         if (ret != 0)
5169                 return ret;
5170
5171         /* check that mtu is within the allowed range */
5172         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5173                 return -EINVAL;
5174
5175         /* If device is started, refuse mtu that requires the support of
5176          * scattered packets when this feature has not been enabled before.
5177          */
5178         if (dev_data->dev_started && !dev_data->scattered_rx &&
5179             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5180              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5181                 PMD_INIT_LOG(ERR, "Stop port first.");
5182                 return -EINVAL;
5183         }
5184
5185         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5186         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5187
5188         /* switch to jumbo mode if needed */
5189         if (frame_size > RTE_ETHER_MAX_LEN) {
5190                 dev->data->dev_conf.rxmode.offloads |=
5191                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5192                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5193         } else {
5194                 dev->data->dev_conf.rxmode.offloads &=
5195                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5196                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5197         }
5198         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5199
5200         /* update max frame size */
5201         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5202
5203         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5204         maxfrs &= 0x0000FFFF;
5205         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5206         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5207
5208         return 0;
5209 }
5210
5211 /*
5212  * Virtual Function operations
5213  */
5214 static void
5215 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5216 {
5217         struct ixgbe_interrupt *intr =
5218                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5219         struct ixgbe_hw *hw =
5220                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5221
5222         PMD_INIT_FUNC_TRACE();
5223
5224         /* Clear interrupt mask to stop from interrupts being generated */
5225         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5226
5227         IXGBE_WRITE_FLUSH(hw);
5228
5229         /* Clear mask value. */
5230         intr->mask = 0;
5231 }
5232
5233 static void
5234 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5235 {
5236         struct ixgbe_interrupt *intr =
5237                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5238         struct ixgbe_hw *hw =
5239                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5240
5241         PMD_INIT_FUNC_TRACE();
5242
5243         /* VF enable interrupt autoclean */
5244         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5245         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5246         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5247
5248         IXGBE_WRITE_FLUSH(hw);
5249
5250         /* Save IXGBE_VTEIMS value to mask. */
5251         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5252 }
5253
5254 static int
5255 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5256 {
5257         struct rte_eth_conf *conf = &dev->data->dev_conf;
5258         struct ixgbe_adapter *adapter = dev->data->dev_private;
5259
5260         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5261                      dev->data->port_id);
5262
5263         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5264                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5265
5266         /*
5267          * VF has no ability to enable/disable HW CRC
5268          * Keep the persistent behavior the same as Host PF
5269          */
5270 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5271         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5272                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5273                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5274         }
5275 #else
5276         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5277                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5278                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5279         }
5280 #endif
5281
5282         /*
5283          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5284          * allocation or vector Rx preconditions we will reset it.
5285          */
5286         adapter->rx_bulk_alloc_allowed = true;
5287         adapter->rx_vec_allowed = true;
5288
5289         return 0;
5290 }
5291
5292 static int
5293 ixgbevf_dev_start(struct rte_eth_dev *dev)
5294 {
5295         struct ixgbe_hw *hw =
5296                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5297         uint32_t intr_vector = 0;
5298         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5299         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5300
5301         int err, mask = 0;
5302
5303         PMD_INIT_FUNC_TRACE();
5304
5305         /* Stop the link setup handler before resetting the HW. */
5306         ixgbe_dev_wait_setup_link_complete(dev, 0);
5307
5308         err = hw->mac.ops.reset_hw(hw);
5309
5310         /**
5311          * In this case, reuses the MAC address assigned by VF
5312          * initialization.
5313          */
5314         if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) {
5315                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5316                 return err;
5317         }
5318
5319         hw->mac.get_link_status = true;
5320
5321         /* negotiate mailbox API version to use with the PF. */
5322         ixgbevf_negotiate_api(hw);
5323
5324         ixgbevf_dev_tx_init(dev);
5325
5326         /* This can fail when allocating mbufs for descriptor rings */
5327         err = ixgbevf_dev_rx_init(dev);
5328         if (err) {
5329                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5330                 ixgbe_dev_clear_queues(dev);
5331                 return err;
5332         }
5333
5334         /* Set vfta */
5335         ixgbevf_set_vfta_all(dev, 1);
5336
5337         /* Set HW strip */
5338         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5339                 ETH_VLAN_EXTEND_MASK;
5340         err = ixgbevf_vlan_offload_config(dev, mask);
5341         if (err) {
5342                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5343                 ixgbe_dev_clear_queues(dev);
5344                 return err;
5345         }
5346
5347         ixgbevf_dev_rxtx_start(dev);
5348
5349         /* check and configure queue intr-vector mapping */
5350         if (rte_intr_cap_multiple(intr_handle) &&
5351             dev->data->dev_conf.intr_conf.rxq) {
5352                 /* According to datasheet, only vector 0/1/2 can be used,
5353                  * now only one vector is used for Rx queue
5354                  */
5355                 intr_vector = 1;
5356                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5357                         return -1;
5358         }
5359
5360         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5361                 intr_handle->intr_vec =
5362                         rte_zmalloc("intr_vec",
5363                                     dev->data->nb_rx_queues * sizeof(int), 0);
5364                 if (intr_handle->intr_vec == NULL) {
5365                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5366                                      " intr_vec", dev->data->nb_rx_queues);
5367                         return -ENOMEM;
5368                 }
5369         }
5370         ixgbevf_configure_msix(dev);
5371
5372         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5373          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5374          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5375          * is not cleared, it will fail when following rte_intr_enable( ) tries
5376          * to map Rx queue interrupt to other VFIO vectors.
5377          * So clear uio/vfio intr/evevnfd first to avoid failure.
5378          */
5379         rte_intr_disable(intr_handle);
5380
5381         rte_intr_enable(intr_handle);
5382
5383         /* Re-enable interrupt for VF */
5384         ixgbevf_intr_enable(dev);
5385
5386         /*
5387          * Update link status right before return, because it may
5388          * start link configuration process in a separate thread.
5389          */
5390         ixgbevf_dev_link_update(dev, 0);
5391
5392         hw->adapter_stopped = false;
5393
5394         return 0;
5395 }
5396
5397 static int
5398 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5399 {
5400         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5401         struct ixgbe_adapter *adapter = dev->data->dev_private;
5402         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5403         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5404
5405         if (hw->adapter_stopped)
5406                 return 0;
5407
5408         PMD_INIT_FUNC_TRACE();
5409
5410         ixgbe_dev_wait_setup_link_complete(dev, 0);
5411
5412         ixgbevf_intr_disable(dev);
5413
5414         dev->data->dev_started = 0;
5415         hw->adapter_stopped = 1;
5416         ixgbe_stop_adapter(hw);
5417
5418         /*
5419           * Clear what we set, but we still keep shadow_vfta to
5420           * restore after device starts
5421           */
5422         ixgbevf_set_vfta_all(dev, 0);
5423
5424         /* Clear stored conf */
5425         dev->data->scattered_rx = 0;
5426
5427         ixgbe_dev_clear_queues(dev);
5428
5429         /* Clean datapath event and queue/vec mapping */
5430         rte_intr_efd_disable(intr_handle);
5431         if (intr_handle->intr_vec != NULL) {
5432                 rte_free(intr_handle->intr_vec);
5433                 intr_handle->intr_vec = NULL;
5434         }
5435
5436         adapter->rss_reta_updated = 0;
5437
5438         return 0;
5439 }
5440
5441 static int
5442 ixgbevf_dev_close(struct rte_eth_dev *dev)
5443 {
5444         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5445         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5446         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5447         int ret;
5448
5449         PMD_INIT_FUNC_TRACE();
5450         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5451                 return 0;
5452
5453         ixgbe_reset_hw(hw);
5454
5455         ret = ixgbevf_dev_stop(dev);
5456
5457         ixgbe_dev_free_queues(dev);
5458
5459         /**
5460          * Remove the VF MAC address ro ensure
5461          * that the VF traffic goes to the PF
5462          * after stop, close and detach of the VF
5463          **/
5464         ixgbevf_remove_mac_addr(dev, 0);
5465
5466         rte_intr_disable(intr_handle);
5467         rte_intr_callback_unregister(intr_handle,
5468                                      ixgbevf_dev_interrupt_handler, dev);
5469
5470         return ret;
5471 }
5472
5473 /*
5474  * Reset VF device
5475  */
5476 static int
5477 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5478 {
5479         int ret;
5480
5481         ret = eth_ixgbevf_dev_uninit(dev);
5482         if (ret)
5483                 return ret;
5484
5485         ret = eth_ixgbevf_dev_init(dev);
5486
5487         return ret;
5488 }
5489
5490 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5491 {
5492         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5493         struct ixgbe_vfta *shadow_vfta =
5494                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5495         int i = 0, j = 0, vfta = 0, mask = 1;
5496
5497         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5498                 vfta = shadow_vfta->vfta[i];
5499                 if (vfta) {
5500                         mask = 1;
5501                         for (j = 0; j < 32; j++) {
5502                                 if (vfta & mask)
5503                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5504                                                        on, false);
5505                                 mask <<= 1;
5506                         }
5507                 }
5508         }
5509
5510 }
5511
5512 static int
5513 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5514 {
5515         struct ixgbe_hw *hw =
5516                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5517         struct ixgbe_vfta *shadow_vfta =
5518                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5519         uint32_t vid_idx = 0;
5520         uint32_t vid_bit = 0;
5521         int ret = 0;
5522
5523         PMD_INIT_FUNC_TRACE();
5524
5525         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5526         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5527         if (ret) {
5528                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5529                 return ret;
5530         }
5531         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5532         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5533
5534         /* Save what we set and retore it after device reset */
5535         if (on)
5536                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5537         else
5538                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5539
5540         return 0;
5541 }
5542
5543 static void
5544 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5545 {
5546         struct ixgbe_hw *hw =
5547                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5548         uint32_t ctrl;
5549
5550         PMD_INIT_FUNC_TRACE();
5551
5552         if (queue >= hw->mac.max_rx_queues)
5553                 return;
5554
5555         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5556         if (on)
5557                 ctrl |= IXGBE_RXDCTL_VME;
5558         else
5559                 ctrl &= ~IXGBE_RXDCTL_VME;
5560         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5561
5562         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5563 }
5564
5565 static int
5566 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5567 {
5568         struct ixgbe_rx_queue *rxq;
5569         uint16_t i;
5570         int on = 0;
5571
5572         /* VF function only support hw strip feature, others are not support */
5573         if (mask & ETH_VLAN_STRIP_MASK) {
5574                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5575                         rxq = dev->data->rx_queues[i];
5576                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5577                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5578                 }
5579         }
5580
5581         return 0;
5582 }
5583
5584 static int
5585 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5586 {
5587         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5588
5589         ixgbevf_vlan_offload_config(dev, mask);
5590
5591         return 0;
5592 }
5593
5594 int
5595 ixgbe_vt_check(struct ixgbe_hw *hw)
5596 {
5597         uint32_t reg_val;
5598
5599         /* if Virtualization Technology is enabled */
5600         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5601         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5602                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5603                 return -1;
5604         }
5605
5606         return 0;
5607 }
5608
5609 static uint32_t
5610 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5611 {
5612         uint32_t vector = 0;
5613
5614         switch (hw->mac.mc_filter_type) {
5615         case 0:   /* use bits [47:36] of the address */
5616                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5617                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5618                 break;
5619         case 1:   /* use bits [46:35] of the address */
5620                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5621                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5622                 break;
5623         case 2:   /* use bits [45:34] of the address */
5624                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5625                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5626                 break;
5627         case 3:   /* use bits [43:32] of the address */
5628                 vector = ((uc_addr->addr_bytes[4]) |
5629                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5630                 break;
5631         default:  /* Invalid mc_filter_type */
5632                 break;
5633         }
5634
5635         /* vector can only be 12-bits or boundary will be exceeded */
5636         vector &= 0xFFF;
5637         return vector;
5638 }
5639
5640 static int
5641 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5642                         struct rte_ether_addr *mac_addr, uint8_t on)
5643 {
5644         uint32_t vector;
5645         uint32_t uta_idx;
5646         uint32_t reg_val;
5647         uint32_t uta_shift;
5648         uint32_t rc;
5649         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5650         const uint32_t ixgbe_uta_bit_shift = 5;
5651         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5652         const uint32_t bit1 = 0x1;
5653
5654         struct ixgbe_hw *hw =
5655                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5656         struct ixgbe_uta_info *uta_info =
5657                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5658
5659         /* The UTA table only exists on 82599 hardware and newer */
5660         if (hw->mac.type < ixgbe_mac_82599EB)
5661                 return -ENOTSUP;
5662
5663         vector = ixgbe_uta_vector(hw, mac_addr);
5664         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5665         uta_shift = vector & ixgbe_uta_bit_mask;
5666
5667         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5668         if (rc == on)
5669                 return 0;
5670
5671         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5672         if (on) {
5673                 uta_info->uta_in_use++;
5674                 reg_val |= (bit1 << uta_shift);
5675                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5676         } else {
5677                 uta_info->uta_in_use--;
5678                 reg_val &= ~(bit1 << uta_shift);
5679                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5680         }
5681
5682         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5683
5684         if (uta_info->uta_in_use > 0)
5685                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5686                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5687         else
5688                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5689
5690         return 0;
5691 }
5692
5693 static int
5694 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5695 {
5696         int i;
5697         struct ixgbe_hw *hw =
5698                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5699         struct ixgbe_uta_info *uta_info =
5700                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5701
5702         /* The UTA table only exists on 82599 hardware and newer */
5703         if (hw->mac.type < ixgbe_mac_82599EB)
5704                 return -ENOTSUP;
5705
5706         if (on) {
5707                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5708                         uta_info->uta_shadow[i] = ~0;
5709                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5710                 }
5711         } else {
5712                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5713                         uta_info->uta_shadow[i] = 0;
5714                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5715                 }
5716         }
5717         return 0;
5718
5719 }
5720
5721 uint32_t
5722 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5723 {
5724         uint32_t new_val = orig_val;
5725
5726         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5727                 new_val |= IXGBE_VMOLR_AUPE;
5728         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5729                 new_val |= IXGBE_VMOLR_ROMPE;
5730         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5731                 new_val |= IXGBE_VMOLR_ROPE;
5732         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5733                 new_val |= IXGBE_VMOLR_BAM;
5734         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5735                 new_val |= IXGBE_VMOLR_MPE;
5736
5737         return new_val;
5738 }
5739
5740 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5741 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5742 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5743 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5744 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5745         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5746         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5747
5748 static int
5749 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5750                       struct rte_eth_mirror_conf *mirror_conf,
5751                       uint8_t rule_id, uint8_t on)
5752 {
5753         uint32_t mr_ctl, vlvf;
5754         uint32_t mp_lsb = 0;
5755         uint32_t mv_msb = 0;
5756         uint32_t mv_lsb = 0;
5757         uint32_t mp_msb = 0;
5758         uint8_t i = 0;
5759         int reg_index = 0;
5760         uint64_t vlan_mask = 0;
5761
5762         const uint8_t pool_mask_offset = 32;
5763         const uint8_t vlan_mask_offset = 32;
5764         const uint8_t dst_pool_offset = 8;
5765         const uint8_t rule_mr_offset  = 4;
5766         const uint8_t mirror_rule_mask = 0x0F;
5767
5768         struct ixgbe_mirror_info *mr_info =
5769                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5770         struct ixgbe_hw *hw =
5771                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5772         uint8_t mirror_type = 0;
5773
5774         if (ixgbe_vt_check(hw) < 0)
5775                 return -ENOTSUP;
5776
5777         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5778                 return -EINVAL;
5779
5780         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5781                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5782                             mirror_conf->rule_type);
5783                 return -EINVAL;
5784         }
5785
5786         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5787                 mirror_type |= IXGBE_MRCTL_VLME;
5788                 /* Check if vlan id is valid and find conresponding VLAN ID
5789                  * index in VLVF
5790                  */
5791                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5792                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5793                                 /* search vlan id related pool vlan filter
5794                                  * index
5795                                  */
5796                                 reg_index = ixgbe_find_vlvf_slot(
5797                                                 hw,
5798                                                 mirror_conf->vlan.vlan_id[i],
5799                                                 false);
5800                                 if (reg_index < 0)
5801                                         return -EINVAL;
5802                                 vlvf = IXGBE_READ_REG(hw,
5803                                                       IXGBE_VLVF(reg_index));
5804                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5805                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5806                                       mirror_conf->vlan.vlan_id[i]))
5807                                         vlan_mask |= (1ULL << reg_index);
5808                                 else
5809                                         return -EINVAL;
5810                         }
5811                 }
5812
5813                 if (on) {
5814                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5815                         mv_msb = vlan_mask >> vlan_mask_offset;
5816
5817                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5818                                                 mirror_conf->vlan.vlan_mask;
5819                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5820                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5821                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5822                                                 mirror_conf->vlan.vlan_id[i];
5823                         }
5824                 } else {
5825                         mv_lsb = 0;
5826                         mv_msb = 0;
5827                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5828                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5829                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5830                 }
5831         }
5832
5833         /**
5834          * if enable pool mirror, write related pool mask register,if disable
5835          * pool mirror, clear PFMRVM register
5836          */
5837         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5838                 mirror_type |= IXGBE_MRCTL_VPME;
5839                 if (on) {
5840                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5841                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5842                         mr_info->mr_conf[rule_id].pool_mask =
5843                                         mirror_conf->pool_mask;
5844
5845                 } else {
5846                         mp_lsb = 0;
5847                         mp_msb = 0;
5848                         mr_info->mr_conf[rule_id].pool_mask = 0;
5849                 }
5850         }
5851         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5852                 mirror_type |= IXGBE_MRCTL_UPME;
5853         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5854                 mirror_type |= IXGBE_MRCTL_DPME;
5855
5856         /* read  mirror control register and recalculate it */
5857         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5858
5859         if (on) {
5860                 mr_ctl |= mirror_type;
5861                 mr_ctl &= mirror_rule_mask;
5862                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5863         } else {
5864                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5865         }
5866
5867         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5868         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5869
5870         /* write mirrror control  register */
5871         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5872
5873         /* write pool mirrror control  register */
5874         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5875                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5876                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5877                                 mp_msb);
5878         }
5879         /* write VLAN mirrror control  register */
5880         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5881                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5882                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5883                                 mv_msb);
5884         }
5885
5886         return 0;
5887 }
5888
5889 static int
5890 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5891 {
5892         int mr_ctl = 0;
5893         uint32_t lsb_val = 0;
5894         uint32_t msb_val = 0;
5895         const uint8_t rule_mr_offset = 4;
5896
5897         struct ixgbe_hw *hw =
5898                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5899         struct ixgbe_mirror_info *mr_info =
5900                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5901
5902         if (ixgbe_vt_check(hw) < 0)
5903                 return -ENOTSUP;
5904
5905         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5906                 return -EINVAL;
5907
5908         memset(&mr_info->mr_conf[rule_id], 0,
5909                sizeof(struct rte_eth_mirror_conf));
5910
5911         /* clear PFVMCTL register */
5912         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5913
5914         /* clear pool mask register */
5915         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5916         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5917
5918         /* clear vlan mask register */
5919         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5920         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5921
5922         return 0;
5923 }
5924
5925 static int
5926 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5927 {
5928         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5929         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5930         struct ixgbe_interrupt *intr =
5931                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5932         struct ixgbe_hw *hw =
5933                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5934         uint32_t vec = IXGBE_MISC_VEC_ID;
5935
5936         if (rte_intr_allow_others(intr_handle))
5937                 vec = IXGBE_RX_VEC_START;
5938         intr->mask |= (1 << vec);
5939         RTE_SET_USED(queue_id);
5940         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5941
5942         rte_intr_ack(intr_handle);
5943
5944         return 0;
5945 }
5946
5947 static int
5948 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5949 {
5950         struct ixgbe_interrupt *intr =
5951                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5952         struct ixgbe_hw *hw =
5953                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5954         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5955         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5956         uint32_t vec = IXGBE_MISC_VEC_ID;
5957
5958         if (rte_intr_allow_others(intr_handle))
5959                 vec = IXGBE_RX_VEC_START;
5960         intr->mask &= ~(1 << vec);
5961         RTE_SET_USED(queue_id);
5962         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5963
5964         return 0;
5965 }
5966
5967 static int
5968 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5969 {
5970         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5971         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5972         uint32_t mask;
5973         struct ixgbe_hw *hw =
5974                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5975         struct ixgbe_interrupt *intr =
5976                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5977
5978         if (queue_id < 16) {
5979                 ixgbe_disable_intr(hw);
5980                 intr->mask |= (1 << queue_id);
5981                 ixgbe_enable_intr(dev);
5982         } else if (queue_id < 32) {
5983                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5984                 mask &= (1 << queue_id);
5985                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5986         } else if (queue_id < 64) {
5987                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5988                 mask &= (1 << (queue_id - 32));
5989                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5990         }
5991         rte_intr_ack(intr_handle);
5992
5993         return 0;
5994 }
5995
5996 static int
5997 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5998 {
5999         uint32_t mask;
6000         struct ixgbe_hw *hw =
6001                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6002         struct ixgbe_interrupt *intr =
6003                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
6004
6005         if (queue_id < 16) {
6006                 ixgbe_disable_intr(hw);
6007                 intr->mask &= ~(1 << queue_id);
6008                 ixgbe_enable_intr(dev);
6009         } else if (queue_id < 32) {
6010                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6011                 mask &= ~(1 << queue_id);
6012                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6013         } else if (queue_id < 64) {
6014                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6015                 mask &= ~(1 << (queue_id - 32));
6016                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6017         }
6018
6019         return 0;
6020 }
6021
6022 static void
6023 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6024                      uint8_t queue, uint8_t msix_vector)
6025 {
6026         uint32_t tmp, idx;
6027
6028         if (direction == -1) {
6029                 /* other causes */
6030                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6031                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6032                 tmp &= ~0xFF;
6033                 tmp |= msix_vector;
6034                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6035         } else {
6036                 /* rx or tx cause */
6037                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6038                 idx = ((16 * (queue & 1)) + (8 * direction));
6039                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6040                 tmp &= ~(0xFF << idx);
6041                 tmp |= (msix_vector << idx);
6042                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6043         }
6044 }
6045
6046 /**
6047  * set the IVAR registers, mapping interrupt causes to vectors
6048  * @param hw
6049  *  pointer to ixgbe_hw struct
6050  * @direction
6051  *  0 for Rx, 1 for Tx, -1 for other causes
6052  * @queue
6053  *  queue to map the corresponding interrupt to
6054  * @msix_vector
6055  *  the vector to map to the corresponding queue
6056  */
6057 static void
6058 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6059                    uint8_t queue, uint8_t msix_vector)
6060 {
6061         uint32_t tmp, idx;
6062
6063         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6064         if (hw->mac.type == ixgbe_mac_82598EB) {
6065                 if (direction == -1)
6066                         direction = 0;
6067                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6068                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6069                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6070                 tmp |= (msix_vector << (8 * (queue & 0x3)));
6071                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6072         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6073                         (hw->mac.type == ixgbe_mac_X540) ||
6074                         (hw->mac.type == ixgbe_mac_X550) ||
6075                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
6076                 if (direction == -1) {
6077                         /* other causes */
6078                         idx = ((queue & 1) * 8);
6079                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6080                         tmp &= ~(0xFF << idx);
6081                         tmp |= (msix_vector << idx);
6082                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6083                 } else {
6084                         /* rx or tx causes */
6085                         idx = ((16 * (queue & 1)) + (8 * direction));
6086                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6087                         tmp &= ~(0xFF << idx);
6088                         tmp |= (msix_vector << idx);
6089                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6090                 }
6091         }
6092 }
6093
6094 static void
6095 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6096 {
6097         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6098         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6099         struct ixgbe_hw *hw =
6100                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6101         uint32_t q_idx;
6102         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6103         uint32_t base = IXGBE_MISC_VEC_ID;
6104
6105         /* Configure VF other cause ivar */
6106         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6107
6108         /* won't configure msix register if no mapping is done
6109          * between intr vector and event fd.
6110          */
6111         if (!rte_intr_dp_is_en(intr_handle))
6112                 return;
6113
6114         if (rte_intr_allow_others(intr_handle)) {
6115                 base = IXGBE_RX_VEC_START;
6116                 vector_idx = IXGBE_RX_VEC_START;
6117         }
6118
6119         /* Configure all RX queues of VF */
6120         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6121                 /* Force all queue use vector 0,
6122                  * as IXGBE_VF_MAXMSIVECOTR = 1
6123                  */
6124                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6125                 intr_handle->intr_vec[q_idx] = vector_idx;
6126                 if (vector_idx < base + intr_handle->nb_efd - 1)
6127                         vector_idx++;
6128         }
6129
6130         /* As RX queue setting above show, all queues use the vector 0.
6131          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6132          */
6133         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6134                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6135                         | IXGBE_EITR_CNT_WDIS);
6136 }
6137
6138 /**
6139  * Sets up the hardware to properly generate MSI-X interrupts
6140  * @hw
6141  *  board private structure
6142  */
6143 static void
6144 ixgbe_configure_msix(struct rte_eth_dev *dev)
6145 {
6146         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6147         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6148         struct ixgbe_hw *hw =
6149                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6150         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6151         uint32_t vec = IXGBE_MISC_VEC_ID;
6152         uint32_t mask;
6153         uint32_t gpie;
6154
6155         /* won't configure msix register if no mapping is done
6156          * between intr vector and event fd
6157          * but if misx has been enabled already, need to configure
6158          * auto clean, auto mask and throttling.
6159          */
6160         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6161         if (!rte_intr_dp_is_en(intr_handle) &&
6162             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6163                 return;
6164
6165         if (rte_intr_allow_others(intr_handle))
6166                 vec = base = IXGBE_RX_VEC_START;
6167
6168         /* setup GPIE for MSI-x mode */
6169         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6170         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6171                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6172         /* auto clearing and auto setting corresponding bits in EIMS
6173          * when MSI-X interrupt is triggered
6174          */
6175         if (hw->mac.type == ixgbe_mac_82598EB) {
6176                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6177         } else {
6178                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6179                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6180         }
6181         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6182
6183         /* Populate the IVAR table and set the ITR values to the
6184          * corresponding register.
6185          */
6186         if (rte_intr_dp_is_en(intr_handle)) {
6187                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6188                         queue_id++) {
6189                         /* by default, 1:1 mapping */
6190                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6191                         intr_handle->intr_vec[queue_id] = vec;
6192                         if (vec < base + intr_handle->nb_efd - 1)
6193                                 vec++;
6194                 }
6195
6196                 switch (hw->mac.type) {
6197                 case ixgbe_mac_82598EB:
6198                         ixgbe_set_ivar_map(hw, -1,
6199                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6200                                            IXGBE_MISC_VEC_ID);
6201                         break;
6202                 case ixgbe_mac_82599EB:
6203                 case ixgbe_mac_X540:
6204                 case ixgbe_mac_X550:
6205                 case ixgbe_mac_X550EM_x:
6206                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6207                         break;
6208                 default:
6209                         break;
6210                 }
6211         }
6212         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6213                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6214                         | IXGBE_EITR_CNT_WDIS);
6215
6216         /* set up to autoclear timer, and the vectors */
6217         mask = IXGBE_EIMS_ENABLE_MASK;
6218         mask &= ~(IXGBE_EIMS_OTHER |
6219                   IXGBE_EIMS_MAILBOX |
6220                   IXGBE_EIMS_LSC);
6221
6222         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6223 }
6224
6225 int
6226 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6227                            uint16_t queue_idx, uint16_t tx_rate)
6228 {
6229         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6230         struct rte_eth_rxmode *rxmode;
6231         uint32_t rf_dec, rf_int;
6232         uint32_t bcnrc_val;
6233         uint16_t link_speed = dev->data->dev_link.link_speed;
6234
6235         if (queue_idx >= hw->mac.max_tx_queues)
6236                 return -EINVAL;
6237
6238         if (tx_rate != 0) {
6239                 /* Calculate the rate factor values to set */
6240                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6241                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6242                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6243
6244                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6245                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6246                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6247                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6248         } else {
6249                 bcnrc_val = 0;
6250         }
6251
6252         rxmode = &dev->data->dev_conf.rxmode;
6253         /*
6254          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6255          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6256          * set as 0x4.
6257          */
6258         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6259             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6260                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6261                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6262         else
6263                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6264                         IXGBE_MMW_SIZE_DEFAULT);
6265
6266         /* Set RTTBCNRC of queue X */
6267         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6268         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6269         IXGBE_WRITE_FLUSH(hw);
6270
6271         return 0;
6272 }
6273
6274 static int
6275 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6276                      __rte_unused uint32_t index,
6277                      __rte_unused uint32_t pool)
6278 {
6279         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6280         int diag;
6281
6282         /*
6283          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6284          * operation. Trap this case to avoid exhausting the [very limited]
6285          * set of PF resources used to store VF MAC addresses.
6286          */
6287         if (memcmp(hw->mac.perm_addr, mac_addr,
6288                         sizeof(struct rte_ether_addr)) == 0)
6289                 return -1;
6290         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6291         if (diag != 0)
6292                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6293                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6294                             mac_addr->addr_bytes[0],
6295                             mac_addr->addr_bytes[1],
6296                             mac_addr->addr_bytes[2],
6297                             mac_addr->addr_bytes[3],
6298                             mac_addr->addr_bytes[4],
6299                             mac_addr->addr_bytes[5],
6300                             diag);
6301         return diag;
6302 }
6303
6304 static void
6305 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6306 {
6307         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6308         struct rte_ether_addr *perm_addr =
6309                 (struct rte_ether_addr *)hw->mac.perm_addr;
6310         struct rte_ether_addr *mac_addr;
6311         uint32_t i;
6312         int diag;
6313
6314         /*
6315          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6316          * not support the deletion of a given MAC address.
6317          * Instead, it imposes to delete all MAC addresses, then to add again
6318          * all MAC addresses with the exception of the one to be deleted.
6319          */
6320         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6321
6322         /*
6323          * Add again all MAC addresses, with the exception of the deleted one
6324          * and of the permanent MAC address.
6325          */
6326         for (i = 0, mac_addr = dev->data->mac_addrs;
6327              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6328                 /* Skip the deleted MAC address */
6329                 if (i == index)
6330                         continue;
6331                 /* Skip NULL MAC addresses */
6332                 if (rte_is_zero_ether_addr(mac_addr))
6333                         continue;
6334                 /* Skip the permanent MAC address */
6335                 if (memcmp(perm_addr, mac_addr,
6336                                 sizeof(struct rte_ether_addr)) == 0)
6337                         continue;
6338                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6339                 if (diag != 0)
6340                         PMD_DRV_LOG(ERR,
6341                                     "Adding again MAC address "
6342                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6343                                     "diag=%d",
6344                                     mac_addr->addr_bytes[0],
6345                                     mac_addr->addr_bytes[1],
6346                                     mac_addr->addr_bytes[2],
6347                                     mac_addr->addr_bytes[3],
6348                                     mac_addr->addr_bytes[4],
6349                                     mac_addr->addr_bytes[5],
6350                                     diag);
6351         }
6352 }
6353
6354 static int
6355 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6356                         struct rte_ether_addr *addr)
6357 {
6358         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6359
6360         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6361
6362         return 0;
6363 }
6364
6365 int
6366 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6367                         struct rte_eth_syn_filter *filter,
6368                         bool add)
6369 {
6370         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6371         struct ixgbe_filter_info *filter_info =
6372                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6373         uint32_t syn_info;
6374         uint32_t synqf;
6375
6376         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6377                 return -EINVAL;
6378
6379         syn_info = filter_info->syn_info;
6380
6381         if (add) {
6382                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6383                         return -EINVAL;
6384                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6385                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6386
6387                 if (filter->hig_pri)
6388                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6389                 else
6390                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6391         } else {
6392                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6393                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6394                         return -ENOENT;
6395                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6396         }
6397
6398         filter_info->syn_info = synqf;
6399         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6400         IXGBE_WRITE_FLUSH(hw);
6401         return 0;
6402 }
6403
6404
6405 static inline enum ixgbe_5tuple_protocol
6406 convert_protocol_type(uint8_t protocol_value)
6407 {
6408         if (protocol_value == IPPROTO_TCP)
6409                 return IXGBE_FILTER_PROTOCOL_TCP;
6410         else if (protocol_value == IPPROTO_UDP)
6411                 return IXGBE_FILTER_PROTOCOL_UDP;
6412         else if (protocol_value == IPPROTO_SCTP)
6413                 return IXGBE_FILTER_PROTOCOL_SCTP;
6414         else
6415                 return IXGBE_FILTER_PROTOCOL_NONE;
6416 }
6417
6418 /* inject a 5-tuple filter to HW */
6419 static inline void
6420 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6421                            struct ixgbe_5tuple_filter *filter)
6422 {
6423         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6424         int i;
6425         uint32_t ftqf, sdpqf;
6426         uint32_t l34timir = 0;
6427         uint8_t mask = 0xff;
6428
6429         i = filter->index;
6430
6431         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6432                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6433         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6434
6435         ftqf = (uint32_t)(filter->filter_info.proto &
6436                 IXGBE_FTQF_PROTOCOL_MASK);
6437         ftqf |= (uint32_t)((filter->filter_info.priority &
6438                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6439         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6440                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6441         if (filter->filter_info.dst_ip_mask == 0)
6442                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6443         if (filter->filter_info.src_port_mask == 0)
6444                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6445         if (filter->filter_info.dst_port_mask == 0)
6446                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6447         if (filter->filter_info.proto_mask == 0)
6448                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6449         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6450         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6451         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6452
6453         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6454         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6455         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6456         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6457
6458         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6459         l34timir |= (uint32_t)(filter->queue <<
6460                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6461         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6462 }
6463
6464 /*
6465  * add a 5tuple filter
6466  *
6467  * @param
6468  * dev: Pointer to struct rte_eth_dev.
6469  * index: the index the filter allocates.
6470  * filter: ponter to the filter that will be added.
6471  * rx_queue: the queue id the filter assigned to.
6472  *
6473  * @return
6474  *    - On success, zero.
6475  *    - On failure, a negative value.
6476  */
6477 static int
6478 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6479                         struct ixgbe_5tuple_filter *filter)
6480 {
6481         struct ixgbe_filter_info *filter_info =
6482                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6483         int i, idx, shift;
6484
6485         /*
6486          * look for an unused 5tuple filter index,
6487          * and insert the filter to list.
6488          */
6489         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6490                 idx = i / (sizeof(uint32_t) * NBBY);
6491                 shift = i % (sizeof(uint32_t) * NBBY);
6492                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6493                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6494                         filter->index = i;
6495                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6496                                           filter,
6497                                           entries);
6498                         break;
6499                 }
6500         }
6501         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6502                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6503                 return -ENOSYS;
6504         }
6505
6506         ixgbe_inject_5tuple_filter(dev, filter);
6507
6508         return 0;
6509 }
6510
6511 /*
6512  * remove a 5tuple filter
6513  *
6514  * @param
6515  * dev: Pointer to struct rte_eth_dev.
6516  * filter: the pointer of the filter will be removed.
6517  */
6518 static void
6519 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6520                         struct ixgbe_5tuple_filter *filter)
6521 {
6522         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6523         struct ixgbe_filter_info *filter_info =
6524                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6525         uint16_t index = filter->index;
6526
6527         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6528                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6529         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6530         rte_free(filter);
6531
6532         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6533         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6534         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6535         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6536         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6537 }
6538
6539 static int
6540 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6541 {
6542         struct ixgbe_hw *hw;
6543         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6544         struct rte_eth_dev_data *dev_data = dev->data;
6545
6546         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6547
6548         if (mtu < RTE_ETHER_MIN_MTU ||
6549                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6550                 return -EINVAL;
6551
6552         /* If device is started, refuse mtu that requires the support of
6553          * scattered packets when this feature has not been enabled before.
6554          */
6555         if (dev_data->dev_started && !dev_data->scattered_rx &&
6556             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6557              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6558                 PMD_INIT_LOG(ERR, "Stop port first.");
6559                 return -EINVAL;
6560         }
6561
6562         /*
6563          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6564          * request of the version 2.0 of the mailbox API.
6565          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6566          * of the mailbox API.
6567          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6568          * prior to 3.11.33 which contains the following change:
6569          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6570          */
6571         ixgbevf_rlpml_set_vf(hw, max_frame);
6572
6573         /* update max frame size */
6574         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6575         return 0;
6576 }
6577
6578 static inline struct ixgbe_5tuple_filter *
6579 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6580                         struct ixgbe_5tuple_filter_info *key)
6581 {
6582         struct ixgbe_5tuple_filter *it;
6583
6584         TAILQ_FOREACH(it, filter_list, entries) {
6585                 if (memcmp(key, &it->filter_info,
6586                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6587                         return it;
6588                 }
6589         }
6590         return NULL;
6591 }
6592
6593 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6594 static inline int
6595 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6596                         struct ixgbe_5tuple_filter_info *filter_info)
6597 {
6598         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6599                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6600                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6601                 return -EINVAL;
6602
6603         switch (filter->dst_ip_mask) {
6604         case UINT32_MAX:
6605                 filter_info->dst_ip_mask = 0;
6606                 filter_info->dst_ip = filter->dst_ip;
6607                 break;
6608         case 0:
6609                 filter_info->dst_ip_mask = 1;
6610                 break;
6611         default:
6612                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6613                 return -EINVAL;
6614         }
6615
6616         switch (filter->src_ip_mask) {
6617         case UINT32_MAX:
6618                 filter_info->src_ip_mask = 0;
6619                 filter_info->src_ip = filter->src_ip;
6620                 break;
6621         case 0:
6622                 filter_info->src_ip_mask = 1;
6623                 break;
6624         default:
6625                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6626                 return -EINVAL;
6627         }
6628
6629         switch (filter->dst_port_mask) {
6630         case UINT16_MAX:
6631                 filter_info->dst_port_mask = 0;
6632                 filter_info->dst_port = filter->dst_port;
6633                 break;
6634         case 0:
6635                 filter_info->dst_port_mask = 1;
6636                 break;
6637         default:
6638                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6639                 return -EINVAL;
6640         }
6641
6642         switch (filter->src_port_mask) {
6643         case UINT16_MAX:
6644                 filter_info->src_port_mask = 0;
6645                 filter_info->src_port = filter->src_port;
6646                 break;
6647         case 0:
6648                 filter_info->src_port_mask = 1;
6649                 break;
6650         default:
6651                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6652                 return -EINVAL;
6653         }
6654
6655         switch (filter->proto_mask) {
6656         case UINT8_MAX:
6657                 filter_info->proto_mask = 0;
6658                 filter_info->proto =
6659                         convert_protocol_type(filter->proto);
6660                 break;
6661         case 0:
6662                 filter_info->proto_mask = 1;
6663                 break;
6664         default:
6665                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6666                 return -EINVAL;
6667         }
6668
6669         filter_info->priority = (uint8_t)filter->priority;
6670         return 0;
6671 }
6672
6673 /*
6674  * add or delete a ntuple filter
6675  *
6676  * @param
6677  * dev: Pointer to struct rte_eth_dev.
6678  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6679  * add: if true, add filter, if false, remove filter
6680  *
6681  * @return
6682  *    - On success, zero.
6683  *    - On failure, a negative value.
6684  */
6685 int
6686 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6687                         struct rte_eth_ntuple_filter *ntuple_filter,
6688                         bool add)
6689 {
6690         struct ixgbe_filter_info *filter_info =
6691                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6692         struct ixgbe_5tuple_filter_info filter_5tuple;
6693         struct ixgbe_5tuple_filter *filter;
6694         int ret;
6695
6696         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6697                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6698                 return -EINVAL;
6699         }
6700
6701         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6702         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6703         if (ret < 0)
6704                 return ret;
6705
6706         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6707                                          &filter_5tuple);
6708         if (filter != NULL && add) {
6709                 PMD_DRV_LOG(ERR, "filter exists.");
6710                 return -EEXIST;
6711         }
6712         if (filter == NULL && !add) {
6713                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6714                 return -ENOENT;
6715         }
6716
6717         if (add) {
6718                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6719                                 sizeof(struct ixgbe_5tuple_filter), 0);
6720                 if (filter == NULL)
6721                         return -ENOMEM;
6722                 rte_memcpy(&filter->filter_info,
6723                                  &filter_5tuple,
6724                                  sizeof(struct ixgbe_5tuple_filter_info));
6725                 filter->queue = ntuple_filter->queue;
6726                 ret = ixgbe_add_5tuple_filter(dev, filter);
6727                 if (ret < 0) {
6728                         rte_free(filter);
6729                         return ret;
6730                 }
6731         } else
6732                 ixgbe_remove_5tuple_filter(dev, filter);
6733
6734         return 0;
6735 }
6736
6737 int
6738 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6739                         struct rte_eth_ethertype_filter *filter,
6740                         bool add)
6741 {
6742         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6743         struct ixgbe_filter_info *filter_info =
6744                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6745         uint32_t etqf = 0;
6746         uint32_t etqs = 0;
6747         int ret;
6748         struct ixgbe_ethertype_filter ethertype_filter;
6749
6750         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6751                 return -EINVAL;
6752
6753         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6754                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6755                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6756                         " ethertype filter.", filter->ether_type);
6757                 return -EINVAL;
6758         }
6759
6760         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6761                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6762                 return -EINVAL;
6763         }
6764         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6765                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6766                 return -EINVAL;
6767         }
6768
6769         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6770         if (ret >= 0 && add) {
6771                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6772                             filter->ether_type);
6773                 return -EEXIST;
6774         }
6775         if (ret < 0 && !add) {
6776                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6777                             filter->ether_type);
6778                 return -ENOENT;
6779         }
6780
6781         if (add) {
6782                 etqf = IXGBE_ETQF_FILTER_EN;
6783                 etqf |= (uint32_t)filter->ether_type;
6784                 etqs |= (uint32_t)((filter->queue <<
6785                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6786                                     IXGBE_ETQS_RX_QUEUE);
6787                 etqs |= IXGBE_ETQS_QUEUE_EN;
6788
6789                 ethertype_filter.ethertype = filter->ether_type;
6790                 ethertype_filter.etqf = etqf;
6791                 ethertype_filter.etqs = etqs;
6792                 ethertype_filter.conf = FALSE;
6793                 ret = ixgbe_ethertype_filter_insert(filter_info,
6794                                                     &ethertype_filter);
6795                 if (ret < 0) {
6796                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6797                         return -ENOSPC;
6798                 }
6799         } else {
6800                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6801                 if (ret < 0)
6802                         return -ENOSYS;
6803         }
6804         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6805         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6806         IXGBE_WRITE_FLUSH(hw);
6807
6808         return 0;
6809 }
6810
6811 static int
6812 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6813                      enum rte_filter_type filter_type,
6814                      enum rte_filter_op filter_op,
6815                      void *arg)
6816 {
6817         int ret = 0;
6818
6819         switch (filter_type) {
6820         case RTE_ETH_FILTER_FDIR:
6821                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6822                 break;
6823         case RTE_ETH_FILTER_L2_TUNNEL:
6824                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6825                 break;
6826         case RTE_ETH_FILTER_GENERIC:
6827                 if (filter_op != RTE_ETH_FILTER_GET)
6828                         return -EINVAL;
6829                 *(const void **)arg = &ixgbe_flow_ops;
6830                 break;
6831         default:
6832                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6833                                                         filter_type);
6834                 ret = -EINVAL;
6835                 break;
6836         }
6837
6838         return ret;
6839 }
6840
6841 static u8 *
6842 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
6843                         u8 **mc_addr_ptr, u32 *vmdq)
6844 {
6845         u8 *mc_addr;
6846
6847         *vmdq = 0;
6848         mc_addr = *mc_addr_ptr;
6849         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6850         return mc_addr;
6851 }
6852
6853 static int
6854 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6855                           struct rte_ether_addr *mc_addr_set,
6856                           uint32_t nb_mc_addr)
6857 {
6858         struct ixgbe_hw *hw;
6859         u8 *mc_addr_list;
6860
6861         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6862         mc_addr_list = (u8 *)mc_addr_set;
6863         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6864                                          ixgbe_dev_addr_list_itr, TRUE);
6865 }
6866
6867 static uint64_t
6868 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6869 {
6870         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6871         uint64_t systime_cycles;
6872
6873         switch (hw->mac.type) {
6874         case ixgbe_mac_X550:
6875         case ixgbe_mac_X550EM_x:
6876         case ixgbe_mac_X550EM_a:
6877                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6878                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6879                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6880                                 * NSEC_PER_SEC;
6881                 break;
6882         default:
6883                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6884                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6885                                 << 32;
6886         }
6887
6888         return systime_cycles;
6889 }
6890
6891 static uint64_t
6892 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6893 {
6894         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6895         uint64_t rx_tstamp_cycles;
6896
6897         switch (hw->mac.type) {
6898         case ixgbe_mac_X550:
6899         case ixgbe_mac_X550EM_x:
6900         case ixgbe_mac_X550EM_a:
6901                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6902                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6903                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6904                                 * NSEC_PER_SEC;
6905                 break;
6906         default:
6907                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6908                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6909                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6910                                 << 32;
6911         }
6912
6913         return rx_tstamp_cycles;
6914 }
6915
6916 static uint64_t
6917 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6918 {
6919         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6920         uint64_t tx_tstamp_cycles;
6921
6922         switch (hw->mac.type) {
6923         case ixgbe_mac_X550:
6924         case ixgbe_mac_X550EM_x:
6925         case ixgbe_mac_X550EM_a:
6926                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6927                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6928                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6929                                 * NSEC_PER_SEC;
6930                 break;
6931         default:
6932                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6933                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6934                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6935                                 << 32;
6936         }
6937
6938         return tx_tstamp_cycles;
6939 }
6940
6941 static void
6942 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6943 {
6944         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6945         struct ixgbe_adapter *adapter = dev->data->dev_private;
6946         struct rte_eth_link link;
6947         uint32_t incval = 0;
6948         uint32_t shift = 0;
6949
6950         /* Get current link speed. */
6951         ixgbe_dev_link_update(dev, 1);
6952         rte_eth_linkstatus_get(dev, &link);
6953
6954         switch (link.link_speed) {
6955         case ETH_SPEED_NUM_100M:
6956                 incval = IXGBE_INCVAL_100;
6957                 shift = IXGBE_INCVAL_SHIFT_100;
6958                 break;
6959         case ETH_SPEED_NUM_1G:
6960                 incval = IXGBE_INCVAL_1GB;
6961                 shift = IXGBE_INCVAL_SHIFT_1GB;
6962                 break;
6963         case ETH_SPEED_NUM_10G:
6964         default:
6965                 incval = IXGBE_INCVAL_10GB;
6966                 shift = IXGBE_INCVAL_SHIFT_10GB;
6967                 break;
6968         }
6969
6970         switch (hw->mac.type) {
6971         case ixgbe_mac_X550:
6972         case ixgbe_mac_X550EM_x:
6973         case ixgbe_mac_X550EM_a:
6974                 /* Independent of link speed. */
6975                 incval = 1;
6976                 /* Cycles read will be interpreted as ns. */
6977                 shift = 0;
6978                 /* Fall-through */
6979         case ixgbe_mac_X540:
6980                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6981                 break;
6982         case ixgbe_mac_82599EB:
6983                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6984                 shift -= IXGBE_INCVAL_SHIFT_82599;
6985                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6986                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6987                 break;
6988         default:
6989                 /* Not supported. */
6990                 return;
6991         }
6992
6993         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6994         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6995         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6996
6997         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6998         adapter->systime_tc.cc_shift = shift;
6999         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7000
7001         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7002         adapter->rx_tstamp_tc.cc_shift = shift;
7003         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7004
7005         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7006         adapter->tx_tstamp_tc.cc_shift = shift;
7007         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7008 }
7009
7010 static int
7011 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7012 {
7013         struct ixgbe_adapter *adapter = dev->data->dev_private;
7014
7015         adapter->systime_tc.nsec += delta;
7016         adapter->rx_tstamp_tc.nsec += delta;
7017         adapter->tx_tstamp_tc.nsec += delta;
7018
7019         return 0;
7020 }
7021
7022 static int
7023 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7024 {
7025         uint64_t ns;
7026         struct ixgbe_adapter *adapter = dev->data->dev_private;
7027
7028         ns = rte_timespec_to_ns(ts);
7029         /* Set the timecounters to a new value. */
7030         adapter->systime_tc.nsec = ns;
7031         adapter->rx_tstamp_tc.nsec = ns;
7032         adapter->tx_tstamp_tc.nsec = ns;
7033
7034         return 0;
7035 }
7036
7037 static int
7038 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7039 {
7040         uint64_t ns, systime_cycles;
7041         struct ixgbe_adapter *adapter = dev->data->dev_private;
7042
7043         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7044         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7045         *ts = rte_ns_to_timespec(ns);
7046
7047         return 0;
7048 }
7049
7050 static int
7051 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7052 {
7053         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7054         uint32_t tsync_ctl;
7055         uint32_t tsauxc;
7056
7057         /* Stop the timesync system time. */
7058         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7059         /* Reset the timesync system time value. */
7060         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7061         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7062
7063         /* Enable system time for platforms where it isn't on by default. */
7064         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7065         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7066         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7067
7068         ixgbe_start_timecounters(dev);
7069
7070         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7071         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7072                         (RTE_ETHER_TYPE_1588 |
7073                          IXGBE_ETQF_FILTER_EN |
7074                          IXGBE_ETQF_1588));
7075
7076         /* Enable timestamping of received PTP packets. */
7077         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7078         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7079         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7080
7081         /* Enable timestamping of transmitted PTP packets. */
7082         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7083         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7084         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7085
7086         IXGBE_WRITE_FLUSH(hw);
7087
7088         return 0;
7089 }
7090
7091 static int
7092 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7093 {
7094         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7095         uint32_t tsync_ctl;
7096
7097         /* Disable timestamping of transmitted PTP packets. */
7098         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7099         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7100         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7101
7102         /* Disable timestamping of received PTP packets. */
7103         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7104         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7105         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7106
7107         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7108         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7109
7110         /* Stop incrementating the System Time registers. */
7111         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7112
7113         return 0;
7114 }
7115
7116 static int
7117 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7118                                  struct timespec *timestamp,
7119                                  uint32_t flags __rte_unused)
7120 {
7121         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7122         struct ixgbe_adapter *adapter = dev->data->dev_private;
7123         uint32_t tsync_rxctl;
7124         uint64_t rx_tstamp_cycles;
7125         uint64_t ns;
7126
7127         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7128         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7129                 return -EINVAL;
7130
7131         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7132         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7133         *timestamp = rte_ns_to_timespec(ns);
7134
7135         return  0;
7136 }
7137
7138 static int
7139 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7140                                  struct timespec *timestamp)
7141 {
7142         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7143         struct ixgbe_adapter *adapter = dev->data->dev_private;
7144         uint32_t tsync_txctl;
7145         uint64_t tx_tstamp_cycles;
7146         uint64_t ns;
7147
7148         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7149         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7150                 return -EINVAL;
7151
7152         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7153         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7154         *timestamp = rte_ns_to_timespec(ns);
7155
7156         return 0;
7157 }
7158
7159 static int
7160 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7161 {
7162         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7163         int count = 0;
7164         int g_ind = 0;
7165         const struct reg_info *reg_group;
7166         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7167                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7168
7169         while ((reg_group = reg_set[g_ind++]))
7170                 count += ixgbe_regs_group_count(reg_group);
7171
7172         return count;
7173 }
7174
7175 static int
7176 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7177 {
7178         int count = 0;
7179         int g_ind = 0;
7180         const struct reg_info *reg_group;
7181
7182         while ((reg_group = ixgbevf_regs[g_ind++]))
7183                 count += ixgbe_regs_group_count(reg_group);
7184
7185         return count;
7186 }
7187
7188 static int
7189 ixgbe_get_regs(struct rte_eth_dev *dev,
7190               struct rte_dev_reg_info *regs)
7191 {
7192         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7193         uint32_t *data = regs->data;
7194         int g_ind = 0;
7195         int count = 0;
7196         const struct reg_info *reg_group;
7197         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7198                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7199
7200         if (data == NULL) {
7201                 regs->length = ixgbe_get_reg_length(dev);
7202                 regs->width = sizeof(uint32_t);
7203                 return 0;
7204         }
7205
7206         /* Support only full register dump */
7207         if ((regs->length == 0) ||
7208             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7209                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7210                         hw->device_id;
7211                 while ((reg_group = reg_set[g_ind++]))
7212                         count += ixgbe_read_regs_group(dev, &data[count],
7213                                 reg_group);
7214                 return 0;
7215         }
7216
7217         return -ENOTSUP;
7218 }
7219
7220 static int
7221 ixgbevf_get_regs(struct rte_eth_dev *dev,
7222                 struct rte_dev_reg_info *regs)
7223 {
7224         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7225         uint32_t *data = regs->data;
7226         int g_ind = 0;
7227         int count = 0;
7228         const struct reg_info *reg_group;
7229
7230         if (data == NULL) {
7231                 regs->length = ixgbevf_get_reg_length(dev);
7232                 regs->width = sizeof(uint32_t);
7233                 return 0;
7234         }
7235
7236         /* Support only full register dump */
7237         if ((regs->length == 0) ||
7238             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7239                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7240                         hw->device_id;
7241                 while ((reg_group = ixgbevf_regs[g_ind++]))
7242                         count += ixgbe_read_regs_group(dev, &data[count],
7243                                                       reg_group);
7244                 return 0;
7245         }
7246
7247         return -ENOTSUP;
7248 }
7249
7250 static int
7251 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7252 {
7253         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7254
7255         /* Return unit is byte count */
7256         return hw->eeprom.word_size * 2;
7257 }
7258
7259 static int
7260 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7261                 struct rte_dev_eeprom_info *in_eeprom)
7262 {
7263         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7264         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7265         uint16_t *data = in_eeprom->data;
7266         int first, length;
7267
7268         first = in_eeprom->offset >> 1;
7269         length = in_eeprom->length >> 1;
7270         if ((first > hw->eeprom.word_size) ||
7271             ((first + length) > hw->eeprom.word_size))
7272                 return -EINVAL;
7273
7274         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7275
7276         return eeprom->ops.read_buffer(hw, first, length, data);
7277 }
7278
7279 static int
7280 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7281                 struct rte_dev_eeprom_info *in_eeprom)
7282 {
7283         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7284         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7285         uint16_t *data = in_eeprom->data;
7286         int first, length;
7287
7288         first = in_eeprom->offset >> 1;
7289         length = in_eeprom->length >> 1;
7290         if ((first > hw->eeprom.word_size) ||
7291             ((first + length) > hw->eeprom.word_size))
7292                 return -EINVAL;
7293
7294         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7295
7296         return eeprom->ops.write_buffer(hw,  first, length, data);
7297 }
7298
7299 static int
7300 ixgbe_get_module_info(struct rte_eth_dev *dev,
7301                       struct rte_eth_dev_module_info *modinfo)
7302 {
7303         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7304         uint32_t status;
7305         uint8_t sff8472_rev, addr_mode;
7306         bool page_swap = false;
7307
7308         /* Check whether we support SFF-8472 or not */
7309         status = hw->phy.ops.read_i2c_eeprom(hw,
7310                                              IXGBE_SFF_SFF_8472_COMP,
7311                                              &sff8472_rev);
7312         if (status != 0)
7313                 return -EIO;
7314
7315         /* addressing mode is not supported */
7316         status = hw->phy.ops.read_i2c_eeprom(hw,
7317                                              IXGBE_SFF_SFF_8472_SWAP,
7318                                              &addr_mode);
7319         if (status != 0)
7320                 return -EIO;
7321
7322         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7323                 PMD_DRV_LOG(ERR,
7324                             "Address change required to access page 0xA2, "
7325                             "but not supported. Please report the module "
7326                             "type to the driver maintainers.");
7327                 page_swap = true;
7328         }
7329
7330         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7331                 /* We have a SFP, but it does not support SFF-8472 */
7332                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7333                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7334         } else {
7335                 /* We have a SFP which supports a revision of SFF-8472. */
7336                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7337                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7338         }
7339
7340         return 0;
7341 }
7342
7343 static int
7344 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7345                         struct rte_dev_eeprom_info *info)
7346 {
7347         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7348         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7349         uint8_t databyte = 0xFF;
7350         uint8_t *data = info->data;
7351         uint32_t i = 0;
7352
7353         if (info->length == 0)
7354                 return -EINVAL;
7355
7356         for (i = info->offset; i < info->offset + info->length; i++) {
7357                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7358                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7359                 else
7360                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7361
7362                 if (status != 0)
7363                         return -EIO;
7364
7365                 data[i - info->offset] = databyte;
7366         }
7367
7368         return 0;
7369 }
7370
7371 uint16_t
7372 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7373         switch (mac_type) {
7374         case ixgbe_mac_X550:
7375         case ixgbe_mac_X550EM_x:
7376         case ixgbe_mac_X550EM_a:
7377                 return ETH_RSS_RETA_SIZE_512;
7378         case ixgbe_mac_X550_vf:
7379         case ixgbe_mac_X550EM_x_vf:
7380         case ixgbe_mac_X550EM_a_vf:
7381                 return ETH_RSS_RETA_SIZE_64;
7382         case ixgbe_mac_X540_vf:
7383         case ixgbe_mac_82599_vf:
7384                 return 0;
7385         default:
7386                 return ETH_RSS_RETA_SIZE_128;
7387         }
7388 }
7389
7390 uint32_t
7391 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7392         switch (mac_type) {
7393         case ixgbe_mac_X550:
7394         case ixgbe_mac_X550EM_x:
7395         case ixgbe_mac_X550EM_a:
7396                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7397                         return IXGBE_RETA(reta_idx >> 2);
7398                 else
7399                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7400         case ixgbe_mac_X550_vf:
7401         case ixgbe_mac_X550EM_x_vf:
7402         case ixgbe_mac_X550EM_a_vf:
7403                 return IXGBE_VFRETA(reta_idx >> 2);
7404         default:
7405                 return IXGBE_RETA(reta_idx >> 2);
7406         }
7407 }
7408
7409 uint32_t
7410 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7411         switch (mac_type) {
7412         case ixgbe_mac_X550_vf:
7413         case ixgbe_mac_X550EM_x_vf:
7414         case ixgbe_mac_X550EM_a_vf:
7415                 return IXGBE_VFMRQC;
7416         default:
7417                 return IXGBE_MRQC;
7418         }
7419 }
7420
7421 uint32_t
7422 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7423         switch (mac_type) {
7424         case ixgbe_mac_X550_vf:
7425         case ixgbe_mac_X550EM_x_vf:
7426         case ixgbe_mac_X550EM_a_vf:
7427                 return IXGBE_VFRSSRK(i);
7428         default:
7429                 return IXGBE_RSSRK(i);
7430         }
7431 }
7432
7433 bool
7434 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7435         switch (mac_type) {
7436         case ixgbe_mac_82599_vf:
7437         case ixgbe_mac_X540_vf:
7438                 return 0;
7439         default:
7440                 return 1;
7441         }
7442 }
7443
7444 static int
7445 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7446                         struct rte_eth_dcb_info *dcb_info)
7447 {
7448         struct ixgbe_dcb_config *dcb_config =
7449                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7450         struct ixgbe_dcb_tc_config *tc;
7451         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7452         uint8_t nb_tcs;
7453         uint8_t i, j;
7454
7455         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7456                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7457         else
7458                 dcb_info->nb_tcs = 1;
7459
7460         tc_queue = &dcb_info->tc_queue;
7461         nb_tcs = dcb_info->nb_tcs;
7462
7463         if (dcb_config->vt_mode) { /* vt is enabled*/
7464                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7465                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7466                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7467                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7468                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7469                         for (j = 0; j < nb_tcs; j++) {
7470                                 tc_queue->tc_rxq[0][j].base = j;
7471                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7472                                 tc_queue->tc_txq[0][j].base = j;
7473                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7474                         }
7475                 } else {
7476                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7477                                 for (j = 0; j < nb_tcs; j++) {
7478                                         tc_queue->tc_rxq[i][j].base =
7479                                                 i * nb_tcs + j;
7480                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7481                                         tc_queue->tc_txq[i][j].base =
7482                                                 i * nb_tcs + j;
7483                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7484                                 }
7485                         }
7486                 }
7487         } else { /* vt is disabled*/
7488                 struct rte_eth_dcb_rx_conf *rx_conf =
7489                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7490                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7491                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7492                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7493                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7494                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7495                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7496                         }
7497                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7498                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7499                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7500                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7501                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7502                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7503                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7504                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7505                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7506                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7507                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7508                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7509                         }
7510                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7511                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7512                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7513                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7514                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7515                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7516                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7517                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7518                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7519                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7520                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7521                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7522                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7523                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7524                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7525                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7526                 }
7527         }
7528         for (i = 0; i < dcb_info->nb_tcs; i++) {
7529                 tc = &dcb_config->tc_config[i];
7530                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7531         }
7532         return 0;
7533 }
7534
7535 /* Update e-tag ether type */
7536 static int
7537 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7538                             uint16_t ether_type)
7539 {
7540         uint32_t etag_etype;
7541
7542         if (hw->mac.type != ixgbe_mac_X550 &&
7543             hw->mac.type != ixgbe_mac_X550EM_x &&
7544             hw->mac.type != ixgbe_mac_X550EM_a) {
7545                 return -ENOTSUP;
7546         }
7547
7548         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7549         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7550         etag_etype |= ether_type;
7551         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7552         IXGBE_WRITE_FLUSH(hw);
7553
7554         return 0;
7555 }
7556
7557 /* Config l2 tunnel ether type */
7558 static int
7559 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7560                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7561 {
7562         int ret = 0;
7563         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7564         struct ixgbe_l2_tn_info *l2_tn_info =
7565                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7566
7567         if (l2_tunnel == NULL)
7568                 return -EINVAL;
7569
7570         switch (l2_tunnel->l2_tunnel_type) {
7571         case RTE_L2_TUNNEL_TYPE_E_TAG:
7572                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7573                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7574                 break;
7575         default:
7576                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7577                 ret = -EINVAL;
7578                 break;
7579         }
7580
7581         return ret;
7582 }
7583
7584 /* Enable e-tag tunnel */
7585 static int
7586 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7587 {
7588         uint32_t etag_etype;
7589
7590         if (hw->mac.type != ixgbe_mac_X550 &&
7591             hw->mac.type != ixgbe_mac_X550EM_x &&
7592             hw->mac.type != ixgbe_mac_X550EM_a) {
7593                 return -ENOTSUP;
7594         }
7595
7596         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7597         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7598         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7599         IXGBE_WRITE_FLUSH(hw);
7600
7601         return 0;
7602 }
7603
7604 /* Enable l2 tunnel */
7605 static int
7606 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7607                            enum rte_eth_tunnel_type l2_tunnel_type)
7608 {
7609         int ret = 0;
7610         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7611         struct ixgbe_l2_tn_info *l2_tn_info =
7612                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7613
7614         switch (l2_tunnel_type) {
7615         case RTE_L2_TUNNEL_TYPE_E_TAG:
7616                 l2_tn_info->e_tag_en = TRUE;
7617                 ret = ixgbe_e_tag_enable(hw);
7618                 break;
7619         default:
7620                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7621                 ret = -EINVAL;
7622                 break;
7623         }
7624
7625         return ret;
7626 }
7627
7628 /* Disable e-tag tunnel */
7629 static int
7630 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7631 {
7632         uint32_t etag_etype;
7633
7634         if (hw->mac.type != ixgbe_mac_X550 &&
7635             hw->mac.type != ixgbe_mac_X550EM_x &&
7636             hw->mac.type != ixgbe_mac_X550EM_a) {
7637                 return -ENOTSUP;
7638         }
7639
7640         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7641         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7642         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7643         IXGBE_WRITE_FLUSH(hw);
7644
7645         return 0;
7646 }
7647
7648 /* Disable l2 tunnel */
7649 static int
7650 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7651                             enum rte_eth_tunnel_type l2_tunnel_type)
7652 {
7653         int ret = 0;
7654         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7655         struct ixgbe_l2_tn_info *l2_tn_info =
7656                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7657
7658         switch (l2_tunnel_type) {
7659         case RTE_L2_TUNNEL_TYPE_E_TAG:
7660                 l2_tn_info->e_tag_en = FALSE;
7661                 ret = ixgbe_e_tag_disable(hw);
7662                 break;
7663         default:
7664                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7665                 ret = -EINVAL;
7666                 break;
7667         }
7668
7669         return ret;
7670 }
7671
7672 static int
7673 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7674                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7675 {
7676         int ret = 0;
7677         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7678         uint32_t i, rar_entries;
7679         uint32_t rar_low, rar_high;
7680
7681         if (hw->mac.type != ixgbe_mac_X550 &&
7682             hw->mac.type != ixgbe_mac_X550EM_x &&
7683             hw->mac.type != ixgbe_mac_X550EM_a) {
7684                 return -ENOTSUP;
7685         }
7686
7687         rar_entries = ixgbe_get_num_rx_addrs(hw);
7688
7689         for (i = 1; i < rar_entries; i++) {
7690                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7691                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7692                 if ((rar_high & IXGBE_RAH_AV) &&
7693                     (rar_high & IXGBE_RAH_ADTYPE) &&
7694                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7695                      l2_tunnel->tunnel_id)) {
7696                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7697                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7698
7699                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7700
7701                         return ret;
7702                 }
7703         }
7704
7705         return ret;
7706 }
7707
7708 static int
7709 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7710                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7711 {
7712         int ret = 0;
7713         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7714         uint32_t i, rar_entries;
7715         uint32_t rar_low, rar_high;
7716
7717         if (hw->mac.type != ixgbe_mac_X550 &&
7718             hw->mac.type != ixgbe_mac_X550EM_x &&
7719             hw->mac.type != ixgbe_mac_X550EM_a) {
7720                 return -ENOTSUP;
7721         }
7722
7723         /* One entry for one tunnel. Try to remove potential existing entry. */
7724         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7725
7726         rar_entries = ixgbe_get_num_rx_addrs(hw);
7727
7728         for (i = 1; i < rar_entries; i++) {
7729                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7730                 if (rar_high & IXGBE_RAH_AV) {
7731                         continue;
7732                 } else {
7733                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7734                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7735                         rar_low = l2_tunnel->tunnel_id;
7736
7737                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7738                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7739
7740                         return ret;
7741                 }
7742         }
7743
7744         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7745                      " Please remove a rule before adding a new one.");
7746         return -EINVAL;
7747 }
7748
7749 static inline struct ixgbe_l2_tn_filter *
7750 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7751                           struct ixgbe_l2_tn_key *key)
7752 {
7753         int ret;
7754
7755         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7756         if (ret < 0)
7757                 return NULL;
7758
7759         return l2_tn_info->hash_map[ret];
7760 }
7761
7762 static inline int
7763 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7764                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7765 {
7766         int ret;
7767
7768         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7769                                &l2_tn_filter->key);
7770
7771         if (ret < 0) {
7772                 PMD_DRV_LOG(ERR,
7773                             "Failed to insert L2 tunnel filter"
7774                             " to hash table %d!",
7775                             ret);
7776                 return ret;
7777         }
7778
7779         l2_tn_info->hash_map[ret] = l2_tn_filter;
7780
7781         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7782
7783         return 0;
7784 }
7785
7786 static inline int
7787 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7788                           struct ixgbe_l2_tn_key *key)
7789 {
7790         int ret;
7791         struct ixgbe_l2_tn_filter *l2_tn_filter;
7792
7793         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7794
7795         if (ret < 0) {
7796                 PMD_DRV_LOG(ERR,
7797                             "No such L2 tunnel filter to delete %d!",
7798                             ret);
7799                 return ret;
7800         }
7801
7802         l2_tn_filter = l2_tn_info->hash_map[ret];
7803         l2_tn_info->hash_map[ret] = NULL;
7804
7805         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7806         rte_free(l2_tn_filter);
7807
7808         return 0;
7809 }
7810
7811 /* Add l2 tunnel filter */
7812 int
7813 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7814                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7815                                bool restore)
7816 {
7817         int ret;
7818         struct ixgbe_l2_tn_info *l2_tn_info =
7819                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7820         struct ixgbe_l2_tn_key key;
7821         struct ixgbe_l2_tn_filter *node;
7822
7823         if (!restore) {
7824                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7825                 key.tn_id = l2_tunnel->tunnel_id;
7826
7827                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7828
7829                 if (node) {
7830                         PMD_DRV_LOG(ERR,
7831                                     "The L2 tunnel filter already exists!");
7832                         return -EINVAL;
7833                 }
7834
7835                 node = rte_zmalloc("ixgbe_l2_tn",
7836                                    sizeof(struct ixgbe_l2_tn_filter),
7837                                    0);
7838                 if (!node)
7839                         return -ENOMEM;
7840
7841                 rte_memcpy(&node->key,
7842                                  &key,
7843                                  sizeof(struct ixgbe_l2_tn_key));
7844                 node->pool = l2_tunnel->pool;
7845                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7846                 if (ret < 0) {
7847                         rte_free(node);
7848                         return ret;
7849                 }
7850         }
7851
7852         switch (l2_tunnel->l2_tunnel_type) {
7853         case RTE_L2_TUNNEL_TYPE_E_TAG:
7854                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7855                 break;
7856         default:
7857                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7858                 ret = -EINVAL;
7859                 break;
7860         }
7861
7862         if ((!restore) && (ret < 0))
7863                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7864
7865         return ret;
7866 }
7867
7868 /* Delete l2 tunnel filter */
7869 int
7870 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7871                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7872 {
7873         int ret;
7874         struct ixgbe_l2_tn_info *l2_tn_info =
7875                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7876         struct ixgbe_l2_tn_key key;
7877
7878         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7879         key.tn_id = l2_tunnel->tunnel_id;
7880         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7881         if (ret < 0)
7882                 return ret;
7883
7884         switch (l2_tunnel->l2_tunnel_type) {
7885         case RTE_L2_TUNNEL_TYPE_E_TAG:
7886                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7887                 break;
7888         default:
7889                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7890                 ret = -EINVAL;
7891                 break;
7892         }
7893
7894         return ret;
7895 }
7896
7897 /**
7898  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7899  * @dev: pointer to rte_eth_dev structure
7900  * @filter_op:operation will be taken.
7901  * @arg: a pointer to specific structure corresponding to the filter_op
7902  */
7903 static int
7904 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7905                                   enum rte_filter_op filter_op,
7906                                   void *arg)
7907 {
7908         int ret;
7909
7910         if (filter_op == RTE_ETH_FILTER_NOP)
7911                 return 0;
7912
7913         if (arg == NULL) {
7914                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7915                             filter_op);
7916                 return -EINVAL;
7917         }
7918
7919         switch (filter_op) {
7920         case RTE_ETH_FILTER_ADD:
7921                 ret = ixgbe_dev_l2_tunnel_filter_add
7922                         (dev,
7923                          (struct rte_eth_l2_tunnel_conf *)arg,
7924                          FALSE);
7925                 break;
7926         case RTE_ETH_FILTER_DELETE:
7927                 ret = ixgbe_dev_l2_tunnel_filter_del
7928                         (dev,
7929                          (struct rte_eth_l2_tunnel_conf *)arg);
7930                 break;
7931         default:
7932                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7933                 ret = -EINVAL;
7934                 break;
7935         }
7936         return ret;
7937 }
7938
7939 static int
7940 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7941 {
7942         int ret = 0;
7943         uint32_t ctrl;
7944         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7945
7946         if (hw->mac.type != ixgbe_mac_X550 &&
7947             hw->mac.type != ixgbe_mac_X550EM_x &&
7948             hw->mac.type != ixgbe_mac_X550EM_a) {
7949                 return -ENOTSUP;
7950         }
7951
7952         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7953         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7954         if (en)
7955                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7956         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7957
7958         return ret;
7959 }
7960
7961 /* Enable l2 tunnel forwarding */
7962 static int
7963 ixgbe_dev_l2_tunnel_forwarding_enable
7964         (struct rte_eth_dev *dev,
7965          enum rte_eth_tunnel_type l2_tunnel_type)
7966 {
7967         struct ixgbe_l2_tn_info *l2_tn_info =
7968                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7969         int ret = 0;
7970
7971         switch (l2_tunnel_type) {
7972         case RTE_L2_TUNNEL_TYPE_E_TAG:
7973                 l2_tn_info->e_tag_fwd_en = TRUE;
7974                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7975                 break;
7976         default:
7977                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7978                 ret = -EINVAL;
7979                 break;
7980         }
7981
7982         return ret;
7983 }
7984
7985 /* Disable l2 tunnel forwarding */
7986 static int
7987 ixgbe_dev_l2_tunnel_forwarding_disable
7988         (struct rte_eth_dev *dev,
7989          enum rte_eth_tunnel_type l2_tunnel_type)
7990 {
7991         struct ixgbe_l2_tn_info *l2_tn_info =
7992                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7993         int ret = 0;
7994
7995         switch (l2_tunnel_type) {
7996         case RTE_L2_TUNNEL_TYPE_E_TAG:
7997                 l2_tn_info->e_tag_fwd_en = FALSE;
7998                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7999                 break;
8000         default:
8001                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8002                 ret = -EINVAL;
8003                 break;
8004         }
8005
8006         return ret;
8007 }
8008
8009 static int
8010 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8011                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8012                              bool en)
8013 {
8014         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8015         int ret = 0;
8016         uint32_t vmtir, vmvir;
8017         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8018
8019         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8020                 PMD_DRV_LOG(ERR,
8021                             "VF id %u should be less than %u",
8022                             l2_tunnel->vf_id,
8023                             pci_dev->max_vfs);
8024                 return -EINVAL;
8025         }
8026
8027         if (hw->mac.type != ixgbe_mac_X550 &&
8028             hw->mac.type != ixgbe_mac_X550EM_x &&
8029             hw->mac.type != ixgbe_mac_X550EM_a) {
8030                 return -ENOTSUP;
8031         }
8032
8033         if (en)
8034                 vmtir = l2_tunnel->tunnel_id;
8035         else
8036                 vmtir = 0;
8037
8038         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8039
8040         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8041         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8042         if (en)
8043                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8044         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8045
8046         return ret;
8047 }
8048
8049 /* Enable l2 tunnel tag insertion */
8050 static int
8051 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8052                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8053 {
8054         int ret = 0;
8055
8056         switch (l2_tunnel->l2_tunnel_type) {
8057         case RTE_L2_TUNNEL_TYPE_E_TAG:
8058                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8059                 break;
8060         default:
8061                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8062                 ret = -EINVAL;
8063                 break;
8064         }
8065
8066         return ret;
8067 }
8068
8069 /* Disable l2 tunnel tag insertion */
8070 static int
8071 ixgbe_dev_l2_tunnel_insertion_disable
8072         (struct rte_eth_dev *dev,
8073          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8074 {
8075         int ret = 0;
8076
8077         switch (l2_tunnel->l2_tunnel_type) {
8078         case RTE_L2_TUNNEL_TYPE_E_TAG:
8079                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8080                 break;
8081         default:
8082                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8083                 ret = -EINVAL;
8084                 break;
8085         }
8086
8087         return ret;
8088 }
8089
8090 static int
8091 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8092                              bool en)
8093 {
8094         int ret = 0;
8095         uint32_t qde;
8096         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8097
8098         if (hw->mac.type != ixgbe_mac_X550 &&
8099             hw->mac.type != ixgbe_mac_X550EM_x &&
8100             hw->mac.type != ixgbe_mac_X550EM_a) {
8101                 return -ENOTSUP;
8102         }
8103
8104         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8105         if (en)
8106                 qde |= IXGBE_QDE_STRIP_TAG;
8107         else
8108                 qde &= ~IXGBE_QDE_STRIP_TAG;
8109         qde &= ~IXGBE_QDE_READ;
8110         qde |= IXGBE_QDE_WRITE;
8111         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8112
8113         return ret;
8114 }
8115
8116 /* Enable l2 tunnel tag stripping */
8117 static int
8118 ixgbe_dev_l2_tunnel_stripping_enable
8119         (struct rte_eth_dev *dev,
8120          enum rte_eth_tunnel_type l2_tunnel_type)
8121 {
8122         int ret = 0;
8123
8124         switch (l2_tunnel_type) {
8125         case RTE_L2_TUNNEL_TYPE_E_TAG:
8126                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8127                 break;
8128         default:
8129                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8130                 ret = -EINVAL;
8131                 break;
8132         }
8133
8134         return ret;
8135 }
8136
8137 /* Disable l2 tunnel tag stripping */
8138 static int
8139 ixgbe_dev_l2_tunnel_stripping_disable
8140         (struct rte_eth_dev *dev,
8141          enum rte_eth_tunnel_type l2_tunnel_type)
8142 {
8143         int ret = 0;
8144
8145         switch (l2_tunnel_type) {
8146         case RTE_L2_TUNNEL_TYPE_E_TAG:
8147                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8148                 break;
8149         default:
8150                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8151                 ret = -EINVAL;
8152                 break;
8153         }
8154
8155         return ret;
8156 }
8157
8158 /* Enable/disable l2 tunnel offload functions */
8159 static int
8160 ixgbe_dev_l2_tunnel_offload_set
8161         (struct rte_eth_dev *dev,
8162          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8163          uint32_t mask,
8164          uint8_t en)
8165 {
8166         int ret = 0;
8167
8168         if (l2_tunnel == NULL)
8169                 return -EINVAL;
8170
8171         ret = -EINVAL;
8172         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8173                 if (en)
8174                         ret = ixgbe_dev_l2_tunnel_enable(
8175                                 dev,
8176                                 l2_tunnel->l2_tunnel_type);
8177                 else
8178                         ret = ixgbe_dev_l2_tunnel_disable(
8179                                 dev,
8180                                 l2_tunnel->l2_tunnel_type);
8181         }
8182
8183         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8184                 if (en)
8185                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8186                                 dev,
8187                                 l2_tunnel);
8188                 else
8189                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8190                                 dev,
8191                                 l2_tunnel);
8192         }
8193
8194         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8195                 if (en)
8196                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8197                                 dev,
8198                                 l2_tunnel->l2_tunnel_type);
8199                 else
8200                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8201                                 dev,
8202                                 l2_tunnel->l2_tunnel_type);
8203         }
8204
8205         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8206                 if (en)
8207                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8208                                 dev,
8209                                 l2_tunnel->l2_tunnel_type);
8210                 else
8211                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8212                                 dev,
8213                                 l2_tunnel->l2_tunnel_type);
8214         }
8215
8216         return ret;
8217 }
8218
8219 static int
8220 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8221                         uint16_t port)
8222 {
8223         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8224         IXGBE_WRITE_FLUSH(hw);
8225
8226         return 0;
8227 }
8228
8229 /* There's only one register for VxLAN UDP port.
8230  * So, we cannot add several ports. Will update it.
8231  */
8232 static int
8233 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8234                      uint16_t port)
8235 {
8236         if (port == 0) {
8237                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8238                 return -EINVAL;
8239         }
8240
8241         return ixgbe_update_vxlan_port(hw, port);
8242 }
8243
8244 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8245  * UDP port, it must have a value.
8246  * So, will reset it to the original value 0.
8247  */
8248 static int
8249 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8250                      uint16_t port)
8251 {
8252         uint16_t cur_port;
8253
8254         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8255
8256         if (cur_port != port) {
8257                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8258                 return -EINVAL;
8259         }
8260
8261         return ixgbe_update_vxlan_port(hw, 0);
8262 }
8263
8264 /* Add UDP tunneling port */
8265 static int
8266 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8267                               struct rte_eth_udp_tunnel *udp_tunnel)
8268 {
8269         int ret = 0;
8270         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8271
8272         if (hw->mac.type != ixgbe_mac_X550 &&
8273             hw->mac.type != ixgbe_mac_X550EM_x &&
8274             hw->mac.type != ixgbe_mac_X550EM_a) {
8275                 return -ENOTSUP;
8276         }
8277
8278         if (udp_tunnel == NULL)
8279                 return -EINVAL;
8280
8281         switch (udp_tunnel->prot_type) {
8282         case RTE_TUNNEL_TYPE_VXLAN:
8283                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8284                 break;
8285
8286         case RTE_TUNNEL_TYPE_GENEVE:
8287         case RTE_TUNNEL_TYPE_TEREDO:
8288                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8289                 ret = -EINVAL;
8290                 break;
8291
8292         default:
8293                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8294                 ret = -EINVAL;
8295                 break;
8296         }
8297
8298         return ret;
8299 }
8300
8301 /* Remove UDP tunneling port */
8302 static int
8303 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8304                               struct rte_eth_udp_tunnel *udp_tunnel)
8305 {
8306         int ret = 0;
8307         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8308
8309         if (hw->mac.type != ixgbe_mac_X550 &&
8310             hw->mac.type != ixgbe_mac_X550EM_x &&
8311             hw->mac.type != ixgbe_mac_X550EM_a) {
8312                 return -ENOTSUP;
8313         }
8314
8315         if (udp_tunnel == NULL)
8316                 return -EINVAL;
8317
8318         switch (udp_tunnel->prot_type) {
8319         case RTE_TUNNEL_TYPE_VXLAN:
8320                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8321                 break;
8322         case RTE_TUNNEL_TYPE_GENEVE:
8323         case RTE_TUNNEL_TYPE_TEREDO:
8324                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8325                 ret = -EINVAL;
8326                 break;
8327         default:
8328                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8329                 ret = -EINVAL;
8330                 break;
8331         }
8332
8333         return ret;
8334 }
8335
8336 static int
8337 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8338 {
8339         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8340         int ret;
8341
8342         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8343         case IXGBE_SUCCESS:
8344                 ret = 0;
8345                 break;
8346         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8347                 ret = -ENOTSUP;
8348                 break;
8349         default:
8350                 ret = -EAGAIN;
8351                 break;
8352         }
8353
8354         return ret;
8355 }
8356
8357 static int
8358 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8359 {
8360         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8361         int ret;
8362
8363         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8364         case IXGBE_SUCCESS:
8365                 ret = 0;
8366                 break;
8367         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8368                 ret = -ENOTSUP;
8369                 break;
8370         default:
8371                 ret = -EAGAIN;
8372                 break;
8373         }
8374
8375         return ret;
8376 }
8377
8378 static int
8379 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8380 {
8381         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8382         int ret;
8383         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8384
8385         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8386         case IXGBE_SUCCESS:
8387                 ret = 0;
8388                 break;
8389         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8390                 ret = -ENOTSUP;
8391                 break;
8392         default:
8393                 ret = -EAGAIN;
8394                 break;
8395         }
8396
8397         return ret;
8398 }
8399
8400 static int
8401 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8402 {
8403         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8404         int ret;
8405
8406         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8407         case IXGBE_SUCCESS:
8408                 ret = 0;
8409                 break;
8410         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8411                 ret = -ENOTSUP;
8412                 break;
8413         default:
8414                 ret = -EAGAIN;
8415                 break;
8416         }
8417
8418         return ret;
8419 }
8420
8421 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8422 {
8423         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8424         u32 in_msg = 0;
8425
8426         /* peek the message first */
8427         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8428
8429         /* PF reset VF event */
8430         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8431                 /* dummy mbx read to ack pf */
8432                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8433                         return;
8434                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8435                                              NULL);
8436         }
8437 }
8438
8439 static int
8440 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8441 {
8442         uint32_t eicr;
8443         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8444         struct ixgbe_interrupt *intr =
8445                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8446         ixgbevf_intr_disable(dev);
8447
8448         /* read-on-clear nic registers here */
8449         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8450         intr->flags = 0;
8451
8452         /* only one misc vector supported - mailbox */
8453         eicr &= IXGBE_VTEICR_MASK;
8454         if (eicr == IXGBE_MISC_VEC_ID)
8455                 intr->flags |= IXGBE_FLAG_MAILBOX;
8456
8457         return 0;
8458 }
8459
8460 static int
8461 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8462 {
8463         struct ixgbe_interrupt *intr =
8464                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8465
8466         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8467                 ixgbevf_mbx_process(dev);
8468                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8469         }
8470
8471         ixgbevf_intr_enable(dev);
8472
8473         return 0;
8474 }
8475
8476 static void
8477 ixgbevf_dev_interrupt_handler(void *param)
8478 {
8479         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8480
8481         ixgbevf_dev_interrupt_get_status(dev);
8482         ixgbevf_dev_interrupt_action(dev);
8483 }
8484
8485 /**
8486  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8487  *  @hw: pointer to hardware structure
8488  *
8489  *  Stops the transmit data path and waits for the HW to internally empty
8490  *  the Tx security block
8491  **/
8492 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8493 {
8494 #define IXGBE_MAX_SECTX_POLL 40
8495
8496         int i;
8497         int sectxreg;
8498
8499         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8500         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8501         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8502         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8503                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8504                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8505                         break;
8506                 /* Use interrupt-safe sleep just in case */
8507                 usec_delay(1000);
8508         }
8509
8510         /* For informational purposes only */
8511         if (i >= IXGBE_MAX_SECTX_POLL)
8512                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8513                          "path fully disabled.  Continuing with init.");
8514
8515         return IXGBE_SUCCESS;
8516 }
8517
8518 /**
8519  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8520  *  @hw: pointer to hardware structure
8521  *
8522  *  Enables the transmit data path.
8523  **/
8524 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8525 {
8526         uint32_t sectxreg;
8527
8528         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8529         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8530         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8531         IXGBE_WRITE_FLUSH(hw);
8532
8533         return IXGBE_SUCCESS;
8534 }
8535
8536 /* restore n-tuple filter */
8537 static inline void
8538 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8539 {
8540         struct ixgbe_filter_info *filter_info =
8541                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8542         struct ixgbe_5tuple_filter *node;
8543
8544         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8545                 ixgbe_inject_5tuple_filter(dev, node);
8546         }
8547 }
8548
8549 /* restore ethernet type filter */
8550 static inline void
8551 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8552 {
8553         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8554         struct ixgbe_filter_info *filter_info =
8555                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8556         int i;
8557
8558         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8559                 if (filter_info->ethertype_mask & (1 << i)) {
8560                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8561                                         filter_info->ethertype_filters[i].etqf);
8562                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8563                                         filter_info->ethertype_filters[i].etqs);
8564                         IXGBE_WRITE_FLUSH(hw);
8565                 }
8566         }
8567 }
8568
8569 /* restore SYN filter */
8570 static inline void
8571 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8572 {
8573         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8574         struct ixgbe_filter_info *filter_info =
8575                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8576         uint32_t synqf;
8577
8578         synqf = filter_info->syn_info;
8579
8580         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8581                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8582                 IXGBE_WRITE_FLUSH(hw);
8583         }
8584 }
8585
8586 /* restore L2 tunnel filter */
8587 static inline void
8588 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8589 {
8590         struct ixgbe_l2_tn_info *l2_tn_info =
8591                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8592         struct ixgbe_l2_tn_filter *node;
8593         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8594
8595         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8596                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8597                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8598                 l2_tn_conf.pool           = node->pool;
8599                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8600         }
8601 }
8602
8603 /* restore rss filter */
8604 static inline void
8605 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8606 {
8607         struct ixgbe_filter_info *filter_info =
8608                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8609
8610         if (filter_info->rss_info.conf.queue_num)
8611                 ixgbe_config_rss_filter(dev,
8612                         &filter_info->rss_info, TRUE);
8613 }
8614
8615 static int
8616 ixgbe_filter_restore(struct rte_eth_dev *dev)
8617 {
8618         ixgbe_ntuple_filter_restore(dev);
8619         ixgbe_ethertype_filter_restore(dev);
8620         ixgbe_syn_filter_restore(dev);
8621         ixgbe_fdir_filter_restore(dev);
8622         ixgbe_l2_tn_filter_restore(dev);
8623         ixgbe_rss_filter_restore(dev);
8624
8625         return 0;
8626 }
8627
8628 static void
8629 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8630 {
8631         struct ixgbe_l2_tn_info *l2_tn_info =
8632                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8633         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8634
8635         if (l2_tn_info->e_tag_en)
8636                 (void)ixgbe_e_tag_enable(hw);
8637
8638         if (l2_tn_info->e_tag_fwd_en)
8639                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8640
8641         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8642 }
8643
8644 /* remove all the n-tuple filters */
8645 void
8646 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8647 {
8648         struct ixgbe_filter_info *filter_info =
8649                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8650         struct ixgbe_5tuple_filter *p_5tuple;
8651
8652         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8653                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8654 }
8655
8656 /* remove all the ether type filters */
8657 void
8658 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8659 {
8660         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8661         struct ixgbe_filter_info *filter_info =
8662                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8663         int i;
8664
8665         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8666                 if (filter_info->ethertype_mask & (1 << i) &&
8667                     !filter_info->ethertype_filters[i].conf) {
8668                         (void)ixgbe_ethertype_filter_remove(filter_info,
8669                                                             (uint8_t)i);
8670                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8671                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8672                         IXGBE_WRITE_FLUSH(hw);
8673                 }
8674         }
8675 }
8676
8677 /* remove the SYN filter */
8678 void
8679 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8680 {
8681         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8682         struct ixgbe_filter_info *filter_info =
8683                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8684
8685         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8686                 filter_info->syn_info = 0;
8687
8688                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8689                 IXGBE_WRITE_FLUSH(hw);
8690         }
8691 }
8692
8693 /* remove all the L2 tunnel filters */
8694 int
8695 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8696 {
8697         struct ixgbe_l2_tn_info *l2_tn_info =
8698                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8699         struct ixgbe_l2_tn_filter *l2_tn_filter;
8700         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8701         int ret = 0;
8702
8703         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8704                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8705                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8706                 l2_tn_conf.pool           = l2_tn_filter->pool;
8707                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8708                 if (ret < 0)
8709                         return ret;
8710         }
8711
8712         return 0;
8713 }
8714
8715 void
8716 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8717                                 struct ixgbe_macsec_setting *macsec_setting)
8718 {
8719         struct ixgbe_macsec_setting *macsec =
8720                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8721
8722         macsec->offload_en = macsec_setting->offload_en;
8723         macsec->encrypt_en = macsec_setting->encrypt_en;
8724         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8725 }
8726
8727 void
8728 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8729 {
8730         struct ixgbe_macsec_setting *macsec =
8731                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8732
8733         macsec->offload_en = 0;
8734         macsec->encrypt_en = 0;
8735         macsec->replayprotect_en = 0;
8736 }
8737
8738 void
8739 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8740                                 struct ixgbe_macsec_setting *macsec_setting)
8741 {
8742         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8743         uint32_t ctrl;
8744         uint8_t en = macsec_setting->encrypt_en;
8745         uint8_t rp = macsec_setting->replayprotect_en;
8746
8747         /**
8748          * Workaround:
8749          * As no ixgbe_disable_sec_rx_path equivalent is
8750          * implemented for tx in the base code, and we are
8751          * not allowed to modify the base code in DPDK, so
8752          * just call the hand-written one directly for now.
8753          * The hardware support has been checked by
8754          * ixgbe_disable_sec_rx_path().
8755          */
8756         ixgbe_disable_sec_tx_path_generic(hw);
8757
8758         /* Enable Ethernet CRC (required by MACsec offload) */
8759         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8760         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8761         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8762
8763         /* Enable the TX and RX crypto engines */
8764         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8765         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8766         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8767
8768         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8769         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8770         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8771
8772         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8773         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8774         ctrl |= 0x3;
8775         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8776
8777         /* Enable SA lookup */
8778         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8779         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8780         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8781                      IXGBE_LSECTXCTRL_AUTH;
8782         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8783         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8784         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8785         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8786
8787         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8788         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8789         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8790         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8791         if (rp)
8792                 ctrl |= IXGBE_LSECRXCTRL_RP;
8793         else
8794                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8795         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8796
8797         /* Start the data paths */
8798         ixgbe_enable_sec_rx_path(hw);
8799         /**
8800          * Workaround:
8801          * As no ixgbe_enable_sec_rx_path equivalent is
8802          * implemented for tx in the base code, and we are
8803          * not allowed to modify the base code in DPDK, so
8804          * just call the hand-written one directly for now.
8805          */
8806         ixgbe_enable_sec_tx_path_generic(hw);
8807 }
8808
8809 void
8810 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8811 {
8812         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8813         uint32_t ctrl;
8814
8815         /**
8816          * Workaround:
8817          * As no ixgbe_disable_sec_rx_path equivalent is
8818          * implemented for tx in the base code, and we are
8819          * not allowed to modify the base code in DPDK, so
8820          * just call the hand-written one directly for now.
8821          * The hardware support has been checked by
8822          * ixgbe_disable_sec_rx_path().
8823          */
8824         ixgbe_disable_sec_tx_path_generic(hw);
8825
8826         /* Disable the TX and RX crypto engines */
8827         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8828         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8829         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8830
8831         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8832         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8833         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8834
8835         /* Disable SA lookup */
8836         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8837         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8838         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8839         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8840
8841         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8842         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8843         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8844         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8845
8846         /* Start the data paths */
8847         ixgbe_enable_sec_rx_path(hw);
8848         /**
8849          * Workaround:
8850          * As no ixgbe_enable_sec_rx_path equivalent is
8851          * implemented for tx in the base code, and we are
8852          * not allowed to modify the base code in DPDK, so
8853          * just call the hand-written one directly for now.
8854          */
8855         ixgbe_enable_sec_tx_path_generic(hw);
8856 }
8857
8858 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8859 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8860 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8861 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8862 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8863 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8864 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8865                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8866
8867 RTE_LOG_REGISTER(ixgbe_logtype_init, pmd.net.ixgbe.init, NOTICE);
8868 RTE_LOG_REGISTER(ixgbe_logtype_driver, pmd.net.ixgbe.driver, NOTICE);
8869
8870 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
8871 RTE_LOG_REGISTER(ixgbe_logtype_rx, pmd.net.ixgbe.rx, DEBUG);
8872 #endif
8873 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
8874 RTE_LOG_REGISTER(ixgbe_logtype_tx, pmd.net.ixgbe.tx, DEBUG);
8875 #endif
8876 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
8877 RTE_LOG_REGISTER(ixgbe_logtype_tx_free, pmd.net.ixgbe.tx_free, DEBUG);
8878 #endif