4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
64 #include "ixgbe_logs.h"
65 #include "base/ixgbe_api.h"
66 #include "base/ixgbe_vf.h"
67 #include "base/ixgbe_common.h"
68 #include "ixgbe_ethdev.h"
69 #include "ixgbe_bypass.h"
70 #include "ixgbe_rxtx.h"
71 #include "base/ixgbe_type.h"
72 #include "base/ixgbe_phy.h"
73 #include "ixgbe_regs.h"
76 * High threshold controlling when to start sending XOFF frames. Must be at
77 * least 8 bytes less than receive packet buffer size. This value is in units
80 #define IXGBE_FC_HI 0x80
83 * Low threshold controlling when to start sending XON frames. This value is
84 * in units of 1024 bytes.
86 #define IXGBE_FC_LO 0x40
88 /* Default minimum inter-interrupt interval for EITR configuration */
89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
91 /* Timer value included in XOFF frames. */
92 #define IXGBE_FC_PAUSE 0x680
94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
95 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
96 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
98 #define IXGBE_MMW_SIZE_DEFAULT 0x4
99 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
100 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
103 * Default values for RX/TX configuration
105 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
106 #define IXGBE_DEFAULT_RX_PTHRESH 8
107 #define IXGBE_DEFAULT_RX_HTHRESH 8
108 #define IXGBE_DEFAULT_RX_WTHRESH 0
110 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
111 #define IXGBE_DEFAULT_TX_PTHRESH 32
112 #define IXGBE_DEFAULT_TX_HTHRESH 0
113 #define IXGBE_DEFAULT_TX_WTHRESH 0
114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
116 /* Bit shift and mask */
117 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
118 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
119 #define IXGBE_8_BIT_WIDTH CHAR_BIT
120 #define IXGBE_8_BIT_MASK UINT8_MAX
122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
126 #define IXGBE_HKEY_MAX_INDEX 10
128 /* Additional timesync values. */
129 #define NSEC_PER_SEC 1000000000L
130 #define IXGBE_INCVAL_10GB 0x66666666
131 #define IXGBE_INCVAL_1GB 0x40000000
132 #define IXGBE_INCVAL_100 0x50000000
133 #define IXGBE_INCVAL_SHIFT_10GB 28
134 #define IXGBE_INCVAL_SHIFT_1GB 24
135 #define IXGBE_INCVAL_SHIFT_100 21
136 #define IXGBE_INCVAL_SHIFT_82599 7
137 #define IXGBE_INCPER_SHIFT_82599 24
139 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
141 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
143 #define DEFAULT_ETAG_ETYPE 0x893f
144 #define IXGBE_ETAG_ETYPE 0x00005084
145 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
146 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
147 #define IXGBE_RAH_ADTYPE 0x40000000
148 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
149 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
152 #define IXGBE_QDE_STRIP_TAG 0x00000004
153 #define IXGBE_VTEICR_MASK 0x07
155 enum ixgbevf_xcast_modes {
156 IXGBEVF_XCAST_MODE_NONE = 0,
157 IXGBEVF_XCAST_MODE_MULTI,
158 IXGBEVF_XCAST_MODE_ALLMULTI,
161 #define IXGBE_EXVET_VET_EXT_SHIFT 16
162 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
164 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
165 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
166 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
167 static int ixgbe_dev_start(struct rte_eth_dev *dev);
168 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
169 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
170 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
171 static void ixgbe_dev_close(struct rte_eth_dev *dev);
172 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
173 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
174 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
175 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
176 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
177 int wait_to_complete);
178 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
179 struct rte_eth_stats *stats);
180 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
181 struct rte_eth_xstat *xstats, unsigned n);
182 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
183 struct rte_eth_xstat *xstats, unsigned n);
184 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
185 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
186 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
187 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
188 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
189 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
190 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
194 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
195 struct rte_eth_dev_info *dev_info);
196 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
197 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
198 struct rte_eth_dev_info *dev_info);
199 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
201 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
202 uint16_t vlan_id, int on);
203 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
204 enum rte_vlan_type vlan_type,
206 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
207 uint16_t queue, bool on);
208 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
210 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
211 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
212 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
213 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
214 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
216 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
217 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
218 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
219 struct rte_eth_fc_conf *fc_conf);
220 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
221 struct rte_eth_fc_conf *fc_conf);
222 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
223 struct rte_eth_pfc_conf *pfc_conf);
224 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
225 struct rte_eth_rss_reta_entry64 *reta_conf,
227 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
228 struct rte_eth_rss_reta_entry64 *reta_conf,
230 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
231 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
232 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
233 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
234 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
235 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
237 static void ixgbe_dev_interrupt_delayed_handler(void *param);
238 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
239 uint32_t index, uint32_t pool);
240 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
241 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
242 struct ether_addr *mac_addr);
243 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
245 /* For Virtual Function support */
246 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
247 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
248 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
249 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
250 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
251 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
252 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
253 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
254 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
255 struct rte_eth_stats *stats);
256 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
257 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
258 uint16_t vlan_id, int on);
259 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
260 uint16_t queue, int on);
261 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
262 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
263 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
265 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
267 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
268 uint8_t queue, uint8_t msix_vector);
269 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
270 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
271 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
273 /* For Eth VMDQ APIs support */
274 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
275 ether_addr * mac_addr, uint8_t on);
276 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
277 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
278 uint16_t rx_mask, uint8_t on);
279 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
280 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
281 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
282 uint64_t pool_mask, uint8_t vlan_on);
283 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
284 struct rte_eth_mirror_conf *mirror_conf,
285 uint8_t rule_id, uint8_t on);
286 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
288 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
290 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
292 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
293 uint8_t queue, uint8_t msix_vector);
294 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
296 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
297 uint16_t queue_idx, uint16_t tx_rate);
298 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
299 uint16_t tx_rate, uint64_t q_msk);
301 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
302 struct ether_addr *mac_addr,
303 uint32_t index, uint32_t pool);
304 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
305 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
306 struct ether_addr *mac_addr);
307 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
308 struct rte_eth_syn_filter *filter,
310 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
311 struct rte_eth_syn_filter *filter);
312 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
313 enum rte_filter_op filter_op,
315 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
316 struct ixgbe_5tuple_filter *filter);
317 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
318 struct ixgbe_5tuple_filter *filter);
319 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
320 struct rte_eth_ntuple_filter *filter,
322 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
323 enum rte_filter_op filter_op,
325 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
326 struct rte_eth_ntuple_filter *filter);
327 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
328 struct rte_eth_ethertype_filter *filter,
330 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
331 enum rte_filter_op filter_op,
333 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
334 struct rte_eth_ethertype_filter *filter);
335 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
336 enum rte_filter_type filter_type,
337 enum rte_filter_op filter_op,
339 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
341 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
342 struct ether_addr *mc_addr_set,
343 uint32_t nb_mc_addr);
344 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
345 struct rte_eth_dcb_info *dcb_info);
347 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
348 static int ixgbe_get_regs(struct rte_eth_dev *dev,
349 struct rte_dev_reg_info *regs);
350 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
351 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
352 struct rte_dev_eeprom_info *eeprom);
353 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
354 struct rte_dev_eeprom_info *eeprom);
356 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
357 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
358 struct rte_dev_reg_info *regs);
360 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
361 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
362 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
363 struct timespec *timestamp,
365 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
366 struct timespec *timestamp);
367 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
368 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
369 struct timespec *timestamp);
370 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
371 const struct timespec *timestamp);
372 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
375 static int ixgbe_dev_l2_tunnel_eth_type_conf
376 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
377 static int ixgbe_dev_l2_tunnel_offload_set
378 (struct rte_eth_dev *dev,
379 struct rte_eth_l2_tunnel_conf *l2_tunnel,
382 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
383 enum rte_filter_op filter_op,
386 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
387 struct rte_eth_udp_tunnel *udp_tunnel);
388 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
389 struct rte_eth_udp_tunnel *udp_tunnel);
392 * Define VF Stats MACRO for Non "cleared on read" register
394 #define UPDATE_VF_STAT(reg, last, cur) \
396 uint32_t latest = IXGBE_READ_REG(hw, reg); \
397 cur += (latest - last) & UINT_MAX; \
401 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
403 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
404 u64 new_msb = IXGBE_READ_REG(hw, msb); \
405 u64 latest = ((new_msb << 32) | new_lsb); \
406 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
410 #define IXGBE_SET_HWSTRIP(h, q) do {\
411 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
412 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
413 (h)->bitmap[idx] |= 1 << bit;\
416 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
417 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
418 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
419 (h)->bitmap[idx] &= ~(1 << bit);\
422 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
423 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
424 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
425 (r) = (h)->bitmap[idx] >> bit & 1;\
429 * The set of PCI devices this driver supports
431 static const struct rte_pci_id pci_id_ixgbe_map[] = {
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
483 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
484 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
485 #ifdef RTE_NIC_BYPASS
486 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
488 { .vendor_id = 0, /* sentinel */ },
492 * The set of PCI devices this driver supports (for 82599 VF)
494 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
495 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
500 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
501 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
502 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
503 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
504 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
505 { .vendor_id = 0, /* sentinel */ },
508 static const struct rte_eth_desc_lim rx_desc_lim = {
509 .nb_max = IXGBE_MAX_RING_DESC,
510 .nb_min = IXGBE_MIN_RING_DESC,
511 .nb_align = IXGBE_RXD_ALIGN,
514 static const struct rte_eth_desc_lim tx_desc_lim = {
515 .nb_max = IXGBE_MAX_RING_DESC,
516 .nb_min = IXGBE_MIN_RING_DESC,
517 .nb_align = IXGBE_TXD_ALIGN,
520 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
521 .dev_configure = ixgbe_dev_configure,
522 .dev_start = ixgbe_dev_start,
523 .dev_stop = ixgbe_dev_stop,
524 .dev_set_link_up = ixgbe_dev_set_link_up,
525 .dev_set_link_down = ixgbe_dev_set_link_down,
526 .dev_close = ixgbe_dev_close,
527 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
528 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
529 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
530 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
531 .link_update = ixgbe_dev_link_update,
532 .stats_get = ixgbe_dev_stats_get,
533 .xstats_get = ixgbe_dev_xstats_get,
534 .stats_reset = ixgbe_dev_stats_reset,
535 .xstats_reset = ixgbe_dev_xstats_reset,
536 .xstats_get_names = ixgbe_dev_xstats_get_names,
537 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
538 .dev_infos_get = ixgbe_dev_info_get,
539 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
540 .mtu_set = ixgbe_dev_mtu_set,
541 .vlan_filter_set = ixgbe_vlan_filter_set,
542 .vlan_tpid_set = ixgbe_vlan_tpid_set,
543 .vlan_offload_set = ixgbe_vlan_offload_set,
544 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
545 .rx_queue_start = ixgbe_dev_rx_queue_start,
546 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
547 .tx_queue_start = ixgbe_dev_tx_queue_start,
548 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
549 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
550 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
551 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
552 .rx_queue_release = ixgbe_dev_rx_queue_release,
553 .rx_queue_count = ixgbe_dev_rx_queue_count,
554 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
555 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
556 .tx_queue_release = ixgbe_dev_tx_queue_release,
557 .dev_led_on = ixgbe_dev_led_on,
558 .dev_led_off = ixgbe_dev_led_off,
559 .flow_ctrl_get = ixgbe_flow_ctrl_get,
560 .flow_ctrl_set = ixgbe_flow_ctrl_set,
561 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
562 .mac_addr_add = ixgbe_add_rar,
563 .mac_addr_remove = ixgbe_remove_rar,
564 .mac_addr_set = ixgbe_set_default_mac_addr,
565 .uc_hash_table_set = ixgbe_uc_hash_table_set,
566 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
567 .mirror_rule_set = ixgbe_mirror_rule_set,
568 .mirror_rule_reset = ixgbe_mirror_rule_reset,
569 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
570 .set_vf_rx = ixgbe_set_pool_rx,
571 .set_vf_tx = ixgbe_set_pool_tx,
572 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
573 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
574 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
575 .reta_update = ixgbe_dev_rss_reta_update,
576 .reta_query = ixgbe_dev_rss_reta_query,
577 #ifdef RTE_NIC_BYPASS
578 .bypass_init = ixgbe_bypass_init,
579 .bypass_state_set = ixgbe_bypass_state_store,
580 .bypass_state_show = ixgbe_bypass_state_show,
581 .bypass_event_set = ixgbe_bypass_event_store,
582 .bypass_event_show = ixgbe_bypass_event_show,
583 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
584 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
585 .bypass_ver_show = ixgbe_bypass_ver_show,
586 .bypass_wd_reset = ixgbe_bypass_wd_reset,
587 #endif /* RTE_NIC_BYPASS */
588 .rss_hash_update = ixgbe_dev_rss_hash_update,
589 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
590 .filter_ctrl = ixgbe_dev_filter_ctrl,
591 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
592 .rxq_info_get = ixgbe_rxq_info_get,
593 .txq_info_get = ixgbe_txq_info_get,
594 .timesync_enable = ixgbe_timesync_enable,
595 .timesync_disable = ixgbe_timesync_disable,
596 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
597 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
598 .get_reg = ixgbe_get_regs,
599 .get_eeprom_length = ixgbe_get_eeprom_length,
600 .get_eeprom = ixgbe_get_eeprom,
601 .set_eeprom = ixgbe_set_eeprom,
602 .get_dcb_info = ixgbe_dev_get_dcb_info,
603 .timesync_adjust_time = ixgbe_timesync_adjust_time,
604 .timesync_read_time = ixgbe_timesync_read_time,
605 .timesync_write_time = ixgbe_timesync_write_time,
606 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
607 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
608 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
609 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
613 * dev_ops for virtual function, bare necessities for basic vf
614 * operation have been implemented
616 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
617 .dev_configure = ixgbevf_dev_configure,
618 .dev_start = ixgbevf_dev_start,
619 .dev_stop = ixgbevf_dev_stop,
620 .link_update = ixgbe_dev_link_update,
621 .stats_get = ixgbevf_dev_stats_get,
622 .xstats_get = ixgbevf_dev_xstats_get,
623 .stats_reset = ixgbevf_dev_stats_reset,
624 .xstats_reset = ixgbevf_dev_stats_reset,
625 .xstats_get_names = ixgbevf_dev_xstats_get_names,
626 .dev_close = ixgbevf_dev_close,
627 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
628 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
629 .dev_infos_get = ixgbevf_dev_info_get,
630 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
631 .mtu_set = ixgbevf_dev_set_mtu,
632 .vlan_filter_set = ixgbevf_vlan_filter_set,
633 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
634 .vlan_offload_set = ixgbevf_vlan_offload_set,
635 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
636 .rx_queue_release = ixgbe_dev_rx_queue_release,
637 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
638 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
639 .tx_queue_release = ixgbe_dev_tx_queue_release,
640 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
641 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
642 .mac_addr_add = ixgbevf_add_mac_addr,
643 .mac_addr_remove = ixgbevf_remove_mac_addr,
644 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
645 .rxq_info_get = ixgbe_rxq_info_get,
646 .txq_info_get = ixgbe_txq_info_get,
647 .mac_addr_set = ixgbevf_set_default_mac_addr,
648 .get_reg = ixgbevf_get_regs,
649 .reta_update = ixgbe_dev_rss_reta_update,
650 .reta_query = ixgbe_dev_rss_reta_query,
651 .rss_hash_update = ixgbe_dev_rss_hash_update,
652 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
655 /* store statistics names and its offset in stats structure */
656 struct rte_ixgbe_xstats_name_off {
657 char name[RTE_ETH_XSTATS_NAME_SIZE];
661 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
662 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
663 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
664 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
665 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
666 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
667 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
668 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
669 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
670 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
671 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
672 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
673 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
674 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
675 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
676 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
678 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
680 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
681 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
682 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
683 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
684 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
685 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
686 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
687 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
688 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
689 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
690 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
691 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
692 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
693 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
694 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
695 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
696 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
698 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
700 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
701 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
702 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
703 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
705 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
707 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
709 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
711 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
713 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
715 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
718 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
719 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
720 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
722 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
723 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
724 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
725 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
726 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
728 {"rx_fcoe_no_direct_data_placement_ext_buff",
729 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
731 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
733 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
735 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
737 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
739 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
742 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
743 sizeof(rte_ixgbe_stats_strings[0]))
745 /* Per-queue statistics */
746 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
747 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
748 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
749 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
750 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
753 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
754 sizeof(rte_ixgbe_rxq_strings[0]))
755 #define IXGBE_NB_RXQ_PRIO_VALUES 8
757 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
758 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
759 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
760 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
764 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
765 sizeof(rte_ixgbe_txq_strings[0]))
766 #define IXGBE_NB_TXQ_PRIO_VALUES 8
768 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
769 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
772 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
773 sizeof(rte_ixgbevf_stats_strings[0]))
776 * Atomically reads the link status information from global
777 * structure rte_eth_dev.
780 * - Pointer to the structure rte_eth_dev to read from.
781 * - Pointer to the buffer to be saved with the link status.
784 * - On success, zero.
785 * - On failure, negative value.
788 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
789 struct rte_eth_link *link)
791 struct rte_eth_link *dst = link;
792 struct rte_eth_link *src = &(dev->data->dev_link);
794 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
795 *(uint64_t *)src) == 0)
802 * Atomically writes the link status information into global
803 * structure rte_eth_dev.
806 * - Pointer to the structure rte_eth_dev to read from.
807 * - Pointer to the buffer to be saved with the link status.
810 * - On success, zero.
811 * - On failure, negative value.
814 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
815 struct rte_eth_link *link)
817 struct rte_eth_link *dst = &(dev->data->dev_link);
818 struct rte_eth_link *src = link;
820 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
821 *(uint64_t *)src) == 0)
828 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
831 ixgbe_is_sfp(struct ixgbe_hw *hw)
833 switch (hw->phy.type) {
834 case ixgbe_phy_sfp_avago:
835 case ixgbe_phy_sfp_ftl:
836 case ixgbe_phy_sfp_intel:
837 case ixgbe_phy_sfp_unknown:
838 case ixgbe_phy_sfp_passive_tyco:
839 case ixgbe_phy_sfp_passive_unknown:
846 static inline int32_t
847 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
852 status = ixgbe_reset_hw(hw);
854 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
855 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
856 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
857 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
858 IXGBE_WRITE_FLUSH(hw);
864 ixgbe_enable_intr(struct rte_eth_dev *dev)
866 struct ixgbe_interrupt *intr =
867 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
868 struct ixgbe_hw *hw =
869 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
871 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
872 IXGBE_WRITE_FLUSH(hw);
876 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
879 ixgbe_disable_intr(struct ixgbe_hw *hw)
881 PMD_INIT_FUNC_TRACE();
883 if (hw->mac.type == ixgbe_mac_82598EB) {
884 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
886 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
887 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
888 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
890 IXGBE_WRITE_FLUSH(hw);
894 * This function resets queue statistics mapping registers.
895 * From Niantic datasheet, Initialization of Statistics section:
896 * "...if software requires the queue counters, the RQSMR and TQSM registers
897 * must be re-programmed following a device reset.
900 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
904 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
905 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
906 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
912 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
917 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
918 #define NB_QMAP_FIELDS_PER_QSM_REG 4
919 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
921 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
922 struct ixgbe_stat_mapping_registers *stat_mappings =
923 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
924 uint32_t qsmr_mask = 0;
925 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
929 if ((hw->mac.type != ixgbe_mac_82599EB) &&
930 (hw->mac.type != ixgbe_mac_X540) &&
931 (hw->mac.type != ixgbe_mac_X550) &&
932 (hw->mac.type != ixgbe_mac_X550EM_x) &&
933 (hw->mac.type != ixgbe_mac_X550EM_a))
936 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
937 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
940 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
941 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
942 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
945 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
947 /* Now clear any previous stat_idx set */
948 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
950 stat_mappings->tqsm[n] &= ~clearing_mask;
952 stat_mappings->rqsmr[n] &= ~clearing_mask;
954 q_map = (uint32_t)stat_idx;
955 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
956 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
958 stat_mappings->tqsm[n] |= qsmr_mask;
960 stat_mappings->rqsmr[n] |= qsmr_mask;
962 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
963 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
965 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
966 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
968 /* Now write the mapping in the appropriate register */
970 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
971 stat_mappings->rqsmr[n], n);
972 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
974 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
975 stat_mappings->tqsm[n], n);
976 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
982 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
984 struct ixgbe_stat_mapping_registers *stat_mappings =
985 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
986 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
989 /* write whatever was in stat mapping table to the NIC */
990 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
992 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
995 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1000 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1003 struct ixgbe_dcb_tc_config *tc;
1004 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1006 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1007 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1008 for (i = 0; i < dcb_max_tc; i++) {
1009 tc = &dcb_config->tc_config[i];
1010 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1011 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1012 (uint8_t)(100/dcb_max_tc + (i & 1));
1013 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1014 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1015 (uint8_t)(100/dcb_max_tc + (i & 1));
1016 tc->pfc = ixgbe_dcb_pfc_disabled;
1019 /* Initialize default user to priority mapping, UPx->TC0 */
1020 tc = &dcb_config->tc_config[0];
1021 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1022 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1023 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1024 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1025 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1027 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1028 dcb_config->pfc_mode_enable = false;
1029 dcb_config->vt_mode = true;
1030 dcb_config->round_robin_enable = false;
1031 /* support all DCB capabilities in 82599 */
1032 dcb_config->support.capabilities = 0xFF;
1034 /*we only support 4 Tcs for X540, X550 */
1035 if (hw->mac.type == ixgbe_mac_X540 ||
1036 hw->mac.type == ixgbe_mac_X550 ||
1037 hw->mac.type == ixgbe_mac_X550EM_x ||
1038 hw->mac.type == ixgbe_mac_X550EM_a) {
1039 dcb_config->num_tcs.pg_tcs = 4;
1040 dcb_config->num_tcs.pfc_tcs = 4;
1045 * Ensure that all locks are released before first NVM or PHY access
1048 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1053 * Phy lock should not fail in this early stage. If this is the case,
1054 * it is due to an improper exit of the application.
1055 * So force the release of the faulty lock. Release of common lock
1056 * is done automatically by swfw_sync function.
1058 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1059 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1060 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1062 ixgbe_release_swfw_semaphore(hw, mask);
1065 * These ones are more tricky since they are common to all ports; but
1066 * swfw_sync retries last long enough (1s) to be almost sure that if
1067 * lock can not be taken it is due to an improper lock of the
1070 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1071 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1072 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1074 ixgbe_release_swfw_semaphore(hw, mask);
1078 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1079 * It returns 0 on success.
1082 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1084 struct rte_pci_device *pci_dev;
1085 struct ixgbe_hw *hw =
1086 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1087 struct ixgbe_vfta *shadow_vfta =
1088 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1089 struct ixgbe_hwstrip *hwstrip =
1090 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1091 struct ixgbe_dcb_config *dcb_config =
1092 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1093 struct ixgbe_filter_info *filter_info =
1094 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1099 PMD_INIT_FUNC_TRACE();
1101 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1102 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1103 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1106 * For secondary processes, we don't initialise any further as primary
1107 * has already done this work. Only check we don't need a different
1108 * RX and TX function.
1110 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1111 struct ixgbe_tx_queue *txq;
1112 /* TX queue function in primary, set by last queue initialized
1113 * Tx queue may not initialized by primary process
1115 if (eth_dev->data->tx_queues) {
1116 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1117 ixgbe_set_tx_function(eth_dev, txq);
1119 /* Use default TX function if we get here */
1120 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1121 "Using default TX function.");
1124 ixgbe_set_rx_function(eth_dev);
1128 pci_dev = eth_dev->pci_dev;
1130 rte_eth_copy_pci_info(eth_dev, pci_dev);
1132 /* Vendor and Device ID need to be set before init of shared code */
1133 hw->device_id = pci_dev->id.device_id;
1134 hw->vendor_id = pci_dev->id.vendor_id;
1135 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1136 hw->allow_unsupported_sfp = 1;
1138 /* Initialize the shared code (base driver) */
1139 #ifdef RTE_NIC_BYPASS
1140 diag = ixgbe_bypass_init_shared_code(hw);
1142 diag = ixgbe_init_shared_code(hw);
1143 #endif /* RTE_NIC_BYPASS */
1145 if (diag != IXGBE_SUCCESS) {
1146 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1150 /* pick up the PCI bus settings for reporting later */
1151 ixgbe_get_bus_info(hw);
1153 /* Unlock any pending hardware semaphore */
1154 ixgbe_swfw_lock_reset(hw);
1156 /* Initialize DCB configuration*/
1157 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1158 ixgbe_dcb_init(hw, dcb_config);
1159 /* Get Hardware Flow Control setting */
1160 hw->fc.requested_mode = ixgbe_fc_full;
1161 hw->fc.current_mode = ixgbe_fc_full;
1162 hw->fc.pause_time = IXGBE_FC_PAUSE;
1163 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1164 hw->fc.low_water[i] = IXGBE_FC_LO;
1165 hw->fc.high_water[i] = IXGBE_FC_HI;
1167 hw->fc.send_xon = 1;
1169 /* Make sure we have a good EEPROM before we read from it */
1170 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1171 if (diag != IXGBE_SUCCESS) {
1172 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1176 #ifdef RTE_NIC_BYPASS
1177 diag = ixgbe_bypass_init_hw(hw);
1179 diag = ixgbe_init_hw(hw);
1180 #endif /* RTE_NIC_BYPASS */
1183 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1184 * is called too soon after the kernel driver unbinding/binding occurs.
1185 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1186 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1187 * also called. See ixgbe_identify_phy_82599(). The reason for the
1188 * failure is not known, and only occuts when virtualisation features
1189 * are disabled in the bios. A delay of 100ms was found to be enough by
1190 * trial-and-error, and is doubled to be safe.
1192 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1194 diag = ixgbe_init_hw(hw);
1197 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1198 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1199 "LOM. Please be aware there may be issues associated "
1200 "with your hardware.");
1201 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1202 "please contact your Intel or hardware representative "
1203 "who provided you with this hardware.");
1204 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1205 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1207 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1211 /* Reset the hw statistics */
1212 ixgbe_dev_stats_reset(eth_dev);
1214 /* disable interrupt */
1215 ixgbe_disable_intr(hw);
1217 /* reset mappings for queue statistics hw counters*/
1218 ixgbe_reset_qstat_mappings(hw);
1220 /* Allocate memory for storing MAC addresses */
1221 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1222 hw->mac.num_rar_entries, 0);
1223 if (eth_dev->data->mac_addrs == NULL) {
1225 "Failed to allocate %u bytes needed to store "
1227 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1230 /* Copy the permanent MAC address */
1231 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1232 ð_dev->data->mac_addrs[0]);
1234 /* Allocate memory for storing hash filter MAC addresses */
1235 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1236 IXGBE_VMDQ_NUM_UC_MAC, 0);
1237 if (eth_dev->data->hash_mac_addrs == NULL) {
1239 "Failed to allocate %d bytes needed to store MAC addresses",
1240 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1244 /* initialize the vfta */
1245 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1247 /* initialize the hw strip bitmap*/
1248 memset(hwstrip, 0, sizeof(*hwstrip));
1250 /* initialize PF if max_vfs not zero */
1251 ixgbe_pf_host_init(eth_dev);
1253 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1254 /* let hardware know driver is loaded */
1255 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1256 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1257 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1258 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1259 IXGBE_WRITE_FLUSH(hw);
1261 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1262 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1263 (int) hw->mac.type, (int) hw->phy.type,
1264 (int) hw->phy.sfp_type);
1266 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1267 (int) hw->mac.type, (int) hw->phy.type);
1269 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1270 eth_dev->data->port_id, pci_dev->id.vendor_id,
1271 pci_dev->id.device_id);
1273 rte_intr_callback_register(&pci_dev->intr_handle,
1274 ixgbe_dev_interrupt_handler,
1277 /* enable uio/vfio intr/eventfd mapping */
1278 rte_intr_enable(&pci_dev->intr_handle);
1280 /* enable support intr */
1281 ixgbe_enable_intr(eth_dev);
1283 /* initialize 5tuple filter list */
1284 TAILQ_INIT(&filter_info->fivetuple_list);
1285 memset(filter_info->fivetuple_mask, 0,
1286 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1292 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1294 struct rte_pci_device *pci_dev;
1295 struct ixgbe_hw *hw;
1297 PMD_INIT_FUNC_TRACE();
1299 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1302 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1303 pci_dev = eth_dev->pci_dev;
1305 if (hw->adapter_stopped == 0)
1306 ixgbe_dev_close(eth_dev);
1308 eth_dev->dev_ops = NULL;
1309 eth_dev->rx_pkt_burst = NULL;
1310 eth_dev->tx_pkt_burst = NULL;
1312 /* Unlock any pending hardware semaphore */
1313 ixgbe_swfw_lock_reset(hw);
1315 /* disable uio intr before callback unregister */
1316 rte_intr_disable(&(pci_dev->intr_handle));
1317 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1318 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1320 /* uninitialize PF if max_vfs not zero */
1321 ixgbe_pf_host_uninit(eth_dev);
1323 rte_free(eth_dev->data->mac_addrs);
1324 eth_dev->data->mac_addrs = NULL;
1326 rte_free(eth_dev->data->hash_mac_addrs);
1327 eth_dev->data->hash_mac_addrs = NULL;
1333 * Negotiate mailbox API version with the PF.
1334 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1335 * Then we try to negotiate starting with the most recent one.
1336 * If all negotiation attempts fail, then we will proceed with
1337 * the default one (ixgbe_mbox_api_10).
1340 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1344 /* start with highest supported, proceed down */
1345 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1352 i != RTE_DIM(sup_ver) &&
1353 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1359 generate_random_mac_addr(struct ether_addr *mac_addr)
1363 /* Set Organizationally Unique Identifier (OUI) prefix. */
1364 mac_addr->addr_bytes[0] = 0x00;
1365 mac_addr->addr_bytes[1] = 0x09;
1366 mac_addr->addr_bytes[2] = 0xC0;
1367 /* Force indication of locally assigned MAC address. */
1368 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1369 /* Generate the last 3 bytes of the MAC address with a random number. */
1370 random = rte_rand();
1371 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1375 * Virtual Function device init
1378 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1382 struct rte_pci_device *pci_dev;
1383 struct ixgbe_hw *hw =
1384 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1385 struct ixgbe_vfta *shadow_vfta =
1386 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1387 struct ixgbe_hwstrip *hwstrip =
1388 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1389 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1391 PMD_INIT_FUNC_TRACE();
1393 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1394 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1395 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1397 /* for secondary processes, we don't initialise any further as primary
1398 * has already done this work. Only check we don't need a different
1401 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1402 struct ixgbe_tx_queue *txq;
1403 /* TX queue function in primary, set by last queue initialized
1404 * Tx queue may not initialized by primary process
1406 if (eth_dev->data->tx_queues) {
1407 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1408 ixgbe_set_tx_function(eth_dev, txq);
1410 /* Use default TX function if we get here */
1411 PMD_INIT_LOG(NOTICE,
1412 "No TX queues configured yet. Using default TX function.");
1415 ixgbe_set_rx_function(eth_dev);
1420 pci_dev = eth_dev->pci_dev;
1422 rte_eth_copy_pci_info(eth_dev, pci_dev);
1424 hw->device_id = pci_dev->id.device_id;
1425 hw->vendor_id = pci_dev->id.vendor_id;
1426 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1428 /* initialize the vfta */
1429 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1431 /* initialize the hw strip bitmap*/
1432 memset(hwstrip, 0, sizeof(*hwstrip));
1434 /* Initialize the shared code (base driver) */
1435 diag = ixgbe_init_shared_code(hw);
1436 if (diag != IXGBE_SUCCESS) {
1437 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1441 /* init_mailbox_params */
1442 hw->mbx.ops.init_params(hw);
1444 /* Reset the hw statistics */
1445 ixgbevf_dev_stats_reset(eth_dev);
1447 /* Disable the interrupts for VF */
1448 ixgbevf_intr_disable(hw);
1450 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1451 diag = hw->mac.ops.reset_hw(hw);
1454 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1455 * the underlying PF driver has not assigned a MAC address to the VF.
1456 * In this case, assign a random MAC address.
1458 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1459 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1463 /* negotiate mailbox API version to use with the PF. */
1464 ixgbevf_negotiate_api(hw);
1466 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1467 ixgbevf_get_queues(hw, &tcs, &tc);
1469 /* Allocate memory for storing MAC addresses */
1470 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1471 hw->mac.num_rar_entries, 0);
1472 if (eth_dev->data->mac_addrs == NULL) {
1474 "Failed to allocate %u bytes needed to store "
1476 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1480 /* Generate a random MAC address, if none was assigned by PF. */
1481 if (is_zero_ether_addr(perm_addr)) {
1482 generate_random_mac_addr(perm_addr);
1483 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1485 rte_free(eth_dev->data->mac_addrs);
1486 eth_dev->data->mac_addrs = NULL;
1489 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1490 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1491 "%02x:%02x:%02x:%02x:%02x:%02x",
1492 perm_addr->addr_bytes[0],
1493 perm_addr->addr_bytes[1],
1494 perm_addr->addr_bytes[2],
1495 perm_addr->addr_bytes[3],
1496 perm_addr->addr_bytes[4],
1497 perm_addr->addr_bytes[5]);
1500 /* Copy the permanent MAC address */
1501 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1503 /* reset the hardware with the new settings */
1504 diag = hw->mac.ops.start_hw(hw);
1510 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1514 rte_intr_callback_register(&pci_dev->intr_handle,
1515 ixgbevf_dev_interrupt_handler,
1517 rte_intr_enable(&pci_dev->intr_handle);
1518 ixgbevf_intr_enable(hw);
1520 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1521 eth_dev->data->port_id, pci_dev->id.vendor_id,
1522 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1527 /* Virtual Function device uninit */
1530 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1532 struct ixgbe_hw *hw;
1533 struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1535 PMD_INIT_FUNC_TRACE();
1537 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1540 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1542 if (hw->adapter_stopped == 0)
1543 ixgbevf_dev_close(eth_dev);
1545 eth_dev->dev_ops = NULL;
1546 eth_dev->rx_pkt_burst = NULL;
1547 eth_dev->tx_pkt_burst = NULL;
1549 /* Disable the interrupts for VF */
1550 ixgbevf_intr_disable(hw);
1552 rte_free(eth_dev->data->mac_addrs);
1553 eth_dev->data->mac_addrs = NULL;
1555 rte_intr_disable(&pci_dev->intr_handle);
1556 rte_intr_callback_unregister(&pci_dev->intr_handle,
1557 ixgbevf_dev_interrupt_handler,
1563 static struct eth_driver rte_ixgbe_pmd = {
1565 .name = "rte_ixgbe_pmd",
1566 .id_table = pci_id_ixgbe_map,
1567 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1568 RTE_PCI_DRV_DETACHABLE,
1569 .probe = rte_eth_dev_pci_probe,
1570 .remove = rte_eth_dev_pci_remove,
1572 .eth_dev_init = eth_ixgbe_dev_init,
1573 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1574 .dev_private_size = sizeof(struct ixgbe_adapter),
1578 * virtual function driver struct
1580 static struct eth_driver rte_ixgbevf_pmd = {
1582 .name = "rte_ixgbevf_pmd",
1583 .id_table = pci_id_ixgbevf_map,
1584 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1585 .probe = rte_eth_dev_pci_probe,
1586 .remove = rte_eth_dev_pci_remove,
1588 .eth_dev_init = eth_ixgbevf_dev_init,
1589 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1590 .dev_private_size = sizeof(struct ixgbe_adapter),
1594 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1596 struct ixgbe_hw *hw =
1597 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1598 struct ixgbe_vfta *shadow_vfta =
1599 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1604 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1605 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1606 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1611 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1613 /* update local VFTA copy */
1614 shadow_vfta->vfta[vid_idx] = vfta;
1620 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1623 ixgbe_vlan_hw_strip_enable(dev, queue);
1625 ixgbe_vlan_hw_strip_disable(dev, queue);
1629 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1630 enum rte_vlan_type vlan_type,
1633 struct ixgbe_hw *hw =
1634 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1639 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1640 qinq &= IXGBE_DMATXCTL_GDV;
1642 switch (vlan_type) {
1643 case ETH_VLAN_TYPE_INNER:
1645 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1646 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1647 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1648 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1649 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1650 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1651 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1654 PMD_DRV_LOG(ERR, "Inner type is not supported"
1658 case ETH_VLAN_TYPE_OUTER:
1660 /* Only the high 16-bits is valid */
1661 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1662 IXGBE_EXVET_VET_EXT_SHIFT);
1664 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1665 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1666 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1667 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1668 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1669 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1670 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1676 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1684 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1686 struct ixgbe_hw *hw =
1687 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1690 PMD_INIT_FUNC_TRACE();
1692 /* Filter Table Disable */
1693 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1694 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1696 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1700 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1702 struct ixgbe_hw *hw =
1703 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1704 struct ixgbe_vfta *shadow_vfta =
1705 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1709 PMD_INIT_FUNC_TRACE();
1711 /* Filter Table Enable */
1712 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1713 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1714 vlnctrl |= IXGBE_VLNCTRL_VFE;
1716 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1718 /* write whatever is in local vfta copy */
1719 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1720 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1724 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1726 struct ixgbe_hwstrip *hwstrip =
1727 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1728 struct ixgbe_rx_queue *rxq;
1730 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1734 IXGBE_SET_HWSTRIP(hwstrip, queue);
1736 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1738 if (queue >= dev->data->nb_rx_queues)
1741 rxq = dev->data->rx_queues[queue];
1744 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1746 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1750 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1752 struct ixgbe_hw *hw =
1753 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1756 PMD_INIT_FUNC_TRACE();
1758 if (hw->mac.type == ixgbe_mac_82598EB) {
1759 /* No queue level support */
1760 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1764 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1765 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1766 ctrl &= ~IXGBE_RXDCTL_VME;
1767 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1769 /* record those setting for HW strip per queue */
1770 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1774 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1776 struct ixgbe_hw *hw =
1777 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1780 PMD_INIT_FUNC_TRACE();
1782 if (hw->mac.type == ixgbe_mac_82598EB) {
1783 /* No queue level supported */
1784 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1788 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1789 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1790 ctrl |= IXGBE_RXDCTL_VME;
1791 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1793 /* record those setting for HW strip per queue */
1794 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1798 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1800 struct ixgbe_hw *hw =
1801 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1805 PMD_INIT_FUNC_TRACE();
1807 if (hw->mac.type == ixgbe_mac_82598EB) {
1808 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1809 ctrl &= ~IXGBE_VLNCTRL_VME;
1810 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1812 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1813 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1814 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1815 ctrl &= ~IXGBE_RXDCTL_VME;
1816 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1818 /* record those setting for HW strip per queue */
1819 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1825 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1827 struct ixgbe_hw *hw =
1828 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1832 PMD_INIT_FUNC_TRACE();
1834 if (hw->mac.type == ixgbe_mac_82598EB) {
1835 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1836 ctrl |= IXGBE_VLNCTRL_VME;
1837 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1839 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1840 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1841 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1842 ctrl |= IXGBE_RXDCTL_VME;
1843 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1845 /* record those setting for HW strip per queue */
1846 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1852 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1854 struct ixgbe_hw *hw =
1855 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1858 PMD_INIT_FUNC_TRACE();
1860 /* DMATXCTRL: Geric Double VLAN Disable */
1861 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1862 ctrl &= ~IXGBE_DMATXCTL_GDV;
1863 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1865 /* CTRL_EXT: Global Double VLAN Disable */
1866 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1867 ctrl &= ~IXGBE_EXTENDED_VLAN;
1868 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1873 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1875 struct ixgbe_hw *hw =
1876 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1879 PMD_INIT_FUNC_TRACE();
1881 /* DMATXCTRL: Geric Double VLAN Enable */
1882 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1883 ctrl |= IXGBE_DMATXCTL_GDV;
1884 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1886 /* CTRL_EXT: Global Double VLAN Enable */
1887 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1888 ctrl |= IXGBE_EXTENDED_VLAN;
1889 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1891 /* Clear pooling mode of PFVTCTL. It's required by X550. */
1892 if (hw->mac.type == ixgbe_mac_X550 ||
1893 hw->mac.type == ixgbe_mac_X550EM_x ||
1894 hw->mac.type == ixgbe_mac_X550EM_a) {
1895 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1896 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1897 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1901 * VET EXT field in the EXVET register = 0x8100 by default
1902 * So no need to change. Same to VT field of DMATXCTL register
1907 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1909 if (mask & ETH_VLAN_STRIP_MASK) {
1910 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1911 ixgbe_vlan_hw_strip_enable_all(dev);
1913 ixgbe_vlan_hw_strip_disable_all(dev);
1916 if (mask & ETH_VLAN_FILTER_MASK) {
1917 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1918 ixgbe_vlan_hw_filter_enable(dev);
1920 ixgbe_vlan_hw_filter_disable(dev);
1923 if (mask & ETH_VLAN_EXTEND_MASK) {
1924 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1925 ixgbe_vlan_hw_extend_enable(dev);
1927 ixgbe_vlan_hw_extend_disable(dev);
1932 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1934 struct ixgbe_hw *hw =
1935 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1936 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1937 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1939 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1940 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1944 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1949 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1952 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1958 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1959 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1965 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1967 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1968 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1969 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1970 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1972 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1973 /* check multi-queue mode */
1974 switch (dev_conf->rxmode.mq_mode) {
1975 case ETH_MQ_RX_VMDQ_DCB:
1976 case ETH_MQ_RX_VMDQ_DCB_RSS:
1977 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1978 PMD_INIT_LOG(ERR, "SRIOV active,"
1979 " unsupported mq_mode rx %d.",
1980 dev_conf->rxmode.mq_mode);
1983 case ETH_MQ_RX_VMDQ_RSS:
1984 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1985 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1986 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1987 PMD_INIT_LOG(ERR, "SRIOV is active,"
1988 " invalid queue number"
1989 " for VMDQ RSS, allowed"
1990 " value are 1, 2 or 4.");
1994 case ETH_MQ_RX_VMDQ_ONLY:
1995 case ETH_MQ_RX_NONE:
1996 /* if nothing mq mode configure, use default scheme */
1997 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1998 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1999 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2001 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2002 /* SRIOV only works in VMDq enable mode */
2003 PMD_INIT_LOG(ERR, "SRIOV is active,"
2004 " wrong mq_mode rx %d.",
2005 dev_conf->rxmode.mq_mode);
2009 switch (dev_conf->txmode.mq_mode) {
2010 case ETH_MQ_TX_VMDQ_DCB:
2011 /* DCB VMDQ in SRIOV mode, not implement yet */
2012 PMD_INIT_LOG(ERR, "SRIOV is active,"
2013 " unsupported VMDQ mq_mode tx %d.",
2014 dev_conf->txmode.mq_mode);
2016 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2017 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2021 /* check valid queue number */
2022 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2023 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2024 PMD_INIT_LOG(ERR, "SRIOV is active,"
2025 " nb_rx_q=%d nb_tx_q=%d queue number"
2026 " must be less than or equal to %d.",
2028 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2032 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2033 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2037 /* check configuration for vmdb+dcb mode */
2038 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2039 const struct rte_eth_vmdq_dcb_conf *conf;
2041 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2042 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2043 IXGBE_VMDQ_DCB_NB_QUEUES);
2046 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2047 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2048 conf->nb_queue_pools == ETH_32_POOLS)) {
2049 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2050 " nb_queue_pools must be %d or %d.",
2051 ETH_16_POOLS, ETH_32_POOLS);
2055 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2056 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2058 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2059 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2060 IXGBE_VMDQ_DCB_NB_QUEUES);
2063 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2064 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2065 conf->nb_queue_pools == ETH_32_POOLS)) {
2066 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2067 " nb_queue_pools != %d and"
2068 " nb_queue_pools != %d.",
2069 ETH_16_POOLS, ETH_32_POOLS);
2074 /* For DCB mode check our configuration before we go further */
2075 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2076 const struct rte_eth_dcb_rx_conf *conf;
2078 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2079 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2080 IXGBE_DCB_NB_QUEUES);
2083 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2084 if (!(conf->nb_tcs == ETH_4_TCS ||
2085 conf->nb_tcs == ETH_8_TCS)) {
2086 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2087 " and nb_tcs != %d.",
2088 ETH_4_TCS, ETH_8_TCS);
2093 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2094 const struct rte_eth_dcb_tx_conf *conf;
2096 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2097 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2098 IXGBE_DCB_NB_QUEUES);
2101 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2102 if (!(conf->nb_tcs == ETH_4_TCS ||
2103 conf->nb_tcs == ETH_8_TCS)) {
2104 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2105 " and nb_tcs != %d.",
2106 ETH_4_TCS, ETH_8_TCS);
2112 * When DCB/VT is off, maximum number of queues changes,
2113 * except for 82598EB, which remains constant.
2115 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2116 hw->mac.type != ixgbe_mac_82598EB) {
2117 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2119 "Neither VT nor DCB are enabled, "
2121 IXGBE_NONE_MODE_TX_NB_QUEUES);
2130 ixgbe_dev_configure(struct rte_eth_dev *dev)
2132 struct ixgbe_interrupt *intr =
2133 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2134 struct ixgbe_adapter *adapter =
2135 (struct ixgbe_adapter *)dev->data->dev_private;
2138 PMD_INIT_FUNC_TRACE();
2139 /* multipe queue mode checking */
2140 ret = ixgbe_check_mq_mode(dev);
2142 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2147 /* set flag to update link status after init */
2148 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2151 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2152 * allocation or vector Rx preconditions we will reset it.
2154 adapter->rx_bulk_alloc_allowed = true;
2155 adapter->rx_vec_allowed = true;
2161 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2163 struct ixgbe_hw *hw =
2164 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2165 struct ixgbe_interrupt *intr =
2166 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2169 /* only set up it on X550EM_X */
2170 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2171 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2172 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2173 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2174 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2175 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2180 * Configure device link speed and setup link.
2181 * It returns 0 on success.
2184 ixgbe_dev_start(struct rte_eth_dev *dev)
2186 struct ixgbe_hw *hw =
2187 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2188 struct ixgbe_vf_info *vfinfo =
2189 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2190 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2191 uint32_t intr_vector = 0;
2192 int err, link_up = 0, negotiate = 0;
2197 uint32_t *link_speeds;
2199 PMD_INIT_FUNC_TRACE();
2201 /* IXGBE devices don't support:
2202 * - half duplex (checked afterwards for valid speeds)
2203 * - fixed speed: TODO implement
2205 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2206 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2207 dev->data->port_id);
2211 /* disable uio/vfio intr/eventfd mapping */
2212 rte_intr_disable(intr_handle);
2215 hw->adapter_stopped = 0;
2216 ixgbe_stop_adapter(hw);
2218 /* reinitialize adapter
2219 * this calls reset and start
2221 status = ixgbe_pf_reset_hw(hw);
2224 hw->mac.ops.start_hw(hw);
2225 hw->mac.get_link_status = true;
2227 /* configure PF module if SRIOV enabled */
2228 ixgbe_pf_host_configure(dev);
2230 ixgbe_dev_phy_intr_setup(dev);
2232 /* check and configure queue intr-vector mapping */
2233 if ((rte_intr_cap_multiple(intr_handle) ||
2234 !RTE_ETH_DEV_SRIOV(dev).active) &&
2235 dev->data->dev_conf.intr_conf.rxq != 0) {
2236 intr_vector = dev->data->nb_rx_queues;
2237 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2238 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2239 IXGBE_MAX_INTR_QUEUE_NUM);
2242 if (rte_intr_efd_enable(intr_handle, intr_vector))
2246 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2247 intr_handle->intr_vec =
2248 rte_zmalloc("intr_vec",
2249 dev->data->nb_rx_queues * sizeof(int), 0);
2250 if (intr_handle->intr_vec == NULL) {
2251 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2252 " intr_vec\n", dev->data->nb_rx_queues);
2257 /* confiugre msix for sleep until rx interrupt */
2258 ixgbe_configure_msix(dev);
2260 /* initialize transmission unit */
2261 ixgbe_dev_tx_init(dev);
2263 /* This can fail when allocating mbufs for descriptor rings */
2264 err = ixgbe_dev_rx_init(dev);
2266 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2270 err = ixgbe_dev_rxtx_start(dev);
2272 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2276 /* Skip link setup if loopback mode is enabled for 82599. */
2277 if (hw->mac.type == ixgbe_mac_82599EB &&
2278 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2279 goto skip_link_setup;
2281 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2282 err = hw->mac.ops.setup_sfp(hw);
2287 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2288 /* Turn on the copper */
2289 ixgbe_set_phy_power(hw, true);
2291 /* Turn on the laser */
2292 ixgbe_enable_tx_laser(hw);
2295 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2298 dev->data->dev_link.link_status = link_up;
2300 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2304 link_speeds = &dev->data->dev_conf.link_speeds;
2305 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2306 ETH_LINK_SPEED_10G)) {
2307 PMD_INIT_LOG(ERR, "Invalid link setting");
2312 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2313 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2314 IXGBE_LINK_SPEED_82599_AUTONEG :
2315 IXGBE_LINK_SPEED_82598_AUTONEG;
2317 if (*link_speeds & ETH_LINK_SPEED_10G)
2318 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2319 if (*link_speeds & ETH_LINK_SPEED_1G)
2320 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2321 if (*link_speeds & ETH_LINK_SPEED_100M)
2322 speed |= IXGBE_LINK_SPEED_100_FULL;
2325 err = ixgbe_setup_link(hw, speed, link_up);
2331 if (rte_intr_allow_others(intr_handle)) {
2332 /* check if lsc interrupt is enabled */
2333 if (dev->data->dev_conf.intr_conf.lsc != 0)
2334 ixgbe_dev_lsc_interrupt_setup(dev);
2336 rte_intr_callback_unregister(intr_handle,
2337 ixgbe_dev_interrupt_handler,
2339 if (dev->data->dev_conf.intr_conf.lsc != 0)
2340 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2341 " no intr multiplex\n");
2344 /* check if rxq interrupt is enabled */
2345 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2346 rte_intr_dp_is_en(intr_handle))
2347 ixgbe_dev_rxq_interrupt_setup(dev);
2349 /* enable uio/vfio intr/eventfd mapping */
2350 rte_intr_enable(intr_handle);
2352 /* resume enabled intr since hw reset */
2353 ixgbe_enable_intr(dev);
2355 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2356 ETH_VLAN_EXTEND_MASK;
2357 ixgbe_vlan_offload_set(dev, mask);
2359 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2360 /* Enable vlan filtering for VMDq */
2361 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2364 /* Configure DCB hw */
2365 ixgbe_configure_dcb(dev);
2367 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2368 err = ixgbe_fdir_configure(dev);
2373 /* Restore vf rate limit */
2374 if (vfinfo != NULL) {
2375 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2376 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2377 if (vfinfo[vf].tx_rate[idx] != 0)
2378 ixgbe_set_vf_rate_limit(dev, vf,
2379 vfinfo[vf].tx_rate[idx],
2383 ixgbe_restore_statistics_mapping(dev);
2388 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2389 ixgbe_dev_clear_queues(dev);
2394 * Stop device: disable rx and tx functions to allow for reconfiguring.
2397 ixgbe_dev_stop(struct rte_eth_dev *dev)
2399 struct rte_eth_link link;
2400 struct ixgbe_hw *hw =
2401 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2402 struct ixgbe_vf_info *vfinfo =
2403 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2404 struct ixgbe_filter_info *filter_info =
2405 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2406 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2407 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2410 PMD_INIT_FUNC_TRACE();
2412 /* disable interrupts */
2413 ixgbe_disable_intr(hw);
2416 ixgbe_pf_reset_hw(hw);
2417 hw->adapter_stopped = 0;
2420 ixgbe_stop_adapter(hw);
2422 for (vf = 0; vfinfo != NULL &&
2423 vf < dev->pci_dev->max_vfs; vf++)
2424 vfinfo[vf].clear_to_send = false;
2426 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2427 /* Turn off the copper */
2428 ixgbe_set_phy_power(hw, false);
2430 /* Turn off the laser */
2431 ixgbe_disable_tx_laser(hw);
2434 ixgbe_dev_clear_queues(dev);
2436 /* Clear stored conf */
2437 dev->data->scattered_rx = 0;
2440 /* Clear recorded link status */
2441 memset(&link, 0, sizeof(link));
2442 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2444 /* Remove all ntuple filters of the device */
2445 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2446 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2447 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2448 TAILQ_REMOVE(&filter_info->fivetuple_list,
2452 memset(filter_info->fivetuple_mask, 0,
2453 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2455 if (!rte_intr_allow_others(intr_handle))
2456 /* resume to the default handler */
2457 rte_intr_callback_register(intr_handle,
2458 ixgbe_dev_interrupt_handler,
2461 /* Clean datapath event and queue/vec mapping */
2462 rte_intr_efd_disable(intr_handle);
2463 if (intr_handle->intr_vec != NULL) {
2464 rte_free(intr_handle->intr_vec);
2465 intr_handle->intr_vec = NULL;
2470 * Set device link up: enable tx.
2473 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2475 struct ixgbe_hw *hw =
2476 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2477 if (hw->mac.type == ixgbe_mac_82599EB) {
2478 #ifdef RTE_NIC_BYPASS
2479 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2480 /* Not suported in bypass mode */
2481 PMD_INIT_LOG(ERR, "Set link up is not supported "
2482 "by device id 0x%x", hw->device_id);
2488 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2489 /* Turn on the copper */
2490 ixgbe_set_phy_power(hw, true);
2492 /* Turn on the laser */
2493 ixgbe_enable_tx_laser(hw);
2500 * Set device link down: disable tx.
2503 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2505 struct ixgbe_hw *hw =
2506 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2507 if (hw->mac.type == ixgbe_mac_82599EB) {
2508 #ifdef RTE_NIC_BYPASS
2509 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2510 /* Not suported in bypass mode */
2511 PMD_INIT_LOG(ERR, "Set link down is not supported "
2512 "by device id 0x%x", hw->device_id);
2518 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2519 /* Turn off the copper */
2520 ixgbe_set_phy_power(hw, false);
2522 /* Turn off the laser */
2523 ixgbe_disable_tx_laser(hw);
2530 * Reest and stop device.
2533 ixgbe_dev_close(struct rte_eth_dev *dev)
2535 struct ixgbe_hw *hw =
2536 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2538 PMD_INIT_FUNC_TRACE();
2540 ixgbe_pf_reset_hw(hw);
2542 ixgbe_dev_stop(dev);
2543 hw->adapter_stopped = 1;
2545 ixgbe_dev_free_queues(dev);
2547 ixgbe_disable_pcie_master(hw);
2549 /* reprogram the RAR[0] in case user changed it. */
2550 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2554 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2555 struct ixgbe_hw_stats *hw_stats,
2556 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2557 uint64_t *total_qprc, uint64_t *total_qprdc)
2559 uint32_t bprc, lxon, lxoff, total;
2560 uint32_t delta_gprc = 0;
2562 /* Workaround for RX byte count not including CRC bytes when CRC
2563 + * strip is enabled. CRC bytes are removed from counters when crc_strip
2566 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2567 IXGBE_HLREG0_RXCRCSTRP);
2569 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2570 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2571 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2572 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2574 for (i = 0; i < 8; i++) {
2575 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2577 /* global total per queue */
2578 hw_stats->mpc[i] += mp;
2579 /* Running comprehensive total for stats display */
2580 *total_missed_rx += hw_stats->mpc[i];
2581 if (hw->mac.type == ixgbe_mac_82598EB) {
2582 hw_stats->rnbc[i] +=
2583 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2584 hw_stats->pxonrxc[i] +=
2585 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2586 hw_stats->pxoffrxc[i] +=
2587 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2589 hw_stats->pxonrxc[i] +=
2590 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2591 hw_stats->pxoffrxc[i] +=
2592 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2593 hw_stats->pxon2offc[i] +=
2594 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2596 hw_stats->pxontxc[i] +=
2597 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2598 hw_stats->pxofftxc[i] +=
2599 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2601 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2602 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2603 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2604 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2606 delta_gprc += delta_qprc;
2608 hw_stats->qprc[i] += delta_qprc;
2609 hw_stats->qptc[i] += delta_qptc;
2611 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2612 hw_stats->qbrc[i] +=
2613 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2615 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2617 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2618 hw_stats->qbtc[i] +=
2619 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2621 hw_stats->qprdc[i] += delta_qprdc;
2622 *total_qprdc += hw_stats->qprdc[i];
2624 *total_qprc += hw_stats->qprc[i];
2625 *total_qbrc += hw_stats->qbrc[i];
2627 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2628 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2629 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2632 * An errata states that gprc actually counts good + missed packets:
2633 * Workaround to set gprc to summated queue packet receives
2635 hw_stats->gprc = *total_qprc;
2637 if (hw->mac.type != ixgbe_mac_82598EB) {
2638 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2639 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2640 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2641 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2642 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2643 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2644 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2645 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2647 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2648 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2649 /* 82598 only has a counter in the high register */
2650 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2651 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2652 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2654 uint64_t old_tpr = hw_stats->tpr;
2656 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2657 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2660 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2662 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2663 hw_stats->gptc += delta_gptc;
2664 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2665 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2668 * Workaround: mprc hardware is incorrectly counting
2669 * broadcasts, so for now we subtract those.
2671 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2672 hw_stats->bprc += bprc;
2673 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2674 if (hw->mac.type == ixgbe_mac_82598EB)
2675 hw_stats->mprc -= bprc;
2677 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2678 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2679 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2680 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2681 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2682 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2684 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2685 hw_stats->lxontxc += lxon;
2686 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2687 hw_stats->lxofftxc += lxoff;
2688 total = lxon + lxoff;
2690 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2691 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2692 hw_stats->gptc -= total;
2693 hw_stats->mptc -= total;
2694 hw_stats->ptc64 -= total;
2695 hw_stats->gotc -= total * ETHER_MIN_LEN;
2697 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2698 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2699 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2700 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2701 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2702 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2703 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2704 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2705 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2706 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2707 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2708 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2709 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2710 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2711 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2712 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2713 /* Only read FCOE on 82599 */
2714 if (hw->mac.type != ixgbe_mac_82598EB) {
2715 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2716 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2717 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2718 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2719 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2722 /* Flow Director Stats registers */
2723 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2724 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2728 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2731 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2733 struct ixgbe_hw *hw =
2734 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2735 struct ixgbe_hw_stats *hw_stats =
2736 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2737 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2740 total_missed_rx = 0;
2745 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2746 &total_qprc, &total_qprdc);
2751 /* Fill out the rte_eth_stats statistics structure */
2752 stats->ipackets = total_qprc;
2753 stats->ibytes = total_qbrc;
2754 stats->opackets = hw_stats->gptc;
2755 stats->obytes = hw_stats->gotc;
2757 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2758 stats->q_ipackets[i] = hw_stats->qprc[i];
2759 stats->q_opackets[i] = hw_stats->qptc[i];
2760 stats->q_ibytes[i] = hw_stats->qbrc[i];
2761 stats->q_obytes[i] = hw_stats->qbtc[i];
2762 stats->q_errors[i] = hw_stats->qprdc[i];
2766 stats->imissed = total_missed_rx;
2767 stats->ierrors = hw_stats->crcerrs +
2783 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2785 struct ixgbe_hw_stats *stats =
2786 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2788 /* HW registers are cleared on read */
2789 ixgbe_dev_stats_get(dev, NULL);
2791 /* Reset software totals */
2792 memset(stats, 0, sizeof(*stats));
2795 /* This function calculates the number of xstats based on the current config */
2797 ixgbe_xstats_calc_num(void) {
2798 return IXGBE_NB_HW_STATS +
2799 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2800 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2803 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2804 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2806 const unsigned cnt_stats = ixgbe_xstats_calc_num();
2807 unsigned stat, i, count;
2809 if (xstats_names != NULL) {
2812 /* Note: limit >= cnt_stats checked upstream
2813 * in rte_eth_xstats_names()
2816 /* Extended stats from ixgbe_hw_stats */
2817 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2818 snprintf(xstats_names[count].name,
2819 sizeof(xstats_names[count].name),
2821 rte_ixgbe_stats_strings[i].name);
2825 /* RX Priority Stats */
2826 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2827 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2828 snprintf(xstats_names[count].name,
2829 sizeof(xstats_names[count].name),
2830 "rx_priority%u_%s", i,
2831 rte_ixgbe_rxq_strings[stat].name);
2836 /* TX Priority Stats */
2837 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2838 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2839 snprintf(xstats_names[count].name,
2840 sizeof(xstats_names[count].name),
2841 "tx_priority%u_%s", i,
2842 rte_ixgbe_txq_strings[stat].name);
2850 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2851 struct rte_eth_xstat_name *xstats_names, unsigned limit)
2855 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2858 if (xstats_names != NULL)
2859 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2860 snprintf(xstats_names[i].name,
2861 sizeof(xstats_names[i].name),
2862 "%s", rte_ixgbevf_stats_strings[i].name);
2863 return IXGBEVF_NB_XSTATS;
2867 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2870 struct ixgbe_hw *hw =
2871 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2872 struct ixgbe_hw_stats *hw_stats =
2873 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2874 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2875 unsigned i, stat, count = 0;
2877 count = ixgbe_xstats_calc_num();
2882 total_missed_rx = 0;
2887 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2888 &total_qprc, &total_qprdc);
2890 /* If this is a reset xstats is NULL, and we have cleared the
2891 * registers by reading them.
2896 /* Extended stats from ixgbe_hw_stats */
2898 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2899 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2900 rte_ixgbe_stats_strings[i].offset);
2904 /* RX Priority Stats */
2905 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2906 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2907 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2908 rte_ixgbe_rxq_strings[stat].offset +
2909 (sizeof(uint64_t) * i));
2914 /* TX Priority Stats */
2915 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2916 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2917 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2918 rte_ixgbe_txq_strings[stat].offset +
2919 (sizeof(uint64_t) * i));
2927 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2929 struct ixgbe_hw_stats *stats =
2930 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2932 unsigned count = ixgbe_xstats_calc_num();
2934 /* HW registers are cleared on read */
2935 ixgbe_dev_xstats_get(dev, NULL, count);
2937 /* Reset software totals */
2938 memset(stats, 0, sizeof(*stats));
2942 ixgbevf_update_stats(struct rte_eth_dev *dev)
2944 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2945 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2946 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2948 /* Good Rx packet, include VF loopback */
2949 UPDATE_VF_STAT(IXGBE_VFGPRC,
2950 hw_stats->last_vfgprc, hw_stats->vfgprc);
2952 /* Good Rx octets, include VF loopback */
2953 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2954 hw_stats->last_vfgorc, hw_stats->vfgorc);
2956 /* Good Tx packet, include VF loopback */
2957 UPDATE_VF_STAT(IXGBE_VFGPTC,
2958 hw_stats->last_vfgptc, hw_stats->vfgptc);
2960 /* Good Tx octets, include VF loopback */
2961 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2962 hw_stats->last_vfgotc, hw_stats->vfgotc);
2964 /* Rx Multicst Packet */
2965 UPDATE_VF_STAT(IXGBE_VFMPRC,
2966 hw_stats->last_vfmprc, hw_stats->vfmprc);
2970 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2973 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2974 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2977 if (n < IXGBEVF_NB_XSTATS)
2978 return IXGBEVF_NB_XSTATS;
2980 ixgbevf_update_stats(dev);
2985 /* Extended stats */
2986 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2987 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2988 rte_ixgbevf_stats_strings[i].offset);
2991 return IXGBEVF_NB_XSTATS;
2995 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2997 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2998 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3000 ixgbevf_update_stats(dev);
3005 stats->ipackets = hw_stats->vfgprc;
3006 stats->ibytes = hw_stats->vfgorc;
3007 stats->opackets = hw_stats->vfgptc;
3008 stats->obytes = hw_stats->vfgotc;
3012 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3014 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3015 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3017 /* Sync HW register to the last stats */
3018 ixgbevf_dev_stats_get(dev, NULL);
3020 /* reset HW current stats*/
3021 hw_stats->vfgprc = 0;
3022 hw_stats->vfgorc = 0;
3023 hw_stats->vfgptc = 0;
3024 hw_stats->vfgotc = 0;
3028 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3030 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3031 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3033 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3034 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3035 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3037 * When DCB/VT is off, maximum number of queues changes,
3038 * except for 82598EB, which remains constant.
3040 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3041 hw->mac.type != ixgbe_mac_82598EB)
3042 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3044 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3045 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3046 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3047 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3048 dev_info->max_vfs = dev->pci_dev->max_vfs;
3049 if (hw->mac.type == ixgbe_mac_82598EB)
3050 dev_info->max_vmdq_pools = ETH_16_POOLS;
3052 dev_info->max_vmdq_pools = ETH_64_POOLS;
3053 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3054 dev_info->rx_offload_capa =
3055 DEV_RX_OFFLOAD_VLAN_STRIP |
3056 DEV_RX_OFFLOAD_IPV4_CKSUM |
3057 DEV_RX_OFFLOAD_UDP_CKSUM |
3058 DEV_RX_OFFLOAD_TCP_CKSUM;
3061 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3064 if ((hw->mac.type == ixgbe_mac_82599EB ||
3065 hw->mac.type == ixgbe_mac_X540) &&
3066 !RTE_ETH_DEV_SRIOV(dev).active)
3067 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3069 if (hw->mac.type == ixgbe_mac_X550 ||
3070 hw->mac.type == ixgbe_mac_X550EM_x ||
3071 hw->mac.type == ixgbe_mac_X550EM_a)
3072 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3074 dev_info->tx_offload_capa =
3075 DEV_TX_OFFLOAD_VLAN_INSERT |
3076 DEV_TX_OFFLOAD_IPV4_CKSUM |
3077 DEV_TX_OFFLOAD_UDP_CKSUM |
3078 DEV_TX_OFFLOAD_TCP_CKSUM |
3079 DEV_TX_OFFLOAD_SCTP_CKSUM |
3080 DEV_TX_OFFLOAD_TCP_TSO;
3082 if (hw->mac.type == ixgbe_mac_X550 ||
3083 hw->mac.type == ixgbe_mac_X550EM_x ||
3084 hw->mac.type == ixgbe_mac_X550EM_a)
3085 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3087 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3089 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3090 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3091 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3093 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3097 dev_info->default_txconf = (struct rte_eth_txconf) {
3099 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3100 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3101 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3103 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3104 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3105 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3106 ETH_TXQ_FLAGS_NOOFFLOADS,
3109 dev_info->rx_desc_lim = rx_desc_lim;
3110 dev_info->tx_desc_lim = tx_desc_lim;
3112 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3113 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3114 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3116 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3117 if (hw->mac.type == ixgbe_mac_X540 ||
3118 hw->mac.type == ixgbe_mac_X540_vf ||
3119 hw->mac.type == ixgbe_mac_X550 ||
3120 hw->mac.type == ixgbe_mac_X550_vf) {
3121 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3125 static const uint32_t *
3126 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3128 static const uint32_t ptypes[] = {
3129 /* For non-vec functions,
3130 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3131 * for vec functions,
3132 * refers to _recv_raw_pkts_vec().
3136 RTE_PTYPE_L3_IPV4_EXT,
3138 RTE_PTYPE_L3_IPV6_EXT,
3142 RTE_PTYPE_TUNNEL_IP,
3143 RTE_PTYPE_INNER_L3_IPV6,
3144 RTE_PTYPE_INNER_L3_IPV6_EXT,
3145 RTE_PTYPE_INNER_L4_TCP,
3146 RTE_PTYPE_INNER_L4_UDP,
3150 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3151 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3152 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3153 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3159 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3160 struct rte_eth_dev_info *dev_info)
3162 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3164 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3165 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3166 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3167 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3168 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3169 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3170 dev_info->max_vfs = dev->pci_dev->max_vfs;
3171 if (hw->mac.type == ixgbe_mac_82598EB)
3172 dev_info->max_vmdq_pools = ETH_16_POOLS;
3174 dev_info->max_vmdq_pools = ETH_64_POOLS;
3175 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3176 DEV_RX_OFFLOAD_IPV4_CKSUM |
3177 DEV_RX_OFFLOAD_UDP_CKSUM |
3178 DEV_RX_OFFLOAD_TCP_CKSUM;
3179 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3180 DEV_TX_OFFLOAD_IPV4_CKSUM |
3181 DEV_TX_OFFLOAD_UDP_CKSUM |
3182 DEV_TX_OFFLOAD_TCP_CKSUM |
3183 DEV_TX_OFFLOAD_SCTP_CKSUM |
3184 DEV_TX_OFFLOAD_TCP_TSO;
3186 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3188 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3189 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3190 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3192 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3196 dev_info->default_txconf = (struct rte_eth_txconf) {
3198 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3199 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3200 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3202 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3203 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3204 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3205 ETH_TXQ_FLAGS_NOOFFLOADS,
3208 dev_info->rx_desc_lim = rx_desc_lim;
3209 dev_info->tx_desc_lim = tx_desc_lim;
3212 /* return 0 means link status changed, -1 means not changed */
3214 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3216 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3217 struct rte_eth_link link, old;
3218 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3222 link.link_status = ETH_LINK_DOWN;
3223 link.link_speed = 0;
3224 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3225 memset(&old, 0, sizeof(old));
3226 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3228 hw->mac.get_link_status = true;
3230 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3231 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3232 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3234 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3237 link.link_speed = ETH_SPEED_NUM_100M;
3238 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3239 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3240 if (link.link_status == old.link_status)
3246 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3247 if (link.link_status == old.link_status)
3251 link.link_status = ETH_LINK_UP;
3252 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3254 switch (link_speed) {
3256 case IXGBE_LINK_SPEED_UNKNOWN:
3257 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3258 link.link_speed = ETH_SPEED_NUM_100M;
3261 case IXGBE_LINK_SPEED_100_FULL:
3262 link.link_speed = ETH_SPEED_NUM_100M;
3265 case IXGBE_LINK_SPEED_1GB_FULL:
3266 link.link_speed = ETH_SPEED_NUM_1G;
3269 case IXGBE_LINK_SPEED_10GB_FULL:
3270 link.link_speed = ETH_SPEED_NUM_10G;
3273 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3275 if (link.link_status == old.link_status)
3282 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3284 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3287 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3288 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3289 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3293 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3295 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3298 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3299 fctrl &= (~IXGBE_FCTRL_UPE);
3300 if (dev->data->all_multicast == 1)
3301 fctrl |= IXGBE_FCTRL_MPE;
3303 fctrl &= (~IXGBE_FCTRL_MPE);
3304 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3308 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3310 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3313 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3314 fctrl |= IXGBE_FCTRL_MPE;
3315 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3319 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3321 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3324 if (dev->data->promiscuous == 1)
3325 return; /* must remain in all_multicast mode */
3327 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3328 fctrl &= (~IXGBE_FCTRL_MPE);
3329 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3333 * It clears the interrupt causes and enables the interrupt.
3334 * It will be called once only during nic initialized.
3337 * Pointer to struct rte_eth_dev.
3340 * - On success, zero.
3341 * - On failure, a negative value.
3344 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3346 struct ixgbe_interrupt *intr =
3347 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3349 ixgbe_dev_link_status_print(dev);
3350 intr->mask |= IXGBE_EICR_LSC;
3356 * It clears the interrupt causes and enables the interrupt.
3357 * It will be called once only during nic initialized.
3360 * Pointer to struct rte_eth_dev.
3363 * - On success, zero.
3364 * - On failure, a negative value.
3367 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3369 struct ixgbe_interrupt *intr =
3370 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3372 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3378 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3381 * Pointer to struct rte_eth_dev.
3384 * - On success, zero.
3385 * - On failure, a negative value.
3388 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3391 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3392 struct ixgbe_interrupt *intr =
3393 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3395 /* clear all cause mask */
3396 ixgbe_disable_intr(hw);
3398 /* read-on-clear nic registers here */
3399 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3400 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3404 /* set flag for async link update */
3405 if (eicr & IXGBE_EICR_LSC)
3406 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3408 if (eicr & IXGBE_EICR_MAILBOX)
3409 intr->flags |= IXGBE_FLAG_MAILBOX;
3411 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3412 hw->phy.type == ixgbe_phy_x550em_ext_t &&
3413 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3414 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3420 * It gets and then prints the link status.
3423 * Pointer to struct rte_eth_dev.
3426 * - On success, zero.
3427 * - On failure, a negative value.
3430 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3432 struct rte_eth_link link;
3434 memset(&link, 0, sizeof(link));
3435 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3436 if (link.link_status) {
3437 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3438 (int)(dev->data->port_id),
3439 (unsigned)link.link_speed,
3440 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3441 "full-duplex" : "half-duplex");
3443 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3444 (int)(dev->data->port_id));
3446 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3447 dev->pci_dev->addr.domain,
3448 dev->pci_dev->addr.bus,
3449 dev->pci_dev->addr.devid,
3450 dev->pci_dev->addr.function);
3454 * It executes link_update after knowing an interrupt occurred.
3457 * Pointer to struct rte_eth_dev.
3460 * - On success, zero.
3461 * - On failure, a negative value.
3464 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3466 struct ixgbe_interrupt *intr =
3467 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3469 struct rte_eth_link link;
3470 int intr_enable_delay = false;
3471 struct ixgbe_hw *hw =
3472 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3474 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3476 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3477 ixgbe_pf_mbx_process(dev);
3478 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3481 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3482 ixgbe_handle_lasi(hw);
3483 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3486 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3487 /* get the link status before link update, for predicting later */
3488 memset(&link, 0, sizeof(link));
3489 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3491 ixgbe_dev_link_update(dev, 0);
3494 if (!link.link_status)
3495 /* handle it 1 sec later, wait it being stable */
3496 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3497 /* likely to down */
3499 /* handle it 4 sec later, wait it being stable */
3500 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3502 ixgbe_dev_link_status_print(dev);
3504 intr_enable_delay = true;
3507 if (intr_enable_delay) {
3508 if (rte_eal_alarm_set(timeout * 1000,
3509 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3510 PMD_DRV_LOG(ERR, "Error setting alarm");
3512 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3513 ixgbe_enable_intr(dev);
3514 rte_intr_enable(&(dev->pci_dev->intr_handle));
3522 * Interrupt handler which shall be registered for alarm callback for delayed
3523 * handling specific interrupt to wait for the stable nic state. As the
3524 * NIC interrupt state is not stable for ixgbe after link is just down,
3525 * it needs to wait 4 seconds to get the stable status.
3528 * Pointer to interrupt handle.
3530 * The address of parameter (struct rte_eth_dev *) regsitered before.
3536 ixgbe_dev_interrupt_delayed_handler(void *param)
3538 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3539 struct ixgbe_interrupt *intr =
3540 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3541 struct ixgbe_hw *hw =
3542 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3545 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3546 if (eicr & IXGBE_EICR_MAILBOX)
3547 ixgbe_pf_mbx_process(dev);
3549 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3550 ixgbe_handle_lasi(hw);
3551 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3554 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3555 ixgbe_dev_link_update(dev, 0);
3556 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3557 ixgbe_dev_link_status_print(dev);
3558 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3561 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3562 ixgbe_enable_intr(dev);
3563 rte_intr_enable(&(dev->pci_dev->intr_handle));
3567 * Interrupt handler triggered by NIC for handling
3568 * specific interrupt.
3571 * Pointer to interrupt handle.
3573 * The address of parameter (struct rte_eth_dev *) regsitered before.
3579 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3582 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3584 ixgbe_dev_interrupt_get_status(dev);
3585 ixgbe_dev_interrupt_action(dev);
3589 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3591 struct ixgbe_hw *hw;
3593 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3594 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3598 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3600 struct ixgbe_hw *hw;
3602 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3603 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3607 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3609 struct ixgbe_hw *hw;
3615 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3617 fc_conf->pause_time = hw->fc.pause_time;
3618 fc_conf->high_water = hw->fc.high_water[0];
3619 fc_conf->low_water = hw->fc.low_water[0];
3620 fc_conf->send_xon = hw->fc.send_xon;
3621 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3624 * Return rx_pause status according to actual setting of
3627 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3628 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3634 * Return tx_pause status according to actual setting of
3637 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3638 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3643 if (rx_pause && tx_pause)
3644 fc_conf->mode = RTE_FC_FULL;
3646 fc_conf->mode = RTE_FC_RX_PAUSE;
3648 fc_conf->mode = RTE_FC_TX_PAUSE;
3650 fc_conf->mode = RTE_FC_NONE;
3656 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3658 struct ixgbe_hw *hw;
3660 uint32_t rx_buf_size;
3661 uint32_t max_high_water;
3663 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3670 PMD_INIT_FUNC_TRACE();
3672 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3673 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3674 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3677 * At least reserve one Ethernet frame for watermark
3678 * high_water/low_water in kilo bytes for ixgbe
3680 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3681 if ((fc_conf->high_water > max_high_water) ||
3682 (fc_conf->high_water < fc_conf->low_water)) {
3683 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3684 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3688 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3689 hw->fc.pause_time = fc_conf->pause_time;
3690 hw->fc.high_water[0] = fc_conf->high_water;
3691 hw->fc.low_water[0] = fc_conf->low_water;
3692 hw->fc.send_xon = fc_conf->send_xon;
3693 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3695 err = ixgbe_fc_enable(hw);
3697 /* Not negotiated is not an error case */
3698 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3700 /* check if we want to forward MAC frames - driver doesn't have native
3701 * capability to do that, so we'll write the registers ourselves */
3703 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3705 /* set or clear MFLCN.PMCF bit depending on configuration */
3706 if (fc_conf->mac_ctrl_frame_fwd != 0)
3707 mflcn |= IXGBE_MFLCN_PMCF;
3709 mflcn &= ~IXGBE_MFLCN_PMCF;
3711 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3712 IXGBE_WRITE_FLUSH(hw);
3717 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3722 * ixgbe_pfc_enable_generic - Enable flow control
3723 * @hw: pointer to hardware structure
3724 * @tc_num: traffic class number
3725 * Enable flow control according to the current settings.
3728 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3731 uint32_t mflcn_reg, fccfg_reg;
3733 uint32_t fcrtl, fcrth;
3737 /* Validate the water mark configuration */
3738 if (!hw->fc.pause_time) {
3739 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3743 /* Low water mark of zero causes XOFF floods */
3744 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3745 /* High/Low water can not be 0 */
3746 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3747 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3748 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3752 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3753 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3754 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3758 /* Negotiate the fc mode to use */
3759 ixgbe_fc_autoneg(hw);
3761 /* Disable any previous flow control settings */
3762 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3763 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3765 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3766 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3768 switch (hw->fc.current_mode) {
3771 * If the count of enabled RX Priority Flow control >1,
3772 * and the TX pause can not be disabled
3775 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3776 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3777 if (reg & IXGBE_FCRTH_FCEN)
3781 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3783 case ixgbe_fc_rx_pause:
3785 * Rx Flow control is enabled and Tx Flow control is
3786 * disabled by software override. Since there really
3787 * isn't a way to advertise that we are capable of RX
3788 * Pause ONLY, we will advertise that we support both
3789 * symmetric and asymmetric Rx PAUSE. Later, we will
3790 * disable the adapter's ability to send PAUSE frames.
3792 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3794 * If the count of enabled RX Priority Flow control >1,
3795 * and the TX pause can not be disabled
3798 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3799 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3800 if (reg & IXGBE_FCRTH_FCEN)
3804 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3806 case ixgbe_fc_tx_pause:
3808 * Tx Flow control is enabled, and Rx Flow control is
3809 * disabled by software override.
3811 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3814 /* Flow control (both Rx and Tx) is enabled by SW override. */
3815 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3816 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3819 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3820 ret_val = IXGBE_ERR_CONFIG;
3824 /* Set 802.3x based flow control settings. */
3825 mflcn_reg |= IXGBE_MFLCN_DPF;
3826 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3827 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3829 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3830 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3831 hw->fc.high_water[tc_num]) {
3832 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3833 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3834 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3836 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3838 * In order to prevent Tx hangs when the internal Tx
3839 * switch is enabled we must set the high water mark
3840 * to the maximum FCRTH value. This allows the Tx
3841 * switch to function even under heavy Rx workloads.
3843 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3845 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3847 /* Configure pause time (2 TCs per register) */
3848 reg = hw->fc.pause_time * 0x00010001;
3849 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3850 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3852 /* Configure flow control refresh threshold value */
3853 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3860 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
3862 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3863 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3865 if (hw->mac.type != ixgbe_mac_82598EB) {
3866 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
3872 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3875 uint32_t rx_buf_size;
3876 uint32_t max_high_water;
3878 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3879 struct ixgbe_hw *hw =
3880 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3881 struct ixgbe_dcb_config *dcb_config =
3882 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3884 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3891 PMD_INIT_FUNC_TRACE();
3893 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3894 tc_num = map[pfc_conf->priority];
3895 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3896 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3898 * At least reserve one Ethernet frame for watermark
3899 * high_water/low_water in kilo bytes for ixgbe
3901 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3902 if ((pfc_conf->fc.high_water > max_high_water) ||
3903 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3904 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3905 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3909 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3910 hw->fc.pause_time = pfc_conf->fc.pause_time;
3911 hw->fc.send_xon = pfc_conf->fc.send_xon;
3912 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
3913 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3915 err = ixgbe_dcb_pfc_enable(dev, tc_num);
3917 /* Not negotiated is not an error case */
3918 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3921 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3926 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3927 struct rte_eth_rss_reta_entry64 *reta_conf,
3930 uint16_t i, sp_reta_size;
3933 uint16_t idx, shift;
3934 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3937 PMD_INIT_FUNC_TRACE();
3939 if (!ixgbe_rss_update_sp(hw->mac.type)) {
3940 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3945 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3946 if (reta_size != sp_reta_size) {
3947 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3948 "(%d) doesn't match the number hardware can supported "
3949 "(%d)\n", reta_size, sp_reta_size);
3953 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3954 idx = i / RTE_RETA_GROUP_SIZE;
3955 shift = i % RTE_RETA_GROUP_SIZE;
3956 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3960 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3961 if (mask == IXGBE_4_BIT_MASK)
3964 r = IXGBE_READ_REG(hw, reta_reg);
3965 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3966 if (mask & (0x1 << j))
3967 reta |= reta_conf[idx].reta[shift + j] <<
3970 reta |= r & (IXGBE_8_BIT_MASK <<
3973 IXGBE_WRITE_REG(hw, reta_reg, reta);
3980 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3981 struct rte_eth_rss_reta_entry64 *reta_conf,
3984 uint16_t i, sp_reta_size;
3987 uint16_t idx, shift;
3988 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3991 PMD_INIT_FUNC_TRACE();
3992 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3993 if (reta_size != sp_reta_size) {
3994 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3995 "(%d) doesn't match the number hardware can supported "
3996 "(%d)\n", reta_size, sp_reta_size);
4000 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4001 idx = i / RTE_RETA_GROUP_SIZE;
4002 shift = i % RTE_RETA_GROUP_SIZE;
4003 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4008 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4009 reta = IXGBE_READ_REG(hw, reta_reg);
4010 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4011 if (mask & (0x1 << j))
4012 reta_conf[idx].reta[shift + j] =
4013 ((reta >> (CHAR_BIT * j)) &
4022 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4023 uint32_t index, uint32_t pool)
4025 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4026 uint32_t enable_addr = 1;
4028 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4032 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4034 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4036 ixgbe_clear_rar(hw, index);
4040 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4042 ixgbe_remove_rar(dev, 0);
4044 ixgbe_add_rar(dev, addr, 0, 0);
4048 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4052 struct ixgbe_hw *hw;
4053 struct rte_eth_dev_info dev_info;
4054 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4056 ixgbe_dev_info_get(dev, &dev_info);
4058 /* check that mtu is within the allowed range */
4059 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4062 /* refuse mtu that requires the support of scattered packets when this
4063 * feature has not been enabled before.
4065 if (!dev->data->scattered_rx &&
4066 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4067 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4070 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4071 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4073 /* switch to jumbo mode if needed */
4074 if (frame_size > ETHER_MAX_LEN) {
4075 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4076 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4078 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4079 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4081 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4083 /* update max frame size */
4084 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4086 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4087 maxfrs &= 0x0000FFFF;
4088 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4089 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4095 * Virtual Function operations
4098 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4100 PMD_INIT_FUNC_TRACE();
4102 /* Clear interrupt mask to stop from interrupts being generated */
4103 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4105 IXGBE_WRITE_FLUSH(hw);
4109 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4111 PMD_INIT_FUNC_TRACE();
4113 /* VF enable interrupt autoclean */
4114 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4115 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4116 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4118 IXGBE_WRITE_FLUSH(hw);
4122 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4124 struct rte_eth_conf *conf = &dev->data->dev_conf;
4125 struct ixgbe_adapter *adapter =
4126 (struct ixgbe_adapter *)dev->data->dev_private;
4128 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4129 dev->data->port_id);
4132 * VF has no ability to enable/disable HW CRC
4133 * Keep the persistent behavior the same as Host PF
4135 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4136 if (!conf->rxmode.hw_strip_crc) {
4137 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4138 conf->rxmode.hw_strip_crc = 1;
4141 if (conf->rxmode.hw_strip_crc) {
4142 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4143 conf->rxmode.hw_strip_crc = 0;
4148 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4149 * allocation or vector Rx preconditions we will reset it.
4151 adapter->rx_bulk_alloc_allowed = true;
4152 adapter->rx_vec_allowed = true;
4158 ixgbevf_dev_start(struct rte_eth_dev *dev)
4160 struct ixgbe_hw *hw =
4161 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4162 uint32_t intr_vector = 0;
4163 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4167 PMD_INIT_FUNC_TRACE();
4169 hw->mac.ops.reset_hw(hw);
4170 hw->mac.get_link_status = true;
4172 /* negotiate mailbox API version to use with the PF. */
4173 ixgbevf_negotiate_api(hw);
4175 ixgbevf_dev_tx_init(dev);
4177 /* This can fail when allocating mbufs for descriptor rings */
4178 err = ixgbevf_dev_rx_init(dev);
4180 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4181 ixgbe_dev_clear_queues(dev);
4186 ixgbevf_set_vfta_all(dev, 1);
4189 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4190 ETH_VLAN_EXTEND_MASK;
4191 ixgbevf_vlan_offload_set(dev, mask);
4193 ixgbevf_dev_rxtx_start(dev);
4195 /* check and configure queue intr-vector mapping */
4196 if (dev->data->dev_conf.intr_conf.rxq != 0) {
4197 intr_vector = dev->data->nb_rx_queues;
4198 if (rte_intr_efd_enable(intr_handle, intr_vector))
4202 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4203 intr_handle->intr_vec =
4204 rte_zmalloc("intr_vec",
4205 dev->data->nb_rx_queues * sizeof(int), 0);
4206 if (intr_handle->intr_vec == NULL) {
4207 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4208 " intr_vec\n", dev->data->nb_rx_queues);
4212 ixgbevf_configure_msix(dev);
4214 rte_intr_enable(intr_handle);
4216 /* Re-enable interrupt for VF */
4217 ixgbevf_intr_enable(hw);
4223 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4225 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4226 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4228 PMD_INIT_FUNC_TRACE();
4230 ixgbevf_intr_disable(hw);
4232 hw->adapter_stopped = 1;
4233 ixgbe_stop_adapter(hw);
4236 * Clear what we set, but we still keep shadow_vfta to
4237 * restore after device starts
4239 ixgbevf_set_vfta_all(dev, 0);
4241 /* Clear stored conf */
4242 dev->data->scattered_rx = 0;
4244 ixgbe_dev_clear_queues(dev);
4246 /* Clean datapath event and queue/vec mapping */
4247 rte_intr_efd_disable(intr_handle);
4248 if (intr_handle->intr_vec != NULL) {
4249 rte_free(intr_handle->intr_vec);
4250 intr_handle->intr_vec = NULL;
4255 ixgbevf_dev_close(struct rte_eth_dev *dev)
4257 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4259 PMD_INIT_FUNC_TRACE();
4263 ixgbevf_dev_stop(dev);
4265 ixgbe_dev_free_queues(dev);
4268 * Remove the VF MAC address ro ensure
4269 * that the VF traffic goes to the PF
4270 * after stop, close and detach of the VF
4272 ixgbevf_remove_mac_addr(dev, 0);
4275 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4277 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4278 struct ixgbe_vfta *shadow_vfta =
4279 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4280 int i = 0, j = 0, vfta = 0, mask = 1;
4282 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4283 vfta = shadow_vfta->vfta[i];
4286 for (j = 0; j < 32; j++) {
4288 ixgbe_set_vfta(hw, (i<<5)+j, 0,
4298 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4300 struct ixgbe_hw *hw =
4301 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4302 struct ixgbe_vfta *shadow_vfta =
4303 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4304 uint32_t vid_idx = 0;
4305 uint32_t vid_bit = 0;
4308 PMD_INIT_FUNC_TRACE();
4310 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4311 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4313 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4316 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4317 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4319 /* Save what we set and retore it after device reset */
4321 shadow_vfta->vfta[vid_idx] |= vid_bit;
4323 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4329 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4331 struct ixgbe_hw *hw =
4332 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4335 PMD_INIT_FUNC_TRACE();
4337 if (queue >= hw->mac.max_rx_queues)
4340 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4342 ctrl |= IXGBE_RXDCTL_VME;
4344 ctrl &= ~IXGBE_RXDCTL_VME;
4345 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4347 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4351 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4353 struct ixgbe_hw *hw =
4354 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4358 /* VF function only support hw strip feature, others are not support */
4359 if (mask & ETH_VLAN_STRIP_MASK) {
4360 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4362 for (i = 0; i < hw->mac.max_rx_queues; i++)
4363 ixgbevf_vlan_strip_queue_set(dev, i, on);
4368 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4372 /* we only need to do this if VMDq is enabled */
4373 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4374 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4375 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4383 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4385 uint32_t vector = 0;
4387 switch (hw->mac.mc_filter_type) {
4388 case 0: /* use bits [47:36] of the address */
4389 vector = ((uc_addr->addr_bytes[4] >> 4) |
4390 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4392 case 1: /* use bits [46:35] of the address */
4393 vector = ((uc_addr->addr_bytes[4] >> 3) |
4394 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4396 case 2: /* use bits [45:34] of the address */
4397 vector = ((uc_addr->addr_bytes[4] >> 2) |
4398 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4400 case 3: /* use bits [43:32] of the address */
4401 vector = ((uc_addr->addr_bytes[4]) |
4402 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4404 default: /* Invalid mc_filter_type */
4408 /* vector can only be 12-bits or boundary will be exceeded */
4414 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4422 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4423 const uint32_t ixgbe_uta_bit_shift = 5;
4424 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4425 const uint32_t bit1 = 0x1;
4427 struct ixgbe_hw *hw =
4428 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4429 struct ixgbe_uta_info *uta_info =
4430 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4432 /* The UTA table only exists on 82599 hardware and newer */
4433 if (hw->mac.type < ixgbe_mac_82599EB)
4436 vector = ixgbe_uta_vector(hw, mac_addr);
4437 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4438 uta_shift = vector & ixgbe_uta_bit_mask;
4440 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4444 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4446 uta_info->uta_in_use++;
4447 reg_val |= (bit1 << uta_shift);
4448 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4450 uta_info->uta_in_use--;
4451 reg_val &= ~(bit1 << uta_shift);
4452 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4455 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4457 if (uta_info->uta_in_use > 0)
4458 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4459 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4461 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4467 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4470 struct ixgbe_hw *hw =
4471 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4472 struct ixgbe_uta_info *uta_info =
4473 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4475 /* The UTA table only exists on 82599 hardware and newer */
4476 if (hw->mac.type < ixgbe_mac_82599EB)
4480 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4481 uta_info->uta_shadow[i] = ~0;
4482 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4485 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4486 uta_info->uta_shadow[i] = 0;
4487 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4495 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4497 uint32_t new_val = orig_val;
4499 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4500 new_val |= IXGBE_VMOLR_AUPE;
4501 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4502 new_val |= IXGBE_VMOLR_ROMPE;
4503 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4504 new_val |= IXGBE_VMOLR_ROPE;
4505 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4506 new_val |= IXGBE_VMOLR_BAM;
4507 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4508 new_val |= IXGBE_VMOLR_MPE;
4514 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4515 uint16_t rx_mask, uint8_t on)
4519 struct ixgbe_hw *hw =
4520 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4521 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4523 if (hw->mac.type == ixgbe_mac_82598EB) {
4524 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4525 " on 82599 hardware and newer");
4528 if (ixgbe_vmdq_mode_check(hw) < 0)
4531 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4538 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4544 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4548 const uint8_t bit1 = 0x1;
4550 struct ixgbe_hw *hw =
4551 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4553 if (ixgbe_vmdq_mode_check(hw) < 0)
4556 if (pool >= ETH_64_POOLS)
4559 /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4561 addr = IXGBE_VFRE(1);
4562 val = bit1 << (pool - 32);
4564 addr = IXGBE_VFRE(0);
4568 reg = IXGBE_READ_REG(hw, addr);
4575 IXGBE_WRITE_REG(hw, addr, reg);
4581 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4585 const uint8_t bit1 = 0x1;
4587 struct ixgbe_hw *hw =
4588 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4590 if (ixgbe_vmdq_mode_check(hw) < 0)
4593 if (pool >= ETH_64_POOLS)
4596 /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4598 addr = IXGBE_VFTE(1);
4599 val = bit1 << (pool - 32);
4601 addr = IXGBE_VFTE(0);
4605 reg = IXGBE_READ_REG(hw, addr);
4612 IXGBE_WRITE_REG(hw, addr, reg);
4618 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4619 uint64_t pool_mask, uint8_t vlan_on)
4623 struct ixgbe_hw *hw =
4624 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4626 if (ixgbe_vmdq_mode_check(hw) < 0)
4628 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4629 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4630 ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx,
4640 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
4641 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
4642 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
4643 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
4644 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4645 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4646 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4649 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4650 struct rte_eth_mirror_conf *mirror_conf,
4651 uint8_t rule_id, uint8_t on)
4653 uint32_t mr_ctl, vlvf;
4654 uint32_t mp_lsb = 0;
4655 uint32_t mv_msb = 0;
4656 uint32_t mv_lsb = 0;
4657 uint32_t mp_msb = 0;
4660 uint64_t vlan_mask = 0;
4662 const uint8_t pool_mask_offset = 32;
4663 const uint8_t vlan_mask_offset = 32;
4664 const uint8_t dst_pool_offset = 8;
4665 const uint8_t rule_mr_offset = 4;
4666 const uint8_t mirror_rule_mask = 0x0F;
4668 struct ixgbe_mirror_info *mr_info =
4669 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4670 struct ixgbe_hw *hw =
4671 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4672 uint8_t mirror_type = 0;
4674 if (ixgbe_vmdq_mode_check(hw) < 0)
4677 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4680 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4681 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4682 mirror_conf->rule_type);
4686 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4687 mirror_type |= IXGBE_MRCTL_VLME;
4688 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4689 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
4690 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4691 /* search vlan id related pool vlan filter index */
4692 reg_index = ixgbe_find_vlvf_slot(hw,
4693 mirror_conf->vlan.vlan_id[i],
4697 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4698 if ((vlvf & IXGBE_VLVF_VIEN) &&
4699 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4700 mirror_conf->vlan.vlan_id[i]))
4701 vlan_mask |= (1ULL << reg_index);
4708 mv_lsb = vlan_mask & 0xFFFFFFFF;
4709 mv_msb = vlan_mask >> vlan_mask_offset;
4711 mr_info->mr_conf[rule_id].vlan.vlan_mask =
4712 mirror_conf->vlan.vlan_mask;
4713 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4714 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4715 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4716 mirror_conf->vlan.vlan_id[i];
4721 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4722 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4723 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4728 * if enable pool mirror, write related pool mask register,if disable
4729 * pool mirror, clear PFMRVM register
4731 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4732 mirror_type |= IXGBE_MRCTL_VPME;
4734 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4735 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4736 mr_info->mr_conf[rule_id].pool_mask =
4737 mirror_conf->pool_mask;
4742 mr_info->mr_conf[rule_id].pool_mask = 0;
4745 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4746 mirror_type |= IXGBE_MRCTL_UPME;
4747 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4748 mirror_type |= IXGBE_MRCTL_DPME;
4750 /* read mirror control register and recalculate it */
4751 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4754 mr_ctl |= mirror_type;
4755 mr_ctl &= mirror_rule_mask;
4756 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4758 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4760 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4761 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4763 /* write mirrror control register */
4764 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4766 /* write pool mirrror control register */
4767 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4768 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4769 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4772 /* write VLAN mirrror control register */
4773 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4774 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4775 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4783 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4786 uint32_t lsb_val = 0;
4787 uint32_t msb_val = 0;
4788 const uint8_t rule_mr_offset = 4;
4790 struct ixgbe_hw *hw =
4791 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4792 struct ixgbe_mirror_info *mr_info =
4793 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4795 if (ixgbe_vmdq_mode_check(hw) < 0)
4798 memset(&mr_info->mr_conf[rule_id], 0,
4799 sizeof(struct rte_eth_mirror_conf));
4801 /* clear PFVMCTL register */
4802 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4804 /* clear pool mask register */
4805 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4806 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4808 /* clear vlan mask register */
4809 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4810 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4816 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4819 struct ixgbe_hw *hw =
4820 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4822 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4823 mask |= (1 << IXGBE_MISC_VEC_ID);
4824 RTE_SET_USED(queue_id);
4825 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4827 rte_intr_enable(&dev->pci_dev->intr_handle);
4833 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4836 struct ixgbe_hw *hw =
4837 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4839 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4840 mask &= ~(1 << IXGBE_MISC_VEC_ID);
4841 RTE_SET_USED(queue_id);
4842 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4848 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4851 struct ixgbe_hw *hw =
4852 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4853 struct ixgbe_interrupt *intr =
4854 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4856 if (queue_id < 16) {
4857 ixgbe_disable_intr(hw);
4858 intr->mask |= (1 << queue_id);
4859 ixgbe_enable_intr(dev);
4860 } else if (queue_id < 32) {
4861 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4862 mask &= (1 << queue_id);
4863 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4864 } else if (queue_id < 64) {
4865 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4866 mask &= (1 << (queue_id - 32));
4867 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4869 rte_intr_enable(&dev->pci_dev->intr_handle);
4875 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4878 struct ixgbe_hw *hw =
4879 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4880 struct ixgbe_interrupt *intr =
4881 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4883 if (queue_id < 16) {
4884 ixgbe_disable_intr(hw);
4885 intr->mask &= ~(1 << queue_id);
4886 ixgbe_enable_intr(dev);
4887 } else if (queue_id < 32) {
4888 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4889 mask &= ~(1 << queue_id);
4890 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4891 } else if (queue_id < 64) {
4892 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4893 mask &= ~(1 << (queue_id - 32));
4894 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4901 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4902 uint8_t queue, uint8_t msix_vector)
4906 if (direction == -1) {
4908 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4909 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4912 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4914 /* rx or tx cause */
4915 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4916 idx = ((16 * (queue & 1)) + (8 * direction));
4917 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4918 tmp &= ~(0xFF << idx);
4919 tmp |= (msix_vector << idx);
4920 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4925 * set the IVAR registers, mapping interrupt causes to vectors
4927 * pointer to ixgbe_hw struct
4929 * 0 for Rx, 1 for Tx, -1 for other causes
4931 * queue to map the corresponding interrupt to
4933 * the vector to map to the corresponding queue
4936 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4937 uint8_t queue, uint8_t msix_vector)
4941 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4942 if (hw->mac.type == ixgbe_mac_82598EB) {
4943 if (direction == -1)
4945 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4946 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4947 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4948 tmp |= (msix_vector << (8 * (queue & 0x3)));
4949 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4950 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4951 (hw->mac.type == ixgbe_mac_X540)) {
4952 if (direction == -1) {
4954 idx = ((queue & 1) * 8);
4955 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4956 tmp &= ~(0xFF << idx);
4957 tmp |= (msix_vector << idx);
4958 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4960 /* rx or tx causes */
4961 idx = ((16 * (queue & 1)) + (8 * direction));
4962 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4963 tmp &= ~(0xFF << idx);
4964 tmp |= (msix_vector << idx);
4965 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4971 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4973 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4974 struct ixgbe_hw *hw =
4975 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4977 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4979 /* Configure VF other cause ivar */
4980 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4982 /* won't configure msix register if no mapping is done
4983 * between intr vector and event fd.
4985 if (!rte_intr_dp_is_en(intr_handle))
4988 /* Configure all RX queues of VF */
4989 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4990 /* Force all queue use vector 0,
4991 * as IXGBE_VF_MAXMSIVECOTR = 1
4993 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4994 intr_handle->intr_vec[q_idx] = vector_idx;
4999 * Sets up the hardware to properly generate MSI-X interrupts
5001 * board private structure
5004 ixgbe_configure_msix(struct rte_eth_dev *dev)
5006 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5007 struct ixgbe_hw *hw =
5008 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5009 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5010 uint32_t vec = IXGBE_MISC_VEC_ID;
5014 /* won't configure msix register if no mapping is done
5015 * between intr vector and event fd
5017 if (!rte_intr_dp_is_en(intr_handle))
5020 if (rte_intr_allow_others(intr_handle))
5021 vec = base = IXGBE_RX_VEC_START;
5023 /* setup GPIE for MSI-x mode */
5024 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5025 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5026 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5027 /* auto clearing and auto setting corresponding bits in EIMS
5028 * when MSI-X interrupt is triggered
5030 if (hw->mac.type == ixgbe_mac_82598EB) {
5031 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5033 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5034 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5036 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5038 /* Populate the IVAR table and set the ITR values to the
5039 * corresponding register.
5041 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5043 /* by default, 1:1 mapping */
5044 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5045 intr_handle->intr_vec[queue_id] = vec;
5046 if (vec < base + intr_handle->nb_efd - 1)
5050 switch (hw->mac.type) {
5051 case ixgbe_mac_82598EB:
5052 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5055 case ixgbe_mac_82599EB:
5056 case ixgbe_mac_X540:
5057 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5062 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5063 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5065 /* set up to autoclear timer, and the vectors */
5066 mask = IXGBE_EIMS_ENABLE_MASK;
5067 mask &= ~(IXGBE_EIMS_OTHER |
5068 IXGBE_EIMS_MAILBOX |
5071 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5074 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5075 uint16_t queue_idx, uint16_t tx_rate)
5077 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5078 uint32_t rf_dec, rf_int;
5080 uint16_t link_speed = dev->data->dev_link.link_speed;
5082 if (queue_idx >= hw->mac.max_tx_queues)
5086 /* Calculate the rate factor values to set */
5087 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5088 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5089 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5091 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5092 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5093 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5094 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5100 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5101 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5104 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5105 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5106 IXGBE_MAX_JUMBO_FRAME_SIZE))
5107 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5108 IXGBE_MMW_SIZE_JUMBO_FRAME);
5110 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5111 IXGBE_MMW_SIZE_DEFAULT);
5113 /* Set RTTBCNRC of queue X */
5114 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5115 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5116 IXGBE_WRITE_FLUSH(hw);
5121 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
5122 uint16_t tx_rate, uint64_t q_msk)
5124 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5125 struct ixgbe_vf_info *vfinfo =
5126 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5127 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5128 uint32_t queue_stride =
5129 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5130 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
5131 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
5132 uint16_t total_rate = 0;
5134 if (queue_end >= hw->mac.max_tx_queues)
5137 if (vfinfo != NULL) {
5138 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
5141 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5143 total_rate += vfinfo[vf_idx].tx_rate[idx];
5148 /* Store tx_rate for this vf. */
5149 for (idx = 0; idx < nb_q_per_pool; idx++) {
5150 if (((uint64_t)0x1 << idx) & q_msk) {
5151 if (vfinfo[vf].tx_rate[idx] != tx_rate)
5152 vfinfo[vf].tx_rate[idx] = tx_rate;
5153 total_rate += tx_rate;
5157 if (total_rate > dev->data->dev_link.link_speed) {
5159 * Reset stored TX rate of the VF if it causes exceed
5162 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5166 /* Set RTTBCNRC of each queue/pool for vf X */
5167 for (; queue_idx <= queue_end; queue_idx++) {
5169 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5177 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5178 __attribute__((unused)) uint32_t index,
5179 __attribute__((unused)) uint32_t pool)
5181 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5185 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5186 * operation. Trap this case to avoid exhausting the [very limited]
5187 * set of PF resources used to store VF MAC addresses.
5189 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5191 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5194 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5198 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5200 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5201 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5202 struct ether_addr *mac_addr;
5207 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5208 * not support the deletion of a given MAC address.
5209 * Instead, it imposes to delete all MAC addresses, then to add again
5210 * all MAC addresses with the exception of the one to be deleted.
5212 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5215 * Add again all MAC addresses, with the exception of the deleted one
5216 * and of the permanent MAC address.
5218 for (i = 0, mac_addr = dev->data->mac_addrs;
5219 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5220 /* Skip the deleted MAC address */
5223 /* Skip NULL MAC addresses */
5224 if (is_zero_ether_addr(mac_addr))
5226 /* Skip the permanent MAC address */
5227 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5229 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5232 "Adding again MAC address "
5233 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5235 mac_addr->addr_bytes[0],
5236 mac_addr->addr_bytes[1],
5237 mac_addr->addr_bytes[2],
5238 mac_addr->addr_bytes[3],
5239 mac_addr->addr_bytes[4],
5240 mac_addr->addr_bytes[5],
5246 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5248 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5250 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5253 #define MAC_TYPE_FILTER_SUP(type) do {\
5254 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5255 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5256 (type) != ixgbe_mac_X550EM_a)\
5261 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5262 struct rte_eth_syn_filter *filter,
5265 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5268 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5271 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5274 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5276 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5277 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5279 if (filter->hig_pri)
5280 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5282 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5284 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5286 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5288 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5289 IXGBE_WRITE_FLUSH(hw);
5294 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5295 struct rte_eth_syn_filter *filter)
5297 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5298 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5300 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5301 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5302 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5309 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5310 enum rte_filter_op filter_op,
5313 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5316 MAC_TYPE_FILTER_SUP(hw->mac.type);
5318 if (filter_op == RTE_ETH_FILTER_NOP)
5322 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5327 switch (filter_op) {
5328 case RTE_ETH_FILTER_ADD:
5329 ret = ixgbe_syn_filter_set(dev,
5330 (struct rte_eth_syn_filter *)arg,
5333 case RTE_ETH_FILTER_DELETE:
5334 ret = ixgbe_syn_filter_set(dev,
5335 (struct rte_eth_syn_filter *)arg,
5338 case RTE_ETH_FILTER_GET:
5339 ret = ixgbe_syn_filter_get(dev,
5340 (struct rte_eth_syn_filter *)arg);
5343 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5352 static inline enum ixgbe_5tuple_protocol
5353 convert_protocol_type(uint8_t protocol_value)
5355 if (protocol_value == IPPROTO_TCP)
5356 return IXGBE_FILTER_PROTOCOL_TCP;
5357 else if (protocol_value == IPPROTO_UDP)
5358 return IXGBE_FILTER_PROTOCOL_UDP;
5359 else if (protocol_value == IPPROTO_SCTP)
5360 return IXGBE_FILTER_PROTOCOL_SCTP;
5362 return IXGBE_FILTER_PROTOCOL_NONE;
5366 * add a 5tuple filter
5369 * dev: Pointer to struct rte_eth_dev.
5370 * index: the index the filter allocates.
5371 * filter: ponter to the filter that will be added.
5372 * rx_queue: the queue id the filter assigned to.
5375 * - On success, zero.
5376 * - On failure, a negative value.
5379 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5380 struct ixgbe_5tuple_filter *filter)
5382 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5383 struct ixgbe_filter_info *filter_info =
5384 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5386 uint32_t ftqf, sdpqf;
5387 uint32_t l34timir = 0;
5388 uint8_t mask = 0xff;
5391 * look for an unused 5tuple filter index,
5392 * and insert the filter to list.
5394 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5395 idx = i / (sizeof(uint32_t) * NBBY);
5396 shift = i % (sizeof(uint32_t) * NBBY);
5397 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5398 filter_info->fivetuple_mask[idx] |= 1 << shift;
5400 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5406 if (i >= IXGBE_MAX_FTQF_FILTERS) {
5407 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5411 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5412 IXGBE_SDPQF_DSTPORT_SHIFT);
5413 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5415 ftqf = (uint32_t)(filter->filter_info.proto &
5416 IXGBE_FTQF_PROTOCOL_MASK);
5417 ftqf |= (uint32_t)((filter->filter_info.priority &
5418 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5419 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5420 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5421 if (filter->filter_info.dst_ip_mask == 0)
5422 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5423 if (filter->filter_info.src_port_mask == 0)
5424 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5425 if (filter->filter_info.dst_port_mask == 0)
5426 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5427 if (filter->filter_info.proto_mask == 0)
5428 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5429 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5430 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5431 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5433 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5434 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5435 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5436 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5438 l34timir |= IXGBE_L34T_IMIR_RESERVE;
5439 l34timir |= (uint32_t)(filter->queue <<
5440 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5441 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5446 * remove a 5tuple filter
5449 * dev: Pointer to struct rte_eth_dev.
5450 * filter: the pointer of the filter will be removed.
5453 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5454 struct ixgbe_5tuple_filter *filter)
5456 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5457 struct ixgbe_filter_info *filter_info =
5458 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5459 uint16_t index = filter->index;
5461 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5462 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5463 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5466 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5467 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5468 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5469 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5470 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5474 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5476 struct ixgbe_hw *hw;
5477 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5479 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5481 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5484 /* refuse mtu that requires the support of scattered packets when this
5485 * feature has not been enabled before.
5487 if (!dev->data->scattered_rx &&
5488 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5489 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5493 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5494 * request of the version 2.0 of the mailbox API.
5495 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5496 * of the mailbox API.
5497 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5498 * prior to 3.11.33 which contains the following change:
5499 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5501 ixgbevf_rlpml_set_vf(hw, max_frame);
5503 /* update max frame size */
5504 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5508 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
5509 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5513 static inline struct ixgbe_5tuple_filter *
5514 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5515 struct ixgbe_5tuple_filter_info *key)
5517 struct ixgbe_5tuple_filter *it;
5519 TAILQ_FOREACH(it, filter_list, entries) {
5520 if (memcmp(key, &it->filter_info,
5521 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5528 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5530 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5531 struct ixgbe_5tuple_filter_info *filter_info)
5533 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5534 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5535 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5538 switch (filter->dst_ip_mask) {
5540 filter_info->dst_ip_mask = 0;
5541 filter_info->dst_ip = filter->dst_ip;
5544 filter_info->dst_ip_mask = 1;
5547 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5551 switch (filter->src_ip_mask) {
5553 filter_info->src_ip_mask = 0;
5554 filter_info->src_ip = filter->src_ip;
5557 filter_info->src_ip_mask = 1;
5560 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5564 switch (filter->dst_port_mask) {
5566 filter_info->dst_port_mask = 0;
5567 filter_info->dst_port = filter->dst_port;
5570 filter_info->dst_port_mask = 1;
5573 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5577 switch (filter->src_port_mask) {
5579 filter_info->src_port_mask = 0;
5580 filter_info->src_port = filter->src_port;
5583 filter_info->src_port_mask = 1;
5586 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5590 switch (filter->proto_mask) {
5592 filter_info->proto_mask = 0;
5593 filter_info->proto =
5594 convert_protocol_type(filter->proto);
5597 filter_info->proto_mask = 1;
5600 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5604 filter_info->priority = (uint8_t)filter->priority;
5609 * add or delete a ntuple filter
5612 * dev: Pointer to struct rte_eth_dev.
5613 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5614 * add: if true, add filter, if false, remove filter
5617 * - On success, zero.
5618 * - On failure, a negative value.
5621 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5622 struct rte_eth_ntuple_filter *ntuple_filter,
5625 struct ixgbe_filter_info *filter_info =
5626 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5627 struct ixgbe_5tuple_filter_info filter_5tuple;
5628 struct ixgbe_5tuple_filter *filter;
5631 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5632 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5636 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5637 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5641 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5643 if (filter != NULL && add) {
5644 PMD_DRV_LOG(ERR, "filter exists.");
5647 if (filter == NULL && !add) {
5648 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5653 filter = rte_zmalloc("ixgbe_5tuple_filter",
5654 sizeof(struct ixgbe_5tuple_filter), 0);
5657 (void)rte_memcpy(&filter->filter_info,
5659 sizeof(struct ixgbe_5tuple_filter_info));
5660 filter->queue = ntuple_filter->queue;
5661 ret = ixgbe_add_5tuple_filter(dev, filter);
5667 ixgbe_remove_5tuple_filter(dev, filter);
5673 * get a ntuple filter
5676 * dev: Pointer to struct rte_eth_dev.
5677 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5680 * - On success, zero.
5681 * - On failure, a negative value.
5684 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5685 struct rte_eth_ntuple_filter *ntuple_filter)
5687 struct ixgbe_filter_info *filter_info =
5688 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5689 struct ixgbe_5tuple_filter_info filter_5tuple;
5690 struct ixgbe_5tuple_filter *filter;
5693 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5694 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5698 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5699 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5703 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5705 if (filter == NULL) {
5706 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5709 ntuple_filter->queue = filter->queue;
5714 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5715 * @dev: pointer to rte_eth_dev structure
5716 * @filter_op:operation will be taken.
5717 * @arg: a pointer to specific structure corresponding to the filter_op
5720 * - On success, zero.
5721 * - On failure, a negative value.
5724 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5725 enum rte_filter_op filter_op,
5728 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5731 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5733 if (filter_op == RTE_ETH_FILTER_NOP)
5737 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5742 switch (filter_op) {
5743 case RTE_ETH_FILTER_ADD:
5744 ret = ixgbe_add_del_ntuple_filter(dev,
5745 (struct rte_eth_ntuple_filter *)arg,
5748 case RTE_ETH_FILTER_DELETE:
5749 ret = ixgbe_add_del_ntuple_filter(dev,
5750 (struct rte_eth_ntuple_filter *)arg,
5753 case RTE_ETH_FILTER_GET:
5754 ret = ixgbe_get_ntuple_filter(dev,
5755 (struct rte_eth_ntuple_filter *)arg);
5758 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5766 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5771 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5772 if (filter_info->ethertype_filters[i] == ethertype &&
5773 (filter_info->ethertype_mask & (1 << i)))
5780 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5785 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5786 if (!(filter_info->ethertype_mask & (1 << i))) {
5787 filter_info->ethertype_mask |= 1 << i;
5788 filter_info->ethertype_filters[i] = ethertype;
5796 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5799 if (idx >= IXGBE_MAX_ETQF_FILTERS)
5801 filter_info->ethertype_mask &= ~(1 << idx);
5802 filter_info->ethertype_filters[idx] = 0;
5807 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5808 struct rte_eth_ethertype_filter *filter,
5811 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5812 struct ixgbe_filter_info *filter_info =
5813 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5818 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5821 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5822 filter->ether_type == ETHER_TYPE_IPv6) {
5823 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5824 " ethertype filter.", filter->ether_type);
5828 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5829 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5832 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5833 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5837 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5838 if (ret >= 0 && add) {
5839 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5840 filter->ether_type);
5843 if (ret < 0 && !add) {
5844 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5845 filter->ether_type);
5850 ret = ixgbe_ethertype_filter_insert(filter_info,
5851 filter->ether_type);
5853 PMD_DRV_LOG(ERR, "ethertype filters are full.");
5856 etqf = IXGBE_ETQF_FILTER_EN;
5857 etqf |= (uint32_t)filter->ether_type;
5858 etqs |= (uint32_t)((filter->queue <<
5859 IXGBE_ETQS_RX_QUEUE_SHIFT) &
5860 IXGBE_ETQS_RX_QUEUE);
5861 etqs |= IXGBE_ETQS_QUEUE_EN;
5863 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5867 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5868 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5869 IXGBE_WRITE_FLUSH(hw);
5875 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5876 struct rte_eth_ethertype_filter *filter)
5878 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5879 struct ixgbe_filter_info *filter_info =
5880 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5881 uint32_t etqf, etqs;
5884 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5886 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5887 filter->ether_type);
5891 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5892 if (etqf & IXGBE_ETQF_FILTER_EN) {
5893 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5894 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5896 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5897 IXGBE_ETQS_RX_QUEUE_SHIFT;
5904 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5905 * @dev: pointer to rte_eth_dev structure
5906 * @filter_op:operation will be taken.
5907 * @arg: a pointer to specific structure corresponding to the filter_op
5910 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5911 enum rte_filter_op filter_op,
5914 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5917 MAC_TYPE_FILTER_SUP(hw->mac.type);
5919 if (filter_op == RTE_ETH_FILTER_NOP)
5923 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5928 switch (filter_op) {
5929 case RTE_ETH_FILTER_ADD:
5930 ret = ixgbe_add_del_ethertype_filter(dev,
5931 (struct rte_eth_ethertype_filter *)arg,
5934 case RTE_ETH_FILTER_DELETE:
5935 ret = ixgbe_add_del_ethertype_filter(dev,
5936 (struct rte_eth_ethertype_filter *)arg,
5939 case RTE_ETH_FILTER_GET:
5940 ret = ixgbe_get_ethertype_filter(dev,
5941 (struct rte_eth_ethertype_filter *)arg);
5944 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5952 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5953 enum rte_filter_type filter_type,
5954 enum rte_filter_op filter_op,
5959 switch (filter_type) {
5960 case RTE_ETH_FILTER_NTUPLE:
5961 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5963 case RTE_ETH_FILTER_ETHERTYPE:
5964 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5966 case RTE_ETH_FILTER_SYN:
5967 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5969 case RTE_ETH_FILTER_FDIR:
5970 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5972 case RTE_ETH_FILTER_L2_TUNNEL:
5973 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5976 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5985 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5986 u8 **mc_addr_ptr, u32 *vmdq)
5991 mc_addr = *mc_addr_ptr;
5992 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5997 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5998 struct ether_addr *mc_addr_set,
5999 uint32_t nb_mc_addr)
6001 struct ixgbe_hw *hw;
6004 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6005 mc_addr_list = (u8 *)mc_addr_set;
6006 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6007 ixgbe_dev_addr_list_itr, TRUE);
6011 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6013 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6014 uint64_t systime_cycles;
6016 switch (hw->mac.type) {
6017 case ixgbe_mac_X550:
6018 case ixgbe_mac_X550EM_x:
6019 case ixgbe_mac_X550EM_a:
6020 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6021 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6022 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6026 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6027 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6031 return systime_cycles;
6035 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6037 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6038 uint64_t rx_tstamp_cycles;
6040 switch (hw->mac.type) {
6041 case ixgbe_mac_X550:
6042 case ixgbe_mac_X550EM_x:
6043 case ixgbe_mac_X550EM_a:
6044 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6045 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6046 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6050 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6051 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6052 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6056 return rx_tstamp_cycles;
6060 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6062 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6063 uint64_t tx_tstamp_cycles;
6065 switch (hw->mac.type) {
6066 case ixgbe_mac_X550:
6067 case ixgbe_mac_X550EM_x:
6068 case ixgbe_mac_X550EM_a:
6069 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6070 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6071 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6075 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6076 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6077 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6081 return tx_tstamp_cycles;
6085 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6087 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6088 struct ixgbe_adapter *adapter =
6089 (struct ixgbe_adapter *)dev->data->dev_private;
6090 struct rte_eth_link link;
6091 uint32_t incval = 0;
6094 /* Get current link speed. */
6095 memset(&link, 0, sizeof(link));
6096 ixgbe_dev_link_update(dev, 1);
6097 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6099 switch (link.link_speed) {
6100 case ETH_SPEED_NUM_100M:
6101 incval = IXGBE_INCVAL_100;
6102 shift = IXGBE_INCVAL_SHIFT_100;
6104 case ETH_SPEED_NUM_1G:
6105 incval = IXGBE_INCVAL_1GB;
6106 shift = IXGBE_INCVAL_SHIFT_1GB;
6108 case ETH_SPEED_NUM_10G:
6110 incval = IXGBE_INCVAL_10GB;
6111 shift = IXGBE_INCVAL_SHIFT_10GB;
6115 switch (hw->mac.type) {
6116 case ixgbe_mac_X550:
6117 case ixgbe_mac_X550EM_x:
6118 case ixgbe_mac_X550EM_a:
6119 /* Independent of link speed. */
6121 /* Cycles read will be interpreted as ns. */
6124 case ixgbe_mac_X540:
6125 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6127 case ixgbe_mac_82599EB:
6128 incval >>= IXGBE_INCVAL_SHIFT_82599;
6129 shift -= IXGBE_INCVAL_SHIFT_82599;
6130 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6131 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6134 /* Not supported. */
6138 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6139 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6140 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6142 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6143 adapter->systime_tc.cc_shift = shift;
6144 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6146 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6147 adapter->rx_tstamp_tc.cc_shift = shift;
6148 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6150 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6151 adapter->tx_tstamp_tc.cc_shift = shift;
6152 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6156 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6158 struct ixgbe_adapter *adapter =
6159 (struct ixgbe_adapter *)dev->data->dev_private;
6161 adapter->systime_tc.nsec += delta;
6162 adapter->rx_tstamp_tc.nsec += delta;
6163 adapter->tx_tstamp_tc.nsec += delta;
6169 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6172 struct ixgbe_adapter *adapter =
6173 (struct ixgbe_adapter *)dev->data->dev_private;
6175 ns = rte_timespec_to_ns(ts);
6176 /* Set the timecounters to a new value. */
6177 adapter->systime_tc.nsec = ns;
6178 adapter->rx_tstamp_tc.nsec = ns;
6179 adapter->tx_tstamp_tc.nsec = ns;
6185 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6187 uint64_t ns, systime_cycles;
6188 struct ixgbe_adapter *adapter =
6189 (struct ixgbe_adapter *)dev->data->dev_private;
6191 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6192 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6193 *ts = rte_ns_to_timespec(ns);
6199 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6201 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6205 /* Stop the timesync system time. */
6206 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6207 /* Reset the timesync system time value. */
6208 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6209 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6211 /* Enable system time for platforms where it isn't on by default. */
6212 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6213 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6214 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6216 ixgbe_start_timecounters(dev);
6218 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6219 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6221 IXGBE_ETQF_FILTER_EN |
6224 /* Enable timestamping of received PTP packets. */
6225 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6226 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6227 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6229 /* Enable timestamping of transmitted PTP packets. */
6230 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6231 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6232 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6234 IXGBE_WRITE_FLUSH(hw);
6240 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6242 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6245 /* Disable timestamping of transmitted PTP packets. */
6246 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6247 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6248 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6250 /* Disable timestamping of received PTP packets. */
6251 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6252 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6253 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6255 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6256 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6258 /* Stop incrementating the System Time registers. */
6259 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6265 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6266 struct timespec *timestamp,
6267 uint32_t flags __rte_unused)
6269 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6270 struct ixgbe_adapter *adapter =
6271 (struct ixgbe_adapter *)dev->data->dev_private;
6272 uint32_t tsync_rxctl;
6273 uint64_t rx_tstamp_cycles;
6276 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6277 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6280 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6281 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6282 *timestamp = rte_ns_to_timespec(ns);
6288 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6289 struct timespec *timestamp)
6291 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6292 struct ixgbe_adapter *adapter =
6293 (struct ixgbe_adapter *)dev->data->dev_private;
6294 uint32_t tsync_txctl;
6295 uint64_t tx_tstamp_cycles;
6298 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6299 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6302 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6303 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6304 *timestamp = rte_ns_to_timespec(ns);
6310 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6312 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6315 const struct reg_info *reg_group;
6316 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6317 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6319 while ((reg_group = reg_set[g_ind++]))
6320 count += ixgbe_regs_group_count(reg_group);
6326 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6330 const struct reg_info *reg_group;
6332 while ((reg_group = ixgbevf_regs[g_ind++]))
6333 count += ixgbe_regs_group_count(reg_group);
6339 ixgbe_get_regs(struct rte_eth_dev *dev,
6340 struct rte_dev_reg_info *regs)
6342 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6343 uint32_t *data = regs->data;
6346 const struct reg_info *reg_group;
6347 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6348 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6351 regs->length = ixgbe_get_reg_length(dev);
6352 regs->width = sizeof(uint32_t);
6356 /* Support only full register dump */
6357 if ((regs->length == 0) ||
6358 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6359 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6361 while ((reg_group = reg_set[g_ind++]))
6362 count += ixgbe_read_regs_group(dev, &data[count],
6371 ixgbevf_get_regs(struct rte_eth_dev *dev,
6372 struct rte_dev_reg_info *regs)
6374 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6375 uint32_t *data = regs->data;
6378 const struct reg_info *reg_group;
6381 regs->length = ixgbevf_get_reg_length(dev);
6382 regs->width = sizeof(uint32_t);
6386 /* Support only full register dump */
6387 if ((regs->length == 0) ||
6388 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6389 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6391 while ((reg_group = ixgbevf_regs[g_ind++]))
6392 count += ixgbe_read_regs_group(dev, &data[count],
6401 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6403 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6405 /* Return unit is byte count */
6406 return hw->eeprom.word_size * 2;
6410 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6411 struct rte_dev_eeprom_info *in_eeprom)
6413 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6414 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6415 uint16_t *data = in_eeprom->data;
6418 first = in_eeprom->offset >> 1;
6419 length = in_eeprom->length >> 1;
6420 if ((first > hw->eeprom.word_size) ||
6421 ((first + length) > hw->eeprom.word_size))
6424 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6426 return eeprom->ops.read_buffer(hw, first, length, data);
6430 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6431 struct rte_dev_eeprom_info *in_eeprom)
6433 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6434 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6435 uint16_t *data = in_eeprom->data;
6438 first = in_eeprom->offset >> 1;
6439 length = in_eeprom->length >> 1;
6440 if ((first > hw->eeprom.word_size) ||
6441 ((first + length) > hw->eeprom.word_size))
6444 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6446 return eeprom->ops.write_buffer(hw, first, length, data);
6450 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6452 case ixgbe_mac_X550:
6453 case ixgbe_mac_X550EM_x:
6454 case ixgbe_mac_X550EM_a:
6455 return ETH_RSS_RETA_SIZE_512;
6456 case ixgbe_mac_X550_vf:
6457 case ixgbe_mac_X550EM_x_vf:
6458 case ixgbe_mac_X550EM_a_vf:
6459 return ETH_RSS_RETA_SIZE_64;
6461 return ETH_RSS_RETA_SIZE_128;
6466 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6468 case ixgbe_mac_X550:
6469 case ixgbe_mac_X550EM_x:
6470 case ixgbe_mac_X550EM_a:
6471 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6472 return IXGBE_RETA(reta_idx >> 2);
6474 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6475 case ixgbe_mac_X550_vf:
6476 case ixgbe_mac_X550EM_x_vf:
6477 case ixgbe_mac_X550EM_a_vf:
6478 return IXGBE_VFRETA(reta_idx >> 2);
6480 return IXGBE_RETA(reta_idx >> 2);
6485 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6487 case ixgbe_mac_X550_vf:
6488 case ixgbe_mac_X550EM_x_vf:
6489 case ixgbe_mac_X550EM_a_vf:
6490 return IXGBE_VFMRQC;
6497 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6499 case ixgbe_mac_X550_vf:
6500 case ixgbe_mac_X550EM_x_vf:
6501 case ixgbe_mac_X550EM_a_vf:
6502 return IXGBE_VFRSSRK(i);
6504 return IXGBE_RSSRK(i);
6509 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6511 case ixgbe_mac_82599_vf:
6512 case ixgbe_mac_X540_vf:
6520 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6521 struct rte_eth_dcb_info *dcb_info)
6523 struct ixgbe_dcb_config *dcb_config =
6524 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6525 struct ixgbe_dcb_tc_config *tc;
6528 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6529 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6531 dcb_info->nb_tcs = 1;
6533 if (dcb_config->vt_mode) { /* vt is enabled*/
6534 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6535 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6536 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6537 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6538 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6539 for (j = 0; j < dcb_info->nb_tcs; j++) {
6540 dcb_info->tc_queue.tc_rxq[i][j].base =
6541 i * dcb_info->nb_tcs + j;
6542 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6543 dcb_info->tc_queue.tc_txq[i][j].base =
6544 i * dcb_info->nb_tcs + j;
6545 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6548 } else { /* vt is disabled*/
6549 struct rte_eth_dcb_rx_conf *rx_conf =
6550 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6551 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6552 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6553 if (dcb_info->nb_tcs == ETH_4_TCS) {
6554 for (i = 0; i < dcb_info->nb_tcs; i++) {
6555 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6556 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6558 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6559 dcb_info->tc_queue.tc_txq[0][1].base = 64;
6560 dcb_info->tc_queue.tc_txq[0][2].base = 96;
6561 dcb_info->tc_queue.tc_txq[0][3].base = 112;
6562 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6563 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6564 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6565 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6566 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6567 for (i = 0; i < dcb_info->nb_tcs; i++) {
6568 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6569 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6571 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6572 dcb_info->tc_queue.tc_txq[0][1].base = 32;
6573 dcb_info->tc_queue.tc_txq[0][2].base = 64;
6574 dcb_info->tc_queue.tc_txq[0][3].base = 80;
6575 dcb_info->tc_queue.tc_txq[0][4].base = 96;
6576 dcb_info->tc_queue.tc_txq[0][5].base = 104;
6577 dcb_info->tc_queue.tc_txq[0][6].base = 112;
6578 dcb_info->tc_queue.tc_txq[0][7].base = 120;
6579 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6580 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6581 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6582 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6583 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6584 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6585 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6586 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6589 for (i = 0; i < dcb_info->nb_tcs; i++) {
6590 tc = &dcb_config->tc_config[i];
6591 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6596 /* Update e-tag ether type */
6598 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6599 uint16_t ether_type)
6601 uint32_t etag_etype;
6603 if (hw->mac.type != ixgbe_mac_X550 &&
6604 hw->mac.type != ixgbe_mac_X550EM_x &&
6605 hw->mac.type != ixgbe_mac_X550EM_a) {
6609 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6610 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6611 etag_etype |= ether_type;
6612 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6613 IXGBE_WRITE_FLUSH(hw);
6618 /* Config l2 tunnel ether type */
6620 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6621 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6624 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6626 if (l2_tunnel == NULL)
6629 switch (l2_tunnel->l2_tunnel_type) {
6630 case RTE_L2_TUNNEL_TYPE_E_TAG:
6631 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6634 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6642 /* Enable e-tag tunnel */
6644 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6646 uint32_t etag_etype;
6648 if (hw->mac.type != ixgbe_mac_X550 &&
6649 hw->mac.type != ixgbe_mac_X550EM_x &&
6650 hw->mac.type != ixgbe_mac_X550EM_a) {
6654 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6655 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6656 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6657 IXGBE_WRITE_FLUSH(hw);
6662 /* Enable l2 tunnel */
6664 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6665 enum rte_eth_tunnel_type l2_tunnel_type)
6668 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6670 switch (l2_tunnel_type) {
6671 case RTE_L2_TUNNEL_TYPE_E_TAG:
6672 ret = ixgbe_e_tag_enable(hw);
6675 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6683 /* Disable e-tag tunnel */
6685 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6687 uint32_t etag_etype;
6689 if (hw->mac.type != ixgbe_mac_X550 &&
6690 hw->mac.type != ixgbe_mac_X550EM_x &&
6691 hw->mac.type != ixgbe_mac_X550EM_a) {
6695 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6696 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6697 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6698 IXGBE_WRITE_FLUSH(hw);
6703 /* Disable l2 tunnel */
6705 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6706 enum rte_eth_tunnel_type l2_tunnel_type)
6709 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6711 switch (l2_tunnel_type) {
6712 case RTE_L2_TUNNEL_TYPE_E_TAG:
6713 ret = ixgbe_e_tag_disable(hw);
6716 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6725 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6726 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6729 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6730 uint32_t i, rar_entries;
6731 uint32_t rar_low, rar_high;
6733 if (hw->mac.type != ixgbe_mac_X550 &&
6734 hw->mac.type != ixgbe_mac_X550EM_x &&
6735 hw->mac.type != ixgbe_mac_X550EM_a) {
6739 rar_entries = ixgbe_get_num_rx_addrs(hw);
6741 for (i = 1; i < rar_entries; i++) {
6742 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6743 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6744 if ((rar_high & IXGBE_RAH_AV) &&
6745 (rar_high & IXGBE_RAH_ADTYPE) &&
6746 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6747 l2_tunnel->tunnel_id)) {
6748 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6749 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6751 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6761 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6762 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6765 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6766 uint32_t i, rar_entries;
6767 uint32_t rar_low, rar_high;
6769 if (hw->mac.type != ixgbe_mac_X550 &&
6770 hw->mac.type != ixgbe_mac_X550EM_x &&
6771 hw->mac.type != ixgbe_mac_X550EM_a) {
6775 /* One entry for one tunnel. Try to remove potential existing entry. */
6776 ixgbe_e_tag_filter_del(dev, l2_tunnel);
6778 rar_entries = ixgbe_get_num_rx_addrs(hw);
6780 for (i = 1; i < rar_entries; i++) {
6781 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6782 if (rar_high & IXGBE_RAH_AV) {
6785 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6786 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6787 rar_low = l2_tunnel->tunnel_id;
6789 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6790 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6796 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6797 " Please remove a rule before adding a new one.");
6801 /* Add l2 tunnel filter */
6803 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6804 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6808 switch (l2_tunnel->l2_tunnel_type) {
6809 case RTE_L2_TUNNEL_TYPE_E_TAG:
6810 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6813 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6821 /* Delete l2 tunnel filter */
6823 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6824 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6828 switch (l2_tunnel->l2_tunnel_type) {
6829 case RTE_L2_TUNNEL_TYPE_E_TAG:
6830 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6833 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6842 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6843 * @dev: pointer to rte_eth_dev structure
6844 * @filter_op:operation will be taken.
6845 * @arg: a pointer to specific structure corresponding to the filter_op
6848 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6849 enum rte_filter_op filter_op,
6854 if (filter_op == RTE_ETH_FILTER_NOP)
6858 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6863 switch (filter_op) {
6864 case RTE_ETH_FILTER_ADD:
6865 ret = ixgbe_dev_l2_tunnel_filter_add
6867 (struct rte_eth_l2_tunnel_conf *)arg);
6869 case RTE_ETH_FILTER_DELETE:
6870 ret = ixgbe_dev_l2_tunnel_filter_del
6872 (struct rte_eth_l2_tunnel_conf *)arg);
6875 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6883 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6887 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6889 if (hw->mac.type != ixgbe_mac_X550 &&
6890 hw->mac.type != ixgbe_mac_X550EM_x &&
6891 hw->mac.type != ixgbe_mac_X550EM_a) {
6895 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6896 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6898 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6899 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6904 /* Enable l2 tunnel forwarding */
6906 ixgbe_dev_l2_tunnel_forwarding_enable
6907 (struct rte_eth_dev *dev,
6908 enum rte_eth_tunnel_type l2_tunnel_type)
6912 switch (l2_tunnel_type) {
6913 case RTE_L2_TUNNEL_TYPE_E_TAG:
6914 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6917 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6925 /* Disable l2 tunnel forwarding */
6927 ixgbe_dev_l2_tunnel_forwarding_disable
6928 (struct rte_eth_dev *dev,
6929 enum rte_eth_tunnel_type l2_tunnel_type)
6933 switch (l2_tunnel_type) {
6934 case RTE_L2_TUNNEL_TYPE_E_TAG:
6935 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6938 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6947 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6948 struct rte_eth_l2_tunnel_conf *l2_tunnel,
6952 uint32_t vmtir, vmvir;
6953 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6955 if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6957 "VF id %u should be less than %u",
6959 dev->pci_dev->max_vfs);
6963 if (hw->mac.type != ixgbe_mac_X550 &&
6964 hw->mac.type != ixgbe_mac_X550EM_x &&
6965 hw->mac.type != ixgbe_mac_X550EM_a) {
6970 vmtir = l2_tunnel->tunnel_id;
6974 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6976 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6977 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6979 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6980 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6985 /* Enable l2 tunnel tag insertion */
6987 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6988 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6992 switch (l2_tunnel->l2_tunnel_type) {
6993 case RTE_L2_TUNNEL_TYPE_E_TAG:
6994 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6997 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7005 /* Disable l2 tunnel tag insertion */
7007 ixgbe_dev_l2_tunnel_insertion_disable
7008 (struct rte_eth_dev *dev,
7009 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7013 switch (l2_tunnel->l2_tunnel_type) {
7014 case RTE_L2_TUNNEL_TYPE_E_TAG:
7015 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7018 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7027 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7032 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7034 if (hw->mac.type != ixgbe_mac_X550 &&
7035 hw->mac.type != ixgbe_mac_X550EM_x &&
7036 hw->mac.type != ixgbe_mac_X550EM_a) {
7040 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7042 qde |= IXGBE_QDE_STRIP_TAG;
7044 qde &= ~IXGBE_QDE_STRIP_TAG;
7045 qde &= ~IXGBE_QDE_READ;
7046 qde |= IXGBE_QDE_WRITE;
7047 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7052 /* Enable l2 tunnel tag stripping */
7054 ixgbe_dev_l2_tunnel_stripping_enable
7055 (struct rte_eth_dev *dev,
7056 enum rte_eth_tunnel_type l2_tunnel_type)
7060 switch (l2_tunnel_type) {
7061 case RTE_L2_TUNNEL_TYPE_E_TAG:
7062 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7065 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7073 /* Disable l2 tunnel tag stripping */
7075 ixgbe_dev_l2_tunnel_stripping_disable
7076 (struct rte_eth_dev *dev,
7077 enum rte_eth_tunnel_type l2_tunnel_type)
7081 switch (l2_tunnel_type) {
7082 case RTE_L2_TUNNEL_TYPE_E_TAG:
7083 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7086 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7094 /* Enable/disable l2 tunnel offload functions */
7096 ixgbe_dev_l2_tunnel_offload_set
7097 (struct rte_eth_dev *dev,
7098 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7104 if (l2_tunnel == NULL)
7108 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7110 ret = ixgbe_dev_l2_tunnel_enable(
7112 l2_tunnel->l2_tunnel_type);
7114 ret = ixgbe_dev_l2_tunnel_disable(
7116 l2_tunnel->l2_tunnel_type);
7119 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7121 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7125 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7130 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7132 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7134 l2_tunnel->l2_tunnel_type);
7136 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7138 l2_tunnel->l2_tunnel_type);
7141 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7143 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7145 l2_tunnel->l2_tunnel_type);
7147 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7149 l2_tunnel->l2_tunnel_type);
7156 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7159 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7160 IXGBE_WRITE_FLUSH(hw);
7165 /* There's only one register for VxLAN UDP port.
7166 * So, we cannot add several ports. Will update it.
7169 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7173 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7177 return ixgbe_update_vxlan_port(hw, port);
7180 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7181 * UDP port, it must have a value.
7182 * So, will reset it to the original value 0.
7185 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7190 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7192 if (cur_port != port) {
7193 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7197 return ixgbe_update_vxlan_port(hw, 0);
7200 /* Add UDP tunneling port */
7202 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7203 struct rte_eth_udp_tunnel *udp_tunnel)
7206 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7208 if (hw->mac.type != ixgbe_mac_X550 &&
7209 hw->mac.type != ixgbe_mac_X550EM_x &&
7210 hw->mac.type != ixgbe_mac_X550EM_a) {
7214 if (udp_tunnel == NULL)
7217 switch (udp_tunnel->prot_type) {
7218 case RTE_TUNNEL_TYPE_VXLAN:
7219 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7222 case RTE_TUNNEL_TYPE_GENEVE:
7223 case RTE_TUNNEL_TYPE_TEREDO:
7224 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7229 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7237 /* Remove UDP tunneling port */
7239 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7240 struct rte_eth_udp_tunnel *udp_tunnel)
7243 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7245 if (hw->mac.type != ixgbe_mac_X550 &&
7246 hw->mac.type != ixgbe_mac_X550EM_x &&
7247 hw->mac.type != ixgbe_mac_X550EM_a) {
7251 if (udp_tunnel == NULL)
7254 switch (udp_tunnel->prot_type) {
7255 case RTE_TUNNEL_TYPE_VXLAN:
7256 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7258 case RTE_TUNNEL_TYPE_GENEVE:
7259 case RTE_TUNNEL_TYPE_TEREDO:
7260 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7264 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7272 /* ixgbevf_update_xcast_mode - Update Multicast mode
7273 * @hw: pointer to the HW structure
7274 * @netdev: pointer to net device structure
7275 * @xcast_mode: new multicast mode
7277 * Updates the Multicast Mode of VF.
7279 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
7282 struct ixgbe_mbx_info *mbx = &hw->mbx;
7286 switch (hw->api_version) {
7287 case ixgbe_mbox_api_12:
7293 msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7294 msgbuf[1] = xcast_mode;
7296 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7300 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7304 msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7305 if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7312 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7314 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7316 ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7320 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7322 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7324 ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7327 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7329 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7332 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7335 /* PF reset VF event */
7336 if (in_msg == IXGBE_PF_CONTROL_MSG)
7337 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET);
7341 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7344 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7345 struct ixgbe_interrupt *intr =
7346 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7347 ixgbevf_intr_disable(hw);
7349 /* read-on-clear nic registers here */
7350 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7353 /* only one misc vector supported - mailbox */
7354 eicr &= IXGBE_VTEICR_MASK;
7355 if (eicr == IXGBE_MISC_VEC_ID)
7356 intr->flags |= IXGBE_FLAG_MAILBOX;
7362 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7364 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7365 struct ixgbe_interrupt *intr =
7366 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7368 if (intr->flags & IXGBE_FLAG_MAILBOX) {
7369 ixgbevf_mbx_process(dev);
7370 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7373 ixgbevf_intr_enable(hw);
7379 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7382 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7384 ixgbevf_dev_interrupt_get_status(dev);
7385 ixgbevf_dev_interrupt_action(dev);
7388 DRIVER_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
7389 DRIVER_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
7390 DRIVER_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
7391 DRIVER_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);