drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71
  72 /*
  73  * High threshold controlling when to start sending XOFF frames. Must be at
  74  * least 8 bytes less than receive packet buffer size. This value is in units
  75  * of 1024 bytes.
  76  */
  77 #define IXGBE_FC_HI    0x80
  78
  79 /*
  80  * Low threshold controlling when to start sending XON frames. This value is
  81  * in units of 1024 bytes.
  82  */
  83 #define IXGBE_FC_LO    0x40
  84
  85 /* Timer value included in XOFF frames. */
  86 #define IXGBE_FC_PAUSE 0x680
  87
  88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  89 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  90 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  91
  92 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  93 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  94
  95 /*
  96  *  Default values for RX/TX configuration
  97  */
  98 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  99 #define IXGBE_DEFAULT_RX_PTHRESH      8
 100 #define IXGBE_DEFAULT_RX_HTHRESH      8
 101 #define IXGBE_DEFAULT_RX_WTHRESH      0
 102
 103 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 104 #define IXGBE_DEFAULT_TX_PTHRESH      32
 105 #define IXGBE_DEFAULT_TX_HTHRESH      0
 106 #define IXGBE_DEFAULT_TX_WTHRESH      0
 107 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 108
 109 /* Bit shift and mask */
 110 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 111 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 112 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 113 #define IXGBE_8_BIT_MASK   UINT8_MAX
 114
 115 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 116
 117 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 118
 119 #define IXGBE_HKEY_MAX_INDEX 10
 120
 121 /* Additional timesync values. */
 122 #define IXGBE_TIMINCA_16NS_SHIFT 24
 123 #define IXGBE_TIMINCA_INCVALUE   16000000
 124 #define IXGBE_TIMINCA_INIT       ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
 125                                   | IXGBE_TIMINCA_INCVALUE)
 126
 127 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 128 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 129 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 130 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 131 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 132 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 133 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 134 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 135 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 136 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 137 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 138 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 139                                 int wait_to_complete);
 140 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 141                                 struct rte_eth_stats *stats);
 142 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 143 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 144                                              uint16_t queue_id,
 145                                              uint8_t stat_idx,
 146                                              uint8_t is_rx);
 147 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 148                                struct rte_eth_dev_info *dev_info);
 149 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 150                                  struct rte_eth_dev_info *dev_info);
 151 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 152
 153 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 154                 uint16_t vlan_id, int on);
 155 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 156 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 157                 uint16_t queue, bool on);
 158 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 159                 int on);
 160 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 161 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 162 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 163 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 164 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 165
 166 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 167 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 168 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 169                                struct rte_eth_fc_conf *fc_conf);
 170 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 171                                struct rte_eth_fc_conf *fc_conf);
 172 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 173                 struct rte_eth_pfc_conf *pfc_conf);
 174 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 175                         struct rte_eth_rss_reta_entry64 *reta_conf,
 176                         uint16_t reta_size);
 177 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 178                         struct rte_eth_rss_reta_entry64 *reta_conf,
 179                         uint16_t reta_size);
 180 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 181 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 182 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 183 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 184 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 185                 void *param);
 186 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 187 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 188                 uint32_t index, uint32_t pool);
 189 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 190 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 191                                            struct ether_addr *mac_addr);
 192 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 193
 194 /* For Virtual Function support */
 195 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 196 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 197 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 198 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 199 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 200 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 201 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 202                 struct rte_eth_stats *stats);
 203 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 204 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 205                 uint16_t vlan_id, int on);
 206 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 207                 uint16_t queue, int on);
 208 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 209 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 210
 211 /* For Eth VMDQ APIs support */
 212 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 213                 ether_addr* mac_addr,uint8_t on);
 214 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 215 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 216                 uint16_t rx_mask, uint8_t on);
 217 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 218 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 219 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 220                 uint64_t pool_mask,uint8_t vlan_on);
 221 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 222                 struct rte_eth_mirror_conf *mirror_conf,
 223                 uint8_t rule_id, uint8_t on);
 224 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 225                 uint8_t rule_id);
 226
 227 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 228                 uint16_t queue_idx, uint16_t tx_rate);
 229 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 230                 uint16_t tx_rate, uint64_t q_msk);
 231
 232 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 233                                  struct ether_addr *mac_addr,
 234                                  uint32_t index, uint32_t pool);
 235 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 236 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 237                                              struct ether_addr *mac_addr);
 238 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 239                         struct rte_eth_syn_filter *filter,
 240                         bool add);
 241 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 242                         struct rte_eth_syn_filter *filter);
 243 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 244                         enum rte_filter_op filter_op,
 245                         void *arg);
 246 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 247                         struct ixgbe_5tuple_filter *filter);
 248 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 249                         struct ixgbe_5tuple_filter *filter);
 250 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 251                         struct rte_eth_ntuple_filter *filter,
 252                         bool add);
 253 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 254                                 enum rte_filter_op filter_op,
 255                                 void *arg);
 256 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 257                         struct rte_eth_ntuple_filter *filter);
 258 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 259                         struct rte_eth_ethertype_filter *filter,
 260                         bool add);
 261 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 262                                 enum rte_filter_op filter_op,
 263                                 void *arg);
 264 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 265                         struct rte_eth_ethertype_filter *filter);
 266 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 267                      enum rte_filter_type filter_type,
 268                      enum rte_filter_op filter_op,
 269                      void *arg);
 270 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 271
 272 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 273                                       struct ether_addr *mc_addr_set,
 274                                       uint32_t nb_mc_addr);
 275
 276 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 277 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 278 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 279                                             struct timespec *timestamp,
 280                                             uint32_t flags);
 281 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 282                                             struct timespec *timestamp);
 283
 284 /*
 285  * Define VF Stats MACRO for Non "cleared on read" register
 286  */
 287 #define UPDATE_VF_STAT(reg, last, cur)                          \
 288 {                                                               \
 289         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 290         cur += latest - last;                                   \
 291         last = latest;                                          \
 292 }
 293
 294 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 295 {                                                                \
 296         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 297         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 298         u64 latest = ((new_msb << 32) | new_lsb);                \
 299         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 300         last = latest;                                           \
 301 }
 302
 303 #define IXGBE_SET_HWSTRIP(h, q) do{\
 304                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 305                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 306                 (h)->bitmap[idx] |= 1 << bit;\
 307         }while(0)
 308
 309 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 310                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 311                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 312                 (h)->bitmap[idx] &= ~(1 << bit);\
 313         }while(0)
 314
 315 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 316                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 317                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 318                 (r) = (h)->bitmap[idx] >> bit & 1;\
 319         }while(0)
 320
 321 /*
 322  * The set of PCI devices this driver supports
 323  */
 324 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 325
 326 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 327 #include "rte_pci_dev_ids.h"
 328
 329 { .vendor_id = 0, /* sentinel */ },
 330 };
 331
 332
 333 /*
 334  * The set of PCI devices this driver supports (for 82599 VF)
 335  */
 336 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 337
 338 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 339 #include "rte_pci_dev_ids.h"
 340 { .vendor_id = 0, /* sentinel */ },
 341
 342 };
 343
 344 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 345         .dev_configure        = ixgbe_dev_configure,
 346         .dev_start            = ixgbe_dev_start,
 347         .dev_stop             = ixgbe_dev_stop,
 348         .dev_set_link_up    = ixgbe_dev_set_link_up,
 349         .dev_set_link_down  = ixgbe_dev_set_link_down,
 350         .dev_close            = ixgbe_dev_close,
 351         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 352         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 353         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 354         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 355         .link_update          = ixgbe_dev_link_update,
 356         .stats_get            = ixgbe_dev_stats_get,
 357         .stats_reset          = ixgbe_dev_stats_reset,
 358         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 359         .dev_infos_get        = ixgbe_dev_info_get,
 360         .mtu_set              = ixgbe_dev_mtu_set,
 361         .vlan_filter_set      = ixgbe_vlan_filter_set,
 362         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 363         .vlan_offload_set     = ixgbe_vlan_offload_set,
 364         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 365         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 366         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 367         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 368         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 369         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 370         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 371         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 372         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 373         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 374         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 375         .dev_led_on           = ixgbe_dev_led_on,
 376         .dev_led_off          = ixgbe_dev_led_off,
 377         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 378         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 379         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 380         .mac_addr_add         = ixgbe_add_rar,
 381         .mac_addr_remove      = ixgbe_remove_rar,
 382         .mac_addr_set         = ixgbe_set_default_mac_addr,
 383         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 384         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 385         .mirror_rule_set      = ixgbe_mirror_rule_set,
 386         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 387         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 388         .set_vf_rx            = ixgbe_set_pool_rx,
 389         .set_vf_tx            = ixgbe_set_pool_tx,
 390         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 391         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 392         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 393         .reta_update          = ixgbe_dev_rss_reta_update,
 394         .reta_query           = ixgbe_dev_rss_reta_query,
 395 #ifdef RTE_NIC_BYPASS
 396         .bypass_init          = ixgbe_bypass_init,
 397         .bypass_state_set     = ixgbe_bypass_state_store,
 398         .bypass_state_show    = ixgbe_bypass_state_show,
 399         .bypass_event_set     = ixgbe_bypass_event_store,
 400         .bypass_event_show    = ixgbe_bypass_event_show,
 401         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 402         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 403         .bypass_ver_show      = ixgbe_bypass_ver_show,
 404         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 405 #endif /* RTE_NIC_BYPASS */
 406         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 407         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 408         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 409         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 410         .timesync_enable      = ixgbe_timesync_enable,
 411         .timesync_disable     = ixgbe_timesync_disable,
 412         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 413         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 414 };
 415
 416 /*
 417  * dev_ops for virtual function, bare necessities for basic vf
 418  * operation have been implemented
 419  */
 420 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 421         .dev_configure        = ixgbevf_dev_configure,
 422         .dev_start            = ixgbevf_dev_start,
 423         .dev_stop             = ixgbevf_dev_stop,
 424         .link_update          = ixgbe_dev_link_update,
 425         .stats_get            = ixgbevf_dev_stats_get,
 426         .stats_reset          = ixgbevf_dev_stats_reset,
 427         .dev_close            = ixgbevf_dev_close,
 428         .dev_infos_get        = ixgbevf_dev_info_get,
 429         .mtu_set              = ixgbevf_dev_set_mtu,
 430         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 431         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 432         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 433         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 434         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 435         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 436         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 437         .mac_addr_add         = ixgbevf_add_mac_addr,
 438         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 439         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 440         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 441 };
 442
 443 /**
 444  * Atomically reads the link status information from global
 445  * structure rte_eth_dev.
 446  *
 447  * @param dev
 448  *   - Pointer to the structure rte_eth_dev to read from.
 449  *   - Pointer to the buffer to be saved with the link status.
 450  *
 451  * @return
 452  *   - On success, zero.
 453  *   - On failure, negative value.
 454  */
 455 static inline int
 456 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 457                                 struct rte_eth_link *link)
 458 {
 459         struct rte_eth_link *dst = link;
 460         struct rte_eth_link *src = &(dev->data->dev_link);
 461
 462         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 463                                         *(uint64_t *)src) == 0)
 464                 return -1;
 465
 466         return 0;
 467 }
 468
 469 /**
 470  * Atomically writes the link status information into global
 471  * structure rte_eth_dev.
 472  *
 473  * @param dev
 474  *   - Pointer to the structure rte_eth_dev to read from.
 475  *   - Pointer to the buffer to be saved with the link status.
 476  *
 477  * @return
 478  *   - On success, zero.
 479  *   - On failure, negative value.
 480  */
 481 static inline int
 482 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 483                                 struct rte_eth_link *link)
 484 {
 485         struct rte_eth_link *dst = &(dev->data->dev_link);
 486         struct rte_eth_link *src = link;
 487
 488         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 489                                         *(uint64_t *)src) == 0)
 490                 return -1;
 491
 492         return 0;
 493 }
 494
 495 /*
 496  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 497  */
 498 static inline int
 499 ixgbe_is_sfp(struct ixgbe_hw *hw)
 500 {
 501         switch (hw->phy.type) {
 502         case ixgbe_phy_sfp_avago:
 503         case ixgbe_phy_sfp_ftl:
 504         case ixgbe_phy_sfp_intel:
 505         case ixgbe_phy_sfp_unknown:
 506         case ixgbe_phy_sfp_passive_tyco:
 507         case ixgbe_phy_sfp_passive_unknown:
 508                 return 1;
 509         default:
 510                 return 0;
 511         }
 512 }
 513
 514 static inline int32_t
 515 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 516 {
 517         uint32_t ctrl_ext;
 518         int32_t status;
 519
 520         status = ixgbe_reset_hw(hw);
 521
 522         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 523         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 524         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 525         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 526         IXGBE_WRITE_FLUSH(hw);
 527
 528         return status;
 529 }
 530
 531 static inline void
 532 ixgbe_enable_intr(struct rte_eth_dev *dev)
 533 {
 534         struct ixgbe_interrupt *intr =
 535                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 536         struct ixgbe_hw *hw =
 537                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 538
 539         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 540         IXGBE_WRITE_FLUSH(hw);
 541 }
 542
 543 /*
 544  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 545  */
 546 static void
 547 ixgbe_disable_intr(struct ixgbe_hw *hw)
 548 {
 549         PMD_INIT_FUNC_TRACE();
 550
 551         if (hw->mac.type == ixgbe_mac_82598EB) {
 552                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 553         } else {
 554                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 555                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 556                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 557         }
 558         IXGBE_WRITE_FLUSH(hw);
 559 }
 560
 561 /*
 562  * This function resets queue statistics mapping registers.
 563  * From Niantic datasheet, Initialization of Statistics section:
 564  * "...if software requires the queue counters, the RQSMR and TQSM registers
 565  * must be re-programmed following a device reset.
 566  */
 567 static void
 568 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 569 {
 570         uint32_t i;
 571
 572         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 573                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 574                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 575         }
 576 }
 577
 578
 579 static int
 580 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 581                                   uint16_t queue_id,
 582                                   uint8_t stat_idx,
 583                                   uint8_t is_rx)
 584 {
 585 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 586 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 587 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 588
 589         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 590         struct ixgbe_stat_mapping_registers *stat_mappings =
 591                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 592         uint32_t qsmr_mask = 0;
 593         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 594         uint32_t q_map;
 595         uint8_t n, offset;
 596
 597         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 598                 (hw->mac.type != ixgbe_mac_X540) &&
 599                 (hw->mac.type != ixgbe_mac_X550) &&
 600                 (hw->mac.type != ixgbe_mac_X550EM_x))
 601                 return -ENOSYS;
 602
 603         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
 604                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 605                      queue_id, stat_idx);
 606
 607         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 608         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 609                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 610                 return -EIO;
 611         }
 612         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 613
 614         /* Now clear any previous stat_idx set */
 615         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 616         if (!is_rx)
 617                 stat_mappings->tqsm[n] &= ~clearing_mask;
 618         else
 619                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 620
 621         q_map = (uint32_t)stat_idx;
 622         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 623         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 624         if (!is_rx)
 625                 stat_mappings->tqsm[n] |= qsmr_mask;
 626         else
 627                 stat_mappings->rqsmr[n] |= qsmr_mask;
 628
 629         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
 630                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 631                      queue_id, stat_idx);
 632         PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 633                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 634
 635         /* Now write the mapping in the appropriate register */
 636         if (is_rx) {
 637                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 638                              stat_mappings->rqsmr[n], n);
 639                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 640         }
 641         else {
 642                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 643                              stat_mappings->tqsm[n], n);
 644                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 645         }
 646         return 0;
 647 }
 648
 649 static void
 650 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 651 {
 652         struct ixgbe_stat_mapping_registers *stat_mappings =
 653                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 654         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 655         int i;
 656
 657         /* write whatever was in stat mapping table to the NIC */
 658         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 659                 /* rx */
 660                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 661
 662                 /* tx */
 663                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 664         }
 665 }
 666
 667 static void
 668 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 669 {
 670         uint8_t i;
 671         struct ixgbe_dcb_tc_config *tc;
 672         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 673
 674         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 675         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 676         for (i = 0; i < dcb_max_tc; i++) {
 677                 tc = &dcb_config->tc_config[i];
 678                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 679                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 680                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 681                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 682                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 683                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 684                 tc->pfc = ixgbe_dcb_pfc_disabled;
 685         }
 686
 687         /* Initialize default user to priority mapping, UPx->TC0 */
 688         tc = &dcb_config->tc_config[0];
 689         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 690         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 691         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 692                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 693                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 694         }
 695         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 696         dcb_config->pfc_mode_enable = false;
 697         dcb_config->vt_mode = true;
 698         dcb_config->round_robin_enable = false;
 699         /* support all DCB capabilities in 82599 */
 700         dcb_config->support.capabilities = 0xFF;
 701
 702         /*we only support 4 Tcs for X540, X550 */
 703         if (hw->mac.type == ixgbe_mac_X540 ||
 704                 hw->mac.type == ixgbe_mac_X550 ||
 705                 hw->mac.type == ixgbe_mac_X550EM_x) {
 706                 dcb_config->num_tcs.pg_tcs = 4;
 707                 dcb_config->num_tcs.pfc_tcs = 4;
 708         }
 709 }
 710
 711 /*
 712  * Ensure that all locks are released before first NVM or PHY access
 713  */
 714 static void
 715 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 716 {
 717         uint16_t mask;
 718
 719         /*
 720          * Phy lock should not fail in this early stage. If this is the case,
 721          * it is due to an improper exit of the application.
 722          * So force the release of the faulty lock. Release of common lock
 723          * is done automatically by swfw_sync function.
 724          */
 725         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 726         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 727                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 728         }
 729         ixgbe_release_swfw_semaphore(hw, mask);
 730
 731         /*
 732          * These ones are more tricky since they are common to all ports; but
 733          * swfw_sync retries last long enough (1s) to be almost sure that if
 734          * lock can not be taken it is due to an improper lock of the
 735          * semaphore.
 736          */
 737         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 738         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 739                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 740         }
 741         ixgbe_release_swfw_semaphore(hw, mask);
 742 }
 743
 744 /*
 745  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
 746  * It returns 0 on success.
 747  */
 748 static int
 749 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
 750 {
 751         struct rte_pci_device *pci_dev;
 752         struct ixgbe_hw *hw =
 753                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 754         struct ixgbe_vfta * shadow_vfta =
 755                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 756         struct ixgbe_hwstrip *hwstrip =
 757                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 758         struct ixgbe_dcb_config *dcb_config =
 759                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 760         struct ixgbe_filter_info *filter_info =
 761                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 762         uint32_t ctrl_ext;
 763         uint16_t csum;
 764         int diag, i;
 765
 766         PMD_INIT_FUNC_TRACE();
 767
 768         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 769         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 770         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 771
 772         /*
 773          * For secondary processes, we don't initialise any further as primary
 774          * has already done this work. Only check we don't need a different
 775          * RX and TX function.
 776          */
 777         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 778                 struct ixgbe_tx_queue *txq;
 779                 /* TX queue function in primary, set by last queue initialized
 780                  * Tx queue may not initialized by primary process */
 781                 if (eth_dev->data->tx_queues) {
 782                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 783                         ixgbe_set_tx_function(eth_dev, txq);
 784                 } else {
 785                         /* Use default TX function if we get here */
 786                         PMD_INIT_LOG(INFO, "No TX queues configured yet. "
 787                                            "Using default TX function.");
 788                 }
 789
 790                 ixgbe_set_rx_function(eth_dev);
 791
 792                 return 0;
 793         }
 794         pci_dev = eth_dev->pci_dev;
 795
 796         /* Vendor and Device ID need to be set before init of shared code */
 797         hw->device_id = pci_dev->id.device_id;
 798         hw->vendor_id = pci_dev->id.vendor_id;
 799         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 800         hw->allow_unsupported_sfp = 1;
 801
 802         /* Initialize the shared code (base driver) */
 803 #ifdef RTE_NIC_BYPASS
 804         diag = ixgbe_bypass_init_shared_code(hw);
 805 #else
 806         diag = ixgbe_init_shared_code(hw);
 807 #endif /* RTE_NIC_BYPASS */
 808
 809         if (diag != IXGBE_SUCCESS) {
 810                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 811                 return -EIO;
 812         }
 813
 814         /* pick up the PCI bus settings for reporting later */
 815         ixgbe_get_bus_info(hw);
 816
 817         /* Unlock any pending hardware semaphore */
 818         ixgbe_swfw_lock_reset(hw);
 819
 820         /* Initialize DCB configuration*/
 821         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 822         ixgbe_dcb_init(hw,dcb_config);
 823         /* Get Hardware Flow Control setting */
 824         hw->fc.requested_mode = ixgbe_fc_full;
 825         hw->fc.current_mode = ixgbe_fc_full;
 826         hw->fc.pause_time = IXGBE_FC_PAUSE;
 827         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 828                 hw->fc.low_water[i] = IXGBE_FC_LO;
 829                 hw->fc.high_water[i] = IXGBE_FC_HI;
 830         }
 831         hw->fc.send_xon = 1;
 832
 833         /* Make sure we have a good EEPROM before we read from it */
 834         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 835         if (diag != IXGBE_SUCCESS) {
 836                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 837                 return -EIO;
 838         }
 839
 840 #ifdef RTE_NIC_BYPASS
 841         diag = ixgbe_bypass_init_hw(hw);
 842 #else
 843         diag = ixgbe_init_hw(hw);
 844 #endif /* RTE_NIC_BYPASS */
 845
 846         /*
 847          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 848          * is called too soon after the kernel driver unbinding/binding occurs.
 849          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 850          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 851          * also called. See ixgbe_identify_phy_82599(). The reason for the
 852          * failure is not known, and only occuts when virtualisation features
 853          * are disabled in the bios. A delay of 100ms  was found to be enough by
 854          * trial-and-error, and is doubled to be safe.
 855          */
 856         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 857                 rte_delay_ms(200);
 858                 diag = ixgbe_init_hw(hw);
 859         }
 860
 861         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 862                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 863                     "LOM.  Please be aware there may be issues associated "
 864                     "with your hardware.");
 865                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 866                     "please contact your Intel or hardware representative "
 867                     "who provided you with this hardware.");
 868         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 869                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 870         if (diag) {
 871                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 872                 return -EIO;
 873         }
 874
 875         /* Reset the hw statistics */
 876         ixgbe_dev_stats_reset(eth_dev);
 877
 878         /* disable interrupt */
 879         ixgbe_disable_intr(hw);
 880
 881         /* reset mappings for queue statistics hw counters*/
 882         ixgbe_reset_qstat_mappings(hw);
 883
 884         /* Allocate memory for storing MAC addresses */
 885         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 886                         hw->mac.num_rar_entries, 0);
 887         if (eth_dev->data->mac_addrs == NULL) {
 888                 PMD_INIT_LOG(ERR,
 889                         "Failed to allocate %u bytes needed to store "
 890                         "MAC addresses",
 891                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 892                 return -ENOMEM;
 893         }
 894         /* Copy the permanent MAC address */
 895         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 896                         &eth_dev->data->mac_addrs[0]);
 897
 898         /* Allocate memory for storing hash filter MAC addresses */
 899         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 900                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 901         if (eth_dev->data->hash_mac_addrs == NULL) {
 902                 PMD_INIT_LOG(ERR,
 903                         "Failed to allocate %d bytes needed to store MAC addresses",
 904                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 905                 return -ENOMEM;
 906         }
 907
 908         /* initialize the vfta */
 909         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 910
 911         /* initialize the hw strip bitmap*/
 912         memset(hwstrip, 0, sizeof(*hwstrip));
 913
 914         /* initialize PF if max_vfs not zero */
 915         ixgbe_pf_host_init(eth_dev);
 916
 917         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 918         /* let hardware know driver is loaded */
 919         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 920         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 921         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 922         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 923         IXGBE_WRITE_FLUSH(hw);
 924
 925         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 926                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 927                              (int) hw->mac.type, (int) hw->phy.type,
 928                              (int) hw->phy.sfp_type);
 929         else
 930                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 931                              (int) hw->mac.type, (int) hw->phy.type);
 932
 933         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 934                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 935                         pci_dev->id.device_id);
 936
 937         rte_intr_callback_register(&(pci_dev->intr_handle),
 938                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 939
 940         /* enable uio intr after callback register */
 941         rte_intr_enable(&(pci_dev->intr_handle));
 942
 943         /* enable support intr */
 944         ixgbe_enable_intr(eth_dev);
 945
 946         /* initialize 5tuple filter list */
 947         TAILQ_INIT(&filter_info->fivetuple_list);
 948         memset(filter_info->fivetuple_mask, 0,
 949                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
 950
 951         return 0;
 952 }
 953
 954
 955 /*
 956  * Negotiate mailbox API version with the PF.
 957  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 958  * Then we try to negotiate starting with the most recent one.
 959  * If all negotiation attempts fail, then we will proceed with
 960  * the default one (ixgbe_mbox_api_10).
 961  */
 962 static void
 963 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 964 {
 965         int32_t i;
 966
 967         /* start with highest supported, proceed down */
 968         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 969                 ixgbe_mbox_api_11,
 970                 ixgbe_mbox_api_10,
 971         };
 972
 973         for (i = 0;
 974                         i != RTE_DIM(sup_ver) &&
 975                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 976                         i++)
 977                 ;
 978 }
 979
 980 static void
 981 generate_random_mac_addr(struct ether_addr *mac_addr)
 982 {
 983         uint64_t random;
 984
 985         /* Set Organizationally Unique Identifier (OUI) prefix. */
 986         mac_addr->addr_bytes[0] = 0x00;
 987         mac_addr->addr_bytes[1] = 0x09;
 988         mac_addr->addr_bytes[2] = 0xC0;
 989         /* Force indication of locally assigned MAC address. */
 990         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 991         /* Generate the last 3 bytes of the MAC address with a random number. */
 992         random = rte_rand();
 993         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 994 }
 995
 996 /*
 997  * Virtual Function device init
 998  */
 999 static int
1000 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1001 {
1002         int diag;
1003         uint32_t tc, tcs;
1004         struct rte_pci_device *pci_dev;
1005         struct ixgbe_hw *hw =
1006                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1007         struct ixgbe_vfta * shadow_vfta =
1008                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1009         struct ixgbe_hwstrip *hwstrip =
1010                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1011         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1012
1013         PMD_INIT_FUNC_TRACE();
1014
1015         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1016         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1017         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1018
1019         /* for secondary processes, we don't initialise any further as primary
1020          * has already done this work. Only check we don't need a different
1021          * RX function */
1022         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1023                 if (eth_dev->data->scattered_rx)
1024                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1025                 return 0;
1026         }
1027
1028         pci_dev = eth_dev->pci_dev;
1029
1030         hw->device_id = pci_dev->id.device_id;
1031         hw->vendor_id = pci_dev->id.vendor_id;
1032         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1033
1034         /* initialize the vfta */
1035         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1036
1037         /* initialize the hw strip bitmap*/
1038         memset(hwstrip, 0, sizeof(*hwstrip));
1039
1040         /* Initialize the shared code (base driver) */
1041         diag = ixgbe_init_shared_code(hw);
1042         if (diag != IXGBE_SUCCESS) {
1043                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1044                 return -EIO;
1045         }
1046
1047         /* init_mailbox_params */
1048         hw->mbx.ops.init_params(hw);
1049
1050         /* Reset the hw statistics */
1051         ixgbevf_dev_stats_reset(eth_dev);
1052
1053         /* Disable the interrupts for VF */
1054         ixgbevf_intr_disable(hw);
1055
1056         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1057         diag = hw->mac.ops.reset_hw(hw);
1058
1059         /*
1060          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1061          * the underlying PF driver has not assigned a MAC address to the VF.
1062          * In this case, assign a random MAC address.
1063          */
1064         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1065                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1066                 return (diag);
1067         }
1068
1069         /* negotiate mailbox API version to use with the PF. */
1070         ixgbevf_negotiate_api(hw);
1071
1072         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1073         ixgbevf_get_queues(hw, &tcs, &tc);
1074
1075         /* Allocate memory for storing MAC addresses */
1076         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1077                         hw->mac.num_rar_entries, 0);
1078         if (eth_dev->data->mac_addrs == NULL) {
1079                 PMD_INIT_LOG(ERR,
1080                         "Failed to allocate %u bytes needed to store "
1081                         "MAC addresses",
1082                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1083                 return -ENOMEM;
1084         }
1085
1086         /* Generate a random MAC address, if none was assigned by PF. */
1087         if (is_zero_ether_addr(perm_addr)) {
1088                 generate_random_mac_addr(perm_addr);
1089                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1090                 if (diag) {
1091                         rte_free(eth_dev->data->mac_addrs);
1092                         eth_dev->data->mac_addrs = NULL;
1093                         return diag;
1094                 }
1095                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1096                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1097                              "%02x:%02x:%02x:%02x:%02x:%02x",
1098                              perm_addr->addr_bytes[0],
1099                              perm_addr->addr_bytes[1],
1100                              perm_addr->addr_bytes[2],
1101                              perm_addr->addr_bytes[3],
1102                              perm_addr->addr_bytes[4],
1103                              perm_addr->addr_bytes[5]);
1104         }
1105
1106         /* Copy the permanent MAC address */
1107         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1108
1109         /* reset the hardware with the new settings */
1110         diag = hw->mac.ops.start_hw(hw);
1111         switch (diag) {
1112                 case  0:
1113                         break;
1114
1115                 default:
1116                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1117                         return (-EIO);
1118         }
1119
1120         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1121                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1122                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1123
1124         return 0;
1125 }
1126
1127 static struct eth_driver rte_ixgbe_pmd = {
1128         .pci_drv = {
1129                 .name = "rte_ixgbe_pmd",
1130                 .id_table = pci_id_ixgbe_map,
1131                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1132         },
1133         .eth_dev_init = eth_ixgbe_dev_init,
1134         .dev_private_size = sizeof(struct ixgbe_adapter),
1135 };
1136
1137 /*
1138  * virtual function driver struct
1139  */
1140 static struct eth_driver rte_ixgbevf_pmd = {
1141         .pci_drv = {
1142                 .name = "rte_ixgbevf_pmd",
1143                 .id_table = pci_id_ixgbevf_map,
1144                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1145         },
1146         .eth_dev_init = eth_ixgbevf_dev_init,
1147         .dev_private_size = sizeof(struct ixgbe_adapter),
1148 };
1149
1150 /*
1151  * Driver initialization routine.
1152  * Invoked once at EAL init time.
1153  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1154  */
1155 static int
1156 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1157 {
1158         PMD_INIT_FUNC_TRACE();
1159
1160         rte_eth_driver_register(&rte_ixgbe_pmd);
1161         return 0;
1162 }
1163
1164 /*
1165  * VF Driver initialization routine.
1166  * Invoked one at EAL init time.
1167  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1168  */
1169 static int
1170 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1171 {
1172         PMD_INIT_FUNC_TRACE();
1173
1174         rte_eth_driver_register(&rte_ixgbevf_pmd);
1175         return (0);
1176 }
1177
1178 static int
1179 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1180 {
1181         struct ixgbe_hw *hw =
1182                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1183         struct ixgbe_vfta * shadow_vfta =
1184                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1185         uint32_t vfta;
1186         uint32_t vid_idx;
1187         uint32_t vid_bit;
1188
1189         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1190         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1191         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1192         if (on)
1193                 vfta |= vid_bit;
1194         else
1195                 vfta &= ~vid_bit;
1196         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1197
1198         /* update local VFTA copy */
1199         shadow_vfta->vfta[vid_idx] = vfta;
1200
1201         return 0;
1202 }
1203
1204 static void
1205 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1206 {
1207         if (on)
1208                 ixgbe_vlan_hw_strip_enable(dev, queue);
1209         else
1210                 ixgbe_vlan_hw_strip_disable(dev, queue);
1211 }
1212
1213 static void
1214 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1215 {
1216         struct ixgbe_hw *hw =
1217                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1218
1219         /* Only the high 16-bits is valid */
1220         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1221 }
1222
1223 void
1224 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1225 {
1226         struct ixgbe_hw *hw =
1227                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1228         uint32_t vlnctrl;
1229
1230         PMD_INIT_FUNC_TRACE();
1231
1232         /* Filter Table Disable */
1233         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1234         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1235
1236         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1237 }
1238
1239 void
1240 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1241 {
1242         struct ixgbe_hw *hw =
1243                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1244         struct ixgbe_vfta * shadow_vfta =
1245                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1246         uint32_t vlnctrl;
1247         uint16_t i;
1248
1249         PMD_INIT_FUNC_TRACE();
1250
1251         /* Filter Table Enable */
1252         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1253         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1254         vlnctrl |= IXGBE_VLNCTRL_VFE;
1255
1256         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1257
1258         /* write whatever is in local vfta copy */
1259         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1260                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1261 }
1262
1263 static void
1264 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1265 {
1266         struct ixgbe_hwstrip *hwstrip =
1267                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1268
1269         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1270                 return;
1271
1272         if (on)
1273                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1274         else
1275                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1276 }
1277
1278 static void
1279 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1280 {
1281         struct ixgbe_hw *hw =
1282                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1283         uint32_t ctrl;
1284
1285         PMD_INIT_FUNC_TRACE();
1286
1287         if (hw->mac.type == ixgbe_mac_82598EB) {
1288                 /* No queue level support */
1289                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1290                 return;
1291         }
1292         else {
1293                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1294                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1295                 ctrl &= ~IXGBE_RXDCTL_VME;
1296                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1297         }
1298         /* record those setting for HW strip per queue */
1299         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1300 }
1301
1302 static void
1303 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1304 {
1305         struct ixgbe_hw *hw =
1306                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1307         uint32_t ctrl;
1308
1309         PMD_INIT_FUNC_TRACE();
1310
1311         if (hw->mac.type == ixgbe_mac_82598EB) {
1312                 /* No queue level supported */
1313                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1314                 return;
1315         }
1316         else {
1317                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1318                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1319                 ctrl |= IXGBE_RXDCTL_VME;
1320                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1321         }
1322         /* record those setting for HW strip per queue */
1323         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1324 }
1325
1326 void
1327 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1328 {
1329         struct ixgbe_hw *hw =
1330                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1331         uint32_t ctrl;
1332         uint16_t i;
1333
1334         PMD_INIT_FUNC_TRACE();
1335
1336         if (hw->mac.type == ixgbe_mac_82598EB) {
1337                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1338                 ctrl &= ~IXGBE_VLNCTRL_VME;
1339                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1340         }
1341         else {
1342                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1343                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1344                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1345                         ctrl &= ~IXGBE_RXDCTL_VME;
1346                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1347
1348                         /* record those setting for HW strip per queue */
1349                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1350                 }
1351         }
1352 }
1353
1354 void
1355 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1356 {
1357         struct ixgbe_hw *hw =
1358                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1359         uint32_t ctrl;
1360         uint16_t i;
1361
1362         PMD_INIT_FUNC_TRACE();
1363
1364         if (hw->mac.type == ixgbe_mac_82598EB) {
1365                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1366                 ctrl |= IXGBE_VLNCTRL_VME;
1367                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1368         }
1369         else {
1370                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1371                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1372                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1373                         ctrl |= IXGBE_RXDCTL_VME;
1374                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1375
1376                         /* record those setting for HW strip per queue */
1377                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1378                 }
1379         }
1380 }
1381
1382 static void
1383 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1384 {
1385         struct ixgbe_hw *hw =
1386                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1387         uint32_t ctrl;
1388
1389         PMD_INIT_FUNC_TRACE();
1390
1391         /* DMATXCTRL: Geric Double VLAN Disable */
1392         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1393         ctrl &= ~IXGBE_DMATXCTL_GDV;
1394         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1395
1396         /* CTRL_EXT: Global Double VLAN Disable */
1397         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1398         ctrl &= ~IXGBE_EXTENDED_VLAN;
1399         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1400
1401 }
1402
1403 static void
1404 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1405 {
1406         struct ixgbe_hw *hw =
1407                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1408         uint32_t ctrl;
1409
1410         PMD_INIT_FUNC_TRACE();
1411
1412         /* DMATXCTRL: Geric Double VLAN Enable */
1413         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1414         ctrl |= IXGBE_DMATXCTL_GDV;
1415         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1416
1417         /* CTRL_EXT: Global Double VLAN Enable */
1418         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1419         ctrl |= IXGBE_EXTENDED_VLAN;
1420         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1421
1422         /*
1423          * VET EXT field in the EXVET register = 0x8100 by default
1424          * So no need to change. Same to VT field of DMATXCTL register
1425          */
1426 }
1427
1428 static void
1429 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1430 {
1431         if(mask & ETH_VLAN_STRIP_MASK){
1432                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1433                         ixgbe_vlan_hw_strip_enable_all(dev);
1434                 else
1435                         ixgbe_vlan_hw_strip_disable_all(dev);
1436         }
1437
1438         if(mask & ETH_VLAN_FILTER_MASK){
1439                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1440                         ixgbe_vlan_hw_filter_enable(dev);
1441                 else
1442                         ixgbe_vlan_hw_filter_disable(dev);
1443         }
1444
1445         if(mask & ETH_VLAN_EXTEND_MASK){
1446                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1447                         ixgbe_vlan_hw_extend_enable(dev);
1448                 else
1449                         ixgbe_vlan_hw_extend_disable(dev);
1450         }
1451 }
1452
1453 static void
1454 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1455 {
1456         struct ixgbe_hw *hw =
1457                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1458         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1459         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1460         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1461         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1462 }
1463
1464 static int
1465 ixgbe_dev_configure(struct rte_eth_dev *dev)
1466 {
1467         struct ixgbe_interrupt *intr =
1468                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1469         struct ixgbe_adapter *adapter =
1470                 (struct ixgbe_adapter *)dev->data->dev_private;
1471
1472         PMD_INIT_FUNC_TRACE();
1473
1474         /* set flag to update link status after init */
1475         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1476
1477         /*
1478          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1479          * allocation or vector Rx preconditions we will reset it.
1480          */
1481         adapter->rx_bulk_alloc_allowed = true;
1482         adapter->rx_vec_allowed = true;
1483
1484         return 0;
1485 }
1486
1487 /*
1488  * Configure device link speed and setup link.
1489  * It returns 0 on success.
1490  */
1491 static int
1492 ixgbe_dev_start(struct rte_eth_dev *dev)
1493 {
1494         struct ixgbe_hw *hw =
1495                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1496         struct ixgbe_vf_info *vfinfo =
1497                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1498         int err, link_up = 0, negotiate = 0;
1499         uint32_t speed = 0;
1500         int mask = 0;
1501         int status;
1502         uint16_t vf, idx;
1503
1504         PMD_INIT_FUNC_TRACE();
1505
1506         /* IXGBE devices don't support half duplex */
1507         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1508                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1509                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1510                              dev->data->dev_conf.link_duplex,
1511                              dev->data->port_id);
1512                 return -EINVAL;
1513         }
1514
1515         /* stop adapter */
1516         hw->adapter_stopped = FALSE;
1517         ixgbe_stop_adapter(hw);
1518
1519         /* reinitialize adapter
1520          * this calls reset and start */
1521         status = ixgbe_pf_reset_hw(hw);
1522         if (status != 0)
1523                 return -1;
1524         hw->mac.ops.start_hw(hw);
1525         hw->mac.get_link_status = true;
1526
1527         /* configure PF module if SRIOV enabled */
1528         ixgbe_pf_host_configure(dev);
1529
1530         /* initialize transmission unit */
1531         ixgbe_dev_tx_init(dev);
1532
1533         /* This can fail when allocating mbufs for descriptor rings */
1534         err = ixgbe_dev_rx_init(dev);
1535         if (err) {
1536                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1537                 goto error;
1538         }
1539
1540         err = ixgbe_dev_rxtx_start(dev);
1541         if (err < 0) {
1542                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1543                 goto error;
1544         }
1545
1546         /* Skip link setup if loopback mode is enabled for 82599. */
1547         if (hw->mac.type == ixgbe_mac_82599EB &&
1548                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1549                 goto skip_link_setup;
1550
1551         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1552                 err = hw->mac.ops.setup_sfp(hw);
1553                 if (err)
1554                         goto error;
1555         }
1556
1557         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1558                 /* Turn on the copper */
1559                 ixgbe_set_phy_power(hw, true);
1560         } else {
1561                 /* Turn on the laser */
1562                 ixgbe_enable_tx_laser(hw);
1563         }
1564
1565         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1566         if (err)
1567                 goto error;
1568         dev->data->dev_link.link_status = link_up;
1569
1570         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1571         if (err)
1572                 goto error;
1573
1574         switch(dev->data->dev_conf.link_speed) {
1575         case ETH_LINK_SPEED_AUTONEG:
1576                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1577                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1578                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1579                 break;
1580         case ETH_LINK_SPEED_100:
1581                 /*
1582                  * Invalid for 82598 but error will be detected by
1583                  * ixgbe_setup_link()
1584                  */
1585                 speed = IXGBE_LINK_SPEED_100_FULL;
1586                 break;
1587         case ETH_LINK_SPEED_1000:
1588                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1589                 break;
1590         case ETH_LINK_SPEED_10000:
1591                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1592                 break;
1593         default:
1594                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1595                              dev->data->dev_conf.link_speed,
1596                              dev->data->port_id);
1597                 goto error;
1598         }
1599
1600         err = ixgbe_setup_link(hw, speed, link_up);
1601         if (err)
1602                 goto error;
1603
1604 skip_link_setup:
1605
1606         /* check if lsc interrupt is enabled */
1607         if (dev->data->dev_conf.intr_conf.lsc != 0)
1608                 ixgbe_dev_lsc_interrupt_setup(dev);
1609
1610         /* resume enabled intr since hw reset */
1611         ixgbe_enable_intr(dev);
1612
1613         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1614                 ETH_VLAN_EXTEND_MASK;
1615         ixgbe_vlan_offload_set(dev, mask);
1616
1617         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1618                 /* Enable vlan filtering for VMDq */
1619                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1620         }
1621
1622         /* Configure DCB hw */
1623         ixgbe_configure_dcb(dev);
1624
1625         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1626                 err = ixgbe_fdir_configure(dev);
1627                 if (err)
1628                         goto error;
1629         }
1630
1631         /* Restore vf rate limit */
1632         if (vfinfo != NULL) {
1633                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1634                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1635                                 if (vfinfo[vf].tx_rate[idx] != 0)
1636                                         ixgbe_set_vf_rate_limit(dev, vf,
1637                                                 vfinfo[vf].tx_rate[idx],
1638                                                 1 << idx);
1639         }
1640
1641         ixgbe_restore_statistics_mapping(dev);
1642
1643         return (0);
1644
1645 error:
1646         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1647         ixgbe_dev_clear_queues(dev);
1648         return -EIO;
1649 }
1650
1651 /*
1652  * Stop device: disable rx and tx functions to allow for reconfiguring.
1653  */
1654 static void
1655 ixgbe_dev_stop(struct rte_eth_dev *dev)
1656 {
1657         struct rte_eth_link link;
1658         struct ixgbe_hw *hw =
1659                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1660         struct ixgbe_vf_info *vfinfo =
1661                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1662         struct ixgbe_filter_info *filter_info =
1663                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1664         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
1665         int vf;
1666
1667         PMD_INIT_FUNC_TRACE();
1668
1669         /* disable interrupts */
1670         ixgbe_disable_intr(hw);
1671
1672         /* reset the NIC */
1673         ixgbe_pf_reset_hw(hw);
1674         hw->adapter_stopped = FALSE;
1675
1676         /* stop adapter */
1677         ixgbe_stop_adapter(hw);
1678
1679         for (vf = 0; vfinfo != NULL &&
1680                      vf < dev->pci_dev->max_vfs; vf++)
1681                 vfinfo[vf].clear_to_send = false;
1682
1683         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1684                 /* Turn off the copper */
1685                 ixgbe_set_phy_power(hw, false);
1686         } else {
1687                 /* Turn off the laser */
1688                 ixgbe_disable_tx_laser(hw);
1689         }
1690
1691         ixgbe_dev_clear_queues(dev);
1692
1693         /* Clear stored conf */
1694         dev->data->scattered_rx = 0;
1695         dev->data->lro = 0;
1696
1697         /* Clear recorded link status */
1698         memset(&link, 0, sizeof(link));
1699         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1700
1701         /* Remove all ntuple filters of the device */
1702         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1703              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1704                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1705                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1706                              p_5tuple, entries);
1707                 rte_free(p_5tuple);
1708         }
1709         memset(filter_info->fivetuple_mask, 0,
1710                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1711
1712 }
1713
1714 /*
1715  * Set device link up: enable tx.
1716  */
1717 static int
1718 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1719 {
1720         struct ixgbe_hw *hw =
1721                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1722         if (hw->mac.type == ixgbe_mac_82599EB) {
1723 #ifdef RTE_NIC_BYPASS
1724                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1725                         /* Not suported in bypass mode */
1726                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1727                                      "by device id 0x%x", hw->device_id);
1728                         return -ENOTSUP;
1729                 }
1730 #endif
1731         }
1732
1733         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1734                 /* Turn on the copper */
1735                 ixgbe_set_phy_power(hw, true);
1736         } else {
1737                 /* Turn on the laser */
1738                 ixgbe_enable_tx_laser(hw);
1739         }
1740
1741         return 0;
1742 }
1743
1744 /*
1745  * Set device link down: disable tx.
1746  */
1747 static int
1748 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1749 {
1750         struct ixgbe_hw *hw =
1751                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1752         if (hw->mac.type == ixgbe_mac_82599EB) {
1753 #ifdef RTE_NIC_BYPASS
1754                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1755                         /* Not suported in bypass mode */
1756                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1757                                      "by device id 0x%x", hw->device_id);
1758                         return -ENOTSUP;
1759                 }
1760 #endif
1761         }
1762
1763         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1764                 /* Turn off the copper */
1765                 ixgbe_set_phy_power(hw, false);
1766         } else {
1767                 /* Turn off the laser */
1768                 ixgbe_disable_tx_laser(hw);
1769         }
1770
1771         return 0;
1772 }
1773
1774 /*
1775  * Reest and stop device.
1776  */
1777 static void
1778 ixgbe_dev_close(struct rte_eth_dev *dev)
1779 {
1780         struct ixgbe_hw *hw =
1781                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1782
1783         PMD_INIT_FUNC_TRACE();
1784
1785         ixgbe_pf_reset_hw(hw);
1786
1787         ixgbe_dev_stop(dev);
1788         hw->adapter_stopped = 1;
1789
1790         ixgbe_disable_pcie_master(hw);
1791
1792         /* reprogram the RAR[0] in case user changed it. */
1793         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1794 }
1795
1796 /*
1797  * This function is based on ixgbe_update_stats_counters() in base/ixgbe.c
1798  */
1799 static void
1800 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1801 {
1802         struct ixgbe_hw *hw =
1803                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1804         struct ixgbe_hw_stats *hw_stats =
1805                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1806         uint32_t bprc, lxon, lxoff, total;
1807         uint64_t total_missed_rx, total_qbrc, total_qprc;
1808         unsigned i;
1809
1810         total_missed_rx = 0;
1811         total_qbrc = 0;
1812         total_qprc = 0;
1813
1814         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1815         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1816         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1817         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1818
1819         for (i = 0; i < 8; i++) {
1820                 uint32_t mp;
1821                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1822                 /* global total per queue */
1823                 hw_stats->mpc[i] += mp;
1824                 /* Running comprehensive total for stats display */
1825                 total_missed_rx += hw_stats->mpc[i];
1826                 if (hw->mac.type == ixgbe_mac_82598EB)
1827                         hw_stats->rnbc[i] +=
1828                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1829                 hw_stats->pxontxc[i] +=
1830                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1831                 hw_stats->pxonrxc[i] +=
1832                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1833                 hw_stats->pxofftxc[i] +=
1834                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1835                 hw_stats->pxoffrxc[i] +=
1836                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1837                 hw_stats->pxon2offc[i] +=
1838                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1839         }
1840         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1841                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1842                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1843                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1844                 hw_stats->qbrc[i] +=
1845                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1846                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1847                 hw_stats->qbtc[i] +=
1848                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1849                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1850
1851                 total_qprc += hw_stats->qprc[i];
1852                 total_qbrc += hw_stats->qbrc[i];
1853         }
1854         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1855         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1856         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1857
1858         /* Note that gprc counts missed packets */
1859         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1860
1861         if (hw->mac.type != ixgbe_mac_82598EB) {
1862                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1863                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1864                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1865                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1866                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1867                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1868                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1869                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1870         } else {
1871                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1872                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1873                 /* 82598 only has a counter in the high register */
1874                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1875                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1876                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1877         }
1878
1879         /*
1880          * Workaround: mprc hardware is incorrectly counting
1881          * broadcasts, so for now we subtract those.
1882          */
1883         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1884         hw_stats->bprc += bprc;
1885         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1886         if (hw->mac.type == ixgbe_mac_82598EB)
1887                 hw_stats->mprc -= bprc;
1888
1889         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1890         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1891         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1892         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1893         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1894         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1895
1896         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1897         hw_stats->lxontxc += lxon;
1898         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1899         hw_stats->lxofftxc += lxoff;
1900         total = lxon + lxoff;
1901
1902         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1903         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1904         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1905         hw_stats->gptc -= total;
1906         hw_stats->mptc -= total;
1907         hw_stats->ptc64 -= total;
1908         hw_stats->gotc -= total * ETHER_MIN_LEN;
1909
1910         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1911         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1912         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1913         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1914         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1915         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1916         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1917         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1918         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1919         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1920         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1921         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1922         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1923         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1924         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1925         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1926         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1927         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1928         /* Only read FCOE on 82599 */
1929         if (hw->mac.type != ixgbe_mac_82598EB) {
1930                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1931                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1932                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1933                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1934                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1935         }
1936
1937         if (stats == NULL)
1938                 return;
1939
1940         /* Fill out the rte_eth_stats statistics structure */
1941         stats->ipackets = total_qprc;
1942         stats->ibytes = total_qbrc;
1943         stats->opackets = hw_stats->gptc;
1944         stats->obytes = hw_stats->gotc;
1945         stats->imcasts = hw_stats->mprc;
1946
1947         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1948                 stats->q_ipackets[i] = hw_stats->qprc[i];
1949                 stats->q_opackets[i] = hw_stats->qptc[i];
1950                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1951                 stats->q_obytes[i] = hw_stats->qbtc[i];
1952                 stats->q_errors[i] = hw_stats->qprdc[i];
1953         }
1954
1955         /* Rx Errors */
1956         stats->ibadcrc  = hw_stats->crcerrs;
1957         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1958         stats->imissed  = total_missed_rx;
1959         stats->ierrors  = stats->ibadcrc +
1960                           stats->ibadlen +
1961                           stats->imissed +
1962                           hw_stats->illerrc + hw_stats->errbc;
1963
1964         /* Tx Errors */
1965         stats->oerrors  = 0;
1966
1967         /* XON/XOFF pause frames */
1968         stats->tx_pause_xon  = hw_stats->lxontxc;
1969         stats->rx_pause_xon  = hw_stats->lxonrxc;
1970         stats->tx_pause_xoff = hw_stats->lxofftxc;
1971         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1972
1973         /* Flow Director Stats registers */
1974         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1975         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1976         stats->fdirmatch = hw_stats->fdirmatch;
1977         stats->fdirmiss = hw_stats->fdirmiss;
1978 }
1979
1980 static void
1981 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1982 {
1983         struct ixgbe_hw_stats *stats =
1984                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1985
1986         /* HW registers are cleared on read */
1987         ixgbe_dev_stats_get(dev, NULL);
1988
1989         /* Reset software totals */
1990         memset(stats, 0, sizeof(*stats));
1991 }
1992
1993 static void
1994 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1995 {
1996         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1997         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1998                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1999
2000         /* Good Rx packet, include VF loopback */
2001         UPDATE_VF_STAT(IXGBE_VFGPRC,
2002             hw_stats->last_vfgprc, hw_stats->vfgprc);
2003
2004         /* Good Rx octets, include VF loopback */
2005         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2006             hw_stats->last_vfgorc, hw_stats->vfgorc);
2007
2008         /* Good Tx packet, include VF loopback */
2009         UPDATE_VF_STAT(IXGBE_VFGPTC,
2010             hw_stats->last_vfgptc, hw_stats->vfgptc);
2011
2012         /* Good Tx octets, include VF loopback */
2013         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2014             hw_stats->last_vfgotc, hw_stats->vfgotc);
2015
2016         /* Rx Multicst Packet */
2017         UPDATE_VF_STAT(IXGBE_VFMPRC,
2018             hw_stats->last_vfmprc, hw_stats->vfmprc);
2019
2020         if (stats == NULL)
2021                 return;
2022
2023         stats->ipackets = hw_stats->vfgprc;
2024         stats->ibytes = hw_stats->vfgorc;
2025         stats->opackets = hw_stats->vfgptc;
2026         stats->obytes = hw_stats->vfgotc;
2027         stats->imcasts = hw_stats->vfmprc;
2028 }
2029
2030 static void
2031 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2032 {
2033         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2034                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2035
2036         /* Sync HW register to the last stats */
2037         ixgbevf_dev_stats_get(dev, NULL);
2038
2039         /* reset HW current stats*/
2040         hw_stats->vfgprc = 0;
2041         hw_stats->vfgorc = 0;
2042         hw_stats->vfgptc = 0;
2043         hw_stats->vfgotc = 0;
2044         hw_stats->vfmprc = 0;
2045
2046 }
2047
2048 static void
2049 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2050 {
2051         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2052
2053         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2054         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2055         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2056         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2057         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2058         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2059         dev_info->max_vfs = dev->pci_dev->max_vfs;
2060         if (hw->mac.type == ixgbe_mac_82598EB)
2061                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2062         else
2063                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2064         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2065         dev_info->rx_offload_capa =
2066                 DEV_RX_OFFLOAD_VLAN_STRIP |
2067                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2068                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2069                 DEV_RX_OFFLOAD_TCP_CKSUM;
2070
2071         /*
2072          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2073          * mode.
2074          */
2075         if ((hw->mac.type == ixgbe_mac_82599EB ||
2076              hw->mac.type == ixgbe_mac_X540) &&
2077             !RTE_ETH_DEV_SRIOV(dev).active)
2078                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2079
2080         dev_info->tx_offload_capa =
2081                 DEV_TX_OFFLOAD_VLAN_INSERT |
2082                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2083                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2084                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2085                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2086                 DEV_TX_OFFLOAD_TCP_TSO;
2087
2088         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2089                 .rx_thresh = {
2090                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2091                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2092                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2093                 },
2094                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2095                 .rx_drop_en = 0,
2096         };
2097
2098         dev_info->default_txconf = (struct rte_eth_txconf) {
2099                 .tx_thresh = {
2100                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2101                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2102                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2103                 },
2104                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2105                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2106                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2107                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2108         };
2109         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2110         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2111         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2112 }
2113
2114 static void
2115 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2116                      struct rte_eth_dev_info *dev_info)
2117 {
2118         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2119
2120         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2121         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2122         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2123         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2124         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2125         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2126         dev_info->max_vfs = dev->pci_dev->max_vfs;
2127         if (hw->mac.type == ixgbe_mac_82598EB)
2128                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2129         else
2130                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2131         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2132                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2133                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2134                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2135         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2136                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2137                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2138                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2139                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2140
2141         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2142                 .rx_thresh = {
2143                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2144                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2145                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2146                 },
2147                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2148                 .rx_drop_en = 0,
2149         };
2150
2151         dev_info->default_txconf = (struct rte_eth_txconf) {
2152                 .tx_thresh = {
2153                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2154                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2155                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2156                 },
2157                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2158                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2159                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2160                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2161         };
2162 }
2163
2164 /* return 0 means link status changed, -1 means not changed */
2165 static int
2166 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2167 {
2168         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2169         struct rte_eth_link link, old;
2170         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2171         int link_up;
2172         int diag;
2173
2174         link.link_status = 0;
2175         link.link_speed = 0;
2176         link.link_duplex = 0;
2177         memset(&old, 0, sizeof(old));
2178         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2179
2180         hw->mac.get_link_status = true;
2181
2182         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2183         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2184                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2185         else
2186                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2187
2188         if (diag != 0) {
2189                 link.link_speed = ETH_LINK_SPEED_100;
2190                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2191                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2192                 if (link.link_status == old.link_status)
2193                         return -1;
2194                 return 0;
2195         }
2196
2197         if (link_up == 0) {
2198                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2199                 if (link.link_status == old.link_status)
2200                         return -1;
2201                 return 0;
2202         }
2203         link.link_status = 1;
2204         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2205
2206         switch (link_speed) {
2207         default:
2208         case IXGBE_LINK_SPEED_UNKNOWN:
2209                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2210                 link.link_speed = ETH_LINK_SPEED_100;
2211                 break;
2212
2213         case IXGBE_LINK_SPEED_100_FULL:
2214                 link.link_speed = ETH_LINK_SPEED_100;
2215                 break;
2216
2217         case IXGBE_LINK_SPEED_1GB_FULL:
2218                 link.link_speed = ETH_LINK_SPEED_1000;
2219                 break;
2220
2221         case IXGBE_LINK_SPEED_10GB_FULL:
2222                 link.link_speed = ETH_LINK_SPEED_10000;
2223                 break;
2224         }
2225         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2226
2227         if (link.link_status == old.link_status)
2228                 return -1;
2229
2230         return 0;
2231 }
2232
2233 static void
2234 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2235 {
2236         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2237         uint32_t fctrl;
2238
2239         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2240         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2241         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2242 }
2243
2244 static void
2245 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2246 {
2247         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2248         uint32_t fctrl;
2249
2250         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2251         fctrl &= (~IXGBE_FCTRL_UPE);
2252         if (dev->data->all_multicast == 1)
2253                 fctrl |= IXGBE_FCTRL_MPE;
2254         else
2255                 fctrl &= (~IXGBE_FCTRL_MPE);
2256         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2257 }
2258
2259 static void
2260 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2261 {
2262         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2263         uint32_t fctrl;
2264
2265         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2266         fctrl |= IXGBE_FCTRL_MPE;
2267         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2268 }
2269
2270 static void
2271 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2272 {
2273         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2274         uint32_t fctrl;
2275
2276         if (dev->data->promiscuous == 1)
2277                 return; /* must remain in all_multicast mode */
2278
2279         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2280         fctrl &= (~IXGBE_FCTRL_MPE);
2281         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2282 }
2283
2284 /**
2285  * It clears the interrupt causes and enables the interrupt.
2286  * It will be called once only during nic initialized.
2287  *
2288  * @param dev
2289  *  Pointer to struct rte_eth_dev.
2290  *
2291  * @return
2292  *  - On success, zero.
2293  *  - On failure, a negative value.
2294  */
2295 static int
2296 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2297 {
2298         struct ixgbe_interrupt *intr =
2299                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2300
2301         ixgbe_dev_link_status_print(dev);
2302         intr->mask |= IXGBE_EICR_LSC;
2303
2304         return 0;
2305 }
2306
2307 /*
2308  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2309  *
2310  * @param dev
2311  *  Pointer to struct rte_eth_dev.
2312  *
2313  * @return
2314  *  - On success, zero.
2315  *  - On failure, a negative value.
2316  */
2317 static int
2318 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2319 {
2320         uint32_t eicr;
2321         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2322         struct ixgbe_interrupt *intr =
2323                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2324
2325         /* clear all cause mask */
2326         ixgbe_disable_intr(hw);
2327
2328         /* read-on-clear nic registers here */
2329         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2330         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2331
2332         intr->flags = 0;
2333         if (eicr & IXGBE_EICR_LSC) {
2334                 /* set flag for async link update */
2335                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2336         }
2337
2338         if (eicr & IXGBE_EICR_MAILBOX)
2339                 intr->flags |= IXGBE_FLAG_MAILBOX;
2340
2341         return 0;
2342 }
2343
2344 /**
2345  * It gets and then prints the link status.
2346  *
2347  * @param dev
2348  *  Pointer to struct rte_eth_dev.
2349  *
2350  * @return
2351  *  - On success, zero.
2352  *  - On failure, a negative value.
2353  */
2354 static void
2355 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2356 {
2357         struct rte_eth_link link;
2358
2359         memset(&link, 0, sizeof(link));
2360         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2361         if (link.link_status) {
2362                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2363                                         (int)(dev->data->port_id),
2364                                         (unsigned)link.link_speed,
2365                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2366                                         "full-duplex" : "half-duplex");
2367         } else {
2368                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2369                                 (int)(dev->data->port_id));
2370         }
2371         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2372                                 dev->pci_dev->addr.domain,
2373                                 dev->pci_dev->addr.bus,
2374                                 dev->pci_dev->addr.devid,
2375                                 dev->pci_dev->addr.function);
2376 }
2377
2378 /*
2379  * It executes link_update after knowing an interrupt occurred.
2380  *
2381  * @param dev
2382  *  Pointer to struct rte_eth_dev.
2383  *
2384  * @return
2385  *  - On success, zero.
2386  *  - On failure, a negative value.
2387  */
2388 static int
2389 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2390 {
2391         struct ixgbe_interrupt *intr =
2392                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2393         int64_t timeout;
2394         struct rte_eth_link link;
2395         int intr_enable_delay = false;
2396
2397         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2398
2399         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2400                 ixgbe_pf_mbx_process(dev);
2401                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2402         }
2403
2404         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2405                 /* get the link status before link update, for predicting later */
2406                 memset(&link, 0, sizeof(link));
2407                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2408
2409                 ixgbe_dev_link_update(dev, 0);
2410
2411                 /* likely to up */
2412                 if (!link.link_status)
2413                         /* handle it 1 sec later, wait it being stable */
2414                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2415                 /* likely to down */
2416                 else
2417                         /* handle it 4 sec later, wait it being stable */
2418                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2419
2420                 ixgbe_dev_link_status_print(dev);
2421
2422                 intr_enable_delay = true;
2423         }
2424
2425         if (intr_enable_delay) {
2426                 if (rte_eal_alarm_set(timeout * 1000,
2427                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2428                         PMD_DRV_LOG(ERR, "Error setting alarm");
2429         } else {
2430                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2431                 ixgbe_enable_intr(dev);
2432                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2433         }
2434
2435
2436         return 0;
2437 }
2438
2439 /**
2440  * Interrupt handler which shall be registered for alarm callback for delayed
2441  * handling specific interrupt to wait for the stable nic state. As the
2442  * NIC interrupt state is not stable for ixgbe after link is just down,
2443  * it needs to wait 4 seconds to get the stable status.
2444  *
2445  * @param handle
2446  *  Pointer to interrupt handle.
2447  * @param param
2448  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2449  *
2450  * @return
2451  *  void
2452  */
2453 static void
2454 ixgbe_dev_interrupt_delayed_handler(void *param)
2455 {
2456         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2457         struct ixgbe_interrupt *intr =
2458                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2459         struct ixgbe_hw *hw =
2460                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2461         uint32_t eicr;
2462
2463         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2464         if (eicr & IXGBE_EICR_MAILBOX)
2465                 ixgbe_pf_mbx_process(dev);
2466
2467         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2468                 ixgbe_dev_link_update(dev, 0);
2469                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2470                 ixgbe_dev_link_status_print(dev);
2471                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2472         }
2473
2474         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2475         ixgbe_enable_intr(dev);
2476         rte_intr_enable(&(dev->pci_dev->intr_handle));
2477 }
2478
2479 /**
2480  * Interrupt handler triggered by NIC  for handling
2481  * specific interrupt.
2482  *
2483  * @param handle
2484  *  Pointer to interrupt handle.
2485  * @param param
2486  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2487  *
2488  * @return
2489  *  void
2490  */
2491 static void
2492 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2493                                                         void *param)
2494 {
2495         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2496         ixgbe_dev_interrupt_get_status(dev);
2497         ixgbe_dev_interrupt_action(dev);
2498 }
2499
2500 static int
2501 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2502 {
2503         struct ixgbe_hw *hw;
2504
2505         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2506         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2507 }
2508
2509 static int
2510 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2511 {
2512         struct ixgbe_hw *hw;
2513
2514         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2515         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2516 }
2517
2518 static int
2519 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2520 {
2521         struct ixgbe_hw *hw;
2522         uint32_t mflcn_reg;
2523         uint32_t fccfg_reg;
2524         int rx_pause;
2525         int tx_pause;
2526
2527         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2528
2529         fc_conf->pause_time = hw->fc.pause_time;
2530         fc_conf->high_water = hw->fc.high_water[0];
2531         fc_conf->low_water = hw->fc.low_water[0];
2532         fc_conf->send_xon = hw->fc.send_xon;
2533         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2534
2535         /*
2536          * Return rx_pause status according to actual setting of
2537          * MFLCN register.
2538          */
2539         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2540         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2541                 rx_pause = 1;
2542         else
2543                 rx_pause = 0;
2544
2545         /*
2546          * Return tx_pause status according to actual setting of
2547          * FCCFG register.
2548          */
2549         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2550         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2551                 tx_pause = 1;
2552         else
2553                 tx_pause = 0;
2554
2555         if (rx_pause && tx_pause)
2556                 fc_conf->mode = RTE_FC_FULL;
2557         else if (rx_pause)
2558                 fc_conf->mode = RTE_FC_RX_PAUSE;
2559         else if (tx_pause)
2560                 fc_conf->mode = RTE_FC_TX_PAUSE;
2561         else
2562                 fc_conf->mode = RTE_FC_NONE;
2563
2564         return 0;
2565 }
2566
2567 static int
2568 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2569 {
2570         struct ixgbe_hw *hw;
2571         int err;
2572         uint32_t rx_buf_size;
2573         uint32_t max_high_water;
2574         uint32_t mflcn;
2575         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2576                 ixgbe_fc_none,
2577                 ixgbe_fc_rx_pause,
2578                 ixgbe_fc_tx_pause,
2579                 ixgbe_fc_full
2580         };
2581
2582         PMD_INIT_FUNC_TRACE();
2583
2584         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2585         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2586         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2587
2588         /*
2589          * At least reserve one Ethernet frame for watermark
2590          * high_water/low_water in kilo bytes for ixgbe
2591          */
2592         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2593         if ((fc_conf->high_water > max_high_water) ||
2594                 (fc_conf->high_water < fc_conf->low_water)) {
2595                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2596                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2597                 return (-EINVAL);
2598         }
2599
2600         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2601         hw->fc.pause_time     = fc_conf->pause_time;
2602         hw->fc.high_water[0]  = fc_conf->high_water;
2603         hw->fc.low_water[0]   = fc_conf->low_water;
2604         hw->fc.send_xon       = fc_conf->send_xon;
2605         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
2606
2607         err = ixgbe_fc_enable(hw);
2608
2609         /* Not negotiated is not an error case */
2610         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2611
2612                 /* check if we want to forward MAC frames - driver doesn't have native
2613                  * capability to do that, so we'll write the registers ourselves */
2614
2615                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2616
2617                 /* set or clear MFLCN.PMCF bit depending on configuration */
2618                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2619                         mflcn |= IXGBE_MFLCN_PMCF;
2620                 else
2621                         mflcn &= ~IXGBE_MFLCN_PMCF;
2622
2623                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2624                 IXGBE_WRITE_FLUSH(hw);
2625
2626                 return 0;
2627         }
2628
2629         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2630         return -EIO;
2631 }
2632
2633 /**
2634  *  ixgbe_pfc_enable_generic - Enable flow control
2635  *  @hw: pointer to hardware structure
2636  *  @tc_num: traffic class number
2637  *  Enable flow control according to the current settings.
2638  */
2639 static int
2640 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2641 {
2642         int ret_val = 0;
2643         uint32_t mflcn_reg, fccfg_reg;
2644         uint32_t reg;
2645         uint32_t fcrtl, fcrth;
2646         uint8_t i;
2647         uint8_t nb_rx_en;
2648
2649         /* Validate the water mark configuration */
2650         if (!hw->fc.pause_time) {
2651                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2652                 goto out;
2653         }
2654
2655         /* Low water mark of zero causes XOFF floods */
2656         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2657                  /* High/Low water can not be 0 */
2658                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2659                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2660                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2661                         goto out;
2662                 }
2663
2664                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2665                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2666                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2667                         goto out;
2668                 }
2669         }
2670         /* Negotiate the fc mode to use */
2671         ixgbe_fc_autoneg(hw);
2672
2673         /* Disable any previous flow control settings */
2674         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2675         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2676
2677         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2678         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2679
2680         switch (hw->fc.current_mode) {
2681         case ixgbe_fc_none:
2682                 /*
2683                  * If the count of enabled RX Priority Flow control >1,
2684                  * and the TX pause can not be disabled
2685                  */
2686                 nb_rx_en = 0;
2687                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2688                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2689                         if (reg & IXGBE_FCRTH_FCEN)
2690                                 nb_rx_en++;
2691                 }
2692                 if (nb_rx_en > 1)
2693                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2694                 break;
2695         case ixgbe_fc_rx_pause:
2696                 /*
2697                  * Rx Flow control is enabled and Tx Flow control is
2698                  * disabled by software override. Since there really
2699                  * isn't a way to advertise that we are capable of RX
2700                  * Pause ONLY, we will advertise that we support both
2701                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2702                  * disable the adapter's ability to send PAUSE frames.
2703                  */
2704                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2705                 /*
2706                  * If the count of enabled RX Priority Flow control >1,
2707                  * and the TX pause can not be disabled
2708                  */
2709                 nb_rx_en = 0;
2710                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2711                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2712                         if (reg & IXGBE_FCRTH_FCEN)
2713                                 nb_rx_en++;
2714                 }
2715                 if (nb_rx_en > 1)
2716                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2717                 break;
2718         case ixgbe_fc_tx_pause:
2719                 /*
2720                  * Tx Flow control is enabled, and Rx Flow control is
2721                  * disabled by software override.
2722                  */
2723                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2724                 break;
2725         case ixgbe_fc_full:
2726                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2727                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2728                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2729                 break;
2730         default:
2731                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2732                 ret_val = IXGBE_ERR_CONFIG;
2733                 goto out;
2734                 break;
2735         }
2736
2737         /* Set 802.3x based flow control settings. */
2738         mflcn_reg |= IXGBE_MFLCN_DPF;
2739         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2740         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2741
2742         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2743         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2744                 hw->fc.high_water[tc_num]) {
2745                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2746                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2747                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2748         } else {
2749                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2750                 /*
2751                  * In order to prevent Tx hangs when the internal Tx
2752                  * switch is enabled we must set the high water mark
2753                  * to the maximum FCRTH value.  This allows the Tx
2754                  * switch to function even under heavy Rx workloads.
2755                  */
2756                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2757         }
2758         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2759
2760         /* Configure pause time (2 TCs per register) */
2761         reg = hw->fc.pause_time * 0x00010001;
2762         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2763                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2764
2765         /* Configure flow control refresh threshold value */
2766         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2767
2768 out:
2769         return ret_val;
2770 }
2771
2772 static int
2773 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2774 {
2775         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2776         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2777
2778         if(hw->mac.type != ixgbe_mac_82598EB) {
2779                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2780         }
2781         return ret_val;
2782 }
2783
2784 static int
2785 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2786 {
2787         int err;
2788         uint32_t rx_buf_size;
2789         uint32_t max_high_water;
2790         uint8_t tc_num;
2791         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2792         struct ixgbe_hw *hw =
2793                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2794         struct ixgbe_dcb_config *dcb_config =
2795                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2796
2797         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2798                 ixgbe_fc_none,
2799                 ixgbe_fc_rx_pause,
2800                 ixgbe_fc_tx_pause,
2801                 ixgbe_fc_full
2802         };
2803
2804         PMD_INIT_FUNC_TRACE();
2805
2806         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2807         tc_num = map[pfc_conf->priority];
2808         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2809         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2810         /*
2811          * At least reserve one Ethernet frame for watermark
2812          * high_water/low_water in kilo bytes for ixgbe
2813          */
2814         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2815         if ((pfc_conf->fc.high_water > max_high_water) ||
2816             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2817                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2818                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2819                 return (-EINVAL);
2820         }
2821
2822         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2823         hw->fc.pause_time = pfc_conf->fc.pause_time;
2824         hw->fc.send_xon = pfc_conf->fc.send_xon;
2825         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2826         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2827
2828         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2829
2830         /* Not negotiated is not an error case */
2831         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2832                 return 0;
2833
2834         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2835         return -EIO;
2836 }
2837
2838 static int
2839 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2840                           struct rte_eth_rss_reta_entry64 *reta_conf,
2841                           uint16_t reta_size)
2842 {
2843         uint8_t i, j, mask;
2844         uint32_t reta, r;
2845         uint16_t idx, shift;
2846         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2847
2848         PMD_INIT_FUNC_TRACE();
2849         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2850                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2851                         "(%d) doesn't match the number hardware can supported "
2852                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2853                 return -EINVAL;
2854         }
2855
2856         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2857                 idx = i / RTE_RETA_GROUP_SIZE;
2858                 shift = i % RTE_RETA_GROUP_SIZE;
2859                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2860                                                 IXGBE_4_BIT_MASK);
2861                 if (!mask)
2862                         continue;
2863                 if (mask == IXGBE_4_BIT_MASK)
2864                         r = 0;
2865                 else
2866                         r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2867                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2868                         if (mask & (0x1 << j))
2869                                 reta |= reta_conf[idx].reta[shift + j] <<
2870                                                         (CHAR_BIT * j);
2871                         else
2872                                 reta |= r & (IXGBE_8_BIT_MASK <<
2873                                                 (CHAR_BIT * j));
2874                 }
2875                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2876         }
2877
2878         return 0;
2879 }
2880
2881 static int
2882 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2883                          struct rte_eth_rss_reta_entry64 *reta_conf,
2884                          uint16_t reta_size)
2885 {
2886         uint8_t i, j, mask;
2887         uint32_t reta;
2888         uint16_t idx, shift;
2889         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2890
2891         PMD_INIT_FUNC_TRACE();
2892         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2893                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2894                         "(%d) doesn't match the number hardware can supported "
2895                                 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2896                 return -EINVAL;
2897         }
2898
2899         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2900                 idx = i / RTE_RETA_GROUP_SIZE;
2901                 shift = i % RTE_RETA_GROUP_SIZE;
2902                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2903                                                 IXGBE_4_BIT_MASK);
2904                 if (!mask)
2905                         continue;
2906
2907                 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2908                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2909                         if (mask & (0x1 << j))
2910                                 reta_conf[idx].reta[shift + j] =
2911                                         ((reta >> (CHAR_BIT * j)) &
2912                                                 IXGBE_8_BIT_MASK);
2913                 }
2914         }
2915
2916         return 0;
2917 }
2918
2919 static void
2920 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2921                                 uint32_t index, uint32_t pool)
2922 {
2923         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2924         uint32_t enable_addr = 1;
2925
2926         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2927 }
2928
2929 static void
2930 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2931 {
2932         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2933
2934         ixgbe_clear_rar(hw, index);
2935 }
2936
2937 static void
2938 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
2939 {
2940         ixgbe_remove_rar(dev, 0);
2941
2942         ixgbe_add_rar(dev, addr, 0, 0);
2943 }
2944
2945 static int
2946 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2947 {
2948         uint32_t hlreg0;
2949         uint32_t maxfrs;
2950         struct ixgbe_hw *hw;
2951         struct rte_eth_dev_info dev_info;
2952         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2953
2954         ixgbe_dev_info_get(dev, &dev_info);
2955
2956         /* check that mtu is within the allowed range */
2957         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2958                 return -EINVAL;
2959
2960         /* refuse mtu that requires the support of scattered packets when this
2961          * feature has not been enabled before. */
2962         if (!dev->data->scattered_rx &&
2963             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2964              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2965                 return -EINVAL;
2966
2967         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2968         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2969
2970         /* switch to jumbo mode if needed */
2971         if (frame_size > ETHER_MAX_LEN) {
2972                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2973                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2974         } else {
2975                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2976                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2977         }
2978         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2979
2980         /* update max frame size */
2981         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2982
2983         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2984         maxfrs &= 0x0000FFFF;
2985         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2986         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2987
2988         return 0;
2989 }
2990
2991 /*
2992  * Virtual Function operations
2993  */
2994 static void
2995 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2996 {
2997         PMD_INIT_FUNC_TRACE();
2998
2999         /* Clear interrupt mask to stop from interrupts being generated */
3000         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3001
3002         IXGBE_WRITE_FLUSH(hw);
3003 }
3004
3005 static int
3006 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3007 {
3008         struct rte_eth_conf* conf = &dev->data->dev_conf;
3009         struct ixgbe_adapter *adapter =
3010                         (struct ixgbe_adapter *)dev->data->dev_private;
3011
3012         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3013                      dev->data->port_id);
3014
3015         /*
3016          * VF has no ability to enable/disable HW CRC
3017          * Keep the persistent behavior the same as Host PF
3018          */
3019 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3020         if (!conf->rxmode.hw_strip_crc) {
3021                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
3022                 conf->rxmode.hw_strip_crc = 1;
3023         }
3024 #else
3025         if (conf->rxmode.hw_strip_crc) {
3026                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
3027                 conf->rxmode.hw_strip_crc = 0;
3028         }
3029 #endif
3030
3031         /*
3032          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3033          * allocation or vector Rx preconditions we will reset it.
3034          */
3035         adapter->rx_bulk_alloc_allowed = true;
3036         adapter->rx_vec_allowed = true;
3037
3038         return 0;
3039 }
3040
3041 static int
3042 ixgbevf_dev_start(struct rte_eth_dev *dev)
3043 {
3044         struct ixgbe_hw *hw =
3045                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3046         int err, mask = 0;
3047
3048         PMD_INIT_FUNC_TRACE();
3049
3050         hw->mac.ops.reset_hw(hw);
3051         hw->mac.get_link_status = true;
3052
3053         /* negotiate mailbox API version to use with the PF. */
3054         ixgbevf_negotiate_api(hw);
3055
3056         ixgbevf_dev_tx_init(dev);
3057
3058         /* This can fail when allocating mbufs for descriptor rings */
3059         err = ixgbevf_dev_rx_init(dev);
3060         if (err) {
3061                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3062                 ixgbe_dev_clear_queues(dev);
3063                 return err;
3064         }
3065
3066         /* Set vfta */
3067         ixgbevf_set_vfta_all(dev,1);
3068
3069         /* Set HW strip */
3070         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3071                 ETH_VLAN_EXTEND_MASK;
3072         ixgbevf_vlan_offload_set(dev, mask);
3073
3074         ixgbevf_dev_rxtx_start(dev);
3075
3076         return 0;
3077 }
3078
3079 static void
3080 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3081 {
3082         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3083
3084         PMD_INIT_FUNC_TRACE();
3085
3086         hw->adapter_stopped = TRUE;
3087         ixgbe_stop_adapter(hw);
3088
3089         /*
3090           * Clear what we set, but we still keep shadow_vfta to
3091           * restore after device starts
3092           */
3093         ixgbevf_set_vfta_all(dev,0);
3094
3095         /* Clear stored conf */
3096         dev->data->scattered_rx = 0;
3097
3098         ixgbe_dev_clear_queues(dev);
3099 }
3100
3101 static void
3102 ixgbevf_dev_close(struct rte_eth_dev *dev)
3103 {
3104         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3105
3106         PMD_INIT_FUNC_TRACE();
3107
3108         ixgbe_reset_hw(hw);
3109
3110         ixgbevf_dev_stop(dev);
3111
3112         /* reprogram the RAR[0] in case user changed it. */
3113         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3114 }
3115
3116 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3117 {
3118         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3119         struct ixgbe_vfta * shadow_vfta =
3120                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3121         int i = 0, j = 0, vfta = 0, mask = 1;
3122
3123         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3124                 vfta = shadow_vfta->vfta[i];
3125                 if(vfta){
3126                         mask = 1;
3127                         for (j = 0; j < 32; j++){
3128                                 if(vfta & mask)
3129                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3130                                 mask<<=1;
3131                         }
3132                 }
3133         }
3134
3135 }
3136
3137 static int
3138 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3139 {
3140         struct ixgbe_hw *hw =
3141                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3142         struct ixgbe_vfta * shadow_vfta =
3143                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3144         uint32_t vid_idx = 0;
3145         uint32_t vid_bit = 0;
3146         int ret = 0;
3147
3148         PMD_INIT_FUNC_TRACE();
3149
3150         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3151         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3152         if(ret){
3153                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3154                 return ret;
3155         }
3156         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3157         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3158
3159         /* Save what we set and retore it after device reset */
3160         if (on)
3161                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3162         else
3163                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3164
3165         return 0;
3166 }
3167
3168 static void
3169 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3170 {
3171         struct ixgbe_hw *hw =
3172                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3173         uint32_t ctrl;
3174
3175         PMD_INIT_FUNC_TRACE();
3176
3177         if(queue >= hw->mac.max_rx_queues)
3178                 return;
3179
3180         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3181         if(on)
3182                 ctrl |= IXGBE_RXDCTL_VME;
3183         else
3184                 ctrl &= ~IXGBE_RXDCTL_VME;
3185         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3186
3187         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3188 }
3189
3190 static void
3191 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3192 {
3193         struct ixgbe_hw *hw =
3194                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3195         uint16_t i;
3196         int on = 0;
3197
3198         /* VF function only support hw strip feature, others are not support */
3199         if(mask & ETH_VLAN_STRIP_MASK){
3200                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3201
3202                 for(i=0; i < hw->mac.max_rx_queues; i++)
3203                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3204         }
3205 }
3206
3207 static int
3208 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3209 {
3210         uint32_t reg_val;
3211
3212         /* we only need to do this if VMDq is enabled */
3213         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3214         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3215                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3216                 return (-1);
3217         }
3218
3219         return 0;
3220 }
3221
3222 static uint32_t
3223 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3224 {
3225         uint32_t vector = 0;
3226         switch (hw->mac.mc_filter_type) {
3227         case 0:   /* use bits [47:36] of the address */
3228                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3229                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3230                 break;
3231         case 1:   /* use bits [46:35] of the address */
3232                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3233                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3234                 break;
3235         case 2:   /* use bits [45:34] of the address */
3236                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3237                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3238                 break;
3239         case 3:   /* use bits [43:32] of the address */
3240                 vector = ((uc_addr->addr_bytes[4]) |
3241                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3242                 break;
3243         default:  /* Invalid mc_filter_type */
3244                 break;
3245         }
3246
3247         /* vector can only be 12-bits or boundary will be exceeded */
3248         vector &= 0xFFF;
3249         return vector;
3250 }
3251
3252 static int
3253 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3254                                uint8_t on)
3255 {
3256         uint32_t vector;
3257         uint32_t uta_idx;
3258         uint32_t reg_val;
3259         uint32_t uta_shift;
3260         uint32_t rc;
3261         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3262         const uint32_t ixgbe_uta_bit_shift = 5;
3263         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3264         const uint32_t bit1 = 0x1;
3265
3266         struct ixgbe_hw *hw =
3267                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3268         struct ixgbe_uta_info *uta_info =
3269                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3270
3271         /* The UTA table only exists on 82599 hardware and newer */
3272         if (hw->mac.type < ixgbe_mac_82599EB)
3273                 return (-ENOTSUP);
3274
3275         vector = ixgbe_uta_vector(hw,mac_addr);
3276         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3277         uta_shift = vector & ixgbe_uta_bit_mask;
3278
3279         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3280         if(rc == on)
3281                 return 0;
3282
3283         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3284         if (on) {
3285                 uta_info->uta_in_use++;
3286                 reg_val |= (bit1 << uta_shift);
3287                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3288         } else {
3289                 uta_info->uta_in_use--;
3290                 reg_val &= ~(bit1 << uta_shift);
3291                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3292         }
3293
3294         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3295
3296         if (uta_info->uta_in_use > 0)
3297                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3298                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3299         else
3300                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3301
3302         return 0;
3303 }
3304
3305 static int
3306 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3307 {
3308         int i;
3309         struct ixgbe_hw *hw =
3310                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3311         struct ixgbe_uta_info *uta_info =
3312                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3313
3314         /* The UTA table only exists on 82599 hardware and newer */
3315         if (hw->mac.type < ixgbe_mac_82599EB)
3316                 return (-ENOTSUP);
3317
3318         if(on) {
3319                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3320                         uta_info->uta_shadow[i] = ~0;
3321                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3322                 }
3323         } else {
3324                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3325                         uta_info->uta_shadow[i] = 0;
3326                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3327                 }
3328         }
3329         return 0;
3330
3331 }
3332
3333 uint32_t
3334 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3335 {
3336         uint32_t new_val = orig_val;
3337
3338         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3339                 new_val |= IXGBE_VMOLR_AUPE;
3340         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3341                 new_val |= IXGBE_VMOLR_ROMPE;
3342         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3343                 new_val |= IXGBE_VMOLR_ROPE;
3344         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3345                 new_val |= IXGBE_VMOLR_BAM;
3346         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3347                 new_val |= IXGBE_VMOLR_MPE;
3348
3349         return new_val;
3350 }
3351
3352 static int
3353 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3354                                uint16_t rx_mask, uint8_t on)
3355 {
3356         int val = 0;
3357
3358         struct ixgbe_hw *hw =
3359                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3360         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3361
3362         if (hw->mac.type == ixgbe_mac_82598EB) {
3363                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3364                              " on 82599 hardware and newer");
3365                 return (-ENOTSUP);
3366         }
3367         if (ixgbe_vmdq_mode_check(hw) < 0)
3368                 return (-ENOTSUP);
3369
3370         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3371
3372         if (on)
3373                 vmolr |= val;
3374         else
3375                 vmolr &= ~val;
3376
3377         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3378
3379         return 0;
3380 }
3381
3382 static int
3383 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3384 {
3385         uint32_t reg,addr;
3386         uint32_t val;
3387         const uint8_t bit1 = 0x1;
3388
3389         struct ixgbe_hw *hw =
3390                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3391
3392         if (ixgbe_vmdq_mode_check(hw) < 0)
3393                 return (-ENOTSUP);
3394
3395         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3396         reg = IXGBE_READ_REG(hw, addr);
3397         val = bit1 << pool;
3398
3399         if (on)
3400                 reg |= val;
3401         else
3402                 reg &= ~val;
3403
3404         IXGBE_WRITE_REG(hw, addr,reg);
3405
3406         return 0;
3407 }
3408
3409 static int
3410 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3411 {
3412         uint32_t reg,addr;
3413         uint32_t val;
3414         const uint8_t bit1 = 0x1;
3415
3416         struct ixgbe_hw *hw =
3417                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3418
3419         if (ixgbe_vmdq_mode_check(hw) < 0)
3420                 return (-ENOTSUP);
3421
3422         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3423         reg = IXGBE_READ_REG(hw, addr);
3424         val = bit1 << pool;
3425
3426         if (on)
3427                 reg |= val;
3428         else
3429                 reg &= ~val;
3430
3431         IXGBE_WRITE_REG(hw, addr,reg);
3432
3433         return 0;
3434 }
3435
3436 static int
3437 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3438                         uint64_t pool_mask, uint8_t vlan_on)
3439 {
3440         int ret = 0;
3441         uint16_t pool_idx;
3442         struct ixgbe_hw *hw =
3443                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3444
3445         if (ixgbe_vmdq_mode_check(hw) < 0)
3446                 return (-ENOTSUP);
3447         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3448                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3449                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3450                         if (ret < 0)
3451                                 return ret;
3452         }
3453
3454         return ret;
3455 }
3456
3457 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
3458 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
3459 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
3460 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
3461 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
3462         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
3463         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
3464
3465 static int
3466 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3467                         struct rte_eth_mirror_conf *mirror_conf,
3468                         uint8_t rule_id, uint8_t on)
3469 {
3470         uint32_t mr_ctl,vlvf;
3471         uint32_t mp_lsb = 0;
3472         uint32_t mv_msb = 0;
3473         uint32_t mv_lsb = 0;
3474         uint32_t mp_msb = 0;
3475         uint8_t i = 0;
3476         int reg_index = 0;
3477         uint64_t vlan_mask = 0;
3478
3479         const uint8_t pool_mask_offset = 32;
3480         const uint8_t vlan_mask_offset = 32;
3481         const uint8_t dst_pool_offset = 8;
3482         const uint8_t rule_mr_offset  = 4;
3483         const uint8_t mirror_rule_mask= 0x0F;
3484
3485         struct ixgbe_mirror_info *mr_info =
3486                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3487         struct ixgbe_hw *hw =
3488                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3489         uint8_t mirror_type = 0;
3490
3491         if (ixgbe_vmdq_mode_check(hw) < 0)
3492                 return -ENOTSUP;
3493
3494         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
3495                 return -EINVAL;
3496
3497         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
3498                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
3499                         mirror_conf->rule_type);
3500                 return -EINVAL;
3501         }
3502
3503         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
3504                 mirror_type |= IXGBE_MRCTL_VLME;
3505                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3506                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3507                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3508                                 /* search vlan id related pool vlan filter index */
3509                                 reg_index = ixgbe_find_vlvf_slot(hw,
3510                                                 mirror_conf->vlan.vlan_id[i]);
3511                                 if(reg_index < 0)
3512                                         return -EINVAL;
3513                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3514                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3515                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
3516                                       mirror_conf->vlan.vlan_id[i]))
3517                                         vlan_mask |= (1ULL << reg_index);
3518                                 else
3519                                         return -EINVAL;
3520                         }
3521                 }
3522
3523                 if (on) {
3524                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3525                         mv_msb = vlan_mask >> vlan_mask_offset;
3526
3527                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3528                                                 mirror_conf->vlan.vlan_mask;
3529                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3530                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3531                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3532                                                 mirror_conf->vlan.vlan_id[i];
3533                         }
3534                 } else {
3535                         mv_lsb = 0;
3536                         mv_msb = 0;
3537                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3538                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3539                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3540                 }
3541         }
3542
3543         /*
3544          * if enable pool mirror, write related pool mask register,if disable
3545          * pool mirror, clear PFMRVM register
3546          */
3547         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
3548                 mirror_type |= IXGBE_MRCTL_VPME;
3549                 if (on) {
3550                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3551                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3552                         mr_info->mr_conf[rule_id].pool_mask =
3553                                         mirror_conf->pool_mask;
3554
3555                 } else {
3556                         mp_lsb = 0;
3557                         mp_msb = 0;
3558                         mr_info->mr_conf[rule_id].pool_mask = 0;
3559                 }
3560         }
3561         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
3562                 mirror_type |= IXGBE_MRCTL_UPME;
3563         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
3564                 mirror_type |= IXGBE_MRCTL_DPME;
3565
3566         /* read  mirror control register and recalculate it */
3567         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
3568
3569         if (on) {
3570                 mr_ctl |= mirror_type;
3571                 mr_ctl &= mirror_rule_mask;
3572                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3573         } else
3574                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
3575
3576         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
3577         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3578
3579         /* write mirrror control  register */
3580         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3581
3582         /* write pool mirrror control  register */
3583         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
3584                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3585                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3586                                 mp_msb);
3587         }
3588         /* write VLAN mirrror control  register */
3589         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
3590                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3591                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3592                                 mv_msb);
3593         }
3594
3595         return 0;
3596 }
3597
3598 static int
3599 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3600 {
3601         int mr_ctl = 0;
3602         uint32_t lsb_val = 0;
3603         uint32_t msb_val = 0;
3604         const uint8_t rule_mr_offset = 4;
3605
3606         struct ixgbe_hw *hw =
3607                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3608         struct ixgbe_mirror_info *mr_info =
3609                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3610
3611         if (ixgbe_vmdq_mode_check(hw) < 0)
3612                 return (-ENOTSUP);
3613
3614         memset(&mr_info->mr_conf[rule_id], 0,
3615                 sizeof(struct rte_eth_mirror_conf));
3616
3617         /* clear PFVMCTL register */
3618         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3619
3620         /* clear pool mask register */
3621         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3622         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3623
3624         /* clear vlan mask register */
3625         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3626         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3627
3628         return 0;
3629 }
3630
3631 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3632         uint16_t queue_idx, uint16_t tx_rate)
3633 {
3634         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3635         uint32_t rf_dec, rf_int;
3636         uint32_t bcnrc_val;
3637         uint16_t link_speed = dev->data->dev_link.link_speed;
3638
3639         if (queue_idx >= hw->mac.max_tx_queues)
3640                 return -EINVAL;
3641
3642         if (tx_rate != 0) {
3643                 /* Calculate the rate factor values to set */
3644                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3645                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3646                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3647
3648                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3649                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3650                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3651                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3652         } else {
3653                 bcnrc_val = 0;
3654         }
3655
3656         /*
3657          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3658          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3659          * set as 0x4.
3660          */
3661         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3662                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3663                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3664                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3665                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3666         else
3667                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3668                         IXGBE_MMW_SIZE_DEFAULT);
3669
3670         /* Set RTTBCNRC of queue X */
3671         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3672         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3673         IXGBE_WRITE_FLUSH(hw);
3674
3675         return 0;
3676 }
3677
3678 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3679         uint16_t tx_rate, uint64_t q_msk)
3680 {
3681         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3682         struct ixgbe_vf_info *vfinfo =
3683                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3684         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3685         uint32_t queue_stride =
3686                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3687         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3688         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3689         uint16_t total_rate = 0;
3690
3691         if (queue_end >= hw->mac.max_tx_queues)
3692                 return -EINVAL;
3693
3694         if (vfinfo != NULL) {
3695                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3696                         if (vf_idx == vf)
3697                                 continue;
3698                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3699                                 idx++)
3700                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3701                 }
3702         } else
3703                 return -EINVAL;
3704
3705         /* Store tx_rate for this vf. */
3706         for (idx = 0; idx < nb_q_per_pool; idx++) {
3707                 if (((uint64_t)0x1 << idx) & q_msk) {
3708                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3709                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3710                         total_rate += tx_rate;
3711                 }
3712         }
3713
3714         if (total_rate > dev->data->dev_link.link_speed) {
3715                 /*
3716                  * Reset stored TX rate of the VF if it causes exceed
3717                  * link speed.
3718                  */
3719                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3720                 return -EINVAL;
3721         }
3722
3723         /* Set RTTBCNRC of each queue/pool for vf X  */
3724         for (; queue_idx <= queue_end; queue_idx++) {
3725                 if (0x1 & q_msk)
3726                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3727                 q_msk = q_msk >> 1;
3728         }
3729
3730         return 0;
3731 }
3732
3733 static void
3734 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3735                      __attribute__((unused)) uint32_t index,
3736                      __attribute__((unused)) uint32_t pool)
3737 {
3738         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3739         int diag;
3740
3741         /*
3742          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3743          * operation. Trap this case to avoid exhausting the [very limited]
3744          * set of PF resources used to store VF MAC addresses.
3745          */
3746         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3747                 return;
3748         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3749         if (diag == 0)
3750                 return;
3751         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3752 }
3753
3754 static void
3755 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3756 {
3757         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3758         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3759         struct ether_addr *mac_addr;
3760         uint32_t i;
3761         int diag;
3762
3763         /*
3764          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3765          * not support the deletion of a given MAC address.
3766          * Instead, it imposes to delete all MAC addresses, then to add again
3767          * all MAC addresses with the exception of the one to be deleted.
3768          */
3769         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3770
3771         /*
3772          * Add again all MAC addresses, with the exception of the deleted one
3773          * and of the permanent MAC address.
3774          */
3775         for (i = 0, mac_addr = dev->data->mac_addrs;
3776              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3777                 /* Skip the deleted MAC address */
3778                 if (i == index)
3779                         continue;
3780                 /* Skip NULL MAC addresses */
3781                 if (is_zero_ether_addr(mac_addr))
3782                         continue;
3783                 /* Skip the permanent MAC address */
3784                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3785                         continue;
3786                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3787                 if (diag != 0)
3788                         PMD_DRV_LOG(ERR,
3789                                     "Adding again MAC address "
3790                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3791                                     "diag=%d",
3792                                     mac_addr->addr_bytes[0],
3793                                     mac_addr->addr_bytes[1],
3794                                     mac_addr->addr_bytes[2],
3795                                     mac_addr->addr_bytes[3],
3796                                     mac_addr->addr_bytes[4],
3797                                     mac_addr->addr_bytes[5],
3798                                     diag);
3799         }
3800 }
3801
3802 static void
3803 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3804 {
3805         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3806
3807         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
3808 }
3809
3810 #define MAC_TYPE_FILTER_SUP(type)    do {\
3811         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
3812                 (type) != ixgbe_mac_X550)\
3813                 return -ENOTSUP;\
3814 } while (0)
3815
3816 static int
3817 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
3818                         struct rte_eth_syn_filter *filter,
3819                         bool add)
3820 {
3821         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3822         uint32_t synqf;
3823
3824         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
3825                 return -EINVAL;
3826
3827         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3828
3829         if (add) {
3830                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
3831                         return -EINVAL;
3832                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3833                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3834
3835                 if (filter->hig_pri)
3836                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
3837                 else
3838                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3839         } else {
3840                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
3841                         return -ENOENT;
3842                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3843         }
3844         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3845         IXGBE_WRITE_FLUSH(hw);
3846         return 0;
3847 }
3848
3849 static int
3850 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
3851                         struct rte_eth_syn_filter *filter)
3852 {
3853         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3854         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3855
3856         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3857                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3858                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3859                 return 0;
3860         }
3861         return -ENOENT;
3862 }
3863
3864 static int
3865 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
3866                         enum rte_filter_op filter_op,
3867                         void *arg)
3868 {
3869         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3870         int ret;
3871
3872         MAC_TYPE_FILTER_SUP(hw->mac.type);
3873
3874         if (filter_op == RTE_ETH_FILTER_NOP)
3875                 return 0;
3876
3877         if (arg == NULL) {
3878                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3879                             filter_op);
3880                 return -EINVAL;
3881         }
3882
3883         switch (filter_op) {
3884         case RTE_ETH_FILTER_ADD:
3885                 ret = ixgbe_syn_filter_set(dev,
3886                                 (struct rte_eth_syn_filter *)arg,
3887                                 TRUE);
3888                 break;
3889         case RTE_ETH_FILTER_DELETE:
3890                 ret = ixgbe_syn_filter_set(dev,
3891                                 (struct rte_eth_syn_filter *)arg,
3892                                 FALSE);
3893                 break;
3894         case RTE_ETH_FILTER_GET:
3895                 ret = ixgbe_syn_filter_get(dev,
3896                                 (struct rte_eth_syn_filter *)arg);
3897                 break;
3898         default:
3899                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3900                 ret = -EINVAL;
3901                 break;
3902         }
3903
3904         return ret;
3905 }
3906
3907
3908 static inline enum ixgbe_5tuple_protocol
3909 convert_protocol_type(uint8_t protocol_value)
3910 {
3911         if (protocol_value == IPPROTO_TCP)
3912                 return IXGBE_FILTER_PROTOCOL_TCP;
3913         else if (protocol_value == IPPROTO_UDP)
3914                 return IXGBE_FILTER_PROTOCOL_UDP;
3915         else if (protocol_value == IPPROTO_SCTP)
3916                 return IXGBE_FILTER_PROTOCOL_SCTP;
3917         else
3918                 return IXGBE_FILTER_PROTOCOL_NONE;
3919 }
3920
3921 /*
3922  * add a 5tuple filter
3923  *
3924  * @param
3925  * dev: Pointer to struct rte_eth_dev.
3926  * index: the index the filter allocates.
3927  * filter: ponter to the filter that will be added.
3928  * rx_queue: the queue id the filter assigned to.
3929  *
3930  * @return
3931  *    - On success, zero.
3932  *    - On failure, a negative value.
3933  */
3934 static int
3935 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3936                         struct ixgbe_5tuple_filter *filter)
3937 {
3938         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3939         struct ixgbe_filter_info *filter_info =
3940                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3941         int i, idx, shift;
3942         uint32_t ftqf, sdpqf;
3943         uint32_t l34timir = 0;
3944         uint8_t mask = 0xff;
3945
3946         /*
3947          * look for an unused 5tuple filter index,
3948          * and insert the filter to list.
3949          */
3950         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
3951                 idx = i / (sizeof(uint32_t) * NBBY);
3952                 shift = i % (sizeof(uint32_t) * NBBY);
3953                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3954                         filter_info->fivetuple_mask[idx] |= 1 << shift;
3955                         filter->index = i;
3956                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3957                                           filter,
3958                                           entries);
3959                         break;
3960                 }
3961         }
3962         if (i >= IXGBE_MAX_FTQF_FILTERS) {
3963                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3964                 return -ENOSYS;
3965         }
3966
3967         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
3968                                 IXGBE_SDPQF_DSTPORT_SHIFT);
3969         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
3970
3971         ftqf = (uint32_t)(filter->filter_info.proto &
3972                 IXGBE_FTQF_PROTOCOL_MASK);
3973         ftqf |= (uint32_t)((filter->filter_info.priority &
3974                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
3975         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3976                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3977         if (filter->filter_info.dst_ip_mask == 0)
3978                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3979         if (filter->filter_info.src_port_mask == 0)
3980                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3981         if (filter->filter_info.dst_port_mask == 0)
3982                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3983         if (filter->filter_info.proto_mask == 0)
3984                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3985         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3986         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3987         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3988
3989         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
3990         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
3991         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
3992         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
3993
3994         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3995         l34timir |= (uint32_t)(filter->queue <<
3996                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
3997         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
3998         return 0;
3999 }
4000
4001 /*
4002  * remove a 5tuple filter
4003  *
4004  * @param
4005  * dev: Pointer to struct rte_eth_dev.
4006  * filter: the pointer of the filter will be removed.
4007  */
4008 static void
4009 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
4010                         struct ixgbe_5tuple_filter *filter)
4011 {
4012         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4013         struct ixgbe_filter_info *filter_info =
4014                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4015         uint16_t index = filter->index;
4016
4017         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
4018                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
4019         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4020         rte_free(filter);
4021
4022         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
4023         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
4024         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
4025         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
4026         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
4027 }
4028
4029 static int
4030 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
4031 {
4032         struct ixgbe_hw *hw;
4033         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4034
4035         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4036
4037         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
4038                 return -EINVAL;
4039
4040         /* refuse mtu that requires the support of scattered packets when this
4041          * feature has not been enabled before. */
4042         if (!dev->data->scattered_rx &&
4043             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
4044              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4045                 return -EINVAL;
4046
4047         /*
4048          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
4049          * request of the version 2.0 of the mailbox API.
4050          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
4051          * of the mailbox API.
4052          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
4053          * prior to 3.11.33 which contains the following change:
4054          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4055          */
4056         ixgbevf_rlpml_set_vf(hw, max_frame);
4057
4058         /* update max frame size */
4059         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4060         return 0;
4061 }
4062
4063 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
4064         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
4065                 return -ENOTSUP;\
4066 } while (0)
4067
4068 static inline struct ixgbe_5tuple_filter *
4069 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
4070                         struct ixgbe_5tuple_filter_info *key)
4071 {
4072         struct ixgbe_5tuple_filter *it;
4073
4074         TAILQ_FOREACH(it, filter_list, entries) {
4075                 if (memcmp(key, &it->filter_info,
4076                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
4077                         return it;
4078                 }
4079         }
4080         return NULL;
4081 }
4082
4083 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
4084 static inline int
4085 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
4086                         struct ixgbe_5tuple_filter_info *filter_info)
4087 {
4088         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
4089                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
4090                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
4091                 return -EINVAL;
4092
4093         switch (filter->dst_ip_mask) {
4094         case UINT32_MAX:
4095                 filter_info->dst_ip_mask = 0;
4096                 filter_info->dst_ip = filter->dst_ip;
4097                 break;
4098         case 0:
4099                 filter_info->dst_ip_mask = 1;
4100                 break;
4101         default:
4102                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4103                 return -EINVAL;
4104         }
4105
4106         switch (filter->src_ip_mask) {
4107         case UINT32_MAX:
4108                 filter_info->src_ip_mask = 0;
4109                 filter_info->src_ip = filter->src_ip;
4110                 break;
4111         case 0:
4112                 filter_info->src_ip_mask = 1;
4113                 break;
4114         default:
4115                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4116                 return -EINVAL;
4117         }
4118
4119         switch (filter->dst_port_mask) {
4120         case UINT16_MAX:
4121                 filter_info->dst_port_mask = 0;
4122                 filter_info->dst_port = filter->dst_port;
4123                 break;
4124         case 0:
4125                 filter_info->dst_port_mask = 1;
4126                 break;
4127         default:
4128                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4129                 return -EINVAL;
4130         }
4131
4132         switch (filter->src_port_mask) {
4133         case UINT16_MAX:
4134                 filter_info->src_port_mask = 0;
4135                 filter_info->src_port = filter->src_port;
4136                 break;
4137         case 0:
4138                 filter_info->src_port_mask = 1;
4139                 break;
4140         default:
4141                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4142                 return -EINVAL;
4143         }
4144
4145         switch (filter->proto_mask) {
4146         case UINT8_MAX:
4147                 filter_info->proto_mask = 0;
4148                 filter_info->proto =
4149                         convert_protocol_type(filter->proto);
4150                 break;
4151         case 0:
4152                 filter_info->proto_mask = 1;
4153                 break;
4154         default:
4155                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4156                 return -EINVAL;
4157         }
4158
4159         filter_info->priority = (uint8_t)filter->priority;
4160         return 0;
4161 }
4162
4163 /*
4164  * add or delete a ntuple filter
4165  *
4166  * @param
4167  * dev: Pointer to struct rte_eth_dev.
4168  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4169  * add: if true, add filter, if false, remove filter
4170  *
4171  * @return
4172  *    - On success, zero.
4173  *    - On failure, a negative value.
4174  */
4175 static int
4176 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4177                         struct rte_eth_ntuple_filter *ntuple_filter,
4178                         bool add)
4179 {
4180         struct ixgbe_filter_info *filter_info =
4181                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4182         struct ixgbe_5tuple_filter_info filter_5tuple;
4183         struct ixgbe_5tuple_filter *filter;
4184         int ret;
4185
4186         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4187                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4188                 return -EINVAL;
4189         }
4190
4191         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4192         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4193         if (ret < 0)
4194                 return ret;
4195
4196         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4197                                          &filter_5tuple);
4198         if (filter != NULL && add) {
4199                 PMD_DRV_LOG(ERR, "filter exists.");
4200                 return -EEXIST;
4201         }
4202         if (filter == NULL && !add) {
4203                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4204                 return -ENOENT;
4205         }
4206
4207         if (add) {
4208                 filter = rte_zmalloc("ixgbe_5tuple_filter",
4209                                 sizeof(struct ixgbe_5tuple_filter), 0);
4210                 if (filter == NULL)
4211                         return -ENOMEM;
4212                 (void)rte_memcpy(&filter->filter_info,
4213                                  &filter_5tuple,
4214                                  sizeof(struct ixgbe_5tuple_filter_info));
4215                 filter->queue = ntuple_filter->queue;
4216                 ret = ixgbe_add_5tuple_filter(dev, filter);
4217                 if (ret < 0) {
4218                         rte_free(filter);
4219                         return ret;
4220                 }
4221         } else
4222                 ixgbe_remove_5tuple_filter(dev, filter);
4223
4224         return 0;
4225 }
4226
4227 /*
4228  * get a ntuple filter
4229  *
4230  * @param
4231  * dev: Pointer to struct rte_eth_dev.
4232  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4233  *
4234  * @return
4235  *    - On success, zero.
4236  *    - On failure, a negative value.
4237  */
4238 static int
4239 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
4240                         struct rte_eth_ntuple_filter *ntuple_filter)
4241 {
4242         struct ixgbe_filter_info *filter_info =
4243                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4244         struct ixgbe_5tuple_filter_info filter_5tuple;
4245         struct ixgbe_5tuple_filter *filter;
4246         int ret;
4247
4248         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4249                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4250                 return -EINVAL;
4251         }
4252
4253         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4254         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4255         if (ret < 0)
4256                 return ret;
4257
4258         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4259                                          &filter_5tuple);
4260         if (filter == NULL) {
4261                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4262                 return -ENOENT;
4263         }
4264         ntuple_filter->queue = filter->queue;
4265         return 0;
4266 }
4267
4268 /*
4269  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
4270  * @dev: pointer to rte_eth_dev structure
4271  * @filter_op:operation will be taken.
4272  * @arg: a pointer to specific structure corresponding to the filter_op
4273  *
4274  * @return
4275  *    - On success, zero.
4276  *    - On failure, a negative value.
4277  */
4278 static int
4279 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
4280                                 enum rte_filter_op filter_op,
4281                                 void *arg)
4282 {
4283         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4284         int ret;
4285
4286         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4287
4288         if (filter_op == RTE_ETH_FILTER_NOP)
4289                 return 0;
4290
4291         if (arg == NULL) {
4292                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4293                             filter_op);
4294                 return -EINVAL;
4295         }
4296
4297         switch (filter_op) {
4298         case RTE_ETH_FILTER_ADD:
4299                 ret = ixgbe_add_del_ntuple_filter(dev,
4300                         (struct rte_eth_ntuple_filter *)arg,
4301                         TRUE);
4302                 break;
4303         case RTE_ETH_FILTER_DELETE:
4304                 ret = ixgbe_add_del_ntuple_filter(dev,
4305                         (struct rte_eth_ntuple_filter *)arg,
4306                         FALSE);
4307                 break;
4308         case RTE_ETH_FILTER_GET:
4309                 ret = ixgbe_get_ntuple_filter(dev,
4310                         (struct rte_eth_ntuple_filter *)arg);
4311                 break;
4312         default:
4313                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4314                 ret = -EINVAL;
4315                 break;
4316         }
4317         return ret;
4318 }
4319
4320 static inline int
4321 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4322                         uint16_t ethertype)
4323 {
4324         int i;
4325
4326         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4327                 if (filter_info->ethertype_filters[i] == ethertype &&
4328                     (filter_info->ethertype_mask & (1 << i)))
4329                         return i;
4330         }
4331         return -1;
4332 }
4333
4334 static inline int
4335 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4336                         uint16_t ethertype)
4337 {
4338         int i;
4339
4340         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4341                 if (!(filter_info->ethertype_mask & (1 << i))) {
4342                         filter_info->ethertype_mask |= 1 << i;
4343                         filter_info->ethertype_filters[i] = ethertype;
4344                         return i;
4345                 }
4346         }
4347         return -1;
4348 }
4349
4350 static inline int
4351 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4352                         uint8_t idx)
4353 {
4354         if (idx >= IXGBE_MAX_ETQF_FILTERS)
4355                 return -1;
4356         filter_info->ethertype_mask &= ~(1 << idx);
4357         filter_info->ethertype_filters[idx] = 0;
4358         return idx;
4359 }
4360
4361 static int
4362 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4363                         struct rte_eth_ethertype_filter *filter,
4364                         bool add)
4365 {
4366         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4367         struct ixgbe_filter_info *filter_info =
4368                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4369         uint32_t etqf = 0;
4370         uint32_t etqs = 0;
4371         int ret;
4372
4373         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4374                 return -EINVAL;
4375
4376         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4377                 filter->ether_type == ETHER_TYPE_IPv6) {
4378                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4379                         " ethertype filter.", filter->ether_type);
4380                 return -EINVAL;
4381         }
4382
4383         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4384                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4385                 return -EINVAL;
4386         }
4387         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4388                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4389                 return -EINVAL;
4390         }
4391
4392         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4393         if (ret >= 0 && add) {
4394                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4395                             filter->ether_type);
4396                 return -EEXIST;
4397         }
4398         if (ret < 0 && !add) {
4399                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4400                             filter->ether_type);
4401                 return -ENOENT;
4402         }
4403
4404         if (add) {
4405                 ret = ixgbe_ethertype_filter_insert(filter_info,
4406                         filter->ether_type);
4407                 if (ret < 0) {
4408                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4409                         return -ENOSYS;
4410                 }
4411                 etqf = IXGBE_ETQF_FILTER_EN;
4412                 etqf |= (uint32_t)filter->ether_type;
4413                 etqs |= (uint32_t)((filter->queue <<
4414                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
4415                                     IXGBE_ETQS_RX_QUEUE);
4416                 etqs |= IXGBE_ETQS_QUEUE_EN;
4417         } else {
4418                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4419                 if (ret < 0)
4420                         return -ENOSYS;
4421         }
4422         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4423         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4424         IXGBE_WRITE_FLUSH(hw);
4425
4426         return 0;
4427 }
4428
4429 static int
4430 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4431                         struct rte_eth_ethertype_filter *filter)
4432 {
4433         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4434         struct ixgbe_filter_info *filter_info =
4435                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4436         uint32_t etqf, etqs;
4437         int ret;
4438
4439         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4440         if (ret < 0) {
4441                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4442                             filter->ether_type);
4443                 return -ENOENT;
4444         }
4445
4446         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4447         if (etqf & IXGBE_ETQF_FILTER_EN) {
4448                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4449                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4450                 filter->flags = 0;
4451                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4452                                IXGBE_ETQS_RX_QUEUE_SHIFT;
4453                 return 0;
4454         }
4455         return -ENOENT;
4456 }
4457
4458 /*
4459  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4460  * @dev: pointer to rte_eth_dev structure
4461  * @filter_op:operation will be taken.
4462  * @arg: a pointer to specific structure corresponding to the filter_op
4463  */
4464 static int
4465 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4466                                 enum rte_filter_op filter_op,
4467                                 void *arg)
4468 {
4469         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4470         int ret;
4471
4472         MAC_TYPE_FILTER_SUP(hw->mac.type);
4473
4474         if (filter_op == RTE_ETH_FILTER_NOP)
4475                 return 0;
4476
4477         if (arg == NULL) {
4478                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4479                             filter_op);
4480                 return -EINVAL;
4481         }
4482
4483         switch (filter_op) {
4484         case RTE_ETH_FILTER_ADD:
4485                 ret = ixgbe_add_del_ethertype_filter(dev,
4486                         (struct rte_eth_ethertype_filter *)arg,
4487                         TRUE);
4488                 break;
4489         case RTE_ETH_FILTER_DELETE:
4490                 ret = ixgbe_add_del_ethertype_filter(dev,
4491                         (struct rte_eth_ethertype_filter *)arg,
4492                         FALSE);
4493                 break;
4494         case RTE_ETH_FILTER_GET:
4495                 ret = ixgbe_get_ethertype_filter(dev,
4496                         (struct rte_eth_ethertype_filter *)arg);
4497                 break;
4498         default:
4499                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4500                 ret = -EINVAL;
4501                 break;
4502         }
4503         return ret;
4504 }
4505
4506 static int
4507 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4508                      enum rte_filter_type filter_type,
4509                      enum rte_filter_op filter_op,
4510                      void *arg)
4511 {
4512         int ret = -EINVAL;
4513
4514         switch (filter_type) {
4515         case RTE_ETH_FILTER_NTUPLE:
4516                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
4517                 break;
4518         case RTE_ETH_FILTER_ETHERTYPE:
4519                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4520                 break;
4521         case RTE_ETH_FILTER_SYN:
4522                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
4523                 break;
4524         case RTE_ETH_FILTER_FDIR:
4525                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
4526                 break;
4527         default:
4528                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4529                                                         filter_type);
4530                 break;
4531         }
4532
4533         return ret;
4534 }
4535
4536 static u8 *
4537 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
4538                         u8 **mc_addr_ptr, u32 *vmdq)
4539 {
4540         u8 *mc_addr;
4541
4542         *vmdq = 0;
4543         mc_addr = *mc_addr_ptr;
4544         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
4545         return mc_addr;
4546 }
4547
4548 static int
4549 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
4550                           struct ether_addr *mc_addr_set,
4551                           uint32_t nb_mc_addr)
4552 {
4553         struct ixgbe_hw *hw;
4554         u8 *mc_addr_list;
4555
4556         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4557         mc_addr_list = (u8 *)mc_addr_set;
4558         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
4559                                          ixgbe_dev_addr_list_itr, TRUE);
4560 }
4561
4562 static int
4563 ixgbe_timesync_enable(struct rte_eth_dev *dev)
4564 {
4565         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4566         uint32_t tsync_ctl;
4567         uint32_t tsauxc;
4568
4569         /* Enable system time for platforms where it isn't on by default. */
4570         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
4571         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
4572         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
4573
4574         /* Start incrementing the register used to timestamp PTP packets. */
4575         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
4576
4577         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4578         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
4579                         (ETHER_TYPE_1588 |
4580                          IXGBE_ETQF_FILTER_EN |
4581                          IXGBE_ETQF_1588));
4582
4583         /* Enable timestamping of received PTP packets. */
4584         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
4585         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
4586         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
4587
4588         /* Enable timestamping of transmitted PTP packets. */
4589         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
4590         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
4591         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
4592
4593         return 0;
4594 }
4595
4596 static int
4597 ixgbe_timesync_disable(struct rte_eth_dev *dev)
4598 {
4599         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4600         uint32_t tsync_ctl;
4601
4602         /* Disable timestamping of transmitted PTP packets. */
4603         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
4604         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
4605         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
4606
4607         /* Disable timestamping of received PTP packets. */
4608         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
4609         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
4610         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
4611
4612         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4613         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
4614
4615         /* Stop incrementating the System Time registers. */
4616         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
4617
4618         return 0;
4619 }
4620
4621 static int
4622 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4623                                  struct timespec *timestamp,
4624                                  uint32_t flags __rte_unused)
4625 {
4626         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4627         uint32_t tsync_rxctl;
4628         uint32_t rx_stmpl;
4629         uint32_t rx_stmph;
4630
4631         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
4632         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
4633                 return -EINVAL;
4634
4635         rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
4636         rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
4637
4638         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
4639         timestamp->tv_nsec = 0;
4640
4641         return  0;
4642 }
4643
4644 static int
4645 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4646                                  struct timespec *timestamp)
4647 {
4648         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4649         uint32_t tsync_txctl;
4650         uint32_t tx_stmpl;
4651         uint32_t tx_stmph;
4652
4653         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
4654         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
4655                 return -EINVAL;
4656
4657         tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
4658         tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
4659
4660         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
4661         timestamp->tv_nsec = 0;
4662
4663         return  0;
4664 }
4665
4666 static struct rte_driver rte_ixgbe_driver = {
4667         .type = PMD_PDEV,
4668         .init = rte_ixgbe_pmd_init,
4669 };
4670
4671 static struct rte_driver rte_ixgbevf_driver = {
4672         .type = PMD_PDEV,
4673         .init = rte_ixgbevf_pmd_init,
4674 };
4675
4676 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4677 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);