drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define IXGBE_TIMINCA_16NS_SHIFT 24
 130 #define IXGBE_TIMINCA_INCVALUE   16000000
 131 #define IXGBE_TIMINCA_INIT       ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
 132                                   | IXGBE_TIMINCA_INCVALUE)
 133
 134 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 135 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 136 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 137 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 139 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 142 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 143 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 147                                 int wait_to_complete);
 148 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 149                                 struct rte_eth_stats *stats);
 150 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 151                                 struct rte_eth_xstats *xstats, unsigned n);
 152 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 153                                   struct rte_eth_xstats *xstats, unsigned n);
 154 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 155 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 157                                              uint16_t queue_id,
 158                                              uint8_t stat_idx,
 159                                              uint8_t is_rx);
 160 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 161                                struct rte_eth_dev_info *dev_info);
 162 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 163                                  struct rte_eth_dev_info *dev_info);
 164 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 165
 166 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 167                 uint16_t vlan_id, int on);
 168 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 169 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 170                 uint16_t queue, bool on);
 171 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 172                 int on);
 173 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 174 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 175 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 176 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 177 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 178
 179 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 180 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 181 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 182                                struct rte_eth_fc_conf *fc_conf);
 183 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 184                                struct rte_eth_fc_conf *fc_conf);
 185 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 186                 struct rte_eth_pfc_conf *pfc_conf);
 187 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 188                         struct rte_eth_rss_reta_entry64 *reta_conf,
 189                         uint16_t reta_size);
 190 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 191                         struct rte_eth_rss_reta_entry64 *reta_conf,
 192                         uint16_t reta_size);
 193 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 194 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 195 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 196 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 197 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 198 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 199                 void *param);
 200 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 201 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 202                 uint32_t index, uint32_t pool);
 203 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 204 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 205                                            struct ether_addr *mac_addr);
 206 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 207
 208 /* For Virtual Function support */
 209 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 210 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 211 static int ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev);
 212 static int ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev);
 213 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 214 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 215 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 216 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 217 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 218 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 219 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 220                 struct rte_eth_stats *stats);
 221 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 222 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 223                 uint16_t vlan_id, int on);
 224 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 225                 uint16_t queue, int on);
 226 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 227 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 228 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 229                                           void *param);
 230 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 231                                             uint16_t queue_id);
 232 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 233                                              uint16_t queue_id);
 234 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 235                                  uint8_t queue, uint8_t msix_vector);
 236 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 237
 238 /* For Eth VMDQ APIs support */
 239 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 240                 ether_addr* mac_addr,uint8_t on);
 241 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 242 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 243                 uint16_t rx_mask, uint8_t on);
 244 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 245 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 246 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 247                 uint64_t pool_mask,uint8_t vlan_on);
 248 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 249                 struct rte_eth_mirror_conf *mirror_conf,
 250                 uint8_t rule_id, uint8_t on);
 251 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 252                 uint8_t rule_id);
 253 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 254                                           uint16_t queue_id);
 255 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 256                                            uint16_t queue_id);
 257 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 258                                uint8_t queue, uint8_t msix_vector);
 259 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 260
 261 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 262                 uint16_t queue_idx, uint16_t tx_rate);
 263 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 264                 uint16_t tx_rate, uint64_t q_msk);
 265
 266 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 267                                  struct ether_addr *mac_addr,
 268                                  uint32_t index, uint32_t pool);
 269 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 270 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 271                                              struct ether_addr *mac_addr);
 272 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 273                         struct rte_eth_syn_filter *filter,
 274                         bool add);
 275 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 276                         struct rte_eth_syn_filter *filter);
 277 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 278                         enum rte_filter_op filter_op,
 279                         void *arg);
 280 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 281                         struct ixgbe_5tuple_filter *filter);
 282 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 283                         struct ixgbe_5tuple_filter *filter);
 284 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 285                         struct rte_eth_ntuple_filter *filter,
 286                         bool add);
 287 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 288                                 enum rte_filter_op filter_op,
 289                                 void *arg);
 290 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 291                         struct rte_eth_ntuple_filter *filter);
 292 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 293                         struct rte_eth_ethertype_filter *filter,
 294                         bool add);
 295 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 296                                 enum rte_filter_op filter_op,
 297                                 void *arg);
 298 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 299                         struct rte_eth_ethertype_filter *filter);
 300 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 301                      enum rte_filter_type filter_type,
 302                      enum rte_filter_op filter_op,
 303                      void *arg);
 304 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 305
 306 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 307                                       struct ether_addr *mc_addr_set,
 308                                       uint32_t nb_mc_addr);
 309 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 310                                    struct rte_eth_dcb_info *dcb_info);
 311
 312 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 313 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 314                             struct rte_dev_reg_info *regs);
 315 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 316 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 317                                 struct rte_dev_eeprom_info *eeprom);
 318 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 319                                 struct rte_dev_eeprom_info *eeprom);
 320
 321 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 322 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 323                                 struct rte_dev_reg_info *regs);
 324
 325 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 326 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 327 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 328                                             struct timespec *timestamp,
 329                                             uint32_t flags);
 330 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 331                                             struct timespec *timestamp);
 332
 333 /*
 334  * Define VF Stats MACRO for Non "cleared on read" register
 335  */
 336 #define UPDATE_VF_STAT(reg, last, cur)                          \
 337 {                                                               \
 338         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 339         cur += (latest - last) & UINT_MAX;                      \
 340         last = latest;                                          \
 341 }
 342
 343 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 344 {                                                                \
 345         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 346         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 347         u64 latest = ((new_msb << 32) | new_lsb);                \
 348         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 349         last = latest;                                           \
 350 }
 351
 352 #define IXGBE_SET_HWSTRIP(h, q) do{\
 353                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 354                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 355                 (h)->bitmap[idx] |= 1 << bit;\
 356         }while(0)
 357
 358 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 359                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 360                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 361                 (h)->bitmap[idx] &= ~(1 << bit);\
 362         }while(0)
 363
 364 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 365                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 366                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 367                 (r) = (h)->bitmap[idx] >> bit & 1;\
 368         }while(0)
 369
 370 /*
 371  * The set of PCI devices this driver supports
 372  */
 373 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 374
 375 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 376 #include "rte_pci_dev_ids.h"
 377
 378 { .vendor_id = 0, /* sentinel */ },
 379 };
 380
 381
 382 /*
 383  * The set of PCI devices this driver supports (for 82599 VF)
 384  */
 385 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 386
 387 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 388 #include "rte_pci_dev_ids.h"
 389 { .vendor_id = 0, /* sentinel */ },
 390
 391 };
 392
 393 static const struct rte_eth_desc_lim rx_desc_lim = {
 394         .nb_max = IXGBE_MAX_RING_DESC,
 395         .nb_min = IXGBE_MIN_RING_DESC,
 396         .nb_align = IXGBE_RXD_ALIGN,
 397 };
 398
 399 static const struct rte_eth_desc_lim tx_desc_lim = {
 400         .nb_max = IXGBE_MAX_RING_DESC,
 401         .nb_min = IXGBE_MIN_RING_DESC,
 402         .nb_align = IXGBE_TXD_ALIGN,
 403 };
 404
 405 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 406         .dev_configure        = ixgbe_dev_configure,
 407         .dev_start            = ixgbe_dev_start,
 408         .dev_stop             = ixgbe_dev_stop,
 409         .dev_set_link_up    = ixgbe_dev_set_link_up,
 410         .dev_set_link_down  = ixgbe_dev_set_link_down,
 411         .dev_close            = ixgbe_dev_close,
 412         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 413         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 414         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 415         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 416         .link_update          = ixgbe_dev_link_update,
 417         .stats_get            = ixgbe_dev_stats_get,
 418         .xstats_get           = ixgbe_dev_xstats_get,
 419         .stats_reset          = ixgbe_dev_stats_reset,
 420         .xstats_reset         = ixgbe_dev_xstats_reset,
 421         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 422         .dev_infos_get        = ixgbe_dev_info_get,
 423         .mtu_set              = ixgbe_dev_mtu_set,
 424         .vlan_filter_set      = ixgbe_vlan_filter_set,
 425         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 426         .vlan_offload_set     = ixgbe_vlan_offload_set,
 427         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 428         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 429         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 430         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 431         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 432         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 433         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 434         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 435         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 436         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 437         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 438         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 439         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 440         .dev_led_on           = ixgbe_dev_led_on,
 441         .dev_led_off          = ixgbe_dev_led_off,
 442         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 443         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 444         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 445         .mac_addr_add         = ixgbe_add_rar,
 446         .mac_addr_remove      = ixgbe_remove_rar,
 447         .mac_addr_set         = ixgbe_set_default_mac_addr,
 448         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 449         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 450         .mirror_rule_set      = ixgbe_mirror_rule_set,
 451         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 452         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 453         .set_vf_rx            = ixgbe_set_pool_rx,
 454         .set_vf_tx            = ixgbe_set_pool_tx,
 455         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 456         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 457         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 458         .reta_update          = ixgbe_dev_rss_reta_update,
 459         .reta_query           = ixgbe_dev_rss_reta_query,
 460 #ifdef RTE_NIC_BYPASS
 461         .bypass_init          = ixgbe_bypass_init,
 462         .bypass_state_set     = ixgbe_bypass_state_store,
 463         .bypass_state_show    = ixgbe_bypass_state_show,
 464         .bypass_event_set     = ixgbe_bypass_event_store,
 465         .bypass_event_show    = ixgbe_bypass_event_show,
 466         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 467         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 468         .bypass_ver_show      = ixgbe_bypass_ver_show,
 469         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 470 #endif /* RTE_NIC_BYPASS */
 471         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 472         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 473         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 474         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 475         .rxq_info_get         = ixgbe_rxq_info_get,
 476         .txq_info_get         = ixgbe_txq_info_get,
 477         .timesync_enable      = ixgbe_timesync_enable,
 478         .timesync_disable     = ixgbe_timesync_disable,
 479         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 480         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 481         .get_reg_length       = ixgbe_get_reg_length,
 482         .get_reg              = ixgbe_get_regs,
 483         .get_eeprom_length    = ixgbe_get_eeprom_length,
 484         .get_eeprom           = ixgbe_get_eeprom,
 485         .set_eeprom           = ixgbe_set_eeprom,
 486         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 487 };
 488
 489 /*
 490  * dev_ops for virtual function, bare necessities for basic vf
 491  * operation have been implemented
 492  */
 493 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 494         .dev_configure        = ixgbevf_dev_configure,
 495         .dev_start            = ixgbevf_dev_start,
 496         .dev_stop             = ixgbevf_dev_stop,
 497         .link_update          = ixgbe_dev_link_update,
 498         .stats_get            = ixgbevf_dev_stats_get,
 499         .xstats_get           = ixgbevf_dev_xstats_get,
 500         .stats_reset          = ixgbevf_dev_stats_reset,
 501         .xstats_reset         = ixgbevf_dev_stats_reset,
 502         .dev_close            = ixgbevf_dev_close,
 503         .dev_infos_get        = ixgbevf_dev_info_get,
 504         .mtu_set              = ixgbevf_dev_set_mtu,
 505         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 506         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 507         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 508         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 509         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 510         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 511         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 512         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 513         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 514         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 515         .mac_addr_add         = ixgbevf_add_mac_addr,
 516         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 517         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 518         .rxq_info_get         = ixgbe_rxq_info_get,
 519         .txq_info_get         = ixgbe_txq_info_get,
 520         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 521         .get_reg_length       = ixgbevf_get_reg_length,
 522         .get_reg              = ixgbevf_get_regs,
 523         .reta_update          = ixgbe_dev_rss_reta_update,
 524         .reta_query           = ixgbe_dev_rss_reta_query,
 525         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 526         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 527 };
 528
 529 /* store statistics names and its offset in stats structure */
 530 struct rte_ixgbe_xstats_name_off {
 531         char name[RTE_ETH_XSTATS_NAME_SIZE];
 532         unsigned offset;
 533 };
 534
 535 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 536         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 537         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 538         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 539         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 540         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 541         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 542         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 543         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 544         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 545         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 546         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 547         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 548         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 549         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 550         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 551                 prc1023)},
 552         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 553                 prc1522)},
 554         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 555         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 556         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 557         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 558         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 559         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 560         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 561         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 562         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 563         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 564         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 565         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 566         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 567         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 568         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 569         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 570         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 571                 ptc1023)},
 572         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 573                 ptc1522)},
 574         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 575         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 576         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 577         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 578
 579         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 580                 fdirustat_add)},
 581         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 582                 fdirustat_remove)},
 583         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 584                 fdirfstat_fadd)},
 585         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 586                 fdirfstat_fremove)},
 587         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 588                 fdirmatch)},
 589         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 590                 fdirmiss)},
 591
 592         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 593         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 594         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 595                 fclast)},
 596         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 597         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 598         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 599         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 600         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 601                 fcoe_noddp)},
 602         {"rx_fcoe_no_direct_data_placement_ext_buff",
 603                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 604
 605         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 606                 lxontxc)},
 607         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 608                 lxonrxc)},
 609         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 610                 lxofftxc)},
 611         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 612                 lxoffrxc)},
 613         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 614 };
 615
 616 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 617                            sizeof(rte_ixgbe_stats_strings[0]))
 618
 619 /* Per-queue statistics */
 620 #define IXBGE_NB_8_PER_Q_STATS (8 * 7)
 621 #define IXBGE_NB_16_PER_Q_STATS (16 * 5)
 622 #define IXGBE_NB_Q_STATS (IXBGE_NB_8_PER_Q_STATS + IXBGE_NB_16_PER_Q_STATS)
 623
 624 #define IXGBE_NB_XSTATS (IXGBE_NB_HW_STATS + IXGBE_NB_Q_STATS)
 625
 626 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 627         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 628 };
 629
 630 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 631                 sizeof(rte_ixgbevf_stats_strings[0]))
 632
 633 /**
 634  * Atomically reads the link status information from global
 635  * structure rte_eth_dev.
 636  *
 637  * @param dev
 638  *   - Pointer to the structure rte_eth_dev to read from.
 639  *   - Pointer to the buffer to be saved with the link status.
 640  *
 641  * @return
 642  *   - On success, zero.
 643  *   - On failure, negative value.
 644  */
 645 static inline int
 646 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 647                                 struct rte_eth_link *link)
 648 {
 649         struct rte_eth_link *dst = link;
 650         struct rte_eth_link *src = &(dev->data->dev_link);
 651
 652         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 653                                         *(uint64_t *)src) == 0)
 654                 return -1;
 655
 656         return 0;
 657 }
 658
 659 /**
 660  * Atomically writes the link status information into global
 661  * structure rte_eth_dev.
 662  *
 663  * @param dev
 664  *   - Pointer to the structure rte_eth_dev to read from.
 665  *   - Pointer to the buffer to be saved with the link status.
 666  *
 667  * @return
 668  *   - On success, zero.
 669  *   - On failure, negative value.
 670  */
 671 static inline int
 672 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 673                                 struct rte_eth_link *link)
 674 {
 675         struct rte_eth_link *dst = &(dev->data->dev_link);
 676         struct rte_eth_link *src = link;
 677
 678         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 679                                         *(uint64_t *)src) == 0)
 680                 return -1;
 681
 682         return 0;
 683 }
 684
 685 /*
 686  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 687  */
 688 static inline int
 689 ixgbe_is_sfp(struct ixgbe_hw *hw)
 690 {
 691         switch (hw->phy.type) {
 692         case ixgbe_phy_sfp_avago:
 693         case ixgbe_phy_sfp_ftl:
 694         case ixgbe_phy_sfp_intel:
 695         case ixgbe_phy_sfp_unknown:
 696         case ixgbe_phy_sfp_passive_tyco:
 697         case ixgbe_phy_sfp_passive_unknown:
 698                 return 1;
 699         default:
 700                 return 0;
 701         }
 702 }
 703
 704 static inline int32_t
 705 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 706 {
 707         uint32_t ctrl_ext;
 708         int32_t status;
 709
 710         status = ixgbe_reset_hw(hw);
 711
 712         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 713         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 714         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 715         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 716         IXGBE_WRITE_FLUSH(hw);
 717
 718         return status;
 719 }
 720
 721 static inline void
 722 ixgbe_enable_intr(struct rte_eth_dev *dev)
 723 {
 724         struct ixgbe_interrupt *intr =
 725                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 726         struct ixgbe_hw *hw =
 727                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 728
 729         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 730         IXGBE_WRITE_FLUSH(hw);
 731 }
 732
 733 /*
 734  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 735  */
 736 static void
 737 ixgbe_disable_intr(struct ixgbe_hw *hw)
 738 {
 739         PMD_INIT_FUNC_TRACE();
 740
 741         if (hw->mac.type == ixgbe_mac_82598EB) {
 742                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 743         } else {
 744                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 745                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 746                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 747         }
 748         IXGBE_WRITE_FLUSH(hw);
 749 }
 750
 751 /*
 752  * This function resets queue statistics mapping registers.
 753  * From Niantic datasheet, Initialization of Statistics section:
 754  * "...if software requires the queue counters, the RQSMR and TQSM registers
 755  * must be re-programmed following a device reset.
 756  */
 757 static void
 758 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 759 {
 760         uint32_t i;
 761
 762         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 763                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 764                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 765         }
 766 }
 767
 768
 769 static int
 770 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 771                                   uint16_t queue_id,
 772                                   uint8_t stat_idx,
 773                                   uint8_t is_rx)
 774 {
 775 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 776 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 777 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 778
 779         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 780         struct ixgbe_stat_mapping_registers *stat_mappings =
 781                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 782         uint32_t qsmr_mask = 0;
 783         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 784         uint32_t q_map;
 785         uint8_t n, offset;
 786
 787         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 788                 (hw->mac.type != ixgbe_mac_X540) &&
 789                 (hw->mac.type != ixgbe_mac_X550) &&
 790                 (hw->mac.type != ixgbe_mac_X550EM_x))
 791                 return -ENOSYS;
 792
 793         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 794                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 795                      queue_id, stat_idx);
 796
 797         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 798         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 799                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 800                 return -EIO;
 801         }
 802         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 803
 804         /* Now clear any previous stat_idx set */
 805         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 806         if (!is_rx)
 807                 stat_mappings->tqsm[n] &= ~clearing_mask;
 808         else
 809                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 810
 811         q_map = (uint32_t)stat_idx;
 812         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 813         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 814         if (!is_rx)
 815                 stat_mappings->tqsm[n] |= qsmr_mask;
 816         else
 817                 stat_mappings->rqsmr[n] |= qsmr_mask;
 818
 819         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 820                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 821                      queue_id, stat_idx);
 822         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 823                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 824
 825         /* Now write the mapping in the appropriate register */
 826         if (is_rx) {
 827                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 828                              stat_mappings->rqsmr[n], n);
 829                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 830         }
 831         else {
 832                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 833                              stat_mappings->tqsm[n], n);
 834                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 835         }
 836         return 0;
 837 }
 838
 839 static void
 840 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 841 {
 842         struct ixgbe_stat_mapping_registers *stat_mappings =
 843                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 844         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 845         int i;
 846
 847         /* write whatever was in stat mapping table to the NIC */
 848         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 849                 /* rx */
 850                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 851
 852                 /* tx */
 853                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 854         }
 855 }
 856
 857 static void
 858 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 859 {
 860         uint8_t i;
 861         struct ixgbe_dcb_tc_config *tc;
 862         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 863
 864         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 865         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 866         for (i = 0; i < dcb_max_tc; i++) {
 867                 tc = &dcb_config->tc_config[i];
 868                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 869                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 870                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 871                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 872                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 873                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 874                 tc->pfc = ixgbe_dcb_pfc_disabled;
 875         }
 876
 877         /* Initialize default user to priority mapping, UPx->TC0 */
 878         tc = &dcb_config->tc_config[0];
 879         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 880         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 881         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 882                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 883                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 884         }
 885         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 886         dcb_config->pfc_mode_enable = false;
 887         dcb_config->vt_mode = true;
 888         dcb_config->round_robin_enable = false;
 889         /* support all DCB capabilities in 82599 */
 890         dcb_config->support.capabilities = 0xFF;
 891
 892         /*we only support 4 Tcs for X540, X550 */
 893         if (hw->mac.type == ixgbe_mac_X540 ||
 894                 hw->mac.type == ixgbe_mac_X550 ||
 895                 hw->mac.type == ixgbe_mac_X550EM_x) {
 896                 dcb_config->num_tcs.pg_tcs = 4;
 897                 dcb_config->num_tcs.pfc_tcs = 4;
 898         }
 899 }
 900
 901 /*
 902  * Ensure that all locks are released before first NVM or PHY access
 903  */
 904 static void
 905 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 906 {
 907         uint16_t mask;
 908
 909         /*
 910          * Phy lock should not fail in this early stage. If this is the case,
 911          * it is due to an improper exit of the application.
 912          * So force the release of the faulty lock. Release of common lock
 913          * is done automatically by swfw_sync function.
 914          */
 915         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 916         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 917                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 918         }
 919         ixgbe_release_swfw_semaphore(hw, mask);
 920
 921         /*
 922          * These ones are more tricky since they are common to all ports; but
 923          * swfw_sync retries last long enough (1s) to be almost sure that if
 924          * lock can not be taken it is due to an improper lock of the
 925          * semaphore.
 926          */
 927         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 928         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 929                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 930         }
 931         ixgbe_release_swfw_semaphore(hw, mask);
 932 }
 933
 934 /*
 935  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
 936  * It returns 0 on success.
 937  */
 938 static int
 939 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
 940 {
 941         struct rte_pci_device *pci_dev;
 942         struct ixgbe_hw *hw =
 943                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 944         struct ixgbe_vfta * shadow_vfta =
 945                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 946         struct ixgbe_hwstrip *hwstrip =
 947                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 948         struct ixgbe_dcb_config *dcb_config =
 949                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 950         struct ixgbe_filter_info *filter_info =
 951                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 952         uint32_t ctrl_ext;
 953         uint16_t csum;
 954         int diag, i;
 955
 956         PMD_INIT_FUNC_TRACE();
 957
 958         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 959         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 960         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 961
 962         /*
 963          * For secondary processes, we don't initialise any further as primary
 964          * has already done this work. Only check we don't need a different
 965          * RX and TX function.
 966          */
 967         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 968                 struct ixgbe_tx_queue *txq;
 969                 /* TX queue function in primary, set by last queue initialized
 970                  * Tx queue may not initialized by primary process */
 971                 if (eth_dev->data->tx_queues) {
 972                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 973                         ixgbe_set_tx_function(eth_dev, txq);
 974                 } else {
 975                         /* Use default TX function if we get here */
 976                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
 977                                              "Using default TX function.");
 978                 }
 979
 980                 ixgbe_set_rx_function(eth_dev);
 981
 982                 return 0;
 983         }
 984         pci_dev = eth_dev->pci_dev;
 985
 986         /* Vendor and Device ID need to be set before init of shared code */
 987         hw->device_id = pci_dev->id.device_id;
 988         hw->vendor_id = pci_dev->id.vendor_id;
 989         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 990         hw->allow_unsupported_sfp = 1;
 991
 992         /* Initialize the shared code (base driver) */
 993 #ifdef RTE_NIC_BYPASS
 994         diag = ixgbe_bypass_init_shared_code(hw);
 995 #else
 996         diag = ixgbe_init_shared_code(hw);
 997 #endif /* RTE_NIC_BYPASS */
 998
 999         if (diag != IXGBE_SUCCESS) {
1000                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1001                 return -EIO;
1002         }
1003
1004         /* pick up the PCI bus settings for reporting later */
1005         ixgbe_get_bus_info(hw);
1006
1007         /* Unlock any pending hardware semaphore */
1008         ixgbe_swfw_lock_reset(hw);
1009
1010         /* Initialize DCB configuration*/
1011         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1012         ixgbe_dcb_init(hw,dcb_config);
1013         /* Get Hardware Flow Control setting */
1014         hw->fc.requested_mode = ixgbe_fc_full;
1015         hw->fc.current_mode = ixgbe_fc_full;
1016         hw->fc.pause_time = IXGBE_FC_PAUSE;
1017         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1018                 hw->fc.low_water[i] = IXGBE_FC_LO;
1019                 hw->fc.high_water[i] = IXGBE_FC_HI;
1020         }
1021         hw->fc.send_xon = 1;
1022
1023         /* Make sure we have a good EEPROM before we read from it */
1024         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1025         if (diag != IXGBE_SUCCESS) {
1026                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1027                 return -EIO;
1028         }
1029
1030 #ifdef RTE_NIC_BYPASS
1031         diag = ixgbe_bypass_init_hw(hw);
1032 #else
1033         diag = ixgbe_init_hw(hw);
1034 #endif /* RTE_NIC_BYPASS */
1035
1036         /*
1037          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1038          * is called too soon after the kernel driver unbinding/binding occurs.
1039          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1040          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1041          * also called. See ixgbe_identify_phy_82599(). The reason for the
1042          * failure is not known, and only occuts when virtualisation features
1043          * are disabled in the bios. A delay of 100ms  was found to be enough by
1044          * trial-and-error, and is doubled to be safe.
1045          */
1046         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1047                 rte_delay_ms(200);
1048                 diag = ixgbe_init_hw(hw);
1049         }
1050
1051         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1052                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1053                     "LOM.  Please be aware there may be issues associated "
1054                     "with your hardware.");
1055                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1056                     "please contact your Intel or hardware representative "
1057                     "who provided you with this hardware.");
1058         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1059                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1060         if (diag) {
1061                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1062                 return -EIO;
1063         }
1064
1065         /* Reset the hw statistics */
1066         ixgbe_dev_stats_reset(eth_dev);
1067
1068         /* disable interrupt */
1069         ixgbe_disable_intr(hw);
1070
1071         /* reset mappings for queue statistics hw counters*/
1072         ixgbe_reset_qstat_mappings(hw);
1073
1074         /* Allocate memory for storing MAC addresses */
1075         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1076                         hw->mac.num_rar_entries, 0);
1077         if (eth_dev->data->mac_addrs == NULL) {
1078                 PMD_INIT_LOG(ERR,
1079                         "Failed to allocate %u bytes needed to store "
1080                         "MAC addresses",
1081                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1082                 return -ENOMEM;
1083         }
1084         /* Copy the permanent MAC address */
1085         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1086                         &eth_dev->data->mac_addrs[0]);
1087
1088         /* Allocate memory for storing hash filter MAC addresses */
1089         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1090                         IXGBE_VMDQ_NUM_UC_MAC, 0);
1091         if (eth_dev->data->hash_mac_addrs == NULL) {
1092                 PMD_INIT_LOG(ERR,
1093                         "Failed to allocate %d bytes needed to store MAC addresses",
1094                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1095                 return -ENOMEM;
1096         }
1097
1098         /* initialize the vfta */
1099         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1100
1101         /* initialize the hw strip bitmap*/
1102         memset(hwstrip, 0, sizeof(*hwstrip));
1103
1104         /* initialize PF if max_vfs not zero */
1105         ixgbe_pf_host_init(eth_dev);
1106
1107         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1108         /* let hardware know driver is loaded */
1109         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1110         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1111         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1112         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1113         IXGBE_WRITE_FLUSH(hw);
1114
1115         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1116                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1117                              (int) hw->mac.type, (int) hw->phy.type,
1118                              (int) hw->phy.sfp_type);
1119         else
1120                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1121                              (int) hw->mac.type, (int) hw->phy.type);
1122
1123         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1124                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1125                         pci_dev->id.device_id);
1126
1127         /* enable support intr */
1128         ixgbe_enable_intr(eth_dev);
1129
1130         /* initialize 5tuple filter list */
1131         TAILQ_INIT(&filter_info->fivetuple_list);
1132         memset(filter_info->fivetuple_mask, 0,
1133                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1134
1135         return 0;
1136 }
1137
1138 static int
1139 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1140 {
1141         struct rte_pci_device *pci_dev;
1142         struct ixgbe_hw *hw;
1143
1144         PMD_INIT_FUNC_TRACE();
1145
1146         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1147                 return -EPERM;
1148
1149         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1150         pci_dev = eth_dev->pci_dev;
1151
1152         if (hw->adapter_stopped == 0)
1153                 ixgbe_dev_close(eth_dev);
1154
1155         eth_dev->dev_ops = NULL;
1156         eth_dev->rx_pkt_burst = NULL;
1157         eth_dev->tx_pkt_burst = NULL;
1158
1159         /* Unlock any pending hardware semaphore */
1160         ixgbe_swfw_lock_reset(hw);
1161
1162         /* disable uio intr before callback unregister */
1163         rte_intr_disable(&(pci_dev->intr_handle));
1164         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1165                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1166
1167         /* uninitialize PF if max_vfs not zero */
1168         ixgbe_pf_host_uninit(eth_dev);
1169
1170         rte_free(eth_dev->data->mac_addrs);
1171         eth_dev->data->mac_addrs = NULL;
1172
1173         rte_free(eth_dev->data->hash_mac_addrs);
1174         eth_dev->data->hash_mac_addrs = NULL;
1175
1176         return 0;
1177 }
1178
1179 /*
1180  * Negotiate mailbox API version with the PF.
1181  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1182  * Then we try to negotiate starting with the most recent one.
1183  * If all negotiation attempts fail, then we will proceed with
1184  * the default one (ixgbe_mbox_api_10).
1185  */
1186 static void
1187 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1188 {
1189         int32_t i;
1190
1191         /* start with highest supported, proceed down */
1192         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1193                 ixgbe_mbox_api_11,
1194                 ixgbe_mbox_api_10,
1195         };
1196
1197         for (i = 0;
1198                         i != RTE_DIM(sup_ver) &&
1199                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1200                         i++)
1201                 ;
1202 }
1203
1204 static void
1205 generate_random_mac_addr(struct ether_addr *mac_addr)
1206 {
1207         uint64_t random;
1208
1209         /* Set Organizationally Unique Identifier (OUI) prefix. */
1210         mac_addr->addr_bytes[0] = 0x00;
1211         mac_addr->addr_bytes[1] = 0x09;
1212         mac_addr->addr_bytes[2] = 0xC0;
1213         /* Force indication of locally assigned MAC address. */
1214         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1215         /* Generate the last 3 bytes of the MAC address with a random number. */
1216         random = rte_rand();
1217         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1218 }
1219
1220 /*
1221  * Virtual Function device init
1222  */
1223 static int
1224 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1225 {
1226         int diag;
1227         uint32_t tc, tcs;
1228         struct rte_pci_device *pci_dev;
1229         struct ixgbe_hw *hw =
1230                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1231         struct ixgbe_vfta * shadow_vfta =
1232                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1233         struct ixgbe_hwstrip *hwstrip =
1234                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1235         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1236
1237         PMD_INIT_FUNC_TRACE();
1238
1239         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1240         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1241         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1242
1243         /* for secondary processes, we don't initialise any further as primary
1244          * has already done this work. Only check we don't need a different
1245          * RX function */
1246         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1247                 if (eth_dev->data->scattered_rx)
1248                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1249                 return 0;
1250         }
1251
1252         pci_dev = eth_dev->pci_dev;
1253
1254         hw->device_id = pci_dev->id.device_id;
1255         hw->vendor_id = pci_dev->id.vendor_id;
1256         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1257
1258         /* initialize the vfta */
1259         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1260
1261         /* initialize the hw strip bitmap*/
1262         memset(hwstrip, 0, sizeof(*hwstrip));
1263
1264         /* Initialize the shared code (base driver) */
1265         diag = ixgbe_init_shared_code(hw);
1266         if (diag != IXGBE_SUCCESS) {
1267                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1268                 return -EIO;
1269         }
1270
1271         /* init_mailbox_params */
1272         hw->mbx.ops.init_params(hw);
1273
1274         /* Reset the hw statistics */
1275         ixgbevf_dev_stats_reset(eth_dev);
1276
1277         /* Disable the interrupts for VF */
1278         ixgbevf_intr_disable(hw);
1279
1280         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1281         diag = hw->mac.ops.reset_hw(hw);
1282
1283         /*
1284          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1285          * the underlying PF driver has not assigned a MAC address to the VF.
1286          * In this case, assign a random MAC address.
1287          */
1288         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1289                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1290                 return (diag);
1291         }
1292
1293         /* negotiate mailbox API version to use with the PF. */
1294         ixgbevf_negotiate_api(hw);
1295
1296         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1297         ixgbevf_get_queues(hw, &tcs, &tc);
1298
1299         /* Allocate memory for storing MAC addresses */
1300         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1301                         hw->mac.num_rar_entries, 0);
1302         if (eth_dev->data->mac_addrs == NULL) {
1303                 PMD_INIT_LOG(ERR,
1304                         "Failed to allocate %u bytes needed to store "
1305                         "MAC addresses",
1306                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1307                 return -ENOMEM;
1308         }
1309
1310         /* Generate a random MAC address, if none was assigned by PF. */
1311         if (is_zero_ether_addr(perm_addr)) {
1312                 generate_random_mac_addr(perm_addr);
1313                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1314                 if (diag) {
1315                         rte_free(eth_dev->data->mac_addrs);
1316                         eth_dev->data->mac_addrs = NULL;
1317                         return diag;
1318                 }
1319                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1320                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1321                              "%02x:%02x:%02x:%02x:%02x:%02x",
1322                              perm_addr->addr_bytes[0],
1323                              perm_addr->addr_bytes[1],
1324                              perm_addr->addr_bytes[2],
1325                              perm_addr->addr_bytes[3],
1326                              perm_addr->addr_bytes[4],
1327                              perm_addr->addr_bytes[5]);
1328         }
1329
1330         /* Copy the permanent MAC address */
1331         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1332
1333         /* reset the hardware with the new settings */
1334         diag = hw->mac.ops.start_hw(hw);
1335         switch (diag) {
1336                 case  0:
1337                         break;
1338
1339                 default:
1340                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1341                         return (-EIO);
1342         }
1343
1344         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1345                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1346                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1347
1348         return 0;
1349 }
1350
1351 /* Virtual Function device uninit */
1352
1353 static int
1354 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1355 {
1356         struct ixgbe_hw *hw;
1357         unsigned i;
1358
1359         PMD_INIT_FUNC_TRACE();
1360
1361         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1362                 return -EPERM;
1363
1364         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1365
1366         if (hw->adapter_stopped == 0)
1367                 ixgbevf_dev_close(eth_dev);
1368
1369         eth_dev->dev_ops = NULL;
1370         eth_dev->rx_pkt_burst = NULL;
1371         eth_dev->tx_pkt_burst = NULL;
1372
1373         /* Disable the interrupts for VF */
1374         ixgbevf_intr_disable(hw);
1375
1376         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1377                 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1378                 eth_dev->data->rx_queues[i] = NULL;
1379         }
1380         eth_dev->data->nb_rx_queues = 0;
1381
1382         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1383                 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1384                 eth_dev->data->tx_queues[i] = NULL;
1385         }
1386         eth_dev->data->nb_tx_queues = 0;
1387
1388         rte_free(eth_dev->data->mac_addrs);
1389         eth_dev->data->mac_addrs = NULL;
1390
1391         return 0;
1392 }
1393
1394 static struct eth_driver rte_ixgbe_pmd = {
1395         .pci_drv = {
1396                 .name = "rte_ixgbe_pmd",
1397                 .id_table = pci_id_ixgbe_map,
1398                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1399                         RTE_PCI_DRV_DETACHABLE,
1400         },
1401         .eth_dev_init = eth_ixgbe_dev_init,
1402         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1403         .dev_private_size = sizeof(struct ixgbe_adapter),
1404 };
1405
1406 /*
1407  * virtual function driver struct
1408  */
1409 static struct eth_driver rte_ixgbevf_pmd = {
1410         .pci_drv = {
1411                 .name = "rte_ixgbevf_pmd",
1412                 .id_table = pci_id_ixgbevf_map,
1413                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1414         },
1415         .eth_dev_init = eth_ixgbevf_dev_init,
1416         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1417         .dev_private_size = sizeof(struct ixgbe_adapter),
1418 };
1419
1420 /*
1421  * Driver initialization routine.
1422  * Invoked once at EAL init time.
1423  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1424  */
1425 static int
1426 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1427 {
1428         PMD_INIT_FUNC_TRACE();
1429
1430         rte_eth_driver_register(&rte_ixgbe_pmd);
1431         return 0;
1432 }
1433
1434 /*
1435  * VF Driver initialization routine.
1436  * Invoked one at EAL init time.
1437  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1438  */
1439 static int
1440 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1441 {
1442         PMD_INIT_FUNC_TRACE();
1443
1444         rte_eth_driver_register(&rte_ixgbevf_pmd);
1445         return (0);
1446 }
1447
1448 static int
1449 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1450 {
1451         struct ixgbe_hw *hw =
1452                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1453         struct ixgbe_vfta * shadow_vfta =
1454                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1455         uint32_t vfta;
1456         uint32_t vid_idx;
1457         uint32_t vid_bit;
1458
1459         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1460         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1461         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1462         if (on)
1463                 vfta |= vid_bit;
1464         else
1465                 vfta &= ~vid_bit;
1466         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1467
1468         /* update local VFTA copy */
1469         shadow_vfta->vfta[vid_idx] = vfta;
1470
1471         return 0;
1472 }
1473
1474 static void
1475 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1476 {
1477         if (on)
1478                 ixgbe_vlan_hw_strip_enable(dev, queue);
1479         else
1480                 ixgbe_vlan_hw_strip_disable(dev, queue);
1481 }
1482
1483 static void
1484 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1485 {
1486         struct ixgbe_hw *hw =
1487                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1488
1489         /* Only the high 16-bits is valid */
1490         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1491 }
1492
1493 void
1494 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1495 {
1496         struct ixgbe_hw *hw =
1497                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1498         uint32_t vlnctrl;
1499
1500         PMD_INIT_FUNC_TRACE();
1501
1502         /* Filter Table Disable */
1503         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1504         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1505
1506         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1507 }
1508
1509 void
1510 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1511 {
1512         struct ixgbe_hw *hw =
1513                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1514         struct ixgbe_vfta * shadow_vfta =
1515                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1516         uint32_t vlnctrl;
1517         uint16_t i;
1518
1519         PMD_INIT_FUNC_TRACE();
1520
1521         /* Filter Table Enable */
1522         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1523         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1524         vlnctrl |= IXGBE_VLNCTRL_VFE;
1525
1526         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1527
1528         /* write whatever is in local vfta copy */
1529         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1530                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1531 }
1532
1533 static void
1534 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1535 {
1536         struct ixgbe_hwstrip *hwstrip =
1537                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1538
1539         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1540                 return;
1541
1542         if (on)
1543                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1544         else
1545                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1546 }
1547
1548 static void
1549 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1550 {
1551         struct ixgbe_hw *hw =
1552                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1553         uint32_t ctrl;
1554
1555         PMD_INIT_FUNC_TRACE();
1556
1557         if (hw->mac.type == ixgbe_mac_82598EB) {
1558                 /* No queue level support */
1559                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1560                 return;
1561         }
1562         else {
1563                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1564                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1565                 ctrl &= ~IXGBE_RXDCTL_VME;
1566                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1567         }
1568         /* record those setting for HW strip per queue */
1569         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1570 }
1571
1572 static void
1573 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1574 {
1575         struct ixgbe_hw *hw =
1576                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1577         uint32_t ctrl;
1578
1579         PMD_INIT_FUNC_TRACE();
1580
1581         if (hw->mac.type == ixgbe_mac_82598EB) {
1582                 /* No queue level supported */
1583                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1584                 return;
1585         }
1586         else {
1587                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1588                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1589                 ctrl |= IXGBE_RXDCTL_VME;
1590                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1591         }
1592         /* record those setting for HW strip per queue */
1593         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1594 }
1595
1596 void
1597 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1598 {
1599         struct ixgbe_hw *hw =
1600                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1601         uint32_t ctrl;
1602         uint16_t i;
1603
1604         PMD_INIT_FUNC_TRACE();
1605
1606         if (hw->mac.type == ixgbe_mac_82598EB) {
1607                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1608                 ctrl &= ~IXGBE_VLNCTRL_VME;
1609                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1610         }
1611         else {
1612                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1613                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1614                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1615                         ctrl &= ~IXGBE_RXDCTL_VME;
1616                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1617
1618                         /* record those setting for HW strip per queue */
1619                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1620                 }
1621         }
1622 }
1623
1624 void
1625 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1626 {
1627         struct ixgbe_hw *hw =
1628                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1629         uint32_t ctrl;
1630         uint16_t i;
1631
1632         PMD_INIT_FUNC_TRACE();
1633
1634         if (hw->mac.type == ixgbe_mac_82598EB) {
1635                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1636                 ctrl |= IXGBE_VLNCTRL_VME;
1637                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1638         }
1639         else {
1640                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1641                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1642                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1643                         ctrl |= IXGBE_RXDCTL_VME;
1644                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1645
1646                         /* record those setting for HW strip per queue */
1647                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1648                 }
1649         }
1650 }
1651
1652 static void
1653 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1654 {
1655         struct ixgbe_hw *hw =
1656                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1657         uint32_t ctrl;
1658
1659         PMD_INIT_FUNC_TRACE();
1660
1661         /* DMATXCTRL: Geric Double VLAN Disable */
1662         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1663         ctrl &= ~IXGBE_DMATXCTL_GDV;
1664         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1665
1666         /* CTRL_EXT: Global Double VLAN Disable */
1667         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1668         ctrl &= ~IXGBE_EXTENDED_VLAN;
1669         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1670
1671 }
1672
1673 static void
1674 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1675 {
1676         struct ixgbe_hw *hw =
1677                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1678         uint32_t ctrl;
1679
1680         PMD_INIT_FUNC_TRACE();
1681
1682         /* DMATXCTRL: Geric Double VLAN Enable */
1683         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1684         ctrl |= IXGBE_DMATXCTL_GDV;
1685         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1686
1687         /* CTRL_EXT: Global Double VLAN Enable */
1688         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1689         ctrl |= IXGBE_EXTENDED_VLAN;
1690         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1691
1692         /*
1693          * VET EXT field in the EXVET register = 0x8100 by default
1694          * So no need to change. Same to VT field of DMATXCTL register
1695          */
1696 }
1697
1698 static void
1699 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1700 {
1701         if(mask & ETH_VLAN_STRIP_MASK){
1702                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1703                         ixgbe_vlan_hw_strip_enable_all(dev);
1704                 else
1705                         ixgbe_vlan_hw_strip_disable_all(dev);
1706         }
1707
1708         if(mask & ETH_VLAN_FILTER_MASK){
1709                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1710                         ixgbe_vlan_hw_filter_enable(dev);
1711                 else
1712                         ixgbe_vlan_hw_filter_disable(dev);
1713         }
1714
1715         if(mask & ETH_VLAN_EXTEND_MASK){
1716                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1717                         ixgbe_vlan_hw_extend_enable(dev);
1718                 else
1719                         ixgbe_vlan_hw_extend_disable(dev);
1720         }
1721 }
1722
1723 static void
1724 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1725 {
1726         struct ixgbe_hw *hw =
1727                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1728         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1729         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1730         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1731         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1732 }
1733
1734 static int
1735 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1736 {
1737         switch (nb_rx_q) {
1738         case 1:
1739         case 2:
1740                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1741                 break;
1742         case 4:
1743                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1744                 break;
1745         default:
1746                 return -EINVAL;
1747         }
1748
1749         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1750         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1751
1752         return 0;
1753 }
1754
1755 static int
1756 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1757 {
1758         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1759         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1760         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1761
1762         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1763                 /* check multi-queue mode */
1764                 switch (dev_conf->rxmode.mq_mode) {
1765                 case ETH_MQ_RX_VMDQ_DCB:
1766                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1767                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1768                         PMD_INIT_LOG(ERR, "SRIOV active,"
1769                                         " unsupported mq_mode rx %d.",
1770                                         dev_conf->rxmode.mq_mode);
1771                         return -EINVAL;
1772                 case ETH_MQ_RX_RSS:
1773                 case ETH_MQ_RX_VMDQ_RSS:
1774                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1775                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1776                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1777                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1778                                                 " invalid queue number"
1779                                                 " for VMDQ RSS, allowed"
1780                                                 " value are 1, 2 or 4.");
1781                                         return -EINVAL;
1782                                 }
1783                         break;
1784                 case ETH_MQ_RX_VMDQ_ONLY:
1785                 case ETH_MQ_RX_NONE:
1786                         /* if nothing mq mode configure, use default scheme */
1787                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1788                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1789                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1790                         break;
1791                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1792                         /* SRIOV only works in VMDq enable mode */
1793                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1794                                         " wrong mq_mode rx %d.",
1795                                         dev_conf->rxmode.mq_mode);
1796                         return -EINVAL;
1797                 }
1798
1799                 switch (dev_conf->txmode.mq_mode) {
1800                 case ETH_MQ_TX_VMDQ_DCB:
1801                         /* DCB VMDQ in SRIOV mode, not implement yet */
1802                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1803                                         " unsupported VMDQ mq_mode tx %d.",
1804                                         dev_conf->txmode.mq_mode);
1805                         return -EINVAL;
1806                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1807                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1808                         break;
1809                 }
1810
1811                 /* check valid queue number */
1812                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1813                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1814                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1815                                         " queue number must less equal to %d.",
1816                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1817                         return -EINVAL;
1818                 }
1819         } else {
1820                 /* check configuration for vmdb+dcb mode */
1821                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1822                         const struct rte_eth_vmdq_dcb_conf *conf;
1823
1824                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1825                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1826                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1827                                 return -EINVAL;
1828                         }
1829                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1830                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1831                                conf->nb_queue_pools == ETH_32_POOLS)) {
1832                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1833                                                 " nb_queue_pools must be %d or %d.",
1834                                                 ETH_16_POOLS, ETH_32_POOLS);
1835                                 return -EINVAL;
1836                         }
1837                 }
1838                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1839                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1840
1841                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1842                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1843                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1844                                 return -EINVAL;
1845                         }
1846                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1847                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1848                                conf->nb_queue_pools == ETH_32_POOLS)) {
1849                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1850                                                 " nb_queue_pools != %d and"
1851                                                 " nb_queue_pools != %d.",
1852                                                 ETH_16_POOLS, ETH_32_POOLS);
1853                                 return -EINVAL;
1854                         }
1855                 }
1856
1857                 /* For DCB mode check our configuration before we go further */
1858                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1859                         const struct rte_eth_dcb_rx_conf *conf;
1860
1861                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1862                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1863                                                  IXGBE_DCB_NB_QUEUES);
1864                                 return -EINVAL;
1865                         }
1866                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1867                         if (!(conf->nb_tcs == ETH_4_TCS ||
1868                                conf->nb_tcs == ETH_8_TCS)) {
1869                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1870                                                 " and nb_tcs != %d.",
1871                                                 ETH_4_TCS, ETH_8_TCS);
1872                                 return -EINVAL;
1873                         }
1874                 }
1875
1876                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1877                         const struct rte_eth_dcb_tx_conf *conf;
1878
1879                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1880                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1881                                                  IXGBE_DCB_NB_QUEUES);
1882                                 return -EINVAL;
1883                         }
1884                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1885                         if (!(conf->nb_tcs == ETH_4_TCS ||
1886                                conf->nb_tcs == ETH_8_TCS)) {
1887                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1888                                                 " and nb_tcs != %d.",
1889                                                 ETH_4_TCS, ETH_8_TCS);
1890                                 return -EINVAL;
1891                         }
1892                 }
1893         }
1894         return 0;
1895 }
1896
1897 static int
1898 ixgbe_dev_configure(struct rte_eth_dev *dev)
1899 {
1900         struct ixgbe_interrupt *intr =
1901                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1902         struct ixgbe_adapter *adapter =
1903                 (struct ixgbe_adapter *)dev->data->dev_private;
1904         int ret;
1905
1906         PMD_INIT_FUNC_TRACE();
1907         /* multipe queue mode checking */
1908         ret  = ixgbe_check_mq_mode(dev);
1909         if (ret != 0) {
1910                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
1911                             ret);
1912                 return ret;
1913         }
1914
1915         /* set flag to update link status after init */
1916         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1917
1918         /*
1919          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1920          * allocation or vector Rx preconditions we will reset it.
1921          */
1922         adapter->rx_bulk_alloc_allowed = true;
1923         adapter->rx_vec_allowed = true;
1924
1925         return 0;
1926 }
1927
1928 /*
1929  * Configure device link speed and setup link.
1930  * It returns 0 on success.
1931  */
1932 static int
1933 ixgbe_dev_start(struct rte_eth_dev *dev)
1934 {
1935         struct ixgbe_hw *hw =
1936                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1937         struct ixgbe_vf_info *vfinfo =
1938                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1939         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1940         uint32_t intr_vector = 0;
1941         int err, link_up = 0, negotiate = 0;
1942         uint32_t speed = 0;
1943         int mask = 0;
1944         int status;
1945         uint16_t vf, idx;
1946
1947         PMD_INIT_FUNC_TRACE();
1948
1949         /* IXGBE devices don't support half duplex */
1950         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1951                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1952                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1953                              dev->data->dev_conf.link_duplex,
1954                              dev->data->port_id);
1955                 return -EINVAL;
1956         }
1957
1958         /* stop adapter */
1959         hw->adapter_stopped = 0;
1960         ixgbe_stop_adapter(hw);
1961
1962         /* reinitialize adapter
1963          * this calls reset and start */
1964         status = ixgbe_pf_reset_hw(hw);
1965         if (status != 0)
1966                 return -1;
1967         hw->mac.ops.start_hw(hw);
1968         hw->mac.get_link_status = true;
1969
1970         /* configure PF module if SRIOV enabled */
1971         ixgbe_pf_host_configure(dev);
1972
1973         /* check and configure queue intr-vector mapping */
1974         if (dev->data->dev_conf.intr_conf.rxq != 0)
1975                 intr_vector = dev->data->nb_rx_queues;
1976
1977         if (rte_intr_efd_enable(intr_handle, intr_vector))
1978                 return -1;
1979
1980         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1981                 intr_handle->intr_vec =
1982                         rte_zmalloc("intr_vec",
1983                                     dev->data->nb_rx_queues * sizeof(int),
1984                                     0);
1985                 if (intr_handle->intr_vec == NULL) {
1986                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1987                                      " intr_vec\n", dev->data->nb_rx_queues);
1988                         return -ENOMEM;
1989                 }
1990         }
1991
1992         /* confiugre msix for sleep until rx interrupt */
1993         ixgbe_configure_msix(dev);
1994
1995         /* initialize transmission unit */
1996         ixgbe_dev_tx_init(dev);
1997
1998         /* This can fail when allocating mbufs for descriptor rings */
1999         err = ixgbe_dev_rx_init(dev);
2000         if (err) {
2001                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2002                 goto error;
2003         }
2004
2005         err = ixgbe_dev_rxtx_start(dev);
2006         if (err < 0) {
2007                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2008                 goto error;
2009         }
2010
2011         /* Skip link setup if loopback mode is enabled for 82599. */
2012         if (hw->mac.type == ixgbe_mac_82599EB &&
2013                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2014                 goto skip_link_setup;
2015
2016         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2017                 err = hw->mac.ops.setup_sfp(hw);
2018                 if (err)
2019                         goto error;
2020         }
2021
2022         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2023                 /* Turn on the copper */
2024                 ixgbe_set_phy_power(hw, true);
2025         } else {
2026                 /* Turn on the laser */
2027                 ixgbe_enable_tx_laser(hw);
2028         }
2029
2030         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2031         if (err)
2032                 goto error;
2033         dev->data->dev_link.link_status = link_up;
2034
2035         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2036         if (err)
2037                 goto error;
2038
2039         switch(dev->data->dev_conf.link_speed) {
2040         case ETH_LINK_SPEED_AUTONEG:
2041                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2042                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2043                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2044                 break;
2045         case ETH_LINK_SPEED_100:
2046                 /*
2047                  * Invalid for 82598 but error will be detected by
2048                  * ixgbe_setup_link()
2049                  */
2050                 speed = IXGBE_LINK_SPEED_100_FULL;
2051                 break;
2052         case ETH_LINK_SPEED_1000:
2053                 speed = IXGBE_LINK_SPEED_1GB_FULL;
2054                 break;
2055         case ETH_LINK_SPEED_10000:
2056                 speed = IXGBE_LINK_SPEED_10GB_FULL;
2057                 break;
2058         default:
2059                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2060                              dev->data->dev_conf.link_speed,
2061                              dev->data->port_id);
2062                 goto error;
2063         }
2064
2065         err = ixgbe_setup_link(hw, speed, link_up);
2066         if (err)
2067                 goto error;
2068
2069 skip_link_setup:
2070
2071         /* check if lsc interrupt is enabled */
2072         if (dev->data->dev_conf.intr_conf.lsc != 0) {
2073                 if (rte_intr_allow_others(intr_handle)) {
2074                         rte_intr_callback_register(intr_handle,
2075                                                    ixgbe_dev_interrupt_handler,
2076                                                    (void *)dev);
2077                         ixgbe_dev_lsc_interrupt_setup(dev);
2078                 } else
2079                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2080                                      " no intr multiplex\n");
2081         }
2082
2083         /* check if rxq interrupt is enabled */
2084         if (dev->data->dev_conf.intr_conf.rxq != 0)
2085                 ixgbe_dev_rxq_interrupt_setup(dev);
2086
2087         /* enable uio/vfio intr/eventfd mapping */
2088         rte_intr_enable(intr_handle);
2089
2090         /* resume enabled intr since hw reset */
2091         ixgbe_enable_intr(dev);
2092
2093         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2094                 ETH_VLAN_EXTEND_MASK;
2095         ixgbe_vlan_offload_set(dev, mask);
2096
2097         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2098                 /* Enable vlan filtering for VMDq */
2099                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2100         }
2101
2102         /* Configure DCB hw */
2103         ixgbe_configure_dcb(dev);
2104
2105         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2106                 err = ixgbe_fdir_configure(dev);
2107                 if (err)
2108                         goto error;
2109         }
2110
2111         /* Restore vf rate limit */
2112         if (vfinfo != NULL) {
2113                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2114                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2115                                 if (vfinfo[vf].tx_rate[idx] != 0)
2116                                         ixgbe_set_vf_rate_limit(dev, vf,
2117                                                 vfinfo[vf].tx_rate[idx],
2118                                                 1 << idx);
2119         }
2120
2121         ixgbe_restore_statistics_mapping(dev);
2122
2123         return (0);
2124
2125 error:
2126         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2127         ixgbe_dev_clear_queues(dev);
2128         return -EIO;
2129 }
2130
2131 /*
2132  * Stop device: disable rx and tx functions to allow for reconfiguring.
2133  */
2134 static void
2135 ixgbe_dev_stop(struct rte_eth_dev *dev)
2136 {
2137         struct rte_eth_link link;
2138         struct ixgbe_hw *hw =
2139                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2140         struct ixgbe_vf_info *vfinfo =
2141                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2142         struct ixgbe_filter_info *filter_info =
2143                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2144         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2145         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2146         int vf;
2147
2148         PMD_INIT_FUNC_TRACE();
2149
2150         /* disable interrupts */
2151         ixgbe_disable_intr(hw);
2152
2153         /* disable intr eventfd mapping */
2154         rte_intr_disable(intr_handle);
2155
2156         /* reset the NIC */
2157         ixgbe_pf_reset_hw(hw);
2158         hw->adapter_stopped = 0;
2159
2160         /* stop adapter */
2161         ixgbe_stop_adapter(hw);
2162
2163         for (vf = 0; vfinfo != NULL &&
2164                      vf < dev->pci_dev->max_vfs; vf++)
2165                 vfinfo[vf].clear_to_send = false;
2166
2167         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2168                 /* Turn off the copper */
2169                 ixgbe_set_phy_power(hw, false);
2170         } else {
2171                 /* Turn off the laser */
2172                 ixgbe_disable_tx_laser(hw);
2173         }
2174
2175         ixgbe_dev_clear_queues(dev);
2176
2177         /* Clear stored conf */
2178         dev->data->scattered_rx = 0;
2179         dev->data->lro = 0;
2180
2181         /* Clear recorded link status */
2182         memset(&link, 0, sizeof(link));
2183         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2184
2185         /* Remove all ntuple filters of the device */
2186         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2187              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2188                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2189                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2190                              p_5tuple, entries);
2191                 rte_free(p_5tuple);
2192         }
2193         memset(filter_info->fivetuple_mask, 0,
2194                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2195
2196         /* Clean datapath event and queue/vec mapping */
2197         rte_intr_efd_disable(intr_handle);
2198         if (intr_handle->intr_vec != NULL) {
2199                 rte_free(intr_handle->intr_vec);
2200                 intr_handle->intr_vec = NULL;
2201         }
2202 }
2203
2204 /*
2205  * Set device link up: enable tx.
2206  */
2207 static int
2208 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2209 {
2210         struct ixgbe_hw *hw =
2211                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2212         if (hw->mac.type == ixgbe_mac_82599EB) {
2213 #ifdef RTE_NIC_BYPASS
2214                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2215                         /* Not suported in bypass mode */
2216                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2217                                      "by device id 0x%x", hw->device_id);
2218                         return -ENOTSUP;
2219                 }
2220 #endif
2221         }
2222
2223         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2224                 /* Turn on the copper */
2225                 ixgbe_set_phy_power(hw, true);
2226         } else {
2227                 /* Turn on the laser */
2228                 ixgbe_enable_tx_laser(hw);
2229         }
2230
2231         return 0;
2232 }
2233
2234 /*
2235  * Set device link down: disable tx.
2236  */
2237 static int
2238 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2239 {
2240         struct ixgbe_hw *hw =
2241                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2242         if (hw->mac.type == ixgbe_mac_82599EB) {
2243 #ifdef RTE_NIC_BYPASS
2244                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2245                         /* Not suported in bypass mode */
2246                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2247                                      "by device id 0x%x", hw->device_id);
2248                         return -ENOTSUP;
2249                 }
2250 #endif
2251         }
2252
2253         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2254                 /* Turn off the copper */
2255                 ixgbe_set_phy_power(hw, false);
2256         } else {
2257                 /* Turn off the laser */
2258                 ixgbe_disable_tx_laser(hw);
2259         }
2260
2261         return 0;
2262 }
2263
2264 /*
2265  * Reest and stop device.
2266  */
2267 static void
2268 ixgbe_dev_close(struct rte_eth_dev *dev)
2269 {
2270         struct ixgbe_hw *hw =
2271                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2272
2273         PMD_INIT_FUNC_TRACE();
2274
2275         ixgbe_pf_reset_hw(hw);
2276
2277         ixgbe_dev_stop(dev);
2278         hw->adapter_stopped = 1;
2279
2280         ixgbe_dev_free_queues(dev);
2281
2282         ixgbe_disable_pcie_master(hw);
2283
2284         /* reprogram the RAR[0] in case user changed it. */
2285         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2286 }
2287
2288 static void
2289 ixgbe_read_stats_registers(struct ixgbe_hw *hw, struct ixgbe_hw_stats
2290                                                    *hw_stats, uint64_t *total_missed_rx,
2291                                                    uint64_t *total_qbrc, uint64_t *total_qprc,
2292                                                    uint64_t *total_qprdc)
2293 {
2294         uint32_t bprc, lxon, lxoff, total;
2295         unsigned i;
2296
2297         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2298         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2299         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2300         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2301
2302         for (i = 0; i < 8; i++) {
2303                 uint32_t mp;
2304                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2305                 /* global total per queue */
2306                 hw_stats->mpc[i] += mp;
2307                 /* Running comprehensive total for stats display */
2308                 *total_missed_rx += hw_stats->mpc[i];
2309                 if (hw->mac.type == ixgbe_mac_82598EB) {
2310                         hw_stats->rnbc[i] +=
2311                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2312                         hw_stats->pxonrxc[i] +=
2313                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2314                         hw_stats->pxoffrxc[i] +=
2315                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2316                 } else {
2317                         hw_stats->pxonrxc[i] +=
2318                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2319                         hw_stats->pxoffrxc[i] +=
2320                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2321                         hw_stats->pxon2offc[i] +=
2322                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2323                 }
2324                 hw_stats->pxontxc[i] +=
2325                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2326                 hw_stats->pxofftxc[i] +=
2327                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2328         }
2329         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2330                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2331                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2332                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2333                 hw_stats->qbrc[i] +=
2334                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2335                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2336                 hw_stats->qbtc[i] +=
2337                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2338                 *total_qprdc += hw_stats->qprdc[i] +=
2339                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2340
2341                 *total_qprc += hw_stats->qprc[i];
2342                 *total_qbrc += hw_stats->qbrc[i];
2343         }
2344         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2345         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2346         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2347
2348         /* Note that gprc counts missed packets */
2349         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2350
2351         if (hw->mac.type != ixgbe_mac_82598EB) {
2352                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2353                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2354                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2355                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2356                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2357                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2358                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2359                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2360         } else {
2361                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2362                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2363                 /* 82598 only has a counter in the high register */
2364                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2365                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2366                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2367         }
2368
2369         /*
2370          * Workaround: mprc hardware is incorrectly counting
2371          * broadcasts, so for now we subtract those.
2372          */
2373         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2374         hw_stats->bprc += bprc;
2375         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2376         if (hw->mac.type == ixgbe_mac_82598EB)
2377                 hw_stats->mprc -= bprc;
2378
2379         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2380         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2381         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2382         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2383         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2384         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2385
2386         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2387         hw_stats->lxontxc += lxon;
2388         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2389         hw_stats->lxofftxc += lxoff;
2390         total = lxon + lxoff;
2391
2392         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2393         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2394         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2395         hw_stats->gptc -= total;
2396         hw_stats->mptc -= total;
2397         hw_stats->ptc64 -= total;
2398         hw_stats->gotc -= total * ETHER_MIN_LEN;
2399
2400         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2401         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2402         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2403         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2404         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2405         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2406         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2407         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2408         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2409         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2410         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2411         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2412         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2413         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2414         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2415         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2416         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2417         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2418         /* Only read FCOE on 82599 */
2419         if (hw->mac.type != ixgbe_mac_82598EB) {
2420                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2421                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2422                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2423                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2424                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2425         }
2426
2427         /* Flow Director Stats registers */
2428         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2429         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2430 }
2431
2432 /*
2433  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2434  */
2435 static void
2436 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2437 {
2438         struct ixgbe_hw *hw =
2439                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2440         struct ixgbe_hw_stats *hw_stats =
2441                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2442         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2443         unsigned i;
2444
2445         total_missed_rx = 0;
2446         total_qbrc = 0;
2447         total_qprc = 0;
2448         total_qprdc = 0;
2449
2450         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2451                         &total_qprc, &total_qprdc);
2452
2453         if (stats == NULL)
2454                 return;
2455
2456         /* Fill out the rte_eth_stats statistics structure */
2457         stats->ipackets = total_qprc;
2458         stats->ibytes = total_qbrc;
2459         stats->opackets = hw_stats->gptc;
2460         stats->obytes = hw_stats->gotc;
2461
2462         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2463                 stats->q_ipackets[i] = hw_stats->qprc[i];
2464                 stats->q_opackets[i] = hw_stats->qptc[i];
2465                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2466                 stats->q_obytes[i] = hw_stats->qbtc[i];
2467                 stats->q_errors[i] = hw_stats->qprdc[i];
2468         }
2469
2470         /* Rx Errors */
2471         stats->ierrors  = hw_stats->crcerrs +
2472                           hw_stats->mspdc +
2473                           hw_stats->rlec +
2474                           hw_stats->ruc +
2475                           hw_stats->roc +
2476                           total_missed_rx +
2477                           hw_stats->illerrc +
2478                           hw_stats->errbc +
2479                           hw_stats->xec +
2480                           hw_stats->rfc +
2481                           hw_stats->fccrc +
2482                           hw_stats->fclast;
2483
2484         /* Tx Errors */
2485         stats->oerrors  = 0;
2486 }
2487
2488 static void
2489 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2490 {
2491         struct ixgbe_hw_stats *stats =
2492                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2493
2494         /* HW registers are cleared on read */
2495         ixgbe_dev_stats_get(dev, NULL);
2496
2497         /* Reset software totals */
2498         memset(stats, 0, sizeof(*stats));
2499 }
2500
2501 static int
2502 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2503                                          unsigned n)
2504 {
2505         struct ixgbe_hw *hw =
2506                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2507         struct ixgbe_hw_stats *hw_stats =
2508                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2509         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2510         unsigned i, count = IXGBE_NB_XSTATS;
2511
2512         if (n < count)
2513                 return count;
2514
2515         total_missed_rx = 0;
2516         total_qbrc = 0;
2517         total_qprc = 0;
2518         total_qprdc = 0;
2519
2520         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2521                                    &total_qprc, &total_qprdc);
2522
2523         /* If this is a reset xstats is NULL, and we have cleared the
2524          * registers by reading them.
2525          */
2526         if (!xstats)
2527                 return 0;
2528
2529         /* Extended stats from ixgbe_hw_stats */
2530         count = 0;
2531         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2532                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2533                          rte_ixgbe_stats_strings[i].name);
2534                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2535                                 rte_ixgbe_stats_strings[i].offset);
2536                 count++;
2537         }
2538
2539         /* Per-Q stats, with 8 queues available */
2540         for (i = 0; i < 8; i++) {
2541                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2542                          "rx_q%u_mbuf_allocation_errors", i);
2543                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2544                                 offsetof(struct ixgbe_hw_stats, rnbc[i]));
2545                 count++;
2546
2547                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2548                          "rx_q%u_missed_packets", i);
2549                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2550                                 offsetof(struct ixgbe_hw_stats, mpc[i]));
2551                 count++;
2552
2553                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2554                          "rx_q%u_xon_priority_packets", i);
2555                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2556                                 offsetof(struct ixgbe_hw_stats, pxonrxc[i]));
2557                 count++;
2558
2559                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2560                          "tx_q%u_xon_priority_packets", i);
2561                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2562                                 offsetof(struct ixgbe_hw_stats, pxontxc[i]));
2563                 count++;
2564
2565                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2566                          "rx_q%u_xoff_priority_packets", i);
2567                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2568                                 offsetof(struct ixgbe_hw_stats, pxoffrxc[i]));
2569                 count++;
2570
2571                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2572                          "tx_q%u_xoff_priority_packets", i);
2573                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2574                                 offsetof(struct ixgbe_hw_stats, pxofftxc[i]));
2575                 count++;
2576
2577                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2578                          "xx_q%u_xon_to_xoff_priority_packets", i);
2579                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2580                                 offsetof(struct ixgbe_hw_stats, pxon2offc[i]));
2581                 count++;
2582         }
2583
2584         for (i = 0; i < 16; i++) {
2585                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2586                          "rx_q%u_packets", i);
2587                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2588                                 offsetof(struct ixgbe_hw_stats, qprc[i]));
2589                 count++;
2590
2591                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2592                          "rx_q%u_bytes", i);
2593                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2594                                 offsetof(struct ixgbe_hw_stats, qbrc[i]));
2595                 count++;
2596
2597                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2598                          "tx_q%u_packets", i);
2599                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2600                                 offsetof(struct ixgbe_hw_stats, qptc[i]));
2601                 count++;
2602
2603                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2604                          "tx_q%u_bytes", i);
2605                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2606                                 offsetof(struct ixgbe_hw_stats, qbtc[i]));
2607                 count++;
2608
2609                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2610                          "rx_q%u_dropped", i);
2611                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2612                                 offsetof(struct ixgbe_hw_stats, qprdc[i]));
2613                 count++;
2614         }
2615
2616         return count;
2617 }
2618
2619 static void
2620 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2621 {
2622         struct ixgbe_hw_stats *stats =
2623                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2624
2625         /* HW registers are cleared on read */
2626         ixgbe_dev_xstats_get(dev, NULL, IXGBE_NB_XSTATS);
2627
2628         /* Reset software totals */
2629         memset(stats, 0, sizeof(*stats));
2630 }
2631
2632 static void
2633 ixgbevf_update_stats(struct rte_eth_dev *dev)
2634 {
2635         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2636         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2637                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2638
2639         /* Good Rx packet, include VF loopback */
2640         UPDATE_VF_STAT(IXGBE_VFGPRC,
2641             hw_stats->last_vfgprc, hw_stats->vfgprc);
2642
2643         /* Good Rx octets, include VF loopback */
2644         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2645             hw_stats->last_vfgorc, hw_stats->vfgorc);
2646
2647         /* Good Tx packet, include VF loopback */
2648         UPDATE_VF_STAT(IXGBE_VFGPTC,
2649             hw_stats->last_vfgptc, hw_stats->vfgptc);
2650
2651         /* Good Tx octets, include VF loopback */
2652         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2653             hw_stats->last_vfgotc, hw_stats->vfgotc);
2654
2655         /* Rx Multicst Packet */
2656         UPDATE_VF_STAT(IXGBE_VFMPRC,
2657             hw_stats->last_vfmprc, hw_stats->vfmprc);
2658 }
2659
2660 static int
2661 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2662                        unsigned n)
2663 {
2664         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2665                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2666         unsigned i;
2667
2668         if (n < IXGBEVF_NB_XSTATS)
2669                 return IXGBEVF_NB_XSTATS;
2670
2671         ixgbevf_update_stats(dev);
2672
2673         if (!xstats)
2674                 return 0;
2675
2676         /* Extended stats */
2677         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2678                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2679                          "%s", rte_ixgbevf_stats_strings[i].name);
2680                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2681                         rte_ixgbevf_stats_strings[i].offset);
2682         }
2683
2684         return IXGBEVF_NB_XSTATS;
2685 }
2686
2687 static void
2688 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2689 {
2690         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2691                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2692
2693         ixgbevf_update_stats(dev);
2694
2695         if (stats == NULL)
2696                 return;
2697
2698         stats->ipackets = hw_stats->vfgprc;
2699         stats->ibytes = hw_stats->vfgorc;
2700         stats->opackets = hw_stats->vfgptc;
2701         stats->obytes = hw_stats->vfgotc;
2702         stats->imcasts = hw_stats->vfmprc;
2703         /* stats->imcasts should be removed as imcasts is deprecated */
2704 }
2705
2706 static void
2707 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2708 {
2709         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2710                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2711
2712         /* Sync HW register to the last stats */
2713         ixgbevf_dev_stats_get(dev, NULL);
2714
2715         /* reset HW current stats*/
2716         hw_stats->vfgprc = 0;
2717         hw_stats->vfgorc = 0;
2718         hw_stats->vfgptc = 0;
2719         hw_stats->vfgotc = 0;
2720         hw_stats->vfmprc = 0;
2721
2722 }
2723
2724 static void
2725 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2726 {
2727         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2728
2729         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2730         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2731         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2732         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2733         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2734         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2735         dev_info->max_vfs = dev->pci_dev->max_vfs;
2736         if (hw->mac.type == ixgbe_mac_82598EB)
2737                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2738         else
2739                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2740         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2741         dev_info->rx_offload_capa =
2742                 DEV_RX_OFFLOAD_VLAN_STRIP |
2743                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2744                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2745                 DEV_RX_OFFLOAD_TCP_CKSUM;
2746
2747         /*
2748          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2749          * mode.
2750          */
2751         if ((hw->mac.type == ixgbe_mac_82599EB ||
2752              hw->mac.type == ixgbe_mac_X540) &&
2753             !RTE_ETH_DEV_SRIOV(dev).active)
2754                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2755
2756         dev_info->tx_offload_capa =
2757                 DEV_TX_OFFLOAD_VLAN_INSERT |
2758                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2759                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2760                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2761                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2762                 DEV_TX_OFFLOAD_TCP_TSO;
2763
2764         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2765                 .rx_thresh = {
2766                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2767                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2768                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2769                 },
2770                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2771                 .rx_drop_en = 0,
2772         };
2773
2774         dev_info->default_txconf = (struct rte_eth_txconf) {
2775                 .tx_thresh = {
2776                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2777                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2778                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2779                 },
2780                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2781                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2782                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2783                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2784         };
2785
2786         dev_info->rx_desc_lim = rx_desc_lim;
2787         dev_info->tx_desc_lim = tx_desc_lim;
2788
2789         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2790         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2791         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2792 }
2793
2794 static void
2795 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2796                      struct rte_eth_dev_info *dev_info)
2797 {
2798         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2799
2800         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2801         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2802         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2803         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2804         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2805         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2806         dev_info->max_vfs = dev->pci_dev->max_vfs;
2807         if (hw->mac.type == ixgbe_mac_82598EB)
2808                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2809         else
2810                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2811         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2812                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2813                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2814                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2815         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2816                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2817                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2818                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2819                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2820                                 DEV_TX_OFFLOAD_TCP_TSO;
2821
2822         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2823                 .rx_thresh = {
2824                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2825                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2826                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2827                 },
2828                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2829                 .rx_drop_en = 0,
2830         };
2831
2832         dev_info->default_txconf = (struct rte_eth_txconf) {
2833                 .tx_thresh = {
2834                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2835                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2836                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2837                 },
2838                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2839                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2840                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2841                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2842         };
2843
2844         dev_info->rx_desc_lim = rx_desc_lim;
2845         dev_info->tx_desc_lim = tx_desc_lim;
2846 }
2847
2848 /* return 0 means link status changed, -1 means not changed */
2849 static int
2850 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2851 {
2852         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2853         struct rte_eth_link link, old;
2854         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2855         int link_up;
2856         int diag;
2857
2858         link.link_status = 0;
2859         link.link_speed = 0;
2860         link.link_duplex = 0;
2861         memset(&old, 0, sizeof(old));
2862         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2863
2864         hw->mac.get_link_status = true;
2865
2866         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2867         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2868                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2869         else
2870                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2871
2872         if (diag != 0) {
2873                 link.link_speed = ETH_LINK_SPEED_100;
2874                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2875                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2876                 if (link.link_status == old.link_status)
2877                         return -1;
2878                 return 0;
2879         }
2880
2881         if (link_up == 0) {
2882                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2883                 if (link.link_status == old.link_status)
2884                         return -1;
2885                 return 0;
2886         }
2887         link.link_status = 1;
2888         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2889
2890         switch (link_speed) {
2891         default:
2892         case IXGBE_LINK_SPEED_UNKNOWN:
2893                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2894                 link.link_speed = ETH_LINK_SPEED_100;
2895                 break;
2896
2897         case IXGBE_LINK_SPEED_100_FULL:
2898                 link.link_speed = ETH_LINK_SPEED_100;
2899                 break;
2900
2901         case IXGBE_LINK_SPEED_1GB_FULL:
2902                 link.link_speed = ETH_LINK_SPEED_1000;
2903                 break;
2904
2905         case IXGBE_LINK_SPEED_10GB_FULL:
2906                 link.link_speed = ETH_LINK_SPEED_10000;
2907                 break;
2908         }
2909         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2910
2911         if (link.link_status == old.link_status)
2912                 return -1;
2913
2914         return 0;
2915 }
2916
2917 static void
2918 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2919 {
2920         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2921         uint32_t fctrl;
2922
2923         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2924         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2925         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2926 }
2927
2928 static void
2929 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2930 {
2931         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2932         uint32_t fctrl;
2933
2934         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2935         fctrl &= (~IXGBE_FCTRL_UPE);
2936         if (dev->data->all_multicast == 1)
2937                 fctrl |= IXGBE_FCTRL_MPE;
2938         else
2939                 fctrl &= (~IXGBE_FCTRL_MPE);
2940         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2941 }
2942
2943 static void
2944 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2945 {
2946         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2947         uint32_t fctrl;
2948
2949         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2950         fctrl |= IXGBE_FCTRL_MPE;
2951         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2952 }
2953
2954 static void
2955 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2956 {
2957         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2958         uint32_t fctrl;
2959
2960         if (dev->data->promiscuous == 1)
2961                 return; /* must remain in all_multicast mode */
2962
2963         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2964         fctrl &= (~IXGBE_FCTRL_MPE);
2965         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2966 }
2967
2968 /**
2969  * It clears the interrupt causes and enables the interrupt.
2970  * It will be called once only during nic initialized.
2971  *
2972  * @param dev
2973  *  Pointer to struct rte_eth_dev.
2974  *
2975  * @return
2976  *  - On success, zero.
2977  *  - On failure, a negative value.
2978  */
2979 static int
2980 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2981 {
2982         struct ixgbe_interrupt *intr =
2983                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2984
2985         ixgbe_dev_link_status_print(dev);
2986         intr->mask |= IXGBE_EICR_LSC;
2987
2988         return 0;
2989 }
2990
2991 /**
2992  * It clears the interrupt causes and enables the interrupt.
2993  * It will be called once only during nic initialized.
2994  *
2995  * @param dev
2996  *  Pointer to struct rte_eth_dev.
2997  *
2998  * @return
2999  *  - On success, zero.
3000  *  - On failure, a negative value.
3001  */
3002 static int
3003 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3004 {
3005         struct ixgbe_interrupt *intr =
3006                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3007
3008         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3009
3010         return 0;
3011 }
3012
3013 /*
3014  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3015  *
3016  * @param dev
3017  *  Pointer to struct rte_eth_dev.
3018  *
3019  * @return
3020  *  - On success, zero.
3021  *  - On failure, a negative value.
3022  */
3023 static int
3024 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3025 {
3026         uint32_t eicr;
3027         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3028         struct ixgbe_interrupt *intr =
3029                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3030
3031         /* clear all cause mask */
3032         ixgbe_disable_intr(hw);
3033
3034         /* read-on-clear nic registers here */
3035         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3036         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3037
3038         intr->flags = 0;
3039
3040         /* set flag for async link update */
3041         if (eicr & IXGBE_EICR_LSC)
3042                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3043
3044         if (eicr & IXGBE_EICR_MAILBOX)
3045                 intr->flags |= IXGBE_FLAG_MAILBOX;
3046
3047         return 0;
3048 }
3049
3050 static int
3051 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
3052 {
3053         uint32_t eicr;
3054         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3055         struct ixgbe_interrupt *intr =
3056                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3057
3058         /* clear all cause mask */
3059         ixgbevf_intr_disable(hw);
3060
3061         /* read-on-clear nic registers here */
3062         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
3063         PMD_DRV_LOG(INFO, "eicr %x", eicr);
3064
3065         intr->flags = 0;
3066
3067         /* set flag for async link update */
3068         if (eicr & IXGBE_EICR_LSC)
3069                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3070
3071         return 0;
3072 }
3073
3074 /**
3075  * It gets and then prints the link status.
3076  *
3077  * @param dev
3078  *  Pointer to struct rte_eth_dev.
3079  *
3080  * @return
3081  *  - On success, zero.
3082  *  - On failure, a negative value.
3083  */
3084 static void
3085 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3086 {
3087         struct rte_eth_link link;
3088
3089         memset(&link, 0, sizeof(link));
3090         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3091         if (link.link_status) {
3092                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3093                                         (int)(dev->data->port_id),
3094                                         (unsigned)link.link_speed,
3095                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3096                                         "full-duplex" : "half-duplex");
3097         } else {
3098                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3099                                 (int)(dev->data->port_id));
3100         }
3101         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3102                                 dev->pci_dev->addr.domain,
3103                                 dev->pci_dev->addr.bus,
3104                                 dev->pci_dev->addr.devid,
3105                                 dev->pci_dev->addr.function);
3106 }
3107
3108 /*
3109  * It executes link_update after knowing an interrupt occurred.
3110  *
3111  * @param dev
3112  *  Pointer to struct rte_eth_dev.
3113  *
3114  * @return
3115  *  - On success, zero.
3116  *  - On failure, a negative value.
3117  */
3118 static int
3119 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3120 {
3121         struct ixgbe_interrupt *intr =
3122                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3123         int64_t timeout;
3124         struct rte_eth_link link;
3125         int intr_enable_delay = false;
3126
3127         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3128
3129         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3130                 ixgbe_pf_mbx_process(dev);
3131                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3132         }
3133
3134         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3135                 /* get the link status before link update, for predicting later */
3136                 memset(&link, 0, sizeof(link));
3137                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3138
3139                 ixgbe_dev_link_update(dev, 0);
3140
3141                 /* likely to up */
3142                 if (!link.link_status)
3143                         /* handle it 1 sec later, wait it being stable */
3144                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3145                 /* likely to down */
3146                 else
3147                         /* handle it 4 sec later, wait it being stable */
3148                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3149
3150                 ixgbe_dev_link_status_print(dev);
3151
3152                 intr_enable_delay = true;
3153         }
3154
3155         if (intr_enable_delay) {
3156                 if (rte_eal_alarm_set(timeout * 1000,
3157                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3158                         PMD_DRV_LOG(ERR, "Error setting alarm");
3159         } else {
3160                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3161                 ixgbe_enable_intr(dev);
3162                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3163         }
3164
3165
3166         return 0;
3167 }
3168
3169 static int
3170 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
3171 {
3172         struct ixgbe_hw *hw =
3173                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3174
3175         PMD_DRV_LOG(DEBUG, "enable intr immediately");
3176         ixgbevf_intr_enable(hw);
3177         rte_intr_enable(&dev->pci_dev->intr_handle);
3178         return 0;
3179 }
3180
3181 /**
3182  * Interrupt handler which shall be registered for alarm callback for delayed
3183  * handling specific interrupt to wait for the stable nic state. As the
3184  * NIC interrupt state is not stable for ixgbe after link is just down,
3185  * it needs to wait 4 seconds to get the stable status.
3186  *
3187  * @param handle
3188  *  Pointer to interrupt handle.
3189  * @param param
3190  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3191  *
3192  * @return
3193  *  void
3194  */
3195 static void
3196 ixgbe_dev_interrupt_delayed_handler(void *param)
3197 {
3198         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3199         struct ixgbe_interrupt *intr =
3200                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3201         struct ixgbe_hw *hw =
3202                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3203         uint32_t eicr;
3204
3205         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3206         if (eicr & IXGBE_EICR_MAILBOX)
3207                 ixgbe_pf_mbx_process(dev);
3208
3209         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3210                 ixgbe_dev_link_update(dev, 0);
3211                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3212                 ixgbe_dev_link_status_print(dev);
3213                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3214         }
3215
3216         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3217         ixgbe_enable_intr(dev);
3218         rte_intr_enable(&(dev->pci_dev->intr_handle));
3219 }
3220
3221 /**
3222  * Interrupt handler triggered by NIC  for handling
3223  * specific interrupt.
3224  *
3225  * @param handle
3226  *  Pointer to interrupt handle.
3227  * @param param
3228  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3229  *
3230  * @return
3231  *  void
3232  */
3233 static void
3234 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3235                             void *param)
3236 {
3237         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3238
3239         ixgbe_dev_interrupt_get_status(dev);
3240         ixgbe_dev_interrupt_action(dev);
3241 }
3242
3243 static void
3244 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3245                               void *param)
3246 {
3247         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3248
3249         ixgbevf_dev_interrupt_get_status(dev);
3250         ixgbevf_dev_interrupt_action(dev);
3251 }
3252
3253 static int
3254 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3255 {
3256         struct ixgbe_hw *hw;
3257
3258         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3259         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3260 }
3261
3262 static int
3263 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3264 {
3265         struct ixgbe_hw *hw;
3266
3267         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3268         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3269 }
3270
3271 static int
3272 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3273 {
3274         struct ixgbe_hw *hw;
3275         uint32_t mflcn_reg;
3276         uint32_t fccfg_reg;
3277         int rx_pause;
3278         int tx_pause;
3279
3280         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3281
3282         fc_conf->pause_time = hw->fc.pause_time;
3283         fc_conf->high_water = hw->fc.high_water[0];
3284         fc_conf->low_water = hw->fc.low_water[0];
3285         fc_conf->send_xon = hw->fc.send_xon;
3286         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3287
3288         /*
3289          * Return rx_pause status according to actual setting of
3290          * MFLCN register.
3291          */
3292         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3293         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3294                 rx_pause = 1;
3295         else
3296                 rx_pause = 0;
3297
3298         /*
3299          * Return tx_pause status according to actual setting of
3300          * FCCFG register.
3301          */
3302         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3303         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3304                 tx_pause = 1;
3305         else
3306                 tx_pause = 0;
3307
3308         if (rx_pause && tx_pause)
3309                 fc_conf->mode = RTE_FC_FULL;
3310         else if (rx_pause)
3311                 fc_conf->mode = RTE_FC_RX_PAUSE;
3312         else if (tx_pause)
3313                 fc_conf->mode = RTE_FC_TX_PAUSE;
3314         else
3315                 fc_conf->mode = RTE_FC_NONE;
3316
3317         return 0;
3318 }
3319
3320 static int
3321 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3322 {
3323         struct ixgbe_hw *hw;
3324         int err;
3325         uint32_t rx_buf_size;
3326         uint32_t max_high_water;
3327         uint32_t mflcn;
3328         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3329                 ixgbe_fc_none,
3330                 ixgbe_fc_rx_pause,
3331                 ixgbe_fc_tx_pause,
3332                 ixgbe_fc_full
3333         };
3334
3335         PMD_INIT_FUNC_TRACE();
3336
3337         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3338         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3339         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3340
3341         /*
3342          * At least reserve one Ethernet frame for watermark
3343          * high_water/low_water in kilo bytes for ixgbe
3344          */
3345         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3346         if ((fc_conf->high_water > max_high_water) ||
3347                 (fc_conf->high_water < fc_conf->low_water)) {
3348                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3349                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3350                 return (-EINVAL);
3351         }
3352
3353         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3354         hw->fc.pause_time     = fc_conf->pause_time;
3355         hw->fc.high_water[0]  = fc_conf->high_water;
3356         hw->fc.low_water[0]   = fc_conf->low_water;
3357         hw->fc.send_xon       = fc_conf->send_xon;
3358         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3359
3360         err = ixgbe_fc_enable(hw);
3361
3362         /* Not negotiated is not an error case */
3363         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3364
3365                 /* check if we want to forward MAC frames - driver doesn't have native
3366                  * capability to do that, so we'll write the registers ourselves */
3367
3368                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3369
3370                 /* set or clear MFLCN.PMCF bit depending on configuration */
3371                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3372                         mflcn |= IXGBE_MFLCN_PMCF;
3373                 else
3374                         mflcn &= ~IXGBE_MFLCN_PMCF;
3375
3376                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3377                 IXGBE_WRITE_FLUSH(hw);
3378
3379                 return 0;
3380         }
3381
3382         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3383         return -EIO;
3384 }
3385
3386 /**
3387  *  ixgbe_pfc_enable_generic - Enable flow control
3388  *  @hw: pointer to hardware structure
3389  *  @tc_num: traffic class number
3390  *  Enable flow control according to the current settings.
3391  */
3392 static int
3393 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3394 {
3395         int ret_val = 0;
3396         uint32_t mflcn_reg, fccfg_reg;
3397         uint32_t reg;
3398         uint32_t fcrtl, fcrth;
3399         uint8_t i;
3400         uint8_t nb_rx_en;
3401
3402         /* Validate the water mark configuration */
3403         if (!hw->fc.pause_time) {
3404                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3405                 goto out;
3406         }
3407
3408         /* Low water mark of zero causes XOFF floods */
3409         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3410                  /* High/Low water can not be 0 */
3411                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
3412                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3413                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3414                         goto out;
3415                 }
3416
3417                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3418                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3419                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3420                         goto out;
3421                 }
3422         }
3423         /* Negotiate the fc mode to use */
3424         ixgbe_fc_autoneg(hw);
3425
3426         /* Disable any previous flow control settings */
3427         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3428         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3429
3430         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3431         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3432
3433         switch (hw->fc.current_mode) {
3434         case ixgbe_fc_none:
3435                 /*
3436                  * If the count of enabled RX Priority Flow control >1,
3437                  * and the TX pause can not be disabled
3438                  */
3439                 nb_rx_en = 0;
3440                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3441                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3442                         if (reg & IXGBE_FCRTH_FCEN)
3443                                 nb_rx_en++;
3444                 }
3445                 if (nb_rx_en > 1)
3446                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3447                 break;
3448         case ixgbe_fc_rx_pause:
3449                 /*
3450                  * Rx Flow control is enabled and Tx Flow control is
3451                  * disabled by software override. Since there really
3452                  * isn't a way to advertise that we are capable of RX
3453                  * Pause ONLY, we will advertise that we support both
3454                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3455                  * disable the adapter's ability to send PAUSE frames.
3456                  */
3457                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3458                 /*
3459                  * If the count of enabled RX Priority Flow control >1,
3460                  * and the TX pause can not be disabled
3461                  */
3462                 nb_rx_en = 0;
3463                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3464                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3465                         if (reg & IXGBE_FCRTH_FCEN)
3466                                 nb_rx_en++;
3467                 }
3468                 if (nb_rx_en > 1)
3469                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3470                 break;
3471         case ixgbe_fc_tx_pause:
3472                 /*
3473                  * Tx Flow control is enabled, and Rx Flow control is
3474                  * disabled by software override.
3475                  */
3476                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3477                 break;
3478         case ixgbe_fc_full:
3479                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3480                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3481                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3482                 break;
3483         default:
3484                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3485                 ret_val = IXGBE_ERR_CONFIG;
3486                 goto out;
3487                 break;
3488         }
3489
3490         /* Set 802.3x based flow control settings. */
3491         mflcn_reg |= IXGBE_MFLCN_DPF;
3492         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3493         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3494
3495         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3496         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3497                 hw->fc.high_water[tc_num]) {
3498                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3499                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3500                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3501         } else {
3502                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3503                 /*
3504                  * In order to prevent Tx hangs when the internal Tx
3505                  * switch is enabled we must set the high water mark
3506                  * to the maximum FCRTH value.  This allows the Tx
3507                  * switch to function even under heavy Rx workloads.
3508                  */
3509                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3510         }
3511         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3512
3513         /* Configure pause time (2 TCs per register) */
3514         reg = hw->fc.pause_time * 0x00010001;
3515         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3516                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3517
3518         /* Configure flow control refresh threshold value */
3519         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3520
3521 out:
3522         return ret_val;
3523 }
3524
3525 static int
3526 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3527 {
3528         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3529         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3530
3531         if(hw->mac.type != ixgbe_mac_82598EB) {
3532                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3533         }
3534         return ret_val;
3535 }
3536
3537 static int
3538 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3539 {
3540         int err;
3541         uint32_t rx_buf_size;
3542         uint32_t max_high_water;
3543         uint8_t tc_num;
3544         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3545         struct ixgbe_hw *hw =
3546                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3547         struct ixgbe_dcb_config *dcb_config =
3548                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3549
3550         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3551                 ixgbe_fc_none,
3552                 ixgbe_fc_rx_pause,
3553                 ixgbe_fc_tx_pause,
3554                 ixgbe_fc_full
3555         };
3556
3557         PMD_INIT_FUNC_TRACE();
3558
3559         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3560         tc_num = map[pfc_conf->priority];
3561         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3562         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3563         /*
3564          * At least reserve one Ethernet frame for watermark
3565          * high_water/low_water in kilo bytes for ixgbe
3566          */
3567         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3568         if ((pfc_conf->fc.high_water > max_high_water) ||
3569             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3570                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3571                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3572                 return (-EINVAL);
3573         }
3574
3575         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3576         hw->fc.pause_time = pfc_conf->fc.pause_time;
3577         hw->fc.send_xon = pfc_conf->fc.send_xon;
3578         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3579         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3580
3581         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3582
3583         /* Not negotiated is not an error case */
3584         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3585                 return 0;
3586
3587         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3588         return -EIO;
3589 }
3590
3591 static int
3592 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3593                           struct rte_eth_rss_reta_entry64 *reta_conf,
3594                           uint16_t reta_size)
3595 {
3596         uint8_t i, j, mask;
3597         uint32_t reta, r;
3598         uint16_t idx, shift;
3599         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3600         uint16_t sp_reta_size;
3601         uint32_t reta_reg;
3602
3603         PMD_INIT_FUNC_TRACE();
3604
3605         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3606                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3607                         "NIC.");
3608                 return -ENOTSUP;
3609         }
3610
3611         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3612         if (reta_size != sp_reta_size) {
3613                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3614                         "(%d) doesn't match the number hardware can supported "
3615                         "(%d)\n", reta_size, sp_reta_size);
3616                 return -EINVAL;
3617         }
3618
3619         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3620                 idx = i / RTE_RETA_GROUP_SIZE;
3621                 shift = i % RTE_RETA_GROUP_SIZE;
3622                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3623                                                 IXGBE_4_BIT_MASK);
3624                 if (!mask)
3625                         continue;
3626                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3627                 if (mask == IXGBE_4_BIT_MASK)
3628                         r = 0;
3629                 else
3630                         r = IXGBE_READ_REG(hw, reta_reg);
3631                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3632                         if (mask & (0x1 << j))
3633                                 reta |= reta_conf[idx].reta[shift + j] <<
3634                                                         (CHAR_BIT * j);
3635                         else
3636                                 reta |= r & (IXGBE_8_BIT_MASK <<
3637                                                 (CHAR_BIT * j));
3638                 }
3639                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3640         }
3641
3642         return 0;
3643 }
3644
3645 static int
3646 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3647                          struct rte_eth_rss_reta_entry64 *reta_conf,
3648                          uint16_t reta_size)
3649 {
3650         uint8_t i, j, mask;
3651         uint32_t reta;
3652         uint16_t idx, shift;
3653         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3654         uint16_t sp_reta_size;
3655         uint32_t reta_reg;
3656
3657         PMD_INIT_FUNC_TRACE();
3658         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3659         if (reta_size != sp_reta_size) {
3660                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3661                         "(%d) doesn't match the number hardware can supported "
3662                         "(%d)\n", reta_size, sp_reta_size);
3663                 return -EINVAL;
3664         }
3665
3666         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3667                 idx = i / RTE_RETA_GROUP_SIZE;
3668                 shift = i % RTE_RETA_GROUP_SIZE;
3669                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3670                                                 IXGBE_4_BIT_MASK);
3671                 if (!mask)
3672                         continue;
3673
3674                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3675                 reta = IXGBE_READ_REG(hw, reta_reg);
3676                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3677                         if (mask & (0x1 << j))
3678                                 reta_conf[idx].reta[shift + j] =
3679                                         ((reta >> (CHAR_BIT * j)) &
3680                                                 IXGBE_8_BIT_MASK);
3681                 }
3682         }
3683
3684         return 0;
3685 }
3686
3687 static void
3688 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3689                                 uint32_t index, uint32_t pool)
3690 {
3691         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3692         uint32_t enable_addr = 1;
3693
3694         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3695 }
3696
3697 static void
3698 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3699 {
3700         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3701
3702         ixgbe_clear_rar(hw, index);
3703 }
3704
3705 static void
3706 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3707 {
3708         ixgbe_remove_rar(dev, 0);
3709
3710         ixgbe_add_rar(dev, addr, 0, 0);
3711 }
3712
3713 static int
3714 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3715 {
3716         uint32_t hlreg0;
3717         uint32_t maxfrs;
3718         struct ixgbe_hw *hw;
3719         struct rte_eth_dev_info dev_info;
3720         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3721
3722         ixgbe_dev_info_get(dev, &dev_info);
3723
3724         /* check that mtu is within the allowed range */
3725         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3726                 return -EINVAL;
3727
3728         /* refuse mtu that requires the support of scattered packets when this
3729          * feature has not been enabled before. */
3730         if (!dev->data->scattered_rx &&
3731             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3732              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3733                 return -EINVAL;
3734
3735         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3736         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3737
3738         /* switch to jumbo mode if needed */
3739         if (frame_size > ETHER_MAX_LEN) {
3740                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3741                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3742         } else {
3743                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3744                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3745         }
3746         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3747
3748         /* update max frame size */
3749         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3750
3751         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3752         maxfrs &= 0x0000FFFF;
3753         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3754         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3755
3756         return 0;
3757 }
3758
3759 /*
3760  * Virtual Function operations
3761  */
3762 static void
3763 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3764 {
3765         PMD_INIT_FUNC_TRACE();
3766
3767         /* Clear interrupt mask to stop from interrupts being generated */
3768         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3769
3770         IXGBE_WRITE_FLUSH(hw);
3771 }
3772
3773 static void
3774 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3775 {
3776         PMD_INIT_FUNC_TRACE();
3777
3778         /* VF enable interrupt autoclean */
3779         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3780         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3781         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3782
3783         IXGBE_WRITE_FLUSH(hw);
3784 }
3785
3786 static int
3787 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3788 {
3789         struct rte_eth_conf* conf = &dev->data->dev_conf;
3790         struct ixgbe_adapter *adapter =
3791                         (struct ixgbe_adapter *)dev->data->dev_private;
3792
3793         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3794                      dev->data->port_id);
3795
3796         /*
3797          * VF has no ability to enable/disable HW CRC
3798          * Keep the persistent behavior the same as Host PF
3799          */
3800 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3801         if (!conf->rxmode.hw_strip_crc) {
3802                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3803                 conf->rxmode.hw_strip_crc = 1;
3804         }
3805 #else
3806         if (conf->rxmode.hw_strip_crc) {
3807                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3808                 conf->rxmode.hw_strip_crc = 0;
3809         }
3810 #endif
3811
3812         /*
3813          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3814          * allocation or vector Rx preconditions we will reset it.
3815          */
3816         adapter->rx_bulk_alloc_allowed = true;
3817         adapter->rx_vec_allowed = true;
3818
3819         return 0;
3820 }
3821
3822 static int
3823 ixgbevf_dev_start(struct rte_eth_dev *dev)
3824 {
3825         struct ixgbe_hw *hw =
3826                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3827         uint32_t intr_vector = 0;
3828         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3829
3830         int err, mask = 0;
3831
3832         PMD_INIT_FUNC_TRACE();
3833
3834         hw->mac.ops.reset_hw(hw);
3835         hw->mac.get_link_status = true;
3836
3837         /* negotiate mailbox API version to use with the PF. */
3838         ixgbevf_negotiate_api(hw);
3839
3840         ixgbevf_dev_tx_init(dev);
3841
3842         /* This can fail when allocating mbufs for descriptor rings */
3843         err = ixgbevf_dev_rx_init(dev);
3844         if (err) {
3845                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3846                 ixgbe_dev_clear_queues(dev);
3847                 return err;
3848         }
3849
3850         /* Set vfta */
3851         ixgbevf_set_vfta_all(dev,1);
3852
3853         /* Set HW strip */
3854         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3855                 ETH_VLAN_EXTEND_MASK;
3856         ixgbevf_vlan_offload_set(dev, mask);
3857
3858         ixgbevf_dev_rxtx_start(dev);
3859
3860         /* check and configure queue intr-vector mapping */
3861         if (dev->data->dev_conf.intr_conf.rxq != 0)
3862                 intr_vector = dev->data->nb_rx_queues;
3863
3864         if (rte_intr_efd_enable(intr_handle, intr_vector))
3865                 return -1;
3866
3867         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3868                 intr_handle->intr_vec =
3869                         rte_zmalloc("intr_vec",
3870                                     dev->data->nb_rx_queues * sizeof(int), 0);
3871                 if (intr_handle->intr_vec == NULL) {
3872                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3873                                      " intr_vec\n", dev->data->nb_rx_queues);
3874                         return -ENOMEM;
3875                 }
3876         }
3877         ixgbevf_configure_msix(dev);
3878
3879         if (dev->data->dev_conf.intr_conf.lsc != 0) {
3880                 if (rte_intr_allow_others(intr_handle))
3881                         rte_intr_callback_register(intr_handle,
3882                                         ixgbevf_dev_interrupt_handler,
3883                                         (void *)dev);
3884                 else
3885                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
3886                                      " no intr multiplex\n");
3887         }
3888
3889         rte_intr_enable(intr_handle);
3890
3891         /* Re-enable interrupt for VF */
3892         ixgbevf_intr_enable(hw);
3893
3894         return 0;
3895 }
3896
3897 static void
3898 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3899 {
3900         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3901         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3902
3903         PMD_INIT_FUNC_TRACE();
3904
3905         hw->adapter_stopped = 1;
3906         ixgbe_stop_adapter(hw);
3907
3908         /*
3909           * Clear what we set, but we still keep shadow_vfta to
3910           * restore after device starts
3911           */
3912         ixgbevf_set_vfta_all(dev,0);
3913
3914         /* Clear stored conf */
3915         dev->data->scattered_rx = 0;
3916
3917         ixgbe_dev_clear_queues(dev);
3918
3919         /* disable intr eventfd mapping */
3920         rte_intr_disable(intr_handle);
3921
3922         /* Clean datapath event and queue/vec mapping */
3923         rte_intr_efd_disable(intr_handle);
3924         if (intr_handle->intr_vec != NULL) {
3925                 rte_free(intr_handle->intr_vec);
3926                 intr_handle->intr_vec = NULL;
3927         }
3928 }
3929
3930 static void
3931 ixgbevf_dev_close(struct rte_eth_dev *dev)
3932 {
3933         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3934         struct rte_pci_device *pci_dev;
3935
3936         PMD_INIT_FUNC_TRACE();
3937
3938         ixgbe_reset_hw(hw);
3939
3940         ixgbevf_dev_stop(dev);
3941
3942         ixgbe_dev_free_queues(dev);
3943
3944         /* reprogram the RAR[0] in case user changed it. */
3945         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3946
3947         pci_dev = dev->pci_dev;
3948         if (pci_dev->intr_handle.intr_vec) {
3949                 rte_free(pci_dev->intr_handle.intr_vec);
3950                 pci_dev->intr_handle.intr_vec = NULL;
3951         }
3952 }
3953
3954 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3955 {
3956         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3957         struct ixgbe_vfta * shadow_vfta =
3958                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3959         int i = 0, j = 0, vfta = 0, mask = 1;
3960
3961         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3962                 vfta = shadow_vfta->vfta[i];
3963                 if(vfta){
3964                         mask = 1;
3965                         for (j = 0; j < 32; j++){
3966                                 if(vfta & mask)
3967                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3968                                 mask<<=1;
3969                         }
3970                 }
3971         }
3972
3973 }
3974
3975 static int
3976 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3977 {
3978         struct ixgbe_hw *hw =
3979                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3980         struct ixgbe_vfta * shadow_vfta =
3981                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3982         uint32_t vid_idx = 0;
3983         uint32_t vid_bit = 0;
3984         int ret = 0;
3985
3986         PMD_INIT_FUNC_TRACE();
3987
3988         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3989         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3990         if(ret){
3991                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3992                 return ret;
3993         }
3994         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3995         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3996
3997         /* Save what we set and retore it after device reset */
3998         if (on)
3999                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4000         else
4001                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4002
4003         return 0;
4004 }
4005
4006 static void
4007 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4008 {
4009         struct ixgbe_hw *hw =
4010                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4011         uint32_t ctrl;
4012
4013         PMD_INIT_FUNC_TRACE();
4014
4015         if(queue >= hw->mac.max_rx_queues)
4016                 return;
4017
4018         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4019         if(on)
4020                 ctrl |= IXGBE_RXDCTL_VME;
4021         else
4022                 ctrl &= ~IXGBE_RXDCTL_VME;
4023         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4024
4025         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4026 }
4027
4028 static void
4029 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4030 {
4031         struct ixgbe_hw *hw =
4032                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4033         uint16_t i;
4034         int on = 0;
4035
4036         /* VF function only support hw strip feature, others are not support */
4037         if(mask & ETH_VLAN_STRIP_MASK){
4038                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4039
4040                 for(i=0; i < hw->mac.max_rx_queues; i++)
4041                         ixgbevf_vlan_strip_queue_set(dev,i,on);
4042         }
4043 }
4044
4045 static int
4046 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4047 {
4048         uint32_t reg_val;
4049
4050         /* we only need to do this if VMDq is enabled */
4051         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4052         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4053                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4054                 return (-1);
4055         }
4056
4057         return 0;
4058 }
4059
4060 static uint32_t
4061 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4062 {
4063         uint32_t vector = 0;
4064         switch (hw->mac.mc_filter_type) {
4065         case 0:   /* use bits [47:36] of the address */
4066                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4067                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4068                 break;
4069         case 1:   /* use bits [46:35] of the address */
4070                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4071                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4072                 break;
4073         case 2:   /* use bits [45:34] of the address */
4074                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4075                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4076                 break;
4077         case 3:   /* use bits [43:32] of the address */
4078                 vector = ((uc_addr->addr_bytes[4]) |
4079                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4080                 break;
4081         default:  /* Invalid mc_filter_type */
4082                 break;
4083         }
4084
4085         /* vector can only be 12-bits or boundary will be exceeded */
4086         vector &= 0xFFF;
4087         return vector;
4088 }
4089
4090 static int
4091 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4092                                uint8_t on)
4093 {
4094         uint32_t vector;
4095         uint32_t uta_idx;
4096         uint32_t reg_val;
4097         uint32_t uta_shift;
4098         uint32_t rc;
4099         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4100         const uint32_t ixgbe_uta_bit_shift = 5;
4101         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4102         const uint32_t bit1 = 0x1;
4103
4104         struct ixgbe_hw *hw =
4105                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4106         struct ixgbe_uta_info *uta_info =
4107                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4108
4109         /* The UTA table only exists on 82599 hardware and newer */
4110         if (hw->mac.type < ixgbe_mac_82599EB)
4111                 return (-ENOTSUP);
4112
4113         vector = ixgbe_uta_vector(hw,mac_addr);
4114         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4115         uta_shift = vector & ixgbe_uta_bit_mask;
4116
4117         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4118         if(rc == on)
4119                 return 0;
4120
4121         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4122         if (on) {
4123                 uta_info->uta_in_use++;
4124                 reg_val |= (bit1 << uta_shift);
4125                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4126         } else {
4127                 uta_info->uta_in_use--;
4128                 reg_val &= ~(bit1 << uta_shift);
4129                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4130         }
4131
4132         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4133
4134         if (uta_info->uta_in_use > 0)
4135                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4136                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4137         else
4138                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4139
4140         return 0;
4141 }
4142
4143 static int
4144 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4145 {
4146         int i;
4147         struct ixgbe_hw *hw =
4148                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4149         struct ixgbe_uta_info *uta_info =
4150                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4151
4152         /* The UTA table only exists on 82599 hardware and newer */
4153         if (hw->mac.type < ixgbe_mac_82599EB)
4154                 return (-ENOTSUP);
4155
4156         if(on) {
4157                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4158                         uta_info->uta_shadow[i] = ~0;
4159                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4160                 }
4161         } else {
4162                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4163                         uta_info->uta_shadow[i] = 0;
4164                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4165                 }
4166         }
4167         return 0;
4168
4169 }
4170
4171 uint32_t
4172 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4173 {
4174         uint32_t new_val = orig_val;
4175
4176         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4177                 new_val |= IXGBE_VMOLR_AUPE;
4178         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4179                 new_val |= IXGBE_VMOLR_ROMPE;
4180         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4181                 new_val |= IXGBE_VMOLR_ROPE;
4182         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4183                 new_val |= IXGBE_VMOLR_BAM;
4184         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4185                 new_val |= IXGBE_VMOLR_MPE;
4186
4187         return new_val;
4188 }
4189
4190 static int
4191 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4192                                uint16_t rx_mask, uint8_t on)
4193 {
4194         int val = 0;
4195
4196         struct ixgbe_hw *hw =
4197                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4198         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4199
4200         if (hw->mac.type == ixgbe_mac_82598EB) {
4201                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4202                              " on 82599 hardware and newer");
4203                 return (-ENOTSUP);
4204         }
4205         if (ixgbe_vmdq_mode_check(hw) < 0)
4206                 return (-ENOTSUP);
4207
4208         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4209
4210         if (on)
4211                 vmolr |= val;
4212         else
4213                 vmolr &= ~val;
4214
4215         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4216
4217         return 0;
4218 }
4219
4220 static int
4221 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4222 {
4223         uint32_t reg,addr;
4224         uint32_t val;
4225         const uint8_t bit1 = 0x1;
4226
4227         struct ixgbe_hw *hw =
4228                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4229
4230         if (ixgbe_vmdq_mode_check(hw) < 0)
4231                 return (-ENOTSUP);
4232
4233         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4234         reg = IXGBE_READ_REG(hw, addr);
4235         val = bit1 << pool;
4236
4237         if (on)
4238                 reg |= val;
4239         else
4240                 reg &= ~val;
4241
4242         IXGBE_WRITE_REG(hw, addr,reg);
4243
4244         return 0;
4245 }
4246
4247 static int
4248 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4249 {
4250         uint32_t reg,addr;
4251         uint32_t val;
4252         const uint8_t bit1 = 0x1;
4253
4254         struct ixgbe_hw *hw =
4255                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4256
4257         if (ixgbe_vmdq_mode_check(hw) < 0)
4258                 return (-ENOTSUP);
4259
4260         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4261         reg = IXGBE_READ_REG(hw, addr);
4262         val = bit1 << pool;
4263
4264         if (on)
4265                 reg |= val;
4266         else
4267                 reg &= ~val;
4268
4269         IXGBE_WRITE_REG(hw, addr,reg);
4270
4271         return 0;
4272 }
4273
4274 static int
4275 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4276                         uint64_t pool_mask, uint8_t vlan_on)
4277 {
4278         int ret = 0;
4279         uint16_t pool_idx;
4280         struct ixgbe_hw *hw =
4281                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4282
4283         if (ixgbe_vmdq_mode_check(hw) < 0)
4284                 return (-ENOTSUP);
4285         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4286                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4287                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4288                         if (ret < 0)
4289                                 return ret;
4290         }
4291
4292         return ret;
4293 }
4294
4295 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4296 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4297 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4298 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4299 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4300         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4301         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4302
4303 static int
4304 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4305                         struct rte_eth_mirror_conf *mirror_conf,
4306                         uint8_t rule_id, uint8_t on)
4307 {
4308         uint32_t mr_ctl,vlvf;
4309         uint32_t mp_lsb = 0;
4310         uint32_t mv_msb = 0;
4311         uint32_t mv_lsb = 0;
4312         uint32_t mp_msb = 0;
4313         uint8_t i = 0;
4314         int reg_index = 0;
4315         uint64_t vlan_mask = 0;
4316
4317         const uint8_t pool_mask_offset = 32;
4318         const uint8_t vlan_mask_offset = 32;
4319         const uint8_t dst_pool_offset = 8;
4320         const uint8_t rule_mr_offset  = 4;
4321         const uint8_t mirror_rule_mask= 0x0F;
4322
4323         struct ixgbe_mirror_info *mr_info =
4324                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4325         struct ixgbe_hw *hw =
4326                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4327         uint8_t mirror_type = 0;
4328
4329         if (ixgbe_vmdq_mode_check(hw) < 0)
4330                 return -ENOTSUP;
4331
4332         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4333                 return -EINVAL;
4334
4335         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4336                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4337                         mirror_conf->rule_type);
4338                 return -EINVAL;
4339         }
4340
4341         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4342                 mirror_type |= IXGBE_MRCTL_VLME;
4343                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4344                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4345                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4346                                 /* search vlan id related pool vlan filter index */
4347                                 reg_index = ixgbe_find_vlvf_slot(hw,
4348                                                 mirror_conf->vlan.vlan_id[i]);
4349                                 if(reg_index < 0)
4350                                         return -EINVAL;
4351                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4352                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4353                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4354                                       mirror_conf->vlan.vlan_id[i]))
4355                                         vlan_mask |= (1ULL << reg_index);
4356                                 else
4357                                         return -EINVAL;
4358                         }
4359                 }
4360
4361                 if (on) {
4362                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4363                         mv_msb = vlan_mask >> vlan_mask_offset;
4364
4365                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4366                                                 mirror_conf->vlan.vlan_mask;
4367                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4368                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
4369                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4370                                                 mirror_conf->vlan.vlan_id[i];
4371                         }
4372                 } else {
4373                         mv_lsb = 0;
4374                         mv_msb = 0;
4375                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4376                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4377                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4378                 }
4379         }
4380
4381         /*
4382          * if enable pool mirror, write related pool mask register,if disable
4383          * pool mirror, clear PFMRVM register
4384          */
4385         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4386                 mirror_type |= IXGBE_MRCTL_VPME;
4387                 if (on) {
4388                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4389                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4390                         mr_info->mr_conf[rule_id].pool_mask =
4391                                         mirror_conf->pool_mask;
4392
4393                 } else {
4394                         mp_lsb = 0;
4395                         mp_msb = 0;
4396                         mr_info->mr_conf[rule_id].pool_mask = 0;
4397                 }
4398         }
4399         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4400                 mirror_type |= IXGBE_MRCTL_UPME;
4401         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4402                 mirror_type |= IXGBE_MRCTL_DPME;
4403
4404         /* read  mirror control register and recalculate it */
4405         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4406
4407         if (on) {
4408                 mr_ctl |= mirror_type;
4409                 mr_ctl &= mirror_rule_mask;
4410                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4411         } else
4412                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4413
4414         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4415         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4416
4417         /* write mirrror control  register */
4418         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4419
4420         /* write pool mirrror control  register */
4421         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4422                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4423                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4424                                 mp_msb);
4425         }
4426         /* write VLAN mirrror control  register */
4427         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4428                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4429                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4430                                 mv_msb);
4431         }
4432
4433         return 0;
4434 }
4435
4436 static int
4437 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4438 {
4439         int mr_ctl = 0;
4440         uint32_t lsb_val = 0;
4441         uint32_t msb_val = 0;
4442         const uint8_t rule_mr_offset = 4;
4443
4444         struct ixgbe_hw *hw =
4445                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4446         struct ixgbe_mirror_info *mr_info =
4447                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4448
4449         if (ixgbe_vmdq_mode_check(hw) < 0)
4450                 return (-ENOTSUP);
4451
4452         memset(&mr_info->mr_conf[rule_id], 0,
4453                 sizeof(struct rte_eth_mirror_conf));
4454
4455         /* clear PFVMCTL register */
4456         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4457
4458         /* clear pool mask register */
4459         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4460         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4461
4462         /* clear vlan mask register */
4463         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4464         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4465
4466         return 0;
4467 }
4468
4469 static int
4470 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4471 {
4472         uint32_t mask;
4473         struct ixgbe_hw *hw =
4474                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4475
4476         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4477         mask |= (1 << queue_id);
4478         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4479
4480         rte_intr_enable(&dev->pci_dev->intr_handle);
4481
4482         return 0;
4483 }
4484
4485 static int
4486 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4487 {
4488         uint32_t mask;
4489         struct ixgbe_hw *hw =
4490                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4491
4492         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4493         mask &= ~(1 << queue_id);
4494         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4495
4496         return 0;
4497 }
4498
4499 static int
4500 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4501 {
4502         uint32_t mask;
4503         struct ixgbe_hw *hw =
4504                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4505         struct ixgbe_interrupt *intr =
4506                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4507
4508         if (queue_id < 16) {
4509                 ixgbe_disable_intr(hw);
4510                 intr->mask |= (1 << queue_id);
4511                 ixgbe_enable_intr(dev);
4512         } else if (queue_id < 32) {
4513                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4514                 mask &= (1 << queue_id);
4515                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4516         } else if (queue_id < 64) {
4517                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4518                 mask &= (1 << (queue_id - 32));
4519                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4520         }
4521         rte_intr_enable(&dev->pci_dev->intr_handle);
4522
4523         return 0;
4524 }
4525
4526 static int
4527 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4528 {
4529         uint32_t mask;
4530         struct ixgbe_hw *hw =
4531                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4532         struct ixgbe_interrupt *intr =
4533                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4534
4535         if (queue_id < 16) {
4536                 ixgbe_disable_intr(hw);
4537                 intr->mask &= ~(1 << queue_id);
4538                 ixgbe_enable_intr(dev);
4539         } else if (queue_id < 32) {
4540                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4541                 mask &= ~(1 << queue_id);
4542                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4543         } else if (queue_id < 64) {
4544                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4545                 mask &= ~(1 << (queue_id - 32));
4546                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4547         }
4548
4549         return 0;
4550 }
4551
4552 static void
4553 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4554                      uint8_t queue, uint8_t msix_vector)
4555 {
4556         uint32_t tmp, idx;
4557
4558         if (direction == -1) {
4559                 /* other causes */
4560                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4561                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4562                 tmp &= ~0xFF;
4563                 tmp |= msix_vector;
4564                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4565         } else {
4566                 /* rx or tx cause */
4567                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4568                 idx = ((16 * (queue & 1)) + (8 * direction));
4569                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4570                 tmp &= ~(0xFF << idx);
4571                 tmp |= (msix_vector << idx);
4572                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4573         }
4574 }
4575
4576 /**
4577  * set the IVAR registers, mapping interrupt causes to vectors
4578  * @param hw
4579  *  pointer to ixgbe_hw struct
4580  * @direction
4581  *  0 for Rx, 1 for Tx, -1 for other causes
4582  * @queue
4583  *  queue to map the corresponding interrupt to
4584  * @msix_vector
4585  *  the vector to map to the corresponding queue
4586  */
4587 static void
4588 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4589                    uint8_t queue, uint8_t msix_vector)
4590 {
4591         uint32_t tmp, idx;
4592
4593         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4594         if (hw->mac.type == ixgbe_mac_82598EB) {
4595                 if (direction == -1)
4596                         direction = 0;
4597                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4598                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4599                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4600                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4601                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4602         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4603                         (hw->mac.type == ixgbe_mac_X540)) {
4604                 if (direction == -1) {
4605                         /* other causes */
4606                         idx = ((queue & 1) * 8);
4607                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4608                         tmp &= ~(0xFF << idx);
4609                         tmp |= (msix_vector << idx);
4610                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4611                 } else {
4612                         /* rx or tx causes */
4613                         idx = ((16 * (queue & 1)) + (8 * direction));
4614                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4615                         tmp &= ~(0xFF << idx);
4616                         tmp |= (msix_vector << idx);
4617                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4618                 }
4619         }
4620 }
4621
4622 static void
4623 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4624 {
4625         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4626         struct ixgbe_hw *hw =
4627                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4628         uint32_t q_idx;
4629         uint32_t vector_idx = 0;
4630
4631         /* won't configure msix register if no mapping is done
4632          * between intr vector and event fd.
4633          */
4634         if (!rte_intr_dp_is_en(intr_handle))
4635                 return;
4636
4637         /* Configure all RX queues of VF */
4638         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4639                 /* Force all queue use vector 0,
4640                  * as IXGBE_VF_MAXMSIVECOTR = 1
4641                  */
4642                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4643                 intr_handle->intr_vec[q_idx] = vector_idx;
4644         }
4645
4646         /* Configure VF Rx queue ivar */
4647         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4648 }
4649
4650 /**
4651  * Sets up the hardware to properly generate MSI-X interrupts
4652  * @hw
4653  *  board private structure
4654  */
4655 static void
4656 ixgbe_configure_msix(struct rte_eth_dev *dev)
4657 {
4658         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4659         struct ixgbe_hw *hw =
4660                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4661         uint32_t queue_id, vec = 0;
4662         uint32_t mask;
4663         uint32_t gpie;
4664
4665         /* won't configure msix register if no mapping is done
4666          * between intr vector and event fd
4667          */
4668         if (!rte_intr_dp_is_en(intr_handle))
4669                 return;
4670
4671         /* setup GPIE for MSI-x mode */
4672         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4673         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4674                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4675         /* auto clearing and auto setting corresponding bits in EIMS
4676          * when MSI-X interrupt is triggered
4677          */
4678         if (hw->mac.type == ixgbe_mac_82598EB) {
4679                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4680         } else {
4681                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4682                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4683         }
4684         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4685
4686         /* Populate the IVAR table and set the ITR values to the
4687          * corresponding register.
4688          */
4689         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4690              queue_id++) {
4691                 /* by default, 1:1 mapping */
4692                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4693                 intr_handle->intr_vec[queue_id] = vec;
4694                 if (vec < intr_handle->nb_efd - 1)
4695                         vec++;
4696         }
4697
4698         switch (hw->mac.type) {
4699         case ixgbe_mac_82598EB:
4700                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4701                                    intr_handle->max_intr - 1);
4702                 break;
4703         case ixgbe_mac_82599EB:
4704         case ixgbe_mac_X540:
4705                 ixgbe_set_ivar_map(hw, -1, 1, intr_handle->max_intr - 1);
4706                 break;
4707         default:
4708                 break;
4709         }
4710         IXGBE_WRITE_REG(hw, IXGBE_EITR(queue_id),
4711                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4712
4713         /* set up to autoclear timer, and the vectors */
4714         mask = IXGBE_EIMS_ENABLE_MASK;
4715         mask &= ~(IXGBE_EIMS_OTHER |
4716                   IXGBE_EIMS_MAILBOX |
4717                   IXGBE_EIMS_LSC);
4718
4719         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4720 }
4721
4722 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4723         uint16_t queue_idx, uint16_t tx_rate)
4724 {
4725         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4726         uint32_t rf_dec, rf_int;
4727         uint32_t bcnrc_val;
4728         uint16_t link_speed = dev->data->dev_link.link_speed;
4729
4730         if (queue_idx >= hw->mac.max_tx_queues)
4731                 return -EINVAL;
4732
4733         if (tx_rate != 0) {
4734                 /* Calculate the rate factor values to set */
4735                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4736                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4737                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4738
4739                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4740                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4741                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4742                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4743         } else {
4744                 bcnrc_val = 0;
4745         }
4746
4747         /*
4748          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4749          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4750          * set as 0x4.
4751          */
4752         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4753                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4754                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4755                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4756                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4757         else
4758                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4759                         IXGBE_MMW_SIZE_DEFAULT);
4760
4761         /* Set RTTBCNRC of queue X */
4762         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4763         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4764         IXGBE_WRITE_FLUSH(hw);
4765
4766         return 0;
4767 }
4768
4769 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4770         uint16_t tx_rate, uint64_t q_msk)
4771 {
4772         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4773         struct ixgbe_vf_info *vfinfo =
4774                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4775         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4776         uint32_t queue_stride =
4777                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4778         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4779         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4780         uint16_t total_rate = 0;
4781
4782         if (queue_end >= hw->mac.max_tx_queues)
4783                 return -EINVAL;
4784
4785         if (vfinfo != NULL) {
4786                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4787                         if (vf_idx == vf)
4788                                 continue;
4789                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4790                                 idx++)
4791                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4792                 }
4793         } else
4794                 return -EINVAL;
4795
4796         /* Store tx_rate for this vf. */
4797         for (idx = 0; idx < nb_q_per_pool; idx++) {
4798                 if (((uint64_t)0x1 << idx) & q_msk) {
4799                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4800                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4801                         total_rate += tx_rate;
4802                 }
4803         }
4804
4805         if (total_rate > dev->data->dev_link.link_speed) {
4806                 /*
4807                  * Reset stored TX rate of the VF if it causes exceed
4808                  * link speed.
4809                  */
4810                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4811                 return -EINVAL;
4812         }
4813
4814         /* Set RTTBCNRC of each queue/pool for vf X  */
4815         for (; queue_idx <= queue_end; queue_idx++) {
4816                 if (0x1 & q_msk)
4817                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4818                 q_msk = q_msk >> 1;
4819         }
4820
4821         return 0;
4822 }
4823
4824 static void
4825 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4826                      __attribute__((unused)) uint32_t index,
4827                      __attribute__((unused)) uint32_t pool)
4828 {
4829         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4830         int diag;
4831
4832         /*
4833          * On a 82599 VF, adding again the same MAC addr is not an idempotent
4834          * operation. Trap this case to avoid exhausting the [very limited]
4835          * set of PF resources used to store VF MAC addresses.
4836          */
4837         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4838                 return;
4839         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4840         if (diag == 0)
4841                 return;
4842         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4843 }
4844
4845 static void
4846 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4847 {
4848         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4849         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4850         struct ether_addr *mac_addr;
4851         uint32_t i;
4852         int diag;
4853
4854         /*
4855          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4856          * not support the deletion of a given MAC address.
4857          * Instead, it imposes to delete all MAC addresses, then to add again
4858          * all MAC addresses with the exception of the one to be deleted.
4859          */
4860         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4861
4862         /*
4863          * Add again all MAC addresses, with the exception of the deleted one
4864          * and of the permanent MAC address.
4865          */
4866         for (i = 0, mac_addr = dev->data->mac_addrs;
4867              i < hw->mac.num_rar_entries; i++, mac_addr++) {
4868                 /* Skip the deleted MAC address */
4869                 if (i == index)
4870                         continue;
4871                 /* Skip NULL MAC addresses */
4872                 if (is_zero_ether_addr(mac_addr))
4873                         continue;
4874                 /* Skip the permanent MAC address */
4875                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4876                         continue;
4877                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4878                 if (diag != 0)
4879                         PMD_DRV_LOG(ERR,
4880                                     "Adding again MAC address "
4881                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
4882                                     "diag=%d",
4883                                     mac_addr->addr_bytes[0],
4884                                     mac_addr->addr_bytes[1],
4885                                     mac_addr->addr_bytes[2],
4886                                     mac_addr->addr_bytes[3],
4887                                     mac_addr->addr_bytes[4],
4888                                     mac_addr->addr_bytes[5],
4889                                     diag);
4890         }
4891 }
4892
4893 static void
4894 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4895 {
4896         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4897
4898         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4899 }
4900
4901 #define MAC_TYPE_FILTER_SUP(type)    do {\
4902         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4903                 (type) != ixgbe_mac_X550)\
4904                 return -ENOTSUP;\
4905 } while (0)
4906
4907 static int
4908 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4909                         struct rte_eth_syn_filter *filter,
4910                         bool add)
4911 {
4912         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4913         uint32_t synqf;
4914
4915         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4916                 return -EINVAL;
4917
4918         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4919
4920         if (add) {
4921                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4922                         return -EINVAL;
4923                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4924                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4925
4926                 if (filter->hig_pri)
4927                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
4928                 else
4929                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4930         } else {
4931                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4932                         return -ENOENT;
4933                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4934         }
4935         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4936         IXGBE_WRITE_FLUSH(hw);
4937         return 0;
4938 }
4939
4940 static int
4941 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4942                         struct rte_eth_syn_filter *filter)
4943 {
4944         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4945         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4946
4947         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4948                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4949                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4950                 return 0;
4951         }
4952         return -ENOENT;
4953 }
4954
4955 static int
4956 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4957                         enum rte_filter_op filter_op,
4958                         void *arg)
4959 {
4960         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4961         int ret;
4962
4963         MAC_TYPE_FILTER_SUP(hw->mac.type);
4964
4965         if (filter_op == RTE_ETH_FILTER_NOP)
4966                 return 0;
4967
4968         if (arg == NULL) {
4969                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4970                             filter_op);
4971                 return -EINVAL;
4972         }
4973
4974         switch (filter_op) {
4975         case RTE_ETH_FILTER_ADD:
4976                 ret = ixgbe_syn_filter_set(dev,
4977                                 (struct rte_eth_syn_filter *)arg,
4978                                 TRUE);
4979                 break;
4980         case RTE_ETH_FILTER_DELETE:
4981                 ret = ixgbe_syn_filter_set(dev,
4982                                 (struct rte_eth_syn_filter *)arg,
4983                                 FALSE);
4984                 break;
4985         case RTE_ETH_FILTER_GET:
4986                 ret = ixgbe_syn_filter_get(dev,
4987                                 (struct rte_eth_syn_filter *)arg);
4988                 break;
4989         default:
4990                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
4991                 ret = -EINVAL;
4992                 break;
4993         }
4994
4995         return ret;
4996 }
4997
4998
4999 static inline enum ixgbe_5tuple_protocol
5000 convert_protocol_type(uint8_t protocol_value)
5001 {
5002         if (protocol_value == IPPROTO_TCP)
5003                 return IXGBE_FILTER_PROTOCOL_TCP;
5004         else if (protocol_value == IPPROTO_UDP)
5005                 return IXGBE_FILTER_PROTOCOL_UDP;
5006         else if (protocol_value == IPPROTO_SCTP)
5007                 return IXGBE_FILTER_PROTOCOL_SCTP;
5008         else
5009                 return IXGBE_FILTER_PROTOCOL_NONE;
5010 }
5011
5012 /*
5013  * add a 5tuple filter
5014  *
5015  * @param
5016  * dev: Pointer to struct rte_eth_dev.
5017  * index: the index the filter allocates.
5018  * filter: ponter to the filter that will be added.
5019  * rx_queue: the queue id the filter assigned to.
5020  *
5021  * @return
5022  *    - On success, zero.
5023  *    - On failure, a negative value.
5024  */
5025 static int
5026 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5027                         struct ixgbe_5tuple_filter *filter)
5028 {
5029         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5030         struct ixgbe_filter_info *filter_info =
5031                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5032         int i, idx, shift;
5033         uint32_t ftqf, sdpqf;
5034         uint32_t l34timir = 0;
5035         uint8_t mask = 0xff;
5036
5037         /*
5038          * look for an unused 5tuple filter index,
5039          * and insert the filter to list.
5040          */
5041         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5042                 idx = i / (sizeof(uint32_t) * NBBY);
5043                 shift = i % (sizeof(uint32_t) * NBBY);
5044                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5045                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5046                         filter->index = i;
5047                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5048                                           filter,
5049                                           entries);
5050                         break;
5051                 }
5052         }
5053         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5054                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5055                 return -ENOSYS;
5056         }
5057
5058         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5059                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5060         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5061
5062         ftqf = (uint32_t)(filter->filter_info.proto &
5063                 IXGBE_FTQF_PROTOCOL_MASK);
5064         ftqf |= (uint32_t)((filter->filter_info.priority &
5065                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5066         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5067                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5068         if (filter->filter_info.dst_ip_mask == 0)
5069                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5070         if (filter->filter_info.src_port_mask == 0)
5071                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5072         if (filter->filter_info.dst_port_mask == 0)
5073                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5074         if (filter->filter_info.proto_mask == 0)
5075                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5076         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5077         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5078         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5079
5080         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5081         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5082         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5083         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5084
5085         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5086         l34timir |= (uint32_t)(filter->queue <<
5087                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5088         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5089         return 0;
5090 }
5091
5092 /*
5093  * remove a 5tuple filter
5094  *
5095  * @param
5096  * dev: Pointer to struct rte_eth_dev.
5097  * filter: the pointer of the filter will be removed.
5098  */
5099 static void
5100 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5101                         struct ixgbe_5tuple_filter *filter)
5102 {
5103         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5104         struct ixgbe_filter_info *filter_info =
5105                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5106         uint16_t index = filter->index;
5107
5108         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5109                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5110         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5111         rte_free(filter);
5112
5113         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5114         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5115         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5116         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5117         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5118 }
5119
5120 static int
5121 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5122 {
5123         struct ixgbe_hw *hw;
5124         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5125
5126         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5127
5128         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5129                 return -EINVAL;
5130
5131         /* refuse mtu that requires the support of scattered packets when this
5132          * feature has not been enabled before. */
5133         if (!dev->data->scattered_rx &&
5134             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5135              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5136                 return -EINVAL;
5137
5138         /*
5139          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5140          * request of the version 2.0 of the mailbox API.
5141          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5142          * of the mailbox API.
5143          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5144          * prior to 3.11.33 which contains the following change:
5145          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5146          */
5147         ixgbevf_rlpml_set_vf(hw, max_frame);
5148
5149         /* update max frame size */
5150         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5151         return 0;
5152 }
5153
5154 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5155         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5156                 return -ENOTSUP;\
5157 } while (0)
5158
5159 static inline struct ixgbe_5tuple_filter *
5160 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5161                         struct ixgbe_5tuple_filter_info *key)
5162 {
5163         struct ixgbe_5tuple_filter *it;
5164
5165         TAILQ_FOREACH(it, filter_list, entries) {
5166                 if (memcmp(key, &it->filter_info,
5167                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5168                         return it;
5169                 }
5170         }
5171         return NULL;
5172 }
5173
5174 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5175 static inline int
5176 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5177                         struct ixgbe_5tuple_filter_info *filter_info)
5178 {
5179         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5180                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5181                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5182                 return -EINVAL;
5183
5184         switch (filter->dst_ip_mask) {
5185         case UINT32_MAX:
5186                 filter_info->dst_ip_mask = 0;
5187                 filter_info->dst_ip = filter->dst_ip;
5188                 break;
5189         case 0:
5190                 filter_info->dst_ip_mask = 1;
5191                 break;
5192         default:
5193                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5194                 return -EINVAL;
5195         }
5196
5197         switch (filter->src_ip_mask) {
5198         case UINT32_MAX:
5199                 filter_info->src_ip_mask = 0;
5200                 filter_info->src_ip = filter->src_ip;
5201                 break;
5202         case 0:
5203                 filter_info->src_ip_mask = 1;
5204                 break;
5205         default:
5206                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5207                 return -EINVAL;
5208         }
5209
5210         switch (filter->dst_port_mask) {
5211         case UINT16_MAX:
5212                 filter_info->dst_port_mask = 0;
5213                 filter_info->dst_port = filter->dst_port;
5214                 break;
5215         case 0:
5216                 filter_info->dst_port_mask = 1;
5217                 break;
5218         default:
5219                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5220                 return -EINVAL;
5221         }
5222
5223         switch (filter->src_port_mask) {
5224         case UINT16_MAX:
5225                 filter_info->src_port_mask = 0;
5226                 filter_info->src_port = filter->src_port;
5227                 break;
5228         case 0:
5229                 filter_info->src_port_mask = 1;
5230                 break;
5231         default:
5232                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5233                 return -EINVAL;
5234         }
5235
5236         switch (filter->proto_mask) {
5237         case UINT8_MAX:
5238                 filter_info->proto_mask = 0;
5239                 filter_info->proto =
5240                         convert_protocol_type(filter->proto);
5241                 break;
5242         case 0:
5243                 filter_info->proto_mask = 1;
5244                 break;
5245         default:
5246                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5247                 return -EINVAL;
5248         }
5249
5250         filter_info->priority = (uint8_t)filter->priority;
5251         return 0;
5252 }
5253
5254 /*
5255  * add or delete a ntuple filter
5256  *
5257  * @param
5258  * dev: Pointer to struct rte_eth_dev.
5259  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5260  * add: if true, add filter, if false, remove filter
5261  *
5262  * @return
5263  *    - On success, zero.
5264  *    - On failure, a negative value.
5265  */
5266 static int
5267 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5268                         struct rte_eth_ntuple_filter *ntuple_filter,
5269                         bool add)
5270 {
5271         struct ixgbe_filter_info *filter_info =
5272                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5273         struct ixgbe_5tuple_filter_info filter_5tuple;
5274         struct ixgbe_5tuple_filter *filter;
5275         int ret;
5276
5277         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5278                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5279                 return -EINVAL;
5280         }
5281
5282         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5283         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5284         if (ret < 0)
5285                 return ret;
5286
5287         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5288                                          &filter_5tuple);
5289         if (filter != NULL && add) {
5290                 PMD_DRV_LOG(ERR, "filter exists.");
5291                 return -EEXIST;
5292         }
5293         if (filter == NULL && !add) {
5294                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5295                 return -ENOENT;
5296         }
5297
5298         if (add) {
5299                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5300                                 sizeof(struct ixgbe_5tuple_filter), 0);
5301                 if (filter == NULL)
5302                         return -ENOMEM;
5303                 (void)rte_memcpy(&filter->filter_info,
5304                                  &filter_5tuple,
5305                                  sizeof(struct ixgbe_5tuple_filter_info));
5306                 filter->queue = ntuple_filter->queue;
5307                 ret = ixgbe_add_5tuple_filter(dev, filter);
5308                 if (ret < 0) {
5309                         rte_free(filter);
5310                         return ret;
5311                 }
5312         } else
5313                 ixgbe_remove_5tuple_filter(dev, filter);
5314
5315         return 0;
5316 }
5317
5318 /*
5319  * get a ntuple filter
5320  *
5321  * @param
5322  * dev: Pointer to struct rte_eth_dev.
5323  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5324  *
5325  * @return
5326  *    - On success, zero.
5327  *    - On failure, a negative value.
5328  */
5329 static int
5330 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5331                         struct rte_eth_ntuple_filter *ntuple_filter)
5332 {
5333         struct ixgbe_filter_info *filter_info =
5334                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5335         struct ixgbe_5tuple_filter_info filter_5tuple;
5336         struct ixgbe_5tuple_filter *filter;
5337         int ret;
5338
5339         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5340                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5341                 return -EINVAL;
5342         }
5343
5344         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5345         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5346         if (ret < 0)
5347                 return ret;
5348
5349         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5350                                          &filter_5tuple);
5351         if (filter == NULL) {
5352                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5353                 return -ENOENT;
5354         }
5355         ntuple_filter->queue = filter->queue;
5356         return 0;
5357 }
5358
5359 /*
5360  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5361  * @dev: pointer to rte_eth_dev structure
5362  * @filter_op:operation will be taken.
5363  * @arg: a pointer to specific structure corresponding to the filter_op
5364  *
5365  * @return
5366  *    - On success, zero.
5367  *    - On failure, a negative value.
5368  */
5369 static int
5370 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5371                                 enum rte_filter_op filter_op,
5372                                 void *arg)
5373 {
5374         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5375         int ret;
5376
5377         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5378
5379         if (filter_op == RTE_ETH_FILTER_NOP)
5380                 return 0;
5381
5382         if (arg == NULL) {
5383                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5384                             filter_op);
5385                 return -EINVAL;
5386         }
5387
5388         switch (filter_op) {
5389         case RTE_ETH_FILTER_ADD:
5390                 ret = ixgbe_add_del_ntuple_filter(dev,
5391                         (struct rte_eth_ntuple_filter *)arg,
5392                         TRUE);
5393                 break;
5394         case RTE_ETH_FILTER_DELETE:
5395                 ret = ixgbe_add_del_ntuple_filter(dev,
5396                         (struct rte_eth_ntuple_filter *)arg,
5397                         FALSE);
5398                 break;
5399         case RTE_ETH_FILTER_GET:
5400                 ret = ixgbe_get_ntuple_filter(dev,
5401                         (struct rte_eth_ntuple_filter *)arg);
5402                 break;
5403         default:
5404                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5405                 ret = -EINVAL;
5406                 break;
5407         }
5408         return ret;
5409 }
5410
5411 static inline int
5412 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5413                         uint16_t ethertype)
5414 {
5415         int i;
5416
5417         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5418                 if (filter_info->ethertype_filters[i] == ethertype &&
5419                     (filter_info->ethertype_mask & (1 << i)))
5420                         return i;
5421         }
5422         return -1;
5423 }
5424
5425 static inline int
5426 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5427                         uint16_t ethertype)
5428 {
5429         int i;
5430
5431         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5432                 if (!(filter_info->ethertype_mask & (1 << i))) {
5433                         filter_info->ethertype_mask |= 1 << i;
5434                         filter_info->ethertype_filters[i] = ethertype;
5435                         return i;
5436                 }
5437         }
5438         return -1;
5439 }
5440
5441 static inline int
5442 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5443                         uint8_t idx)
5444 {
5445         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5446                 return -1;
5447         filter_info->ethertype_mask &= ~(1 << idx);
5448         filter_info->ethertype_filters[idx] = 0;
5449         return idx;
5450 }
5451
5452 static int
5453 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5454                         struct rte_eth_ethertype_filter *filter,
5455                         bool add)
5456 {
5457         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5458         struct ixgbe_filter_info *filter_info =
5459                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5460         uint32_t etqf = 0;
5461         uint32_t etqs = 0;
5462         int ret;
5463
5464         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5465                 return -EINVAL;
5466
5467         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5468                 filter->ether_type == ETHER_TYPE_IPv6) {
5469                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5470                         " ethertype filter.", filter->ether_type);
5471                 return -EINVAL;
5472         }
5473
5474         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5475                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5476                 return -EINVAL;
5477         }
5478         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5479                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5480                 return -EINVAL;
5481         }
5482
5483         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5484         if (ret >= 0 && add) {
5485                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5486                             filter->ether_type);
5487                 return -EEXIST;
5488         }
5489         if (ret < 0 && !add) {
5490                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5491                             filter->ether_type);
5492                 return -ENOENT;
5493         }
5494
5495         if (add) {
5496                 ret = ixgbe_ethertype_filter_insert(filter_info,
5497                         filter->ether_type);
5498                 if (ret < 0) {
5499                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5500                         return -ENOSYS;
5501                 }
5502                 etqf = IXGBE_ETQF_FILTER_EN;
5503                 etqf |= (uint32_t)filter->ether_type;
5504                 etqs |= (uint32_t)((filter->queue <<
5505                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5506                                     IXGBE_ETQS_RX_QUEUE);
5507                 etqs |= IXGBE_ETQS_QUEUE_EN;
5508         } else {
5509                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5510                 if (ret < 0)
5511                         return -ENOSYS;
5512         }
5513         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5514         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5515         IXGBE_WRITE_FLUSH(hw);
5516
5517         return 0;
5518 }
5519
5520 static int
5521 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5522                         struct rte_eth_ethertype_filter *filter)
5523 {
5524         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5525         struct ixgbe_filter_info *filter_info =
5526                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5527         uint32_t etqf, etqs;
5528         int ret;
5529
5530         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5531         if (ret < 0) {
5532                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5533                             filter->ether_type);
5534                 return -ENOENT;
5535         }
5536
5537         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5538         if (etqf & IXGBE_ETQF_FILTER_EN) {
5539                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5540                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5541                 filter->flags = 0;
5542                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5543                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5544                 return 0;
5545         }
5546         return -ENOENT;
5547 }
5548
5549 /*
5550  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5551  * @dev: pointer to rte_eth_dev structure
5552  * @filter_op:operation will be taken.
5553  * @arg: a pointer to specific structure corresponding to the filter_op
5554  */
5555 static int
5556 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5557                                 enum rte_filter_op filter_op,
5558                                 void *arg)
5559 {
5560         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5561         int ret;
5562
5563         MAC_TYPE_FILTER_SUP(hw->mac.type);
5564
5565         if (filter_op == RTE_ETH_FILTER_NOP)
5566                 return 0;
5567
5568         if (arg == NULL) {
5569                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5570                             filter_op);
5571                 return -EINVAL;
5572         }
5573
5574         switch (filter_op) {
5575         case RTE_ETH_FILTER_ADD:
5576                 ret = ixgbe_add_del_ethertype_filter(dev,
5577                         (struct rte_eth_ethertype_filter *)arg,
5578                         TRUE);
5579                 break;
5580         case RTE_ETH_FILTER_DELETE:
5581                 ret = ixgbe_add_del_ethertype_filter(dev,
5582                         (struct rte_eth_ethertype_filter *)arg,
5583                         FALSE);
5584                 break;
5585         case RTE_ETH_FILTER_GET:
5586                 ret = ixgbe_get_ethertype_filter(dev,
5587                         (struct rte_eth_ethertype_filter *)arg);
5588                 break;
5589         default:
5590                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5591                 ret = -EINVAL;
5592                 break;
5593         }
5594         return ret;
5595 }
5596
5597 static int
5598 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5599                      enum rte_filter_type filter_type,
5600                      enum rte_filter_op filter_op,
5601                      void *arg)
5602 {
5603         int ret = -EINVAL;
5604
5605         switch (filter_type) {
5606         case RTE_ETH_FILTER_NTUPLE:
5607                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5608                 break;
5609         case RTE_ETH_FILTER_ETHERTYPE:
5610                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5611                 break;
5612         case RTE_ETH_FILTER_SYN:
5613                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5614                 break;
5615         case RTE_ETH_FILTER_FDIR:
5616                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5617                 break;
5618         default:
5619                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5620                                                         filter_type);
5621                 break;
5622         }
5623
5624         return ret;
5625 }
5626
5627 static u8 *
5628 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5629                         u8 **mc_addr_ptr, u32 *vmdq)
5630 {
5631         u8 *mc_addr;
5632
5633         *vmdq = 0;
5634         mc_addr = *mc_addr_ptr;
5635         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5636         return mc_addr;
5637 }
5638
5639 static int
5640 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5641                           struct ether_addr *mc_addr_set,
5642                           uint32_t nb_mc_addr)
5643 {
5644         struct ixgbe_hw *hw;
5645         u8 *mc_addr_list;
5646
5647         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5648         mc_addr_list = (u8 *)mc_addr_set;
5649         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5650                                          ixgbe_dev_addr_list_itr, TRUE);
5651 }
5652
5653 static int
5654 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5655 {
5656         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5657         uint32_t tsync_ctl;
5658         uint32_t tsauxc;
5659
5660         /* Enable system time for platforms where it isn't on by default. */
5661         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5662         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5663         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5664
5665         /* Start incrementing the register used to timestamp PTP packets. */
5666         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
5667
5668         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5669         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5670                         (ETHER_TYPE_1588 |
5671                          IXGBE_ETQF_FILTER_EN |
5672                          IXGBE_ETQF_1588));
5673
5674         /* Enable timestamping of received PTP packets. */
5675         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5676         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5677         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5678
5679         /* Enable timestamping of transmitted PTP packets. */
5680         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5681         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5682         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5683
5684         return 0;
5685 }
5686
5687 static int
5688 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5689 {
5690         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5691         uint32_t tsync_ctl;
5692
5693         /* Disable timestamping of transmitted PTP packets. */
5694         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5695         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5696         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5697
5698         /* Disable timestamping of received PTP packets. */
5699         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5700         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5701         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5702
5703         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5704         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5705
5706         /* Stop incrementating the System Time registers. */
5707         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5708
5709         return 0;
5710 }
5711
5712 static int
5713 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5714                                  struct timespec *timestamp,
5715                                  uint32_t flags __rte_unused)
5716 {
5717         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5718         uint32_t tsync_rxctl;
5719         uint32_t rx_stmpl;
5720         uint32_t rx_stmph;
5721
5722         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5723         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5724                 return -EINVAL;
5725
5726         rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5727         rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
5728
5729         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
5730         timestamp->tv_nsec = 0;
5731
5732         return  0;
5733 }
5734
5735 static int
5736 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5737                                  struct timespec *timestamp)
5738 {
5739         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5740         uint32_t tsync_txctl;
5741         uint32_t tx_stmpl;
5742         uint32_t tx_stmph;
5743
5744         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5745         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5746                 return -EINVAL;
5747
5748         tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5749         tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
5750
5751         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
5752         timestamp->tv_nsec = 0;
5753
5754         return  0;
5755 }
5756
5757 static int
5758 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5759 {
5760         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5761         int count = 0;
5762         int g_ind = 0;
5763         const struct reg_info *reg_group;
5764         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5765                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5766
5767         while ((reg_group = reg_set[g_ind++]))
5768                 count += ixgbe_regs_group_count(reg_group);
5769
5770         return count;
5771 }
5772
5773 static int
5774 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5775 {
5776         int count = 0;
5777         int g_ind = 0;
5778         const struct reg_info *reg_group;
5779
5780         while ((reg_group = ixgbevf_regs[g_ind++]))
5781                 count += ixgbe_regs_group_count(reg_group);
5782
5783         return count;
5784 }
5785
5786 static int
5787 ixgbe_get_regs(struct rte_eth_dev *dev,
5788               struct rte_dev_reg_info *regs)
5789 {
5790         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5791         uint32_t *data = regs->data;
5792         int g_ind = 0;
5793         int count = 0;
5794         const struct reg_info *reg_group;
5795         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5796                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5797
5798         /* Support only full register dump */
5799         if ((regs->length == 0) ||
5800             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
5801                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5802                         hw->device_id;
5803                 while ((reg_group = reg_set[g_ind++]))
5804                         count += ixgbe_read_regs_group(dev, &data[count],
5805                                 reg_group);
5806                 return 0;
5807         }
5808
5809         return -ENOTSUP;
5810 }
5811
5812 static int
5813 ixgbevf_get_regs(struct rte_eth_dev *dev,
5814                 struct rte_dev_reg_info *regs)
5815 {
5816         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5817         uint32_t *data = regs->data;
5818         int g_ind = 0;
5819         int count = 0;
5820         const struct reg_info *reg_group;
5821
5822         /* Support only full register dump */
5823         if ((regs->length == 0) ||
5824             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
5825                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5826                         hw->device_id;
5827                 while ((reg_group = ixgbevf_regs[g_ind++]))
5828                         count += ixgbe_read_regs_group(dev, &data[count],
5829                                                       reg_group);
5830                 return 0;
5831         }
5832
5833         return -ENOTSUP;
5834 }
5835
5836 static int
5837 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
5838 {
5839         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5840
5841         /* Return unit is byte count */
5842         return hw->eeprom.word_size * 2;
5843 }
5844
5845 static int
5846 ixgbe_get_eeprom(struct rte_eth_dev *dev,
5847                 struct rte_dev_eeprom_info *in_eeprom)
5848 {
5849         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5850         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5851         uint16_t *data = in_eeprom->data;
5852         int first, length;
5853
5854         first = in_eeprom->offset >> 1;
5855         length = in_eeprom->length >> 1;
5856         if ((first > hw->eeprom.word_size) ||
5857             ((first + length) > hw->eeprom.word_size))
5858                 return -EINVAL;
5859
5860         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5861
5862         return eeprom->ops.read_buffer(hw, first, length, data);
5863 }
5864
5865 static int
5866 ixgbe_set_eeprom(struct rte_eth_dev *dev,
5867                 struct rte_dev_eeprom_info *in_eeprom)
5868 {
5869         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5870         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5871         uint16_t *data = in_eeprom->data;
5872         int first, length;
5873
5874         first = in_eeprom->offset >> 1;
5875         length = in_eeprom->length >> 1;
5876         if ((first > hw->eeprom.word_size) ||
5877             ((first + length) > hw->eeprom.word_size))
5878                 return -EINVAL;
5879
5880         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5881
5882         return eeprom->ops.write_buffer(hw,  first, length, data);
5883 }
5884
5885 uint16_t
5886 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
5887         switch (mac_type) {
5888         case ixgbe_mac_X550:
5889         case ixgbe_mac_X550EM_x:
5890                 return ETH_RSS_RETA_SIZE_512;
5891         case ixgbe_mac_X550_vf:
5892         case ixgbe_mac_X550EM_x_vf:
5893                 return ETH_RSS_RETA_SIZE_64;
5894         default:
5895                 return ETH_RSS_RETA_SIZE_128;
5896         }
5897 }
5898
5899 uint32_t
5900 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
5901         switch (mac_type) {
5902         case ixgbe_mac_X550:
5903         case ixgbe_mac_X550EM_x:
5904                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
5905                         return IXGBE_RETA(reta_idx >> 2);
5906                 else
5907                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
5908         case ixgbe_mac_X550_vf:
5909         case ixgbe_mac_X550EM_x_vf:
5910                 return IXGBE_VFRETA(reta_idx >> 2);
5911         default:
5912                 return IXGBE_RETA(reta_idx >> 2);
5913         }
5914 }
5915
5916 uint32_t
5917 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
5918         switch (mac_type) {
5919         case ixgbe_mac_X550_vf:
5920         case ixgbe_mac_X550EM_x_vf:
5921                 return IXGBE_VFMRQC;
5922         default:
5923                 return IXGBE_MRQC;
5924         }
5925 }
5926
5927 uint32_t
5928 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
5929         switch (mac_type) {
5930         case ixgbe_mac_X550_vf:
5931         case ixgbe_mac_X550EM_x_vf:
5932                 return IXGBE_VFRSSRK(i);
5933         default:
5934                 return IXGBE_RSSRK(i);
5935         }
5936 }
5937
5938 bool
5939 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
5940         switch (mac_type) {
5941         case ixgbe_mac_82599_vf:
5942         case ixgbe_mac_X540_vf:
5943                 return 0;
5944         default:
5945                 return 1;
5946         }
5947 }
5948
5949 static int
5950 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
5951                         struct rte_eth_dcb_info *dcb_info)
5952 {
5953         struct ixgbe_dcb_config *dcb_config =
5954                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
5955         struct ixgbe_dcb_tc_config *tc;
5956         uint8_t i, j;
5957
5958         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
5959                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
5960         else
5961                 dcb_info->nb_tcs = 1;
5962
5963         if (dcb_config->vt_mode) { /* vt is enabled*/
5964                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
5965                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
5966                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
5967                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
5968                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
5969                         for (j = 0; j < dcb_info->nb_tcs; j++) {
5970                                 dcb_info->tc_queue.tc_rxq[i][j].base =
5971                                                 i * dcb_info->nb_tcs + j;
5972                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
5973                                 dcb_info->tc_queue.tc_txq[i][j].base =
5974                                                 i * dcb_info->nb_tcs + j;
5975                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
5976                         }
5977                 }
5978         } else { /* vt is disabled*/
5979                 struct rte_eth_dcb_rx_conf *rx_conf =
5980                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
5981                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
5982                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
5983                 if (dcb_info->nb_tcs == ETH_4_TCS) {
5984                         for (i = 0; i < dcb_info->nb_tcs; i++) {
5985                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
5986                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
5987                         }
5988                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
5989                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
5990                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
5991                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
5992                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
5993                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
5994                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
5995                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
5996                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
5997                         for (i = 0; i < dcb_info->nb_tcs; i++) {
5998                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
5999                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6000                         }
6001                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6002                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6003                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6004                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6005                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6006                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6007                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6008                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6009                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6010                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6011                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6012                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6013                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6014                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6015                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6016                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6017                 }
6018         }
6019         for (i = 0; i < dcb_info->nb_tcs; i++) {
6020                 tc = &dcb_config->tc_config[i];
6021                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6022         }
6023         return 0;
6024 }
6025
6026 static struct rte_driver rte_ixgbe_driver = {
6027         .type = PMD_PDEV,
6028         .init = rte_ixgbe_pmd_init,
6029 };
6030
6031 static struct rte_driver rte_ixgbevf_driver = {
6032         .type = PMD_PDEV,
6033         .init = rte_ixgbevf_pmd_init,
6034 };
6035
6036 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
6037 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);